electronics/ttl-fpga
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This commit is contained in:
Markus Koch 2019-06-11 21:50:54 +02:00
parent 1c6ae29a8f
commit 339fb214d7
4 changed files with 3961 additions and 3692 deletions
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22
kicad_pcb/logic_block.sch
View File

@ -1566,7 +1566,7 @@ Wire Notes Line
Wire Notes Line
5850 4900 5900 4850
Text Label 3250 10550 0 50 ~ 0
cfgX
cfg28
Wire Wire Line
3600 10550 3100 10550
Wire Bus Line
@ -1589,7 +1589,7 @@ lut_out_b
Text Label 8000 6100 0 50 ~ 0
lut_out_b_async
Text Label 7100 8200 0 50 ~ 0
cfgX
cfg29
Wire Wire Line
7100 8100 7250 8100
Connection ~ 7100 8100
@ -2278,7 +2278,7 @@ $EndComp
Wire Wire Line
3100 8600 3600 8600
Text Label 3250 8600 0 50 ~ 0
cfgX
cfg28
Wire Bus Line
5900 4950 6350 4950
Wire Bus Line
@ -2525,6 +2525,14 @@ Wire Wire Line
6050 1800 6250 1800
Wire Wire Line
3800 5400 5800 5400
Entry Wire Line
5800 5400 5900 5300
Text Label 5450 5400 0 50 ~ 0
cfg31
Wire Notes Line
5300 5500 4850 5500
Text Notes 4900 5600 0 50 ~ 0
cfg[28..16]
Wire Bus Line
13100 7850 13700 7850
Wire Bus Line
@ -2549,12 +2557,4 @@ Wire Bus Line
7750 1800 7750 4350
Wire Bus Line
5900 1800 5900 4350
Entry Wire Line
5800 5400 5900 5300
Text Label 5450 5400 0 50 ~ 0
cfg31
Wire Notes Line
5300 5500 4850 5500
Text Notes 4900 5600 0 50 ~ 0
cfg[28..16]
$EndSCHEMATC

7618
kicad_pcb/ttl-fpga.kicad_pcb
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File diff suppressed because it is too large Load Diff

5
kicad_pcb/ttl-fpga.pro
View File

@ -1,4 +1,4 @@
update=Sat 01 Jun 2019 09:25:42 PM CEST
update=Tue 11 Jun 2019 09:23:50 PM CEST
version=1
last_client=kicad
[general]
@ -29,8 +29,11 @@ MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.3
ViaDiameter1=0.6
ViaDrill1=0.3
ViaDiameter2=0.8
ViaDrill2=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25

8
kicad_pcb/ttl-fpga.sch
View File

@ -594,6 +594,10 @@ F 3 "" H 4150 5400 50 0001 C CNN
$EndComp
Wire Wire Line
8000 4450 7550 4450
Text Label 3450 4050 0 50 ~ 0
mosi_d
Text Label 3450 3950 0 50 ~ 0
miso
Wire Bus Line
7450 4250 7450 4550
Wire Bus Line
@ -602,8 +606,4 @@ Wire Bus Line
6150 2600 6900 2600
Wire Bus Line
6150 5050 6900 5050
Text Label 3450 4050 0 50 ~ 0
mosi_d
Text Label 3450 3950 0 50 ~ 0
miso
$EndSCHEMATC