electronics/ttl-fpga
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Include LUTD config in bit map

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Markus Koch 2019-05-31 20:36:00 +02:00
parent e66cd09c68
commit 37c33e8200
1 changed files with 6 additions and 6 deletions
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logic_block.sch
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@ -1576,8 +1576,8 @@ Wire Wire Line
Connection ~ 3400 2350
Wire Wire Line
3400 2350 3400 3550
Text Notes 650 3850 0 50 ~ 0
ISP Configuration Bit Mapping:\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED enable_n\n\n [30]: Synchronous mode\n [31]: LUT mode 3/4
Text Notes 650 4250 0 50 ~ 0
ISP Configuration Bit Mapping:\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED enable_n\n\n [30]: Synchronous mode\n [31]: LUT mode 3/4\n\n [47..32]: LUT-4 content\n [39..32]: LUT-3/1\n [47..40]: LUT-3/2
Wire Wire Line
1000 2500 3150 2500
Wire Wire Line
@ -1587,11 +1587,11 @@ isp_miso
Wire Notes Line
550 2000 1900 2000
Wire Notes Line
1900 2000 1900 3900
1900 2000 1900 4300
Wire Notes Line
1900 3900 550 3900
1900 4300 550 4300
Wire Notes Line
550 2000 550 3900
550 2000 550 4300
Text Notes 1450 2100 0 50 ~ 10
ISP SPI IF
Text HLabel 5600 6300 0 50 Input ~ 0
@ -2487,6 +2487,7 @@ Wire Bus Line
5700 5350 5700 5500
Wire Bus Line
5700 5350 5850 5350
Connection ~ 5700 5350
Wire Bus Line
12250 8250 12850 8250
Wire Bus Line
@ -2511,5 +2512,4 @@ Wire Bus Line
7100 2200 7100 4750
Wire Bus Line
5250 2200 5250 4750
Connection ~ 5700 5350
$EndSCHEMATC