electronics/ttl-fpga
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kicad: Update kicad_pcb schematic to include bodge-fixes

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This commit is contained in:
Markus Koch 2019-09-22 18:19:06 +02:00
parent 7544e4256a
commit 4424d762f7
3 changed files with 51 additions and 47 deletions
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90
kicad_pcb/logic_block.sch
View File

@ -1,13 +1,13 @@
EESchema Schematic File Version 4
LIBS:ttl-fpga-cache
EELAYER 29 0
EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 2 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "02L"
Rev "03L"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block"
Comment2 ""
@ -2125,19 +2125,6 @@ F 3 "" H 9100 6950 50 0001 C CNN
1 9100 6950
1 0 0 -1
$EndComp
$Comp
L 74xx_IEEE:74253 U?
U 1 1 5D7AF006
P 9300 6050
AR Path="/5D7AF006" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF006" Ref="U7" Part="1"
F 0 "U7" H 9650 6600 50 0000 C CNN
F 1 "74253" H 9700 6750 50 0000 C CNN
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 9300 6050 50 0001 C CNN
F 3 "" H 9300 6050 50 0001 C CNN
1 9300 6050
1 0 0 -1
$EndComp
Wire Wire Line
8750 5800 8350 5800
Wire Wire Line
@ -2174,9 +2161,6 @@ Wire Wire Line
Wire Wire Line
8250 5900 8250 6600
Connection ~ 8250 6600
Wire Wire Line
8150 6000 8150 6500
Connection ~ 8150 6500
Wire Wire Line
8050 6100 8050 6400
Connection ~ 8050 6400
@ -2188,39 +2172,15 @@ Wire Wire Line
8750 6000 8150 6000
Wire Wire Line
8050 6100 8750 6100
Wire Wire Line
8750 6400 8050 6400
Wire Wire Line
8050 6400 8050 7950
Connection ~ 8050 7950
Wire Wire Line
8750 6500 8150 6500
Wire Wire Line
8250 6600 8250 7750
Connection ~ 8250 7750
Wire Wire Line
8250 6600 8750 6600
Wire Wire Line
8750 7750 8250 7750
Wire Wire Line
8150 6500 8150 7850
Connection ~ 8150 7850
Wire Wire Line
8150 7850 8150 8350
Wire Wire Line
8150 7850 8750 7850
8250 6600 8650 6600
Wire Wire Line
8750 7950 8050 7950
Wire Wire Line
8050 7950 8050 8250
Wire Wire Line
8250 8450 8750 8450
Wire Wire Line
8250 7750 8250 8450
Wire Wire Line
8150 8350 8750 8350
Wire Wire Line
8050 8250 8750 8250
Text Label 10600 5900 2 50 ~ 0
fabric0
$Comp
@ -2533,6 +2493,38 @@ Wire Notes Line
5300 5500 4850 5500
Text Notes 4900 5600 0 50 ~ 0
cfg[28..16]
$Comp
L 74xx_IEEE:74253 U?
U 1 1 5D7AF006
P 9300 6050
AR Path="/5D7AF006" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF006" Ref="U7" Part="1"
F 0 "U7" H 9650 6600 50 0000 C CNN
F 1 "74253" H 9700 6750 50 0000 C CNN
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 9300 6050 50 0001 C CNN
F 3 "" H 9300 6050 50 0001 C CNN
1 9300 6050
1 0 0 -1
$EndComp
Wire Wire Line
8750 6500 8650 6500
Wire Wire Line
8050 6400 8750 6400
Wire Wire Line
8650 6500 8650 6600
Connection ~ 8650 6600
Wire Wire Line
8650 6600 8750 6600
Wire Wire Line
8050 8250 8750 8250
Wire Wire Line
8150 8350 8750 8350
Wire Wire Line
8250 8450 8750 8450
Wire Wire Line
8250 6600 8250 7750
Wire Wire Line
8250 7750 8750 7750
Wire Bus Line
13100 7850 13700 7850
Wire Bus Line
@ -2557,4 +2549,16 @@ Wire Bus Line
7750 1800 7750 4350
Wire Bus Line
5900 1800 5900 4350
Connection ~ 8250 7750
Wire Wire Line
8250 7750 8250 8450
Wire Wire Line
8150 6000 8150 7850
Wire Wire Line
8150 7850 8150 8350
Connection ~ 8150 7850
Wire Wire Line
8150 7850 8750 7850
Text Notes 10050 7250 0 50 ~ 0
SEL00 = CC\nSEL01 = Ab\nSEL10 = BB \nSEL11 = bA
$EndSCHEMATC

4
kicad_pcb/lutd.sch
View File

@ -1,13 +1,13 @@
EESchema Schematic File Version 4
LIBS:ttl-fpga-cache
EELAYER 29 0
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 3 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "02L"
Rev "03L"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block"
Comment2 "single 4-input LUT / dual 3-input LUT"

4
kicad_pcb/ttl-fpga.sch
View File

@ -1,13 +1,13 @@
EESchema Schematic File Version 4
LIBS:ttl-fpga-cache
EELAYER 29 0
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "02L"
Rev "03L"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "PCB"
Comment2 ""