electronics/ttl-fpga
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Markus Koch 2019-05-31 22:14:42 +02:00
parent 7066cd590e
commit 5445fa2831
3 changed files with 5 additions and 5 deletions
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6
logic_block.sch
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@ -6,7 +6,7 @@ $Descr A3 16535 11693
encoding utf-8 encoding utf-8
Sheet 2 3 Sheet 2 3
Title "DISCRETE TTL FPGA" Title "DISCRETE TTL FPGA"
Date "" Date "2019-05-31"
Rev "01" Rev "01"
Comp "Markus Koch <markus@notsyncing.net>" Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block" Comment1 "Logic Block"
@ -1800,8 +1800,8 @@ Wire Notes Line
12650 5000 14300 5000 12650 5000 14300 5000
Wire Wire Line Wire Wire Line
3800 5400 6450 5400 3800 5400 6450 5400
Text Notes 7500 5050 0 50 ~ 10 Text Notes 7200 5050 0 50 ~ 10
LUT LUT + Reg
$Comp $Comp
L Device:R R? L Device:R R?
U 1 1 5F6FE7F1 U 1 1 5F6FE7F1

2
lutd.sch
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@ -6,7 +6,7 @@ $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 3 3 Sheet 3 3
Title "DISCRETE TTL FPGA" Title "DISCRETE TTL FPGA"
Date "" Date "2019-05-31"
Rev "01" Rev "01"
Comp "Markus Koch <markus@notsyncing.net>" Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block" Comment1 "Logic Block"

2
ttl-fpga.sch
View File

@ -6,7 +6,7 @@ $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 1 3 Sheet 1 3
Title "DISCRETE TTL FPGA" Title "DISCRETE TTL FPGA"
Date "" Date "2019-05-31"
Rev "01" Rev "01"
Comp "Markus Koch <markus@notsyncing.net>" Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "PCB" Comment1 "PCB"