Editorial
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@ -6,7 +6,7 @@ $Descr A3 16535 11693
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encoding utf-8
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Sheet 2 3
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Title "DISCRETE TTL FPGA"
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Date ""
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Date "2019-05-31"
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Rev "01"
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Comp "Markus Koch <markus@notsyncing.net>"
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Comment1 "Logic Block"
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@ -1800,8 +1800,8 @@ Wire Notes Line
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12650 5000 14300 5000
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Wire Wire Line
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3800 5400 6450 5400
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Text Notes 7500 5050 0 50 ~ 10
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LUT
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Text Notes 7200 5050 0 50 ~ 10
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LUT + Reg
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$Comp
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L Device:R R?
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U 1 1 5F6FE7F1
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2
lutd.sch
2
lutd.sch
@ -6,7 +6,7 @@ $Descr A4 11693 8268
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encoding utf-8
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Sheet 3 3
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Title "DISCRETE TTL FPGA"
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Date ""
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Date "2019-05-31"
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Rev "01"
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Comp "Markus Koch <markus@notsyncing.net>"
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Comment1 "Logic Block"
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@ -6,7 +6,7 @@ $Descr A4 11693 8268
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encoding utf-8
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Sheet 1 3
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Title "DISCRETE TTL FPGA"
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Date ""
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Date "2019-05-31"
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Rev "01"
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Comp "Markus Koch <markus@notsyncing.net>"
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Comment1 "PCB"
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