electronics/ttl-fpga
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Change input LUT mapping to allow F3 access in mode-3

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Markus Koch 2019-06-01 22:03:01 +02:00
parent f762348d03
commit 626dbde9fe
1 changed files with 5 additions and 3 deletions
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8
logic_block.sch
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@ -1257,7 +1257,7 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
5200 9300 4800 9300 5200 9300 4800 9300
Text Label 5200 9900 2 50 ~ 0 Text Label 5200 9900 2 50 ~ 0
fabric2 fabric3
Wire Wire Line Wire Wire Line
5200 9200 4800 9200 5200 9200 4800 9200
Text Label 5200 9200 2 50 ~ 0 Text Label 5200 9200 2 50 ~ 0
@ -1430,8 +1430,6 @@ Wire Wire Line
3600 9750 3600 9650 3600 9750 3600 9650
Wire Wire Line Wire Wire Line
3600 9650 3700 9650 3600 9650 3700 9650
Text Notes 2900 9400 0 50 ~ 0
LUT Input Limitations:\n* 4-bit: Never F3+L2\n* 3-bit: Never F3+L2, L3
Text Label 4450 6100 0 50 ~ 0 Text Label 4450 6100 0 50 ~ 0
lut_in[3..0] lut_in[3..0]
Wire Bus Line Wire Bus Line
@ -2525,4 +2523,8 @@ Wire Bus Line
7750 1800 7750 4350 7750 1800 7750 4350
Wire Bus Line Wire Bus Line
5900 1800 5900 4350 5900 1800 5900 4350
Text Notes 2900 9400 0 50 ~ 0
LUT Input Limitations:\n* 4-bit: Never L2+L3+F3\n L0+L1+F2\n* 3-bit: Never L2+F3
Text Notes 5200 9900 0 50 ~ 0
*
$EndSCHEMATC $EndSCHEMATC