electronics/ttl-fpga
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Configure Gerber export for PCBWay

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This commit is contained in:
Markus Koch 2019-06-16 13:40:37 +02:00
parent b8c465da70
commit 7544e4256a
1 changed files with 5 additions and 5 deletions
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10
kicad_pcb/ttl-fpga.kicad_pcb
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@ -65,7 +65,7 @@
(visible_elements FFFFEF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberextensions true)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
@ -87,9 +87,9 @@
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(drillshape 0)
(scaleselection 1)
(outputdirectory ""))
(outputdirectory "gerbers"))
)
(net 0 "")
@ -6618,7 +6618,7 @@
(segment (start 210.628601 83.553465) (end 210.628601 84.519399) (width 0.1524) (layer B.Cu) (net 110))
(segment (start 210.933412 83.248655) (end 210.628601 83.553465) (width 0.1524) (layer B.Cu) (net 110))
(zone (net 1) (net_name GND) (layer F.Cu) (tstamp 5D040CA7) (hatch edge 0.508)
(zone (net 1) (net_name GND) (layer F.Cu) (tstamp 5D065083) (hatch edge 0.508)
(connect_pads (clearance 0.1524))
(min_thickness 0.1524)
(fill yes (arc_segments 32) (thermal_gap 0.3) (thermal_bridge_width 0.2))
@ -8495,7 +8495,7 @@
)
)
)
(zone (net 1) (net_name GND) (layer B.Cu) (tstamp 5D040CA4) (hatch edge 0.508)
(zone (net 1) (net_name GND) (layer B.Cu) (tstamp 5D065080) (hatch edge 0.508)
(connect_pads (clearance 0.1524))
(min_thickness 0.1524)
(fill yes (arc_segments 32) (thermal_gap 0.3) (thermal_bridge_width 0.2))