From 8b80a78b3b755c8c9bcb3ffaf7c4ff7891cfc6b0 Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Wed, 5 Jun 2019 23:32:39 +0200 Subject: [PATCH] Layout input muxing --- kicad_pcb/logic_block.sch | 310 ++++++++++++----------- kicad_pcb/lutd.sch | 2 +- kicad_pcb/ttl-fpga.kicad_pcb | 468 ++++++++++++++++++++++++++--------- kicad_pcb/ttl-fpga.sch | 2 +- 4 files changed, 522 insertions(+), 260 deletions(-) diff --git a/kicad_pcb/logic_block.sch b/kicad_pcb/logic_block.sch index e59ed27..ba1298f 100644 --- a/kicad_pcb/logic_block.sch +++ b/kicad_pcb/logic_block.sch @@ -7,7 +7,7 @@ encoding utf-8 Sheet 2 3 Title "DISCRETE TTL FPGA" Date "2019-05-31" -Rev "02" +Rev "02L" Comp "Markus Koch " Comment1 "Logic Block" Comment2 "" @@ -982,8 +982,6 @@ F 3 "" H 2450 7350 50 0001 C CNN 1 2450 7350 1 0 0 -1 $EndComp -Text Label 1500 7650 0 50 ~ 0 -fabric_l3 Wire Wire Line 1350 6800 1350 6900 $Comp @@ -1018,26 +1016,22 @@ Text Label 1500 7550 0 50 ~ 0 fabric_l2 Text Label 1500 7350 0 50 ~ 0 fabric_l0 -Text Label 1500 7750 0 50 ~ 0 -fabric0 Text Label 1500 7850 0 50 ~ 0 +fabric0 +Text Label 1500 7750 0 50 ~ 0 fabric1 -Text Label 1500 7450 0 50 ~ 0 +Text Label 1500 7650 0 50 ~ 0 fabric_l1 -Wire Wire Line - 1500 7250 1900 7250 Wire Wire Line 1500 7950 1900 7950 Wire Wire Line 1500 7850 1900 7850 Wire Wire Line 1500 7750 1900 7750 -Wire Wire Line - 1500 7650 1900 7650 Wire Wire Line 1500 7550 1900 7550 Wire Wire Line - 1500 7450 1900 7450 + 1500 7650 1900 7650 Wire Wire Line 1500 7350 1900 7350 $Comp @@ -1164,8 +1158,6 @@ F 3 "" H 4250 6600 50 0001 C CNN 1 4250 6600 -1 0 0 -1 $EndComp -Text Label 1500 7250 0 50 ~ 0 -fabric2 Text Label 1500 9900 0 50 ~ 0 fabric_t1 Wire Wire Line @@ -1174,69 +1166,61 @@ Wire Wire Line 5200 7250 4800 7250 Text Label 5200 7950 2 50 ~ 0 fabric_t2 -Text Label 1500 9400 0 50 ~ 0 -fabric_l3 Text Label 1500 9500 0 50 ~ 0 fabric_l2 Text Label 1500 9700 0 50 ~ 0 fabric_l0 -Text Label 1500 9300 0 50 ~ 0 -fabric0 Text Label 1500 9200 0 50 ~ 0 +fabric0 +Text Label 1500 9300 0 50 ~ 0 fabric1 -Text Label 1500 9600 0 50 ~ 0 +Text Label 1500 9400 0 50 ~ 0 fabric_l1 Wire Wire Line 1500 9900 1900 9900 -Wire Wire Line - 1500 9800 1900 9800 Wire Wire Line 1500 9700 1900 9700 -Wire Wire Line - 1500 9600 1900 9600 -Wire Wire Line - 1500 9500 1900 9500 Wire Wire Line 1500 9400 1900 9400 +Wire Wire Line + 1500 9500 1900 9500 Wire Wire Line 1500 9300 1900 9300 -Text Label 1500 9800 0 50 ~ 0 -fabric2 -Text Label 5200 7650 2 50 ~ 0 +Text Label 5200 7450 2 50 ~ 0 fabric_l3 Text Label 5200 7550 2 50 ~ 0 fabric_l2 Text Label 5200 7350 2 50 ~ 0 fabric_l0 -Text Label 5200 7750 2 50 ~ 0 -fabric0 Text Label 5200 7850 2 50 ~ 0 +fabric0 +Text Label 5200 7750 2 50 ~ 0 fabric1 -Text Label 5200 7450 2 50 ~ 0 +Text Label 5200 7650 2 50 ~ 0 fabric_l1 Wire Wire Line 5200 7950 4800 7950 -Wire Wire Line - 5200 7850 4800 7850 Wire Wire Line 5200 7750 4800 7750 Wire Wire Line - 5200 7650 4800 7650 + 5200 7850 4800 7850 +Wire Wire Line + 5200 7450 4800 7450 Wire Wire Line 5200 7550 4800 7550 Wire Wire Line - 5200 7450 4800 7450 + 5200 7650 4800 7650 Wire Wire Line 5200 7350 4800 7350 Text Label 5200 7250 2 50 ~ 0 fabric3 -Text Label 5200 9400 2 50 ~ 0 +Text Label 5200 9600 2 50 ~ 0 fabric_l3 Text Label 5200 9500 2 50 ~ 0 fabric_l2 Text Label 5200 9700 2 50 ~ 0 fabric_l0 -Text Label 5200 9600 2 50 ~ 0 +Text Label 5200 9400 2 50 ~ 0 fabric_l1 Wire Wire Line 5200 9900 4800 9900 @@ -1245,17 +1229,17 @@ Wire Wire Line Wire Wire Line 5200 9700 4800 9700 Wire Wire Line - 5200 9600 4800 9600 + 5200 9400 4800 9400 Wire Wire Line 5200 9500 4800 9500 Wire Wire Line - 5200 9400 4800 9400 + 5200 9600 4800 9600 Wire Wire Line - 5200 9300 4800 9300 + 5200 9200 4800 9200 Text Label 5200 9800 2 50 ~ 0 fabric3 Wire Wire Line - 5200 9200 4800 9200 + 5200 9300 4800 9300 Text Label 5200 9900 2 50 ~ 0 fabric_t3 Wire Wire Line @@ -1543,7 +1527,7 @@ Wire Wire Line Wire Wire Line 4050 1600 4050 1950 Connection ~ 4050 3150 -Connection ~ 13650 4450 +Connection ~ 13650 3900 Wire Notes Line 15500 3700 10800 3700 Text Notes 14950 3850 0 50 ~ 10 @@ -1838,8 +1822,6 @@ Wire Notes Line 10800 3700 10800 8600 Wire Notes Line rgb(194, 0, 194) 10600 8250 14350 7400 -Wire Notes Line rgb(194, 0, 194) - 10600 7750 13900 6950 Wire Notes Line rgb(194, 0, 194) 10600 5900 13000 6050 Wire Notes Line @@ -1858,21 +1840,13 @@ Wire Wire Line 14650 7400 14350 7400 Wire Wire Line 14650 6950 13900 6950 -Text Label 12450 7100 0 50 ~ 0 -cfg7 -Text Label 12450 6650 0 50 ~ 0 -cfg6 -Text Label 12450 6200 0 50 ~ 0 -cfg5 -Text Label 12450 5750 0 50 ~ 0 -cfg4 -Text Label 14650 5300 1 50 ~ 0 -cfg3 Text Label 14200 5300 1 50 ~ 0 -cfg2 -Text Label 13750 5300 1 50 ~ 0 -cfg1 +cfg4 Text Label 13300 5300 1 50 ~ 0 +cfg3 +Text Label 12450 6650 0 50 ~ 0 +cfg2 +Text Label 12450 7100 0 50 ~ 0 cfg0 Connection ~ 13000 6050 Wire Wire Line @@ -1893,59 +1867,31 @@ fabric2 $Comp L 4xxx:4066 U? U 1 1 5D7AEF7A -P 12450 6050 +P 12450 6950 AR Path="/5D7AEF7A" Ref="U?" Part="1" AR Path="/5D77FDBE/5D7AEF7A" Ref="U4" Part="1" -F 0 "U4" H 12250 6000 50 0000 C CNN -F 1 "4066" H 12650 6000 50 0000 C CNN -F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 12450 6050 50 0001 C CNN -F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 12450 6050 50 0001 C CNN - 1 12450 6050 +F 0 "U4" H 12250 6900 50 0000 C CNN +F 1 "4066" H 12650 6900 50 0000 C CNN +F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 12450 6950 50 0001 C CNN +F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 12450 6950 50 0001 C CNN + 1 12450 6950 1 0 0 -1 $EndComp $Comp L 4xxx:4066 U? U 2 1 5D7AEF74 -P 12450 6500 +P 12450 7400 AR Path="/5D7AEF74" Ref="U?" Part="2" AR Path="/5D77FDBE/5D7AEF74" Ref="U4" Part="2" -F 0 "U4" H 12250 6450 50 0000 C CNN -F 1 "4066" H 12650 6450 50 0000 C CNN -F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 12450 6500 50 0001 C CNN -F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 12450 6500 50 0001 C CNN - 2 12450 6500 - 1 0 0 -1 -$EndComp -$Comp -L 4xxx:4066 U? -U 3 1 5D7AEF6E -P 12450 6950 -AR Path="/5D7AEF6E" Ref="U?" Part="3" -AR Path="/5D77FDBE/5D7AEF6E" Ref="U4" Part="3" -F 0 "U4" H 12250 6900 50 0000 C CNN -F 1 "4066" H 12650 6900 50 0000 C CNN -F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 12450 6950 50 0001 C CNN -F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 12450 6950 50 0001 C CNN - 3 12450 6950 - 1 0 0 -1 -$EndComp -$Comp -L 4xxx:4066 U? -U 4 1 5D7AEF68 -P 12450 7400 -AR Path="/5D7AEF68" Ref="U?" Part="4" -AR Path="/5D77FDBE/5D7AEF68" Ref="U4" Part="4" F 0 "U4" H 12250 7350 50 0000 C CNN F 1 "4066" H 12650 7350 50 0000 C CNN F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 12450 7400 50 0001 C CNN F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 12450 7400 50 0001 C CNN - 4 12450 7400 + 2 12450 7400 1 0 0 -1 $EndComp Wire Wire Line 12750 6050 13000 6050 -Wire Wire Line - 13450 6500 12750 6500 Wire Wire Line 12750 6950 13900 6950 Wire Wire Line @@ -1979,27 +1925,27 @@ $EndComp $Comp L 4xxx:4066 U? U 3 1 5D7AEF52 -P 13450 5300 +P 13000 5300 AR Path="/5D7AEF52" Ref="U?" Part="3" AR Path="/5D77FDBE/5D7AEF52" Ref="U3" Part="3" -F 0 "U3" H 13250 5350 50 0000 C CNN -F 1 "4066" H 13650 5350 50 0000 C CNN -F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 13450 5300 50 0001 C CNN -F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 13450 5300 50 0001 C CNN - 3 13450 5300 +F 0 "U3" H 12800 5350 50 0000 C CNN +F 1 "4066" H 13200 5350 50 0000 C CNN +F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 13000 5300 50 0001 C CNN +F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 13000 5300 50 0001 C CNN + 3 13000 5300 0 1 1 0 $EndComp $Comp L 4xxx:4066 U? U 4 1 5D7AEF4C -P 13000 5300 +P 13450 5300 AR Path="/5D7AEF4C" Ref="U?" Part="4" AR Path="/5D77FDBE/5D7AEF4C" Ref="U3" Part="4" -F 0 "U3" H 12800 5350 50 0000 C CNN -F 1 "4066" H 13200 5350 50 0000 C CNN -F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 13000 5300 50 0001 C CNN -F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 13000 5300 50 0001 C CNN - 4 13000 5300 +F 0 "U3" H 13250 5350 50 0000 C CNN +F 1 "4066" H 13650 5350 50 0000 C CNN +F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 13450 5300 50 0001 C CNN +F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 13450 5300 50 0001 C CNN + 4 13450 5300 0 1 1 0 $EndComp Entry Wire Line @@ -2016,58 +1962,58 @@ Connection ~ 14750 6700 Text HLabel 14850 6700 2 50 BiDi ~ 0 fabric_r[3..0] Wire Wire Line - 12150 7400 11700 7400 -Text Label 12100 7400 2 50 ~ 0 + 12350 5300 11900 5300 +Text Label 12300 5300 2 50 ~ 0 fabric_l3 Wire Wire Line - 12150 6950 11700 6950 -Text Label 12100 6950 2 50 ~ 0 + 12350 4850 11900 4850 +Text Label 12300 4850 2 50 ~ 0 fabric_l2 Wire Wire Line - 12150 6500 11700 6500 -Text Label 12100 6500 2 50 ~ 0 + 12350 4400 11900 4400 +Text Label 12300 4400 2 50 ~ 0 fabric_l1 Wire Wire Line - 12150 6050 11700 6050 -Text Label 12100 6050 2 50 ~ 0 + 12350 3950 11900 3950 +Text Label 12300 3950 2 50 ~ 0 fabric_l0 Entry Wire Line - 11700 7400 11600 7300 + 11900 5300 11800 5200 Entry Wire Line - 11700 6950 11600 6850 + 11900 4850 11800 4750 Entry Wire Line - 11700 6500 11600 6600 + 11900 4400 11800 4500 Entry Wire Line - 11700 6050 11600 6150 + 11900 3950 11800 4050 Wire Bus Line - 11600 6750 11450 6750 -Connection ~ 11600 6750 -Text HLabel 11450 6750 0 50 BiDi ~ 0 + 11800 4650 11650 4650 +Connection ~ 11800 4650 +Text HLabel 11650 4650 0 50 BiDi ~ 0 fabric_l[3..0] Wire Wire Line - 13000 5000 13000 4550 -Text Label 13000 4950 1 50 ~ 0 + 13000 4450 13000 4000 +Text Label 13000 4400 1 50 ~ 0 fabric_t0 Wire Wire Line - 13450 5000 13450 4550 -Text Label 13450 4950 1 50 ~ 0 + 13450 4450 13450 4000 +Text Label 13450 4400 1 50 ~ 0 fabric_t1 Wire Wire Line - 13900 5000 13900 4550 -Text Label 13900 4950 1 50 ~ 0 + 13900 4450 13900 4000 +Text Label 13900 4400 1 50 ~ 0 fabric_t2 Wire Wire Line - 14350 5000 14350 4550 -Text Label 14350 4950 1 50 ~ 0 + 14350 4450 14350 4000 +Text Label 14350 4400 1 50 ~ 0 fabric_t3 Entry Wire Line - 13000 4550 13100 4450 + 13000 4000 13100 3900 Entry Wire Line - 13450 4550 13550 4450 + 13450 4000 13550 3900 Entry Wire Line - 13900 4550 13800 4450 + 13900 4000 13800 3900 Entry Wire Line - 14350 4550 14250 4450 + 14350 4000 14250 3900 Entry Wire Line 14350 7750 14250 7850 Entry Wire Line @@ -2487,31 +2433,117 @@ Wire Wire Line 7750 5800 8350 5800 Connection ~ 8350 5800 Wire Bus Line - 13650 4450 13650 4350 -Text HLabel 13650 4350 1 50 BiDi ~ 0 + 13650 3900 13650 3800 +Text HLabel 13650 3800 1 50 BiDi ~ 0 fabric_t[3..0] Text Notes 2900 9400 0 50 ~ 0 LUT Input Limitations:\n* 4-bit: Never T2+T3+F3\n T0+T1+F2\n* 3-bit: Never T2+F3, T3 Text Notes 5200 9800 0 50 ~ 0 * -Text Label 5200 9300 2 50 ~ 0 -fabric0 Text Label 5200 9200 2 50 ~ 0 +fabric0 +Text Label 5200 9300 2 50 ~ 0 fabric1 Wire Wire Line 14350 5600 14350 7400 +$Comp +L 4xxx:4066 U? +U 4 1 5D7AEF68 +P 12450 6500 +AR Path="/5D7AEF68" Ref="U?" Part="4" +AR Path="/5D77FDBE/5D7AEF68" Ref="U4" Part="4" +F 0 "U4" H 12250 6450 50 0000 C CNN +F 1 "4066" H 12650 6450 50 0000 C CNN +F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 12450 6500 50 0001 C CNN +F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 12450 6500 50 0001 C CNN + 4 12450 6500 + 1 0 0 -1 +$EndComp +$Comp +L 4xxx:4066 U? +U 3 1 5D7AEF6E +P 12450 6050 +AR Path="/5D7AEF6E" Ref="U?" Part="3" +AR Path="/5D77FDBE/5D7AEF6E" Ref="U4" Part="3" +F 0 "U4" H 12250 6000 50 0000 C CNN +F 1 "4066" H 12650 6000 50 0000 C CNN +F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 12450 6050 50 0001 C CNN +F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 12450 6050 50 0001 C CNN + 3 12450 6050 + 1 0 0 -1 +$EndComp +Text Label 13750 5300 1 50 ~ 0 +cfg6 +Text Label 14650 5300 1 50 ~ 0 +cfg7 +Wire Notes Line rgb(194, 0, 194) + 10600 7750 13900 6950 +Wire Wire Line + 12150 6500 11700 6500 +Text Label 12100 6500 2 50 ~ 0 +fabric_t1 +Wire Wire Line + 12150 6950 11700 6950 +Text Label 12100 6950 2 50 ~ 0 +fabric_t2 +Wire Wire Line + 14350 5000 14350 4550 +Text Label 14350 4950 1 50 ~ 0 +fabric_t3 +Wire Wire Line + 12150 7400 11700 7400 +Text Label 12100 7400 2 50 ~ 0 +fabric_l3 +Wire Wire Line + 13900 4550 13900 5000 +Text Label 13900 4600 3 50 ~ 0 +fabric_l2 +Wire Wire Line + 13450 4550 13450 5000 +Text Label 13450 4600 3 50 ~ 0 +fabric_l1 +Wire Wire Line + 13000 4550 13000 5000 +Text Label 13000 4600 3 50 ~ 0 +fabric_l0 +Wire Wire Line + 12750 6500 13450 6500 +Text Label 12100 6050 2 50 ~ 0 +fabric_t0 +Wire Wire Line + 12150 6050 11700 6050 +Text Label 1500 7250 0 50 ~ 0 +fabric2 +Wire Wire Line + 1500 7250 1900 7250 +Wire Wire Line + 1500 7450 1900 7450 +Text Label 1500 7450 0 50 ~ 0 +fabric_l3 +Text Label 1500 9800 0 50 ~ 0 +fabric2 +Wire Wire Line + 1500 9800 1900 9800 +Wire Wire Line + 1500 9600 1900 9600 +Text Label 1500 9600 0 50 ~ 0 +fabric_l3 +Text Label 12450 6200 0 50 ~ 0 +cfg1 +Text Label 12450 5750 0 50 ~ 0 +cfg5 Wire Bus Line 13100 7850 13700 7850 Wire Bus Line 13700 7850 14250 7850 Wire Bus Line - 13650 4450 14250 4450 + 13650 3900 14250 3900 Wire Bus Line - 13100 4450 13650 4450 + 13100 3900 13650 3900 Wire Bus Line - 11600 6150 11600 6750 + 11800 4050 11800 4650 Wire Bus Line - 11600 6750 11600 7300 + 11800 4650 11800 5200 Wire Bus Line 14750 6700 14750 7300 Wire Bus Line diff --git a/kicad_pcb/lutd.sch b/kicad_pcb/lutd.sch index 022cfa2..2149313 100644 --- a/kicad_pcb/lutd.sch +++ b/kicad_pcb/lutd.sch @@ -7,7 +7,7 @@ encoding utf-8 Sheet 3 3 Title "DISCRETE TTL FPGA" Date "2019-05-31" -Rev "02" +Rev "02L" Comp "Markus Koch " Comment1 "Logic Block" Comment2 "single 4-input LUT / dual 3-input LUT" diff --git a/kicad_pcb/ttl-fpga.kicad_pcb b/kicad_pcb/ttl-fpga.kicad_pcb index 1b36c4e..4cf3d43 100644 --- a/kicad_pcb/ttl-fpga.kicad_pcb +++ b/kicad_pcb/ttl-fpga.kicad_pcb @@ -3,7 +3,7 @@ (general (thickness 1.6) (drawings 4) - (tracks 0) + (tracks 229) (zones 0) (modules 71) (nets 111) @@ -352,7 +352,7 @@ (pad 1 smd roundrect (at -2.475 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 34 /fabric_l2)) (pad 2 smd roundrect (at -2.475 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 33 /fabric_l1)) + (net 35 /fabric_l3)) (pad 3 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 32 /fabric_l0)) (pad 4 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) @@ -374,11 +374,11 @@ (pad 12 smd roundrect (at 2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 23 /fabric_t0)) (pad 13 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 39 /fabric_b1)) - (pad 14 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 40 /fabric_b0)) + (pad 14 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 39 /fabric_b1)) (pad 15 smd roundrect (at 2.475 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 35 /fabric_l3)) + (net 33 /fabric_l1)) (pad 16 smd roundrect (at 2.475 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 2 VCC)) (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-16_3.9x9.9mm_P1.27mm.wrl @@ -2430,7 +2430,7 @@ ) (module Package_SO:SOIC-14_3.9x8.7mm_P1.27mm (layer B.Cu) (tedit 5C97300E) (tstamp 5CF2C830) - (at 102.87 49.53) + (at 92.775 50.8) (descr "SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") (tags "SOIC SO") (path /5D77FDBE/5DA6508D) @@ -2441,50 +2441,50 @@ (fp_text value 74164 (at 0 -5.28) (layer B.Fab) (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_line (start 0 -4.435) (end 1.95 -4.435) (layer B.SilkS) (width 0.12)) - (fp_line (start 0 -4.435) (end -1.95 -4.435) (layer B.SilkS) (width 0.12)) - (fp_line (start 0 4.435) (end 1.95 4.435) (layer B.SilkS) (width 0.12)) - (fp_line (start 0 4.435) (end -3.45 4.435) (layer B.SilkS) (width 0.12)) - (fp_line (start -0.975 4.325) (end 1.95 4.325) (layer B.Fab) (width 0.1)) - (fp_line (start 1.95 4.325) (end 1.95 -4.325) (layer B.Fab) (width 0.1)) - (fp_line (start 1.95 -4.325) (end -1.95 -4.325) (layer B.Fab) (width 0.1)) - (fp_line (start -1.95 -4.325) (end -1.95 3.35) (layer B.Fab) (width 0.1)) - (fp_line (start -1.95 3.35) (end -0.975 4.325) (layer B.Fab) (width 0.1)) - (fp_line (start -3.7 4.58) (end -3.7 -4.58) (layer B.CrtYd) (width 0.05)) - (fp_line (start -3.7 -4.58) (end 3.7 -4.58) (layer B.CrtYd) (width 0.05)) - (fp_line (start 3.7 -4.58) (end 3.7 4.58) (layer B.CrtYd) (width 0.05)) - (fp_line (start 3.7 4.58) (end -3.7 4.58) (layer B.CrtYd) (width 0.05)) (fp_text user %R (at 0 0) (layer B.Fab) (effects (font (size 0.98 0.98) (thickness 0.15)) (justify mirror)) ) - (pad 1 smd roundrect (at -2.475 3.81) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 26 /LogicBlock/isp_mosi)) - (pad 2 smd roundrect (at -2.475 2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 26 /LogicBlock/isp_mosi)) - (pad 3 smd roundrect (at -2.475 1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 50 /LogicBlock/cfg0)) - (pad 4 smd roundrect (at -2.475 0) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 51 /LogicBlock/cfg1)) - (pad 5 smd roundrect (at -2.475 -1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 52 /LogicBlock/cfg2)) - (pad 6 smd roundrect (at -2.475 -2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 53 /LogicBlock/cfg3)) - (pad 7 smd roundrect (at -2.475 -3.81) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 1 GND)) - (pad 8 smd roundrect (at 2.475 -3.81) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 27 /LogicBlock/isp_sck)) - (pad 9 smd roundrect (at 2.475 -2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 2 VCC)) - (pad 10 smd roundrect (at 2.475 -1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 54 /LogicBlock/cfg4)) - (pad 11 smd roundrect (at 2.475 0) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 55 /LogicBlock/cfg5)) - (pad 12 smd roundrect (at 2.475 1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 56 /LogicBlock/cfg6)) - (pad 13 smd roundrect (at 2.475 2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 57 /LogicBlock/cfg7)) + (fp_line (start 3.7 4.58) (end -3.7 4.58) (layer B.CrtYd) (width 0.05)) + (fp_line (start 3.7 -4.58) (end 3.7 4.58) (layer B.CrtYd) (width 0.05)) + (fp_line (start -3.7 -4.58) (end 3.7 -4.58) (layer B.CrtYd) (width 0.05)) + (fp_line (start -3.7 4.58) (end -3.7 -4.58) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.95 3.35) (end -0.975 4.325) (layer B.Fab) (width 0.1)) + (fp_line (start -1.95 -4.325) (end -1.95 3.35) (layer B.Fab) (width 0.1)) + (fp_line (start 1.95 -4.325) (end -1.95 -4.325) (layer B.Fab) (width 0.1)) + (fp_line (start 1.95 4.325) (end 1.95 -4.325) (layer B.Fab) (width 0.1)) + (fp_line (start -0.975 4.325) (end 1.95 4.325) (layer B.Fab) (width 0.1)) + (fp_line (start 0 4.435) (end -3.45 4.435) (layer B.SilkS) (width 0.12)) + (fp_line (start 0 4.435) (end 1.95 4.435) (layer B.SilkS) (width 0.12)) + (fp_line (start 0 -4.435) (end -1.95 -4.435) (layer B.SilkS) (width 0.12)) + (fp_line (start 0 -4.435) (end 1.95 -4.435) (layer B.SilkS) (width 0.12)) (pad 14 smd roundrect (at 2.475 3.81) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 2 VCC)) + (pad 13 smd roundrect (at 2.475 2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 57 /LogicBlock/cfg7)) + (pad 12 smd roundrect (at 2.475 1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 56 /LogicBlock/cfg6)) + (pad 11 smd roundrect (at 2.475 0) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 55 /LogicBlock/cfg5)) + (pad 10 smd roundrect (at 2.475 -1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 54 /LogicBlock/cfg4)) + (pad 9 smd roundrect (at 2.475 -2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 2 VCC)) + (pad 8 smd roundrect (at 2.475 -3.81) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 27 /LogicBlock/isp_sck)) + (pad 7 smd roundrect (at -2.475 -3.81) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 6 smd roundrect (at -2.475 -2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 53 /LogicBlock/cfg3)) + (pad 5 smd roundrect (at -2.475 -1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 52 /LogicBlock/cfg2)) + (pad 4 smd roundrect (at -2.475 0) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 51 /LogicBlock/cfg1)) + (pad 3 smd roundrect (at -2.475 1.27) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 50 /LogicBlock/cfg0)) + (pad 2 smd roundrect (at -2.475 2.54) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 26 /LogicBlock/isp_mosi)) + (pad 1 smd roundrect (at -2.475 3.81) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 26 /LogicBlock/isp_mosi)) (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-14_3.9x8.7mm_P1.27mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -2493,7 +2493,7 @@ ) (module Package_SO:SOIC-14_3.9x8.7mm_P1.27mm (layer B.Cu) (tedit 5C97300E) (tstamp 5CF85585) - (at 91.505 63.5) + (at 99.06358 71.9836) (descr "SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") (tags "SOIC SO") (path /5D77FDBE/5DB5F0CD) @@ -2619,7 +2619,7 @@ ) (module Package_SO:SOIC-14_3.9x8.7mm_P1.27mm (layer F.Cu) (tedit 5C97300E) (tstamp 5CF57B3F) - (at 115.57 72.39 90) + (at 102.87 72.39 90) (descr "SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") (tags "SOIC SO") (path /5D77FDBE/5DB5F0EE) @@ -2749,7 +2749,7 @@ ) (module Package_SO:SOIC-16_3.9x9.9mm_P1.27mm (layer B.Cu) (tedit 5C97300E) (tstamp 5CF84EFF) - (at 106.615 61.595 180) + (at 107.885 61.595 180) (descr "SOIC, 16 Pin (JEDEC MS-012AC, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") (tags "SOIC SO") (path /5D77FDBE/5E01B8F6) @@ -2779,7 +2779,7 @@ (pad 1 smd roundrect (at -2.475 4.445 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 34 /fabric_l2)) (pad 2 smd roundrect (at -2.475 3.175 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 33 /fabric_l1)) + (net 35 /fabric_l3)) (pad 3 smd roundrect (at -2.475 1.905 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 32 /fabric_l0)) (pad 4 smd roundrect (at -2.475 0.635 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) @@ -2801,11 +2801,11 @@ (pad 12 smd roundrect (at 2.475 -0.635 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 21 /fabric_t2)) (pad 13 smd roundrect (at 2.475 0.635 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 39 /fabric_b1)) - (pad 14 smd roundrect (at 2.475 1.905 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 40 /fabric_b0)) + (pad 14 smd roundrect (at 2.475 1.905 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 39 /fabric_b1)) (pad 15 smd roundrect (at 2.475 3.175 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 35 /fabric_l3)) + (net 33 /fabric_l1)) (pad 16 smd roundrect (at 2.475 4.445 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 2 VCC)) (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-16_3.9x9.9mm_P1.27mm.wrl @@ -2913,7 +2913,7 @@ (pad 16 smd roundrect (at 2.475 4.445 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 2 VCC)) (pad 15 smd roundrect (at 2.475 3.175 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 33 /fabric_l1)) + (net 35 /fabric_l3)) (pad 14 smd roundrect (at 2.475 1.905 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 32 /fabric_l0)) (pad 13 smd roundrect (at 2.475 0.635 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) @@ -2935,11 +2935,11 @@ (pad 5 smd roundrect (at -2.475 -0.635 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 81 /LogicBlock/lut_in1)) (pad 4 smd roundrect (at -2.475 0.635 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 39 /fabric_b1)) - (pad 3 smd roundrect (at -2.475 1.905 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 40 /fabric_b0)) + (pad 3 smd roundrect (at -2.475 1.905 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 39 /fabric_b1)) (pad 2 smd roundrect (at -2.475 3.175 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) - (net 35 /fabric_l3)) + (net 33 /fabric_l1)) (pad 1 smd roundrect (at -2.475 4.445 180) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 34 /fabric_l2)) (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-16_3.9x9.9mm_P1.27mm.wrl @@ -2950,7 +2950,7 @@ ) (module Package_SO:SOIC-16_3.9x9.9mm_P1.27mm (layer F.Cu) (tedit 5C97300E) (tstamp 5CF733FC) - (at 106.615 61.595) + (at 107.885 61.595) (descr "SOIC, 16 Pin (JEDEC MS-012AC, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") (tags "SOIC SO") (path /5D77FDBE/5E01B8D6) @@ -2980,7 +2980,7 @@ (pad 16 smd roundrect (at 2.475 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 2 VCC)) (pad 15 smd roundrect (at 2.475 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 33 /fabric_l1)) + (net 35 /fabric_l3)) (pad 14 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 32 /fabric_l0)) (pad 13 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) @@ -3002,11 +3002,11 @@ (pad 5 smd roundrect (at -2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 82 /LogicBlock/lut_in3)) (pad 4 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 39 /fabric_b1)) - (pad 3 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 40 /fabric_b0)) + (pad 3 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 39 /fabric_b1)) (pad 2 smd roundrect (at -2.475 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 35 /fabric_l3)) + (net 33 /fabric_l1)) (pad 1 smd roundrect (at -2.475 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 34 /fabric_l2)) (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-16_3.9x9.9mm_P1.27mm.wrl @@ -3343,61 +3343,61 @@ ) ) - (module Package_SO:SOIC-14_3.9x8.7mm_P1.27mm (layer F.Cu) (tedit 5C97300E) (tstamp 5CF2E0C2) - (at 99.06 49.53) + (module Package_SO:SOIC-14_3.9x8.7mm_P1.27mm (layer B.Cu) (tedit 5C97300E) (tstamp 5CF8DCF5) + (at 102.235 50.735 270) (descr "SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") (tags "SOIC SO") (path /5D77FDBE/5E0E0FAE) (attr smd) - (fp_text reference U3 (at 0 -5.28) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text reference U3 (at 0 5.28 90) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_text value 4066 (at 0 5.28) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text value 4066 (at 0 -5.28 90) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_line (start 0 4.435) (end 1.95 4.435) (layer F.SilkS) (width 0.12)) - (fp_line (start 0 4.435) (end -1.95 4.435) (layer F.SilkS) (width 0.12)) - (fp_line (start 0 -4.435) (end 1.95 -4.435) (layer F.SilkS) (width 0.12)) - (fp_line (start 0 -4.435) (end -3.45 -4.435) (layer F.SilkS) (width 0.12)) - (fp_line (start -0.975 -4.325) (end 1.95 -4.325) (layer F.Fab) (width 0.1)) - (fp_line (start 1.95 -4.325) (end 1.95 4.325) (layer F.Fab) (width 0.1)) - (fp_line (start 1.95 4.325) (end -1.95 4.325) (layer F.Fab) (width 0.1)) - (fp_line (start -1.95 4.325) (end -1.95 -3.35) (layer F.Fab) (width 0.1)) - (fp_line (start -1.95 -3.35) (end -0.975 -4.325) (layer F.Fab) (width 0.1)) - (fp_line (start -3.7 -4.58) (end -3.7 4.58) (layer F.CrtYd) (width 0.05)) - (fp_line (start -3.7 4.58) (end 3.7 4.58) (layer F.CrtYd) (width 0.05)) - (fp_line (start 3.7 4.58) (end 3.7 -4.58) (layer F.CrtYd) (width 0.05)) - (fp_line (start 3.7 -4.58) (end -3.7 -4.58) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.98 0.98) (thickness 0.15))) + (fp_line (start 0 -4.435) (end 1.95 -4.435) (layer B.SilkS) (width 0.12)) + (fp_line (start 0 -4.435) (end -1.95 -4.435) (layer B.SilkS) (width 0.12)) + (fp_line (start 0 4.435) (end 1.95 4.435) (layer B.SilkS) (width 0.12)) + (fp_line (start 0 4.435) (end -3.45 4.435) (layer B.SilkS) (width 0.12)) + (fp_line (start -0.975 4.325) (end 1.95 4.325) (layer B.Fab) (width 0.1)) + (fp_line (start 1.95 4.325) (end 1.95 -4.325) (layer B.Fab) (width 0.1)) + (fp_line (start 1.95 -4.325) (end -1.95 -4.325) (layer B.Fab) (width 0.1)) + (fp_line (start -1.95 -4.325) (end -1.95 3.35) (layer B.Fab) (width 0.1)) + (fp_line (start -1.95 3.35) (end -0.975 4.325) (layer B.Fab) (width 0.1)) + (fp_line (start -3.7 4.58) (end -3.7 -4.58) (layer B.CrtYd) (width 0.05)) + (fp_line (start -3.7 -4.58) (end 3.7 -4.58) (layer B.CrtYd) (width 0.05)) + (fp_line (start 3.7 -4.58) (end 3.7 4.58) (layer B.CrtYd) (width 0.05)) + (fp_line (start 3.7 4.58) (end -3.7 4.58) (layer B.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer B.Fab) + (effects (font (size 0.98 0.98) (thickness 0.15)) (justify mirror)) ) - (pad 1 smd roundrect (at -2.475 -3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (pad 1 smd roundrect (at -2.475 3.81 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 20 /fabric_t3)) - (pad 2 smd roundrect (at -2.475 -2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (pad 2 smd roundrect (at -2.475 2.54 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 110 /fabric_b3)) - (pad 3 smd roundrect (at -2.475 -1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (pad 3 smd roundrect (at -2.475 1.27 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 38 /fabric_b2)) - (pad 4 smd roundrect (at -2.475 0) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 21 /fabric_t2)) - (pad 5 smd roundrect (at -2.475 1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 52 /LogicBlock/cfg2)) - (pad 6 smd roundrect (at -2.475 2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 51 /LogicBlock/cfg1)) - (pad 7 smd roundrect (at -2.475 3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 1 GND)) - (pad 8 smd roundrect (at 2.475 3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 22 /fabric_t1)) - (pad 9 smd roundrect (at 2.475 2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 39 /fabric_b1)) - (pad 10 smd roundrect (at 2.475 1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 40 /fabric_b0)) - (pad 11 smd roundrect (at 2.475 0) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 23 /fabric_t0)) - (pad 12 smd roundrect (at 2.475 -1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 50 /LogicBlock/cfg0)) - (pad 13 smd roundrect (at 2.475 -2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (pad 4 smd roundrect (at -2.475 0 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 34 /fabric_l2)) + (pad 5 smd roundrect (at -2.475 -1.27 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 54 /LogicBlock/cfg4)) + (pad 6 smd roundrect (at -2.475 -2.54 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 53 /LogicBlock/cfg3)) - (pad 14 smd roundrect (at 2.475 -3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (pad 7 smd roundrect (at -2.475 -3.81 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 8 smd roundrect (at 2.475 -3.81 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 32 /fabric_l0)) + (pad 9 smd roundrect (at 2.475 -2.54 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 40 /fabric_b0)) + (pad 10 smd roundrect (at 2.475 -1.27 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 39 /fabric_b1)) + (pad 11 smd roundrect (at 2.475 0 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 33 /fabric_l1)) + (pad 12 smd roundrect (at 2.475 1.27 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 56 /LogicBlock/cfg6)) + (pad 13 smd roundrect (at 2.475 2.54 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) + (net 57 /LogicBlock/cfg7)) + (pad 14 smd roundrect (at 2.475 3.81 270) (size 1.95 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25) (net 2 VCC)) (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-14_3.9x8.7mm_P1.27mm.wrl (at (xyz 0 0 0)) @@ -3406,8 +3406,8 @@ ) ) - (module Package_SO:SOIC-14_3.9x8.7mm_P1.27mm (layer F.Cu) (tedit 5C97300E) (tstamp 5CF2E0E1) - (at 106.68 49.53) + (module Package_SO:SOIC-14_3.9x8.7mm_P1.27mm (layer F.Cu) (tedit 5C97300E) (tstamp 5CF8DDB0) + (at 102.805 50.165) (descr "SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") (tags "SOIC SO") (path /5D77FDBE/5E0E1A05) @@ -3437,31 +3437,31 @@ (pad 14 smd roundrect (at 2.475 -3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 2 VCC)) (pad 13 smd roundrect (at 2.475 -2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 54 /LogicBlock/cfg4)) + (net 52 /LogicBlock/cfg2)) (pad 12 smd roundrect (at 2.475 -1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 57 /LogicBlock/cfg7)) + (net 51 /LogicBlock/cfg1)) (pad 11 smd roundrect (at 2.475 0) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 35 /fabric_l3)) + (net 22 /fabric_t1)) (pad 10 smd roundrect (at 2.475 1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 110 /fabric_b3)) + (net 39 /fabric_b1)) (pad 9 smd roundrect (at 2.475 2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 38 /fabric_b2)) + (net 40 /fabric_b0)) (pad 8 smd roundrect (at 2.475 3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 34 /fabric_l2)) + (net 23 /fabric_t0)) (pad 7 smd roundrect (at -2.475 3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 1 GND)) (pad 6 smd roundrect (at -2.475 2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 56 /LogicBlock/cfg6)) - (pad 5 smd roundrect (at -2.475 1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) (net 55 /LogicBlock/cfg5)) + (pad 5 smd roundrect (at -2.475 1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 50 /LogicBlock/cfg0)) (pad 4 smd roundrect (at -2.475 0) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 33 /fabric_l1)) + (net 35 /fabric_l3)) (pad 3 smd roundrect (at -2.475 -1.27) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 39 /fabric_b1)) + (net 110 /fabric_b3)) (pad 2 smd roundrect (at -2.475 -2.54) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 40 /fabric_b0)) + (net 38 /fabric_b2)) (pad 1 smd roundrect (at -2.475 -3.81) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) - (net 32 /fabric_l0)) + (net 21 /fabric_t2)) (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-14_3.9x8.7mm_P1.27mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -4012,4 +4012,234 @@ (gr_line (start 208.28 91.44) (end 256.54 91.44) (layer Edge.Cuts) (width 0.05)) (gr_line (start 208.28 43.18) (end 208.28 91.44) (layer Edge.Cuts) (width 0.05)) + (segment (start 111.435 62.23) (end 110.36 62.23) (width 0.1524) (layer F.Cu) (net 20)) + (segment (start 112.28071 62.23) (end 111.435 62.23) (width 0.1524) (layer F.Cu) (net 20)) + (segment (start 112.788989 61.721721) (end 112.28071 62.23) (width 0.1524) (layer F.Cu) (net 20)) + (segment (start 112.788989 52.725609) (end 112.788989 61.721721) (width 0.1524) (layer F.Cu) (net 20)) + (segment (start 107.49788 47.4345) (end 112.788989 52.725609) (width 0.1524) (layer F.Cu) (net 20)) + (via (at 98.425 48.26) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 20)) + (segment (start 107.49788 47.010236) (end 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