electronics/ttl-fpga
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Swap L and T bus on input MUX

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This commit is contained in:
Markus Koch 2019-06-01 22:42:13 +02:00
parent 104cc9c9c9
commit 9eaef0c055
1 changed files with 26 additions and 26 deletions
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52
logic_block.sch
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@ -983,7 +983,7 @@ F 3 "" H 2450 7350 50 0001 C CNN
1 0 0 -1
$EndComp
Text Label 1500 7650 0 50 ~ 0
fabric_t3
fabric_l3
Wire Wire Line
1350 6800 1350 6900
$Comp
@ -1013,17 +1013,17 @@ F 3 "" H 2450 8150 50 0001 C CNN
1 0 0 -1
$EndComp
Text Label 1500 7250 0 50 ~ 0
fabric_l0
Text Label 1500 7550 0 50 ~ 0
fabric_t2
Text Label 1500 7350 0 50 ~ 0
fabric_t0
Text Label 1500 7550 0 50 ~ 0
fabric_l2
Text Label 1500 7350 0 50 ~ 0
fabric_l0
Text Label 1500 7750 0 50 ~ 0
fabric0
Text Label 1500 7850 0 50 ~ 0
fabric1
Text Label 1500 7450 0 50 ~ 0
fabric_t1
fabric_l1
Wire Wire Line
1500 7250 1900 7250
Wire Wire Line
@ -1167,25 +1167,25 @@ $EndComp
Text Label 1500 7950 0 50 ~ 0
fabric2
Text Label 1500 9200 0 50 ~ 0
fabric_l1
fabric_t1
Wire Wire Line
1500 9200 1900 9200
Wire Wire Line
5200 7250 4800 7250
Text Label 5200 7250 2 50 ~ 0
fabric_l2
Text Label 1500 9600 0 50 ~ 0
fabric_t3
Text Label 1500 9500 0 50 ~ 0
fabric_t2
Text Label 1500 9600 0 50 ~ 0
fabric_l3
Text Label 1500 9500 0 50 ~ 0
fabric_l2
Text Label 1500 9300 0 50 ~ 0
fabric_t0
fabric_l0
Text Label 1500 9700 0 50 ~ 0
fabric0
Text Label 1500 9800 0 50 ~ 0
fabric1
Text Label 1500 9400 0 50 ~ 0
fabric_t1
fabric_l1
Wire Wire Line
1500 9900 1900 9900
Wire Wire Line
@ -1203,17 +1203,17 @@ Wire Wire Line
Text Label 1500 9900 0 50 ~ 0
fabric2
Text Label 5200 7650 2 50 ~ 0
fabric_t3
fabric_l3
Text Label 5200 7550 2 50 ~ 0
fabric_t2
fabric_l2
Text Label 5200 7350 2 50 ~ 0
fabric_t0
fabric_l0
Text Label 5200 7750 2 50 ~ 0
fabric0
Text Label 5200 7850 2 50 ~ 0
fabric1
Text Label 5200 7450 2 50 ~ 0
fabric_t1
fabric_l1
Wire Wire Line
5200 7950 4800 7950
Wire Wire Line
@ -1231,17 +1231,17 @@ Wire Wire Line
Text Label 5200 7950 2 50 ~ 0
fabric3
Text Label 5200 9600 2 50 ~ 0
fabric_t3
fabric_l3
Text Label 5200 9500 2 50 ~ 0
fabric_t2
fabric_l2
Text Label 5200 9300 2 50 ~ 0
fabric_t0
fabric_l0
Text Label 5200 9700 2 50 ~ 0
fabric0
Text Label 5200 9800 2 50 ~ 0
fabric1
Text Label 5200 9400 2 50 ~ 0
fabric_t1
fabric_l1
Wire Wire Line
5200 9900 4800 9900
Wire Wire Line
@ -1261,7 +1261,7 @@ fabric3
Wire Wire Line
5200 9200 4800 9200
Text Label 5200 9200 2 50 ~ 0
fabric_l3
fabric_t3
Wire Wire Line
1900 6900 1500 6900
Wire Wire Line
@ -2499,6 +2499,10 @@ Wire Bus Line
13650 4450 13650 4350
Text HLabel 13650 4350 1 50 BiDi ~ 0
fabric_t[3..0]
Text Notes 2900 9400 0 50 ~ 0
LUT Input Limitations:\n* 4-bit: Never T2+T3+F3\n T0+T1+F2\n* 3-bit: Never T2+F3, T3
Text Notes 5200 9900 0 50 ~ 0
*
Wire Bus Line
13100 7850 13700 7850
Wire Bus Line
@ -2523,8 +2527,4 @@ Wire Bus Line
7750 1800 7750 4350
Wire Bus Line
5900 1800 5900 4350
Text Notes 2900 9400 0 50 ~ 0
LUT Input Limitations:\n* 4-bit: Never L2+L3+F3\n L0+L1+F2\n* 3-bit: Never L2+F3
Text Notes 5200 9900 0 50 ~ 0
*
$EndSCHEMATC