electronics/ttl-fpga
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Fix output MUX selection logic

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Fixes #15.
This commit is contained in:
Markus Koch 2019-09-13 12:55:32 +09:00
parent 7abcead6a9
commit a2abccfc5d
1 changed files with 32 additions and 17 deletions
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43
sw/kousaten/src/fpga_cell_lut34.c
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@ -43,11 +43,9 @@ static int LUT_OUT_MUX[4][4] = {
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC}, {LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A} {LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
}; };
static int LUT_OUT_BITMAP[4][2] = { static int LUT_OUT_BITMAP[2][2] = {
{27, 23}, {27, 23},
{27, 23}, /* Shared with 0 */ {25, 30}
{25, 30},
{25, 30}, /* Shared with 2 */
}; };
static int LUT_OUT_EN_N_BITMAP[4] = { static int LUT_OUT_EN_N_BITMAP[4] = {
22, 26, 31, 24 22, 26, 31, 24
@ -76,16 +74,33 @@ static int fpga_cell_lut34_lut_get_mux(int lut, char port) {
return -1; return -1;
} }
static int fpga_cell_lut34_lut_get_out_mux(int lut, char port) { static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports) {
int i; int i;
int lut;
if (port == LUT_OUT_DC || port == LUT_OUT_Z) ports = ports + lut_group;
return 255;
if (lut_group < 0 || lut_group > 2) {
report(LL_ERROR,
"Invalid LUT group requested.");
return -1;
}
lut = lut_group * 2;
report(LL_DEBUG, "port0=%c, port1=%c", ports[0], ports[1]);
for (i = 0; i < 4; ++i) { for (i = 0; i < 4; ++i) {
if (LUT_OUT_MUX[lut][i] == port) if (ports[0] == LUT_OUT_DC ||
ports[0] == LUT_OUT_Z ||
ports[0] == LUT_OUT_MUX[lut][i]) {
if (ports[1] == LUT_OUT_DC ||
ports[1] == LUT_OUT_Z ||
ports[1] == LUT_OUT_MUX[lut + 1][i])
return i; return i;
} }
}
return -1; return -1;
} }
@ -171,7 +186,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
for (i = 0; i < 4; ++i) { for (i = 0; i < 4; ++i) {
fix_bitfields(LUT_IN_BITMAP[i], 3); fix_bitfields(LUT_IN_BITMAP[i], 3);
} }
for (i = 0; i < 4; ++i) { for (i = 0; i < 2; ++i) {
fix_bitfields(LUT_OUT_BITMAP[i], 2); fix_bitfields(LUT_OUT_BITMAP[i], 2);
} }
fix_bitfields(LUT_OUT_EN_N_BITMAP, 4); fix_bitfields(LUT_OUT_EN_N_BITMAP, 4);
@ -205,8 +220,8 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
} }
/* LUT output sel + enable */ /* LUT output sel + enable */
for (i = 0; i < 4; ++i) { for (i = 0; i < 2; ++i) {
temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel[i]); temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel);
if (temp < 0) { if (temp < 0) {
report(LL_ERROR, report(LL_ERROR,
@ -216,13 +231,13 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
goto fail; goto fail;
} }
if (temp != 255) { report (LL_DEBUG, "select output sel: %d\n", temp);
BS_SET_BITS(temp, 2, LUT_OUT_BITMAP[i], BS_SET_BITS(temp, 2, LUT_OUT_BITMAP[i],
"Couldn't set LUT output sel %d for output %d.", temp, i); "Couldn't set LUT output sel %d for output %d.", temp, i);
}
} }
for (i = 0; i < 4; ++i) { for (i = 0; i < 2; ++i) {
temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */ temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp, BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
"Couldn't %s output for output %d.", "Couldn't %s output for output %d.",