Start layout
This commit is contained in:
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a2608f41ae
commit
b15d865090
@ -1012,7 +1012,7 @@ F 3 "" H 2450 8150 50 0001 C CNN
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1 2450 8150
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1 2450 8150
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1 0 0 -1
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1 0 0 -1
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$EndComp
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$EndComp
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Text Label 1500 7250 0 50 ~ 0
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Text Label 1500 7950 0 50 ~ 0
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fabric_t0
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fabric_t0
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Text Label 1500 7550 0 50 ~ 0
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Text Label 1500 7550 0 50 ~ 0
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fabric_l2
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fabric_l2
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@ -1164,27 +1164,27 @@ F 3 "" H 4250 6600 50 0001 C CNN
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1 4250 6600
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1 4250 6600
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-1 0 0 -1
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-1 0 0 -1
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$EndComp
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$EndComp
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Text Label 1500 7950 0 50 ~ 0
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Text Label 1500 7250 0 50 ~ 0
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fabric2
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fabric2
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Text Label 1500 9200 0 50 ~ 0
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Text Label 1500 9900 0 50 ~ 0
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fabric_t1
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fabric_t1
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Wire Wire Line
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Wire Wire Line
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1500 9200 1900 9200
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1500 9200 1900 9200
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Wire Wire Line
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Wire Wire Line
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5200 7250 4800 7250
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5200 7250 4800 7250
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Text Label 5200 7250 2 50 ~ 0
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Text Label 5200 7950 2 50 ~ 0
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fabric_t2
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fabric_t2
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Text Label 1500 9600 0 50 ~ 0
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Text Label 1500 9400 0 50 ~ 0
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fabric_l3
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fabric_l3
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Text Label 1500 9500 0 50 ~ 0
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Text Label 1500 9500 0 50 ~ 0
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fabric_l2
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fabric_l2
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Text Label 1500 9300 0 50 ~ 0
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fabric_l0
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Text Label 1500 9700 0 50 ~ 0
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Text Label 1500 9700 0 50 ~ 0
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fabric_l0
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Text Label 1500 9300 0 50 ~ 0
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fabric0
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fabric0
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Text Label 1500 9800 0 50 ~ 0
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Text Label 1500 9200 0 50 ~ 0
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fabric1
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fabric1
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Text Label 1500 9400 0 50 ~ 0
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Text Label 1500 9600 0 50 ~ 0
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fabric_l1
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fabric_l1
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Wire Wire Line
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Wire Wire Line
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1500 9900 1900 9900
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1500 9900 1900 9900
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@ -1200,7 +1200,7 @@ Wire Wire Line
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1500 9400 1900 9400
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1500 9400 1900 9400
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Wire Wire Line
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Wire Wire Line
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1500 9300 1900 9300
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1500 9300 1900 9300
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Text Label 1500 9900 0 50 ~ 0
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Text Label 1500 9800 0 50 ~ 0
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fabric2
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fabric2
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Text Label 5200 7650 2 50 ~ 0
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Text Label 5200 7650 2 50 ~ 0
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fabric_l3
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fabric_l3
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@ -1228,19 +1228,15 @@ Wire Wire Line
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5200 7450 4800 7450
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5200 7450 4800 7450
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Wire Wire Line
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Wire Wire Line
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5200 7350 4800 7350
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5200 7350 4800 7350
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Text Label 5200 7950 2 50 ~ 0
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Text Label 5200 7250 2 50 ~ 0
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fabric3
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fabric3
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Text Label 5200 9600 2 50 ~ 0
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Text Label 5200 9400 2 50 ~ 0
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fabric_l3
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fabric_l3
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Text Label 5200 9500 2 50 ~ 0
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Text Label 5200 9500 2 50 ~ 0
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fabric_l2
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fabric_l2
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Text Label 5200 9300 2 50 ~ 0
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fabric_l0
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Text Label 5200 9700 2 50 ~ 0
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Text Label 5200 9700 2 50 ~ 0
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fabric0
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fabric_l0
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Text Label 5200 9800 2 50 ~ 0
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Text Label 5200 9600 2 50 ~ 0
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fabric1
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Text Label 5200 9400 2 50 ~ 0
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fabric_l1
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fabric_l1
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Wire Wire Line
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Wire Wire Line
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5200 9900 4800 9900
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5200 9900 4800 9900
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@ -1256,11 +1252,11 @@ Wire Wire Line
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5200 9400 4800 9400
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5200 9400 4800 9400
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Wire Wire Line
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Wire Wire Line
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5200 9300 4800 9300
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5200 9300 4800 9300
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Text Label 5200 9900 2 50 ~ 0
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Text Label 5200 9800 2 50 ~ 0
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fabric3
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fabric3
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Wire Wire Line
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Wire Wire Line
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5200 9200 4800 9200
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5200 9200 4800 9200
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Text Label 5200 9200 2 50 ~ 0
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Text Label 5200 9900 2 50 ~ 0
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fabric_t3
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fabric_t3
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Wire Wire Line
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Wire Wire Line
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1900 6900 1500 6900
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1900 6900 1500 6900
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@ -1571,7 +1567,7 @@ Connection ~ 4050 1950
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Wire Wire Line
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Wire Wire Line
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4050 1950 4050 3150
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4050 1950 4050 3150
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Text Notes 1300 3850 0 50 ~ 0
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Text Notes 1300 3850 0 50 ~ 0
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ISP Configuration Bit Mapping:\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED _enable\n\n [30]: Synchronous mode\n [31]: LUT mode _3/4\n\n [47..32]: LUT-4 content\n [39..32]: LUT-3/A\n [47..40]: LUT-3/B
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ISP Configuration Bit Mapping:\n -- OUT OF DATE --\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED _enable\n\n [30]: Synchronous mode\n [31]: LUT mode _3/4\n\n [47..32]: LUT-4 content\n [39..32]: LUT-3/A\n [47..40]: LUT-3/B
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Wire Wire Line
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Wire Wire Line
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1650 2100 3800 2100
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1650 2100 3800 2100
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Wire Wire Line
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Wire Wire Line
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@ -2435,7 +2431,7 @@ Wire Wire Line
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10250 8250 10600 8250
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10250 8250 10600 8250
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Wire Wire Line
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Wire Wire Line
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9850 8250 9950 8250
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9850 8250 9950 8250
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Text Notes 5200 7950 0 50 ~ 0
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Text Notes 5200 7250 0 50 ~ 0
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*
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*
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Text Label 14350 7750 1 50 Italic 0
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Text Label 14350 7750 1 50 Italic 0
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fabric_b3
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fabric_b3
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@ -2447,10 +2443,6 @@ Text Label 13000 7750 1 50 Italic 0
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fabric_b0
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fabric_b0
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Text Label 14650 6050 0 50 Italic 0
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Text Label 14650 6050 0 50 Italic 0
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fabric_r0
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fabric_r0
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Wire Wire Line
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14350 6050 14350 5600
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Wire Wire Line
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14350 7400 14350 6050
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Wire Wire Line
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Wire Wire Line
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14650 6500 13450 6500
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14650 6500 13450 6500
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Wire Wire Line
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Wire Wire Line
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@ -2461,7 +2453,6 @@ Text Label 14650 6950 0 50 Italic 0
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fabric_r2
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fabric_r2
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Text Label 14650 7400 0 50 Italic 0
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Text Label 14650 7400 0 50 Italic 0
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fabric_r3
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fabric_r3
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Connection ~ 14350 6050
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Wire Wire Line
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Wire Wire Line
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14350 6050 14650 6050
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14350 6050 14650 6050
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$Sheet
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$Sheet
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@ -2501,8 +2492,14 @@ Text HLabel 13650 4350 1 50 BiDi ~ 0
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fabric_t[3..0]
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fabric_t[3..0]
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Text Notes 2900 9400 0 50 ~ 0
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Text Notes 2900 9400 0 50 ~ 0
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LUT Input Limitations:\n* 4-bit: Never T2+T3+F3\n T0+T1+F2\n* 3-bit: Never T2+F3, T3
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LUT Input Limitations:\n* 4-bit: Never T2+T3+F3\n T0+T1+F2\n* 3-bit: Never T2+F3, T3
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Text Notes 5200 9900 0 50 ~ 0
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Text Notes 5200 9800 0 50 ~ 0
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*
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*
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Text Label 5200 9300 2 50 ~ 0
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fabric0
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Text Label 5200 9200 2 50 ~ 0
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fabric1
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Wire Wire Line
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14350 5600 14350 7400
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Wire Bus Line
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Wire Bus Line
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13100 7850 13700 7850
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13100 7850 13700 7850
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Wire Bus Line
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Wire Bus Line
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4015
kicad_pcb/ttl-fpga.kicad_pcb
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4015
kicad_pcb/ttl-fpga.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
@ -581,14 +581,6 @@ F 3 "" H 3550 5400 50 0001 C CNN
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1 3550 5400
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1 3550 5400
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1 0 0 -1
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1 0 0 -1
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$EndComp
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$EndComp
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Wire Bus Line
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6150 2600 6900 2600
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Wire Bus Line
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6150 5050 6900 5050
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Wire Bus Line
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3900 4250 3900 4550
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Wire Bus Line
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7450 4250 7450 4550
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Wire Wire Line
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Wire Wire Line
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4150 5350 4150 5400
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4150 5350 4150 5400
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$Comp
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$Comp
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@ -602,4 +594,12 @@ F 3 "" H 4150 5400 50 0001 C CNN
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1 4150 5400
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1 4150 5400
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1 0 0 -1
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1 0 0 -1
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$EndComp
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$EndComp
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Wire Bus Line
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7450 4250 7450 4550
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Wire Bus Line
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3900 4250 3900 4550
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Wire Bus Line
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6150 2600 6900 2600
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Wire Bus Line
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6150 5050 6900 5050
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$EndSCHEMATC
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$EndSCHEMATC
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