From bf55a828a8b7cade55d62264b9c3eac7893978ce Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Thu, 30 May 2019 21:12:52 +0200 Subject: [PATCH] Fix LUT split enable logic --- logic_block.sch | 57 +++++------ lutd.sch | 168 ++++++++++++++++++++----------- sym-lib-table | 3 + ttl-fpga-cache.lib | 19 ++++ ttl-fpga-rescue.dcm | 3 + ttl-fpga-rescue.lib | 236 ++++++++++++++++++++++++++++++++++++++++++++ ttl-fpga.sch | 1 + 7 files changed, 401 insertions(+), 86 deletions(-) create mode 100644 sym-lib-table create mode 100644 ttl-fpga-rescue.dcm create mode 100644 ttl-fpga-rescue.lib diff --git a/logic_block.sch b/logic_block.sch index 2aace03..b5e155e 100644 --- a/logic_block.sch +++ b/logic_block.sch @@ -1,4 +1,5 @@ EESchema Schematic File Version 4 +LIBS:ttl-fpga-cache EELAYER 29 0 EELAYER END $Descr A4 11693 8268 @@ -1669,34 +1670,6 @@ F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 5100 1100 50 0001 C CNN 5 5100 1100 1 0 0 -1 $EndComp -Wire Bus Line - 10500 3000 10500 3550 -Wire Bus Line - 10500 3550 10500 4150 -Wire Bus Line - 6300 3600 6300 4150 -Wire Bus Line - 6300 3000 6300 3600 -Wire Bus Line - 7800 1300 8350 1300 -Wire Bus Line - 8350 1300 8950 1300 -Wire Bus Line - 8400 5750 8950 5750 -Wire Bus Line - 7800 5750 8400 5750 -Wire Bus Line - 1600 4950 1600 5500 -Wire Bus Line - 2400 3900 2400 4850 -Wire Bus Line - 1600 5500 1600 7650 -Wire Bus Line - 4750 3900 4750 7300 -Wire Bus Line - 2400 1200 2400 3900 -Wire Bus Line - 4250 1200 4250 3900 $Comp L 4xxx:4066 U? U 5 1 5E0E0FAE @@ -1736,4 +1709,32 @@ F 3 "http://www.ti.com/lit/ds/symlink/cd4066b.pdf" H 6450 1100 50 0001 C CNN 5 6450 1100 1 0 0 -1 $EndComp +Wire Bus Line + 10500 3000 10500 3550 +Wire Bus Line + 10500 3550 10500 4150 +Wire Bus Line + 6300 3600 6300 4150 +Wire Bus Line + 6300 3000 6300 3600 +Wire Bus Line + 7800 1300 8350 1300 +Wire Bus Line + 8350 1300 8950 1300 +Wire Bus Line + 8400 5750 8950 5750 +Wire Bus Line + 7800 5750 8400 5750 +Wire Bus Line + 1600 4950 1600 5500 +Wire Bus Line + 2400 3900 2400 4850 +Wire Bus Line + 1600 5500 1600 7650 +Wire Bus Line + 4750 3900 4750 7300 +Wire Bus Line + 2400 1200 2400 3900 +Wire Bus Line + 4250 1200 4250 3900 $EndSCHEMATC diff --git a/lutd.sch b/lutd.sch index 7a75952..64be3a7 100644 --- a/lutd.sch +++ b/lutd.sch @@ -1,4 +1,5 @@ EESchema Schematic File Version 4 +LIBS:ttl-fpga-cache EELAYER 29 0 EELAYER END $Descr A4 11693 8268 @@ -236,12 +237,10 @@ Wire Wire Line Connection ~ 6200 4400 Wire Wire Line 4250 4650 3950 4650 -Entry Wire Line - 3850 4550 3950 4650 Text Label 3950 4650 0 50 ~ 0 -lut_in3 +lut_b_en_n Wire Wire Line - 3950 3100 4250 3100 + 4150 3100 4250 3100 Text Label 8150 3850 0 50 ~ 0 cfg_sync Wire Wire Line @@ -416,31 +415,29 @@ B $Comp L Device:Q_NPN_BCE Q? U 1 1 5D215162 -P 3700 2150 +P 3700 1750 AR Path="/5CF41639/5D215162" Ref="Q?" Part="1" AR Path="/5D77FDBE/5D7AF013/5D215162" Ref="Q?" Part="1" -F 0 "Q?" H 3891 2196 50 0000 L CNN -F 1 "Q_NPN_BCE" H 3891 2105 50 0000 L CNN -F 2 "" H 3900 2250 50 0001 C CNN -F 3 "~" H 3700 2150 50 0001 C CNN - 1 3700 2150 +F 0 "Q?" H 3891 1796 50 0000 L CNN +F 1 "Q_NPN_BCE" H 3891 1705 50 0000 L CNN +F 2 "" H 3900 1850 50 0001 C CNN +F 3 "~" H 3700 1750 50 0001 C CNN + 1 3700 1750 1 0 0 -1 $EndComp $Comp L Device:R R? U 1 1 5D21734D -P 3800 1700 +P 3800 1250 AR Path="/5CF41639/5D21734D" Ref="R?" Part="1" AR Path="/5D77FDBE/5D7AF013/5D21734D" Ref="R?" Part="1" -F 0 "R?" H 3730 1654 50 0000 R CNN -F 1 "10k" H 3730 1745 50 0000 R CNN -F 2 "" V 3730 1700 50 0001 C CNN -F 3 "~" H 3800 1700 50 0001 C CNN - 1 3800 1700 +F 0 "R?" H 3730 1204 50 0000 R CNN +F 1 "10k" H 3730 1295 50 0000 R CNN +F 2 "" V 3730 1250 50 0001 C CNN +F 3 "~" H 3800 1250 50 0001 C CNN + 1 3800 1250 1 0 0 1 $EndComp -Wire Wire Line - 3800 1850 3800 1900 $Comp L power:GNDD #PWR? U 1 1 5D2296E9 @@ -455,31 +452,11 @@ F 3 "" H 3800 2450 50 0001 C CNN 1 0 0 -1 $EndComp Wire Wire Line - 3800 2450 3800 2350 -Wire Wire Line - 3800 1550 3800 1450 -$Comp -L power:VCC #PWR? -U 1 1 5D22E805 -P 3800 1450 -AR Path="/5CF41639/5D22E805" Ref="#PWR?" Part="1" -AR Path="/5D77FDBE/5D7AF013/5D22E805" Ref="#PWR?" Part="1" -F 0 "#PWR?" H 3800 1300 50 0001 C CNN -F 1 "VCC" H 3817 1623 50 0000 C CNN -F 2 "" H 3800 1450 50 0001 C CNN -F 3 "" H 3800 1450 50 0001 C CNN - 1 3800 1450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 1900 3800 1900 -Connection ~ 3800 1900 -Wire Wire Line - 3800 1900 3800 1950 + 3800 2450 3800 1950 Entry Wire Line 2900 2700 3000 2600 Wire Wire Line - 3000 2600 3000 2150 + 3000 2600 3000 1750 Text Label 3000 2600 1 50 ~ 0 lut_in3 Wire Wire Line @@ -673,8 +650,8 @@ F 3 "" H 3300 4550 50 0001 C CNN $EndComp Wire Wire Line 3300 4550 3300 4650 -Text Label 3950 3100 0 50 ~ 0 -lut_in3_n +Text Label 3900 1500 0 50 ~ 0 +lut_a_en_n Wire Wire Line 8100 900 8100 3850 Wire Wire Line @@ -694,33 +671,108 @@ Wire Wire Line Text HLabel 2000 1000 0 50 Input ~ 0 cfg_split_n Wire Wire Line - 2000 1000 3950 1000 -Wire Wire Line - 3950 1000 3950 1900 -Connection ~ 3950 1900 -Wire Wire Line - 3950 1900 3950 3100 + 2000 1000 2200 1000 $Comp L Device:R R? U 1 1 5D748DEE -P 3250 2150 +P 3250 1750 AR Path="/5CF41639/5D748DEE" Ref="R?" Part="1" AR Path="/5D77FDBE/5D7AF013/5D748DEE" Ref="R?" Part="1" -F 0 "R?" V 3043 2150 50 0000 C CNN -F 1 "10k" V 3134 2150 50 0000 C CNN -F 2 "" V 3180 2150 50 0001 C CNN -F 3 "~" H 3250 2150 50 0001 C CNN - 1 3250 2150 +F 0 "R?" V 3043 1750 50 0000 C CNN +F 1 "10k" V 3134 1750 50 0000 C CNN +F 2 "" V 3180 1750 50 0001 C CNN +F 3 "~" H 3250 1750 50 0001 C CNN + 1 3250 1750 0 -1 1 0 $EndComp Wire Wire Line - 3100 2150 3000 2150 + 3100 1750 3000 1750 Wire Wire Line - 3400 2150 3500 2150 + 3400 1750 3500 1750 +Wire Wire Line + 3800 1400 3800 1500 +Wire Wire Line + 4150 1500 3800 1500 +Wire Wire Line + 4150 1500 4150 3100 +Connection ~ 3800 1500 +Wire Wire Line + 3800 1500 3800 1550 +Wire Wire Line + 3800 1000 3800 1100 +$Comp +L Device:R R? +U 1 1 5CF7FFE1 +P 2750 1750 +AR Path="/5CF41639/5CF7FFE1" Ref="R?" Part="1" +AR Path="/5D77FDBE/5D7AF013/5CF7FFE1" Ref="R?" Part="1" +F 0 "R?" V 2543 1750 50 0000 C CNN +F 1 "10k" V 2634 1750 50 0000 C CNN +F 2 "" V 2680 1750 50 0001 C CNN +F 3 "~" H 2750 1750 50 0001 C CNN + 1 2750 1750 + 0 -1 1 0 +$EndComp +Wire Wire Line + 2900 1750 3000 1750 +Connection ~ 3000 1750 +$Comp +L Device:R R? +U 1 1 5CF89787 +P 2200 2200 +AR Path="/5CF41639/5CF89787" Ref="R?" Part="1" +AR Path="/5D77FDBE/5D7AF013/5CF89787" Ref="R?" Part="1" +F 0 "R?" H 2130 2154 50 0000 R CNN +F 1 "10k" H 2130 2245 50 0000 R CNN +F 2 "" V 2130 2200 50 0001 C CNN +F 3 "~" H 2200 2200 50 0001 C CNN + 1 2200 2200 + 1 0 0 1 +$EndComp +Wire Wire Line + 2200 1550 2200 1000 +Connection ~ 2200 1000 +Wire Wire Line + 2200 1000 3800 1000 +$Comp +L power:GNDD #PWR? +U 1 1 5CF9E825 +P 2200 2450 +AR Path="/5CF41639/5CF9E825" Ref="#PWR?" Part="1" +AR Path="/5D77FDBE/5D7AF013/5CF9E825" Ref="#PWR?" Part="1" +F 0 "#PWR?" H 2200 2200 50 0001 C CNN +F 1 "GNDD" H 2204 2295 50 0000 C CNN +F 2 "" H 2200 2450 50 0001 C CNN +F 3 "" H 2200 2450 50 0001 C CNN + 1 2200 2450 + 1 0 0 -1 +$EndComp +$Comp +L Device:Q_PNP_BCE Q? +U 1 1 5CFA4AF5 +P 2300 1750 +F 0 "Q?" H 2491 1704 50 0000 L CNN +F 1 "Q_PNP_BCE" H 2491 1795 50 0000 L CNN +F 2 "" H 2500 1850 50 0001 C CNN +F 3 "~" H 2300 1750 50 0001 C CNN + 1 2300 1750 + -1 0 0 1 +$EndComp +Wire Wire Line + 2200 2350 2200 2450 +Wire Wire Line + 2600 1750 2500 1750 Wire Bus Line 2000 2700 3850 2700 Wire Bus Line 3850 2700 3850 4950 -Text Notes 1850 1250 0 50 ~ 0 -TODO: MUX B needs to be\npermanently enabled for split mode +Wire Wire Line + 2200 2000 2200 2050 +Wire Wire Line + 2200 1950 2200 2000 +Connection ~ 2200 2000 +Wire Wire Line + 2200 2000 1750 2000 +Text Label 1750 2000 0 50 ~ 0 +lut_b_en_n $EndSCHEMATC diff --git a/sym-lib-table b/sym-lib-table new file mode 100644 index 0000000..0376b79 --- /dev/null +++ b/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name ttl-fpga-rescue)(type Legacy)(uri ${KIPRJMOD}/ttl-fpga-rescue.lib)(options "")(descr "")) +) diff --git a/ttl-fpga-cache.lib b/ttl-fpga-cache.lib index eeb66e2..1f14b1f 100644 --- a/ttl-fpga-cache.lib +++ b/ttl-fpga-cache.lib @@ -248,6 +248,25 @@ X E 3 100 -200 100 U 50 50 1 1 P ENDDRAW ENDDEF # +# Device_Q_PNP_BCE +# +DEF Device_Q_PNP_BCE Q 0 0 Y N 1 F N +F0 "Q" 200 50 50 H V L CNN +F1 "Device_Q_PNP_BCE" 200 -50 50 H V L CNN +F2 "" 200 100 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X B 1 -200 0 225 R 50 50 1 1 I +X C 2 100 200 100 D 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# # Device_R # DEF Device_R R 0 0 N Y 1 F N diff --git a/ttl-fpga-rescue.dcm b/ttl-fpga-rescue.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/ttl-fpga-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/ttl-fpga-rescue.lib b/ttl-fpga-rescue.lib new file mode 100644 index 0000000..7008adb --- /dev/null +++ b/ttl-fpga-rescue.lib @@ -0,0 +1,236 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# 4066-4xxx +# +DEF 4066-4xxx U 0 40 Y Y 5 L N +F0 "U" -300 350 50 H V C CNN +F1 "4066-4xxx" -300 -350 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + DIP?14* +$ENDFPLIST +DRAW +S -200 300 200 -300 5 1 10 f +P 2 1 0 6 0 50 0 100 N +P 4 1 0 0 -100 0 100 100 100 -100 -100 0 f +P 4 1 0 0 -100 100 100 0 -100 -100 -100 100 f +P 2 2 0 6 0 50 0 100 N +P 4 2 0 0 -100 0 100 100 100 -100 -100 0 f +P 4 2 0 0 -100 100 100 0 -100 -100 -100 100 f +P 2 3 0 6 0 50 0 100 N +P 4 3 0 0 -100 0 100 100 100 -100 -100 0 f +P 4 3 0 0 -100 100 100 0 -100 -100 -100 100 f +P 2 4 0 6 0 50 0 100 N +P 4 4 0 0 -100 0 100 100 100 -100 -100 0 f +P 4 4 0 0 -100 100 100 0 -100 -100 -100 100 f +X ~ 1 -300 0 200 R 50 50 1 0 P +X ~ 13 0 300 200 D 50 50 1 0 I +X ~ 2 300 0 200 L 50 50 1 0 P +X ~ 3 300 0 200 L 50 50 2 0 P +X ~ 4 -300 0 200 R 50 50 2 0 P +X ~ 5 0 300 200 D 50 50 2 0 I +X ~ 6 0 300 200 D 50 50 3 0 I +X ~ 8 -300 0 200 R 50 50 3 0 P +X ~ 9 300 0 200 L 50 50 3 0 P +X ~ 10 300 0 200 L 50 50 4 0 P +X ~ 11 -300 0 200 R 50 50 4 0 P +X ~ 12 0 300 200 D 50 50 4 0 I +X VDD 14 0 500 200 D 50 50 5 0 W +X VSS 7 0 -500 200 U 50 50 5 0 W +ENDDRAW +ENDDEF +# +# 74157-74xx_IEEE +# +DEF 74157-74xx_IEEE U 0 30 Y Y 1 F N +F0 "U" 300 400 50 H V C CNN +F1 "74157-74xx_IEEE" 250 -650 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +T 0 0 100 60 0 0 0 MUX Normal 0 C C +S -250 -400 250 -600 0 0 0 N +S -250 -200 250 -400 0 0 0 N +S -250 0 250 -200 0 0 0 N +S -250 200 250 0 0 0 0 N +P 9 0 0 0 -200 200 -200 250 -250 250 -250 500 250 500 250 250 200 250 200 200 200 200 N +X VCC 16 150 500 0 D 50 50 0 0 W N +X GND 8 0 500 0 D 50 50 0 0 W N +X A/B 1 -550 300 300 R 50 50 1 1 I +X I1d 10 -550 -550 300 R 50 50 1 1 I +X I0d 11 -550 -450 300 R 50 50 1 1 I +X Qc 12 550 -300 300 L 50 50 1 1 O +X I1c 13 -550 -350 300 R 50 50 1 1 I +X I0c 14 -550 -250 300 R 50 50 1 1 I +X ~EN 15 -550 400 300 R 50 50 1 1 I I +X I0a 2 -550 150 300 R 50 50 1 1 I +X I1a 3 -550 50 300 R 50 50 1 1 I +X Qa 4 550 100 300 L 50 50 1 1 O +X I0b 5 -550 -50 300 R 50 50 1 1 I +X I1b 6 -550 -150 300 R 50 50 1 1 I +X Qb 7 550 -100 300 L 50 50 1 1 O +X Qd 9 550 -500 300 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74164-74xx_IEEE +# +DEF 74164-74xx_IEEE U 0 30 Y Y 1 F N +F0 "U" 350 250 50 H V C CNN +F1 "74164-74xx_IEEE" 250 -900 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +T 0 -170 -40 60 0 0 0 & Normal 0 C C +S -250 -750 250 -850 0 1 0 N +S -250 -650 250 -750 0 1 0 N +S -250 -550 250 -650 0 1 0 N +S -250 -450 250 -550 0 1 0 N +S -250 -350 250 -450 0 1 0 N +S -250 -250 250 -350 0 1 0 N +S -250 -150 250 -250 0 1 0 N +S -250 50 250 -150 0 1 0 N +P 3 0 1 0 -100 50 -100 -150 -100 -150 N +P 9 0 1 0 -200 50 -200 100 -250 100 -250 350 250 350 250 100 200 100 200 50 200 50 N +X A 1 -550 0 300 R 50 50 1 1 I +X Qe 10 550 -500 300 L 50 50 1 1 O +X Qf 11 550 -600 300 L 50 50 1 1 O +X Qg 12 550 -700 300 L 50 50 1 1 O +X Qh 13 550 -800 300 L 50 50 1 1 O +X Vdd 14 200 350 0 D 50 50 1 1 W N +X B 2 -550 -100 300 R 50 50 1 1 I +X Qa 3 550 -50 300 L 50 50 1 1 O +X Qb 4 550 -200 300 L 50 50 1 1 O +X Qc 5 550 -300 300 L 50 50 1 1 O +X Qd 6 550 -400 300 L 50 50 1 1 O +X Vss 7 0 350 0 D 50 50 1 1 W N +X CK 8 -550 150 300 R 50 50 1 1 I C +X ~R 9 -550 250 300 R 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# 74251-74xx_IEEE +# +DEF 74251-74xx_IEEE U 0 30 Y Y 1 F N +F0 "U" 300 600 50 H V C CNN +F1 "74251-74xx_IEEE" 350 -800 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +T 0 0 250 50 0 0 0 MUX Normal 0 C C +S -250 650 250 -700 0 0 0 N +P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N +P 5 0 0 0 80 380 20 380 50 320 80 380 80 380 N +X VCC 16 0 650 0 D 50 50 0 0 W N +X GND 8 0 -700 0 U 50 50 0 0 W N +X I3 1 -550 -200 300 R 50 50 1 1 I +X S1 10 -550 350 300 R 50 50 1 1 I +X S0 11 -550 450 300 R 50 50 1 1 I +X I7 12 -550 -600 300 R 50 50 1 1 I +X I6 13 -550 -500 300 R 50 50 1 1 I +X I5 14 -550 -400 300 R 50 50 1 1 I +X I4 15 -550 -300 300 R 50 50 1 1 I +X I2 2 -550 -100 300 R 50 50 1 1 I +X I1 3 -550 0 300 R 50 50 1 1 I +X I0 4 -550 100 300 R 50 50 1 1 I +X Q 5 550 350 300 L 50 50 1 1 T +X ~Q 6 550 -350 300 L 50 50 1 1 T I +X ~E 7 -550 550 300 R 50 50 1 1 I I +X S2 9 -550 250 300 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 74253-74xx_IEEE +# +DEF 74253-74xx_IEEE U 0 30 Y Y 1 F N +F0 "U" 300 650 50 H V C CNN +F1 "74253-74xx_IEEE" 150 -650 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +T 0 0 300 60 0 0 0 MUX Normal 0 C C +S -250 -100 250 -600 0 0 0 N +S -250 450 250 -100 0 0 0 N +P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N +P 5 0 0 0 80 180 20 180 50 120 80 180 80 180 N +P 9 0 0 0 -200 450 -200 500 -250 500 -250 750 250 750 250 500 200 500 200 450 200 450 N +X VCC 16 150 750 0 D 50 50 0 0 W N +X GND 8 0 750 0 D 50 50 0 0 W N +X ~ENa 1 -550 350 300 R 50 50 1 1 I I +X I0b 10 -550 -250 300 R 50 50 1 1 I +X I1b 11 -550 -350 300 R 50 50 1 1 I +X I2b 12 -550 -450 300 R 50 50 1 1 I +X I3b 13 -550 -550 300 R 50 50 1 1 I +X A 14 -550 650 300 R 50 50 1 1 I +X ~ENb 15 -550 -150 300 R 50 50 1 1 I I +X B 2 -550 550 300 R 50 50 1 1 I +X I3a 3 -550 -50 300 R 50 50 1 1 I +X I2a 4 -550 50 300 R 50 50 1 1 I +X I1a 5 -550 150 300 R 50 50 1 1 I +X I0a 6 -550 250 300 R 50 50 1 1 I +X Qa 7 550 150 300 L 50 50 1 1 T +X Qb 9 550 -350 300 L 50 50 1 1 T +ENDDRAW +ENDDEF +# +# D_ALT-Device +# +DEF D_ALT-Device D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "D_ALT-Device" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 50 -50 -50 N +P 2 0 1 0 50 0 -50 0 N +P 4 0 1 8 50 50 50 -50 -50 0 50 50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Q_NPN_BCE-Device +# +DEF Q_NPN_BCE-Device Q 0 0 Y N 1 F N +F0 "Q" 200 50 50 H V L CNN +F1 "Q_NPN_BCE-Device" 200 -50 50 H V L CNN +F2 "" 200 100 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X B 1 -200 0 225 R 50 50 1 1 I +X C 2 100 200 100 D 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R-Device +# +DEF R-Device R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R-Device" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/ttl-fpga.sch b/ttl-fpga.sch index 589f717..f6b4e7b 100644 --- a/ttl-fpga.sch +++ b/ttl-fpga.sch @@ -1,4 +1,5 @@ EESchema Schematic File Version 4 +LIBS:ttl-fpga-cache EELAYER 29 0 EELAYER END $Descr A4 11693 8268