Implement ISP chain walker
This commit is contained in:
parent
cf80ff7b6b
commit
d0fed3cce4
23
sw/kousaten/src/fpga.c
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23
sw/kousaten/src/fpga.c
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@ -0,0 +1,23 @@
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#include "fpga.h"
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#include "fpga_global.h"
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int fpga_generate_bitstream(struct fpga_cell *cell)
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{
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struct fpga_cell *current_cell = cell;
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enum fpga_isp_channel current_channel = FPGA_ISP_CHANNEL_NORMAL;
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while (current_cell) {
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report(LL_DEBUG,
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"Adding %p (%c) to ISP chain.",
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current_cell, current_cell->type->identifier);
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current_cell = current_cell->type->get_next_isp(current_cell,
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¤t_channel);
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if (current_channel == FPGA_ISP_CHANNEL_ERROR)
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return 1;
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}
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report(LL_INFO,
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"Bitstream generation finished.");
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return 0;
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}
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7
sw/kousaten/src/fpga.h
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7
sw/kousaten/src/fpga.h
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@ -0,0 +1,7 @@
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#ifndef FPGA_H
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#define FPGA_H
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#include "fpga_cell.h"
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int fpga_generate_bitstream(struct fpga_cell *cell);
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#endif // FPGA_H
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@ -1,21 +1,57 @@
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#include "fpga_cell.h"
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#include "fpga_cell.h"
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#include "fpga_global.h"
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#include "fpga_global.h"
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#include <stddef.h>
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#include "fpga_cell_lut34.h"
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#include "fpga_cell_none.h"
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#include "fpga_cell_wire.h"
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void fpga_cell_init(struct fpga_cell *fpga_cell,
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static struct fpga_cell_type fpga_cell_list[] = {
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enum fpga_cell_type fpga_cell_type)
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{
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.identifier = ' ',
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.cell_new = fpga_cell_none_new,
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.get_next_isp = fpga_cell_none_get_next_isp
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},
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{
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.identifier = '[',
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.cell_new = fpga_cell_wire_new,
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.get_next_isp = fpga_cell_wire_get_next_isp
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},
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{
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.identifier = ']',
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.cell_new = fpga_cell_wire_new,
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.get_next_isp = fpga_cell_wire_get_next_isp
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},
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{
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.identifier = 'P',
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.cell_new = fpga_cell_wire_new,
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.get_next_isp = fpga_cell_wire_get_next_isp
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},
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{
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.identifier = 'L',
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.cell_new = fpga_cell_lut34_new,
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.get_next_isp = fpga_cell_lut34_get_next_isp
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},
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{
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.identifier = '\0',
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.cell_new = NULL,
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.get_next_isp = NULL
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}
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};
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void fpga_cell_init(struct fpga_cell *cell,
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struct fpga_cell_type *cell_type)
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{
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{
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int i;
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int i;
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for (i = 0; i < FPGA_CELL_CONNECTION_COUNT; ++i) {
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for (i = 0; i < FPGA_CELL_CONNECTION_COUNT; ++i) {
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fpga_cell->cell_connections[i] = NULL;
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cell->cell_connections[i] = NULL;
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}
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}
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fpga_cell->type = fpga_cell_type;
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cell->type = cell_type;
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//fpga_cell->get_next_isp = fpga_cell_get_next_isp_dummy;
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report(LL_DEBUG,
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report(LL_DEBUG,
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"Initialized cell of type %d at %p.",
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"Initialized cell of type %d at %p.",
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fpga_cell_type, fpga_cell);
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cell_type, cell);
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}
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}
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enum fpga_cell_position fpga_cell_connection_opposing(enum fpga_cell_position position)
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enum fpga_cell_position fpga_cell_connection_opposing(enum fpga_cell_position position)
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@ -84,3 +120,52 @@ struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell,
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return next;
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return next;
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}
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}
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/**
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* @brief fpga_cell_get_next_isp Get the next cell in the ISP chain
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* @param fpga_cell the current cell in the ISP chain
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* @param isp_channel the current channel. This will be updated when calling this function!
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* @return the next ISP cell
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*/
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struct fpga_cell *fpga_cell_get_next_isp_dummy(struct fpga_cell *cell,
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enum fpga_isp_channel *isp_channel)
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{
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report(LL_CRITICAL,
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"Internal error. Cell type %c does not implement get_next_isp!",
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cell->type->identifier);
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*isp_channel = FPGA_ISP_CHANNEL_ERROR;
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return NULL;
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}
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/**
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* @brief fpga_cell_new Create a new instance of type <identifier>
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* @param identifier
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* @return
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*/
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struct fpga_cell *fpga_cell_new(char identifier)
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{
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struct fpga_cell_type *cell_type = fpga_cell_list;
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struct fpga_cell *cell = NULL;
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while (cell_type->identifier) {
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if (identifier == cell_type->identifier) {
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cell = cell_type->cell_new();
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if (!cell) {
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report(LL_CRITICAL,
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"Out of memory when creating cell.");
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return NULL;
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}
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cell->type = cell_type;
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report(LL_DEBUG,
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"Created cell %p of type %c.",
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cell, identifier);
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return cell;
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}
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cell_type++;
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}
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report(LL_ERROR,
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"Invalid cell type %c found in FDEF.",
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identifier);
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return NULL;
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}
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@ -1,5 +1,6 @@
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#ifndef FPGA_CELL_H
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#ifndef FPGA_CELL_H
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#define FPGA_CELL_H
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#define FPGA_CELL_H
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#include <stddef.h>
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enum fpga_cell_position {
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enum fpga_cell_position {
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LEFT = 0,
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LEFT = 0,
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@ -9,30 +10,43 @@ enum fpga_cell_position {
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FPGA_CELL_CONNECTION_COUNT
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FPGA_CELL_CONNECTION_COUNT
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};
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};
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enum fpga_cell_type {
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enum fpga_isp_channel {
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FPGA_CELL_NONE = 0,
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FPGA_ISP_CHANNEL_NORMAL = 0,
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FPGA_CELL_WIRE,
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FPGA_ISP_CHANNEL_BACK,
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FPGA_CELL_LUT34
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FPGA_ISP_CHANNEL_LFDN,
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FPGA_ISP_CHANNEL_DNUP,
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FPGA_ISP_CHANNEL_ERROR
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};
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struct fpga_cell_type
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{
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char identifier;
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struct fpga_cell *(*cell_new)();
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struct fpga_cell *(*get_next_isp)(struct fpga_cell *cell,
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enum fpga_isp_channel *isp_channel);
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};
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};
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/* FPGA Logic cell base parameters */
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/* FPGA Logic cell base parameters */
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struct fpga_cell
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struct fpga_cell
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{
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{
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enum fpga_cell_type type;
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struct fpga_cell_type *type;
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struct fpga_cell *cell_connections[FPGA_CELL_CONNECTION_COUNT];
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struct fpga_cell *cell_connections[FPGA_CELL_CONNECTION_COUNT];
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/* Cell-specific data will be appended depending on the cell type. */
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/* Cell-specific data will be appended depending on the cell type. */
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};
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};
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void fpga_cell_init(struct fpga_cell *fpga_cell,
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void fpga_cell_init(struct fpga_cell *cell,
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enum fpga_cell_type fpga_cell_type);
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struct fpga_cell_type *cell_type);
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int fpga_cell_connect(struct fpga_cell *fpga_cell,
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int fpga_cell_connect(struct fpga_cell *fpga_cell,
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struct fpga_cell *target_cell,
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struct fpga_cell *target_cell,
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enum fpga_cell_position position);
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enum fpga_cell_position position);
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struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell,
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struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell,
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enum fpga_cell_position position);
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enum fpga_cell_position position);
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struct fpga_cell *fpga_cell_get_next_isp_dummy(struct fpga_cell *fpga_cell,
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enum fpga_isp_channel *isp_channel);
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struct fpga_cell *fpga_cell_new(char identifier);
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#define FPGA_TO_CELL(a) ((struct fpga_cell*) a)
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#define FPGA_TO_CELL(a) ((struct fpga_cell*) a)
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#endif // FPGA_CELL_H
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#endif // FPGA_CELL_H
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@ -1,15 +1,32 @@
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#include "fpga_cell_lut34.h"
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#include "fpga_cell_lut34.h"
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#include "fpga_global.h"
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#include <stdlib.h>
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#include <stdlib.h>
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struct fpga_cell_lut34 *fpga_cell_lut_34_new()
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struct fpga_cell *fpga_cell_lut34_new()
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{
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{
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struct fpga_cell_lut34 *fpga_cell_lut_34;
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struct fpga_cell_lut34 *fpga_cell_lut_34;
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fpga_cell_lut_34 = malloc(sizeof(struct fpga_cell_lut34));
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fpga_cell_lut_34 = malloc(sizeof(struct fpga_cell_lut34));
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if (fpga_cell_lut_34) {
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fpga_cell_init(FPGA_TO_CELL(fpga_cell_lut_34),
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FPGA_CELL_LUT34);
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}
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return fpga_cell_lut_34;
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return FPGA_TO_CELL(fpga_cell_lut_34);
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}
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struct fpga_cell *fpga_cell_lut34_get_next_isp(struct fpga_cell *cell,
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enum fpga_isp_channel *isp_channel)
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{
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switch (*isp_channel) {
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case FPGA_ISP_CHANNEL_LFDN:
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*isp_channel = FPGA_ISP_CHANNEL_NORMAL;
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return cell->cell_connections[BOTTOM];
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case FPGA_ISP_CHANNEL_NORMAL:
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return cell->cell_connections[RIGHT];
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case FPGA_ISP_CHANNEL_BACK:
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return cell->cell_connections[LEFT];
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default:
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report(LL_ERROR,
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"Unhandled ISP channel %d for LUT34.",
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*isp_channel);
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}
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return NULL;
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}
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}
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@ -23,6 +23,8 @@ struct fpga_cell_lut34 {
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enum lut_mode lut_mode; /* Look-up table mode selection */
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enum lut_mode lut_mode; /* Look-up table mode selection */
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};
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};
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struct fpga_cell_lut34 *fpga_cell_lut_34_new();
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struct fpga_cell *fpga_cell_lut34_new();
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struct fpga_cell *fpga_cell_lut34_get_next_isp(struct fpga_cell *cell,
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enum fpga_isp_channel *isp_channel);
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#endif // FPGA_CELL_LUT34_H
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#endif // FPGA_CELL_LUT34_H
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@ -1,15 +1,20 @@
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#include "fpga_cell_none.h"
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#include "fpga_cell_none.h"
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#include <stdlib.h>
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#include <stdlib.h>
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#include "fpga_global.h"
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struct fpga_cell_none *fpga_cell_none_new()
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struct fpga_cell *fpga_cell_none_new()
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{
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{
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struct fpga_cell_none *fpga_cell_none;
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struct fpga_cell_none *fpga_cell_none;
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fpga_cell_none = malloc(sizeof(struct fpga_cell_none));
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fpga_cell_none = malloc(sizeof(struct fpga_cell_none));
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if (fpga_cell_none) {
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fpga_cell_init(FPGA_TO_CELL(fpga_cell_none),
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FPGA_CELL_NONE);
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}
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return fpga_cell_none;
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return FPGA_TO_CELL(fpga_cell_none);
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}
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struct fpga_cell *fpga_cell_none_get_next_isp(struct fpga_cell *fpga_cell,
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enum fpga_isp_channel *isp_channel)
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{
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report(LL_WARNING,
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"ISP signal ran into empty cell. Terminating chain.");
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return NULL;
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}
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}
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@ -7,6 +7,8 @@ struct fpga_cell_none {
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struct fpga_cell base_cell;
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struct fpga_cell base_cell;
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};
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};
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struct fpga_cell_none *fpga_cell_none_new();
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struct fpga_cell *fpga_cell_none_new();
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struct fpga_cell *fpga_cell_none_get_next_isp(struct fpga_cell *fpga_cell,
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enum fpga_isp_channel *isp_channel);
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#endif // FPGA_CELL_NONE_H
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#endif // FPGA_CELL_NONE_H
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61
sw/kousaten/src/fpga_cell_wire.c
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61
sw/kousaten/src/fpga_cell_wire.c
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#include "fpga_cell_wire.h"
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#include <stdlib.h>
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#include "fpga_global.h"
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struct fpga_cell *fpga_cell_wire_new()
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{
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struct fpga_cell_wire *fpga_cell_wire;
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fpga_cell_wire = malloc(sizeof(struct fpga_cell_wire));
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return FPGA_TO_CELL(fpga_cell_wire);
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}
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struct fpga_cell *fpga_cell_wire_get_next_isp(struct fpga_cell *cell,
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enum fpga_isp_channel *isp_channel)
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{
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switch (*isp_channel) {
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case FPGA_ISP_CHANNEL_NORMAL:
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switch (cell->type->identifier) {
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case 'P':
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return cell->cell_connections[RIGHT];
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case ']':
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*isp_channel = FPGA_ISP_CHANNEL_BACK;
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return cell->cell_connections[LEFT];
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default:
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goto fail;
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}
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case FPGA_ISP_CHANNEL_BACK:
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switch (cell->type->identifier) {
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case 'P':
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case '[':
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*isp_channel = FPGA_ISP_CHANNEL_LFDN;
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return cell->cell_connections[RIGHT];
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}
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}
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// switch (cell->type->identifier) {
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// case ' ':
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// report(LL_WARNING,
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// "ISP signal ran into empty cell. Terminating chain.");
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// return NULL;
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// case ']':
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// switch (*isp_channel) {
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// case FPGA_ISP_CHANNEL_NORMAL:
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// *isp_channel = FPGA_ISP_CHANNEL_BACK;
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// return cell->cell_connections[LEFT];
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// default:
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// goto fail;
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// }
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// }
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fail:
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report(LL_ERROR,
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"Entered wiring cell %c on invalid ISP channel %d.",
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cell->type->identifier, *isp_channel);
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*isp_channel = FPGA_ISP_CHANNEL_ERROR;
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return NULL;
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return NULL;
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}
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14
sw/kousaten/src/fpga_cell_wire.h
Normal file
14
sw/kousaten/src/fpga_cell_wire.h
Normal file
@ -0,0 +1,14 @@
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#ifndef FPGA_CELL_WIRE_H
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#define FPGA_CELL_WIRE_H
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#include "fpga_cell.h"
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struct fpga_cell_wire {
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struct fpga_cell base_cell;
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};
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|
|
||||||
|
struct fpga_cell *fpga_cell_wire_new();
|
||||||
|
struct fpga_cell *fpga_cell_wire_get_next_isp(struct fpga_cell *cell,
|
||||||
|
enum fpga_isp_channel *isp_channel);
|
||||||
|
|
||||||
|
#endif // FPGA_CELL_WIRE_H
|
@ -21,31 +21,14 @@ struct fpga_cell *fpga_fdef_loader_load(char *filename)
|
|||||||
|
|
||||||
while ((c = fgetc(fdef)) != EOF) {
|
while ((c = fgetc(fdef)) != EOF) {
|
||||||
switch (c) {
|
switch (c) {
|
||||||
case 'L':
|
|
||||||
cell = FPGA_TO_CELL(fpga_cell_lut_34_new());
|
|
||||||
if (!cell) {
|
|
||||||
report(LL_CRITICAL,
|
|
||||||
"Out of memory when creating cell.");
|
|
||||||
/* TODO: clean up existing cells */
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case '\n':
|
case '\n':
|
||||||
col = 0;
|
col = 0;
|
||||||
line++;
|
line++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
report(LL_ERROR,
|
cell = fpga_cell_new((char) c);
|
||||||
"%s:%d:%d: Invalid cell type %c. Replacing with empty cell.",
|
|
||||||
filename, line, col, c);
|
|
||||||
/* fall-through */
|
|
||||||
case ' ':
|
|
||||||
cell = FPGA_TO_CELL(fpga_cell_none_new());
|
|
||||||
if (!cell) {
|
if (!cell) {
|
||||||
report(LL_CRITICAL,
|
|
||||||
"Out of memory when creating cell.");
|
|
||||||
/* TODO: clean up existing cells */
|
/* TODO: clean up existing cells */
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
@ -2,20 +2,34 @@
|
|||||||
#include "fpga_cell.h"
|
#include "fpga_cell.h"
|
||||||
#include "fpga_fdef_loader.h"
|
#include "fpga_fdef_loader.h"
|
||||||
#include "fpga_global.h"
|
#include "fpga_global.h"
|
||||||
|
#include "fpga.h"
|
||||||
|
|
||||||
|
#define E_FDEF 1
|
||||||
|
#define E_BITSTREAM 2
|
||||||
|
|
||||||
int development_test_main(int argc, char *argv[])
|
int development_test_main(int argc, char *argv[])
|
||||||
{
|
{
|
||||||
struct fpga_cell *entry_cell;
|
struct fpga_cell *entry_cell;
|
||||||
|
|
||||||
entry_cell = fpga_fdef_loader_load("fdef/16x16.fdef");
|
entry_cell = fpga_fdef_loader_load("fdef/4x4.fdef");
|
||||||
|
|
||||||
if (!entry_cell) {
|
if (!entry_cell) {
|
||||||
report(LL_CRITICAL, "Error loading FDEF.\n");
|
report(LL_CRITICAL, "Error loading FDEF.");
|
||||||
return 1;
|
return E_FDEF;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// if (entry_cell->type != FPGA_CELL_PROG) {
|
||||||
|
// report(LL_CRITICAL, "Entry cell must be of type P.");
|
||||||
|
// return E_FDEF;
|
||||||
|
// }
|
||||||
|
|
||||||
report(LL_INFO, "FDEF loaded.");
|
report(LL_INFO, "FDEF loaded.");
|
||||||
|
|
||||||
|
if (fpga_generate_bitstream(entry_cell)) {
|
||||||
|
report(LL_CRITICAL, "Critical error during bitstream generation.");
|
||||||
|
return E_BITSTREAM;
|
||||||
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user