electronics/ttl-fpga
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Add LEDs

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This commit is contained in:
Markus Koch 2019-05-31 18:52:59 +02:00
parent 6cbafd76a3
commit e66cd09c68
4 changed files with 909 additions and 769 deletions
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1605
logic_block.sch
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File diff suppressed because it is too large Load Diff

24
lutd.sch
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@ -397,17 +397,17 @@ Wire Wire Line
Wire Wire Line
8500 4500 8150 4500
Wire Wire Line
9600 4050 10000 4050
Text HLabel 10000 4050 2 50 Output ~ 0
9600 4050 10250 4050
Text HLabel 10250 4050 2 50 Output ~ 0
lut_out_a
Text HLabel 10000 4250 2 50 Output ~ 0
Text HLabel 10250 4250 2 50 Output ~ 0
lut_out_c
Text HLabel 10000 4450 2 50 Output ~ 0
Text HLabel 10250 4450 2 50 Output ~ 0
lut_out_b
Wire Wire Line
10000 4450 9600 4450
10250 4450 9600 4450
Wire Wire Line
9600 4250 10000 4250
9600 4250 10250 4250
Text Notes 4800 3700 0 94 ~ 0
A
Text Notes 4800 5300 0 94 ~ 0
@ -664,10 +664,10 @@ Text Label 8150 4700 0 50 ~ 0
async_b
Wire Wire Line
8500 4700 8150 4700
Text HLabel 10000 4650 2 50 Output ~ 0
Text HLabel 10250 4650 2 50 Output ~ 0
lut_out_b_async
Wire Wire Line
10000 4650 9600 4650
10250 4650 9600 4650
Text HLabel 2000 1000 0 50 Input ~ 0
cfg_split_n
Wire Wire Line
@ -971,6 +971,14 @@ Wire Wire Line
Wire Wire Line
10850 900 10650 900
Connection ~ 10650 900
Text Label 9600 4050 0 50 ~ 0
lut_out_a
Text Label 9600 4250 0 50 ~ 0
lut_out_c
Text Label 9600 4450 0 50 ~ 0
lut_out_b
Text Label 9600 4650 0 50 ~ 0
lut_out_b_async
Wire Bus Line
2000 2700 3850 2700
Wire Bus Line

17
ttl-fpga-cache.lib
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@ -257,23 +257,6 @@ X Pin_9 9 -200 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_TestPoint
#
DEF Connector_TestPoint TP 0 30 N N 1 F N
F0 "TP" 0 270 50 H V C CNN
F1 "Connector_TestPoint" 0 200 50 H V C CNN
F2 "" 200 0 50 H I C CNN
F3 "" 200 0 50 H I C CNN
$FPLIST
Pin*
Test*
$ENDFPLIST
DRAW
C 0 130 30 0 1 0 N
X 1 1 0 0 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N

32
ttl-fpga.sch
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@ -82,15 +82,15 @@ Wire Wire Line
Wire Wire Line
8000 4150 7550 4150
Entry Wire Line
7550 4250 7450 4150
7550 4350 7450 4450
Entry Wire Line
7550 4350 7450 4250
7550 4250 7450 4350
Entry Wire Line
7550 4450 7450 4350
7550 4150 7450 4250
Entry Wire Line
7550 4150 7450 4050
7550 4450 7450 4550
Wire Bus Line
7450 4050 6800 4050
7450 4550 6800 4550
Wire Wire Line
4450 3300 4450 3250
Wire Wire Line
@ -285,7 +285,7 @@ F1 "logic_block.sch" 50
F2 "fabric_b[3..0]" I R 6800 4850 50
F3 "fabric_t[3..0]" I R 6800 2800 50
F4 "fabric_l[3..0]" I L 4550 4550 50
F5 "fabric_r[3..0]" I R 6800 4050 50
F5 "fabric_r[3..0]" I R 6800 4550 50
F6 "rst_n" I L 4550 3100 50
F7 "clk" I L 4550 3000 50
F8 "isp_mosi" I L 4550 3400 50
@ -402,7 +402,7 @@ Wire Notes Line
6400 3400 6300 3350
Wire Notes Line
6400 3400 6300 3450
Text Label 6850 4050 0 50 ~ 0
Text Label 6900 4550 0 50 ~ 0
fabric_r[3..0]
Wire Wire Line
5750 2050 5750 2500
@ -413,19 +413,6 @@ Wire Wire Line
Connection ~ 4300 3400
Wire Wire Line
4300 3400 4550 3400
$Comp
L Connector:TestPoint TP?
U 1 1 6010FDC8
P 7900 4050
F 0 "TP?" V 7900 4300 50 0000 C CNN
F 1 "mosi_d" V 7900 3550 50 0000 C CNN
F 2 "" H 8100 4050 50 0001 C CNN
F 3 "~" H 8100 4050 50 0001 C CNN
1 7900 4050
0 -1 -1 0
$EndComp
Wire Wire Line
8000 4050 7900 4050
Wire Notes Line
8550 3850 8650 3850
Wire Notes Line
@ -499,8 +486,11 @@ Wire Wire Line
5150 2250 5150 2150
Wire Wire Line
5200 5150 5200 5200
NoConn ~ 5950 2050
NoConn ~ 8000 4050
NoConn ~ 5950 5600
Wire Bus Line
7450 4050 7450 4350
7450 4250 7450 4550
Wire Bus Line
3900 4250 3900 4550
Wire Bus Line