diff --git a/sw/kousaten/src/fpga_cell_lut34.c b/sw/kousaten/src/fpga_cell_lut34.c index e1aed64..931fb3d 100644 --- a/sw/kousaten/src/fpga_cell_lut34.c +++ b/sw/kousaten/src/fpga_cell_lut34.c @@ -19,7 +19,7 @@ static int LUT3_BITMAP[2][8] = { }; /* LUT Config Definitions */ -static int BIT_LUT_SYNC = 20; +static int BIT_LUT_SYNC_N = 20; static int BIT_LUT_SPLIT_N = 21; /* LUT IN MUX Definitions */ @@ -178,7 +178,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell) fix_bitfields(ROUTE_BITMAP, 8); fix_bitfields(&BIT_LED_LUT_IN, 1); fix_bitfields(&BIT_LED_LUT_OUT_N, 1); - fix_bitfields(&BIT_LUT_SYNC, 1); + fix_bitfields(&BIT_LUT_SYNC_N, 1); fix_bitfields(&BIT_LUT_SPLIT_N, 1); } @@ -254,7 +254,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell) BS_SET_BIT(BIT_LUT_SPLIT_N, 0, "Couldn't set LUT3-2 mode. Did you configure a LUT4 before?"); } } - BS_SET_BIT(BIT_LUT_SYNC, lut34->sync, "Couldn't %s synchronous mode.", + BS_SET_BIT(BIT_LUT_SYNC_N, !lut34->sync, "Couldn't %s synchronous mode.", (lut34->sync ? "enabling" : "disabling")); /* Basic check whether each bit has been configured */ diff --git a/sw/kousaten/src/main.c b/sw/kousaten/src/main.c index 5f7f50c..9a32c6e 100644 --- a/sw/kousaten/src/main.c +++ b/sw/kousaten/src/main.c @@ -76,7 +76,7 @@ int development_test_main(int argc, char *argv[]) ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[1] = LUT_NET_F2; ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[2] = LUT_NET_L2; ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[3] = LUT_NET_L3; - ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->sync = 0; + ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->sync = 1; ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[0] = 'A'; ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[1] = 'Z';