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30e18b4357
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sw: Add 16-bit counter demo
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2019-09-27 15:23:03 +02:00 |
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6fbdcf9016
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sw: Fix coding style
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2019-09-23 21:29:36 +02:00 |
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7bb7049eea
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sw: Fix logic to determine when to enable the output drivers
Before, it was always enabling all outputs,
even when they should have been tristated.
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2019-09-23 21:28:54 +02:00 |
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98a7a5d170
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sw: Create function to determine whether an output is driven
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2019-09-23 21:27:45 +02:00 |
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953818f43c
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sw: Report if bit is unset in final bitstream result
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2019-09-23 21:26:50 +02:00 |
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72dabd64db
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sw: Swap the order of the two LUTs in the bitstream
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2019-09-23 21:25:27 +02:00 |
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f27c728472
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sw: Implement bodgefix for schematic rev 03L
|
2019-09-22 19:11:43 +02:00 |
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30c83a658f
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sw: Fix fpga_cell_lut34_lut_get_out_mux
Was accessing wrong data when generating info for set 2.
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2019-09-22 19:11:21 +02:00 |
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0a493bdd2a
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Remove unnecessary debug output
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2019-09-13 13:02:05 +09:00 |
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a072dbfe8a
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Fix unnecessary semicolon warnings in bit set / unset macros
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2019-09-13 12:59:24 +09:00 |
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a2abccfc5d
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Fix output MUX selection logic
Fixes #15.
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2019-09-13 12:55:32 +09:00 |
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7abcead6a9
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des: Fix data type of drive_sel
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2019-09-13 12:48:28 +09:00 |
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f60d76f831
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Fix sync polarity
Fixes #11.
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2019-06-29 12:48:26 +02:00 |
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9a06c054e8
|
Fix bitstream generator collision check
|
2019-06-29 12:37:59 +02:00 |
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29efb7446b
|
Add spreadsheet to help generate LUT configs
|
2019-06-22 17:50:42 +02:00 |
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0de1c093cd
|
Add program.sh script
|
2019-06-22 17:47:20 +02:00 |
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15fe4e4ca3
|
Add test configuration for 2-bit counter
|
2019-06-22 17:24:44 +02:00 |
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6846aff71d
|
Add debug print for bitstream bits
|
2019-06-22 17:24:26 +02:00 |
|
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|
01df956317
|
Fix a variety of bugs found during integration
|
2019-06-22 17:24:09 +02:00 |
|
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|
28adf2340b
|
Add FDEF for single-cell FPGA
|
2019-06-21 21:17:32 +02:00 |
|
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|
ae2e6552ce
|
Add option to generate binary or ASCII hex bitstreams
|
2019-06-21 21:16:46 +02:00 |
|
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|
7df813fc71
|
Add argument parsing
|
2019-06-21 20:57:56 +02:00 |
|
|
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0834cf0c0d
|
Finish basic bitstream generator
|
2019-06-21 20:31:34 +02:00 |
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5d86f8c7cf
|
Start bitstream generator
|
2019-06-20 13:45:04 +02:00 |
|
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a1d635889c
|
Clean up
|
2019-06-19 18:32:59 +02:00 |
|
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925e17372a
|
Implement fpga_isp_chain_new
|
2019-06-19 18:25:21 +02:00 |
|
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|
d0fed3cce4
|
Implement ISP chain walker
|
2019-06-18 20:15:35 +02:00 |
|
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cf80ff7b6b
|
Reverse order of log levels
|
2019-06-17 22:08:24 +02:00 |
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|
0309934d82
|
Add comments for later cleanups
|
2019-06-17 22:08:11 +02:00 |
|
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|
e12120fade
|
Start implementing Kousaten
|
2019-06-16 21:27:42 +02:00 |
|
|
|
0072ed418b
|
Initialize CMakeProject for Kousaten
|
2019-06-16 17:11:20 +02:00 |
|
|
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7544e4256a
|
Configure Gerber export for PCBWay
|
2019-06-16 13:40:37 +02:00 |
|
|
|
b8c465da70
|
Add power LED label
|
2019-06-16 13:20:47 +02:00 |
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2de7b3ec6c
|
Add part numbers to silkscreen
|
2019-06-16 13:18:15 +02:00 |
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1f72590231
|
Make some minor adjustments
|
2019-06-15 12:57:17 +02:00 |
|
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|
685bc88045
|
Change Schottky footprint to SOD123
|
2019-06-15 11:47:19 +02:00 |
|
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|
58ad3a75c5
|
Cover the board in silkscreen
|
2019-06-14 20:42:09 +02:00 |
|
|
|
718d70132b
|
Add MokM0d logo
|
2019-06-14 19:51:25 +02:00 |
|
|
|
45827f239a
|
Clean up silkscreen
|
2019-06-13 19:47:35 +02:00 |
|
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|
9f96e5cf82
|
Editiorial
|
2019-06-13 19:19:26 +02:00 |
|
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|
01043be425
|
Remove incorrect junction
Fixes #7.
|
2019-06-13 19:18:58 +02:00 |
|
|
|
dc5b791b6d
|
Finish layout
|
2019-06-13 19:16:26 +02:00 |
|
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|
339fb214d7
|
Continue work on rev 1
|
2019-06-11 21:50:54 +02:00 |
|
|
|
1c6ae29a8f
|
Layout rev 1
|
2019-06-10 19:48:44 +02:00 |
|
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f85577c0f1
|
Reset routing, place all components
|
2019-06-10 17:27:15 +02:00 |
|
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|
a1046d75b8
|
Continue trial layout
|
2019-06-10 14:25:54 +02:00 |
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fc94685478
|
Every day I'm layoutin'
|
2019-06-09 23:22:42 +02:00 |
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a9d8d0e654
|
doc: Add notes
|
2019-06-06 21:25:18 +02:00 |
|
|
|
01918678ce
|
Add licensing information
|
2019-06-06 20:45:55 +02:00 |
|
|
|
8b80a78b3b
|
Layout input muxing
|
2019-06-05 23:32:39 +02:00 |
|
