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30e18b4357
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sw: Add 16-bit counter demo
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2019-09-27 15:23:03 +02:00 |
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6fbdcf9016
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sw: Fix coding style
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2019-09-23 21:29:36 +02:00 |
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7bb7049eea
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sw: Fix logic to determine when to enable the output drivers
Before, it was always enabling all outputs,
even when they should have been tristated.
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2019-09-23 21:28:54 +02:00 |
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98a7a5d170
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sw: Create function to determine whether an output is driven
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2019-09-23 21:27:45 +02:00 |
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953818f43c
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sw: Report if bit is unset in final bitstream result
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2019-09-23 21:26:50 +02:00 |
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72dabd64db
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sw: Swap the order of the two LUTs in the bitstream
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2019-09-23 21:25:27 +02:00 |
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f27c728472
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sw: Implement bodgefix for schematic rev 03L
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2019-09-22 19:11:43 +02:00 |
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30c83a658f
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sw: Fix fpga_cell_lut34_lut_get_out_mux
Was accessing wrong data when generating info for set 2.
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2019-09-22 19:11:21 +02:00 |
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0a493bdd2a
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Remove unnecessary debug output
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2019-09-13 13:02:05 +09:00 |
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a072dbfe8a
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Fix unnecessary semicolon warnings in bit set / unset macros
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2019-09-13 12:59:24 +09:00 |
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a2abccfc5d
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Fix output MUX selection logic
Fixes #15.
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2019-09-13 12:55:32 +09:00 |
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7abcead6a9
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des: Fix data type of drive_sel
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2019-09-13 12:48:28 +09:00 |
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f60d76f831
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Fix sync polarity
Fixes #11.
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2019-06-29 12:48:26 +02:00 |
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9a06c054e8
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Fix bitstream generator collision check
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2019-06-29 12:37:59 +02:00 |
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0de1c093cd
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Add program.sh script
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2019-06-22 17:47:20 +02:00 |
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15fe4e4ca3
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Add test configuration for 2-bit counter
|
2019-06-22 17:24:44 +02:00 |
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6846aff71d
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Add debug print for bitstream bits
|
2019-06-22 17:24:26 +02:00 |
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01df956317
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Fix a variety of bugs found during integration
|
2019-06-22 17:24:09 +02:00 |
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28adf2340b
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Add FDEF for single-cell FPGA
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2019-06-21 21:17:32 +02:00 |
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ae2e6552ce
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Add option to generate binary or ASCII hex bitstreams
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2019-06-21 21:16:46 +02:00 |
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7df813fc71
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Add argument parsing
|
2019-06-21 20:57:56 +02:00 |
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0834cf0c0d
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Finish basic bitstream generator
|
2019-06-21 20:31:34 +02:00 |
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5d86f8c7cf
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Start bitstream generator
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2019-06-20 13:45:04 +02:00 |
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a1d635889c
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Clean up
|
2019-06-19 18:32:59 +02:00 |
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925e17372a
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Implement fpga_isp_chain_new
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2019-06-19 18:25:21 +02:00 |
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d0fed3cce4
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Implement ISP chain walker
|
2019-06-18 20:15:35 +02:00 |
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cf80ff7b6b
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Reverse order of log levels
|
2019-06-17 22:08:24 +02:00 |
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0309934d82
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Add comments for later cleanups
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2019-06-17 22:08:11 +02:00 |
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e12120fade
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Start implementing Kousaten
|
2019-06-16 21:27:42 +02:00 |
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0072ed418b
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Initialize CMakeProject for Kousaten
|
2019-06-16 17:11:20 +02:00 |
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