Add option to generate binary or ASCII hex bitstreams

sw/kousaten/src/fpga.c

@@ -5,11 +5,11 @@
 #include <string.h>
 
 int fpga_generate_bitstream(struct fpga_chain *chain,
-			    char *filename)
+			    char *filename, int ascii)
 {
 	int i;
 	char *buf = NULL;
-	FILE *bitstream = stderr;
+	FILE *bitstream = stdout;
 
 	if (strcmp(filename, "-")) {
 		bitstream = fopen(filename, "wb");
@@ -37,9 +37,13 @@ int fpga_generate_bitstream(struct fpga_chain *chain,
 			goto fail;
 		}
 		for (int j = 0; j < chain->head[i]->type->isp_length; ++j) {
-			fprintf(bitstream, "%02X ", buf[j] & 0xFF);
+			if (ascii)
+				fprintf(bitstream, "%02X ", buf[j] & 0xFF);
+			else
+				fputc(buf[j] & 0xFF, bitstream);
 		}
-		fprintf(bitstream, "\n");
+		if (ascii)
+			fprintf(bitstream, "\n");
 		free(buf);
 	}
 

sw/kousaten/src/fpga.h

@@ -3,6 +3,6 @@
 #include "fpga_cell.h"
 
 int fpga_generate_bitstream(struct fpga_chain *chain,
-			    char *filename);
+			    char *filename, int ascii);
 
 #endif // FPGA_H

sw/kousaten/src/main.c

@@ -3,6 +3,8 @@
 #include "fpga_fdef_loader.h"
 #include "fpga_global.h"
 #include "fpga.h"
+#include "unistd.h"
+#include "string.h"
 
 #define E_FDEF 1
 #define E_BITSTREAM 2
@@ -12,11 +14,47 @@ int development_test_main(int argc, char *argv[])
 	struct fpga_cell *entry_cell;
 	struct fpga_chain *chain;
 
+	int opt;
 	char *fdef_filename = "fdef/4x4.fdef";
+	char *kst_filename = "-";
 	char *bitstream_filename = "-";
+	int bitstream_ascii = 0;
 
 	set_log_level(LL_DEBUG);
 
+	while((opt = getopt(argc, argv, "f:i:o:a")) != -1)
+	{
+		switch(opt)
+		{
+		case 'f':
+			fdef_filename = optarg;
+			break;
+		case 'i':
+			kst_filename = optarg;
+			report(LL_WARNING, "Input not yet implemented.");
+			break;
+		case 'o':
+			bitstream_filename = optarg;
+			break;
+		case 'h':
+			bitstream_ascii = 1;
+			break;
+		case ':':
+		case '?':
+			printf("Usage: %s [-f fdef] [-i input.kst] [-o output.bin] [-h]\n"
+			       "Generate bitstreams for the TTL-FPGA.\n\n"
+			       "When INPUT or OUTPUT is -, read/write standard input.\n\n"
+			       "  -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
+			       "  -i\tKousaten input file, default stdin\n"
+			       "  -o\tOutput file, default stdout\n"
+			       "  -a\tGenerate output as ASCII HEX\n",
+			       argv[0]);
+			return 0;
+		default:
+			break;
+		}
+	}
+
 	entry_cell = fpga_fdef_loader_load(fdef_filename);
 	if (!entry_cell) {
 		report(LL_CRITICAL, "Error loading FDEF.");
@@ -34,9 +72,9 @@ int development_test_main(int argc, char *argv[])
 	/* TODO: Configure application specific logic */
 	((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[0] = 'A';
 	((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[0] = 'C';
-	((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT4 = 0;
+	((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT4 = 0x0F;
 
-	if (fpga_generate_bitstream(chain, bitstream_filename)) {
+	if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) {
 		report(LL_ERROR, "Bitstream generation failed.");
 		return E_BITSTREAM;
 	}