electronics/ttl-fpga
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2 Commits
0a493bdd2a ... f27c728472

Author SHA1 Message Date
Markus Koch
f27c728472 sw: Implement bodgefix for schematic rev 03L 2019-09-22 19:11:43 +02:00
Markus Koch
30c83a658f sw: Fix fpga_cell_lut34_lut_get_out_mux 
Was accessing wrong data when generating info for set 2.
 2019-09-22 19:11:21 +02:00
1 changed files with 2 additions and 3 deletions
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sw/kousaten/src/fpga_cell_lut34.c
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@ -39,7 +39,7 @@ static int LUT_IN_BITMAP[4][3] = {
/* LUT OUT MUX Definitions */ /* LUT OUT MUX Definitions */
static int LUT_OUT_MUX[4][4] = { static int LUT_OUT_MUX[4][4] = {
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC}, {LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}, {LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_A, LUT_OUT_A},
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC}, {LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A} {LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
}; };
@ -78,8 +78,6 @@ static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports) {
int i; int i;
int lut; int lut;
ports = ports + lut_group;
if (lut_group < 0 || lut_group > 2) { if (lut_group < 0 || lut_group > 2) {
report(LL_ERROR, report(LL_ERROR,
"Invalid LUT group requested."); "Invalid LUT group requested.");
@ -87,6 +85,7 @@ static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports) {
} }
lut = lut_group * 2; lut = lut_group * 2;
ports = ports + lut;
for (i = 0; i < 4; ++i) { for (i = 0; i < 4; ++i) {
if (ports[0] == LUT_OUT_DC || if (ports[0] == LUT_OUT_DC ||