logic_block.sch

@@ -6,7 +6,7 @@ $Descr A3 16535 11693
 encoding utf-8
 Sheet 2 3
 Title "DISCRETE TTL FPGA"
-Date "2019-05-31"
+Date ""
 Rev "01"
 Comp "Markus Koch <markus@notsyncing.net>"
 Comment1 "Logic Block"
@@ -1800,14 +1800,30 @@ Wire Notes Line
 	12650 5000 14300 5000
 Wire Wire Line
 	3800 5400 6450 5400
-Text Notes 7200 5050 0    50   ~ 10
-LUT + Reg
+Text Notes 7500 5050 0    50   ~ 10
+LUT
+Connection ~ 10100 8250
+Wire Wire Line
+	10100 8250 10400 8250
+Wire Wire Line
+	9700 8250 9650 8250
+Connection ~ 9700 8250
+Wire Wire Line
+	10100 8250 10050 8250
+Wire Wire Line
+	10100 8350 10100 8250
+Wire Wire Line
+	9700 8350 10100 8350
+Wire Wire Line
+	9700 8250 9700 8350
+Wire Wire Line
+	9750 8250 9700 8250
 $Comp
 L Device:R R?
 U 1 1 5F6FE7F1
 P 9900 8250
 F 0 "R?" V 9693 8250 50  0000 C CNN
-F 1 "470" V 9784 8250 50  0000 C CNN
+F 1 "DNP" V 9784 8250 50  0000 C CNN
 F 2 "" V 9830 8250 50  0001 C CNN
 F 3 "~" H 9900 8250 50  0001 C CNN
 	1    9900 8250
@@ -1815,12 +1831,28 @@ F 3 "~" H 9900 8250 50  0001 C CNN
 $EndComp
 Text Label 10400 8250 2    50   ~ 0
 fabric3
+Connection ~ 10100 7750
+Wire Wire Line
+	10100 7750 10400 7750
+Wire Wire Line
+	9700 7750 9650 7750
+Connection ~ 9700 7750
+Wire Wire Line
+	10100 7750 10050 7750
+Wire Wire Line
+	10100 7850 10100 7750
+Wire Wire Line
+	9700 7850 10100 7850
+Wire Wire Line
+	9700 7750 9700 7850
+Wire Wire Line
+	9750 7750 9700 7750
 $Comp
 L Device:R R?
 U 1 1 5F6D346A
 P 9900 7750
 F 0 "R?" V 9693 7750 50  0000 C CNN
-F 1 "470" V 9784 7750 50  0000 C CNN
+F 1 "DNP" V 9784 7750 50  0000 C CNN
 F 2 "" V 9830 7750 50  0001 C CNN
 F 3 "~" H 9900 7750 50  0001 C CNN
 	1    9900 7750
@@ -1828,12 +1860,28 @@ F 3 "~" H 9900 7750 50  0001 C CNN
 $EndComp
 Text Label 10400 7750 2    50   ~ 0
 fabric2
+Connection ~ 10100 6400
+Wire Wire Line
+	10100 6400 10400 6400
+Wire Wire Line
+	9700 6400 9650 6400
+Connection ~ 9700 6400
+Wire Wire Line
+	10100 6400 10050 6400
+Wire Wire Line
+	10100 6500 10100 6400
+Wire Wire Line
+	9700 6500 10100 6500
+Wire Wire Line
+	9700 6400 9700 6500
+Wire Wire Line
+	9750 6400 9700 6400
 $Comp
 L Device:R R?
 U 1 1 5F6AC414
 P 9900 6400
 F 0 "R?" V 9693 6400 50  0000 C CNN
-F 1 "470" V 9784 6400 50  0000 C CNN
+F 1 "DNP" V 9784 6400 50  0000 C CNN
 F 2 "" V 9830 6400 50  0001 C CNN
 F 3 "~" H 9900 6400 50  0001 C CNN
 	1    9900 6400
@@ -1841,12 +1889,28 @@ F 3 "~" H 9900 6400 50  0001 C CNN
 $EndComp
 Text Label 10400 6400 2    50   ~ 0
 fabric1
+Connection ~ 10100 5900
+Wire Wire Line
+	10100 5900 10400 5900
+Wire Wire Line
+	9700 5900 9650 5900
+Connection ~ 9700 5900
+Wire Wire Line
+	10100 5900 10050 5900
+Wire Wire Line
+	10100 6000 10100 5900
+Wire Wire Line
+	9700 6000 10100 6000
+Wire Wire Line
+	9700 5900 9700 6000
+Wire Wire Line
+	9750 5900 9700 5900
 $Comp
 L Device:R R?
 U 1 1 5F4F0B12
 P 9900 5900
 F 0 "R?" V 9693 5900 50  0000 C CNN
-F 1 "470" V 9784 5900 50  0000 C CNN
+F 1 "DNP" V 9784 5900 50  0000 C CNN
 F 2 "" V 9830 5900 50  0001 C CNN
 F 3 "~" H 9900 5900 50  0001 C CNN
 	1    9900 5900
@@ -2486,20 +2550,4 @@ Wire Bus Line
 	7750 1800 7750 4350
 Wire Bus Line
 	5900 1800 5900 4350
-Wire Wire Line
-	10050 5900 10400 5900
-Wire Wire Line
-	9650 5900 9750 5900
-Wire Wire Line
-	9650 6400 9750 6400
-Wire Wire Line
-	10050 6400 10400 6400
-Wire Wire Line
-	9650 7750 9750 7750
-Wire Wire Line
-	10050 7750 10400 7750
-Wire Wire Line
-	10050 8250 10400 8250
-Wire Wire Line
-	9650 8250 9750 8250
 $EndSCHEMATC

lutd.sch

@@ -6,7 +6,7 @@ $Descr A4 11693 8268
 encoding utf-8
 Sheet 3 3
 Title "DISCRETE TTL FPGA"
-Date "2019-05-31"
+Date ""
 Rev "01"
 Comp "Markus Koch <markus@notsyncing.net>"
 Comment1 "Logic Block"

ttl-fpga.sch

@@ -6,7 +6,7 @@ $Descr A4 11693 8268
 encoding utf-8
 Sheet 1 3
 Title "DISCRETE TTL FPGA"
-Date "2019-05-31"
+Date ""
 Rev "01"
 Comp "Markus Koch <markus@notsyncing.net>"
 Comment1 "PCB"