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base: electronics:5bcc79e505e7f7af65e127653a489c54ab42b52d
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electronics:sw
electronics:master
electronics:rev02
electronics:rev01
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compare: electronics:798144c729a60c1b5248e4a71832d95d0b91380b
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electronics:master
electronics:sw
electronics:rev02
electronics:rev01

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kicad_pcb/logic_block.sch
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kicad_pcb/lutd.sch
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EESchema Schematic File Version 4
LIBS:ttl-fpga-cache
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 3 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "02"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block"
Comment2 "single 4-input LUT / dual 3-input LUT"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
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U 1 1 5CF42176
P 3100 3450
AR Path="/5CF41639/5CF42176" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF42176" Ref="U13" Part="1"
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F 1 "74164" H 3500 3750 50 0000 C CNN
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F 3 "" H 3100 3450 50 0001 C CNN
1 3100 3450
1 0 0 -1
$EndComp
$Comp
L 74xx_IEEE:74164 U?
U 1 1 5CF427E5
P 3100 5000
AR Path="/5CF41639/5CF427E5" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF427E5" Ref="U17" Part="1"
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F 3 "" H 3100 5000 50 0001 C CNN
1 3100 5000
1 0 0 -1
$EndComp
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
3650 4250 3700 4250
Wire Wire Line
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Wire Wire Line
2450 5050 2500 5050
Wire Wire Line
3700 4250 3700 4400
Connection ~ 2500 5050
Wire Wire Line
2500 5050 2500 5000
Wire Wire Line
2550 3550 2500 3550
Wire Wire Line
2500 3550 2500 3500
Wire Wire Line
2500 3450 2550 3450
Wire Wire Line
2550 4850 2350 4850
Wire Wire Line
2350 4850 2350 3300
Wire Wire Line
2350 3300 2550 3300
Wire Wire Line
2500 3500 2000 3500
Connection ~ 2500 3500
Wire Wire Line
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Wire Wire Line
2350 3300 2000 3300
Connection ~ 2350 3300
Wire Wire Line
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Wire Wire Line
3650 3650 4250 3650
Wire Wire Line
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Wire Wire Line
3650 3950 4250 3950
Wire Wire Line
3650 4050 4250 4050
Wire Wire Line
3650 4150 4250 4150
Connection ~ 3700 4250
Wire Wire Line
3700 4250 4250 4250
Wire Wire Line
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Wire Wire Line
3700 3550 3700 3500
Wire Wire Line
3700 3500 3650 3500
$Comp
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U 1 1 5CF5B900
P 4800 5200
AR Path="/5CF41639/5CF5B900" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF5B900" Ref="U18" Part="1"
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F 3 "" H 4800 5200 50 0001 C CNN
1 4800 5200
1 0 0 -1
$EndComp
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
4250 5700 3650 5700
Wire Wire Line
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Wire Wire Line
4250 5100 3700 5100
Wire Wire Line
3700 5100 3700 5050
Wire Wire Line
3700 5050 3650 5050
Entry Wire Line
3850 3100 3950 3200
Entry Wire Line
3850 3200 3950 3300
Entry Wire Line
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Wire Wire Line
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$Comp
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P 4800 3650
AR Path="/5CF41639/5CF4F8AB" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF4F8AB" Ref="U14" Part="1"
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F 3 "" H 4800 3650 50 0001 C CNN
1 4800 3650
1 0 0 -1
$EndComp
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3950 3300 4250 3300
Wire Wire Line
3950 3400 4250 3400
Entry Wire Line
3850 4750 3950 4850
Entry Wire Line
3850 4650 3950 4750
Entry Wire Line
3850 4850 3950 4950
Wire Wire Line
3950 4750 4250 4750
Wire Wire Line
3950 4850 4250 4850
Wire Wire Line
3950 4950 4250 4950
Text Label 3950 3300 0 50 ~ 0
lut_in1
Text Label 3950 3400 0 50 ~ 0
lut_in2
Text Label 3950 4750 0 50 ~ 0
lut_in0
Text Label 3950 4850 0 50 ~ 0
lut_in1
Text Label 3950 4950 0 50 ~ 0
lut_in2
Text HLabel 2000 3300 0 50 Input ~ 0
isp_sck
Text HLabel 2000 3500 0 50 Input ~ 0
isp_mosi
Wire Wire Line
3700 5800 3700 5950
Connection ~ 3700 5800
Wire Wire Line
3700 5800 3650 5800
Wire Wire Line
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Text HLabel 2000 5950 0 50 Output ~ 0
isp_miso
Text HLabel 2000 2700 0 50 Input ~ 0
lut_in[3..0]
Text Label 3950 3200 0 50 ~ 0
lut_in0
Text Label 2050 2700 0 50 ~ 0
lut_in[3..0]
NoConn ~ 5350 4000
NoConn ~ 5350 5550
Text HLabel 2000 1350 0 50 Input ~ 0
cfg_sync
NoConn ~ 7450 4300
NoConn ~ 7450 4400
NoConn ~ 7450 4500
Text HLabel 2000 6650 0 50 Input ~ 0
clk
Text HLabel 2000 6750 0 50 Input ~ 0
rst_n
$Comp
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P 6200 4550
AR Path="/5CF41639/5D015E6D" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D015E6D" Ref="#PWR065" Part="1"
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F 2 "" H 6200 4550 50 0001 C CNN
F 3 "" H 6200 4550 50 0001 C CNN
1 6200 4550
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
6450 4400 6200 4400
Wire Wire Line
6200 4400 6200 4500
Connection ~ 6200 4500
Wire Wire Line
6450 4300 6200 4300
Wire Wire Line
6200 4300 6200 4400
Connection ~ 6200 4400
Wire Wire Line
4250 4650 3950 4650
Text Label 3950 4650 0 50 ~ 0
lut_b_en_n
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Text Label 8150 3850 0 50 ~ 0
cfg_sync
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$Comp
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U 1 1 5D187D09
P 9050 4150
AR Path="/5CF41639/5D187D09" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D187D09" Ref="U15" Part="1"
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F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 9050 4150 50 0001 C CNN
F 3 "" H 9050 4150 50 0001 C CNN
1 9050 4150
1 0 0 -1
$EndComp
$Comp
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U 1 1 5CF941AD
P 6950 4400
AR Path="/5CF41639/5CF941AD" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF941AD" Ref="U16" Part="1"
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1 6950 4400
1 0 0 -1
$EndComp
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Wire Wire Line
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Wire Wire Line
6100 4000 6450 4000
Wire Wire Line
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Wire Wire Line
6100 4200 6450 4200
Wire Wire Line
5350 4850 5800 4850
Wire Wire Line
5800 4650 5800 4850
Connection ~ 5800 4850
Wire Wire Line
5800 4850 6100 4850
Wire Wire Line
5800 4350 5800 4100
Wire Wire Line
5800 3500 5800 3300
Connection ~ 5800 3300
Wire Wire Line
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Wire Wire Line
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Connection ~ 5800 4100
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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P 5550 4350
AR Path="/5CF41639/5D1A7947" Ref="R?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D1A7947" Ref="R16" Part="1"
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F 3 "~" H 5550 4350 50 0001 C CNN
1 5550 4350
1 0 0 1
$EndComp
$Comp
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P 5550 4600
AR Path="/5CF41639/5D1A7DBD" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D1A7DBD" Ref="#PWR066" Part="1"
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F 2 "" H 5550 4600 50 0001 C CNN
F 3 "" H 5550 4600 50 0001 C CNN
1 5550 4600
1 0 0 -1
$EndComp
Wire Wire Line
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Text Label 6150 4000 0 50 ~ 0
async_a
Text Label 6150 4100 0 50 ~ 0
async_c
Text Label 6150 4200 0 50 ~ 0
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Text Label 7550 4000 0 50 ~ 0
sync_a
Text Label 7550 4100 0 50 ~ 0
sync_c
Text Label 7550 4200 0 50 ~ 0
sync_b
Wire Wire Line
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Wire Wire Line
7950 4100 7950 4200
Wire Wire Line
7950 4200 8500 4200
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
7850 4200 7850 4400
Wire Wire Line
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Text Label 8150 4100 0 50 ~ 0
async_a
Text Label 8150 4300 0 50 ~ 0
async_c
Text Label 8150 4500 0 50 ~ 0
async_b
Wire Wire Line
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Wire Wire Line
8500 4500 8150 4500
Wire Wire Line
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Text HLabel 10250 4050 2 50 Output ~ 0
lut_out_a
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lut_out_c
Text HLabel 10250 4450 2 50 Output ~ 0
lut_out_b
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Wire Wire Line
9600 4250 10250 4250
Text Notes 4800 3700 0 94 ~ 0
A
Text Notes 4800 5300 0 94 ~ 0
B
Entry Wire Line
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Text Label 2550 2600 0 50 ~ 0
lut_in3
Wire Wire Line
6450 4700 6350 4700
Wire Wire Line
6350 4700 6350 6650
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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AR Path="/5D77FDBE/5D7AF013/5D26A4EB" Ref="#PWR068" Part="1"
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1 6950 5300
1 0 0 -1
$EndComp
Wire Wire Line
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1 8300 3550
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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1 6950 3600
1 0 0 -1
$EndComp
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$Comp
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1 0 0 -1
$EndComp
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$Comp
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AR Path="/5D77FDBE/5D7AF013/5D2970E5" Ref="#PWR061" Part="1"
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1 4450 4400
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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$Comp
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$EndComp
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AR Path="/5D77FDBE/5D7AF013/5D29EA17" Ref="#PWR054" Part="1"
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$EndComp
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$Comp
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F 3 "" H 2900 2850 50 0001 C CNN
1 2900 2850
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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P 3300 3000
AR Path="/5CF41639/5D2B7E69" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2B7E69" Ref="#PWR055" Part="1"
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1 3300 3000
1 0 0 -1
$EndComp
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Wire Wire Line
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$Comp
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AR Path="/5D77FDBE/5D7AF013/5D2CD01F" Ref="#PWR062" Part="1"
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F 2 "" H 2900 4450 50 0001 C CNN
F 3 "" H 2900 4450 50 0001 C CNN
1 2900 4450
1 0 0 -1
$EndComp
Wire Wire Line
2900 4450 3100 4450
Wire Wire Line
3100 4450 3100 4650
$Comp
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P 3300 4550
AR Path="/5CF41639/5D2D1794" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2D1794" Ref="#PWR064" Part="1"
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1 3300 4550
1 0 0 -1
$EndComp
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Wire Wire Line
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Text Label 8150 4700 0 50 ~ 0
async_b
Wire Wire Line
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Text HLabel 10250 4650 2 50 Output ~ 0
lut_out_b_async
Wire Wire Line
10250 4650 9600 4650
Text HLabel 2000 1650 0 50 Input ~ 0
cfg_split_n
$Comp
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P 8850 3450
AR Path="/5CF41639/5CF3ABB3" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF3ABB3" Ref="#PWR057" Part="1"
AR Path="/5D77FDBE/5CF3ABB3" Ref="#PWR?" Part="1"
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1 8850 3450
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
9050 3450 9050 3650
$Comp
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P 9200 3550
AR Path="/5CF41639/5CF3ABBB" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF3ABBB" Ref="#PWR059" Part="1"
AR Path="/5D77FDBE/5CF3ABBB" Ref="#PWR?" Part="1"
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F 2 "" H 9200 3550 50 0001 C CNN
F 3 "" H 9200 3550 50 0001 C CNN
1 9200 3550
1 0 0 -1
$EndComp
Wire Wire Line
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$Comp
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P 9500 2050
AR Path="/5D77FDBE/5D2EACB1" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACB1" Ref="C16" Part="1"
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F 3 "~" H 9500 2050 50 0001 C CNN
1 9500 2050
1 0 0 -1
$EndComp
$Comp
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U 1 1 5D2EACB7
P 9700 2050
AR Path="/5D77FDBE/5D2EACB7" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACB7" Ref="C17" Part="1"
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F 2 "Capacitor_SMD:C_0603_1608Metric" H 9738 1900 50 0001 C CNN
F 3 "~" H 9700 2050 50 0001 C CNN
1 9700 2050
1 0 0 -1
$EndComp
$Comp
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U 1 1 5D2EACBD
P 9900 2050
AR Path="/5D77FDBE/5D2EACBD" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACBD" Ref="C18" Part="1"
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F 3 "~" H 9900 2050 50 0001 C CNN
1 9900 2050
1 0 0 -1
$EndComp
$Comp
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P 10100 2050
AR Path="/5D77FDBE/5D2EACC3" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACC3" Ref="C19" Part="1"
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F 3 "~" H 10100 2050 50 0001 C CNN
1 10100 2050
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 9900 1800
Wire Wire Line
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Wire Wire Line
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Connection ~ 9700 1800
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 9900 2300
Wire Wire Line
9900 2300 10100 2300
Wire Wire Line
9700 2200 9700 2300
Connection ~ 9700 2300
$Comp
L power:GNDD #PWR?
U 1 1 5D2EACE7
P 9700 2400
AR Path="/5D77FDBE/5D2EACE7" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACE7" Ref="#PWR052" Part="1"
F 0 "#PWR052" H 9700 2150 50 0001 C CNN
F 1 "GNDD" H 9704 2245 50 0000 C CNN
F 2 "" H 9700 2400 50 0001 C CNN
F 3 "" H 9700 2400 50 0001 C CNN
1 9700 2400
1 0 0 -1
$EndComp
$Comp
L Device:C C?
U 1 1 5D2FCD73
P 10300 2050
AR Path="/5D77FDBE/5D2FCD73" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2FCD73" Ref="C20" Part="1"
F 0 "C20" H 10300 2150 50 0000 L CNN
F 1 "100n" H 10300 1950 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 10338 1900 50 0001 C CNN
F 3 "~" H 10300 2050 50 0001 C CNN
1 10300 2050
1 0 0 -1
$EndComp
$Comp
L Device:C C?
U 1 1 5D2FCFE7
P 9300 2050
AR Path="/5D77FDBE/5D2FCFE7" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2FCFE7" Ref="C15" Part="1"
F 0 "C15" H 9300 2150 50 0000 L CNN
F 1 "100n" H 9300 1950 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9338 1900 50 0001 C CNN
F 3 "~" H 9300 2050 50 0001 C CNN
1 9300 2050
1 0 0 -1
$EndComp
Wire Wire Line
9300 1900 9300 1800
Wire Wire Line
9300 1800 9500 1800
Connection ~ 9500 1800
Wire Wire Line
9500 2300 9300 2300
Wire Wire Line
9300 2300 9300 2200
Connection ~ 9500 2300
Wire Wire Line
10100 2300 10300 2300
Wire Wire Line
10300 2300 10300 2200
Connection ~ 10100 2300
Wire Wire Line
10300 1900 10300 1800
Wire Wire Line
10300 1800 10100 1800
Connection ~ 10100 1800
Text Label 9600 4050 0 50 ~ 0
lut_out_a
Text Label 9600 4250 0 50 ~ 0
lut_out_c
Text Label 9600 4450 0 50 ~ 0
lut_out_b
Text Label 9600 4650 0 50 ~ 0
lut_out_b_async
Wire Wire Line
2550 2400 2550 2600
$Comp
L Device:C C?
U 1 1 5D182B36
P 9100 2050
AR Path="/5D77FDBE/5D182B36" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D182B36" Ref="C14" Part="1"
F 0 "C14" H 9100 2150 50 0000 L CNN
F 1 "100n" H 9100 1950 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9138 1900 50 0001 C CNN
F 3 "~" H 9100 2050 50 0001 C CNN
1 9100 2050
1 0 0 -1
$EndComp
Wire Wire Line
9100 2200 9100 2300
Wire Wire Line
9100 2300 9300 2300
Connection ~ 9300 2300
Wire Wire Line
9100 1900 9100 1800
Wire Wire Line
9100 1800 9300 1800
Connection ~ 9300 1800
$Comp
L power:VCC #PWR?
U 1 1 5D2EACE1
P 9700 1700
AR Path="/5D77FDBE/5D2EACE1" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACE1" Ref="#PWR051" Part="1"
F 0 "#PWR051" H 9700 1550 50 0001 C CNN
F 1 "VCC" H 9717 1873 50 0000 C CNN
F 2 "" H 9700 1700 50 0001 C CNN
F 3 "" H 9700 1700 50 0001 C CNN
1 9700 1700
1 0 0 -1
$EndComp
Wire Wire Line
9700 1800 9900 1800
Wire Wire Line
9700 2300 9900 2300
Wire Wire Line
9700 1700 9700 1800
Wire Wire Line
9700 2400 9700 2300
Wire Notes Line
3950 4400 3950 4550
Wire Notes Line
3950 4550 3900 4500
Wire Notes Line
3950 4550 4000 4500
Wire Wire Line
2000 1350 8100 1350
Text HLabel 2000 2150 0 50 Input ~ 0
lut_in3_n
Text Label 3950 2150 2 50 ~ 0
lut_b_en_n
$Comp
L Device:R R15
U 1 1 5D4D5C26
P 4150 2150
F 0 "R15" H 4220 2196 50 0000 L CNN
F 1 "10k" H 4220 2105 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 4080 2150 50 0001 C CNN
F 3 "~" H 4150 2150 50 0001 C CNN
1 4150 2150
1 0 0 -1
$EndComp
Connection ~ 4150 2400
Wire Wire Line
4150 2400 4150 3100
Wire Wire Line
2000 1650 3500 1650
Wire Wire Line
4150 1650 4150 2000
Wire Wire Line
2550 2400 3650 2400
Wire Wire Line
4150 2400 3950 2400
$Comp
L Device:D_Schottky D11
U 1 1 5D50C782
P 3800 2400
F 0 "D11" H 3800 2500 50 0000 C CNN
F 1 "D_Schottky" H 3800 2300 50 0000 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 3800 2400 50 0001 C CNN
F 3 "~" H 3800 2400 50 0001 C CNN
1 3800 2400
1 0 0 -1
$EndComp
Wire Wire Line
4150 2300 4150 2400
Text Label 4550 2400 2 50 ~ 0
lut_a_en_n
$Comp
L Device:R R14
U 1 1 5D544A69
P 3500 1900
F 0 "R14" H 3570 1946 50 0000 L CNN
F 1 "10k" H 3570 1855 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 3430 1900 50 0001 C CNN
F 3 "~" H 3500 1900 50 0001 C CNN
1 3500 1900
1 0 0 -1
$EndComp
$Comp
L Device:D_Schottky D10
U 1 1 5D544D70
P 3150 2150
F 0 "D10" H 3150 2250 50 0000 C CNN
F 1 "D_Schottky" H 3150 2050 50 0000 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 3150 2150 50 0001 C CNN
F 3 "~" H 3150 2150 50 0001 C CNN
1 3150 2150
1 0 0 -1
$EndComp
Wire Wire Line
3300 2150 3500 2150
Wire Wire Line
3500 2150 3500 2050
Wire Wire Line
2000 2150 3000 2150
Wire Wire Line
3500 1750 3500 1650
Connection ~ 3500 1650
Wire Wire Line
3500 1650 4150 1650
Connection ~ 3500 2150
Wire Wire Line
3500 2150 3950 2150
Wire Wire Line
4150 2400 4550 2400
$Comp
L power:VCC #PWR?
U 1 1 5D6F060A
P 2450 3100
AR Path="/5CF41639/5D6F060A" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D6F060A" Ref="#PWR056" Part="1"
F 0 "#PWR056" H 2450 2950 50 0001 C CNN
F 1 "VCC" H 2467 3273 50 0000 C CNN
F 2 "" H 2450 3100 50 0001 C CNN
F 3 "" H 2450 3100 50 0001 C CNN
1 2450 3100
1 0 0 -1
$EndComp
Wire Wire Line
2450 3100 2450 3200
Wire Wire Line
2450 3200 2550 3200
$Comp
L power:VCC #PWR?
U 1 1 5D6F756A
P 2550 4650
AR Path="/5CF41639/5D6F756A" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D6F756A" Ref="#PWR067" Part="1"
F 0 "#PWR067" H 2550 4500 50 0001 C CNN
F 1 "VCC" H 2567 4823 50 0000 C CNN
F 2 "" H 2550 4650 50 0001 C CNN
F 3 "" H 2550 4650 50 0001 C CNN
1 2550 4650
1 0 0 -1
$EndComp
Wire Wire Line
2550 4650 2550 4750
$Comp
L Device:D_Schottky D12
U 1 1 5D7F6986
P 5800 3650
F 0 "D12" H 5800 3750 50 0000 C CNN
F 1 "D_Schottky" H 5800 3550 50 0000 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 5800 3650 50 0001 C CNN
F 3 "~" H 5800 3650 50 0001 C CNN
1 5800 3650
0 -1 -1 0
$EndComp
$Comp
L Device:D_Schottky D13
U 1 1 5D7F6FF8
P 5800 4500
F 0 "D13" H 5800 4600 50 0000 C CNN
F 1 "D_Schottky" H 5800 4400 50 0000 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 5800 4500 50 0001 C CNN
F 3 "~" H 5800 4500 50 0001 C CNN
1 5800 4500
0 1 1 0
$EndComp
Wire Notes Line
3950 4400 4000 4350
Wire Notes Line
4000 2300 4050 2250
Wire Notes Line
4000 2300 3950 2250
Wire Notes Line
4000 2150 3950 2150
Wire Notes Line
4000 2150 4000 2300
Wire Bus Line
2000 2700 3850 2700
Wire Bus Line
3850 2700 3850 4950
$EndSCHEMATC

3
kicad_pcb/sym-lib-table
View File

@ -1,3 +0,0 @@
(sym_lib_table
(lib (name ttl-fpga-rescue)(type Legacy)(uri ${KIPRJMOD}/ttl-fpga-rescue.lib)(options "")(descr ""))
)

438
kicad_pcb/ttl-fpga-cache.lib
View File

@ -1,438 +0,0 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 4xxx_4066
#
DEF 4xxx_4066 U 0 40 Y Y 5 L N
F0 "U" -300 350 50 H V C CNN
F1 "4xxx_4066" -300 -350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 4066
$FPLIST
DIP?14*
$ENDFPLIST
DRAW
S -200 300 200 -300 5 1 10 f
P 2 1 0 6 0 50 0 100 N
P 4 1 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 1 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 2 0 6 0 50 0 100 N
P 4 2 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 2 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 3 0 6 0 50 0 100 N
P 4 3 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 3 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 4 0 6 0 50 0 100 N
P 4 4 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 4 0 0 -100 100 100 0 -100 -100 -100 100 f
X ~ 1 -300 0 200 R 50 50 1 0 P
X ~ 13 0 300 200 D 50 50 1 0 I
X ~ 2 300 0 200 L 50 50 1 0 P
X ~ 3 300 0 200 L 50 50 2 0 P
X ~ 4 -300 0 200 R 50 50 2 0 P
X ~ 5 0 300 200 D 50 50 2 0 I
X ~ 6 0 300 200 D 50 50 3 0 I
X ~ 8 -300 0 200 R 50 50 3 0 P
X ~ 9 300 0 200 L 50 50 3 0 P
X ~ 10 300 0 200 L 50 50 4 0 P
X ~ 11 -300 0 200 R 50 50 4 0 P
X ~ 12 0 300 200 D 50 50 4 0 I
X VDD 14 0 500 200 D 50 50 5 0 W
X VSS 7 0 -500 200 U 50 50 5 0 W
ENDDRAW
ENDDEF
#
# 74xx_74LS174
#
DEF 74xx_74LS174 U 0 40 Y Y 1 L N
F0 "U" -300 550 50 H V C CNN
F1 "74xx_74LS174" -300 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP?16*
$ENDFPLIST
DRAW
S -300 500 300 -600 1 1 10 f
X ~Mr 1 -500 -500 200 R 50 50 1 0 I
X Q3 10 500 100 200 L 50 50 1 0 O
X D3 11 -500 100 200 R 50 50 1 0 I
X Q4 12 500 0 200 L 50 50 1 0 O
X D4 13 -500 0 200 R 50 50 1 0 I
X D5 14 -500 -100 200 R 50 50 1 0 I
X Q5 15 500 -100 200 L 50 50 1 0 O
X VCC 16 0 700 200 D 50 50 1 0 W
X Q0 2 500 400 200 L 50 50 1 0 O
X D0 3 -500 400 200 R 50 50 1 0 I
X D1 4 -500 300 200 R 50 50 1 0 I
X Q1 5 500 300 200 L 50 50 1 0 O
X D2 6 -500 200 200 R 50 50 1 0 I
X Q2 7 500 200 200 L 50 50 1 0 O
X GND 8 0 -800 200 U 50 50 1 0 W
X Cp 9 -500 -300 200 R 50 50 1 0 I C
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74157
#
DEF 74xx_IEEE_74157 U 0 30 Y Y 1 F N
F0 "U" 300 400 50 H V C CNN
F1 "74xx_IEEE_74157" 250 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 100 60 0 0 0 MUX Normal 0 C C
S -250 -400 250 -600 0 0 0 N
S -250 -200 250 -400 0 0 0 N
S -250 0 250 -200 0 0 0 N
S -250 200 250 0 0 0 0 N
P 9 0 0 0 -200 200 -200 250 -250 250 -250 500 250 500 250 250 200 250 200 200 200 200 N
X VCC 16 150 500 0 D 50 50 0 0 W N
X GND 8 0 500 0 D 50 50 0 0 W N
X A/B 1 -550 300 300 R 50 50 1 1 I
X I1d 10 -550 -550 300 R 50 50 1 1 I
X I0d 11 -550 -450 300 R 50 50 1 1 I
X Qc 12 550 -300 300 L 50 50 1 1 O
X I1c 13 -550 -350 300 R 50 50 1 1 I
X I0c 14 -550 -250 300 R 50 50 1 1 I
X ~EN 15 -550 400 300 R 50 50 1 1 I I
X I0a 2 -550 150 300 R 50 50 1 1 I
X I1a 3 -550 50 300 R 50 50 1 1 I
X Qa 4 550 100 300 L 50 50 1 1 O
X I0b 5 -550 -50 300 R 50 50 1 1 I
X I1b 6 -550 -150 300 R 50 50 1 1 I
X Qb 7 550 -100 300 L 50 50 1 1 O
X Qd 9 550 -500 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74164
#
DEF 74xx_IEEE_74164 U 0 30 Y Y 1 F N
F0 "U" 350 250 50 H V C CNN
F1 "74xx_IEEE_74164" 250 -900 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 -170 -40 60 0 0 0 & Normal 0 C C
S -250 -750 250 -850 0 1 0 N
S -250 -650 250 -750 0 1 0 N
S -250 -550 250 -650 0 1 0 N
S -250 -450 250 -550 0 1 0 N
S -250 -350 250 -450 0 1 0 N
S -250 -250 250 -350 0 1 0 N
S -250 -150 250 -250 0 1 0 N
S -250 50 250 -150 0 1 0 N
P 3 0 1 0 -100 50 -100 -150 -100 -150 N
P 9 0 1 0 -200 50 -200 100 -250 100 -250 350 250 350 250 100 200 100 200 50 200 50 N
X A 1 -550 0 300 R 50 50 1 1 I
X Qe 10 550 -500 300 L 50 50 1 1 O
X Qf 11 550 -600 300 L 50 50 1 1 O
X Qg 12 550 -700 300 L 50 50 1 1 O
X Qh 13 550 -800 300 L 50 50 1 1 O
X Vdd 14 200 350 0 D 50 50 1 1 W N
X B 2 -550 -100 300 R 50 50 1 1 I
X Qa 3 550 -50 300 L 50 50 1 1 O
X Qb 4 550 -200 300 L 50 50 1 1 O
X Qc 5 550 -300 300 L 50 50 1 1 O
X Qd 6 550 -400 300 L 50 50 1 1 O
X Vss 7 0 350 0 D 50 50 1 1 W N
X CK 8 -550 150 300 R 50 50 1 1 I C
X ~R 9 -550 250 300 R 50 50 1 1 I I
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74251
#
DEF 74xx_IEEE_74251 U 0 30 Y Y 1 F N
F0 "U" 300 600 50 H V C CNN
F1 "74xx_IEEE_74251" 350 -800 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 250 50 0 0 0 MUX Normal 0 C C
S -250 650 250 -700 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 380 20 380 50 320 80 380 80 380 N
X VCC 16 0 650 0 D 50 50 0 0 W N
X GND 8 0 -700 0 U 50 50 0 0 W N
X I3 1 -550 -200 300 R 50 50 1 1 I
X S1 10 -550 350 300 R 50 50 1 1 I
X S0 11 -550 450 300 R 50 50 1 1 I
X I7 12 -550 -600 300 R 50 50 1 1 I
X I6 13 -550 -500 300 R 50 50 1 1 I
X I5 14 -550 -400 300 R 50 50 1 1 I
X I4 15 -550 -300 300 R 50 50 1 1 I
X I2 2 -550 -100 300 R 50 50 1 1 I
X I1 3 -550 0 300 R 50 50 1 1 I
X I0 4 -550 100 300 R 50 50 1 1 I
X Q 5 550 350 300 L 50 50 1 1 T
X ~Q 6 550 -350 300 L 50 50 1 1 T I
X ~E 7 -550 550 300 R 50 50 1 1 I I
X S2 9 -550 250 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74253
#
DEF 74xx_IEEE_74253 U 0 30 Y Y 1 F N
F0 "U" 300 650 50 H V C CNN
F1 "74xx_IEEE_74253" 150 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 300 60 0 0 0 MUX Normal 0 C C
S -250 -100 250 -600 0 0 0 N
S -250 450 250 -100 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 180 20 180 50 120 80 180 80 180 N
P 9 0 0 0 -200 450 -200 500 -250 500 -250 750 250 750 250 500 200 500 200 450 200 450 N
X VCC 16 150 750 0 D 50 50 0 0 W N
X GND 8 0 750 0 D 50 50 0 0 W N
X ~ENa 1 -550 350 300 R 50 50 1 1 I I
X I0b 10 -550 -250 300 R 50 50 1 1 I
X I1b 11 -550 -350 300 R 50 50 1 1 I
X I2b 12 -550 -450 300 R 50 50 1 1 I
X I3b 13 -550 -550 300 R 50 50 1 1 I
X A 14 -550 650 300 R 50 50 1 1 I
X ~ENb 15 -550 -150 300 R 50 50 1 1 I I
X B 2 -550 550 300 R 50 50 1 1 I
X I3a 3 -550 -50 300 R 50 50 1 1 I
X I2a 4 -550 50 300 R 50 50 1 1 I
X I1a 5 -550 150 300 R 50 50 1 1 I
X I0a 6 -550 250 300 R 50 50 1 1 I
X Qa 7 550 150 300 L 50 50 1 1 T
X Qb 9 550 -350 300 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# Connector_Conn_01x12_Female
#
DEF Connector_Conn_01x12_Female J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Connector_Conn_01x12_Female" 0 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
A 0 -600 20 901 -901 1 1 6 N 0 -580 0 -620
A 0 -500 20 901 -901 1 1 6 N 0 -480 0 -520
A 0 -400 20 901 -901 1 1 6 N 0 -380 0 -420
A 0 -300 20 901 -901 1 1 6 N 0 -280 0 -320
A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
A 0 100 20 901 -901 1 1 6 N 0 120 0 80
A 0 200 20 901 -901 1 1 6 N 0 220 0 180
A 0 300 20 901 -901 1 1 6 N 0 320 0 280
A 0 400 20 901 -901 1 1 6 N 0 420 0 380
A 0 500 20 901 -901 1 1 6 N 0 520 0 480
P 2 1 1 6 -50 -600 -20 -600 N
P 2 1 1 6 -50 -500 -20 -500 N
P 2 1 1 6 -50 -400 -20 -400 N
P 2 1 1 6 -50 -300 -20 -300 N
P 2 1 1 6 -50 -200 -20 -200 N
P 2 1 1 6 -50 -100 -20 -100 N
P 2 1 1 6 -50 0 -20 0 N
P 2 1 1 6 -50 100 -20 100 N
P 2 1 1 6 -50 200 -20 200 N
P 2 1 1 6 -50 300 -20 300 N
P 2 1 1 6 -50 400 -20 400 N
P 2 1 1 6 -50 500 -20 500 N
X Pin_1 1 -200 500 150 R 50 50 1 1 P
X Pin_10 10 -200 -400 150 R 50 50 1 1 P
X Pin_11 11 -200 -500 150 R 50 50 1 1 P
X Pin_12 12 -200 -600 150 R 50 50 1 1 P
X Pin_2 2 -200 400 150 R 50 50 1 1 P
X Pin_3 3 -200 300 150 R 50 50 1 1 P
X Pin_4 4 -200 200 150 R 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 -200 0 150 R 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 -200 -200 150 R 50 50 1 1 P
X Pin_9 9 -200 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Conn_01x12_Male
#
DEF Connector_Conn_01x12_Male J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Connector_Conn_01x12_Male" 0 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S 34 -595 0 -605 1 1 6 F
S 34 -495 0 -505 1 1 6 F
S 34 -395 0 -405 1 1 6 F
S 34 -295 0 -305 1 1 6 F
S 34 -195 0 -205 1 1 6 F
S 34 -95 0 -105 1 1 6 F
S 34 5 0 -5 1 1 6 F
S 34 105 0 95 1 1 6 F
S 34 205 0 195 1 1 6 F
S 34 305 0 295 1 1 6 F
S 34 405 0 395 1 1 6 F
S 34 505 0 495 1 1 6 F
P 2 1 1 6 50 -600 34 -600 N
P 2 1 1 6 50 -500 34 -500 N
P 2 1 1 6 50 -400 34 -400 N
P 2 1 1 6 50 -300 34 -300 N
P 2 1 1 6 50 -200 34 -200 N
P 2 1 1 6 50 -100 34 -100 N
P 2 1 1 6 50 0 34 0 N
P 2 1 1 6 50 100 34 100 N
P 2 1 1 6 50 200 34 200 N
P 2 1 1 6 50 300 34 300 N
P 2 1 1 6 50 400 34 400 N
P 2 1 1 6 50 500 34 500 N
X Pin_1 1 200 500 150 L 50 50 1 1 P
X Pin_10 10 200 -400 150 L 50 50 1 1 P
X Pin_11 11 200 -500 150 L 50 50 1 1 P
X Pin_12 12 200 -600 150 L 50 50 1 1 P
X Pin_2 2 200 400 150 L 50 50 1 1 P
X Pin_3 3 200 300 150 L 50 50 1 1 P
X Pin_4 4 200 200 150 L 50 50 1 1 P
X Pin_5 5 200 100 150 L 50 50 1 1 P
X Pin_6 6 200 0 150 L 50 50 1 1 P
X Pin_7 7 200 -100 150 L 50 50 1 1 P
X Pin_8 8 200 -200 150 L 50 50 1 1 P
X Pin_9 9 200 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Schottky
#
DEF Device_D_Schottky D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_D_Schottky" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_GNDD
#
DEF power_GNDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GNDD" 0 -125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -50 -60 50 -80 0 1 10 F
P 2 0 1 0 0 0 0 -60 N
X GNDD 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VCC
#
DEF power_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

3
kicad_pcb/ttl-fpga-rescue.dcm
View File

@ -1,3 +0,0 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

236
kicad_pcb/ttl-fpga-rescue.lib
View File

@ -1,236 +0,0 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 4066-4xxx
#
DEF 4066-4xxx U 0 40 Y Y 5 L N
F0 "U" -300 350 50 H V C CNN
F1 "4066-4xxx" -300 -350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP?14*
$ENDFPLIST
DRAW
S -200 300 200 -300 5 1 10 f
P 2 1 0 6 0 50 0 100 N
P 4 1 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 1 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 2 0 6 0 50 0 100 N
P 4 2 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 2 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 3 0 6 0 50 0 100 N
P 4 3 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 3 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 4 0 6 0 50 0 100 N
P 4 4 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 4 0 0 -100 100 100 0 -100 -100 -100 100 f
X ~ 1 -300 0 200 R 50 50 1 0 P
X ~ 13 0 300 200 D 50 50 1 0 I
X ~ 2 300 0 200 L 50 50 1 0 P
X ~ 3 300 0 200 L 50 50 2 0 P
X ~ 4 -300 0 200 R 50 50 2 0 P
X ~ 5 0 300 200 D 50 50 2 0 I
X ~ 6 0 300 200 D 50 50 3 0 I
X ~ 8 -300 0 200 R 50 50 3 0 P
X ~ 9 300 0 200 L 50 50 3 0 P
X ~ 10 300 0 200 L 50 50 4 0 P
X ~ 11 -300 0 200 R 50 50 4 0 P
X ~ 12 0 300 200 D 50 50 4 0 I
X VDD 14 0 500 200 D 50 50 5 0 W
X VSS 7 0 -500 200 U 50 50 5 0 W
ENDDRAW
ENDDEF
#
# 74157-74xx_IEEE
#
DEF 74157-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 300 400 50 H V C CNN
F1 "74157-74xx_IEEE" 250 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 100 60 0 0 0 MUX Normal 0 C C
S -250 -400 250 -600 0 0 0 N
S -250 -200 250 -400 0 0 0 N
S -250 0 250 -200 0 0 0 N
S -250 200 250 0 0 0 0 N
P 9 0 0 0 -200 200 -200 250 -250 250 -250 500 250 500 250 250 200 250 200 200 200 200 N
X VCC 16 150 500 0 D 50 50 0 0 W N
X GND 8 0 500 0 D 50 50 0 0 W N
X A/B 1 -550 300 300 R 50 50 1 1 I
X I1d 10 -550 -550 300 R 50 50 1 1 I
X I0d 11 -550 -450 300 R 50 50 1 1 I
X Qc 12 550 -300 300 L 50 50 1 1 O
X I1c 13 -550 -350 300 R 50 50 1 1 I
X I0c 14 -550 -250 300 R 50 50 1 1 I
X ~EN 15 -550 400 300 R 50 50 1 1 I I
X I0a 2 -550 150 300 R 50 50 1 1 I
X I1a 3 -550 50 300 R 50 50 1 1 I
X Qa 4 550 100 300 L 50 50 1 1 O
X I0b 5 -550 -50 300 R 50 50 1 1 I
X I1b 6 -550 -150 300 R 50 50 1 1 I
X Qb 7 550 -100 300 L 50 50 1 1 O
X Qd 9 550 -500 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# 74164-74xx_IEEE
#
DEF 74164-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 350 250 50 H V C CNN
F1 "74164-74xx_IEEE" 250 -900 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 -170 -40 60 0 0 0 & Normal 0 C C
S -250 -750 250 -850 0 1 0 N
S -250 -650 250 -750 0 1 0 N
S -250 -550 250 -650 0 1 0 N
S -250 -450 250 -550 0 1 0 N
S -250 -350 250 -450 0 1 0 N
S -250 -250 250 -350 0 1 0 N
S -250 -150 250 -250 0 1 0 N
S -250 50 250 -150 0 1 0 N
P 3 0 1 0 -100 50 -100 -150 -100 -150 N
P 9 0 1 0 -200 50 -200 100 -250 100 -250 350 250 350 250 100 200 100 200 50 200 50 N
X A 1 -550 0 300 R 50 50 1 1 I
X Qe 10 550 -500 300 L 50 50 1 1 O
X Qf 11 550 -600 300 L 50 50 1 1 O
X Qg 12 550 -700 300 L 50 50 1 1 O
X Qh 13 550 -800 300 L 50 50 1 1 O
X Vdd 14 200 350 0 D 50 50 1 1 W N
X B 2 -550 -100 300 R 50 50 1 1 I
X Qa 3 550 -50 300 L 50 50 1 1 O
X Qb 4 550 -200 300 L 50 50 1 1 O
X Qc 5 550 -300 300 L 50 50 1 1 O
X Qd 6 550 -400 300 L 50 50 1 1 O
X Vss 7 0 350 0 D 50 50 1 1 W N
X CK 8 -550 150 300 R 50 50 1 1 I C
X ~R 9 -550 250 300 R 50 50 1 1 I I
ENDDRAW
ENDDEF
#
# 74251-74xx_IEEE
#
DEF 74251-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 300 600 50 H V C CNN
F1 "74251-74xx_IEEE" 350 -800 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 250 50 0 0 0 MUX Normal 0 C C
S -250 650 250 -700 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 380 20 380 50 320 80 380 80 380 N
X VCC 16 0 650 0 D 50 50 0 0 W N
X GND 8 0 -700 0 U 50 50 0 0 W N
X I3 1 -550 -200 300 R 50 50 1 1 I
X S1 10 -550 350 300 R 50 50 1 1 I
X S0 11 -550 450 300 R 50 50 1 1 I
X I7 12 -550 -600 300 R 50 50 1 1 I
X I6 13 -550 -500 300 R 50 50 1 1 I
X I5 14 -550 -400 300 R 50 50 1 1 I
X I4 15 -550 -300 300 R 50 50 1 1 I
X I2 2 -550 -100 300 R 50 50 1 1 I
X I1 3 -550 0 300 R 50 50 1 1 I
X I0 4 -550 100 300 R 50 50 1 1 I
X Q 5 550 350 300 L 50 50 1 1 T
X ~Q 6 550 -350 300 L 50 50 1 1 T I
X ~E 7 -550 550 300 R 50 50 1 1 I I
X S2 9 -550 250 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 74253-74xx_IEEE
#
DEF 74253-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 300 650 50 H V C CNN
F1 "74253-74xx_IEEE" 150 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 300 60 0 0 0 MUX Normal 0 C C
S -250 -100 250 -600 0 0 0 N
S -250 450 250 -100 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 180 20 180 50 120 80 180 80 180 N
P 9 0 0 0 -200 450 -200 500 -250 500 -250 750 250 750 250 500 200 500 200 450 200 450 N
X VCC 16 150 750 0 D 50 50 0 0 W N
X GND 8 0 750 0 D 50 50 0 0 W N
X ~ENa 1 -550 350 300 R 50 50 1 1 I I
X I0b 10 -550 -250 300 R 50 50 1 1 I
X I1b 11 -550 -350 300 R 50 50 1 1 I
X I2b 12 -550 -450 300 R 50 50 1 1 I
X I3b 13 -550 -550 300 R 50 50 1 1 I
X A 14 -550 650 300 R 50 50 1 1 I
X ~ENb 15 -550 -150 300 R 50 50 1 1 I I
X B 2 -550 550 300 R 50 50 1 1 I
X I3a 3 -550 -50 300 R 50 50 1 1 I
X I2a 4 -550 50 300 R 50 50 1 1 I
X I1a 5 -550 150 300 R 50 50 1 1 I
X I0a 6 -550 250 300 R 50 50 1 1 I
X Qa 7 550 150 300 L 50 50 1 1 T
X Qb 9 550 -350 300 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# D_ALT-Device
#
DEF D_ALT-Device D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D_ALT-Device" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 50 -50 -50 N
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 F
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Q_NPN_BCE-Device
#
DEF Q_NPN_BCE-Device Q 0 0 Y N 1 F N
F0 "Q" 200 50 50 H V L CNN
F1 "Q_NPN_BCE-Device" 200 -50 50 H V L CNN
F2 "" 200 100 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 225 R 50 50 1 1 I
X C 2 100 200 100 D 50 50 1 1 P
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# R-Device
#
DEF R-Device R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R-Device" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

238
kicad_pcb/ttl-fpga.pro
View File

@ -1,238 +0,0 @@
update=Sat 01 Jun 2019 09:25:42 PM CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=ttl-fpga.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
ViaDiameter1=0.6
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

605
kicad_pcb/ttl-fpga.sch
View File

@ -1,605 +0,0 @@
EESchema Schematic File Version 4
LIBS:ttl-fpga-cache
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "02"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "PCB"
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
8000 3350 7900 3350
Wire Wire Line
7900 3350 7900 3250
$Comp
L power:VCC #PWR04
U 1 1 5FF9C392
P 7900 3250
F 0 "#PWR04" H 7900 3100 50 0001 C CNN
F 1 "VCC" H 7917 3423 50 0000 C CNN
F 2 "" H 7900 3250 50 0001 C CNN
F 3 "" H 7900 3250 50 0001 C CNN
1 7900 3250
-1 0 0 -1
$EndComp
$Comp
L power:GNDD #PWR06
U 1 1 5FF9C39C
P 7800 3450
F 0 "#PWR06" H 7800 3200 50 0001 C CNN
F 1 "GNDD" V 7804 3340 50 0000 R CNN
F 2 "" H 7800 3450 50 0001 C CNN
F 3 "" H 7800 3450 50 0001 C CNN
1 7800 3450
0 1 -1 0
$EndComp
Wire Wire Line
7800 3450 8000 3450
Wire Wire Line
7200 3750 7200 3300
Wire Wire Line
8000 3750 7200 3750
Wire Wire Line
7300 3650 7300 3100
Wire Wire Line
8000 3650 7300 3650
Wire Wire Line
7400 3550 7400 3000
Wire Wire Line
8000 3550 7400 3550
Text Label 7550 4450 0 50 ~ 0
fabric_r3
Text Label 7550 4350 0 50 ~ 0
fabric_r2
Text Label 7550 4250 0 50 ~ 0
fabric_r1
Text Label 7550 4150 0 50 ~ 0
fabric_r0
Wire Wire Line
8000 4450 7550 4450
Wire Wire Line
8000 4350 7550 4350
Wire Wire Line
8000 4250 7550 4250
Wire Wire Line
8000 4150 7550 4150
Entry Wire Line
7550 4350 7450 4450
Entry Wire Line
7550 4250 7450 4350
Entry Wire Line
7550 4150 7450 4250
Entry Wire Line
7550 4450 7450 4550
Wire Bus Line
7450 4550 6800 4550
Wire Wire Line
4450 3300 4450 3250
Wire Wire Line
5000 3250 5000 3300
Wire Wire Line
5000 3300 5650 3300
Wire Wire Line
4450 3250 5000 3250
Connection ~ 4450 3300
Wire Wire Line
4450 3300 4550 3300
Wire Wire Line
4450 3100 4450 3050
Wire Wire Line
4450 3050 5000 3050
Wire Wire Line
5000 3050 5000 3100
Wire Wire Line
5000 3100 5550 3100
Connection ~ 4450 3100
Wire Wire Line
4450 3100 4550 3100
Wire Wire Line
4950 3000 4950 2950
Wire Wire Line
4950 2950 4450 2950
Wire Wire Line
4950 3000 5450 3000
Wire Wire Line
4450 3000 4550 3000
Wire Wire Line
4450 2950 4450 3000
Connection ~ 4450 3000
Wire Wire Line
4200 3400 4300 3400
Wire Wire Line
3900 3000 4450 3000
Wire Wire Line
4000 3100 4450 3100
Wire Wire Line
4100 3300 4450 3300
Entry Wire Line
3900 4250 3800 4150
Entry Wire Line
3900 4550 3800 4450
Entry Wire Line
3900 4450 3800 4350
Entry Wire Line
3900 4350 3800 4250
Wire Wire Line
3350 4150 3800 4150
Wire Wire Line
3350 4250 3800 4250
Wire Wire Line
3350 4350 3800 4350
Wire Wire Line
3350 4450 3800 4450
Text Label 3800 4150 2 50 ~ 0
fabric_l0
Text Label 3800 4250 2 50 ~ 0
fabric_l1
Text Label 3800 4350 2 50 ~ 0
fabric_l2
Text Label 3800 4450 2 50 ~ 0
fabric_l3
Wire Wire Line
3350 3550 3900 3550
Wire Wire Line
3900 3550 3900 3000
Wire Wire Line
3350 3650 4000 3650
Wire Wire Line
4000 3650 4000 3100
Wire Wire Line
3350 3750 4100 3750
Wire Wire Line
4100 3750 4100 3300
Wire Wire Line
3350 3850 4200 3850
Wire Wire Line
4200 3850 4200 3400
Wire Wire Line
3550 3450 3350 3450
$Comp
L power:GNDD #PWR05
U 1 1 5FE8BD0F
P 3550 3450
F 0 "#PWR05" H 3550 3200 50 0001 C CNN
F 1 "GNDD" V 3554 3340 50 0000 R CNN
F 2 "" H 3550 3450 50 0001 C CNN
F 3 "" H 3550 3450 50 0001 C CNN
1 3550 3450
0 -1 -1 0
$EndComp
$Comp
L power:VCC #PWR03
U 1 1 5FE8B843
P 3450 3250
F 0 "#PWR03" H 3450 3100 50 0001 C CNN
F 1 "VCC" H 3467 3423 50 0000 C CNN
F 2 "" H 3450 3250 50 0001 C CNN
F 3 "" H 3450 3250 50 0001 C CNN
1 3450 3250
1 0 0 -1
$EndComp
Wire Wire Line
3450 3350 3450 3250
Wire Wire Line
3350 3350 3450 3350
Wire Wire Line
6800 3400 7100 3400
Text Label 3950 4550 0 50 ~ 0
fabric_l[3..0]
Wire Wire Line
7100 3400 7100 3850
Wire Wire Line
7100 3850 8000 3850
Wire Wire Line
3350 3950 8000 3950
Text Notes 3100 4500 2 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI\nMISO\nMOSI_D\nI0\nI1\nI2\nI3
Text Notes 8250 4500 0 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nmiso\nmosi\n\nI0\nI1\nI2\nI3
Wire Wire Line
5250 5600 5250 5550
$Comp
L power:VCC #PWR012
U 1 1 60046AFF
P 5250 5550
F 0 "#PWR012" H 5250 5400 50 0001 C CNN
F 1 "VCC" H 5150 5650 50 0000 C CNN
F 2 "" H 5250 5550 50 0001 C CNN
F 3 "" H 5250 5550 50 0001 C CNN
1 5250 5550
1 0 0 -1
$EndComp
$Comp
L power:GNDD #PWR09
U 1 1 60046AF5
P 5200 5200
F 0 "#PWR09" H 5200 4950 50 0001 C CNN
F 1 "GNDD" H 5204 5045 50 0000 C CNN
F 2 "" H 5200 5200 50 0001 C CNN
F 3 "" H 5200 5200 50 0001 C CNN
1 5200 5200
1 0 0 -1
$EndComp
Wire Wire Line
5200 5150 5350 5150
Wire Wire Line
5350 5150 5350 5600
Text Label 6350 5150 3 50 ~ 0
fabric_b3
Text Label 6250 5150 3 50 ~ 0
fabric_b2
Text Label 6150 5150 3 50 ~ 0
fabric_b1
Text Label 6050 5150 3 50 ~ 0
fabric_b0
Wire Wire Line
6350 5600 6350 5150
Wire Wire Line
6250 5600 6250 5150
Wire Wire Line
6150 5600 6150 5150
Wire Wire Line
6050 5600 6050 5150
Entry Wire Line
6250 5150 6350 5050
Entry Wire Line
6150 5150 6250 5050
Entry Wire Line
6050 5150 6150 5050
Entry Wire Line
6350 5150 6450 5050
$Sheet
S 4550 2700 2250 2250
U 5D77FDBE
F0 "LogicBlock" 50
F1 "logic_block.sch" 50
F2 "fabric_b[3..0]" I R 6800 4850 50
F3 "fabric_t[3..0]" I R 6800 2800 50
F4 "fabric_l[3..0]" I L 4550 4550 50
F5 "fabric_r[3..0]" I R 6800 4550 50
F6 "rst_n" I L 4550 3100 50
F7 "clk" I L 4550 3000 50
F8 "isp_mosi" I L 4550 3400 50
F9 "isp_sck" I L 4550 3300 50
F10 "isp_miso" O R 6800 3400 50
$EndSheet
Wire Bus Line
6800 4850 6900 4850
Wire Bus Line
6900 4850 6900 5050
Wire Wire Line
5450 5600 5450 3000
Connection ~ 5450 3000
Wire Wire Line
5450 3000 7400 3000
Wire Wire Line
5550 5600 5550 3100
Connection ~ 5550 3100
Wire Wire Line
5550 3100 7300 3100
Wire Wire Line
5650 5600 5650 3300
Connection ~ 5650 3300
Wire Bus Line
3900 4550 4550 4550
Wire Wire Line
5750 4050 5750 5600
Wire Wire Line
3350 4050 5750 4050
Text Notes 6400 5850 3 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI0\nI1\nI2\nI3
$Comp
L Connector:Conn_01x12_Female J4
U 1 1 60090C3D
P 5750 5800
F 0 "J4" H 5700 6400 50 0000 C CNN
F 1 "Bottom" V 5650 5050 50 0000 C CNN
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 5750 5800 50 0001 C CNN
F 3 "~" H 5750 5800 50 0001 C CNN
1 5750 5800
0 -1 1 0
$EndComp
Text Notes 6400 1800 1 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI0\nI1\nI2\nI3
$Comp
L power:VCC #PWR01
U 1 1 600A7963
P 5150 2150
F 0 "#PWR01" H 5150 2000 50 0001 C CNN
F 1 "VCC" H 5250 2200 50 0000 C CNN
F 2 "" H 5150 2150 50 0001 C CNN
F 3 "" H 5150 2150 50 0001 C CNN
1 5150 2150
-1 0 0 -1
$EndComp
Wire Wire Line
5250 2250 5150 2250
Wire Wire Line
5250 2050 5250 2250
Text Label 6350 2500 1 50 ~ 0
fabric_t3
Text Label 6250 2500 1 50 ~ 0
fabric_t2
Text Label 6150 2500 1 50 ~ 0
fabric_t1
Text Label 6050 2500 1 50 ~ 0
fabric_t0
Wire Wire Line
6350 2050 6350 2500
Wire Wire Line
6250 2050 6250 2500
Wire Wire Line
6150 2050 6150 2500
Wire Wire Line
6050 2050 6050 2500
Entry Wire Line
6250 2500 6350 2600
Entry Wire Line
6150 2500 6250 2600
Entry Wire Line
6050 2500 6150 2600
Entry Wire Line
6350 2500 6450 2600
Wire Bus Line
6900 2800 6800 2800
Wire Bus Line
6900 2600 6900 2800
Text Label 6250 5050 0 50 ~ 0
fabric_b[3..0]
Text Label 6450 2600 0 50 ~ 0
fabric_t[3..0]
Wire Wire Line
5450 2050 5450 3000
Wire Wire Line
5550 3100 5550 2050
Wire Wire Line
5650 3300 7200 3300
Wire Wire Line
5650 3300 5650 2050
Wire Notes Line
6400 3400 4950 3400
Wire Notes Line
6400 3400 6300 3350
Wire Notes Line
6400 3400 6300 3450
Text Label 6900 4550 0 50 ~ 0
fabric_r[3..0]
Wire Wire Line
5750 2050 5750 2500
Wire Wire Line
5750 2500 4300 2500
Wire Wire Line
4300 2500 4300 3400
Connection ~ 4300 3400
Wire Wire Line
4300 3400 4550 3400
Wire Notes Line
8550 3850 8650 3850
Wire Notes Line
8550 3950 8600 3900
Wire Notes Line
8550 3950 8600 4000
Wire Notes Line
8650 3950 8550 3950
Wire Notes Line
8650 3850 8650 3950
Wire Notes Line
2850 3950 2600 3950
Wire Notes Line
2600 3950 2600 4050
Wire Notes Line
2600 4050 2700 4050
Wire Notes Line
2650 4000 2700 4050
Wire Notes Line
2700 4050 2650 4100
Wire Notes Line
2450 3850 2850 3850
Wire Notes Line
2850 3850 2800 3800
Wire Notes Line
2850 3850 2800 3900
Wire Notes Line
5750 6200 5750 6350
Wire Notes Line
5750 6350 5700 6300
Wire Notes Line
5750 6350 5800 6300
Wire Notes Line
5750 1300 5750 1450
Wire Notes Line
5750 1450 5700 1400
Wire Notes Line
5750 1450 5800 1400
Text Notes 1900 3850 0 50 ~ 0
PROGRAMMER
Wire Notes Line
2850 3750 2450 3750
Wire Notes Line
2850 3750 2800 3700
Wire Notes Line
2850 3750 2800 3800
Wire Notes Line
2450 3650 2450 3950
Wire Notes Line
2450 3950 1850 3950
Wire Notes Line
1850 3950 1850 3650
Wire Notes Line
1850 3650 2450 3650
Wire Wire Line
5850 5600 5850 2050
Wire Wire Line
5350 2250 5350 2050
$Comp
L power:GNDD #PWR02
U 1 1 600A7959
P 5350 2250
F 0 "#PWR02" H 5350 2000 50 0001 C CNN
F 1 "GNDD" H 5354 2095 50 0000 C CNN
F 2 "" H 5350 2250 50 0001 C CNN
F 3 "" H 5350 2250 50 0001 C CNN
1 5350 2250
-1 0 0 -1
$EndComp
Wire Wire Line
5150 2250 5150 2150
Wire Wire Line
5200 5150 5200 5200
NoConn ~ 5950 2050
NoConn ~ 8000 4050
NoConn ~ 5950 5600
Wire Notes Line
3150 1850 8200 1850
Wire Notes Line
8200 1850 8200 5800
Wire Notes Line
8200 5800 3150 5800
Wire Notes Line
3150 5800 3150 1850
$Comp
L Connector:Conn_01x12_Male J1
U 1 1 5CF30EFB
P 5750 1850
F 0 "J1" H 5850 2450 50 0000 R CNN
F 1 "Top" V 5850 1200 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 5750 1850 50 0001 C CNN
F 3 "~" H 5750 1850 50 0001 C CNN
1 5750 1850
0 -1 1 0
$EndComp
$Comp
L Connector:Conn_01x12_Male J3
U 1 1 5CF23FEF
P 8200 3850
F 0 "J3" H 8300 4450 50 0000 R CNN
F 1 "Right" H 8400 3200 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 8200 3850 50 0001 C CNN
F 3 "~" H 8200 3850 50 0001 C CNN
1 8200 3850
-1 0 0 -1
$EndComp
$Comp
L Connector:Conn_01x12_Female J2
U 1 1 5FE88CA2
P 3150 3850
F 0 "J2" H 3100 4450 50 0000 C CNN
F 1 "Left" H 3050 3200 50 0000 C CNN
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 3150 3850 50 0001 C CNN
F 3 "~" H 3150 3850 50 0001 C CNN
1 3150 3850
-1 0 0 -1
$EndComp
$Comp
L Device:CP C1
U 1 1 5CF70F0E
P 3550 5150
F 0 "C1" H 3668 5196 50 0000 L CNN
F 1 "10u" H 3668 5105 50 0000 L CNN
F 2 "Capacitor_SMD:C_1206_3216Metric" H 3588 5000 50 0001 C CNN
F 3 "~" H 3550 5150 50 0001 C CNN
1 3550 5150
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR07
U 1 1 5CF715DB
P 3550 4900
F 0 "#PWR07" H 3550 4750 50 0001 C CNN
F 1 "VCC" H 3567 5073 50 0000 C CNN
F 2 "" H 3550 4900 50 0001 C CNN
F 3 "" H 3550 4900 50 0001 C CNN
1 3550 4900
1 0 0 -1
$EndComp
Wire Wire Line
3550 5000 3550 4900
$Comp
L Device:LED D?
U 1 1 5CFB92E6
P 4150 5200
AR Path="/5D77FDBE/5D7AF013/5CFB92E6" Ref="D?" Part="1"
AR Path="/5D77FDBE/5CFB92E6" Ref="D?" Part="1"
AR Path="/5CFB92E6" Ref="D1" Part="1"
F 0 "D1" V 4200 5100 50 0000 R CNN
F 1 "PWR" V 4100 5100 50 0000 R CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 4150 5200 50 0001 C CNN
F 3 "~" H 4150 5200 50 0001 C CNN
1 4150 5200
0 -1 -1 0
$EndComp
$Comp
L Device:R R?
U 1 1 5CFB92EC
P 3950 5000
AR Path="/5D77FDBE/5D7AF013/5CFB92EC" Ref="R?" Part="1"
AR Path="/5D77FDBE/5CFB92EC" Ref="R?" Part="1"
AR Path="/5CFB92EC" Ref="R1" Part="1"
F 0 "R1" H 4020 5046 50 0000 L CNN
F 1 "470" H 4020 4955 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 3880 5000 50 0001 C CNN
F 3 "~" H 3950 5000 50 0001 C CNN
1 3950 5000
0 -1 -1 0
$EndComp
$Comp
L power:VCC #PWR08
U 1 1 5CFBED78
P 3750 4900
F 0 "#PWR08" H 3750 4750 50 0001 C CNN
F 1 "VCC" H 3767 5073 50 0000 C CNN
F 2 "" H 3750 4900 50 0001 C CNN
F 3 "" H 3750 4900 50 0001 C CNN
1 3750 4900
1 0 0 -1
$EndComp
Wire Wire Line
3800 5000 3750 5000
Wire Wire Line
3750 5000 3750 4900
Wire Wire Line
4100 5000 4150 5000
Wire Wire Line
4150 5000 4150 5050
Wire Wire Line
3550 5400 3550 5300
$Comp
L power:GNDD #PWR010
U 1 1 5CF71B50
P 3550 5400
F 0 "#PWR010" H 3550 5150 50 0001 C CNN
F 1 "GNDD" V 3554 5290 50 0000 R CNN
F 2 "" H 3550 5400 50 0001 C CNN
F 3 "" H 3550 5400 50 0001 C CNN
1 3550 5400
1 0 0 -1
$EndComp
Wire Bus Line
6150 2600 6900 2600
Wire Bus Line
6150 5050 6900 5050
Wire Bus Line
3900 4250 3900 4550
Wire Bus Line
7450 4250 7450 4550
Wire Wire Line
4150 5350 4150 5400
$Comp
L power:GNDD #PWR011
U 1 1 5CFBCC03
P 4150 5400
F 0 "#PWR011" H 4150 5150 50 0001 C CNN
F 1 "GNDD" V 4154 5290 50 0000 R CNN
F 2 "" H 4150 5400 50 0001 C CNN
F 3 "" H 4150 5400 50 0001 C CNN
1 4150 5400
1 0 0 -1
$EndComp
$EndSCHEMATC

0
kicad_clean/logic_block.sch → logic_block.sch
View File

0
kicad_clean/lutd.sch → lutd.sch
View File

0
kicad_clean/sym-lib-table → sym-lib-table
View File

0
kicad_clean/ttl-fpga-cache.lib → ttl-fpga-cache.lib
View File

0
kicad_clean/ttl-fpga-rescue.dcm → ttl-fpga-rescue.dcm
View File

0
kicad_clean/ttl-fpga-rescue.lib → ttl-fpga-rescue.lib
View File

0
kicad_clean/ttl-fpga.pro → ttl-fpga.pro
View File

0
kicad_clean/ttl-fpga.sch → ttl-fpga.sch
View File