electronics/ttl-fpga
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base: electronics:5bcc79e505e7f7af65e127653a489c54ab42b52d
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electronics:sw
electronics:master
electronics:rev02
electronics:rev01
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compare: electronics:b15d865090b04728efe366d142aa28a1b26a59ae
Branches Tags
electronics:master
electronics:sw
electronics:rev02
electronics:rev01

2 Commits
5bcc79e505 ... b15d865090

Author SHA1 Message Date
Markus Koch
b15d865090 Start layout 2019-06-04 22:43:08 +02:00
Markus Koch
a2608f41ae Ignore BOM 2019-06-04 22:42:56 +02:00
4 changed files with 4049 additions and 36 deletions
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1
.gitignore vendored
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@ -5,3 +5,4 @@
fp-info-cache fp-info-cache
*.pdf *.pdf
*.plt *.plt
*bom*

53
kicad_pcb/logic_block.sch
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@ -1571,7 +1567,7 @@ Connection ~ 4050 1950
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ISP Configuration Bit Mapping:\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED _enable\n\n [30]: Synchronous mode\n [31]: LUT mode _3/4\n\n [47..32]: LUT-4 content\n [39..32]: LUT-3/A\n [47..40]: LUT-3/B ISP Configuration Bit Mapping:\n -- OUT OF DATE --\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED _enable\n\n [30]: Synchronous mode\n [31]: LUT mode _3/4\n\n [47..32]: LUT-4 content\n [39..32]: LUT-3/A\n [47..40]: LUT-3/B
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* *
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LUT Input Limitations:\n* 4-bit: Never T2+T3+F3\n T0+T1+F2\n* 3-bit: Never T2+F3, T3 LUT Input Limitations:\n* 4-bit: Never T2+T3+F3\n T0+T1+F2\n* 3-bit: Never T2+F3, T3
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4015
kicad_pcb/ttl-fpga.kicad_pcb Normal file
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16
kicad_pcb/ttl-fpga.sch
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$EndSCHEMATC $EndSCHEMATC