electronics/ttl-fpga
1
0
Fork 0
Code Issues 1 Pull Requests Releases 1 Wiki Activity

Compare commits

base: electronics:e3c4a300d2acc729acf49555115f560806e74bd7
Branches Tags
electronics:sw
electronics:master
electronics:rev02
electronics:rev01
..
compare: electronics:5445fa28315f7f434db40f946bc107886e00b2e4
Branches Tags
electronics:master
electronics:sw
electronics:rev02
electronics:rev01

2 Commits
e3c4a300d2 ... 5445fa2831

Author SHA1 Message Date
Markus Koch
5445fa2831 Editorial 2019-05-31 22:14:42 +02:00
Markus Koch
7066cd590e Force protection resistors at fabric driver outputs 2019-05-31 22:12:15 +02:00
3 changed files with 25 additions and 73 deletions
Show Stats Expand all files Collapse all files

94
logic_block.sch
View File

@ -6,7 +6,7 @@ $Descr A3 16535 11693
encoding utf-8 encoding utf-8
Sheet 2 3 Sheet 2 3
Title "DISCRETE TTL FPGA" Title "DISCRETE TTL FPGA"
Date "" Date "2019-05-31"
Rev "01" Rev "01"
Comp "Markus Koch <markus@notsyncing.net>" Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block" Comment1 "Logic Block"
@ -1800,30 +1800,14 @@ Wire Notes Line
12650 5000 14300 5000 12650 5000 14300 5000
Wire Wire Line Wire Wire Line
3800 5400 6450 5400 3800 5400 6450 5400
Text Notes 7500 5050 0 50 ~ 10 Text Notes 7200 5050 0 50 ~ 10
LUT LUT + Reg
Connection ~ 10100 8250
Wire Wire Line
10100 8250 10400 8250
Wire Wire Line
9700 8250 9650 8250
Connection ~ 9700 8250
Wire Wire Line
10100 8250 10050 8250
Wire Wire Line
10100 8350 10100 8250
Wire Wire Line
9700 8350 10100 8350
Wire Wire Line
9700 8250 9700 8350
Wire Wire Line
9750 8250 9700 8250
$Comp $Comp
L Device:R R? L Device:R R?
U 1 1 5F6FE7F1 U 1 1 5F6FE7F1
P 9900 8250 P 9900 8250
F 0 "R?" V 9693 8250 50 0000 C CNN F 0 "R?" V 9693 8250 50 0000 C CNN
F 1 "DNP" V 9784 8250 50 0000 C CNN F 1 "470" V 9784 8250 50 0000 C CNN
F 2 "" V 9830 8250 50 0001 C CNN F 2 "" V 9830 8250 50 0001 C CNN
F 3 "~" H 9900 8250 50 0001 C CNN F 3 "~" H 9900 8250 50 0001 C CNN
1 9900 8250 1 9900 8250
@ -1831,28 +1815,12 @@ F 3 "~" H 9900 8250 50 0001 C CNN
$EndComp $EndComp
Text Label 10400 8250 2 50 ~ 0 Text Label 10400 8250 2 50 ~ 0
fabric3 fabric3
Connection ~ 10100 7750
Wire Wire Line
10100 7750 10400 7750
Wire Wire Line
9700 7750 9650 7750
Connection ~ 9700 7750
Wire Wire Line
10100 7750 10050 7750
Wire Wire Line
10100 7850 10100 7750
Wire Wire Line
9700 7850 10100 7850
Wire Wire Line
9700 7750 9700 7850
Wire Wire Line
9750 7750 9700 7750
$Comp $Comp
L Device:R R? L Device:R R?
U 1 1 5F6D346A U 1 1 5F6D346A
P 9900 7750 P 9900 7750
F 0 "R?" V 9693 7750 50 0000 C CNN F 0 "R?" V 9693 7750 50 0000 C CNN
F 1 "DNP" V 9784 7750 50 0000 C CNN F 1 "470" V 9784 7750 50 0000 C CNN
F 2 "" V 9830 7750 50 0001 C CNN F 2 "" V 9830 7750 50 0001 C CNN
F 3 "~" H 9900 7750 50 0001 C CNN F 3 "~" H 9900 7750 50 0001 C CNN
1 9900 7750 1 9900 7750
@ -1860,28 +1828,12 @@ F 3 "~" H 9900 7750 50 0001 C CNN
$EndComp $EndComp
Text Label 10400 7750 2 50 ~ 0 Text Label 10400 7750 2 50 ~ 0
fabric2 fabric2
Connection ~ 10100 6400
Wire Wire Line
10100 6400 10400 6400
Wire Wire Line
9700 6400 9650 6400
Connection ~ 9700 6400
Wire Wire Line
10100 6400 10050 6400
Wire Wire Line
10100 6500 10100 6400
Wire Wire Line
9700 6500 10100 6500
Wire Wire Line
9700 6400 9700 6500
Wire Wire Line
9750 6400 9700 6400
$Comp $Comp
L Device:R R? L Device:R R?
U 1 1 5F6AC414 U 1 1 5F6AC414
P 9900 6400 P 9900 6400
F 0 "R?" V 9693 6400 50 0000 C CNN F 0 "R?" V 9693 6400 50 0000 C CNN
F 1 "DNP" V 9784 6400 50 0000 C CNN F 1 "470" V 9784 6400 50 0000 C CNN
F 2 "" V 9830 6400 50 0001 C CNN F 2 "" V 9830 6400 50 0001 C CNN
F 3 "~" H 9900 6400 50 0001 C CNN F 3 "~" H 9900 6400 50 0001 C CNN
1 9900 6400 1 9900 6400
@ -1889,28 +1841,12 @@ F 3 "~" H 9900 6400 50 0001 C CNN
$EndComp $EndComp
Text Label 10400 6400 2 50 ~ 0 Text Label 10400 6400 2 50 ~ 0
fabric1 fabric1
Connection ~ 10100 5900
Wire Wire Line
10100 5900 10400 5900
Wire Wire Line
9700 5900 9650 5900
Connection ~ 9700 5900
Wire Wire Line
10100 5900 10050 5900
Wire Wire Line
10100 6000 10100 5900
Wire Wire Line
9700 6000 10100 6000
Wire Wire Line
9700 5900 9700 6000
Wire Wire Line
9750 5900 9700 5900
$Comp $Comp
L Device:R R? L Device:R R?
U 1 1 5F4F0B12 U 1 1 5F4F0B12
P 9900 5900 P 9900 5900
F 0 "R?" V 9693 5900 50 0000 C CNN F 0 "R?" V 9693 5900 50 0000 C CNN
F 1 "DNP" V 9784 5900 50 0000 C CNN F 1 "470" V 9784 5900 50 0000 C CNN
F 2 "" V 9830 5900 50 0001 C CNN F 2 "" V 9830 5900 50 0001 C CNN
F 3 "~" H 9900 5900 50 0001 C CNN F 3 "~" H 9900 5900 50 0001 C CNN
1 9900 5900 1 9900 5900
@ -2550,4 +2486,20 @@ Wire Bus Line
7750 1800 7750 4350 7750 1800 7750 4350
Wire Bus Line Wire Bus Line
5900 1800 5900 4350 5900 1800 5900 4350
Wire Wire Line
10050 5900 10400 5900
Wire Wire Line
9650 5900 9750 5900
Wire Wire Line
9650 6400 9750 6400
Wire Wire Line
10050 6400 10400 6400
Wire Wire Line
9650 7750 9750 7750
Wire Wire Line
10050 7750 10400 7750
Wire Wire Line
10050 8250 10400 8250
Wire Wire Line
9650 8250 9750 8250
$EndSCHEMATC $EndSCHEMATC

2
lutd.sch
View File

@ -6,7 +6,7 @@ $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 3 3 Sheet 3 3
Title "DISCRETE TTL FPGA" Title "DISCRETE TTL FPGA"
Date "" Date "2019-05-31"
Rev "01" Rev "01"
Comp "Markus Koch <markus@notsyncing.net>" Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block" Comment1 "Logic Block"

2
ttl-fpga.sch
View File

@ -6,7 +6,7 @@ $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 1 3 Sheet 1 3
Title "DISCRETE TTL FPGA" Title "DISCRETE TTL FPGA"
Date "" Date "2019-05-31"
Rev "01" Rev "01"
Comp "Markus Koch <markus@notsyncing.net>" Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "PCB" Comment1 "PCB"