electronics/ttl-fpga
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5 Commits
f27c728472 ... 6fbdcf9016

Author SHA1 Message Date
Markus Koch
6fbdcf9016 sw: Fix coding style 2019-09-23 21:29:36 +02:00
Markus Koch
7bb7049eea sw: Fix logic to determine when to enable the output drivers 
Before, it was always enabling all outputs,
even when they should have been tristated.
 2019-09-23 21:28:54 +02:00
Markus Koch
98a7a5d170 sw: Create function to determine whether an output is driven 2019-09-23 21:27:45 +02:00
Markus Koch
953818f43c sw: Report if bit is unset in final bitstream result 2019-09-23 21:26:50 +02:00
Markus Koch
72dabd64db sw: Swap the order of the two LUTs in the bitstream 2019-09-23 21:25:27 +02:00
1 changed files with 21 additions and 18 deletions
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39
sw/kousaten/src/fpga_cell_lut34.c
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@ -10,12 +10,12 @@ static int need_fix = 1;
/* LUT Definitions (correct offset, no fix must be applied) */
static int LUT4_BITMAP[16] = {
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31
24, 25, 26, 27, 28, 29, 30, 31,
16, 17, 18, 19, 20, 21, 22, 23
};
static int LUT3_BITMAP[2][8] = {
{16, 17, 18, 19, 20, 21, 22, 23},
{24, 25, 26, 27, 28, 29, 30, 31}
{24, 25, 26, 27, 28, 29, 30, 31},
{16, 17, 18, 19, 20, 21, 22, 23}
};
/* LUT Config Definitions */
@ -61,7 +61,13 @@ static int ROUTE_BITMAP[8] = {
static int BIT_LED_LUT_IN = 28;
static int BIT_LED_LUT_OUT_N = 29; /* Low-active */
static int fpga_cell_lut34_lut_get_mux(int lut, char port) {
static inline int fpga_cell_lut34_is_driven(char drive_sel)
{
return (drive_sel != LUT_OUT_DC && drive_sel != LUT_OUT_Z);
}
static int fpga_cell_lut34_lut_get_mux(int lut, char port)
{
int i;
if (port == LUT_NET_DC)
@ -74,7 +80,8 @@ static int fpga_cell_lut34_lut_get_mux(int lut, char port) {
return -1;
}
static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports) {
static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports)
{
int i;
int lut;
@ -88,11 +95,9 @@ static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports) {
ports = ports + lut;
for (i = 0; i < 4; ++i) {
if (ports[0] == LUT_OUT_DC ||
ports[0] == LUT_OUT_Z ||
if (!fpga_cell_lut34_is_driven(ports[0]) ||
ports[0] == LUT_OUT_MUX[lut][i]) {
if (ports[1] == LUT_OUT_DC ||
ports[1] == LUT_OUT_Z ||
if (!fpga_cell_lut34_is_driven(ports[1]) ||
ports[1] == LUT_OUT_MUX[lut + 1][i])
return i;
}
@ -232,15 +237,11 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
"Couldn't set LUT output sel %d for output %d.", temp, i);
}
for (i = 0; i < 2; ++i) {
temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
for (i = 0; i < 4; ++i) {
temp = fpga_cell_lut34_is_driven(lut34->drive_sel[i]);
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
"Couldn't %s output for output %d.",
(!temp ? "enable" : "disabled"), i);
if (!temp) {
BS_SET_BITS(0, 2 , LUT_OUT_BITMAP[i],
"Couldn't set LUT output sel 0 for output %d (undriven by user logic).", i);
}
}
/* Routing */
@ -280,8 +281,10 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
report(LL_DEBUG, "Bitstream result for %p:", cell);
for (i = 0; i < 48; ++i) {
report(LL_DEBUG,
" %d: %d",
i, fpga_cell_bitstream_is_set(buf, i));
" %d: %d%s",
i,
fpga_cell_bitstream_is_set(buf, i),
(fpga_cell_bitstream_is_set(sbuf, i) ? "" : " (Z)"));
}
free(sbuf);