#ifndef FPGA_CELL_H #define FPGA_CELL_H #include enum fpga_cell_position { LEFT = 0, TOP, RIGHT, BOTTOM, FPGA_CELL_CONNECTION_COUNT }; enum fpga_isp_channel { FPGA_ISP_CHANNEL_NORMAL = 0, FPGA_ISP_CHANNEL_BACK, FPGA_ISP_CHANNEL_LFDN, FPGA_ISP_CHANNEL_DNUP, FPGA_ISP_CHANNEL_ERROR }; struct fpga_cell_type { char identifier; struct fpga_cell *(*cell_new)(); struct fpga_cell *(*get_next_isp)(struct fpga_cell *cell, enum fpga_isp_channel *isp_channel); unsigned long isp_length; char *(*isp_generate_bitstream)(struct fpga_cell *cell); }; /* FPGA Logic cell base parameters */ struct fpga_cell { struct fpga_cell_type *type; struct fpga_cell *cell_connections[FPGA_CELL_CONNECTION_COUNT]; /* Cell-specific data will be appended depending on the cell type. */ }; struct fpga_chain { struct fpga_cell **head; int length; }; void fpga_cell_init(struct fpga_cell *cell, struct fpga_cell_type *cell_type); int fpga_cell_connect(struct fpga_cell *fpga_cell, struct fpga_cell *target_cell, enum fpga_cell_position position); struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell, enum fpga_cell_position position); struct fpga_cell *fpga_cell_get_next_isp_dummy(struct fpga_cell *fpga_cell, enum fpga_isp_channel *isp_channel); char *fpga_cell_isp_generate_bitstream_dummy(struct fpga_cell *cell); struct fpga_cell *fpga_cell_new(char identifier); #define FPGA_TO_CELL(a) ((struct fpga_cell*) a) struct fpga_chain *fpga_isp_chain_new(struct fpga_cell *entry); int fpga_cell_bitstream_set_bit(char *buffer, char *sbuffer, int bit, int value); int fpga_cell_bitstream_set_bits(char *buffer, char *sbuffer, int value, int nbits, int *mapping); int fpga_cell_bitstream_is_set(char *buffer, int bit); #endif // FPGA_CELL_H