#include #include "fpga_cell.h" #include "fpga_fdef_loader.h" #include "fpga_global.h" #include "fpga.h" #include "unistd.h" #include "string.h" #include "fpga_cell_lut34.h" /* For testing purposes only */ #define E_FDEF 1 #define E_BITSTREAM 2 static void test_design_cell_ripple(struct fpga_cell_lut34 *cell, int first, int last) { cell->lut_in_sel[0] = LUT_NET_F0; // Own state cell->lut_in_sel[1] = LUT_NET_F2; // Feedback &-net -- just for fun cell->lut_in_sel[2] = (first ? LUT_NET_T2 : LUT_NET_L1); // &-state of previous stages cell->lut_in_sel[3] = LUT_NET_L0; // Previous state -- just for fun cell->sync = 1; cell->drive_sel[0] = 'A'; cell->drive_sel[1] = 'b'; cell->drive_sel[2] = (last ? 'b' : 'Z'); cell->drive_sel[3] = 'Z'; cell->route_en = (1 << ROUTE_L2); cell->LUT3[0] = 0b01011010; cell->LUT3[1] = 0b10100000; } // WARNING: Requires a >=4x4 FPGA FDEF! static void test_design_counter(struct fpga_cell *entry_cell) { struct fpga_cell_lut34 *cell; int i, j; for (i = 0; i < 4; ++i) { cell = ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT])); for (j = 4 - i; j < 4; ++j) { cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[BOTTOM]; } test_design_cell_ripple(cell, 1, 0); cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT]; test_design_cell_ripple(cell, 0, 0); cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT]; test_design_cell_ripple(cell, 0, 0); cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT]; test_design_cell_ripple(cell, 0, 1); } } int development_test_main(int argc, char *argv[]) { struct fpga_cell *entry_cell; struct fpga_chain *chain; int opt; char *fdef_filename = "fdef/4x4.fdef"; char *kst_filename = "-"; char *bitstream_filename = "-"; int bitstream_ascii = 0; set_log_level(LL_DEBUG); while((opt = getopt(argc, argv, "f:i:o:h")) != -1) { switch(opt) { case 'f': fdef_filename = optarg; break; case 'i': kst_filename = optarg; report(LL_WARNING, "Input not yet implemented."); break; case 'o': bitstream_filename = optarg; break; case 'h': bitstream_ascii = 1; break; case ':': case '?': printf("Usage: %s [-f fdef] [-i input.kst] [-o output.bin] [-h]\n" "Generate bitstreams for the TTL-FPGA.\n\n" "When INPUT or OUTPUT is -, read/write standard input.\n\n" " -f\tFDEF FPGA description file, default fdef/4x4.fdef\n" " -i\tKousaten input file, default stdin\n" " -o\tOutput file, default stdout\n" " -h\tGenerate output as ASCII HEX\n", argv[0]); return 0; default: break; } } entry_cell = fpga_fdef_loader_load(fdef_filename); if (!entry_cell) { report(LL_CRITICAL, "Error loading FDEF."); return E_FDEF; } report(LL_INFO, "FDEF loaded."); chain = fpga_isp_chain_new(entry_cell); if (!chain) { report(LL_CRITICAL, "Critical error during bitstream generation."); return E_BITSTREAM; } report(LL_INFO, "Chain loaded."); test_design_counter(entry_cell); if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) { report(LL_ERROR, "Bitstream generation failed."); return E_BITSTREAM; } report(LL_INFO, "Generated bitstream."); return 0; } int main(int argc, char *argv[]) { return development_test_main(argc, argv); }