ttl-fpga/sw/kousaten/src/fpga_cell_lut34.h

62 lines
1.4 KiB
C

#ifndef FPGA_CELL_LUT34_H
#define FPGA_CELL_LUT34_H
#include "fpga_cell.h"
enum LUT_NET_NAMES {
LUT_NET_DC = '\0', /* Dont' care */
LUT_NET_T0 = '0',
LUT_NET_T1 = '1',
LUT_NET_T2 = '2',
LUT_NET_T3 = '3',
LUT_NET_L0 = 'A',
LUT_NET_L1 = 'B',
LUT_NET_L2 = 'C',
LUT_NET_L3 = 'D',
LUT_NET_F0 = 'W',
LUT_NET_F1 = 'X',
LUT_NET_F2 = 'Y',
LUT_NET_F3 = 'Z'
};
enum LUT_OUT_NAMES {
LUT_OUT_DC = '\0', /* Don't care, treated like Z */
LUT_OUT_Z = 'Z',
LUT_OUT_C = 'C',
LUT_OUT_A = 'A',
LUT_OUT_B = 'B',
LUT_OUT_B_ASYNC = 'b'
};
enum ROUTE_NAMES {
ROUTE_L0 = 0,
ROUTE_L1,
ROUTE_L2,
ROUTE_L3,
ROUTE_T0,
ROUTE_T1,
ROUTE_T2,
ROUTE_T3
};
struct fpga_cell_lut34 {
struct fpga_cell base_cell;
int led_lut_in_enable;
int led_lut_out_enable;
char lut_in_sel[4]; /* Input select */
char drive_sel[4]; /* Which signal to drive onto each fabric line */
int sync; /* Register output on rising edge of clk */
int route_en; /* Bitfield, Enable routing between {left, top} and main fabric */
int LUT4; /* Look-up table for LUT-4 configuration */
int LUT3[2]; /* Look-up tables for LUT-3 configuration */
};
struct fpga_cell *fpga_cell_lut34_new();
struct fpga_cell *fpga_cell_lut34_get_next_isp(struct fpga_cell *cell,
enum fpga_isp_channel *isp_channel);
char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell);
#endif // FPGA_CELL_LUT34_H