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trashernet

VHDL 0 0

Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers, including physical!

Updated 2024-07-23 19:00:19 +02:00

cocotb_helpers

Python 0 0

Small helper scripts / libraries / templates for use with VHDL + Cocotb test benches.

Updated 2022-04-18 17:02:02 +02:00

rgboard

VHDL 0 0

Simple WS2812B-based RGB LED wall.

Updated 2019-02-20 17:45:39 +01:00

model-ghdl

C 0 0

A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.

Updated 2018-01-21 14:14:47 +01:00

mor1kx-bemicrocv

Verilog 0 0

Softcore system for the bemicro cv development board using the OpenRisc Mor1kx processor.

Updated 2017-03-17 22:05:13 +01:00

ws2812b-vhdl

VHDL 0 0

A controller for the WorldSemi WS2812B RGB LEDs written in plain VHDL.

Updated 2016-11-05 15:10:25 +01:00