Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers, including physical!
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Small helper scripts / libraries / templates for use with VHDL + Cocotb test benches.
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A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.
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Softcore system for the bemicro cv development board using the OpenRisc Mor1kx processor.
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A controller for the WorldSemi WS2812B RGB LEDs written in plain VHDL.
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