library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library design;
use design.all;

library ip;
use ip.wishbone_package.all;

entity bench_gpio is
end entity bench_gpio;

architecture RTL of bench_gpio is
	signal clk    : std_logic;
	signal rst    : std_logic;
	signal clr    : std_logic;
	signal wb_in  : wishbone_v3_slave_in;
	signal wb_out : wishbone_v3_slave_out;
	signal gpio   : std_logic_vector(31 downto 0);

begin
	gpio_inst : entity design.gpio
		port map(
			clk    => clk,
			rst    => rst,
			clr    => clr,
			wb_in  => wb_in,
			wb_out => wb_out,
			gpio   => gpio
		);

	clock_driver : process
		constant period : time := 10 ns;
	begin
		clk <= '0';
		wait for period / 2;
		clk <= '1';
		wait for period / 2;
	end process clock_driver;

	test : process is
	begin
		rst       <= '1';
		clr       <= '0';
		wb_in.STB <= '0';
		wb_in.CYC <= '0';
		wb_in.ADR <= (others => '0');
		wb_in.DAT <= (others => '0');
		wb_in.SEL <= (others => '1');
		wb_in.WE  <= '0';

		wait for 20 ns;
		wait until rising_edge(clk);
		rst <= '0';
		wait until rising_edge(clk);

		wb_in.DAT <= x"0000ffff";
		wb_in.WE  <= '1';
		wb_in.STB <= '1';
		wb_in.CYC <= '1';
		wait until rising_edge(clk);
		wb_in.WE  <= '0';
		wb_in.STB <= '0';
		wb_in.CYC <= '0';

		wait until rising_edge(clk);
		wb_in.WE  <= '1';
		wb_in.STB <= '1';
		wb_in.CYC <= '1';
		wb_in.ADR <= x"00000004";
		wb_in.DAT <= x"12345678";
		
		wait until rising_edge(clk);
		wb_in.WE  <= '0';
		wb_in.STB <= '0';
		wb_in.CYC <= '0';
		
		wait until rising_edge(clk);
		wb_in.ADR <= x"00000008";

		wait;
	end process test;

	gpio(31 downto 28) <= (others => '1');

end architecture RTL;
