// ddr3_mm_interconnect_2.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 185

`timescale 1 ps / 1 ps
module ddr3_mm_interconnect_2 (
		input  wire        csr_clk_out_clk_clk,                             //                           csr_clk_out_clk.clk
		input  wire        if_csr_m0_clk_reset_reset_bridge_in_reset_reset, // if_csr_m0_clk_reset_reset_bridge_in_reset.reset
		input  wire        p0_csr_reset_n_reset_bridge_in_reset_reset,      //      p0_csr_reset_n_reset_bridge_in_reset.reset
		input  wire [31:0] if_csr_m0_master_address,                        //                          if_csr_m0_master.address
		output wire        if_csr_m0_master_waitrequest,                    //                                          .waitrequest
		input  wire [3:0]  if_csr_m0_master_byteenable,                     //                                          .byteenable
		input  wire        if_csr_m0_master_read,                           //                                          .read
		output wire [31:0] if_csr_m0_master_readdata,                       //                                          .readdata
		output wire        if_csr_m0_master_readdatavalid,                  //                                          .readdatavalid
		input  wire        if_csr_m0_master_write,                          //                                          .write
		input  wire [31:0] if_csr_m0_master_writedata,                      //                                          .writedata
		output wire [9:0]  c0_csr_address,                                  //                                    c0_csr.address
		output wire        c0_csr_write,                                    //                                          .write
		output wire        c0_csr_read,                                     //                                          .read
		input  wire [7:0]  c0_csr_readdata,                                 //                                          .readdata
		output wire [7:0]  c0_csr_writedata,                                //                                          .writedata
		output wire [0:0]  c0_csr_byteenable,                               //                                          .byteenable
		input  wire        c0_csr_readdatavalid,                            //                                          .readdatavalid
		input  wire        c0_csr_waitrequest,                              //                                          .waitrequest
		output wire [7:0]  p0_csr_address,                                  //                                    p0_csr.address
		output wire        p0_csr_write,                                    //                                          .write
		output wire        p0_csr_read,                                     //                                          .read
		input  wire [31:0] p0_csr_readdata,                                 //                                          .readdata
		output wire [31:0] p0_csr_writedata,                                //                                          .writedata
		output wire [3:0]  p0_csr_byteenable,                               //                                          .byteenable
		input  wire        p0_csr_readdatavalid,                            //                                          .readdatavalid
		input  wire        p0_csr_waitrequest                               //                                          .waitrequest
	);

	wire          if_csr_m0_master_translator_avalon_universal_master_0_waitrequest;   // if_csr_m0_master_agent:av_waitrequest -> if_csr_m0_master_translator:uav_waitrequest
	wire   [31:0] if_csr_m0_master_translator_avalon_universal_master_0_readdata;      // if_csr_m0_master_agent:av_readdata -> if_csr_m0_master_translator:uav_readdata
	wire          if_csr_m0_master_translator_avalon_universal_master_0_debugaccess;   // if_csr_m0_master_translator:uav_debugaccess -> if_csr_m0_master_agent:av_debugaccess
	wire   [31:0] if_csr_m0_master_translator_avalon_universal_master_0_address;       // if_csr_m0_master_translator:uav_address -> if_csr_m0_master_agent:av_address
	wire          if_csr_m0_master_translator_avalon_universal_master_0_read;          // if_csr_m0_master_translator:uav_read -> if_csr_m0_master_agent:av_read
	wire    [3:0] if_csr_m0_master_translator_avalon_universal_master_0_byteenable;    // if_csr_m0_master_translator:uav_byteenable -> if_csr_m0_master_agent:av_byteenable
	wire          if_csr_m0_master_translator_avalon_universal_master_0_readdatavalid; // if_csr_m0_master_agent:av_readdatavalid -> if_csr_m0_master_translator:uav_readdatavalid
	wire          if_csr_m0_master_translator_avalon_universal_master_0_lock;          // if_csr_m0_master_translator:uav_lock -> if_csr_m0_master_agent:av_lock
	wire          if_csr_m0_master_translator_avalon_universal_master_0_write;         // if_csr_m0_master_translator:uav_write -> if_csr_m0_master_agent:av_write
	wire   [31:0] if_csr_m0_master_translator_avalon_universal_master_0_writedata;     // if_csr_m0_master_translator:uav_writedata -> if_csr_m0_master_agent:av_writedata
	wire    [2:0] if_csr_m0_master_translator_avalon_universal_master_0_burstcount;    // if_csr_m0_master_translator:uav_burstcount -> if_csr_m0_master_agent:av_burstcount
	wire   [31:0] p0_csr_agent_m0_readdata;                                            // p0_csr_translator:uav_readdata -> p0_csr_agent:m0_readdata
	wire          p0_csr_agent_m0_waitrequest;                                         // p0_csr_translator:uav_waitrequest -> p0_csr_agent:m0_waitrequest
	wire          p0_csr_agent_m0_debugaccess;                                         // p0_csr_agent:m0_debugaccess -> p0_csr_translator:uav_debugaccess
	wire   [31:0] p0_csr_agent_m0_address;                                             // p0_csr_agent:m0_address -> p0_csr_translator:uav_address
	wire    [3:0] p0_csr_agent_m0_byteenable;                                          // p0_csr_agent:m0_byteenable -> p0_csr_translator:uav_byteenable
	wire          p0_csr_agent_m0_read;                                                // p0_csr_agent:m0_read -> p0_csr_translator:uav_read
	wire          p0_csr_agent_m0_readdatavalid;                                       // p0_csr_translator:uav_readdatavalid -> p0_csr_agent:m0_readdatavalid
	wire          p0_csr_agent_m0_lock;                                                // p0_csr_agent:m0_lock -> p0_csr_translator:uav_lock
	wire   [31:0] p0_csr_agent_m0_writedata;                                           // p0_csr_agent:m0_writedata -> p0_csr_translator:uav_writedata
	wire          p0_csr_agent_m0_write;                                               // p0_csr_agent:m0_write -> p0_csr_translator:uav_write
	wire    [2:0] p0_csr_agent_m0_burstcount;                                          // p0_csr_agent:m0_burstcount -> p0_csr_translator:uav_burstcount
	wire          p0_csr_agent_rf_source_valid;                                        // p0_csr_agent:rf_source_valid -> p0_csr_agent_rsp_fifo:in_valid
	wire  [102:0] p0_csr_agent_rf_source_data;                                         // p0_csr_agent:rf_source_data -> p0_csr_agent_rsp_fifo:in_data
	wire          p0_csr_agent_rf_source_ready;                                        // p0_csr_agent_rsp_fifo:in_ready -> p0_csr_agent:rf_source_ready
	wire          p0_csr_agent_rf_source_startofpacket;                                // p0_csr_agent:rf_source_startofpacket -> p0_csr_agent_rsp_fifo:in_startofpacket
	wire          p0_csr_agent_rf_source_endofpacket;                                  // p0_csr_agent:rf_source_endofpacket -> p0_csr_agent_rsp_fifo:in_endofpacket
	wire          p0_csr_agent_rsp_fifo_out_valid;                                     // p0_csr_agent_rsp_fifo:out_valid -> p0_csr_agent:rf_sink_valid
	wire  [102:0] p0_csr_agent_rsp_fifo_out_data;                                      // p0_csr_agent_rsp_fifo:out_data -> p0_csr_agent:rf_sink_data
	wire          p0_csr_agent_rsp_fifo_out_ready;                                     // p0_csr_agent:rf_sink_ready -> p0_csr_agent_rsp_fifo:out_ready
	wire          p0_csr_agent_rsp_fifo_out_startofpacket;                             // p0_csr_agent_rsp_fifo:out_startofpacket -> p0_csr_agent:rf_sink_startofpacket
	wire          p0_csr_agent_rsp_fifo_out_endofpacket;                               // p0_csr_agent_rsp_fifo:out_endofpacket -> p0_csr_agent:rf_sink_endofpacket
	wire          cmd_mux_src_valid;                                                   // cmd_mux:src_valid -> p0_csr_agent:cp_valid
	wire  [101:0] cmd_mux_src_data;                                                    // cmd_mux:src_data -> p0_csr_agent:cp_data
	wire          cmd_mux_src_ready;                                                   // p0_csr_agent:cp_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                 // cmd_mux:src_channel -> p0_csr_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                           // cmd_mux:src_startofpacket -> p0_csr_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                             // cmd_mux:src_endofpacket -> p0_csr_agent:cp_endofpacket
	wire    [7:0] c0_csr_agent_m0_readdata;                                            // c0_csr_translator:uav_readdata -> c0_csr_agent:m0_readdata
	wire          c0_csr_agent_m0_waitrequest;                                         // c0_csr_translator:uav_waitrequest -> c0_csr_agent:m0_waitrequest
	wire          c0_csr_agent_m0_debugaccess;                                         // c0_csr_agent:m0_debugaccess -> c0_csr_translator:uav_debugaccess
	wire   [31:0] c0_csr_agent_m0_address;                                             // c0_csr_agent:m0_address -> c0_csr_translator:uav_address
	wire    [0:0] c0_csr_agent_m0_byteenable;                                          // c0_csr_agent:m0_byteenable -> c0_csr_translator:uav_byteenable
	wire          c0_csr_agent_m0_read;                                                // c0_csr_agent:m0_read -> c0_csr_translator:uav_read
	wire          c0_csr_agent_m0_readdatavalid;                                       // c0_csr_translator:uav_readdatavalid -> c0_csr_agent:m0_readdatavalid
	wire          c0_csr_agent_m0_lock;                                                // c0_csr_agent:m0_lock -> c0_csr_translator:uav_lock
	wire    [7:0] c0_csr_agent_m0_writedata;                                           // c0_csr_agent:m0_writedata -> c0_csr_translator:uav_writedata
	wire          c0_csr_agent_m0_write;                                               // c0_csr_agent:m0_write -> c0_csr_translator:uav_write
	wire    [0:0] c0_csr_agent_m0_burstcount;                                          // c0_csr_agent:m0_burstcount -> c0_csr_translator:uav_burstcount
	wire          c0_csr_agent_rf_source_valid;                                        // c0_csr_agent:rf_source_valid -> c0_csr_agent_rsp_fifo:in_valid
	wire   [75:0] c0_csr_agent_rf_source_data;                                         // c0_csr_agent:rf_source_data -> c0_csr_agent_rsp_fifo:in_data
	wire          c0_csr_agent_rf_source_ready;                                        // c0_csr_agent_rsp_fifo:in_ready -> c0_csr_agent:rf_source_ready
	wire          c0_csr_agent_rf_source_startofpacket;                                // c0_csr_agent:rf_source_startofpacket -> c0_csr_agent_rsp_fifo:in_startofpacket
	wire          c0_csr_agent_rf_source_endofpacket;                                  // c0_csr_agent:rf_source_endofpacket -> c0_csr_agent_rsp_fifo:in_endofpacket
	wire          c0_csr_agent_rsp_fifo_out_valid;                                     // c0_csr_agent_rsp_fifo:out_valid -> c0_csr_agent:rf_sink_valid
	wire   [75:0] c0_csr_agent_rsp_fifo_out_data;                                      // c0_csr_agent_rsp_fifo:out_data -> c0_csr_agent:rf_sink_data
	wire          c0_csr_agent_rsp_fifo_out_ready;                                     // c0_csr_agent:rf_sink_ready -> c0_csr_agent_rsp_fifo:out_ready
	wire          c0_csr_agent_rsp_fifo_out_startofpacket;                             // c0_csr_agent_rsp_fifo:out_startofpacket -> c0_csr_agent:rf_sink_startofpacket
	wire          c0_csr_agent_rsp_fifo_out_endofpacket;                               // c0_csr_agent_rsp_fifo:out_endofpacket -> c0_csr_agent:rf_sink_endofpacket
	wire          c0_csr_agent_rdata_fifo_src_valid;                                   // c0_csr_agent:rdata_fifo_src_valid -> c0_csr_agent_rdata_fifo:in_valid
	wire    [9:0] c0_csr_agent_rdata_fifo_src_data;                                    // c0_csr_agent:rdata_fifo_src_data -> c0_csr_agent_rdata_fifo:in_data
	wire          c0_csr_agent_rdata_fifo_src_ready;                                   // c0_csr_agent_rdata_fifo:in_ready -> c0_csr_agent:rdata_fifo_src_ready
	wire          if_csr_m0_master_agent_cp_valid;                                     // if_csr_m0_master_agent:cp_valid -> router:sink_valid
	wire  [101:0] if_csr_m0_master_agent_cp_data;                                      // if_csr_m0_master_agent:cp_data -> router:sink_data
	wire          if_csr_m0_master_agent_cp_ready;                                     // router:sink_ready -> if_csr_m0_master_agent:cp_ready
	wire          if_csr_m0_master_agent_cp_startofpacket;                             // if_csr_m0_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          if_csr_m0_master_agent_cp_endofpacket;                               // if_csr_m0_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          p0_csr_agent_rp_valid;                                               // p0_csr_agent:rp_valid -> router_001:sink_valid
	wire  [101:0] p0_csr_agent_rp_data;                                                // p0_csr_agent:rp_data -> router_001:sink_data
	wire          p0_csr_agent_rp_ready;                                               // router_001:sink_ready -> p0_csr_agent:rp_ready
	wire          p0_csr_agent_rp_startofpacket;                                       // p0_csr_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          p0_csr_agent_rp_endofpacket;                                         // p0_csr_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                // router_001:src_valid -> rsp_demux:sink_valid
	wire  [101:0] router_001_src_data;                                                 // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                // rsp_demux:sink_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                              // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                        // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                          // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          c0_csr_agent_rp_valid;                                               // c0_csr_agent:rp_valid -> router_002:sink_valid
	wire   [74:0] c0_csr_agent_rp_data;                                                // c0_csr_agent:rp_data -> router_002:sink_data
	wire          c0_csr_agent_rp_ready;                                               // router_002:sink_ready -> c0_csr_agent:rp_ready
	wire          c0_csr_agent_rp_startofpacket;                                       // c0_csr_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          c0_csr_agent_rp_endofpacket;                                         // c0_csr_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_src_valid;                                                    // router:src_valid -> if_csr_m0_master_limiter:cmd_sink_valid
	wire  [101:0] router_src_data;                                                     // router:src_data -> if_csr_m0_master_limiter:cmd_sink_data
	wire          router_src_ready;                                                    // if_csr_m0_master_limiter:cmd_sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                  // router:src_channel -> if_csr_m0_master_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                            // router:src_startofpacket -> if_csr_m0_master_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                              // router:src_endofpacket -> if_csr_m0_master_limiter:cmd_sink_endofpacket
	wire  [101:0] if_csr_m0_master_limiter_cmd_src_data;                               // if_csr_m0_master_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          if_csr_m0_master_limiter_cmd_src_ready;                              // cmd_demux:sink_ready -> if_csr_m0_master_limiter:cmd_src_ready
	wire    [1:0] if_csr_m0_master_limiter_cmd_src_channel;                            // if_csr_m0_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          if_csr_m0_master_limiter_cmd_src_startofpacket;                      // if_csr_m0_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          if_csr_m0_master_limiter_cmd_src_endofpacket;                        // if_csr_m0_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                   // rsp_mux:src_valid -> if_csr_m0_master_limiter:rsp_sink_valid
	wire  [101:0] rsp_mux_src_data;                                                    // rsp_mux:src_data -> if_csr_m0_master_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                   // if_csr_m0_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                 // rsp_mux:src_channel -> if_csr_m0_master_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                           // rsp_mux:src_startofpacket -> if_csr_m0_master_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                             // rsp_mux:src_endofpacket -> if_csr_m0_master_limiter:rsp_sink_endofpacket
	wire          if_csr_m0_master_limiter_rsp_src_valid;                              // if_csr_m0_master_limiter:rsp_src_valid -> if_csr_m0_master_agent:rp_valid
	wire  [101:0] if_csr_m0_master_limiter_rsp_src_data;                               // if_csr_m0_master_limiter:rsp_src_data -> if_csr_m0_master_agent:rp_data
	wire          if_csr_m0_master_limiter_rsp_src_ready;                              // if_csr_m0_master_agent:rp_ready -> if_csr_m0_master_limiter:rsp_src_ready
	wire    [1:0] if_csr_m0_master_limiter_rsp_src_channel;                            // if_csr_m0_master_limiter:rsp_src_channel -> if_csr_m0_master_agent:rp_channel
	wire          if_csr_m0_master_limiter_rsp_src_startofpacket;                      // if_csr_m0_master_limiter:rsp_src_startofpacket -> if_csr_m0_master_agent:rp_startofpacket
	wire          if_csr_m0_master_limiter_rsp_src_endofpacket;                        // if_csr_m0_master_limiter:rsp_src_endofpacket -> if_csr_m0_master_agent:rp_endofpacket
	wire          c0_csr_burst_adapter_source0_valid;                                  // c0_csr_burst_adapter:source0_valid -> c0_csr_agent:cp_valid
	wire   [74:0] c0_csr_burst_adapter_source0_data;                                   // c0_csr_burst_adapter:source0_data -> c0_csr_agent:cp_data
	wire          c0_csr_burst_adapter_source0_ready;                                  // c0_csr_agent:cp_ready -> c0_csr_burst_adapter:source0_ready
	wire    [1:0] c0_csr_burst_adapter_source0_channel;                                // c0_csr_burst_adapter:source0_channel -> c0_csr_agent:cp_channel
	wire          c0_csr_burst_adapter_source0_startofpacket;                          // c0_csr_burst_adapter:source0_startofpacket -> c0_csr_agent:cp_startofpacket
	wire          c0_csr_burst_adapter_source0_endofpacket;                            // c0_csr_burst_adapter:source0_endofpacket -> c0_csr_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [101:0] cmd_demux_src0_data;                                                 // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                              // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                        // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                          // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [101:0] cmd_demux_src1_data;                                                 // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [1:0] cmd_demux_src1_channel;                                              // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                        // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                          // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [101:0] rsp_demux_src0_data;                                                 // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                              // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                        // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                          // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                            // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [101:0] rsp_demux_001_src0_data;                                             // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                            // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [1:0] rsp_demux_001_src0_channel;                                          // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                    // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                      // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          router_002_src_valid;                                                // router_002:src_valid -> c0_csr_rsp_width_adapter:in_valid
	wire   [74:0] router_002_src_data;                                                 // router_002:src_data -> c0_csr_rsp_width_adapter:in_data
	wire          router_002_src_ready;                                                // c0_csr_rsp_width_adapter:in_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                              // router_002:src_channel -> c0_csr_rsp_width_adapter:in_channel
	wire          router_002_src_startofpacket;                                        // router_002:src_startofpacket -> c0_csr_rsp_width_adapter:in_startofpacket
	wire          router_002_src_endofpacket;                                          // router_002:src_endofpacket -> c0_csr_rsp_width_adapter:in_endofpacket
	wire          c0_csr_rsp_width_adapter_src_valid;                                  // c0_csr_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
	wire  [101:0] c0_csr_rsp_width_adapter_src_data;                                   // c0_csr_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
	wire          c0_csr_rsp_width_adapter_src_ready;                                  // rsp_demux_001:sink_ready -> c0_csr_rsp_width_adapter:out_ready
	wire    [1:0] c0_csr_rsp_width_adapter_src_channel;                                // c0_csr_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
	wire          c0_csr_rsp_width_adapter_src_startofpacket;                          // c0_csr_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          c0_csr_rsp_width_adapter_src_endofpacket;                            // c0_csr_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          cmd_mux_001_src_valid;                                               // cmd_mux_001:src_valid -> c0_csr_cmd_width_adapter:in_valid
	wire  [101:0] cmd_mux_001_src_data;                                                // cmd_mux_001:src_data -> c0_csr_cmd_width_adapter:in_data
	wire          cmd_mux_001_src_ready;                                               // c0_csr_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
	wire    [1:0] cmd_mux_001_src_channel;                                             // cmd_mux_001:src_channel -> c0_csr_cmd_width_adapter:in_channel
	wire          cmd_mux_001_src_startofpacket;                                       // cmd_mux_001:src_startofpacket -> c0_csr_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                         // cmd_mux_001:src_endofpacket -> c0_csr_cmd_width_adapter:in_endofpacket
	wire          c0_csr_cmd_width_adapter_src_valid;                                  // c0_csr_cmd_width_adapter:out_valid -> c0_csr_burst_adapter:sink0_valid
	wire   [74:0] c0_csr_cmd_width_adapter_src_data;                                   // c0_csr_cmd_width_adapter:out_data -> c0_csr_burst_adapter:sink0_data
	wire          c0_csr_cmd_width_adapter_src_ready;                                  // c0_csr_burst_adapter:sink0_ready -> c0_csr_cmd_width_adapter:out_ready
	wire    [1:0] c0_csr_cmd_width_adapter_src_channel;                                // c0_csr_cmd_width_adapter:out_channel -> c0_csr_burst_adapter:sink0_channel
	wire          c0_csr_cmd_width_adapter_src_startofpacket;                          // c0_csr_cmd_width_adapter:out_startofpacket -> c0_csr_burst_adapter:sink0_startofpacket
	wire          c0_csr_cmd_width_adapter_src_endofpacket;                            // c0_csr_cmd_width_adapter:out_endofpacket -> c0_csr_burst_adapter:sink0_endofpacket
	wire    [1:0] if_csr_m0_master_limiter_cmd_valid_data;                             // if_csr_m0_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
	wire          p0_csr_agent_rdata_fifo_src_valid;                                   // p0_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] p0_csr_agent_rdata_fifo_src_data;                                    // p0_csr_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire          p0_csr_agent_rdata_fifo_src_ready;                                   // avalon_st_adapter:in_0_ready -> p0_csr_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_out_0_valid;                                       // avalon_st_adapter:out_0_valid -> p0_csr_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                        // avalon_st_adapter:out_0_data -> p0_csr_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                       // p0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                       // avalon_st_adapter:out_0_error -> p0_csr_agent:rdata_fifo_sink_error
	wire          c0_csr_agent_rdata_fifo_out_valid;                                   // c0_csr_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
	wire    [9:0] c0_csr_agent_rdata_fifo_out_data;                                    // c0_csr_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
	wire          c0_csr_agent_rdata_fifo_out_ready;                                   // avalon_st_adapter_001:in_0_ready -> c0_csr_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_001_out_0_valid;                                   // avalon_st_adapter_001:out_0_valid -> c0_csr_agent:rdata_fifo_sink_valid
	wire    [9:0] avalon_st_adapter_001_out_0_data;                                    // avalon_st_adapter_001:out_0_data -> c0_csr_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_001_out_0_ready;                                   // c0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire    [0:0] avalon_st_adapter_001_out_0_error;                                   // avalon_st_adapter_001:out_0_error -> c0_csr_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) if_csr_m0_master_translator (
		.clk                    (csr_clk_out_clk_clk),                                                 //                       clk.clk
		.reset                  (p0_csr_reset_n_reset_bridge_in_reset_reset),                          //                     reset.reset
		.uav_address            (if_csr_m0_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (if_csr_m0_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (if_csr_m0_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (if_csr_m0_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (if_csr_m0_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (if_csr_m0_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (if_csr_m0_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (if_csr_m0_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (if_csr_m0_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (if_csr_m0_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (if_csr_m0_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (if_csr_m0_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (if_csr_m0_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (if_csr_m0_master_byteenable),                                         //                          .byteenable
		.av_read                (if_csr_m0_master_read),                                               //                          .read
		.av_readdata            (if_csr_m0_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (if_csr_m0_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (if_csr_m0_master_write),                                              //                          .write
		.av_writedata           (if_csr_m0_master_writedata),                                          //                          .writedata
		.av_burstcount          (1'b1),                                                                //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                //               (terminated)
		.av_begintransfer       (1'b0),                                                                //               (terminated)
		.av_chipselect          (1'b0),                                                                //               (terminated)
		.av_lock                (1'b0),                                                                //               (terminated)
		.av_debugaccess         (1'b0),                                                                //               (terminated)
		.uav_clken              (),                                                                    //               (terminated)
		.av_clken               (1'b1),                                                                //               (terminated)
		.uav_response           (2'b00),                                                               //               (terminated)
		.av_response            (),                                                                    //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                //               (terminated)
		.av_writeresponsevalid  ()                                                                     //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (8),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) p0_csr_translator (
		.clk                    (csr_clk_out_clk_clk),                        //                      clk.clk
		.reset                  (p0_csr_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (p0_csr_agent_m0_address),                    // avalon_universal_slave_0.address
		.uav_burstcount         (p0_csr_agent_m0_burstcount),                 //                         .burstcount
		.uav_read               (p0_csr_agent_m0_read),                       //                         .read
		.uav_write              (p0_csr_agent_m0_write),                      //                         .write
		.uav_waitrequest        (p0_csr_agent_m0_waitrequest),                //                         .waitrequest
		.uav_readdatavalid      (p0_csr_agent_m0_readdatavalid),              //                         .readdatavalid
		.uav_byteenable         (p0_csr_agent_m0_byteenable),                 //                         .byteenable
		.uav_readdata           (p0_csr_agent_m0_readdata),                   //                         .readdata
		.uav_writedata          (p0_csr_agent_m0_writedata),                  //                         .writedata
		.uav_lock               (p0_csr_agent_m0_lock),                       //                         .lock
		.uav_debugaccess        (p0_csr_agent_m0_debugaccess),                //                         .debugaccess
		.av_address             (p0_csr_address),                             //      avalon_anti_slave_0.address
		.av_write               (p0_csr_write),                               //                         .write
		.av_read                (p0_csr_read),                                //                         .read
		.av_readdata            (p0_csr_readdata),                            //                         .readdata
		.av_writedata           (p0_csr_writedata),                           //                         .writedata
		.av_byteenable          (p0_csr_byteenable),                          //                         .byteenable
		.av_readdatavalid       (p0_csr_readdatavalid),                       //                         .readdatavalid
		.av_waitrequest         (p0_csr_waitrequest),                         //                         .waitrequest
		.av_begintransfer       (),                                           //              (terminated)
		.av_beginbursttransfer  (),                                           //              (terminated)
		.av_burstcount          (),                                           //              (terminated)
		.av_writebyteenable     (),                                           //              (terminated)
		.av_lock                (),                                           //              (terminated)
		.av_chipselect          (),                                           //              (terminated)
		.av_clken               (),                                           //              (terminated)
		.uav_clken              (1'b0),                                       //              (terminated)
		.av_debugaccess         (),                                           //              (terminated)
		.av_outputenable        (),                                           //              (terminated)
		.uav_response           (),                                           //              (terminated)
		.av_response            (2'b00),                                      //              (terminated)
		.uav_writeresponsevalid (),                                           //              (terminated)
		.av_writeresponsevalid  (1'b0)                                        //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (10),
		.AV_DATA_W                      (8),
		.UAV_DATA_W                     (8),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (1),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (1),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (1),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) c0_csr_translator (
		.clk                    (csr_clk_out_clk_clk),                        //                      clk.clk
		.reset                  (p0_csr_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (c0_csr_agent_m0_address),                    // avalon_universal_slave_0.address
		.uav_burstcount         (c0_csr_agent_m0_burstcount),                 //                         .burstcount
		.uav_read               (c0_csr_agent_m0_read),                       //                         .read
		.uav_write              (c0_csr_agent_m0_write),                      //                         .write
		.uav_waitrequest        (c0_csr_agent_m0_waitrequest),                //                         .waitrequest
		.uav_readdatavalid      (c0_csr_agent_m0_readdatavalid),              //                         .readdatavalid
		.uav_byteenable         (c0_csr_agent_m0_byteenable),                 //                         .byteenable
		.uav_readdata           (c0_csr_agent_m0_readdata),                   //                         .readdata
		.uav_writedata          (c0_csr_agent_m0_writedata),                  //                         .writedata
		.uav_lock               (c0_csr_agent_m0_lock),                       //                         .lock
		.uav_debugaccess        (c0_csr_agent_m0_debugaccess),                //                         .debugaccess
		.av_address             (c0_csr_address),                             //      avalon_anti_slave_0.address
		.av_write               (c0_csr_write),                               //                         .write
		.av_read                (c0_csr_read),                                //                         .read
		.av_readdata            (c0_csr_readdata),                            //                         .readdata
		.av_writedata           (c0_csr_writedata),                           //                         .writedata
		.av_byteenable          (c0_csr_byteenable),                          //                         .byteenable
		.av_readdatavalid       (c0_csr_readdatavalid),                       //                         .readdatavalid
		.av_waitrequest         (c0_csr_waitrequest),                         //                         .waitrequest
		.av_begintransfer       (),                                           //              (terminated)
		.av_beginbursttransfer  (),                                           //              (terminated)
		.av_burstcount          (),                                           //              (terminated)
		.av_writebyteenable     (),                                           //              (terminated)
		.av_lock                (),                                           //              (terminated)
		.av_chipselect          (),                                           //              (terminated)
		.av_clken               (),                                           //              (terminated)
		.uav_clken              (1'b0),                                       //              (terminated)
		.av_debugaccess         (),                                           //              (terminated)
		.av_outputenable        (),                                           //              (terminated)
		.uav_response           (),                                           //              (terminated)
		.av_response            (2'b00),                                      //              (terminated)
		.uav_writeresponsevalid (),                                           //              (terminated)
		.av_writeresponsevalid  (1'b0)                                        //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (101),
		.PKT_ORI_BURST_SIZE_L      (99),
		.PKT_RESPONSE_STATUS_H     (98),
		.PKT_RESPONSE_STATUS_L     (97),
		.PKT_QOS_H                 (86),
		.PKT_QOS_L                 (86),
		.PKT_DATA_SIDEBAND_H       (84),
		.PKT_DATA_SIDEBAND_L       (84),
		.PKT_ADDR_SIDEBAND_H       (83),
		.PKT_ADDR_SIDEBAND_L       (83),
		.PKT_BURST_TYPE_H          (82),
		.PKT_BURST_TYPE_L          (81),
		.PKT_CACHE_H               (96),
		.PKT_CACHE_L               (93),
		.PKT_THREAD_ID_H           (89),
		.PKT_THREAD_ID_L           (89),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (92),
		.PKT_PROTECTION_L          (90),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (87),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (88),
		.PKT_DEST_ID_L             (88),
		.ST_DATA_W                 (102),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) if_csr_m0_master_agent (
		.clk                   (csr_clk_out_clk_clk),                                                 //       clk.clk
		.reset                 (p0_csr_reset_n_reset_bridge_in_reset_reset),                          // clk_reset.reset
		.av_address            (if_csr_m0_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (if_csr_m0_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (if_csr_m0_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (if_csr_m0_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (if_csr_m0_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (if_csr_m0_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (if_csr_m0_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (if_csr_m0_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (if_csr_m0_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (if_csr_m0_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (if_csr_m0_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (if_csr_m0_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (if_csr_m0_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (if_csr_m0_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (if_csr_m0_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (if_csr_m0_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (if_csr_m0_master_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (if_csr_m0_master_limiter_rsp_src_data),                               //          .data
		.rp_channel            (if_csr_m0_master_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (if_csr_m0_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (if_csr_m0_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (if_csr_m0_master_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                    // (terminated)
		.av_writeresponsevalid ()                                                                     // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (101),
		.PKT_ORI_BURST_SIZE_L      (99),
		.PKT_RESPONSE_STATUS_H     (98),
		.PKT_RESPONSE_STATUS_L     (97),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (92),
		.PKT_PROTECTION_L          (90),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (87),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (88),
		.PKT_DEST_ID_L             (88),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (102),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) p0_csr_agent (
		.clk                     (csr_clk_out_clk_clk),                        //             clk.clk
		.reset                   (p0_csr_reset_n_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (p0_csr_agent_m0_address),                    //              m0.address
		.m0_burstcount           (p0_csr_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (p0_csr_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (p0_csr_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (p0_csr_agent_m0_lock),                       //                .lock
		.m0_readdata             (p0_csr_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (p0_csr_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (p0_csr_agent_m0_read),                       //                .read
		.m0_waitrequest          (p0_csr_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (p0_csr_agent_m0_writedata),                  //                .writedata
		.m0_write                (p0_csr_agent_m0_write),                      //                .write
		.rp_endofpacket          (p0_csr_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (p0_csr_agent_rp_ready),                      //                .ready
		.rp_valid                (p0_csr_agent_rp_valid),                      //                .valid
		.rp_data                 (p0_csr_agent_rp_data),                       //                .data
		.rp_startofpacket        (p0_csr_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                        //                .channel
		.rf_sink_ready           (p0_csr_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (p0_csr_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (p0_csr_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (p0_csr_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (p0_csr_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (p0_csr_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (p0_csr_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (p0_csr_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (p0_csr_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (p0_csr_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),              //                .error
		.rdata_fifo_src_ready    (p0_csr_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (p0_csr_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (p0_csr_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                        //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (103),
		.FIFO_DEPTH          (5),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) p0_csr_agent_rsp_fifo (
		.clk               (csr_clk_out_clk_clk),                        //       clk.clk
		.reset             (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (p0_csr_agent_rf_source_data),                //        in.data
		.in_valid          (p0_csr_agent_rf_source_valid),               //          .valid
		.in_ready          (p0_csr_agent_rf_source_ready),               //          .ready
		.in_startofpacket  (p0_csr_agent_rf_source_startofpacket),       //          .startofpacket
		.in_endofpacket    (p0_csr_agent_rf_source_endofpacket),         //          .endofpacket
		.out_data          (p0_csr_agent_rsp_fifo_out_data),             //       out.data
		.out_valid         (p0_csr_agent_rsp_fifo_out_valid),            //          .valid
		.out_ready         (p0_csr_agent_rsp_fifo_out_ready),            //          .ready
		.out_startofpacket (p0_csr_agent_rsp_fifo_out_startofpacket),    //          .startofpacket
		.out_endofpacket   (p0_csr_agent_rsp_fifo_out_endofpacket),      //          .endofpacket
		.csr_address       (2'b00),                                      // (terminated)
		.csr_read          (1'b0),                                       // (terminated)
		.csr_write         (1'b0),                                       // (terminated)
		.csr_readdata      (),                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),       // (terminated)
		.almost_full_data  (),                                           // (terminated)
		.almost_empty_data (),                                           // (terminated)
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.in_error          (1'b0),                                       // (terminated)
		.out_error         (),                                           // (terminated)
		.in_channel        (1'b0),                                       // (terminated)
		.out_channel       ()                                            // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (74),
		.PKT_ORI_BURST_SIZE_L      (72),
		.PKT_RESPONSE_STATUS_H     (71),
		.PKT_RESPONSE_STATUS_L     (70),
		.PKT_BURST_SIZE_H          (53),
		.PKT_BURST_SIZE_L          (51),
		.PKT_TRANS_LOCK            (45),
		.PKT_BEGIN_BURST           (58),
		.PKT_PROTECTION_H          (65),
		.PKT_PROTECTION_L          (63),
		.PKT_BURSTWRAP_H           (50),
		.PKT_BURSTWRAP_L           (50),
		.PKT_BYTE_CNT_H            (49),
		.PKT_BYTE_CNT_L            (47),
		.PKT_ADDR_H                (40),
		.PKT_ADDR_L                (9),
		.PKT_TRANS_COMPRESSED_READ (41),
		.PKT_TRANS_POSTED          (42),
		.PKT_TRANS_WRITE           (43),
		.PKT_TRANS_READ            (44),
		.PKT_DATA_H                (7),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (8),
		.PKT_BYTEEN_L              (8),
		.PKT_SRC_ID_H              (60),
		.PKT_SRC_ID_L              (60),
		.PKT_DEST_ID_H             (61),
		.PKT_DEST_ID_L             (61),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (75),
		.AVS_BURSTCOUNT_W          (1),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) c0_csr_agent (
		.clk                     (csr_clk_out_clk_clk),                        //             clk.clk
		.reset                   (p0_csr_reset_n_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (c0_csr_agent_m0_address),                    //              m0.address
		.m0_burstcount           (c0_csr_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (c0_csr_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (c0_csr_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (c0_csr_agent_m0_lock),                       //                .lock
		.m0_readdata             (c0_csr_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (c0_csr_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (c0_csr_agent_m0_read),                       //                .read
		.m0_waitrequest          (c0_csr_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (c0_csr_agent_m0_writedata),                  //                .writedata
		.m0_write                (c0_csr_agent_m0_write),                      //                .write
		.rp_endofpacket          (c0_csr_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (c0_csr_agent_rp_ready),                      //                .ready
		.rp_valid                (c0_csr_agent_rp_valid),                      //                .valid
		.rp_data                 (c0_csr_agent_rp_data),                       //                .data
		.rp_startofpacket        (c0_csr_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (c0_csr_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (c0_csr_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (c0_csr_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (c0_csr_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (c0_csr_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (c0_csr_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (c0_csr_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (c0_csr_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (c0_csr_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (c0_csr_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (c0_csr_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (c0_csr_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (c0_csr_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (c0_csr_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (c0_csr_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (c0_csr_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),          //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),           //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),          //                .error
		.rdata_fifo_src_ready    (c0_csr_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (c0_csr_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (c0_csr_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                        //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (76),
		.FIFO_DEPTH          (5),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) c0_csr_agent_rsp_fifo (
		.clk               (csr_clk_out_clk_clk),                        //       clk.clk
		.reset             (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (c0_csr_agent_rf_source_data),                //        in.data
		.in_valid          (c0_csr_agent_rf_source_valid),               //          .valid
		.in_ready          (c0_csr_agent_rf_source_ready),               //          .ready
		.in_startofpacket  (c0_csr_agent_rf_source_startofpacket),       //          .startofpacket
		.in_endofpacket    (c0_csr_agent_rf_source_endofpacket),         //          .endofpacket
		.out_data          (c0_csr_agent_rsp_fifo_out_data),             //       out.data
		.out_valid         (c0_csr_agent_rsp_fifo_out_valid),            //          .valid
		.out_ready         (c0_csr_agent_rsp_fifo_out_ready),            //          .ready
		.out_startofpacket (c0_csr_agent_rsp_fifo_out_startofpacket),    //          .startofpacket
		.out_endofpacket   (c0_csr_agent_rsp_fifo_out_endofpacket),      //          .endofpacket
		.csr_address       (2'b00),                                      // (terminated)
		.csr_read          (1'b0),                                       // (terminated)
		.csr_write         (1'b0),                                       // (terminated)
		.csr_readdata      (),                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),       // (terminated)
		.almost_full_data  (),                                           // (terminated)
		.almost_empty_data (),                                           // (terminated)
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.in_error          (1'b0),                                       // (terminated)
		.out_error         (),                                           // (terminated)
		.in_channel        (1'b0),                                       // (terminated)
		.out_channel       ()                                            // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (10),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) c0_csr_agent_rdata_fifo (
		.clk               (csr_clk_out_clk_clk),                        //       clk.clk
		.reset             (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (c0_csr_agent_rdata_fifo_src_data),           //        in.data
		.in_valid          (c0_csr_agent_rdata_fifo_src_valid),          //          .valid
		.in_ready          (c0_csr_agent_rdata_fifo_src_ready),          //          .ready
		.out_data          (c0_csr_agent_rdata_fifo_out_data),           //       out.data
		.out_valid         (c0_csr_agent_rdata_fifo_out_valid),          //          .valid
		.out_ready         (c0_csr_agent_rdata_fifo_out_ready),          //          .ready
		.csr_address       (2'b00),                                      // (terminated)
		.csr_read          (1'b0),                                       // (terminated)
		.csr_write         (1'b0),                                       // (terminated)
		.csr_readdata      (),                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),       // (terminated)
		.almost_full_data  (),                                           // (terminated)
		.almost_empty_data (),                                           // (terminated)
		.in_startofpacket  (1'b0),                                       // (terminated)
		.in_endofpacket    (1'b0),                                       // (terminated)
		.out_startofpacket (),                                           // (terminated)
		.out_endofpacket   (),                                           // (terminated)
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.in_error          (1'b0),                                       // (terminated)
		.out_error         (),                                           // (terminated)
		.in_channel        (1'b0),                                       // (terminated)
		.out_channel       ()                                            // (terminated)
	);

	ddr3_mm_interconnect_2_router router (
		.sink_ready         (if_csr_m0_master_agent_cp_ready),            //      sink.ready
		.sink_valid         (if_csr_m0_master_agent_cp_valid),            //          .valid
		.sink_data          (if_csr_m0_master_agent_cp_data),             //          .data
		.sink_startofpacket (if_csr_m0_master_agent_cp_startofpacket),    //          .startofpacket
		.sink_endofpacket   (if_csr_m0_master_agent_cp_endofpacket),      //          .endofpacket
		.clk                (csr_clk_out_clk_clk),                        //       clk.clk
		.reset              (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                           //       src.ready
		.src_valid          (router_src_valid),                           //          .valid
		.src_data           (router_src_data),                            //          .data
		.src_channel        (router_src_channel),                         //          .channel
		.src_startofpacket  (router_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                      //          .endofpacket
	);

	ddr3_mm_interconnect_2_router_001 router_001 (
		.sink_ready         (p0_csr_agent_rp_ready),                      //      sink.ready
		.sink_valid         (p0_csr_agent_rp_valid),                      //          .valid
		.sink_data          (p0_csr_agent_rp_data),                       //          .data
		.sink_startofpacket (p0_csr_agent_rp_startofpacket),              //          .startofpacket
		.sink_endofpacket   (p0_csr_agent_rp_endofpacket),                //          .endofpacket
		.clk                (csr_clk_out_clk_clk),                        //       clk.clk
		.reset              (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                       //       src.ready
		.src_valid          (router_001_src_valid),                       //          .valid
		.src_data           (router_001_src_data),                        //          .data
		.src_channel        (router_001_src_channel),                     //          .channel
		.src_startofpacket  (router_001_src_startofpacket),               //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                  //          .endofpacket
	);

	ddr3_mm_interconnect_2_router_002 router_002 (
		.sink_ready         (c0_csr_agent_rp_ready),                      //      sink.ready
		.sink_valid         (c0_csr_agent_rp_valid),                      //          .valid
		.sink_data          (c0_csr_agent_rp_data),                       //          .data
		.sink_startofpacket (c0_csr_agent_rp_startofpacket),              //          .startofpacket
		.sink_endofpacket   (c0_csr_agent_rp_endofpacket),                //          .endofpacket
		.clk                (csr_clk_out_clk_clk),                        //       clk.clk
		.reset              (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                       //       src.ready
		.src_valid          (router_002_src_valid),                       //          .valid
		.src_data           (router_002_src_data),                        //          .data
		.src_channel        (router_002_src_channel),                     //          .channel
		.src_startofpacket  (router_002_src_startofpacket),               //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                  //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (88),
		.PKT_DEST_ID_L             (88),
		.PKT_SRC_ID_H              (87),
		.PKT_SRC_ID_L              (87),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (6),
		.PIPELINED                 (0),
		.ST_DATA_W                 (102),
		.ST_CHANNEL_W              (2),
		.VALID_WIDTH               (2),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) if_csr_m0_master_limiter (
		.clk                    (csr_clk_out_clk_clk),                            //       clk.clk
		.reset                  (p0_csr_reset_n_reset_bridge_in_reset_reset),     // clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                               //  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                               //          .valid
		.cmd_sink_data          (router_src_data),                                //          .data
		.cmd_sink_channel       (router_src_channel),                             //          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                       //          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                         //          .endofpacket
		.cmd_src_ready          (if_csr_m0_master_limiter_cmd_src_ready),         //   cmd_src.ready
		.cmd_src_data           (if_csr_m0_master_limiter_cmd_src_data),          //          .data
		.cmd_src_channel        (if_csr_m0_master_limiter_cmd_src_channel),       //          .channel
		.cmd_src_startofpacket  (if_csr_m0_master_limiter_cmd_src_startofpacket), //          .startofpacket
		.cmd_src_endofpacket    (if_csr_m0_master_limiter_cmd_src_endofpacket),   //          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                              //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                              //          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                            //          .channel
		.rsp_sink_data          (rsp_mux_src_data),                               //          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                      //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                        //          .endofpacket
		.rsp_src_ready          (if_csr_m0_master_limiter_rsp_src_ready),         //   rsp_src.ready
		.rsp_src_valid          (if_csr_m0_master_limiter_rsp_src_valid),         //          .valid
		.rsp_src_data           (if_csr_m0_master_limiter_rsp_src_data),          //          .data
		.rsp_src_channel        (if_csr_m0_master_limiter_rsp_src_channel),       //          .channel
		.rsp_src_startofpacket  (if_csr_m0_master_limiter_rsp_src_startofpacket), //          .startofpacket
		.rsp_src_endofpacket    (if_csr_m0_master_limiter_rsp_src_endofpacket),   //          .endofpacket
		.cmd_src_valid          (if_csr_m0_master_limiter_cmd_valid_data)         // cmd_valid.data
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (40),
		.PKT_ADDR_L                (9),
		.PKT_BEGIN_BURST           (58),
		.PKT_BYTE_CNT_H            (49),
		.PKT_BYTE_CNT_L            (47),
		.PKT_BYTEEN_H              (8),
		.PKT_BYTEEN_L              (8),
		.PKT_BURST_SIZE_H          (53),
		.PKT_BURST_SIZE_L          (51),
		.PKT_BURST_TYPE_H          (55),
		.PKT_BURST_TYPE_L          (54),
		.PKT_BURSTWRAP_H           (50),
		.PKT_BURSTWRAP_L           (50),
		.PKT_TRANS_COMPRESSED_READ (41),
		.PKT_TRANS_WRITE           (43),
		.PKT_TRANS_READ            (44),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (75),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (47),
		.OUT_BURSTWRAP_H           (50),
		.COMPRESSED_READ_SUPPORT   (0),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (1),
		.BURSTWRAP_CONST_VALUE     (1),
		.ADAPTER_VERSION           ("13.1")
	) c0_csr_burst_adapter (
		.clk                   (csr_clk_out_clk_clk),                        //       cr0.clk
		.reset                 (p0_csr_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.sink0_valid           (c0_csr_cmd_width_adapter_src_valid),         //     sink0.valid
		.sink0_data            (c0_csr_cmd_width_adapter_src_data),          //          .data
		.sink0_channel         (c0_csr_cmd_width_adapter_src_channel),       //          .channel
		.sink0_startofpacket   (c0_csr_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.sink0_endofpacket     (c0_csr_cmd_width_adapter_src_endofpacket),   //          .endofpacket
		.sink0_ready           (c0_csr_cmd_width_adapter_src_ready),         //          .ready
		.source0_valid         (c0_csr_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (c0_csr_burst_adapter_source0_data),          //          .data
		.source0_channel       (c0_csr_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (c0_csr_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (c0_csr_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (c0_csr_burst_adapter_source0_ready)          //          .ready
	);

	ddr3_mm_interconnect_2_cmd_demux cmd_demux (
		.clk                (csr_clk_out_clk_clk),                            //        clk.clk
		.reset              (p0_csr_reset_n_reset_bridge_in_reset_reset),     //  clk_reset.reset
		.sink_ready         (if_csr_m0_master_limiter_cmd_src_ready),         //       sink.ready
		.sink_channel       (if_csr_m0_master_limiter_cmd_src_channel),       //           .channel
		.sink_data          (if_csr_m0_master_limiter_cmd_src_data),          //           .data
		.sink_startofpacket (if_csr_m0_master_limiter_cmd_src_startofpacket), //           .startofpacket
		.sink_endofpacket   (if_csr_m0_master_limiter_cmd_src_endofpacket),   //           .endofpacket
		.sink_valid         (if_csr_m0_master_limiter_cmd_valid_data),        // sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                           //       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                           //           .valid
		.src0_data          (cmd_demux_src0_data),                            //           .data
		.src0_channel       (cmd_demux_src0_channel),                         //           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                   //           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                     //           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                           //       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                           //           .valid
		.src1_data          (cmd_demux_src1_data),                            //           .data
		.src1_channel       (cmd_demux_src1_channel),                         //           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                   //           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                      //           .endofpacket
	);

	ddr3_mm_interconnect_2_cmd_mux cmd_mux (
		.clk                 (csr_clk_out_clk_clk),                        //       clk.clk
		.reset               (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_src_valid),                          //          .valid
		.src_data            (cmd_mux_src_data),                           //          .data
		.src_channel         (cmd_mux_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                       //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                     //          .channel
		.sink0_data          (cmd_demux_src0_data),                        //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                  //          .endofpacket
	);

	ddr3_mm_interconnect_2_cmd_mux cmd_mux_001 (
		.clk                 (csr_clk_out_clk_clk),                        //       clk.clk
		.reset               (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                      //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                      //          .valid
		.src_data            (cmd_mux_001_src_data),                       //          .data
		.src_channel         (cmd_mux_001_src_channel),                    //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),              //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                //          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                       //          .valid
		.sink0_channel       (cmd_demux_src1_channel),                     //          .channel
		.sink0_data          (cmd_demux_src1_data),                        //          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                  //          .endofpacket
	);

	ddr3_mm_interconnect_2_rsp_demux rsp_demux (
		.clk                (csr_clk_out_clk_clk),                        //       clk.clk
		.reset              (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                       //      sink.ready
		.sink_channel       (router_001_src_channel),                     //          .channel
		.sink_data          (router_001_src_data),                        //          .data
		.sink_startofpacket (router_001_src_startofpacket),               //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                 //          .endofpacket
		.sink_valid         (router_001_src_valid),                       //          .valid
		.src0_ready         (rsp_demux_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_src0_data),                        //          .data
		.src0_channel       (rsp_demux_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                  //          .endofpacket
	);

	ddr3_mm_interconnect_2_rsp_demux rsp_demux_001 (
		.clk                (csr_clk_out_clk_clk),                        //       clk.clk
		.reset              (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (c0_csr_rsp_width_adapter_src_ready),         //      sink.ready
		.sink_channel       (c0_csr_rsp_width_adapter_src_channel),       //          .channel
		.sink_data          (c0_csr_rsp_width_adapter_src_data),          //          .data
		.sink_startofpacket (c0_csr_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (c0_csr_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink_valid         (c0_csr_rsp_width_adapter_src_valid),         //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                   //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                   //          .valid
		.src0_data          (rsp_demux_001_src0_data),                    //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                 //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),           //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)              //          .endofpacket
	);

	ddr3_mm_interconnect_2_rsp_mux rsp_mux (
		.clk                 (csr_clk_out_clk_clk),                        //       clk.clk
		.reset               (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                          //       src.ready
		.src_valid           (rsp_mux_src_valid),                          //          .valid
		.src_data            (rsp_mux_src_data),                           //          .data
		.src_channel         (rsp_mux_src_channel),                        //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                       //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                       //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                     //          .channel
		.sink0_data          (rsp_demux_src0_data),                        //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                 //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                   //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                   //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                 //          .channel
		.sink1_data          (rsp_demux_001_src0_data),                    //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),           //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket)              //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (40),
		.IN_PKT_ADDR_L                 (9),
		.IN_PKT_DATA_H                 (7),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (8),
		.IN_PKT_BYTEEN_L               (8),
		.IN_PKT_BYTE_CNT_H             (49),
		.IN_PKT_BYTE_CNT_L             (47),
		.IN_PKT_TRANS_COMPRESSED_READ  (41),
		.IN_PKT_TRANS_WRITE            (43),
		.IN_PKT_BURSTWRAP_H            (50),
		.IN_PKT_BURSTWRAP_L            (50),
		.IN_PKT_BURST_SIZE_H           (53),
		.IN_PKT_BURST_SIZE_L           (51),
		.IN_PKT_RESPONSE_STATUS_H      (71),
		.IN_PKT_RESPONSE_STATUS_L      (70),
		.IN_PKT_TRANS_EXCLUSIVE        (46),
		.IN_PKT_BURST_TYPE_H           (55),
		.IN_PKT_BURST_TYPE_L           (54),
		.IN_PKT_ORI_BURST_SIZE_L       (72),
		.IN_PKT_ORI_BURST_SIZE_H       (74),
		.IN_ST_DATA_W                  (75),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (76),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (80),
		.OUT_PKT_BURST_SIZE_L          (78),
		.OUT_PKT_RESPONSE_STATUS_H     (98),
		.OUT_PKT_RESPONSE_STATUS_L     (97),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (82),
		.OUT_PKT_BURST_TYPE_L          (81),
		.OUT_PKT_ORI_BURST_SIZE_L      (99),
		.OUT_PKT_ORI_BURST_SIZE_H      (101),
		.OUT_ST_DATA_W                 (102),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) c0_csr_rsp_width_adapter (
		.clk                  (csr_clk_out_clk_clk),                        //       clk.clk
		.reset                (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (router_002_src_valid),                       //      sink.valid
		.in_channel           (router_002_src_channel),                     //          .channel
		.in_startofpacket     (router_002_src_startofpacket),               //          .startofpacket
		.in_endofpacket       (router_002_src_endofpacket),                 //          .endofpacket
		.in_ready             (router_002_src_ready),                       //          .ready
		.in_data              (router_002_src_data),                        //          .data
		.out_endofpacket      (c0_csr_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (c0_csr_rsp_width_adapter_src_data),          //          .data
		.out_channel          (c0_csr_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (c0_csr_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (c0_csr_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (c0_csr_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                      // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (76),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (77),
		.IN_PKT_BURSTWRAP_L            (77),
		.IN_PKT_BURST_SIZE_H           (80),
		.IN_PKT_BURST_SIZE_L           (78),
		.IN_PKT_RESPONSE_STATUS_H      (98),
		.IN_PKT_RESPONSE_STATUS_L      (97),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (82),
		.IN_PKT_BURST_TYPE_L           (81),
		.IN_PKT_ORI_BURST_SIZE_L       (99),
		.IN_PKT_ORI_BURST_SIZE_H       (101),
		.IN_ST_DATA_W                  (102),
		.OUT_PKT_ADDR_H                (40),
		.OUT_PKT_ADDR_L                (9),
		.OUT_PKT_DATA_H                (7),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (8),
		.OUT_PKT_BYTEEN_L              (8),
		.OUT_PKT_BYTE_CNT_H            (49),
		.OUT_PKT_BYTE_CNT_L            (47),
		.OUT_PKT_TRANS_COMPRESSED_READ (41),
		.OUT_PKT_BURST_SIZE_H          (53),
		.OUT_PKT_BURST_SIZE_L          (51),
		.OUT_PKT_RESPONSE_STATUS_H     (71),
		.OUT_PKT_RESPONSE_STATUS_L     (70),
		.OUT_PKT_TRANS_EXCLUSIVE       (46),
		.OUT_PKT_BURST_TYPE_H          (55),
		.OUT_PKT_BURST_TYPE_L          (54),
		.OUT_PKT_ORI_BURST_SIZE_L      (72),
		.OUT_PKT_ORI_BURST_SIZE_H      (74),
		.OUT_ST_DATA_W                 (75),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) c0_csr_cmd_width_adapter (
		.clk                  (csr_clk_out_clk_clk),                        //       clk.clk
		.reset                (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (cmd_mux_001_src_valid),                      //      sink.valid
		.in_channel           (cmd_mux_001_src_channel),                    //          .channel
		.in_startofpacket     (cmd_mux_001_src_startofpacket),              //          .startofpacket
		.in_endofpacket       (cmd_mux_001_src_endofpacket),                //          .endofpacket
		.in_ready             (cmd_mux_001_src_ready),                      //          .ready
		.in_data              (cmd_mux_001_src_data),                       //          .data
		.out_endofpacket      (c0_csr_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (c0_csr_cmd_width_adapter_src_data),          //          .data
		.out_channel          (c0_csr_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (c0_csr_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (c0_csr_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (c0_csr_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                      // (terminated)
	);

	ddr3_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (csr_clk_out_clk_clk),                        // in_clk_0.clk
		.in_rst_0_reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (p0_csr_agent_rdata_fifo_src_data),           //     in_0.data
		.in_0_valid     (p0_csr_agent_rdata_fifo_src_valid),          //         .valid
		.in_0_ready     (p0_csr_agent_rdata_fifo_src_ready),          //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)               //         .error
	);

	ddr3_mm_interconnect_2_avalon_st_adapter_001 #(
		.inBitsPerSymbol (10),
		.inUsePackets    (0),
		.inDataWidth     (10),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (10),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (csr_clk_out_clk_clk),                        // in_clk_0.clk
		.in_rst_0_reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (c0_csr_agent_rdata_fifo_out_data),           //     in_0.data
		.in_0_valid     (c0_csr_agent_rdata_fifo_out_valid),          //         .valid
		.in_0_ready     (c0_csr_agent_rdata_fifo_out_ready),          //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),           //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),          //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),          //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)           //         .error
	);

endmodule
