library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity edgeDetector is
	port(
		clk         : in  std_logic;
		rst         : in  std_logic;
		sig         : in  std_logic;
		risingEdge  : out std_logic;
		fallingEdge : out std_logic;
		anyEdge     : out std_logic
	);
end entity edgeDetector;

architecture RTL of edgeDetector is
	signal temp : std_logic_vector(1 downto 0);
begin
	shiftomat : process(rst, clk) is
	begin
		if rst = '1' then
			temp <= "00";
		elsif rising_edge(clk) then
			temp <= temp(0) & sig;
		end if;
	end process shiftomat;

	risingEdge  <= '1' when (temp = "01") else '0';
	fallingEdge <= '1' when (temp = "10") else '0';
	anyEdge     <= '1' when (temp = "01" or temp = "10") else '0';	
end architecture RTL;
