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-- software and tools, and its AMPP partner logic functions, and any output 
-- files any of the foregoing (including device programming or simulation 
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-- Agreement, Altera MegaCore Function License Agreement, or other applicable 
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Library ieee;
use ieee.std_logic_1164.all;

entity ddr3_pll0_sim_delay is
   generic (
     delay     : natural := 1);

   port (
     o   : out std_logic;
     i   : in  std_logic);
end ddr3_pll0_sim_delay;

architecture behavior of ddr3_pll0_sim_delay is
begin
  o <= i after delay * 1 ps;
end behavior;

