library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library design;
use design.all;

library ip;
use ip.wishbone_package.all;

entity bench_top is
end entity bench_top;

architecture RTL of bench_top is
	signal clk_hw       : std_logic;
	signal rst_hw       : std_logic;
	signal GPIOA        : std_logic_vector(wishbone_data_width - 1 downto 0);
	signal jinn_uart_rx : std_logic;
	signal jinn_uart_tx : std_logic;
	signal uart_rx      : std_logic;
	signal uart_tx      : std_logic;
	-- DDR3
	signal mem_a        : std_logic_vector(12 downto 0);
	signal mem_ba       : std_logic_vector(2 downto 0);
	signal mem_ck       : std_logic_vector(0 downto 0);
	signal mem_ck_n     : std_logic_vector(0 downto 0);
	signal mem_cke      : std_logic_vector(0 downto 0);
	signal mem_cs_n     : std_logic_vector(0 downto 0);
	signal mem_dm       : std_logic_vector(1 downto 0);
	signal mem_ras_n    : std_logic_vector(0 downto 0);
	signal mem_cas_n    : std_logic_vector(0 downto 0);
	signal mem_we_n     : std_logic_vector(0 downto 0);
	signal mem_reset_n  : std_logic;
	signal mem_dq       : std_logic_vector(15 downto 0);
	signal mem_dqs      : std_logic_vector(1 downto 0);
	signal mem_dqs_n    : std_logic_vector(1 downto 0);
	signal mem_odt      : std_logic_vector(0 downto 0);
	signal oct_rzqin    : std_logic;
begin
	top_inst : entity design.top
		port map(
			clk_hw       => clk_hw,
			rst_hw       => rst_hw,
			GPIOA        => GPIOA,
			jinn_uart_rx => jinn_uart_rx,
			jinn_uart_tx => jinn_uart_tx,
			uart_rx      => uart_rx,
			uart_tx      => uart_tx,
			mem_a        => mem_a,
			mem_ba       => mem_ba,
			mem_ck       => mem_ck,
			mem_ck_n     => mem_ck_n,
			mem_cke      => mem_cke,
			mem_cs_n     => mem_cs_n,
			mem_dm       => mem_dm,
			mem_ras_n    => mem_ras_n,
			mem_cas_n    => mem_cas_n,
			mem_we_n     => mem_we_n,
			mem_reset_n  => mem_reset_n,
			mem_dq       => mem_dq,
			mem_dqs      => mem_dqs,
			mem_dqs_n    => mem_dqs_n,
			mem_odt      => mem_odt,
			oct_rzqin    => oct_rzqin
		);

	clock_driver : process
		constant period : time := 10 ns;
	begin
		clk_hw <= '0';
		wait for period / 2;
		clk_hw  <= '1';
		wait for period / 2;
	end process clock_driver;

	test : process is
	begin
		rst_hw <= '0';
		wait for 50 ns;
		rst_hw <= '1';
		wait;
	end process test;

end architecture RTL;
