library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_package.all;

entity test_slave is
  generic(
    delay : integer := 1
  );
  port(
    -- Common wishbone signals
    clk        : in  std_logic;
    rst        : in  std_logic;
    -- Slave control port
    slave_i    : in  wishbone_slave_in;
    slave_o    : out wishbone_slave_out
  );
end test_slave;

architecture rtl of test_slave is
  type result_t is array(delay downto 0) of wishbone_data;
  signal ack_shift : std_logic_vector(delay downto 0);
  signal res_shift : result_t;
begin
  slave_o.ACK <= ack_shift(0);
  slave_o.ERR <= '0';
  slave_o.RTY <= '0';
  slave_o.DAT <= res_shift(0);
  slave_o.STALL <= '0';
  
  ack_shift(delay) <= slave_i.STB and slave_i.CYC;
  
  main : process(clk)
  begin
    if rising_edge(clk) then
      if (rst = '1') then
        ack_shift(delay-1 downto 0) <= (others => '0');
        res_shift <= (others => (others => '0'));
      else
        if (slave_i.CYC = '1' and slave_i.STB = '1' and slave_i.WE = '0') then
          res_shift(delay) <= std_logic_vector(unsigned(res_shift(delay)) + 1);
        end if;
        ack_shift(delay-1 downto 0) <= ack_shift(delay downto 1);
        res_shift(delay-1 downto 0) <= res_shift(delay downto 1);
      end if;
    end if;
  end process;
end rtl;
