diff --git a/cores/flashrom-wb/flashrom_spi.vhd b/cores/flashrom-wb/flashrom_spi.vhd index 39f1164..7249ea0 100644 --- a/cores/flashrom-wb/flashrom_spi.vhd +++ b/cores/flashrom-wb/flashrom_spi.vhd @@ -45,6 +45,7 @@ architecture RTL of flashrom_spi is signal oneBitRead : std_logic; signal pseudoEdge : boolean; signal dummy_passed : boolean; + signal prevent_retrig : boolean; begin toSpi : process(clk, rst) is procedure default_state is @@ -77,20 +78,28 @@ begin else case state is when IDLE => - delayCycle <= '0'; - spi_sck <= '0'; - oneBitRead <= '0'; - dummy_passed <= false; - data_out <= (others => '0'); - if data_in_valid = '1' then - state <= TX; - bitCounter <= 0; - bitCounterIn <= 0; - data_in_length_i <= 0; - pseudoEdge <= true; + prevent_retrig <= false; + delayCycle <= '0'; + spi_sck <= '0'; + oneBitRead <= '0'; + dummy_passed <= false; + data_out <= (others => '0'); + if ckDiv = clk_divider - 2 then -- ensures cs inactive time between transactions + if data_in_valid = '1' then + ckDiv <= 0; + state <= TX; + bitCounter <= 0; + bitCounterIn <= 0; + data_in_length_i <= 0; + pseudoEdge <= true; + end if; + else + ckDiv <= ckDiv + 1; end if; - ckDiv <= 0; when TX => + if data_in_valid = '0' then + prevent_retrig <= true; + end if; if ckDiv = clk_divider - 2 or pseudoEdge then ckDiv <= 0; if not pseudoEdge then @@ -104,7 +113,7 @@ begin if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data if bitCounter = data_in_length_i then bitCounter <= 0; - if data_in_valid = '1' then + if data_in_valid = '1' and not prevent_retrig then shiftreg <= data_in; data_in_length_i <= data_in_length - 1; data_out_length_i <= data_out_length - 1; @@ -140,6 +149,7 @@ begin if delayCycle = '1' then spi_sck <= '0'; state <= IDLE; + ckDiv <= 0; end if; end if; end if;