flashrom: Added write command, fixed read command
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				| @ -39,8 +39,8 @@ architecture rtl of bench_flashrom_controller is | ||||
| 	signal status_update_stb : std_logic; | ||||
| 	signal status            : std_logic_vector(7 downto 0); | ||||
| 	signal info              : std_logic_vector(31 downto 0); | ||||
| 	signal data_in           : std_logic_vector(7 downto 0); | ||||
| 	signal data_in_valid     : std_logic; | ||||
| 	signal data_in           : std_logic_vector(7 downto 0) := x"00"; | ||||
| 	signal data_in_next      : std_logic; | ||||
| 	signal data_out          : std_logic_vector(7 downto 0); | ||||
| 	signal data_out_valid    : std_logic; | ||||
| 	signal spi_si            : std_logic; | ||||
| @ -50,7 +50,7 @@ architecture rtl of bench_flashrom_controller is | ||||
| 	signal spi_cs_n          : std_logic; | ||||
| 	signal spi_wp_n          : std_logic; | ||||
| 	signal spi_busy          : std_logic; | ||||
| 	signal spi_clk_cnt       : integer := 0; | ||||
| 	signal spi_clk_cnt       : integer                      := 0; | ||||
| 
 | ||||
| begin | ||||
| 	DataFlash_inst : entity work.DataFlash | ||||
| @ -83,7 +83,7 @@ begin | ||||
| 			status            => status, | ||||
| 			info              => info, | ||||
| 			data_in           => data_in, | ||||
| 			data_in_valid     => data_in_valid, | ||||
| 			data_in_next      => data_in_next, | ||||
| 			data_out          => data_out, | ||||
| 			data_out_valid    => data_out_valid, | ||||
| 			spi_si            => spi_si, | ||||
| @ -125,61 +125,35 @@ begin | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		wait for 100 us; | ||||
| 		strobe(sync_stb);               -- Make sure background_op_enable is '1' in device model (power up delay) | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		wait until spi_busy = '1'; | ||||
| 		wait for 100 us; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(load_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait; | ||||
| 	end process bench; | ||||
| 
 | ||||
| 	spiclkcounter : process is | ||||
| 	begin | ||||
| 		wait until spi_sck = '1'; | ||||
| 		wait until data_out_valid = '1'; | ||||
| 		spi_clk_cnt <= spi_clk_cnt + 1; | ||||
| 	end process spiclkcounter; | ||||
| 
 | ||||
| 	data_provider : process is | ||||
| 	begin | ||||
| 		wait until data_in_next = '1'; | ||||
| 		--wait until data_in_next = '1'; | ||||
| 		data_in <= std_logic_vector(unsigned(data_in) + 1); | ||||
| 	end process data_provider; | ||||
| 
 | ||||
| end architecture rtl; | ||||
|  | ||||
| @ -21,7 +21,7 @@ entity flashrom_controller is | ||||
| 
 | ||||
| 		-- Data IF		 | ||||
| 		data_in           : in  std_logic_vector(7 downto 0); | ||||
| 		data_in_valid     : in  std_logic; | ||||
| 		data_in_next      : out std_logic; | ||||
| 		data_out          : out std_logic_vector(7 downto 0); | ||||
| 		data_out_valid    : out std_logic; | ||||
| 
 | ||||
| @ -40,7 +40,7 @@ architecture RTL of flashrom_controller is | ||||
| 	constant max_dummy_bits       : integer := 63; | ||||
| 	constant bootup_delay         : integer := 4000; | ||||
| 
 | ||||
| 	type state_t is (INIT, GETINFO, GETSTATUS, LOADPAGE, IDLE); | ||||
| 	type state_t is (INIT, GETINFO, GETSTATUS, LOADPAGE, WRITEPAGE, IDLE); | ||||
| 	signal state : state_t; | ||||
| 
 | ||||
| 	signal spif_data_in_valid   : std_logic; | ||||
| @ -54,6 +54,7 @@ architecture RTL of flashrom_controller is | ||||
| 	signal words_sent               : integer range 0 to 511; | ||||
| 	signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits; | ||||
| 	signal spif_transmission_active : std_logic; | ||||
| 	signal command_is_latched       : boolean; | ||||
| begin | ||||
| 	spi_wp_n <= '1'; | ||||
| 
 | ||||
| @ -81,14 +82,15 @@ begin | ||||
| 			transmission_active => spif_transmission_active); | ||||
| 
 | ||||
| 	flashrom_controller_p : process(clk, rst) is | ||||
| 		variable temp_cnt : integer range 0 to bootup_delay; | ||||
| 		variable done     : boolean; | ||||
| 		variable write_cnt : integer range 0 to bootup_delay; | ||||
| 		variable done      : boolean; | ||||
| 
 | ||||
| 		procedure default_state is | ||||
| 		begin | ||||
| 			spi_reset_n        <= '1'; | ||||
| 			spif_data_in_valid <= '0'; | ||||
| 			done               := false; | ||||
| 			command_is_latched <= false; | ||||
| 		end procedure default_state; | ||||
| 
 | ||||
| 		procedure reset_state is | ||||
| @ -97,13 +99,14 @@ begin | ||||
| 			state       <= INIT; | ||||
| 			spi_reset_n <= '0'; | ||||
| 			words_sent  <= 0; | ||||
| 			write_cnt   := 0; | ||||
| 
 | ||||
| 			spif_data_in             <= (others => '0'); | ||||
| 			spif_data_in_length      <= 0; | ||||
| 			spif_data_out_length     <= 0; | ||||
| 			spif_data_out_dummy_bits <= 0; | ||||
| 
 | ||||
| 			temp_cnt := 0; | ||||
| 			write_cnt := 0; | ||||
| 		end procedure reset_state; | ||||
| 
 | ||||
| 		procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector) is | ||||
| @ -114,17 +117,17 @@ begin | ||||
| 			spif_data_in_valid       <= '1'; | ||||
| 			spif_data_in             <= data_in & padBits(spif_data_in, data_in); | ||||
| 
 | ||||
| 			if temp_cnt = nTxWords then | ||||
| 			if write_cnt = nTxWords then | ||||
| 				spif_data_in_valid <= '0'; | ||||
| 			elsif spif_data_next = '1' then | ||||
| 				temp_cnt := temp_cnt + 1; | ||||
| 				write_cnt := write_cnt + 1; | ||||
| 			end if; | ||||
| 
 | ||||
| 			if spif_data_out_valid = '1' and (temp_cnt = nTxWords) then | ||||
| 			if spif_data_out_valid = '1' and (write_cnt = nTxWords) then | ||||
| 				spif_data_in_valid <= '0'; | ||||
| 				done               := true; | ||||
| 				state              <= IDLE; | ||||
| 				temp_cnt           := 0; | ||||
| 				write_cnt          := 0; | ||||
| 			end if; | ||||
| 		end procedure run_command_single; | ||||
| 
 | ||||
| @ -139,11 +142,11 @@ begin | ||||
| 				case state is | ||||
| 					when INIT => | ||||
| 						words_sent <= 0; | ||||
| 						if temp_cnt = bootup_delay then | ||||
| 							temp_cnt := 0; | ||||
| 							state    <= GETINFO; | ||||
| 						if write_cnt = bootup_delay then | ||||
| 							write_cnt := 0; | ||||
| 							state     <= GETINFO; | ||||
| 						else | ||||
| 							temp_cnt := temp_cnt + 1; | ||||
| 							write_cnt := write_cnt + 1; | ||||
| 						end if; | ||||
| 					when GETINFO =>     -- TODO: In simulation I can only call this command once?! | ||||
| 						run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID); | ||||
| @ -151,23 +154,38 @@ begin | ||||
| 							info <= spif_data_out; | ||||
| 						end if; | ||||
| 					when IDLE => | ||||
| 						temp_cnt := 0; | ||||
| 						write_cnt := 0; | ||||
| 						if status_update_stb = '1' then | ||||
| 							state <= GETSTATUS; | ||||
| 						end if; | ||||
| 						if load_stb = '1' then --debug only | ||||
| 						if load_stb = '1' then | ||||
| 							state <= LOADPAGE; | ||||
| 						end if; | ||||
| 						if sync_stb = '1' then | ||||
| 							state <= WRITEPAGE; | ||||
| 						end if; | ||||
| 					when GETSTATUS => | ||||
| 						run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS); | ||||
| 						if done then | ||||
| 							status <= spif_data_out(7 downto 0); | ||||
| 						end if; | ||||
| 					when LOADPAGE => | ||||
| 						run_command_single(24, 8, 34, 256/3+3, FLASHROM_COMMAND_CONT_ARRAY_READ & page); -- TODO: This will read one byte too far | ||||
| 						run_command_single(32, 8, 34, 258, FLASHROM_COMMAND_CONT_ARRAY_READ & page); | ||||
| 						if spif_data_next = '1' or command_is_latched then | ||||
| 							command_is_latched  <= true; | ||||
| 							spif_data_in_length <= 8; | ||||
| 							spif_data_in        <= (others => '0'); | ||||
| 						end if; | ||||
| 						if done then | ||||
| 							report "Load page done." severity note; | ||||
| 						end if; | ||||
| 					when WRITEPAGE => | ||||
| 						run_command_single(32, 8, 34, 257, FLASHROM_COMMAND_WRITE_THROUGH_1 & page); | ||||
| 						if spif_data_next = '1' or command_is_latched then | ||||
| 							command_is_latched  <= true; | ||||
| 							spif_data_in_length <= 8; | ||||
| 							spif_data_in        <= data_in & padBits(spif_data_in, data_in); | ||||
| 						end if; | ||||
| 				end case; | ||||
| 			end if; | ||||
| 		end if; | ||||
| @ -176,4 +194,5 @@ begin | ||||
| 
 | ||||
| 	data_out       <= spif_data_out(7 downto 0); | ||||
| 	data_out_valid <= spif_data_out_valid when state = LOADPAGE else '0'; | ||||
| 	data_in_next   <= spif_data_next when (state = WRITEPAGE) and command_is_latched else '0'; | ||||
| end architecture RTL; | ||||
|  | ||||
| @ -7,7 +7,8 @@ package flashrom_pkg is | ||||
| 	constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; | ||||
| 	constant FLASHROM_COMMAND_GET_STATUS      : std_logic_vector(7 downto 0) := x"D7"; | ||||
| 	constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B"; | ||||
| 
 | ||||
| 	constant FLASHROM_COMMAND_WRITE_THROUGH_1 : std_logic_vector(7 downto 0) := x"82"; | ||||
| 	 | ||||
| 	function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector; | ||||
| end package flashrom_pkg; | ||||
| 
 | ||||
|  | ||||
							
								
								
									
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								wave/flashrom_controller.do
									
									
									
									
									
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								wave/flashrom_controller.do
									
									
									
									
									
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							| @ -0,0 +1,85 @@ | ||||
| onerror {resume} | ||||
| quietly WaveActivateNextPane {} 0 | ||||
| add wave -noupdate /bench_flashrom_controller/DataFlash_inst/RDYBSY | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/clk | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/rst | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/clr | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/ready | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/page | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/sync_stb | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/load_stb | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/status_update_stb | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/status | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/info | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_in_next | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_in | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_out | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_out_valid | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_si | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_so | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_sck | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_reset_n | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_cs_n | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_wp_n | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/state | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in_valid | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in_length | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_next | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_valid | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_length | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/words_sent | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_dummy_bits | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_transmission_active | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_max_word_length | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/max_dummy_bits | ||||
| add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/bootup_delay | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clk_divider | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/max_word_length | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/max_dummy_bits | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clk | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/rst | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clr | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_si | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_so | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_sck | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_cs_n | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_valid | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_length | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_next | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_valid | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_length | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_dummy_bits | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/transmission_active | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/state | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/ckDiv | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/shiftreg | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/bitCounter | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/bitCounterIn | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_length_i | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_length_i | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/delayCycle | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/oneBitRead | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/pseudoEdge | ||||
| add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/dummy_passed | ||||
| TreeUpdate [SetDefaultTree] | ||||
| WaveRestoreCursors {{Cursor 1} {40873000 ps} 1} {{Cursor 2} {16507398 ps} 0} {{Cursor 3} {1785398 ps} 0} | ||||
| quietly wave cursor active 2 | ||||
| configure wave -namecolwidth 150 | ||||
| configure wave -valuecolwidth 100 | ||||
| configure wave -justifyvalue left | ||||
| configure wave -signalnamewidth 1 | ||||
| configure wave -snapdistance 10 | ||||
| configure wave -datasetprefix 0 | ||||
| configure wave -rowmargin 4 | ||||
| configure wave -childrowmargin 2 | ||||
| configure wave -gridoffset 0 | ||||
| configure wave -gridperiod 1 | ||||
| configure wave -griddelta 40 | ||||
| configure wave -timeline 0 | ||||
| configure wave -timelineunits ns | ||||
| update | ||||
| WaveRestoreZoom {0 ps} {105 us} | ||||
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