diff --git a/design/top.vhd b/design/top.vhd index b259048..811614e 100644 --- a/design/top.vhd +++ b/design/top.vhd @@ -59,12 +59,12 @@ architecture RTL of top is -- WB config constant masters : natural := 3; - constant slaves : natural := 5; - constant INTERCON_ID_SRAM : natural := 0; - constant INTERCON_ID_DDR3 : natural := 1; - constant INTERCON_ID_FLASH : natural := 2; - constant INTERCON_ID_GPIO : natural := 3; - constant INTERCON_ID_UART : natural := 4; + constant slaves : natural := 4; + --constant INTERCON_ID_SRAM : natural := 0; + constant INTERCON_ID_DDR3 : natural := 0; + constant INTERCON_ID_FLASH : natural := 1; + constant INTERCON_ID_GPIO : natural := 2; + constant INTERCON_ID_UART : natural := 3; -- constant INTERCON_ID_NS16550 : natural := 4; constant in_simulation : boolean := false @@ -144,13 +144,13 @@ begin pll_locked <= '1'; -- SRAM - sram_wb_inst : entity work.sram_wb - port map( - clk => clk, - rst => rst, - wb_in => intercon_slave_i(INTERCON_ID_SRAM), - wb_out => intercon_slave_o(INTERCON_ID_SRAM) - ); + -- sram_wb_inst : entity work.sram_wb + -- port map( + -- clk => clk, + -- rst => rst, + -- wb_in => intercon_slave_i(INTERCON_ID_SRAM), + -- wb_out => intercon_slave_o(INTERCON_ID_SRAM) + -- ); -- CPU interrupt <= (others => '0'); @@ -363,16 +363,16 @@ begin master_i => intercon_slave_o, master_o => intercon_slave_i, address => ( - INTERCON_ID_SRAM => x"00000000", - INTERCON_ID_DDR3 => x"10000000", + --INTERCON_ID_SRAM => x"00000000", + INTERCON_ID_DDR3 => x"00000000", INTERCON_ID_FLASH => x"40000000", INTERCON_ID_GPIO => x"80000000", INTERCON_ID_UART => x"80000100" ), mask => ( - INTERCON_ID_SRAM => x"ffff0000", + --INTERCON_ID_SRAM => x"ffffff00", -- TODO: Match size of SRAM (or remove) INTERCON_ID_DDR3 => x"f0000000", - INTERCON_ID_FLASH => x"f0000000", + INTERCON_ID_FLASH => x"fffff000", -- TODO: Correct size INTERCON_ID_GPIO => x"fffffff0", INTERCON_ID_UART => x"ffffffc0" )