diff --git a/cores/uart/uart_wb.vhd b/cores/uart/uart_wb.vhd
index 5a1636e..e1192e9 100644
--- a/cores/uart/uart_wb.vhd
+++ b/cores/uart/uart_wb.vhd
@@ -1,3 +1,6 @@
+-- TODO: WARN: SEL bits ignored.
+-- TODO: Multiple ports is broken (address mapping * 4), plus some ACK error maybe?
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -14,8 +17,8 @@ entity uart_wb is
 		clk     : in  std_logic;
 		rst     : in  std_logic;
 		-- Wishbone
-		slave_i : in  wishbone_slave_in;
-		slave_o : out wishbone_slave_out;
+		slave_i : in  wishbone_v3_slave_in;
+		slave_o : out wishbone_v3_slave_out;
 		irq_o   : out std_logic_vector(portcount - 1 downto 0);
 		-- UART
 		rx      : in  std_logic_vector(portcount - 1 downto 0);
@@ -93,7 +96,7 @@ begin
 			end loop;
 		elsif rising_edge(clk) then
 			for i in 0 to portcount - 1 loop
-				slave_o.ACK <= '0';
+				slave_o.ACK  <= '0';
 				tx_strobe(i) <= '0';
 
 				--SR update
@@ -143,9 +146,8 @@ begin
 		end if;
 	end process wb;
 
-	slave_o.RTY   <= '0';
-	slave_o.STALL <= '0';
-	slave_o.ERR   <= '0';
+	slave_o.RTY <= '0';
+	slave_o.ERR <= '0';
 
 	applyCR : for i in 0 to portcount - 1 generate
 		ckDiv(i)        <= CR(i)(31 downto 16);