fpga/mor1kx-bemicrocv
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Converted UART to Wishbone v3

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This commit is contained in:
Markus Koch 2017-03-02 09:29:41 +01:00
parent 32434cf802
commit 4ca1ba0928
1 changed files with 8 additions and 6 deletions
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14
cores/uart/uart_wb.vhd
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@ -1,3 +1,6 @@
-- TODO: WARN: SEL bits ignored.
-- TODO: Multiple ports is broken (address mapping * 4), plus some ACK error maybe?
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@ -14,8 +17,8 @@ entity uart_wb is
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
-- Wishbone -- Wishbone
slave_i : in wishbone_slave_in; slave_i : in wishbone_v3_slave_in;
slave_o : out wishbone_slave_out; slave_o : out wishbone_v3_slave_out;
irq_o : out std_logic_vector(portcount - 1 downto 0); irq_o : out std_logic_vector(portcount - 1 downto 0);
-- UART -- UART
rx : in std_logic_vector(portcount - 1 downto 0); rx : in std_logic_vector(portcount - 1 downto 0);
@ -93,7 +96,7 @@ begin
end loop; end loop;
elsif rising_edge(clk) then elsif rising_edge(clk) then
for i in 0 to portcount - 1 loop for i in 0 to portcount - 1 loop
slave_o.ACK <= '0'; slave_o.ACK <= '0';
tx_strobe(i) <= '0'; tx_strobe(i) <= '0';
--SR update --SR update
@ -143,9 +146,8 @@ begin
end if; end if;
end process wb; end process wb;
slave_o.RTY <= '0'; slave_o.RTY <= '0';
slave_o.STALL <= '0'; slave_o.ERR <= '0';
slave_o.ERR <= '0';
applyCR : for i in 0 to portcount - 1 generate applyCR : for i in 0 to portcount - 1 generate
ckDiv(i) <= CR(i)(31 downto 16); ckDiv(i) <= CR(i)(31 downto 16);