Converted UART to Wishbone v3

This commit is contained in:
Markus Koch 2017-03-02 09:29:41 +01:00
parent 32434cf802
commit 4ca1ba0928
1 changed files with 8 additions and 6 deletions

View File

@ -1,3 +1,6 @@
-- TODO: WARN: SEL bits ignored.
-- TODO: Multiple ports is broken (address mapping * 4), plus some ACK error maybe?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@ -14,8 +17,8 @@ entity uart_wb is
clk : in std_logic;
rst : in std_logic;
-- Wishbone
slave_i : in wishbone_slave_in;
slave_o : out wishbone_slave_out;
slave_i : in wishbone_v3_slave_in;
slave_o : out wishbone_v3_slave_out;
irq_o : out std_logic_vector(portcount - 1 downto 0);
-- UART
rx : in std_logic_vector(portcount - 1 downto 0);
@ -144,7 +147,6 @@ begin
end process wb;
slave_o.RTY <= '0';
slave_o.STALL <= '0';
slave_o.ERR <= '0';
applyCR : for i in 0 to portcount - 1 generate