From 5ad7677b3a1a0622eef8f2d92bcae58ac7b96d8e Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Sun, 4 Dec 2016 18:00:31 +0100 Subject: [PATCH] flashrom: Added GETSTATUS command --- bench/bench_flashrom_controller.vhd | 24 ++++++++++++++--- cores/flashrom-wb/flashrom_controller.vhd | 32 ++++++++++++++++++++--- cores/flashrom-wb/flashrom_pkg.vhd | 1 + 3 files changed, 49 insertions(+), 8 deletions(-) diff --git a/bench/bench_flashrom_controller.vhd b/bench/bench_flashrom_controller.vhd index 8dff5c6..6feb2a4 100644 --- a/bench/bench_flashrom_controller.vhd +++ b/bench/bench_flashrom_controller.vhd @@ -37,7 +37,7 @@ architecture rtl of bench_flashrom_controller is signal sync_stb : std_logic; signal load_stb : std_logic; signal status_update_stb : std_logic; - signal status : std_logic_vector(31 downto 0); + signal status : std_logic_vector(7 downto 0); signal info : std_logic_vector(31 downto 0); signal data_in : std_logic_vector(7 downto 0); signal data_in_valid : std_logic; @@ -50,6 +50,7 @@ architecture rtl of bench_flashrom_controller is signal spi_cs_n : std_logic; signal spi_wp_n : std_logic; signal spi_busy : std_logic; + signal spi_clk_cnt : integer := 0; begin DataFlash_inst : entity work.DataFlash @@ -57,7 +58,7 @@ begin flashmemory => "devicemodels/memory.txt", Rapid_interface => true, fsck => 66, - DEVICE => "AT45DB011D", + DEVICE => "AT45DB011D", --AT45DB011D Tsck => 13.6 ns) port map( SI => spi_si, @@ -115,9 +116,24 @@ begin wait until (rising_edge(clk)); -- bench code here - - + wait until ready = '1'; + strobe(load_stb); + + wait until ready = '1'; + strobe(load_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); wait; end process bench; + spiclkcounter : process is + begin + wait until spi_sck = '1'; + spi_clk_cnt <= spi_clk_cnt + 1; + end process spiclkcounter; + end architecture rtl; diff --git a/cores/flashrom-wb/flashrom_controller.vhd b/cores/flashrom-wb/flashrom_controller.vhd index 1f1a79e..28e2b63 100644 --- a/cores/flashrom-wb/flashrom_controller.vhd +++ b/cores/flashrom-wb/flashrom_controller.vhd @@ -16,7 +16,7 @@ entity flashrom_controller is sync_stb : in std_logic; -- Synchronize current memory page with chip, only sampled when ready load_stb : in std_logic; -- Load page into local buffer, only sampled when ready status_update_stb : in std_logic; -- Update status vector - status : out std_logic_vector(31 downto 0); -- value of the status register (update using status_update_stb) + status : out std_logic_vector(7 downto 0); -- value of the status register (update using status_update_stb) info : out std_logic_vector(31 downto 0); -- value of the information register (updated on reset) -- Data IF @@ -40,7 +40,7 @@ architecture RTL of flashrom_controller is constant max_dummy_bits : integer := 16; constant bootup_delay : integer := 4000; - type state_t is (INIT, GETINFO, IDLE); + type state_t is (INIT, GETINFO, GETSTATUS, IDLE); signal state : state_t; signal spif_data_in_valid : std_logic; @@ -59,7 +59,7 @@ begin flashrom_spi_inst : entity work.flashrom_spi generic map( - clk_divider => 2, + clk_divider => 4, max_word_length => spif_max_word_length, max_dummy_bits => max_dummy_bits) port map( @@ -135,9 +135,33 @@ begin elsif spif_data_next = '1' then temp_cnt := temp_cnt + 1; end if; - when IDLE => null; + when IDLE => + temp_cnt := 0; + if status_update_stb = '1' then + state <= GETSTATUS; + end if; + if load_stb = '1' then --debug only + state <= GETINFO; + end if; + when GETSTATUS => + spif_data_in_length <= 8; -- Other bits after OpCode are don't care, so just repeat OPC + spif_data_out_length <= 8; + spif_data_out_dummy_bits <= 16; + spif_data_in_valid <= '1'; + spif_data_in <= FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS); + if spif_data_out_valid = '1' then + status <= spif_data_out(7 downto 0); + state <= IDLE; + end if; + if temp_cnt = 3 then + spif_data_in_valid <= '0'; + elsif spif_data_next = '1' then + temp_cnt := temp_cnt + 1; + end if; end case; end if; end if; end process flashrom_controller_p; + + ready <= '1' when state = IDLE else '0'; end architecture RTL; diff --git a/cores/flashrom-wb/flashrom_pkg.vhd b/cores/flashrom-wb/flashrom_pkg.vhd index e533c2e..9c215e5 100644 --- a/cores/flashrom-wb/flashrom_pkg.vhd +++ b/cores/flashrom-wb/flashrom_pkg.vhd @@ -5,6 +5,7 @@ use ieee.numeric_std.all; package flashrom_pkg is constant FLASHROM_ADDR_WIDTH : integer := 12; constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; + constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7"; function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector; end package flashrom_pkg;