flashrom: Added GETSTATUS command
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				@ -37,7 +37,7 @@ architecture rtl of bench_flashrom_controller is
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	signal sync_stb          : std_logic;
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	signal load_stb          : std_logic;
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	signal status_update_stb : std_logic;
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	signal status            : std_logic_vector(31 downto 0);
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	signal status            : std_logic_vector(7 downto 0);
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	signal info              : std_logic_vector(31 downto 0);
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	signal data_in           : std_logic_vector(7 downto 0);
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	signal data_in_valid     : std_logic;
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@ -50,6 +50,7 @@ architecture rtl of bench_flashrom_controller is
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	signal spi_cs_n          : std_logic;
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	signal spi_wp_n          : std_logic;
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	signal spi_busy          : std_logic;
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	signal spi_clk_cnt       : integer := 0;
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begin
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	DataFlash_inst : entity work.DataFlash
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@ -57,7 +58,7 @@ begin
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			flashmemory     => "devicemodels/memory.txt",
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			Rapid_interface => true,
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			fsck            => 66,
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			DEVICE          => "AT45DB011D",
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			DEVICE          => "AT45DB011D", --AT45DB011D
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			Tsck            => 13.6 ns)
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		port map(
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			SI     => spi_si,
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@ -115,9 +116,24 @@ begin
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		wait until (rising_edge(clk));
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		-- bench code here
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		wait until ready = '1';
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		strobe(load_stb);
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		wait until ready = '1';
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		strobe(load_stb);
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		wait until ready = '1';
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		strobe(status_update_stb);
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		wait until ready = '1';
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		strobe(status_update_stb);
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		wait;
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	end process bench;
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	spiclkcounter : process is
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	begin
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		wait until spi_sck = '1';
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		spi_clk_cnt <= spi_clk_cnt + 1;
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	end process spiclkcounter;
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end architecture rtl;
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@ -16,7 +16,7 @@ entity flashrom_controller is
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		sync_stb          : in  std_logic; -- Synchronize current memory page with chip, only sampled when ready
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		load_stb          : in  std_logic; -- Load page into local buffer, only sampled when ready
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		status_update_stb : in  std_logic; -- Update status vector
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		status            : out std_logic_vector(31 downto 0); -- value of the status register (update using status_update_stb) 
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		status            : out std_logic_vector(7 downto 0); -- value of the status register (update using status_update_stb) 
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		info              : out std_logic_vector(31 downto 0); -- value of the information register (updated on reset)
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		-- Data IF		
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@ -40,7 +40,7 @@ architecture RTL of flashrom_controller is
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	constant max_dummy_bits       : integer := 16;
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	constant bootup_delay         : integer := 4000;
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	type state_t is (INIT, GETINFO, IDLE);
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	type state_t is (INIT, GETINFO, GETSTATUS, IDLE);
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	signal state : state_t;
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	signal spif_data_in_valid   : std_logic;
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@ -59,7 +59,7 @@ begin
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	flashrom_spi_inst : entity work.flashrom_spi
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		generic map(
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			clk_divider     => 2,
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			clk_divider     => 4,
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			max_word_length => spif_max_word_length,
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			max_dummy_bits  => max_dummy_bits)
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		port map(
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@ -135,9 +135,33 @@ begin
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						elsif spif_data_next = '1' then
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							temp_cnt := temp_cnt + 1;
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						end if;
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					when IDLE => null;
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					when IDLE =>
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						temp_cnt := 0;
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						if status_update_stb = '1' then
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							state    <= GETSTATUS;
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						end if;
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						if load_stb = '1' then --debug only
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							state  <= GETINFO;
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							end if;
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					when GETSTATUS =>
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						spif_data_in_length      <= 8; -- Other bits after OpCode are don't care, so just repeat OPC
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						spif_data_out_length     <= 8;
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						spif_data_out_dummy_bits <= 16;
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						spif_data_in_valid       <= '1';
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						spif_data_in             <= FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS);
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						if spif_data_out_valid = '1' then
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							status <= spif_data_out(7 downto 0);
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							state  <= IDLE;
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						end if;
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						if temp_cnt = 3 then
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							spif_data_in_valid <= '0';
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						elsif spif_data_next = '1' then
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							temp_cnt := temp_cnt + 1;
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						end if;
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				end case;
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			end if;
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		end if;
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	end process flashrom_controller_p;
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	ready <= '1' when state = IDLE else '0';
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end architecture RTL;
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@ -5,6 +5,7 @@ use ieee.numeric_std.all;
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package flashrom_pkg is
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	constant FLASHROM_ADDR_WIDTH              : integer                      := 12;
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	constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F";
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	constant FLASHROM_COMMAND_GET_STATUS      : std_logic_vector(7 downto 0) := x"D7";
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	function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector;
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end package flashrom_pkg;
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