From 76e62176426bb676c7d4a4eea47a9ddae9545612 Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Thu, 2 Mar 2017 08:51:53 +0100 Subject: [PATCH] Added prelim. GPIO --- bench/bench_gpio.vhd | 87 ++++++++++++++++++++++++++++++++++++ cores/gpio/gpio.vhd | 74 ++++++++++++++++++++++++++++++ design/top.vhd | 21 +++++++-- quartus/mor1kx-bemicrocv.qsf | 4 +- 4 files changed, 181 insertions(+), 5 deletions(-) create mode 100644 bench/bench_gpio.vhd create mode 100644 cores/gpio/gpio.vhd diff --git a/bench/bench_gpio.vhd b/bench/bench_gpio.vhd new file mode 100644 index 0000000..ddc3b07 --- /dev/null +++ b/bench/bench_gpio.vhd @@ -0,0 +1,87 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library design; +use design.all; + +library ip; +use ip.wishbone_package.all; + +entity bench_gpio is +end entity bench_gpio; + +architecture RTL of bench_gpio is + signal clk : std_logic; + signal rst : std_logic; + signal clr : std_logic; + signal wb_in : wishbone_v3_slave_in; + signal wb_out : wishbone_v3_slave_out; + signal gpio : std_logic_vector(31 downto 0); + +begin + gpio_inst : entity design.gpio + port map( + clk => clk, + rst => rst, + clr => clr, + wb_in => wb_in, + wb_out => wb_out, + gpio => gpio + ); + + clock_driver : process + constant period : time := 10 ns; + begin + clk <= '0'; + wait for period / 2; + clk <= '1'; + wait for period / 2; + end process clock_driver; + + test : process is + begin + rst <= '1'; + clr <= '0'; + wb_in.STB <= '0'; + wb_in.CYC <= '0'; + wb_in.ADR <= (others => '0'); + wb_in.DAT <= (others => '0'); + wb_in.SEL <= (others => '1'); + wb_in.WE <= '0'; + + wait for 20 ns; + wait until rising_edge(clk); + rst <= '0'; + wait until rising_edge(clk); + + wb_in.DAT <= x"0000ffff"; + wb_in.WE <= '1'; + wb_in.STB <= '1'; + wb_in.CYC <= '1'; + wait until rising_edge(clk); + wb_in.WE <= '0'; + wb_in.STB <= '0'; + wb_in.CYC <= '0'; + + wait until rising_edge(clk); + wb_in.WE <= '1'; + wb_in.STB <= '1'; + wb_in.CYC <= '1'; + wb_in.ADR <= x"00000004"; + wb_in.DAT <= x"12345678"; + + wait until rising_edge(clk); + wb_in.WE <= '0'; + wb_in.STB <= '0'; + wb_in.CYC <= '0'; + + wait until rising_edge(clk); + wb_in.ADR <= x"00000008"; + + wait; + end process test; + + gpio(31 downto 28) <= (others => '1'); + +end architecture RTL; diff --git a/cores/gpio/gpio.vhd b/cores/gpio/gpio.vhd new file mode 100644 index 0000000..1edab07 --- /dev/null +++ b/cores/gpio/gpio.vhd @@ -0,0 +1,74 @@ +-- TODO: This is only a placeholder for a "real" GPIO core. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ip; +use ip.wishbone_package.all; + +entity gpio is + port( + clk : in std_logic; + rst : in std_logic; + clr : in std_logic; + -- Wishbone + wb_in : in wishbone_v3_slave_in; + wb_out : out wishbone_v3_slave_out; + -- Ports + gpio : inout std_logic_vector(31 downto 0) + ); +end entity gpio; + +architecture RTL of gpio is + signal reg_port : std_logic_vector(31 downto 0); + signal reg_ddr : std_logic_vector(31 downto 0); +begin + gpio_p : process(clk, rst) is + procedure default_state is + begin + null; + end procedure default_state; + + procedure reset_state is + begin + default_state; + reg_ddr <= (others => '0'); + reg_port <= (others => '0'); + end procedure reset_state; + begin + if rst = '1' then + reset_state; + elsif rising_edge(clk) then + default_state; + if clr = '1' then + reset_state; + else + if (wb_in.STB = '1' and wb_in.CYC = '1' and wb_in.WE = '1') then + for i in 0 to 3 loop + if (wb_in.SEL(i) = '1') then + case wb_in.ADR(3 downto 2) is + when "00" => reg_ddr((i + 1) * 8 - 1 downto i * 8) <= wb_in.DAT((i + 1) * 8 - 1 downto i * 8); + when "01" => reg_port((i + 1) * 8 - 1 downto i * 8) <= wb_in.DAT((i + 1) * 8 - 1 downto i * 8); + when others => null; + end case; + end if; + end loop; + end if; + end if; + end if; + end process gpio_p; + + wb_out.ERR <= '0'; + wb_out.RTY <= '0'; + wb_out.ACK <= (wb_in.STB and wb_in.CYC); + + read : with wb_in.ADR(3 downto 2) select wb_out.DAT <= + reg_ddr when "00", + reg_port when "01", + gpio when others; + + writeport : for i in 0 to 31 generate + gpio(i) <= reg_port(i) when reg_ddr(i) = '1' else 'Z'; + end generate writeport; +end architecture RTL; diff --git a/design/top.vhd b/design/top.vhd index 257053c..2ec68f3 100644 --- a/design/top.vhd +++ b/design/top.vhd @@ -59,11 +59,11 @@ architecture RTL of top is -- WB config constant masters : natural := 3; - constant slaves : natural := 3; + constant slaves : natural := 4; constant INTERCON_ID_SRAM : natural := 0; constant INTERCON_ID_DDR3 : natural := 1; constant INTERCON_ID_FLASH : natural := 2; - -- constant INTERCON_ID_GPIO : natural := 2; + constant INTERCON_ID_GPIO : natural := 3; -- constant INTERCON_ID_UART : natural := 3; -- constant INTERCON_ID_NS16550 : natural := 4; @@ -322,6 +322,17 @@ begin spi_wp_n => flash_wp_n ); + -- GPIO + gpio_inst : entity work.gpio + port map( + clk => clk, + rst => rst, + clr => '0', + wb_in => intercon_slave_i(INTERCON_ID_GPIO), + wb_out => intercon_slave_o(INTERCON_ID_GPIO), + gpio => GPIOA + ); + -- Intercon crossbar_inst : entity ip.crossbar generic map( @@ -339,12 +350,14 @@ begin address => ( INTERCON_ID_SRAM => x"00000000", INTERCON_ID_DDR3 => x"10000000", - INTERCON_ID_FLASH => x"90000000" + INTERCON_ID_FLASH => x"40000000", + INTERCON_ID_GPIO => x"80000000" ), mask => ( INTERCON_ID_SRAM => x"ffff0000", INTERCON_ID_DDR3 => x"f0000000", - INTERCON_ID_FLASH => x"f0000000" + INTERCON_ID_FLASH => x"f0000000", + INTERCON_ID_GPIO => x"fffffffc" ) ); end architecture RTL; diff --git a/quartus/mor1kx-bemicrocv.qsf b/quartus/mor1kx-bemicrocv.qsf index 1dca8cc..f304b30 100644 --- a/quartus/mor1kx-bemicrocv.qsf +++ b/quartus/mor1kx-bemicrocv.qsf @@ -323,7 +323,8 @@ set_location_assignment PIN_N16 -to flash_sck set_location_assignment PIN_M16 -to flash_si set_location_assignment PIN_M18 -to flash_so set_location_assignment PIN_N19 -to flash_wp_n -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_global_assignment -name VHDL_FILE ../cores/gpio/gpio.vhd set_global_assignment -name VHDL_FILE ../cores/generic/fancy_spi_master.vhd set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_wb.vhd" set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_pkg.vhd" @@ -381,3 +382,4 @@ set_global_assignment -name VHDL_FILE ../design/top.vhd set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/wishbone_package.vhd -library ip set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/crossbar_v3.vhd -library ip set_global_assignment -name QIP_FILE ../ip/altera/ddr3.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file