From 9ff74212428e334fa14fc0f15ca8e271e97b1947 Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Sun, 4 Dec 2016 18:27:58 +0100 Subject: [PATCH] flashrom: Cleanup --- bench/bench_flashrom_controller.vhd | 12 +++-- cores/flashrom-wb/flashrom_controller.vhd | 66 ++++++++++++----------- 2 files changed, 44 insertions(+), 34 deletions(-) diff --git a/bench/bench_flashrom_controller.vhd b/bench/bench_flashrom_controller.vhd index 6feb2a4..0cae27c 100644 --- a/bench/bench_flashrom_controller.vhd +++ b/bench/bench_flashrom_controller.vhd @@ -118,15 +118,21 @@ begin -- bench code here wait until ready = '1'; strobe(load_stb); - + wait until ready = '1'; strobe(load_stb); - + wait until ready = '1'; strobe(status_update_stb); - + wait until ready = '1'; strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(load_stb); wait; end process bench; diff --git a/cores/flashrom-wb/flashrom_controller.vhd b/cores/flashrom-wb/flashrom_controller.vhd index 28e2b63..a4d265a 100644 --- a/cores/flashrom-wb/flashrom_controller.vhd +++ b/cores/flashrom-wb/flashrom_controller.vhd @@ -82,11 +82,13 @@ begin flashrom_controller_p : process(clk, rst) is variable temp_cnt : integer range 0 to bootup_delay; + variable done : boolean; procedure default_state is begin spi_reset_n <= '1'; spif_data_in_valid <= '0'; + done := false; end procedure default_state; procedure reset_state is @@ -103,6 +105,29 @@ begin temp_cnt := 0; end procedure reset_state; + + procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector(31 downto 0)) is + begin + spif_data_in_length <= data_in_length; + spif_data_out_length <= data_out_length; + spif_data_out_dummy_bits <= data_out_dummy_bits; + spif_data_in_valid <= '1'; + spif_data_in <= data_in; + + if temp_cnt = nTxWords then + spif_data_in_valid <= '0'; + elsif spif_data_next = '1' then + temp_cnt := temp_cnt + 1; + end if; + + if spif_data_out_valid = '1' then + spif_data_in_valid <= '0'; + done := true; + state <= IDLE; + temp_cnt := 0; + end if; + end procedure run_command_single; + begin if rst = '1' then reset_state; @@ -120,48 +145,27 @@ begin else temp_cnt := temp_cnt + 1; end if; - when GETINFO => - spif_data_in_length <= 8; -- Other bits after OpCode are don't care, so just repeat OPC - spif_data_out_length <= 32; - spif_data_out_dummy_bits <= 8; - spif_data_in_valid <= '1'; - spif_data_in <= FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID); - if spif_data_out_valid = '1' then - info <= spif_data_out; - state <= IDLE; - end if; - if temp_cnt = 5 then - spif_data_in_valid <= '0'; - elsif spif_data_next = '1' then - temp_cnt := temp_cnt + 1; + when GETINFO => -- TODO: In simulation I can only call this command once?! + run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID)); + if done then + info <= spif_data_out; end if; when IDLE => temp_cnt := 0; if status_update_stb = '1' then - state <= GETSTATUS; + state <= GETSTATUS; end if; if load_stb = '1' then --debug only - state <= GETINFO; - end if; - when GETSTATUS => - spif_data_in_length <= 8; -- Other bits after OpCode are don't care, so just repeat OPC - spif_data_out_length <= 8; - spif_data_out_dummy_bits <= 16; - spif_data_in_valid <= '1'; - spif_data_in <= FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS); - if spif_data_out_valid = '1' then - status <= spif_data_out(7 downto 0); - state <= IDLE; + state <= GETINFO; end if; - if temp_cnt = 3 then - spif_data_in_valid <= '0'; - elsif spif_data_next = '1' then - temp_cnt := temp_cnt + 1; + when GETSTATUS => + run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS)); + if done then + status <= spif_data_out(7 downto 0); end if; end case; end if; end if; end process flashrom_controller_p; - ready <= '1' when state = IDLE else '0'; end architecture RTL;