commit a1efcf62c4f93322009e4a8e0c8a14ae77735a56 Author: Markus Koch Date: Thu Aug 4 19:22:38 2016 +0200 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..6b8a9b3 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +*.wlf +wlf* +*.vstf +transcript + diff --git a/.library_mapping.xml b/.library_mapping.xml new file mode 100644 index 0000000..db5835c --- /dev/null +++ b/.library_mapping.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.project b/.project new file mode 100644 index 0000000..a41a011 --- /dev/null +++ b/.project @@ -0,0 +1,45 @@ + + + mor1kx-bemicrocv + + + + + + org.eclipse.xtext.ui.shared.xtextBuilder + + + + + + com.sigasi.hdt.vhdl.ui.vhdlNature + org.eclipse.xtext.ui.shared.xtextNature + + + + Common Libraries + 2 + virtual:/virtual + + + Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt + 1 + sigasiresource:/vhdl/readme2.txt + + + Common Libraries/IEEE + 2 + sigasiresource:/vhdl/93/IEEE + + + Common Libraries/STD + 2 + sigasiresource:/vhdl/93/STD + + + Common Libraries/IEEE/Synopsys + 2 + sigasiresource:/vhdl/93/IEEE%20Synopsys + + + diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..ebe7c61 --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +encoding//Common\ Libraries/IEEE=utf-8 +encoding//Common\ Libraries/IEEE/Synopsys=utf-8 +encoding//Common\ Libraries/STD=utf-8 +encoding/Common\ Libraries=utf-8 diff --git a/bench/OLDbench_flashrom_spi.vhd.old b/bench/OLDbench_flashrom_spi.vhd.old new file mode 100644 index 0000000..3dabb4e --- /dev/null +++ b/bench/OLDbench_flashrom_spi.vhd.old @@ -0,0 +1,92 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity bench_flashrom_spi is +end entity bench_flashrom_spi; + +library design; +use design.all; + +architecture RTL of bench_flashrom_spi is + signal clk : std_logic; + signal spi_clk : std_logic; + signal rst : std_logic; + signal spi_si : std_logic; + signal spi_so : std_logic; + signal spi_sck : std_logic; + signal spi_reset_n : std_logic; + signal spi_cs_n : std_logic; + signal spi_wp_n : std_logic; + signal toSpiDataIn : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal toSpiWrite : STD_LOGIC; + signal toSpiFull : STD_LOGIC; + signal fromSpiDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal fromSpiRead : STD_LOGIC; + signal fromSpiEmpty : STD_LOGIC; + + procedure waitclk is + begin + wait until rising_edge(clk); + end procedure waitclk; + + procedure strobe(signal s : out std_logic) is + begin + s <= '1'; + waitclk; + s <= '0'; + waitclk; + end procedure strobe; + +begin + flashrom_spi_inst : entity design.flashrom_spi + port map( + spi_clk => spi_clk, + clk => clk, + rst => rst, + spi_si => spi_si, + spi_so => spi_so, + spi_sck => spi_sck, + spi_reset_n => spi_reset_n, + spi_cs_n => spi_cs_n, + spi_wp_n => spi_wp_n, + toSpiDataIn => toSpiDataIn, + toSpiWrite => toSpiWrite, + toSpiFull => toSpiFull, + fromSpiDataOut => fromSpiDataOut, + fromSpiRead => fromSpiRead, + fromSpiEmpty => fromSpiEmpty + ); + + clock_driver : process + constant period : time := 10 ns; + begin + clk <= '0'; + wait for period / 2; + clk <= '1'; + wait for period / 2; + end process clock_driver; + spi_clk <= clk; + + test : process is + begin + spi_so <= '0'; + rst <= '1'; + toSpiDataIn <= (others => '0'); + toSpiWrite <= '0'; + fromSpiRead <= '0'; + + wait for 40 ns; + + rst <= '0'; + wait for 20 ns; + toSpiDataIn <= x"55"; + strobe(toSpiWrite); + waitclk; + toSpiDataIn <= x"AA"; + strobe(toSpiWrite); + + wait; + end process test; + +end architecture RTL; diff --git a/bench/bench_flashrom_controller.vhd b/bench/bench_flashrom_controller.vhd new file mode 100644 index 0000000..587ebf7 --- /dev/null +++ b/bench/bench_flashrom_controller.vhd @@ -0,0 +1,199 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library design; +use design.all; +use design.flashrom_pkg.all; + +entity bench_flashrom_controller is +end entity bench_flashrom_controller; + +architecture rtl of bench_flashrom_controller is + signal clk : std_logic; + signal rst : std_logic; + + procedure waitclk is + begin + wait until rising_edge(clk); + end procedure waitclk; + procedure waitnclk(n : integer) is + begin + for i in 1 to n loop + wait until rising_edge(clk); + end loop; + end procedure waitnclk; + procedure strobe(signal s : out std_logic) is + begin + s <= '1'; + waitclk; + s <= '0'; + waitclk; + end procedure strobe; + signal clr : std_logic; + signal ready : std_logic; + signal page : std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0); + signal sync_stb : std_logic; + signal load_stb : std_logic; + signal status_update_stb : std_logic; + signal status : std_logic_vector(31 downto 0); + signal info : std_logic_vector(31 downto 0); + signal data_in : std_logic_vector(7 downto 0); + signal data_in_valid : std_logic; + signal data_out : std_logic_vector(7 downto 0); + signal data_out_valid : std_logic; + signal spi_si : std_logic; + signal spi_so : std_logic; + signal spi_sck : std_logic; + signal spi_reset_n : std_logic; + signal spi_cs_n : std_logic; + signal spi_wp_n : std_logic; + +begin + flashrom_controller_inst : entity design.flashrom_controller + port map( + clk => clk, + rst => rst, + clr => clr, + ready => ready, + page => page, + sync_stb => sync_stb, + load_stb => load_stb, + status_update_stb => status_update_stb, + status => status, + info => info, + data_in => data_in, + data_in_valid => data_in_valid, + data_out => data_out, + data_out_valid => data_out_valid, + spi_si => spi_si, + spi_so => spi_so, + spi_sck => spi_sck, + spi_reset_n => spi_reset_n, + spi_cs_n => spi_cs_n, + spi_wp_n => spi_wp_n + ); + + -- clock driver + clock_driver : process + constant PERIOD : time := 10 ns; + begin + clk <= '0'; + wait for PERIOD / 2; + clk <= '1'; + wait for PERIOD / 2; + end process clock_driver; + + --testbench + bench : process is + begin + rst <= '1'; + clr <= '0'; + wait for 10 ns * 2; + wait until (rising_edge(clk)); + rst <= '0'; + wait for 10 ns * 2; + wait until (rising_edge(clk)); + + -- bench code here + + + wait; + end process bench; + + + + -- debugging only! + spi_so_p : process is + procedure spitx(constant value : std_logic) is + begin + spi_so <= value; + wait until rising_edge(spi_sck); + end procedure spitx; + begin + spi_so <= '0'; + wait until rising_edge(spi_sck); + wait until rising_edge(spi_sck); + + + -- 0x0 (dummy) + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + -- INFO FOO: 0x1F + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('1'); + spitx('1'); + spitx('1'); + spitx('1'); + -- + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('1'); + spitx('1'); + -- + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + -- + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + + + + + -- 0x88 + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + -- 0x44 + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + -- 0x22 + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + + wait; + end process spi_so_p; +end architecture rtl; diff --git a/bench/bench_flashrom_spi.vhd b/bench/bench_flashrom_spi.vhd new file mode 100644 index 0000000..065636f --- /dev/null +++ b/bench/bench_flashrom_spi.vhd @@ -0,0 +1,205 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library design; +use design.all; + +entity bench_flashrom_spi is +end entity bench_flashrom_spi; + +architecture rtl of bench_flashrom_spi is + signal clk : std_logic; + signal rst : std_logic; + + procedure waitclk is + begin + wait until rising_edge(clk); + end procedure waitclk; + procedure waitnclk(n : integer) is + begin + for i in 1 to n loop + wait until rising_edge(clk); + end loop; + end procedure waitnclk; + procedure strobe(signal s : out std_logic) is + begin + s <= '1'; + waitclk; + s <= '0'; + waitclk; + end procedure strobe; + + constant max_word_length : integer := 16; + constant max_dummy_bits : integer := 16; + + signal clr : std_logic; + signal spi_si : std_logic; + signal spi_so : std_logic := '0'; + signal spi_sck : std_logic; + signal spi_cs_n : std_logic; + signal data_in_valid : std_logic; + signal data_in : std_logic_vector(max_word_length - 1 downto 0); + signal data_next : std_logic; + signal data_out : std_logic_vector(max_word_length - 1 downto 0); + signal data_out_valid : std_logic; + signal data_in_length : integer range 0 to max_word_length; + signal data_out_length : integer range 0 to max_word_length; + signal data_out_dummy_bits : integer range 0 to max_dummy_bits; + signal transmission_active : std_logic; + +begin + flashrom_spi_inst : entity design.flashrom_spi + generic map( + clk_divider => 4, + max_word_length => max_word_length, + max_dummy_bits => max_dummy_bits) + port map( + data_out_dummy_bits => data_out_dummy_bits, + data_out_length => data_out_length, + clk => clk, + rst => rst, + clr => clr, + spi_si => spi_si, + spi_so => spi_so, + spi_sck => spi_sck, + spi_cs_n => spi_cs_n, + data_in_valid => data_in_valid, + data_in => data_in, + data_next => data_next, + data_out => data_out, + data_out_valid => data_out_valid, + data_in_length => data_in_length, + transmission_active => transmission_active + ); + + -- clock driver + clock_driver : process + constant PERIOD : time := 10 ns; + begin + clk <= '0'; + wait for PERIOD / 2; + clk <= '1'; + wait for PERIOD / 2; + end process clock_driver; + + --testbench + bench : process is + begin + rst <= '1'; + data_in <= x"0000"; + data_in_valid <= '0'; + wait for 10 ns * 2; + wait until (rising_edge(clk)); + rst <= '0'; + wait for 10 ns * 2; + wait until (rising_edge(clk)); + + -- bench code here + data_out_dummy_bits <= 0; + + data_in_length <= 8; + data_out_length <= 8; + data_in <= x"FF00"; + data_in_valid <= '1'; + wait until data_next = '1'; + + data_in_length <= 16; + data_out_length <= 16; + data_in <= x"0055"; + data_in_valid <= '1'; + wait until data_next = '1'; + + data_in_valid <= '0'; + wait until transmission_active = '0'; + waitnclk(10); -- new SPI transaction + + data_out_dummy_bits <= 16; + data_in_length <= 16; + data_out_length <= 16; + data_in <= x"0055"; + data_in_valid <= '1'; + wait until data_next = '1'; + wait until data_next = '1'; -- 32 bits total + + data_in_valid <= '0'; + + wait; + end process bench; + + spi_so_p : process is + procedure spitx(constant value : std_logic) is + begin + spi_so <= value; + wait until rising_edge(spi_sck); + end procedure spitx; + begin + spi_so <= '0'; + wait until rising_edge(spi_sck); + wait until rising_edge(spi_sck); + + -- 8 bit word + spitx('1'); + for i in 1 to 7 loop + spitx('0'); + end loop; + + -- 8 bit word + spitx('0'); + spitx('1'); + for i in 1 to 6 loop + spitx('0'); + end loop; + + -- 8 bit word + spitx('0'); + spitx('0'); + spitx('1'); + for i in 1 to 5 loop + spitx('0'); + end loop; + + wait until rising_edge(spi_sck); + + -- 0x80 (dummy) + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('0'); + -- 0x88 + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + -- 0x44 + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + -- 0x22 + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + spitx('0'); + spitx('0'); + spitx('1'); + spitx('0'); + + wait; + end process spi_so_p; + +end architecture rtl; diff --git a/bench/bench_sram_wb.vhd b/bench/bench_sram_wb.vhd new file mode 100644 index 0000000..7988c59 --- /dev/null +++ b/bench/bench_sram_wb.vhd @@ -0,0 +1,119 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library design; +use design.all; + +library ip; +use ip.all; +use ip.wishbone_package.all; + +entity bench_sram_wb is +end entity bench_sram_wb; + +architecture RTL of bench_sram_wb is + signal clk : std_logic; + signal rst : std_logic; + signal wb_in : wishbone_v3_slave_in; + signal wb_out : wishbone_v3_slave_out; + +begin + sram_wb_inst : entity design.sram_wb + port map( + clk => clk, + rst => rst, + wb_in => wb_in, + wb_out => wb_out + ); + + clock_driver : process + constant period : time := 10 ns; + begin + clk <= '0'; + wait for period / 2; + clk <= '1'; + wait for period / 2; + end process clock_driver; + + wb_in.CYC <= wb_in.STB; + test : process is + begin + rst <= '1'; + wb_in.DAT <= (others => '0'); + wb_in.STB <= '0'; + wb_in.SEL <= "1111"; + wb_in.WE <= '0'; + wb_in.ADR <= (others => '0'); + wait for 20 ns; + + wait until rising_edge(clk); + rst <= '0'; + + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- wb_in.DAT <= x"12345678"; + -- wb_in.WE <= '1'; + -- wb_in.STB <= '1'; + -- wait until rising_edge(clk); + -- --wait until rising_edge(wb_out.ACK); + -- wb_in.STB <= '0'; + -- wait until rising_edge(clk); + -- wb_in.ADR <= x"00000004"; + -- wb_in.DAT <= x"AABBCCDD"; + -- wb_in.WE <= '1'; + -- wb_in.STB <= '1'; + -- wait until rising_edge(clk); + -- --wait until rising_edge(wb_out.ACK); + -- wb_in.STB <= '0'; + -- wait until rising_edge(clk); + -- wb_in.ADR <= x"00000004"; + -- wb_in.DAT <= x"FF111111"; + -- wb_in.SEL <= "1000"; + -- wb_in.WE <= '1'; + -- wb_in.STB <= '1'; + -- wait until rising_edge(clk); + -- --wait until rising_edge(wb_out.ACK); + -- wb_in.STB <= '0'; + -- wb_in.SEL <= "1111"; + -- wait until rising_edge(clk); + -- + -- wait until rising_edge(clk); + -- wait until rising_edge(clk); + -- wait until rising_edge(clk); + -- wb_in.ADR <= x"00000000"; + -- wb_in.DAT <= x"FFFFFFFF"; + -- wb_in.WE <= '0'; + -- wb_in.STB <= '1'; + -- wait until rising_edge(clk); + -- wait until rising_edge(wb_out.ACK); + -- wait until rising_edge(clk); + -- wb_in.STB <= '0'; + + -- wait until rising_edge(clk); + -- wb_in.DAT <= x"FFFFFFFF"; + -- wb_in.ADR <= x"00000004"; + -- wb_in.WE <= '0'; + -- wb_in.STB <= '1'; + -- wait until rising_edge(clk); + -- wait until rising_edge(wb_out.ACK); + -- wait until rising_edge(clk); + -- wb_in.STB <= '0'; + + for i in 0 to 1000 loop + wait until rising_edge(clk); + wb_in.ADR <= std_logic_vector(to_unsigned(i, 30) & "00"); + wb_in.WE <= '0'; + wb_in.STB <= '1'; + wait until rising_edge(clk); + wait until rising_edge(wb_out.ACK); + wait until rising_edge(clk); + wb_in.STB <= '0'; + end loop; + + wait; + end process test; + +end architecture RTL; diff --git a/bench/bench_top.vhd b/bench/bench_top.vhd new file mode 100644 index 0000000..2238fa1 --- /dev/null +++ b/bench/bench_top.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library design; +use design.all; + +library ip; +use ip.wishbone_package.all; + +entity bench_top is +end entity bench_top; + +architecture RTL of bench_top is + signal clk_hw : std_logic; + signal rst_hw : std_logic; + signal GPIOA : std_logic_vector(wishbone_data_width - 1 downto 0); + signal jinn_uart_rx : std_logic; + signal jinn_uart_tx : std_logic; + signal uart_rx : std_logic; + signal uart_tx : std_logic; + -- DDR3 + signal mem_a : std_logic_vector(12 downto 0); + signal mem_ba : std_logic_vector(2 downto 0); + signal mem_ck : std_logic_vector(0 downto 0); + signal mem_ck_n : std_logic_vector(0 downto 0); + signal mem_cke : std_logic_vector(0 downto 0); + signal mem_cs_n : std_logic_vector(0 downto 0); + signal mem_dm : std_logic_vector(1 downto 0); + signal mem_ras_n : std_logic_vector(0 downto 0); + signal mem_cas_n : std_logic_vector(0 downto 0); + signal mem_we_n : std_logic_vector(0 downto 0); + signal mem_reset_n : std_logic; + signal mem_dq : std_logic_vector(15 downto 0); + signal mem_dqs : std_logic_vector(1 downto 0); + signal mem_dqs_n : std_logic_vector(1 downto 0); + signal mem_odt : std_logic_vector(0 downto 0); + signal oct_rzqin : std_logic; +begin + top_inst : entity design.top + port map( + clk_hw => clk_hw, + rst_hw => rst_hw, + GPIOA => GPIOA, + jinn_uart_rx => jinn_uart_rx, + jinn_uart_tx => jinn_uart_tx, + uart_rx => uart_rx, + uart_tx => uart_tx, + mem_a => mem_a, + mem_ba => mem_ba, + mem_ck => mem_ck, + mem_ck_n => mem_ck_n, + mem_cke => mem_cke, + mem_cs_n => mem_cs_n, + mem_dm => mem_dm, + mem_ras_n => mem_ras_n, + mem_cas_n => mem_cas_n, + mem_we_n => mem_we_n, + mem_reset_n => mem_reset_n, + mem_dq => mem_dq, + mem_dqs => mem_dqs, + mem_dqs_n => mem_dqs_n, + mem_odt => mem_odt, + oct_rzqin => oct_rzqin + ); + + clock_driver : process + constant period : time := 10 ns; + begin + clk_hw <= '0'; + wait for period / 2; + clk_hw <= '1'; + wait for period / 2; + end process clock_driver; + + test : process is + begin + rst_hw <= '0'; + wait for 50 ns; + rst_hw <= '1'; + wait; + end process test; + +end architecture RTL; diff --git a/compile.do b/compile.do new file mode 100644 index 0000000..b0304db --- /dev/null +++ b/compile.do @@ -0,0 +1,39 @@ +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_branch_prediction.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_espresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_espresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_simple_dpram_sclk.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_avalon.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_prontoespresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_prontoespresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-sprs.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_wb32.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dcache.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_store_buffer.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cache_lru.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode_execute_cappuccino.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_icache.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ticktimer.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cfgrs.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_immu.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_true_dpram_sclk.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_cappuccino.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-defines.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_cappuccino.v +vlog -sv -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_utils.vh +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_espresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dmmu.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_espresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_prontoespresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_alu.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_pic.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_cappuccino.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_cappuccino.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_cappuccino.v +vlog -work mor1kx ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_espresso.v \ No newline at end of file diff --git a/cores/OLDflashrom-wb/flashrom-spi.vhd b/cores/OLDflashrom-wb/flashrom-spi.vhd new file mode 100644 index 0000000..d582db8 --- /dev/null +++ b/cores/OLDflashrom-wb/flashrom-spi.vhd @@ -0,0 +1,168 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ip; +use ip.all; + +entity flashrom_spi is + port( + clk : in std_logic; + spi_clk : in std_logic; + rst : in std_logic; + + -- SPI flash hardware signals + spi_si : out std_logic; -- SPI serial in + spi_so : in std_logic; -- SPI serial out + spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module + spi_reset_n : out std_logic; -- SPI hard reset + spi_cs_n : out std_logic; -- SPI chip select + spi_wp_n : out std_logic; -- SPI write protect + + -- FPGA -> ROM + toSpiDataIn : in STD_LOGIC_VECTOR(7 DOWNTO 0); + toSpiWrite : in STD_LOGIC; + toSpiFull : out STD_LOGIC; + + -- ROM -> FPGA + fromSpiDataOut : out STD_LOGIC_VECTOR(7 DOWNTO 0); + fromSpiRead : in STD_LOGIC; + fromSpiEmpty : out STD_LOGIC + ); +end entity flashrom_spi; + +architecture RTL of flashrom_spi is + signal spi_rst : std_logic; + + signal toSpiRead : STD_LOGIC; + signal toSpiDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal toSpiEmpty : STD_LOGIC; + signal fromSpiDataIn : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal fromSpiWrite : STD_LOGIC; + signal fromSpiFull : STD_LOGIC; + + signal outshifter_cnt : unsigned(2 downto 0); + signal outshifter_data : std_logic_vector(7 downto 0); + signal inshifter_cnt : unsigned(2 downto 0); + signal inshifter_data : std_logic_vector(7 downto 0); + signal spi_cs_n_del : std_logic; +begin + spi_sck <= spi_clk; + + resetSync : process(rst, spi_clk) is + variable cnt : integer range 0 to 1; + begin + if rst = '1' then + cnt := 1; + spi_rst <= '1'; + elsif rising_edge(spi_clk) then + spi_rst <= '1'; + if cnt = 0 then + spi_rst <= '0'; + else + cnt := cnt - 1; + end if; + end if; + end process resetSync; + + -- FPGA -> ROM + shifter : process(spi_clk, rst) is + variable loaded : std_logic; + begin + if rst = '1' then + outshifter_data <= (others => '0'); + outshifter_cnt <= (others => '1'); + spi_cs_n <= '1'; + toSpiRead <= '0'; + loaded := '0'; + elsif rising_edge(spi_clk) then -- provide data on falling edge + toSpiRead <= '0'; + if outshifter_cnt = "101" then + if toSpiEmpty = '0' then + toSpiRead <= '1'; + loaded := '1'; + end if; + end if; + if outshifter_cnt = "111" then + if loaded = '1' then + loaded := '0'; + outshifter_data <= toSpiDataOut; + spi_cs_n <= '0'; + outshifter_cnt <= "000"; + else + spi_cs_n <= '1'; + --shifter_cnt <= "000"; + if toSpiEmpty = '0' then + outshifter_cnt <= "101"; + end if; + end if; + else + outshifter_cnt <= outshifter_cnt + 1; + outshifter_data <= outshifter_data(6 downto 0) & '0'; + end if; + end if; + end process shifter; + spi_si <= outshifter_data(7); + + spiFifo_wb2spi_inst : entity ip.spiFifo + port map( + aclr => rst, + data => toSpiDataIn, + rdclk => spi_clk, + rdreq => toSpiRead, + wrclk => clk, + wrreq => toSpiWrite, + q => toSpiDataOut, + rdempty => toSpiEmpty, + wrfull => toSpiFull + ); + + errorHandler_wb : process(clk, rst) is + begin + if rst = '1' then + elsif rising_edge(clk) then + if toSpiWrite = '1' and toSpiFull = '1' then + -- TODO: ERROR: Fifo full! + report "ERROR: SPI transmit FIFO full!" severity failure; + end if; + end if; + end process errorHandler_wb; + + -- ROM -> FPGA + shifter_in : process(spi_clk, rst) is + begin + if rst = '1' then + inshifter_data <= (others => '0'); + inshifter_cnt <= (others => '0'); + fromSpiWrite <= '0'; + spi_cs_n_del <= '1'; + elsif rising_edge(spi_clk) then -- sample on rising edge + spi_cs_n_del <= spi_cs_n; + fromSpiWrite <= '0'; + if spi_cs_n = '0' then + inshifter_cnt <= inshifter_cnt + 1; + inshifter_data <= inshifter_data(6 downto 0) & spi_so; + if inshifter_cnt = "111" then + fromSpiWrite <= '1'; + end if; + else + inshifter_data <= (others => '0'); + inshifter_cnt <= (others => '0'); + end if; + end if; + end process shifter_in; + + spiFifo_spi2wb_inst : entity ip.spiFifo + port map( + aclr => rst, + data => fromSpiDataIn, + rdclk => clk, + rdreq => fromSpiRead, + wrclk => spi_clk, + wrreq => fromSpiWrite, + q => fromSpiDataOut, + rdempty => fromSpiEmpty, + wrfull => fromSpiFull + ); + fromSpiDataIn <= inshifter_data; +end architecture RTL; diff --git a/cores/flashrom-wb/flashrom_controller.vhd b/cores/flashrom-wb/flashrom_controller.vhd new file mode 100644 index 0000000..e239f90 --- /dev/null +++ b/cores/flashrom-wb/flashrom_controller.vhd @@ -0,0 +1,130 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.flashrom_pkg.all; + +entity flashrom_controller is + port( + clk : in std_logic; + rst : in std_logic; + clr : in std_logic; + + -- Control IF + ready : out std_logic; -- The controller is ready to accept commands + page : in std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0); + sync_stb : in std_logic; -- Synchronize current memory page with chip, only sampled when ready + load_stb : in std_logic; -- Load page into local buffer, only sampled when ready + status_update_stb : in std_logic; -- Update status vector + status : out std_logic_vector(31 downto 0); -- value of the status register (update using status_update_stb) + info : out std_logic_vector(31 downto 0); -- value of the information register (updated on reset) + + -- Data IF + data_in : in std_logic_vector(7 downto 0); + data_in_valid : in std_logic; + data_out : out std_logic_vector(7 downto 0); + data_out_valid : out std_logic; + + -- SPI flash hardware signals + spi_si : out std_logic; -- SPI serial in + spi_so : in std_logic; -- SPI serial out + spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module + spi_reset_n : out std_logic; -- SPI hard reset + spi_cs_n : out std_logic; -- SPI chip select + spi_wp_n : out std_logic -- SPI write protect + ); +end entity flashrom_controller; + +architecture RTL of flashrom_controller is + constant spif_max_word_length : integer := 32; + constant max_dummy_bits : integer := 16; + + type state_t is (INIT, GETINFO, IDLE); + signal state : state_t; + + signal spif_data_in_valid : std_logic; + signal spif_data_in : std_logic_vector(spif_max_word_length - 1 downto 0); + signal spif_data_in_length : integer range 0 to spif_max_word_length; + signal spif_data_next : std_logic; + signal spif_data_out : std_logic_vector(spif_max_word_length - 1 downto 0); + signal spif_data_out_valid : std_logic; + signal spif_data_out_length : integer range 0 to spif_max_word_length; + + signal words_sent : integer range 0 to 511; + signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits; + signal spif_transmission_active : std_logic; +begin + spi_wp_n <= '1'; + + flashrom_spi_inst : entity work.flashrom_spi + generic map( + clk_divider => 2, + max_word_length => spif_max_word_length, + max_dummy_bits => max_dummy_bits) + port map( + clk => clk, + rst => rst, + clr => clr, + spi_si => spi_si, + spi_so => spi_so, + spi_sck => spi_sck, + spi_cs_n => spi_cs_n, + data_in_valid => spif_data_in_valid, + data_in => spif_data_in, + data_in_length => spif_data_in_length, + data_next => spif_data_next, + data_out => spif_data_out, + data_out_valid => spif_data_out_valid, + data_out_length => spif_data_out_length, + data_out_dummy_bits => spif_data_out_dummy_bits, + transmission_active => spif_transmission_active); + + flashrom_controller_p : process(clk, rst) is + procedure default_state is + begin + spi_reset_n <= '1'; + spif_data_in_valid <= '0'; + end procedure default_state; + + procedure reset_state is + begin + default_state; + state <= INIT; + spi_reset_n <= '0'; + words_sent <= 0; + + spif_data_in <= (others => '0'); + spif_data_in_length <= 0; + spif_data_out_length <= 0; + spif_data_out_dummy_bits <= 0; + end procedure reset_state; + begin + if rst = '1' then + reset_state; + elsif rising_edge(clk) then + default_state; + if clr = '1' then + reset_state; + else + case state is + when INIT => + words_sent <= 0; + state <= GETINFO; + when GETINFO => + spif_data_in_length <= 16; -- Other bits after OpCode are don't care, so just repeat OPC + spif_data_out_length <= 32; + spif_data_out_dummy_bits <= 8; + spif_data_in_valid <= '1'; + spif_data_in <= FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID); + if spif_data_out_valid = '1' then + info <= spif_data_out; + state <= IDLE; + spif_data_in_valid <= '0'; + end if; + when IDLE => + null; + end case; + end if; + end if; + end process flashrom_controller_p; +end architecture RTL; diff --git a/cores/flashrom-wb/flashrom_pkg.vhd b/cores/flashrom-wb/flashrom_pkg.vhd new file mode 100644 index 0000000..e533c2e --- /dev/null +++ b/cores/flashrom-wb/flashrom_pkg.vhd @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package flashrom_pkg is + constant FLASHROM_ADDR_WIDTH : integer := 12; + constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; + + function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector; +end package flashrom_pkg; + +package body flashrom_pkg is + function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector is + begin + return std_logic_vector(to_unsigned(0, target'length - other'length)); + end function padBits; + +end package body flashrom_pkg; diff --git a/cores/flashrom-wb/flashrom_spi.vhd b/cores/flashrom-wb/flashrom_spi.vhd new file mode 100644 index 0000000..26f8b95 --- /dev/null +++ b/cores/flashrom-wb/flashrom_spi.vhd @@ -0,0 +1,145 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity flashrom_spi is + generic( + clk_divider : integer range 2 to 9999 := 2; + max_word_length : integer := 32; + max_dummy_bits : integer := 8 + ); + port( + clk : in std_logic; + rst : in std_logic; + clr : in std_logic; + + -- SPI flash hardware signals + spi_si : out std_logic; -- SPI serial in + spi_so : in std_logic; -- SPI serial out + spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module + spi_cs_n : out std_logic; -- SPI chip select + + -- Logic interface + data_in_valid : in std_logic; -- Data to Flash ROM + data_in : in std_logic_vector(max_word_length - 1 downto 0); + data_in_length : in integer range 0 to max_word_length; + data_next : out std_logic; + data_out : out std_logic_vector(max_word_length - 1 downto 0); + data_out_valid : out std_logic; -- Data from Flash ROM + data_out_length : in integer range 0 to max_word_length; + data_out_dummy_bits : in integer range 0 to max_dummy_bits; + transmission_active : out std_logic + ); +end entity flashrom_spi; + +architecture RTL of flashrom_spi is + type txstate_t is (IDLE, TX); + signal state : txstate_t; + signal ckDiv : integer range 0 to clk_divider - 2; + signal shiftreg : std_logic_vector(max_word_length - 1 downto 0); + signal bitCounter : integer range 0 to max_word_length - 1; + signal bitCounterIn : integer range 0 to max_word_length + max_dummy_bits - 1; -- TODO: Actually this must count until the higher of the two + signal data_in_length_i : integer range 0 to max_word_length; + signal data_out_length_i : integer range 0 to max_word_length; + signal delayCycle : std_logic; + signal oneBitRead : std_logic; + signal dummy_passed : boolean; +begin + toSpi : process(clk, rst) is + procedure default_state is + begin + data_next <= '0'; + data_out_valid <= '0'; + end procedure default_state; + + procedure reset_state is + begin + state <= IDLE; + spi_sck <= '0'; + shiftreg <= (others => '0'); + bitCounter <= 0; + bitCounterIn <= 0; + data_out <= (others => '0'); + delayCycle <= '0'; + oneBitRead <= '0'; + dummy_passed <= false; + default_state; + end procedure reset_state; + begin + if rst = '1' then + reset_state; + elsif rising_edge(clk) then + default_state; + if clr = '1' then + reset_state; + else + case state is + when IDLE => + delayCycle <= '0'; + spi_sck <= '0'; + oneBitRead <= '0'; + dummy_passed <= false; + data_out <= (others => '0'); + if data_in_valid = '1' then + state <= TX; + bitCounter <= 0; + bitCounterIn <= 0; + data_in_length_i <= 0; + end if; + when TX => + if ckDiv = clk_divider - 2 then + spi_sck <= not spi_sck; + if spi_sck = '0' then -- rising edge + if bitCounter = data_in_length_i then + bitCounter <= 0; + if data_in_valid = '1' then + shiftreg <= data_in; + data_in_length_i <= data_in_length - 1; + data_out_length_i <= data_out_length - 1; + data_next <= '1'; + else + delayCycle <= '1'; + end if; + else + bitCounter <= bitCounter + 1; + shiftreg <= shiftreg(shiftreg'high - 1 downto 0) & '0'; + end if; + else -- spi_sck = '1' (falling edge) + data_out <= data_out(data_out'high - 1 downto 0) & spi_so; + + if bitCounterIn = 0 then + if dummy_passed then + data_out_valid <= '1'; + end if; + end if; + if not dummy_passed then + if bitCounterIn = data_out_dummy_bits then + dummy_passed <= true; + bitCounterIn <= 1; + else + bitCounterIn <= bitCounterIn + 1; + end if; + else + if bitCounterIn = data_out_length_i then + bitCounterIn <= 0; + else + bitCounterIn <= bitCounterIn + 1; + end if; + if delayCycle = '1' then + spi_sck <= '0'; + state <= IDLE; + end if; + end if; + end if; + else + ckDiv <= ckDiv + 1; + end if; + end case; + end if; + end if; + end process toSpi; + spi_si <= shiftreg(shiftreg'high); + spi_cs_n <= '0' when state = TX else '1'; + + transmission_active <= '1' when state = TX else '0'; +end architecture RTL; diff --git a/cores/flashrom-wb/flashrom_spi2.copyvhd b/cores/flashrom-wb/flashrom_spi2.copyvhd new file mode 100644 index 0000000..ff74fef --- /dev/null +++ b/cores/flashrom-wb/flashrom_spi2.copyvhd @@ -0,0 +1,141 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity flashrom_spi is + generic( + clk_divider : integer range 2 to 9999 := 2; + max_word_length : integer := 32; + max_dummy_bits : integer := 8 + ); + port( + clk : in std_logic; + rst : in std_logic; + clr : in std_logic; + + -- SPI flash hardware signals + spi_si : out std_logic; -- SPI serial in + spi_so : in std_logic; -- SPI serial out + spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module + spi_cs_n : out std_logic; -- SPI chip select + + -- Logic interface + data_in_valid : in std_logic; + data_in : in std_logic_vector(max_word_length - 1 downto 0); + data_in_length : in integer range 0 to max_word_length; + data_next : out std_logic; + data_out : out std_logic_vector(max_word_length - 1 downto 0); + data_out_valid : out std_logic; + data_out_length : in integer range 0 to max_word_length; + data_out_dummy_bits : in integer range 0 to max_dummy_bits; + transmission_active : out std_logic + ); +end entity flashrom_spi; + +architecture RTL of flashrom_spi is + type txstate_t is (IDLE, TX); + signal state : txstate_t; + signal ckDiv : integer range 0 to clk_divider - 2; + signal shiftreg : std_logic_vector(max_word_length - 1 downto 0); + signal bitCounter : integer range 0 to max_word_length - 1; + signal bitCounterIn : integer range 0 to max_word_length + max_dummy_bits - 1; + signal data_in_length_i : integer range 0 to max_word_length; + signal data_out_length_i : integer range 0 to max_word_length; + signal delayCycle : std_logic; + signal oneBitRead : std_logic; + signal dummy_passed : boolean; +begin + toSpi : process(clk, rst) is + procedure default_state is + begin + data_next <= '0'; + data_out_valid <= '0'; + end procedure default_state; + + procedure reset_state is + begin + state <= IDLE; + spi_sck <= '0'; + shiftreg <= (others => '0'); + bitCounter <= 0; + bitCounterIn <= 0; + data_out <= (others => '0'); + delayCycle <= '0'; + oneBitRead <= '0'; + dummy_passed <= false; + default_state; + end procedure reset_state; + begin + if rst = '1' then + reset_state; + elsif rising_edge(clk) then + default_state; + if clr = '1' then + reset_state; + else + case state is + when IDLE => + delayCycle <= '0'; + spi_sck <= '0'; + oneBitRead <= '0'; + dummy_passed <= false; + data_out <= (others => '0'); + if data_in_valid = '1' then + state <= TX; + bitCounter <= 0; + bitCounterIn <= 0; + data_in_length_i <= 0; + end if; + when TX => + if ckDiv = clk_divider - 2 then + spi_sck <= not spi_sck; + if spi_sck = '0' then -- rising edge + if bitCounter = data_in_length_i then + bitCounter <= 0; + if data_in_valid = '1' then + shiftreg <= data_in; + data_in_length_i <= data_in_length - 1; + data_out_length_i <= data_out_length - 1; + data_next <= '1'; + else + delayCycle <= '1'; + end if; + else + bitCounter <= bitCounter + 1; + shiftreg <= shiftreg(shiftreg'high - 1 downto 0) & '0'; + end if; + else -- spi_sck = '1' (falling edge) + data_out <= data_out(data_out'high - 1 downto 0) & spi_so; + oneBitRead <= '1'; + if bitCounterIn = 0 then + if dummy_passed then + data_out_valid <= '1'; + end if; + end if; + if not dummy_passed and bitCounterIn = data_out_dummy_bits then + dummy_passed <= true; + bitCounterIn <= 1; + else + if bitCounterIn = data_out_length_i then + bitCounterIn <= 0; + else + bitCounterIn <= bitCounterIn + 1; + end if; + if delayCycle = '1' then + spi_sck <= '0'; + state <= IDLE; + end if; + end if; + end if; + else + ckDiv <= ckDiv + 1; + end if; + end case; + end if; + end if; + end process toSpi; + spi_si <= shiftreg(shiftreg'high); + spi_cs_n <= '0' when state = TX else '1'; + + transmission_active <= '1' when state = TX else '0'; +end architecture RTL; diff --git a/cores/generic/edgeDetector.vhd b/cores/generic/edgeDetector.vhd new file mode 100644 index 0000000..970387a --- /dev/null +++ b/cores/generic/edgeDetector.vhd @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity edgeDetector is + port( + clk : in std_logic; + rst : in std_logic; + sig : in std_logic; + risingEdge : out std_logic; + fallingEdge : out std_logic; + anyEdge : out std_logic + ); +end entity edgeDetector; + +architecture RTL of edgeDetector is + signal temp : std_logic_vector(1 downto 0); +begin + shiftomat : process(rst, clk) is + begin + if rst = '1' then + temp <= "00"; + elsif rising_edge(clk) then + temp <= temp(0) & sig; + end if; + end process shiftomat; + + risingEdge <= '1' when (temp = "01") else '0'; + fallingEdge <= '1' when (temp = "10") else '0'; + anyEdge <= '1' when (temp = "01" or temp = "10") else '0'; +end architecture RTL; diff --git a/cores/generic/synchronizer.vhd b/cores/generic/synchronizer.vhd new file mode 100644 index 0000000..3630ae0 --- /dev/null +++ b/cores/generic/synchronizer.vhd @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity synchronizer is + generic(COUNT : integer := 1); + port( + clk : in std_logic; + rst : in std_logic; + dIn : in std_logic_vector(COUNT - 1 downto 0); + dOut : out std_logic_vector(COUNT - 1 downto 0) + ); +end entity synchronizer; + +architecture RTL of synchronizer is + signal temp : std_logic_vector(COUNT - 1 downto 0); +begin + synch : process(rst, clk) is + begin + for i in 0 to COUNT - 1 loop + if rst = '1' then + temp(i) <= '0'; + dOut(i) <= '0'; + elsif rising_edge(clk) then + temp(i) <= dIn(i); + dOut(i) <= temp(i); + end if; + end loop; + end process synch; + +end architecture RTL; diff --git a/cores/jinn.vhd b/cores/jinn.vhd new file mode 100644 index 0000000..c310306 --- /dev/null +++ b/cores/jinn.vhd @@ -0,0 +1,199 @@ +-- A simple Wishbone interface, controllable via UART. +-- Author: Markus Koch +-- +-- Instructions: +-- Write: TX [Write-Count] [32b Addr] [32b Data] -------- [32b Addr] [32b Data] -------- ... [Write-Count] [32b Addr] [32b Data] ... +-- RX ----------------------------------- [8b CKS] --------------------- [8b CKS] ... ----------------------------------- ... +-- +-- Read: TX [8b 0x0] [32b Addr] ---------- [32b Addr] ... +-- RX ------------------- [32b Data] ---------- ... +-- +-- Stall: TX [8b 0xFF] +-- RX --------- +-- +-- Reset: TX [8b 0xFE] +-- --------- +-- +-- Log: +-- 2015/06/24: Created file +-- 2015/06/24: Removed logic for tx/rx buffers +-- 2015/07/14: Added stall/reset logic + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ip; +use ip.wishbone_package.all; + +entity jinn is + port( + clk_i : in std_logic; + rst_i : in std_logic; + + -- Wishbone + master_i : in wishbone_v3_master_in; + master_o : out wishbone_v3_master_out; + + -- CPU Control + cpu_stall : out std_logic; + cpu_reset : out std_logic; + + -- Data link + data_i : in std_logic_vector(7 downto 0); -- Data in from UART + data_available : in std_logic; -- UART RX strobe + + data_o : out std_logic_vector(7 downto 0); -- Data out to UART + data_valid_o : out std_logic; -- Data out strobe + output_busy_i : in std_logic -- Transmit busy -> stall core + ); +end entity jinn; + +architecture RTL of jinn is + signal write_counter : integer range 0 to 255; + signal position : integer range 0 to 7; + signal address : wishbone_address; + signal data : wishbone_data; + signal cks : unsigned(7 downto 0); + + type state_t is (COMMAND, PARSE, EXECUTE, TXSERIAL); + signal state : state_t; + signal txDelay : std_logic; +begin + jinn_p : process(clk_i, rst_i) is + begin + if rst_i = '1' then + -- RESET! + position <= 0; + state <= COMMAND; + write_counter <= 0; + data_valid_o <= '0'; + address <= (others => '0'); + data <= (others => '0'); + master_o.CYC <= '0'; + master_o.STB <= '0'; + master_o.ADR <= (others => '0'); + master_o.DAT <= (others => '0'); + master_o.WE <= '0'; + txDelay <= '0'; + cks <= (others => '0'); + cpu_stall <= '0'; + cpu_reset <= '1'; + elsif rising_edge(clk_i) then + data_valid_o <= '0'; + master_o.CYC <= '0'; + master_o.STB <= '0'; + + cpu_reset <= '0'; + + case state is + when COMMAND => + cks <= (others => '0'); + position <= 0; + txDelay <= '0'; + if data_available = '1' then + if unsigned(data_i) = x"FF" then + cpu_stall <= '1'; + elsif unsigned(data_i) = x"FE" then + cpu_reset <= '1'; + cpu_stall <= '0'; + else + write_counter <= to_integer(unsigned(data_i)); + state <= PARSE; + end if; + end if; + when PARSE => + if data_available = '1' then + cks <= cks + unsigned(data_i); -- Sum everything, address and data + if position < 7 then + position <= position + 1; + end if; + + if position < 4 then -- addr word + --address(8 * (position + 1) - 1 downto 8 * position) <= data_i; + address <= address(23 downto 0) & data_i; + else -- data word + --data(8 * (position + 1 - 4) - 1 downto 8 * (position - 4)) <= data_i; + data <= data(23 downto 0) & data_i; + end if; + + if (position = 7) or (position = 3 and write_counter = 0) then -- only retrieve address in read mode + position <= 0; + state <= EXECUTE; + + -- master_o.ADR <= address; + -- master_o.DAT <= data; + -- master_o.CYC <= '1'; + -- master_o.STB <= '1'; + -- if write_counter = 0 then + -- master_o.WE <= '0'; + -- else + -- master_o.WE <= '1'; + -- end if; + end if; + end if; + when EXECUTE => + master_o.ADR <= address; + master_o.DAT <= data; + master_o.CYC <= '1'; + master_o.STB <= '1'; + if write_counter = 0 then + master_o.WE <= '0'; + else + master_o.WE <= '1'; + end if; + + if master_i.ERR = '1' or master_i.ACK = '1' then -- END OF transmission + master_o.CYC <= '0'; + master_o.STB <= '0'; + + if write_counter = 0 then -- read + data <= master_i.DAT; + state <= TXSERIAL; + position <= 0; + else + write_counter <= write_counter - 1; + if master_i.ACK = '1' then + data <= std_logic_vector(cks) & x"000000"; -- ACK! + else + data <= not std_logic_vector(cks) & x"FFFFFF"; -- NAK! by sending a probably woring checksum + end if; + position <= 3; -- Only transmit one byte (the checksum) + state <= TXSERIAL; + cks <= (others => '0'); + end if; + elsif master_i.RTY = '1' then + null; + -- wait + end if; + when TXSERIAL => + txDelay <= not txDelay; + if txDelay = '0' and output_busy_i = '0' then -- only every odd cycle (uart has a busy-activate delay of 1) + --data_o <= address(8 * (position + 1) - 1 downto 8 * position); + data_o <= data(31 downto 24); + data <= data(23 downto 0) & x"00"; + data_valid_o <= '1'; + + if position = 3 then + position <= 0; + if write_counter = 0 then + state <= COMMAND; -- R/W selector (Write-Count) + else + state <= PARSE; -- more writes are following directly + end if; + else + position <= position + 1; + end if; + end if; + end case; + + --master_o.CYC <= '0'; -- DEBUG ONLY - diasble moduel + --master_o.STB <= '0'; -- DEBUG ONYL + end if; + end process jinn_p; + master_o.SEL <= "1111"; + + master_o.BTE <= (others => '0'); + master_o.CTI <= (others => '0'); + master_o.LOCK <= '0'; +end architecture RTL; diff --git a/cores/sram/sram_wb.vhd b/cores/sram/sram_wb.vhd new file mode 100644 index 0000000..0114bfb --- /dev/null +++ b/cores/sram/sram_wb.vhd @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ip; +use ip.wishbone_package.all; +use ip.all; + +entity sram_wb is + port( + clk : in std_logic; + rst : in std_logic; + + -- Wishbone + wb_in : in wishbone_v3_slave_in; + wb_out : out wishbone_v3_slave_out + ); +end entity sram_wb; + +architecture RTL of sram_wb is + signal ram_address : std_logic_vector(10 DOWNTO 0); + signal ram_byteena : std_logic_vector(3 DOWNTO 0); + signal ram_dIn : std_logic_vector(31 DOWNTO 0); + signal ram_we : std_logic; + signal ram_dOut : std_logic_vector(31 DOWNTO 0); + signal ackRead : std_logic; +begin + ram0_inst : entity ip.ram0 + port map( + address => ram_address, + byteena => ram_byteena, + clock => clk, + data => ram_dIn, + wren => ram_we, + q => ram_dOut + ); + + sram_p : process(clk, rst) is + begin + if rst = '1' then + ackRead <= '0'; + elsif rising_edge(clk) then + ackRead <= '0'; + if wb_in.CYC = '1' and wb_in.STB = '1' and wb_in.WE = '0' then + ackRead <= '1'; + end if; + end if; + end process sram_p; + + ram_address <= wb_in.ADR(12 downto 2); + ram_we <= wb_in.WE and wb_in.CYC and wb_in.STB; + wb_out.ACK <= (wb_in.WE or ackRead) and wb_in.CYC and wb_in.STB; + wb_out.ERR <= '0'; + wb_out.RTY <= '0'; + wb_out.DAT <= ram_dOut; + + ram_dIn <= wb_in.DAT; + ram_byteena <= wb_in.SEL; + +end architecture RTL; diff --git a/cores/uart/uart_rx.vhd b/cores/uart/uart_rx.vhd new file mode 100644 index 0000000..a4b6765 --- /dev/null +++ b/cores/uart/uart_rx.vhd @@ -0,0 +1,155 @@ +-- A simple UART (TX) +-- Author : Kurisu +-- Modifed : Markus + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity uart_rx is + port( + clk : in std_logic; + rst : in std_logic; + data : out std_logic_vector(7 downto 0); + byte_ready : out std_logic; + error : out std_logic; + + ckDiv : in std_logic_vector(15 downto 0); + parityEnable : in std_logic; + parityOdd : in std_logic; + twoStopBits : in std_logic; + + rx : in std_logic + ); +end entity uart_rx; + +architecture RTL of uart_rx is + constant SYNCH_COUNT : integer := 11; -- Min. 8 + constant BITCOUNT : integer := 8; + + type state_t is (SYNCH, IDLE, START, RECEIVE, PARITY, STOP); + + signal state : state_t; + signal clkDivider : unsigned(15 downto 0); + signal bitCounter : integer range 0 to SYNCH_COUNT; + signal data_i : std_logic_vector(7 downto 0); + signal rx_edge : std_logic; + signal parity_calc : std_logic; + signal rx_i : std_logic; + +begin + synchronizer_inst : entity work.synchronizer + generic map( + COUNT => 1 + ) + port map( + clk => clk, + rst => rst, + dIn(0) => rx, + dOut(0) => rx_i + ); + + edgeDetector_inst : entity work.edgeDetector + port map(clk => clk, + rst => rst, + sig => rx_i, + risingEdge => open, + fallingEdge => open, + anyEdge => rx_edge); + + rxFSM : process(clk, rst, parityOdd, ckDiv) is + begin + if rst = '1' then + state <= SYNCH; + bitCounter <= SYNCH_COUNT; + clkDivider <= unsigned(ckDiv); + error <= '0'; + parity_calc <= parityOdd; + data_i <= x"00"; + data <= x"00"; + byte_ready <= '0'; + elsif rising_edge(clk) then + byte_ready <= '0'; + error <= '0'; + if (clkDivider = 0) then + clkDivider <= unsigned(ckDiv); + else + clkDivider <= clkDivider - 1; + end if; + case state is + when SYNCH => -- Wait for 11 consecutive ones + if (clkDivider = to_unsigned(0, clkDivider'length)) then + if rx_i = '1' then + if bitCounter = 0 then + state <= IDLE; + else + bitCounter <= bitcounter - 1; + end if; + else + bitCounter <= SYNCH_COUNT; + end if; + end if; + when IDLE => -- Detect transition for sync + if rx_i = '0' then + state <= START; + clkDivider <= unsigned('0' & ckDiv(15 downto 1)); -- cMax_half. After that we are in the middle of the start bit + parity_calc <= parityOdd; + end if; + when START => + if (clkDivider = to_unsigned(0, clkDivider'length)) then + if rx_i = '0' then + state <= RECEIVE; + bitCounter <= 0; + else + report "uart_rx: START BIT ERROR" severity warning; + error <= '1'; + state <= SYNCH; + end if; + end if; + when RECEIVE => + if (clkDivider = to_unsigned(0, clkDivider'length)) then + data_i(bitCounter) <= rx_i; + if rx_i = '1' then + parity_calc <= not parity_calc; + end if; + if bitCounter = BITCOUNT - 1 then + bitCounter <= 0; + if parityEnable = '1' then + state <= PARITY; + else + state <= STOP; + end if; + else + bitCounter <= bitCounter + 1; + end if; + end if; + when PARITY => + if (clkDivider = to_unsigned(0, clkDivider'length)) then + if parity_calc = rx_i then + state <= STOP; + else + state <= SYNCH; + error <= '1'; + report "uart_rx: PARITY ERROR" severity warning; + end if; + end if; + when STOP => + if (clkDivider = to_unsigned(0, clkDivider'length)) then + if (rx_i = '1') then + bitCounter <= bitCounter + 1; + if bitCounter = 1 or twoStopBits = '0' then + state <= IDLE; + data <= data_i; + byte_ready <= '1'; + end if; + else + error <= '1'; + state <= SYNCH; + report "uart_rx: STOP BIT ERROR" severity warning; + end if; + end if; + end case; + end if; + end process rxFSM; + +end architecture RTL; diff --git a/cores/uart/uart_tx.vhd b/cores/uart/uart_tx.vhd new file mode 100644 index 0000000..336158a --- /dev/null +++ b/cores/uart/uart_tx.vhd @@ -0,0 +1,104 @@ +-- A simple UART (TX) +-- Author : Kurisu +-- Modifed : Markus + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity uart_tx is + port( + clk : in std_logic; + rst : in std_logic; + data : in std_logic_vector(7 downto 0); + byte_ready : in std_logic; + busy : out std_logic; + + ckDiv : in std_logic_vector(15 downto 0); + parityEnable : in std_logic; + parityOdd : in std_logic; + twoStopBits : in std_logic; + + tx : out std_logic + ); +end entity uart_tx; + +architecture RTL of uart_tx is + type state_t is (IDLE, START, TRANSMIT, PARITY, STOP); + + signal state : state_t; + signal clkDivider : unsigned(15 downto 0); + signal data_i : std_logic_vector(7 downto 0); + signal bitCounter : integer range 0 to 7; + signal parity_calc : std_logic; + +begin + txFSM : process(clk, rst, ckDiv, parityOdd) is + begin + if rst = '1' then + data_i <= x"00"; + state <= IDLE; + tx <= '1'; + bitCounter <= 0; + busy <= '0'; + clkDivider <= unsigned(ckDiv); + parity_calc <= parityOdd; + elsif rising_edge(clk) then + busy <= '1'; + + if (clkDivider = 0) then + clkDivider <= unsigned(ckDiv); + else + clkDivider <= clkDivider - 1; + end if; + + case state is + when IDLE => + busy <= '0'; + tx <= '1'; + if byte_ready = '1' then + data_i <= data; + state <= START; + clkDivider <= unsigned(ckDiv); + bitCounter <= 0; + parity_calc <= '0'; + busy <= '1'; + tx <= '1'; + end if; + when START => + tx <= '0'; + state <= TRANSMIT; + when TRANSMIT => + if (clkDivider = to_unsigned(0, clkDivider'length)) then + tx <= data_i(bitCounter); + if data_i(bitCounter) = '1' then + parity_calc <= not parity_calc; + end if; + if bitCounter = 7 then + bitCounter <= 0; + if parityEnable = '1' then + state <= PARITY; + else + state <= STOP; + end if; + else + bitCounter <= bitCounter + 1; + end if; + end if; + when PARITY => + if (clkDivider = to_unsigned(0, clkDivider'length)) then + tx <= parity_calc; + state <= STOP; + end if; + when STOP => + if (clkDivider = to_unsigned(0, clkDivider'length)) then + tx <= '1'; + bitCounter <= bitCounter + 1; + if (bitCounter = 1 and twoStopBits = '0') or (bitCounter = 2 and twoStopBits = '1') then + state <= IDLE; + end if; + end if; + end case; + end if; + end process txFSM; +end architecture RTL; diff --git a/cores/uart/uart_wb.vhd b/cores/uart/uart_wb.vhd new file mode 100644 index 0000000..5a1636e --- /dev/null +++ b/cores/uart/uart_wb.vhd @@ -0,0 +1,162 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.OR_REDUCE; + +library ip; +use ip.wishbone_package.all; + +entity uart_wb is + generic( + portcount : integer := 1 + ); + port( + clk : in std_logic; + rst : in std_logic; + -- Wishbone + slave_i : in wishbone_slave_in; + slave_o : out wishbone_slave_out; + irq_o : out std_logic_vector(portcount - 1 downto 0); + -- UART + rx : in std_logic_vector(portcount - 1 downto 0); + tx : out std_logic_vector(portcount - 1 downto 0) + ); +end entity uart_wb; + +architecture RTL of uart_wb is + constant addressQuantum : integer := 4; + constant registersPerCore : integer := 5; + + type uart_data is array (portcount - 1 downto 0) of std_logic_vector(7 downto 0); + type uart_ckDiv is array (portcount - 1 downto 0) of std_logic_vector(15 downto 0); + type uart_register is array (portcount - 1 downto 0) of std_logic_vector(31 downto 0); + + signal rx_data : uart_data; + signal rx_byte_ready : std_logic_vector(portcount - 1 downto 0); + signal rx_error : std_logic_vector(portcount - 1 downto 0); + signal ckDiv : uart_ckDiv; + signal parityEnable : std_logic_vector(portcount - 1 downto 0); + signal parityOdd : std_logic_vector(portcount - 1 downto 0); + signal twoStopBits : std_logic_vector(portcount - 1 downto 0); + signal tx_data : uart_data; + signal tx_strobe : std_logic_vector(portcount - 1 downto 0); + signal tx_busy : std_logic_vector(portcount - 1 downto 0); + + signal CR : uart_register; + signal SR : uart_register; + signal IMR : uart_register; + signal MASKEDSR : uart_register; + + signal data_in_buffered : uart_data; + +begin + generate_label : for i in 0 to portcount - 1 generate + uart_rx_inst : entity work.uart_rx + port map( + clk => clk, + rst => rst, + data => rx_data(i), + byte_ready => rx_byte_ready(i), + error => rx_error(i), + ckDiv => ckDiv(i), + parityEnable => parityEnable(i), + parityOdd => parityOdd(i), + twoStopBits => twoStopBits(i), + rx => rx(i) + ); + uart_tx_inst : entity work.uart_tx + port map( + clk => clk, + rst => rst, + data => tx_data(i), + byte_ready => tx_strobe(i), + busy => tx_busy(i), + ckDiv => ckDiv(i), + parityEnable => parityEnable(i), + parityOdd => parityOdd(i), + twoStopBits => twoStopBits(i), + tx => tx(i) + ); + end generate generate_label; + + wb : process(rst, clk) is + begin + if rst = '1' then + slave_o.DAT <= (others => '0'); + + for i in 0 to portcount - 1 loop + SR(i) <= (others => '0'); + CR(i) <= (others => '0'); + IMR(i) <= (others => '0'); + tx_strobe(i) <= '0'; + tx_data(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + for i in 0 to portcount - 1 loop + slave_o.ACK <= '0'; + tx_strobe(i) <= '0'; + + --SR update + if (rx_error(i) = '1') then + SR(i)(17) <= '1'; -- Set RXEI + end if; + if (rx_byte_ready(i) = '1') then + SR(i)(18) <= '1'; -- Set RXI + SR(i)(16) <= '1'; -- Set RXNE (no FIFO yet) + data_in_buffered(i) <= rx_data(i); + end if; + + SR(i)(0) <= tx_busy(i); -- TXBF; no FIFO + SR(i)(1) <= tx_busy(i); -- TXActive + + -- WB + if slave_i.CYC = '1' and slave_i.STB = '1' then + if unsigned(slave_i.ADR) = to_unsigned((registersPerCore * i), slave_i.ADR'length) then -- CRx + slave_o.DAT <= CR(i); + if slave_i.we = '1' then + CR(i) <= slave_i.DAT; + end if; + elsif unsigned(slave_i.ADR) = to_unsigned((registersPerCore * i) + 1 * addressQuantum, slave_i.ADR'length) then --SRx + slave_o.DAT <= SR(i); + if slave_i.we = '1' then + SR(i) <= slave_i.DAT and (x"00" & "00000110" & x"0000"); -- mask RO bits + end if; + elsif unsigned(slave_i.ADR) = to_unsigned((registersPerCore * i) + 2 * addressQuantum, slave_i.ADR'length) then --IMRx + slave_o.DAT <= IMR(i); + if slave_i.we = '1' then + IMR(i) <= slave_i.DAT; + end if; + elsif unsigned(slave_i.ADR) = to_unsigned((registersPerCore * i) + 3 * addressQuantum, slave_i.ADR'length) then --ODRx + slave_o.DAT <= x"000000" & tx_data(i); --(others => '0'); + if slave_i.we = '1' then + tx_data(i) <= slave_i.DAT(7 downto 0); + tx_strobe(i) <= '1'; + end if; + elsif unsigned(slave_i.ADR) = to_unsigned((registersPerCore * i) + 4 * addressQuantum, slave_i.ADR'length) then --IDRx + slave_o.DAT <= x"000000" & data_in_buffered(i); + SR(i)(18) <= '0'; -- RXI Clear interrupt + SR(i)(16) <= '0'; -- RXNE No FIFO -> buffer is immediately empty again + end if; + slave_o.ACK <= '1'; + end if; + end loop; + end if; + end process wb; + + slave_o.RTY <= '0'; + slave_o.STALL <= '0'; + slave_o.ERR <= '0'; + + applyCR : for i in 0 to portcount - 1 generate + ckDiv(i) <= CR(i)(31 downto 16); + parityEnable(i) <= CR(i)(1); + parityOdd(i) <= CR(i)(0); + twoStopBits(i) <= CR(i)(2); + end generate applyCR; + + masking : for i in 0 to portcount - 1 generate + MASKEDSR(i) <= SR(i) and IMR(i); + irq_o(i) <= OR_REDUCE(MASKEDSR(i)); + end generate masking; + +end architecture RTL; diff --git a/datasets/ram_init - Copy.hex b/datasets/ram_init - Copy.hex new file mode 100644 index 0000000..4ef164c --- /dev/null +++ b/datasets/ram_init - Copy.hex @@ -0,0 +1,53 @@ +:1000000000000000150000000000000000000000DB +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:100100001500000015000000180000001820000174 +:10011000A821FFFC18400001A842FFFC1860000164 +:10012000A863738018800001A8847474E404180024 +:100130001000000615000000D80300009C630001B9 +:1001400003FFFFFB1500000018600001A8636800B2 +:1001500018800001A88470C818A00001A8A5279DD8 +:10016000E404180010000008150000008CC5000011 +:10017000D80330009C6300019CA5000103FFFFF938 +:10018000150000009C6000009C8000009CA0000006 +:100190009CC000009CE000009D0000009D4000000D +:1001A0009D6000009D8000009DA000009DC000009B +:1001B0009DE000009E0000009E2000009E40000088 +:1001C0009E6000009E8000009EA00000188000003D +:1001D000A8842004480020001500000018800001B9 +:1001E000A88412704800200015000000188000004C +:1001F000A88420284800200015000000000000000E +:10020000150000009C21FF0CD4014818040002D402 +:100210001500000019200000A9290DD41860000065 +:10022000A86322E044001800150000000000000050 +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:10030000150000009C21FF0CD40148180400029441 +:100310001500000019200000A9290DD41860000064 +:10032000A8630D2C44001800150000000000000018 +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD \ No newline at end of file diff --git a/datasets/ram_init.hex b/datasets/ram_init.hex new file mode 100644 index 0000000..d3a4d1f --- /dev/null +++ b/datasets/ram_init.hex @@ -0,0 +1,37 @@ +:100040001500000015000000180000001820000174 +:10004400A821FFFC18400001A842FFFC1860000164 +:10004800A863738018800001A8847474E404180024 +:10004C001000000615000000D80300009C630001B9 +:1000500003FFFFFB1500000018600001A8636800B2 +:1000540018800001A88470C818A00001A8A5279DD8 +:10005800E404180010000008150000008CC5000011 +:10005C00D80330009C6300019CA5000103FFFFF938 +:10006000150000009C6000009C8000009CA0000006 +:100064009CC000009CE000009D0000009D4000000D +:100068009D6000009D8000009DA000009DC000009B +:10006C009DE000009E0000009E2000009E40000088 +:100070009E6000009E8000009EA00000188000003D +:1001D000A8842004480020001500000018800001B9 +:1001E000A88412704800200015000000188000004C +:1001F000A88420284800200015000000000000000E +:10020000150000009C21FF0CD4014818040002D402 +:100210001500000019200000A9290DD41860000065 +:10022000A86322E044001800150000000000000050 +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:10030000150000009C21FF0CD40148180400029441 +:100310001500000019200000A9290DD41860000064 +:10032000A8630D2C44001800150000000000000018 +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD \ No newline at end of file diff --git a/design/top.vhd b/design/top.vhd new file mode 100644 index 0000000..fed183f --- /dev/null +++ b/design/top.vhd @@ -0,0 +1,321 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ddr3; + +library ip; +use ip.wishbone_package.all; +use ip.mor1kx_pkg.all; + +entity top is + port( + clk_hw : in std_logic; + rst_hw : in std_logic; + + -- GPIO + GPIOA : inout std_logic_vector(wishbone_data_width - 1 downto 0); + + -- JINN + jinn_uart_rx : in std_logic; + jinn_uart_tx : out std_logic; + + -- UART + uart_rx : in std_logic; + uart_tx : out std_logic; + + -- DDR3 RAM + mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a + mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n + mem_reset_n : out std_logic; -- .mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt + oct_rzqin : in std_logic -- oct.rzqin + ); + +end entity top; + +architecture RTL of top is + constant debug_baud : natural := 460800; + constant F_CPU : natural := 50000000; + + -- WB config + constant masters : natural := 3; + constant slaves : natural := 2; + constant INTERCON_ID_SRAM : natural := 0; + constant INTERCON_ID_DDR3 : natural := 1; + constant INTERCON_ID_GPIO : natural := 2; + constant INTERCON_ID_UART : natural := 3; + constant INTERCON_ID_NS16550 : natural := 4; + + constant in_simulation : boolean := false + --pragma synthesis_off + or true +--pragma synthesis_on +; + constant in_synthesis : boolean := not in_simulation; + + signal clk : std_logic; + signal rst : std_logic; + signal interrupt : std_logic_vector(32 - 1 downto 0); + signal intercon_slave_i : wishbone_v3_slave_in_vector(slaves - 1 downto 0); + signal intercon_slave_o : wishbone_v3_slave_out_vector(slaves - 1 downto 0); + signal intercon_master_i : wishbone_v3_master_in_vector(masters - 1 downto 0); + signal intercon_master_o : wishbone_v3_master_out_vector(masters - 1 downto 0); + + signal pll_locked : std_logic; + signal rst_ddr3_n : std_logic; + signal debug_o : debug_interface_o; + signal debug_i : debug_interface_i; + signal traceport_exec_valid_o : std_logic; + signal traceport_exec_pc_o : std_logic_vector(31 downto 0); + signal traceport_exec_insn_o : std_logic_vector(OR1K_INSN_WIDTH - 1 downto 0); + signal traceport_exec_wbdata_o : std_logic_vector(OPTION_OPERAND_WIDTH - 1 downto 0); + signal traceport_exec_wbreg_o : std_logic_vector(OPTION_RF_ADDR_WIDTH - 1 downto 0); + signal traceport_exec_wben_o : std_logic; + signal mor1kx_rst : std_logic; + signal jinn_data_i : std_logic_vector(7 downto 0); + signal jinn_data_available : std_logic; + signal jinn_data_o : std_logic_vector(7 downto 0); + signal jinn_data_valid_o : std_logic; + signal jinn_uart_busy_i : std_logic; + + signal avl_ready_0 : std_logic; + signal avl_burstbegin_0 : std_logic; + signal avl_addr_0 : std_logic_vector(24 downto 0); + signal avl_rdata_valid_0 : std_logic; + signal avl_rdata_0 : std_logic_vector(31 downto 0); + signal avl_wdata_0 : std_logic_vector(31 downto 0); + signal avl_be_0 : std_logic_vector(3 downto 0); + signal avl_read_req_0 : std_logic; + signal avl_write_req_0 : std_logic; + signal avl_size_0 : std_logic_vector(2 downto 0); + + signal local_init_done : std_logic; -- status.local_init_done + signal local_cal_success : std_logic; -- .local_cal_success + signal local_cal_fail : std_logic; -- .local_cal_fail + + signal avl_reqEn : std_logic; + signal writeAck : std_logic; + signal readAck : std_logic; +begin + debug_i.addr <= (others => '0'); + debug_i.dat <= (others => '0'); + debug_i.stb <= '1'; + debug_i.we <= '0'; + + -- System controller + resetSync : process(clk, rst_hw) is + begin + if rst_hw = '0' then -- low active + rst <= '1'; + rst_ddr3_n <= '0'; + elsif rising_edge(clk) then + if pll_locked = '1' then + rst_ddr3_n <= '1'; -- Start DDR3 Controller + if local_init_done = '1' and local_cal_success = '1' then + rst <= '0'; -- Start system! + end if; + end if; + end if; + end process resetSync; + + -- Clock management + clk <= clk_hw; + pll_locked <= '1'; + + -- SRAM + sram_wb_inst : entity work.sram_wb + port map( + clk => clk, + rst => rst, + wb_in => intercon_slave_i(INTERCON_ID_SRAM), + wb_out => intercon_slave_o(INTERCON_ID_SRAM) + ); + + -- CPU + interrupt <= (others => '0'); + mor1kx_vhdl_inst : entity ip.mor1kx_vhdl + port map( + clk => clk, + rst => mor1kx_rst, + data_o => intercon_master_o(1), + data_i => intercon_master_i(1), + inst_o => intercon_master_o(0), + inst_i => intercon_master_i(0), + irq_i => interrupt, + debug_o => debug_o, + debug_i => debug_i, + traceport_exec_valid_o => traceport_exec_valid_o, + traceport_exec_pc_o => traceport_exec_pc_o, + traceport_exec_insn_o => traceport_exec_insn_o, + traceport_exec_wbdata_o => traceport_exec_wbdata_o, + traceport_exec_wbreg_o => traceport_exec_wbreg_o, + traceport_exec_wben_o => traceport_exec_wben_o + ); + + -- Debug interface + jinn_inst : entity work.jinn + port map( + clk_i => clk, + rst_i => rst, + master_i => intercon_master_i(2), + master_o => intercon_master_o(2), + cpu_stall => debug_i.stall, + cpu_reset => mor1kx_rst, + data_i => jinn_data_i, + data_available => jinn_data_available, + data_o => jinn_data_o, + data_valid_o => jinn_data_valid_o, + output_busy_i => jinn_uart_busy_i + ); + + uart_rx_inst : entity work.uart_rx + port map( + clk => clk, + rst => rst, + data => jinn_data_i, + byte_ready => jinn_data_available, + error => open, + ckDiv => std_logic_vector(to_unsigned(F_CPU / debug_baud - 1, 16)), + parityEnable => '0', + parityOdd => '0', + twoStopBits => '0', + rx => jinn_uart_rx + ); + + uart_tx_inst : entity work.uart_tx + port map( + clk => clk, + rst => rst, + data => jinn_data_o, + byte_ready => jinn_data_valid_o, + busy => jinn_uart_busy_i, + ckDiv => std_logic_vector(to_unsigned(F_CPU / debug_baud - 1, 16)), + parityEnable => '0', + parityOdd => '0', + twoStopBits => '0', + tx => jinn_uart_tx + ); + + -- DDR3 RAM + ddr3_inst : entity ddr3.ddr3 + port map( + pll_ref_clk => clk, + global_reset_n => rst_hw, + soft_reset_n => '1', + afi_clk => open, + afi_half_clk => open, + afi_reset_n => open, + afi_reset_export_n => open, + mem_a => mem_a, + mem_ba => mem_ba, + mem_ck => mem_ck, + mem_ck_n => mem_ck_n, + mem_cke => mem_cke, + mem_cs_n => mem_cs_n, + mem_dm => mem_dm, + mem_ras_n => mem_ras_n, + mem_cas_n => mem_cas_n, + mem_we_n => mem_we_n, + mem_reset_n => mem_reset_n, + mem_dq => mem_dq, + mem_dqs => mem_dqs, + mem_dqs_n => mem_dqs_n, + mem_odt => mem_odt, + avl_ready_0 => avl_ready_0, + avl_burstbegin_0 => avl_burstbegin_0, + avl_addr_0 => avl_addr_0, + avl_rdata_valid_0 => avl_rdata_valid_0, + avl_rdata_0 => avl_rdata_0, + avl_wdata_0 => avl_wdata_0, + avl_be_0 => avl_be_0, + avl_read_req_0 => avl_read_req_0, + avl_write_req_0 => avl_write_req_0, + avl_size_0 => avl_size_0, + mp_cmd_clk_0_clk => clk, + mp_cmd_reset_n_0_reset_n => rst_hw, + mp_rfifo_clk_0_clk => clk, + mp_rfifo_reset_n_0_reset_n => rst_hw, + mp_wfifo_clk_0_clk => clk, + mp_wfifo_reset_n_0_reset_n => rst_hw, + local_init_done => local_init_done, + local_cal_success => local_cal_success, + local_cal_fail => local_cal_fail, + oct_rzqin => oct_rzqin, + pll_mem_clk => open, + pll_write_clk => open, + pll_locked => open, + pll_write_clk_pre_phy_clk => open, + pll_addr_cmd_clk => open, + pll_avl_clk => open, + pll_config_clk => open, + pll_mem_phy_clk => open, + afi_phy_clk => open, + pll_avl_phy_clk => open, + csr_clk => clk, + csr_reset_n => rst_hw + ); + + avl_addr_0 <= intercon_slave_i(INTERCON_ID_DDR3).ADR(26 downto 2); -- & "00"; + avl_be_0 <= intercon_slave_i(INTERCON_ID_DDR3).SEL; + avl_burstbegin_0 <= '0'; + + avl_wdata_0 <= intercon_slave_i(INTERCON_ID_DDR3).DAT; + avl_read_req_0 <= (intercon_slave_i(INTERCON_ID_DDR3).STB and (not intercon_slave_i(INTERCON_ID_DDR3).WE)) and avl_reqEn; + avl_write_req_0 <= (intercon_slave_i(INTERCON_ID_DDR3).STB and intercon_slave_i(INTERCON_ID_DDR3).WE) and avl_reqEn; + avl_size_0 <= "001"; + + intercon_slave_o(INTERCON_ID_DDR3).DAT <= avl_rdata_0; + intercon_slave_o(INTERCON_ID_DDR3).ERR <= '0'; + intercon_slave_o(INTERCON_ID_DDR3).RTY <= '0'; + intercon_slave_o(INTERCON_ID_DDR3).ACK <= (readAck or writeAck) and intercon_slave_i(INTERCON_ID_DDR3).STB; + + readAck <= avl_rdata_valid_0; --(avl_rdata_valid_0 and not intercon_slave_i(INTERCON_ID_SRAM).WE); + writeAck <= (intercon_slave_i(INTERCON_ID_DDR3).WE and avl_ready_0); + + wb2avl : process(clk, rst) is + begin + if rst = '1' then + avl_reqEn <= '1'; + elsif rising_edge(clk) then + if intercon_slave_i(INTERCON_ID_DDR3).STB = '1' then + avl_reqEn <= '0'; + else + avl_reqEn <= '1'; + end if; + end if; + end process wb2avl; + + -- Intercon + crossbar_inst : entity ip.crossbar + generic map( + masters => masters, + slaves => slaves, + async => true + ) + port map( + clk => clk, + rst => rst, + slave_i => intercon_master_o, + slave_o => intercon_master_i, + master_i => intercon_slave_o, + master_o => intercon_slave_i, + address => (0 => x"00000000", -- SRAM + 1 => x"80000000" + ), + mask => (0 => x"ffff0000", + 1 => x"f0000000" + ) + ); +end architecture RTL; diff --git a/devicemodels/atmel_flash_user_guide_with_rapids.doc b/devicemodels/atmel_flash_user_guide_with_rapids.doc new file mode 100644 index 0000000..67aa9c7 Binary files /dev/null and b/devicemodels/atmel_flash_user_guide_with_rapids.doc differ diff --git a/devicemodels/dataflash2.1.vhd b/devicemodels/dataflash2.1.vhd new file mode 100644 index 0000000..3ffd32f --- /dev/null +++ b/devicemodels/dataflash2.1.vhd @@ -0,0 +1,3780 @@ +------------------------------------------------------------------------------- +-- This is the property of PERFTRENDS TECHNOLOGIES PRIVATE LIMITED and +-- possession or use of file has to be with the written LICENCE AGGREMENT +-- from PERFTRENDS TECHNOLOGIES PRIVATE LIMITED. +-- +------------------------------------------------------------------------------- +-- +-- Project : Atmel DataFlash model +------------------------------------------------------------------------------- +-- File : $RCSfile: DataFlash2.1.vhd,v $ +-- Path : $Source: /home/cvs/atmel_flash_dev/design/DataFlash2.1.vhd,v $ +-- Author : E.MAGESH +-- Created on : 20-06-06 +-- Revision : $Revision: 1.1 $ +-- Last modified by : $Author: magesh $ +-- Last modified on : $Date: 2006/07/19 13:54:54 $ +------------------------------------------------------------------------------- +-- Module : FlashMemory +-- Description : +-- +-- +------------------------------------------------------------------------------- +-- +-- Design hierarchy : +-- Instantiated Modules : +------------------------------------------------------------------------------- +-- Revision history : +-- $Log: DataFlash2.1.vhd,v $ +-- Revision 1.1 2006/07/19 13:54:54 magesh +-- *** empty log message *** +-- +-- Revision 1.5 2006/06/29 12:34:49 magesh +-- *** empty log message *** +-- +-- Revision 1.4 2006/06/27 12:05:42 magesh +-- *** empty log message *** +-- +-- Revision 1.3 2006/06/21 14:24:03 magesh +-- *** empty log message *** +-- +-- Revision 1.2 2006/06/20 13:34:01 magesh +-- *** empty log message *** +-- +------------------------------------------------------------------------------- + + +library std; + use std.textio.all; +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_textio.all; + use ieee.std_logic_arith.all; + use IEEE.Std_logic_unsigned.all; + use IEEE.numeric_std.all; +---entity declarations-------------- +entity DataFlash is +generic ( + flashmemory : string := "memory.txt"; + Rapid_interface : boolean := true ; + fsck : integer := 66; + DEVICE : string(1 to 10) :="AT45DB011D"; + Tsck : Time := 13.6 ns); +port( + SI : in std_logic; -- Data SPI + CSB : in std_logic; -- Chip Select SPI + SCK : in std_logic; -- Clock SPI + WPB : in std_logic; -- Hard Ware Page Write protecteds Pin + RESETB : in std_logic; -- Reset Pin + SO : out std_logic; -- Serial Output + RDYBSY : out std_logic -- Ready Busy pin + ); +end DataFlash ; + + + +----architecture declarations------ +architecture design of DataFlash is +constant t_buffer : integer := 2; +signal binary_page : std_logic := '0'; +signal status2 : std_logic :='1'; +signal status3 : std_logic ; +signal status4 : std_logic ; +signal status5 : std_logic ; + +constant TFP : TIME := 14000000 ns; +constant TCE : TIME := 400000000 ns; -- TBD Spec. time is 5s +constant TVCSL : TIME := 30000 ns; -- ?? +constant TPUW : TIME := 10000000 ns; -- ?? + +---- Input Times check +constant Tcar1 : Time := Tsck ; +constant Tcar2 : Time := 30 ns ; -- 33 Mhz operation + +constant Twh : TIME := Tsck/2 ; -- SCK High Time +constant Twl : TIME := Tsck/2 ; -- SCK Low Time +constant Tcs : TIME := 50 ns ; -- Minimum CS! High Time +constant Tcss : TIME := 5 ns ; -- CS! setup Time +constant Tcsh : TIME := 5 ns ; -- CS! Hold Time +constant Tcsb : TIME := 100 ns ; -- Max +constant Tsu : TIME := 2 ns ; -- Data in Setup Time +constant Th : TIME := 3 ns ; -- Data in Hold Time + +---- Outup delay +constant Tho : TIME := 0 ns ; -- Output Hold Time +constant Tdis : TIME := 8 ns ; -- Output Disable Time +constant Tv : TIME := 8 ns ; -- Output Valid +constant Twpe : TIME := 1 ns ; -- +constant Twpd : TIME := 1 ns ; -- +constant Tedpd : TIME := 3 us; +constant Trdpd : TIME := 30 us; + +---- Processing Time +constant Txfr : TIME := 400 us ; -- Page to Buffer Transfer_Compare Time +constant Tcomp : TIME := 400 us; +constant Tep : TIME := 40 ms ; -- Page Erase and Programming Time +constant Tp : TIME := 6 ms; -- Page Programming Time +constant Tpe : TIME := 35 ms; +constant Tbe : TIME := 100 ms; +constant Tse : TIME := 5000 ms; -- Spec. time is 5s +constant Trst : TIME := 10 us ; -- Reset Pulse Width +constant Trec : TIME := 1 us; -- Reset Recovery Time + +------------------------------------------------ +signal TsckRp , TsckRw , TsckF , TcsR , TcsF , Tsckm , Tsim , TsckRh : time := 0 ns ; + +------------- global signal declarations--------- + +-----opcode enable signal--------- + + +signal MMCAR : std_logic; +constant binary_opt : std_logic :='1' ; +signal buffer2read : std_logic; +signal MMPTB1T : std_logic; +signal MMPTB2T : std_logic; +signal MMPTB1C : std_logic; +signal MMPTB2C : std_logic; +signal B1W : std_logic; +signal B2W : std_logic; +signal B1TMMPPWBIE : std_logic; +signal B2TMMPPWBIE : std_logic; +signal B1TMMPPWOBIE : std_logic; +signal B2TMMPPWOBIE : std_logic; +signal PE : std_logic; +signal BE : std_logic; +signal SE : std_logic; + +signal CE : std_logic; +signal MMPPB1 : std_logic; +signal MMPPB2 : std_logic; +signal APRB1 : std_logic; +signal APRB2 : std_logic; + +signal OP3D : std_logic; +signal BPS : std_logic; +signal PRE : std_logic; +signal PRP : std_logic; +signal LRP : std_logic; +signal SPE : std_logic; +signal SPD : std_logic; +signal PRR : std_logic; +signal LRR : std_logic; +signal OP9B : std_logic; +signal SRP : std_logic; + +signal security_flag : std_logic:='0'; +signal soft_prot_enabled : std_logic :='0'; +signal tmp_reg1 : std_logic_vector(7 downto 0); +signal tmp_reg2 : std_logic_vector(7 downto 0); + +signal less_than_33mhz : std_logic; +--signal less_than_20Mhz : std_logic; +signal locked : std_logic; +signal protecteds: std_logic; + +signal protection : bit_vector(511 downto 0) := (others=>'1'); +signal lockdown : bit_vector(511 downto 0) := (others=>'0'); +signal security : bit_vector(511 downto 0) := (others=>'1'); +signal factory : bit_vector(511 downto 0) := (others=>'1'); + + +function device_Sel1 (DEVICE : in string(1 to 10) + ) return std_logic is + variable status3 : std_logic; +begin +if (DEVICE="AT45DB041D")then + status3 := '1'; + + elsif(DEVICE="AT45DB081D") then + status3 := '0'; + + + elsif(DEVICE="AT45DB161D") then + status3 := '1' ; + + elsif(DEVICE="AT45DB321D") then + status3 := '0'; + + elsif(DEVICE="AT45DB642D") then + status3 := '1'; + + elsif(DEVICE="AT45DB011D") then + status3 := '1'; + + elsif(DEVICE="AT45DB021D") then + status3 :='1'; + + else + status3 := '1'; + + end if; + +return status3; + +end device_sel1; + + + +function device_Sel2 (DEVICE : in string(1 to 10) + ) return std_logic is + variable status4 : std_logic; +begin +if (DEVICE="AT45DB041D")then + + status4 := '1'; + + elsif(DEVICE="AT45DB081D") then + + status4 := '0'; + + + elsif(DEVICE="AT45DB161D") then + + status4 := '0' ; + + elsif(DEVICE="AT45DB321D") then + + status4 := '1'; + + elsif(DEVICE="AT45DB642D") then + + status4 := '1'; + + elsif(DEVICE="AT45DB011D") then + + status4 := '0'; + + elsif(DEVICE="AT45DB021D") then + + status4 :='1'; + + else + + status4 := '1'; + + end if; + +return status4; + +end device_sel2; + + +function device_Sel3 (DEVICE : in string(1 to 10) + ) return std_logic is + variable status5 : std_logic; +begin + +if (DEVICE="AT45DB041D")then + + status5 := '0'; + elsif(DEVICE="AT45DB081D") then + + status5 := '1'; + + elsif(DEVICE="AT45DB161D") then + + status5 := '1' ; + elsif(DEVICE="AT45DB321D") then + + status5 := '1'; + elsif(DEVICE="AT45DB642D") then + + status5 := '1'; + elsif(DEVICE="AT45DB011D") then + + status5 := '0'; + elsif(DEVICE="AT45DB021D") then + + status5 :='0'; + else + + status5 := '0'; + end if; +return status5; + +end device_sel3; + + + + + + + +function page_cal (DEVICE : in string(1 to 10) + ) return integer is + variable pages : integer range 1 to 8192 := 2048; +begin + case DEVICE is + when "AT45DB041D" => + pages := 2048; + when "AT45DB081D" => + pages := 4096; + when "AT45DB161D" => + pages := 4096; + when "AT45DB321D" => + pages := 8192; + when "AT45DB642D" => + pages := 8192; + when "AT45DB011D" => + pages := 512; + when "AT45DB021D" => + pages := 1024; + when OTHERS => + pages := 2048; + end case; + + return pages; + +end page_cal; + + + +function pageper_sector (DEVICE : in string(1 to 10) + ) return integer is + variable page_per_sector : integer range 1 to 256 :=256; + +begin + + + case DEVICE is + when "AT45DB041D" => + page_per_sector := 256; + when "AT45DB081D" => + page_per_sector := 256; + when "AT45DB161D" => + page_per_sector := 256; + when "AT45DB321D" => + page_per_sector := 128; + when "AT45DB642D" => + page_per_sector := 256; + when "AT45DB011D" => + page_per_sector := 128; + when "AT45DB021D" => + page_per_sector := 128; + when OTHERS => + page_per_sector := 256; + end case; + + return page_per_sector; + + +end pageper_sector; + + +function sec_tors (DEVICE : in string(1 to 10) + ) return integer is + variable sectors : integer range 1 to 64 :=8; + + +begin + case DEVICE is + when "AT45DB041D" => + sectors := 8; + when "AT45DB081D" => + sectors := 16; + when "AT45DB161D" => + sectors := 16; + when "AT45DB321D" => + sectors := 64; + when "AT45DB642D" => + sectors := 32; + when "AT45DB011D" => + sectors := 4; + when "AT45DB021D" => + sectors := 8; + when OTHERS => + sectors := 8; + end case; + + return sectors; + + end sec_tors; + +function pagesize_forbuffer (DEVICE : in string(1 to 10) + ) return integer is + variable page_size : integer range 1 to 1056 :=264; + + +begin +case DEVICE is + when "AT45DB041D" => + page_size := 264; + when "AT45DB081D" => + page_size := 264; + when "AT45DB161D" => + page_size := 528; + when "AT45DB321D" => + page_size := 528; + when "AT45DB642D" => + page_size := 1056; + when "AT45DB011D" => + page_size := 264; + when "AT45DB021D" => + page_size := 264; + when OTHERS => + page_size:= 264; + end case; + + return page_size; + + end pagesize_forbuffer; + + +function pagesize (DEVICE : in string(1 to 10); + signal binary_page : in std_logic + ) return integer is + variable page_size : integer range 1 to 1056 :=264; + + +begin +case DEVICE is + when "AT45DB041D" => + page_size := (264 - (conv_integer(BINARY_page) * 8)); + when "AT45DB081D" => + page_size := (264 -(conv_integer(BINARY_page) * 8)); + when "AT45DB161D" => + page_size := (528 -(conv_integer(BINARY_page) * 16)); + when "AT45DB321D" => + page_size := (528 - (conv_integer(BINARY_page) * 16)); + when "AT45DB642D" => + page_size := (1056 - (conv_integer(BINARY_page) * 32)); + when "AT45DB011D" => + + page_size := (264 - (conv_integer(BINARY_page) * 8)); + when "AT45DB021D" => + + page_size := (264 - (conv_integer(BINARY_page) * 8)); + when OTHERS => + + page_size:= (264 - (conv_integer(BINARY_page) * 8)); + end case; + + return page_size; + + end pagesize; + + + + +function memsize (page_size : in integer range 1 to 1056; + pages : in integer range 1 to 8192 + ) return integer is +variable mem_size : integer range 1 to 69206016; +begin + + mem_size := page_size * pages; + return mem_size; + +end memsize; + + + + + + +function b_address (DEVICE : in string(1 to 10); + signal binary_page : in std_logic + ) return integer is +variable baddress : integer range 1 to 11 := 9; +begin + + case DEVICE is + when "AT45DB041D" => + baddress := (9 - (conv_integer(BINARY_page) * 1)); + when "AT45DB081D" => + baddress := (9 -(conv_integer(BINARY_page) * 1)); + when "AT45DB161D" => + baddress := (10 -(conv_integer(BINARY_page) * 1)); + when "AT45DB321D" => + baddress:= (10 - (conv_integer(BINARY_page) * 1)); + when "AT45DB642D" => + baddress := (11 - (conv_integer(BINARY_page) * 1)); + when "AT45DB011D" => + baddress := (9 - (conv_integer(BINARY_page) * 1)); + when "AT45DB021D" => + baddress := (9 - (conv_integer(BINARY_page) * 1)); + when OTHERS => + baddress:= (9 - (conv_integer(BINARY_page) * 1)); + end case; + + return baddress; + + + +end b_address; + + + + + +function p_address (DEVICE : in string(1 to 10) + ) return integer is +variable paddress : integer range 1 to 14 := 11; +begin + + case DEVICE is + when "AT45DB041D" => + paddress := 11; + when "AT45DB081D" => + paddress := 12; + when "AT45DB161D" => + paddress := 12; + when "AT45DB321D" => + paddress := 13; + when "AT45DB642D" => + paddress := 13; + when "AT45DB011D" => + paddress := 9; + when "AT45DB021D" => + paddress := 10; + when OTHERS => + paddress := 11; + end case; + + return paddress; + + + +end p_address; + + +function s_address (DEVICE : in string(1 to 10) + ) return integer is +variable saddress : integer range 1 to 6 := 3; +begin + + case DEVICE is + when "AT45DB041D" => + saddress := 3; + when "AT45DB081D" => + saddress := 4; + when "AT45DB161D" => + saddress := 4; + when "AT45DB321D" => + saddress := 6; + when "AT45DB642D" => + saddress := 5; + when "AT45DB011D" => + saddress := 2; + when "AT45DB021D" => + saddress := 3; + when OTHERS => + saddress := 3; + end case; + + return saddress; + + + +end s_address; + + +function manid (DEVICE : in string(1 to 10) + ) return std_logic_vector is +variable man_id : std_logic_vector(31 downto 0); +begin + +case DEVICE is + when "AT45DB041D" => + man_id := X"1F_24_00_00"; + when "AT45DB081D" => + man_id := X"1F_25_00_00"; + when "AT45DB161D" => + man_id := X"1F_26_00_00"; + when "AT45DB321D" => + man_id := X"1F_27_00_00"; + when "AT45DB642D" => + man_id := X"1F_28_00_00"; + when "AT45DB011D" => + man_id := X"1F_22_00_00"; + when "AT45DB021D" => + man_id := X"1F_23_00_00"; + when OTHERS => + man_id := X"1F_24_01_00"; + end case; + + return man_id; + + +end manid; +--------------timing task implementation-------- + +procedure checkSetupCS( + signal CsSignal : in std_logic; + CsSignalName : in string; + signal TriggerSignal : in std_logic; + TriggerSignalName : in string; + ExpectedDelay : in time; + ExpectedDelayName : in string; + signal LastCsFall : inout time; + FullPathName : in string; + CheckEnabled : in boolean + ) is + + variable ln : Line; +begin + if ( CsSignal'event and CsSignal = '0' ) then + LastCsFall <= now; + end if ; + + if TriggerSignal'event and (now - LastCsFall < ExpectedDelay ) and + (now > 0 ns) and (expectedDelay /= 0 ns) and ( lastCsFall /= 0 ns ) + and checkEnabled then + write(ln, string'("Error on ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(CsSignalName)); + write(ln, string'("' to '")); + write(ln, string'(TriggerSignalName)); + write(ln, string'("' Setup violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(ExpectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(ExpectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - LastCsFall ); + + writeline(output, ln); + end if; + + +end checkSetupCs ; + +-------------------------------------------------------------------------- +-- CsSignal __________/-------- +-- TriggerSignal ======x============ +-- <---> + + procedure checkHoldCS( + signal CsSignal : in std_logic; + CsSignalName : in string; + signal TriggerSignal : in std_logic; + TriggerSignalName : in string; + ExpectedDelay : in time; + ExpectedDelayName : in string; + signal LastTriggerEdge : inout time ; + FullPathName : in string ; + CheckEnabled : in boolean + ) is + +variable ln : Line; +begin + if triggerSignal'event then + LastTriggerEdge <= now ; + end if; + + if CsSignal'event and CsSignal = '1' and ( now - LastTriggerEdge < ExpectedDelay) and + (now > 0 ns) and (expectedDelay /= 0 ns) and ( LastTriggerEdge /= 0 ns ) + and checkEnabled then + write(ln, string'("Error on ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(CsSignalName)); + write(ln, string'("' to '")); + write(ln, string'(triggerSignalName)); + write(ln, string'("' Hold violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - LastTriggerEdge); + + writeline(output, ln); + end if; + + +end checkHoldCs; + + +----------------------------------------------------------------------- +-- Trigger ___________/--------- +-- Reference =====x=============== +-- <-----> + + procedure checkSetupRise( + signal ReferenceSignal : in std_logic; + ReferenceSignalName : in string; + signal TriggerSignal : in std_logic; + TriggerSignalName : in string; + ExpectedDelay : in time; + ExpectedDelayName : in string; + signal LastReferenceMove : inout time; + FullPathName : in string ; + CheckEnabled : in boolean + ) is + + variable ln : Line; + +begin + if referenceSignal'Event then + LastReferenceMove <= now ; + end if; + + + if triggerSignal'event and triggerSignal = '1' and + ( now - LastReferenceMove < expectedDelay) and + (now > 0 ns) and (expectedDelay /= 0 ns) and ( LastReferenceMove /= 0 ns ) + and checkEnabled then + write(ln, string'("Error on ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(referenceSignalName)); + write(ln, string'("' to '")); + write(ln, string'(triggerSignalName)); + write(ln, string'("' Setup violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - LastReferenceMove); + + writeline(output, ln); + + end if; + + +end checkSetupRise; + + +----------------------------------------------------------------- +-- Trigger __________/---------- +-- Reference ================x==== +-- <-----> + + + procedure checkHoldRise( + signal ReferenceSignal : in std_logic; + ReferenceSignalName : in string; + signal TriggerSignal : in std_logic; + TriggerSignalName : in string; + ExpectedDelay : in time; + ExpectedDelayName : in string; + signal LastTriggerRise : inout time; + FullPathName : in string ; + CheckEnabled : in boolean + ) is + variable ln : Line; +begin + if TriggerSignal'event and TriggerSignal = '1' then + LastTriggerRise <= now ; + end if; + if ReferenceSignal'event and ( now - LastTriggerRise < expectedDelay) and + (now > 0 ns) and (expectedDelay /= 0 ns) and ( LastTriggerRise /= 0 ns ) + and checkEnabled then + write(ln, string'("Error on ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(referenceSignalName)); + write(ln, string'("' to '")); + write(ln, string'(triggerSignalName)); + write(ln, string'("' Hold violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - LastTriggerRise); + + writeline(output, ln); + end if; + + +end checkHoldRise; + + +------------------------------------------------------------------------------ +-- Signal ____/------\_______/---- +-- <--------------> + + procedure checkPeriod( + signal TestSignal : in std_logic; + TestSignalName : in string; + expectedDelay : in time; + expectedDelayName : in string; + signal LastSignalRise : inout time; + fullPathName : in string; + checkEnabled : in boolean + ) is + variable ln : Line; +begin + +if (TestSignal'event and TestSignal = '1') then + if (now - lastSignalRise < expectedDelay) and ( lastSignalRise /= 0 ns ) and + (now > 0 ns) and (expectedDelay /= 0 ns) and checkEnabled then + write(ln, string'("Error on ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(TestSignalName)); + write(ln, string'("' Periode violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - lastSignalRise); + + writeline(output, ln); + end if; + + +LastSignalRise <= now; +end if; + + +end checkPeriod; + +---------------------------------------------------------------------- +-- Signal ____/---------\____ +-- <---------> + + + procedure checkWidth1( + signal TestSignal : in std_logic; + TestSignalName : in string; + ExpectedDelay : in time; + ExpectedDelayName : in string; + signal LastSignalRise : inout time ; + FullPathName : in string ; + CheckEnabled : in boolean + ) is + variable ln : Line; +begin + + if (TestSignal'event and TestSignal = '1') then + LastSignalRise <= now; + end if; + + if (TestSignal'event and TestSignal = '0') and + (now - lastSignalRise < expectedDelay) and + (now > 0 ns) and (expectedDelay /= 0 ns) and ( lastSignalRise /= 0 ns ) + and checkEnabled then + write(ln, string'("Error on ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(TestSignalName)); + write(ln, string'("' Pulse Width violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - lastSignalRise); + + writeline(output, ln); + end if; + + +end checkWidth1; + +---------------------------------------------------------------------- +-- Signal ----\_________/----- +-- <---------> + + procedure checkWidth0( + signal TestSignal : in std_logic; + TestSignalName : in string; + ExpectedDelay : in time; + ExpectedDelayName : in string; + signal LastSignalFall : inout time ; + fullPathName : in string ; + checkEnabled : in boolean + ) is + variable ln : Line; +begin + if (TestSignal'event and TestSignal = '0') then + lastSignalFall <= now; + end if; + + if (TestSignal'event and TestSignal = '1') and + (now - lastSignalFall < expectedDelay) and ( lastSignalFall /= 0 ns ) and + (now > 0 ns) and (expectedDelay /= 0 ns) and checkEnabled then + write(ln, string'("Error on ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(TestSignalName)); + write(ln, string'("' Pulse Width violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - lastSignalFall); + + writeline(output, ln); + end if; + +end checkWidth0; +------------------------------------------------------------------- +------------------------------------------------------------------- +------------------------------------------------------------------- + FUNCTION integer_to_bit_vector (VAL, width : INTEGER) RETURN BIT_VECTOR IS + VARIABLE result : BIT_VECTOR (width-1 downto 0) := (OTHERS=>'0'); + VARIABLE bits : INTEGER := width; + BEGIN + IF (bits > 31) THEN -- Avoid overflow errors. + bits := 31; + ELSE + ASSERT 2**bits > VAL REPORT + "Value too big FOR BIT_VECTOR width" + SEVERITY WARNING; + END IF; + + FOR i IN 0 TO bits - 1 LOOP + IF ((val/(2**i)) MOD 2 = 1) THEN + result(i) := '1'; + END IF; + + END LOOP; + + RETURN (result); + END integer_to_bit_vector ; + PROCEDURE removespace(VARIABLE l : IN line; pos : OUT integer) IS + BEGIN + pos := l'low; + FOR i IN l'low TO l'high LOOP + CASE l(i) IS + WHEN ' ' | ht => + pos := i + 1; + WHEN OTHERS => + EXIT; + END CASE; + END LOOP; + END; + PROCEDURE removeline(l : INOUT line; pos : integer) IS + VARIABLE tmpl : line; + BEGIN + tmpl := l; + l := NEW string'(tmpl(pos TO tmpl'high)); + deallocate(tmpl); + END; + PROCEDURE hexa_to_bit_vector(l: INOUT line; u: in integer; value: OUT bit_vector) IS + CONSTANT not_digit : integer := -999; + FUNCTION digit_value(c : character) RETURN integer IS + BEGIN + IF (c >= '0') AND (c <= '9') THEN + RETURN (character'pos(c) - character'pos('0')); + ELSIF (c >= 'a') AND (c <= 'f') THEN + RETURN (character'pos(c) - character'pos('a') + 10); + ELSIF (c >= 'A') AND (c <= 'F') THEN + RETURN (character'pos(c) - character'pos('A') + 10); + ELSE + RETURN not_digit; + END IF; + END; + VARIABLE digit : bit_vector(4 downto 1); + VARIABLE digit1 : bit_vector(u downto 1); + VARIABLE digitx : integer; + VARIABLE pos : integer; + VARIABLE t : integer := u/4; + BEGIN + removespace(l, pos); + FOR i IN pos TO l'right LOOP + digitx := digit_value(l(i)); + EXIT WHEN (digitx = not_digit) OR (digitx >= 16); + digit := integer_to_bit_vector(digitx,4); + if t >= 1 then + digit1 := digit1(u-4 downto 1) & digit; + t := t - 1; + else + end if; + pos := i + 1; + END LOOP; + value := digit1; + removeline(l, pos); + END; + +--******************************************--- +--******************************************-- + +signal page_status : std_logic_vector(page_cal(device)-1 downto 0); +signal temp_page_status : std_logic; +signal page : std_logic_vector(p_address(device)-1 downto 0); +signal temp_reg2 : std_logic_vector(7 downto 0); + +signal temp_page : std_logic_vector(p_address(device)-1 downto 0); + +signal byte : std_logic_vector(b_address(device,binary_page)-1 downto 0); + +---protecteds/locked status reg----- +signal prot_status : std_logic_vector(sec_tors(device) downto 0); +signal sector : std_logic_vector(s_address(device)-1 downto 0); + +type buffer1 is array(pagesize_forbuffer(device)-1 downto 0) of bit_vector(7 downto 0); +signal tbuffer1 : buffer1; + +type buffer2 is array(pagesize_forbuffer(device)-1 downto 0) of bit_vector(7 downto 0); +signal tbuffer2 : buffer2; + +--memory initalization-- +constant N : integer range 1 to 69206016 := memsize(pagesize_forbuffer(device),page_cal(DEVICE)); +constant M : integer := 8; + +type memtype is array(N-1 downto 0) of bit_vector(7 downto 0); +signal memory : memtype; + +--protection initialization--- +constant p : integer := sec_tors(device); +type prot_type is array(p-1 downto 0) of bit_vector(7 downto 0); +signal prot_reg : prot_type; + +--lock initialization-- +type lock_type is array(p-1 downto 0) of bit_vector(7 downto 0); +signal lock_reg : lock_type; + +--factory security --- +type factory_type is array(63 downto 0 ) of bit_vector(7 downto 0); +signal factory_reg : factory_type; + +--security reg-- +type security_type is array(63 downto 0) of bit_vector(7 downto 0); +signal security_reg : security_type; +--in security register 0 to 63 byte one time user programmable +---64 to 127 byte factory programmable by atmel-- + + +----------------------op3d------ +signal op3d_tmp_reg : std_logic_vector(7 downto 0):= "00000000"; +----------------------opc7------ +signal opc7_tmp_reg : std_logic_vector(7 downto 0):= "00000000"; +----------------------MMPPB1----------- +signal MMPPB1_temp_page : std_logic_vector(p_address(device)-1 downto 0); +signal MMPPB1_page : std_logic_vector(p_address(device)-1 downto 0); +signal MMPPB1_byte : std_logic_vector(b_address(device,binary_page)-1 downto 0); +signal MMPPB1_tmp_reg : std_logic_vector(7 downto 0):= "00000000"; +signal MMPPB1_tmp_reg1 : std_logic_vector(7 downto 0):= "00000000"; +signal MMPPB1_tmp_reg2 : std_logic_vector(7 downto 0):= "00000000"; + + +----------------------MMPPB2----------- +signal MMPPB2_temp_page : std_logic_vector(p_address(device)-1 downto 0); +signal MMPPB2_page : std_logic_vector(p_address(device)-1 downto 0); +signal MMPPB2_byte : std_logic_vector(b_address(device,binary_page)-1 downto 0); +signal MMPPB2_tmp_reg1 : std_logic_vector(7 downto 0):= "00000000"; +signal MMPPB2_tmp_reg2 : std_logic_vector(7 downto 0):= "00000000"; + +--------------------- + + + +--------------comp page address function implementation--------------- +function comp_page_addr ( paddress : in integer range 1 to 14; + signal binary_page : in std_logic; + signal page_addr0 : in std_logic_vector( 7 downto 0); + signal page_addr1 : in std_logic_vector( 7 downto 0); + man_id : in std_logic_vector(31 downto 0) + ) return std_logic_vector is +variable page1 : std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0); +begin + + + case(PADDRESS) is + --when 14 => + --if(binary_page='1') then + --page := (page_addr0(7 downto 0)) & (page_addr1(7 downto 2)); + --else --4 address bytes + --page := temp_reg2(0) & page_addr0(7 downto 0) & page_addr1(7 downto 2); + --end if; + when 13 => + --64mb-- + if(MAN_ID = X"1F280000")then + if(binary_page='1') then + page1 := page_addr0(6 downto 0) & page_addr1(7 downto 2); + else + page1 := page_addr0(7 downto 0) &page_addr1(7 downto 3); + end if; + end if; + --32 mb-- + if (MAN_ID = X"1F270100") then + if (binary_page = '1') then + page1 := page_addr0(5 downto 0) & page_addr1(7 downto 1); + else + page1 := page_addr0(6 downto 0) & page_addr1(7 downto 2); + end if; + end if; + when 12=> + ---16mb---- + if (MAN_ID = X"1F260000") then + if (binary_page = '1') then + page1 := page_addr0(4 downto 0) & page_addr1(7 downto 1); + else + page1 := page_addr0(5 downto 0) & page_addr1(7 downto 2); + end if; + end if; + --8mb-- + if (MAN_ID = X"1F250000") then + if (binary_page = '1') then + page1 := page_addr0(3 downto 0) & page_addr1(7 downto 0); + else + page1 := page_addr0(4 downto 0) & page_addr1(7 downto 1); + end if; + end if; + ---4 mb--- + when 11=> + if (binary_page = '1') then + page1 := page_addr0(2 downto 0) & page_addr1(7 downto 0); + else + page1 := page_addr0(3 downto 0) & page_addr1(7 downto 1); + end if; + --2mb--- + when 10=> + if (binary_page = '1') then + page1 :=page_addr0(1 downto 0) & page_addr1(7 downto 0); + else + page1 :=page_addr0(2 downto 0) & page_addr1(7 downto 1); + end if; + --1mb--- + when 9 => + if (binary_page ='1') then + page1 := page_addr0(0) & page_addr1(7 downto 0); + else + page1 := page_addr0(1 downto 0) & page_addr1(7 downto 1); + end if; + + when others => + + end case; + + return page1; +end comp_page_addr; + +----------------function compute_sector addr------- + +function comp_sector_addr ( paddress : in integer range 1 to 14; + page1 : in std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0) + --signal sector : in std_logic_vector((S_ADDRESS(device))-1 DOWNTO 0); + ) return std_logic_vector is +variable sector1 : std_logic_vector((S_ADDRESS(device))-1 DOWNTO 0); +begin + + +sector1 := page1(P_ADDRESS(device)-1 downto P_ADDRESS(device)-S_ADDRESS(device)); + +return sector1; +end comp_sector_addr; + +procedure compute_sector_address + ( + paddress : in integer range 1 to 14; + signal page : in std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0); + signal sector : out std_logic_vector((S_ADDRESS(device))-1 downto 0) + ) is +begin +sector <= page(P_ADDRESS(device)-1 downto P_ADDRESS(device)-S_ADDRESS(device)); + +end compute_sector_address; + + +---------------------------- +function comp_byte_addr + (baddress : integer range 1 to 11 ; + signal page_addr1 : in std_logic_vector( 7 downto 0); + signal byte_addr : in std_logic_vector( 7 downto 0); + signal binary_page : in std_logic + ) return std_logic_vector is +variable byte : std_logic_vector((b_address(device,binary_page))-1 DOWNTO 0); +begin + report " entered into comp_byte_addr" ; + case(baddress)is + when 11 => + byte := page_addr1(2 downto 0) & byte_addr ; --b"00000000" ; + when 10 => + byte := page_addr1(1 downto 0) & byte_addr ; --b"00000000" ; + when 9 => + + byte := page_addr1(0) & byte_addr ; --b"00000000" ; + when others=> + + byte :=byte_addr ; + end case; + + return byte; +end comp_byte_addr; + + + + + + + + + + + +procedure compute_address + ( page : in std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0); + page_size : in integer range 1 to 1056; + byte : in std_logic_vector((b_address(device,binary_page))-1 DOWNTO 0); + page_boundary_low : out integer; + page_boundary_high : out integer; + current_address : out integer; + mem_no : out integer; + signal binary_page : in std_logic + ) is + + variable temp_low : integer ; +begin + report "entered into compute_address"; + + temp_low := (conv_integer(page) * pagesize(device,binary_page)); + page_boundary_low := temp_low; + page_boundary_high := temp_low + (pagesize(device,binary_page) - 1); + report "entered into byte"; + current_address := temp_low + conv_integer(byte); + --memno 10 is for memory access--- + mem_no := 10; + +end compute_address; + + + + +procedure read_out + (signal SCK,CSB : in std_logic; + page_boundary_low : in integer; + page_boundary_high :in integer; + current_address : inout integer; + mem_no : in integer; + signal buf1 : in buffer1; + signal buf2 : in buffer2; + signal memory : in memtype; + --signal temp_reg1 :inout std_logic_vector(7 downto 0); + signal so_reg : out std_logic; + signal so_on1 : out std_logic + ) + is +variable t_reg : std_logic_vector(7 downto 0); +begin + + report " Read loop entered "; +if(mem_no=1)then + t_reg := to_stdlogicvector(buf1(current_address)); +elsif(mem_no=2)then + t_reg := to_stdlogicvector(buf2(current_address)); +elsif(mem_no=10)then + t_reg := to_stdlogicvector(memory(current_address)); +else +end if; + +read_loop : loop + for i in 7 downto 0 loop + wait until (SCK'EVENT and SCK ='0') or (CSB'EVENT and CSB='1'); + report " entered into for loop of read_out"; + exit read_loop when (CSB='1' ) ; + wait for Tv; + SO_reg <= t_reg(i); + so_on1 <= '1'; + end loop; + + current_address := current_address + 1; + report "comes out from for loop of read_out--------------------"; + if(current_address > page_boundary_high) then + current_address := page_boundary_low; + end if; + if(mem_no = 1)then + t_reg := to_stdlogicvector(buf1(current_address)); + elsif (mem_no = 2) then + t_reg := to_stdlogicvector(buf2(current_address)); + elsif (mem_no = 10) then + t_reg := to_stdlogicvector(memory(current_address)); + end if; +end loop; + wait for Tdis; + SO_reg <= '0'; + so_on1 <= '0'; + +report " Read loop exited"; +end read_out; + + +procedure read_out_x + (signal CSB,sck : in std_logic; + signal so_reg,so_on1 : out std_logic + ) is +begin +report " Readx loop entered "; +so_on1 <='0'; +read_loopx : loop + wait until (SCK'EVENT and SCK ='0') or (CSB'EVENT and CSB='1'); + exit read_loopx when (CSB='1' ) ; + wait for Tv; + SO_reg <= 'X'; + so_on1 <= '1'; +end loop; + wait for Tdis; + SO_reg <= '0'; + so_on1 <= '0'; + + report " Readx loop exited"; +end read_out_x; + + +procedure read_out_array + (signal SCK,CSB : in std_logic; + page_size : in integer range 1 to 1056; + mem_size : in integer range 1 to 69206016; + page_boundary_low : in integer; + page_boundary_high :in integer; + current_address : in integer; + signal memory : in memtype; + signal so_reg : out std_logic; + signal so_on1 : out std_logic + ) + is +variable t_reg_array : std_logic_vector(7 downto 0); +variable temp_high : integer; +variable temp_low : integer; +variable temp_add : integer; + + +begin + + report " Read_array loop entered "; + + temp_high := page_boundary_high; + temp_low := page_boundary_low; + temp_add := current_address; + + t_reg_array := to_stdlogicvector(memory(temp_add)); + + read_array_loop : loop + for i in 7 downto 0 loop + wait until (SCK'EVENT and SCK ='0') or (CSB'EVENT and CSB='1'); + exit read_array_loop when (CSB='1' ) ; + wait for Tv; + SO_reg <= t_reg_array(i); + so_on1 <= '1'; + end loop; + report"read_array procedure----------------------------------------------------"; + temp_add := temp_add + 1; + if (temp_add >= N)then + temp_add := 0; --Note that rollover occurs at end of memory, + temp_high := pagesize(device,binary_page) - 1; -- and not at the end of the page + temp_low := 0; + end if; + + if (temp_add > temp_high) then-- going to next page + temp_high := temp_high + pagesize(device,binary_page); + temp_low := temp_low + pagesize(device,binary_page); + end if; + t_reg_array := to_stdlogicvector(memory(temp_add)); +end loop; + wait for Tdis; + SO_reg <= '0'; + so_on1 <= '0'; + + report " Read_array loop exited "; +end read_out_array; + + + +procedure transfer_to_buffer + ( + buf_type : in integer; + page_boundary_low : in integer; + signal memory : in memtype; + signal buf1 : inout buffer1; + signal buf2 : inout buffer2 + ) is +begin + report " transfer to buffer entered "; +if (buf_type = 1) then + for i in 0 to pagesize(device,binary_page)-1 LOOP + buf1(i) <= memory(page_boundary_low + i); + end loop; + elsif (buf_type = 2) then + for i in 0 to pagesize(device,binary_page)-1 loop + buf2(i) <= memory(page_boundary_low + i); + end loop; + else + report"Int Error 2. This message should never appear"; + + +end if; + report " transfer to buffer exited "; +end transfer_to_buffer; + + + + + +procedure compare_with_buffer + ( buf_type : in integer; + page_boundary_low : in integer; + signal memory : in memtype; + signal buf1 : in buffer1; + signal buf2 : in buffer2; + signal status : out std_logic + ) is + +variable tmp1,tmp2 : bit_vector(7 downto 0); +begin + report " compare with buf entered "; +status <='0'; +if(buf_type = 1) then + for i in 0 to pagesize(device,binary_page)-1 loop + tmp1 := memory(page_boundary_low + i); + tmp2 := buf1(i); + for k in 0 to 7 loop + if(tmp1(k) /= tmp2(k)) then + status <= '1'; + exit; + end if; + end loop; + end loop; +elsif (buf_type = 2) then + + for i in 0 to pagesize(device,binary_page)-1 loop + tmp1 := memory(page_boundary_low + i); + tmp2 := buf2(i); + for k in 0 to 7 loop + if(tmp1(k) /= tmp2(k)) then + status <= '1'; + exit; + end if; + end loop; + end loop; +else + + report"Int error 3. This message should never appear"; + +end if; + report " compare with exited "; +end compare_with_buffer; + + + + +-----------write_data------------ +procedure write_data + ( current_address : inout integer; + page_boundary_low : in integer; + page_boundary_high : in integer; + signal buf1 : inout buffer1; + signal buf2 : inout buffer2; + buf_type : in integer; + signal CSB,SCK,SI : in std_logic + ) is + +variable buf_temp_reg : std_logic_vector(7 downto 0); +variable temp :std_logic := '0'; +begin + + report "first time entering " ; + + write_loop : loop + + if (CSB = '0') then + + for i in 7 downto 0 loop + wait until (SCK'EVENT and SCK ='1') or (CSB'EVENT and CSB='1'); + exit write_loop when (CSB='1' ) ; + buf_temp_reg(i):=SI; + end loop; + + + if (buf_type=1) then + buf1(current_address)<= To_bitvector(buf_temp_reg,'0'); + elsif(buf_type=2) then + buf2(current_address)<= To_bitvector(buf_temp_reg,'0'); + end if; + current_address := current_address + 1; + wait for 1 ps; + if (current_address > page_boundary_high) then + current_address := page_boundary_low; + wait for 1 ps; + end if; + end if; + +end loop; + + + report " loop exited"; + +end write_data; + +------------------check_protection------------- + + +function check_protect( + page1 : in std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0); + page_per_sector : in integer; + signal prot_status : in std_logic_vector(sec_tors(device) downto 0); + sector : in std_logic_vector(s_address(device)-1 downto 0); + WPB,soft_prot_enabled : in std_logic + ) return std_logic is + +variable protecteds : std_logic; +begin + protecteds := '0'; + + if ((WPB = '0') or (soft_prot_enabled ='1')) then + if (conv_integer(page1) < 8) then + protecteds := prot_status(0); + elsif (page1 < PAGE_PER_SECTOR) then + protecteds := prot_status(1); + else + protecteds := prot_status(conv_integer(sector) + 1); + end if; + end if; + + return protecteds; +end check_protect; + + + +--------------check lock down--------- + + +function check_lockd ( + page1 : in std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0); + page_per_sector : in integer; + signal lock_status : in std_logic_vector(sec_tors(device) downto 0); + sector : in std_logic_vector(s_address(device)-1 downto 0) + ) return std_logic is +variable locked : std_logic; +begin +locked :='0'; + + if (page1 < 8) then + locked := lock_status(0); + elsif (page1 < PAGE_PER_SECTOR) then + locked := lock_status(1); + else + locked := lock_status(conv_integer(sector)+1); + end if; +return locked; +end check_lockd; + + + +----------write_to_memory---------- + + +procedure write_to_memory + ( buf_type : in integer; + page : in std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0); + page_size : in integer range 1 to 1056; + signal buf1 : in buffer1; + signal buf2 : in buffer2; + + page_boundary_low : in integer; + signal memory : inout memtype + + ) is +begin + +report " write to memory entered "; +if (buf_type = 1) then + for i in 0 to page_size-1 loop + memory(page_boundary_low+i) <= buf1(i); + end loop; + elsif (buf_type = 2) then + for i in 0 to page_size-1 loop + memory(page_boundary_low+i) <= buf2(i); + end loop; +end if; + +report " write to memory exited "; +end write_to_memory; + + + + + + + + + +procedure erase_page + ( + page : in std_logic_vector((P_ADDRESS(device))-1 DOWNTO 0); + page_size : in integer range 1 to 1056; + page_boundary_low : in integer; + signal memory : inout memtype; + signal page_status : out std_logic + + ) is + +variable buf1 : buffer1; +variable buf2 : buffer2; +variable mem : memtype; + +begin +report " erase page entered "; +for i in 0 to pagesize(device,binary_page)-1 loop + memory(page_boundary_low + i ) <= (others=>'1'); + page_status <='0'; +end loop; +report " erase page exited "; +end erase_page; + + + +----------read_out_reg-------- +procedure read_out_reg + ( reg_type : in integer; + add : in integer; + high : in integer; + signal prot_reg : in prot_type ; + signal lock_reg : in lock_type ; + signal security_reg : in security_type ; + signal CSB,SCK : in std_logic; + signal so_reg : out std_logic; + signal so_on1 : out std_logic + + ) is +variable temp_add : integer; +variable t_reg1 : std_logic_vector(7 downto 0); +begin + report " Read out reg loop entered "; + temp_add := add; +if( reg_type= 21)then + t_reg1 := to_stdlogicvector(prot_reg(temp_add)); +elsif(reg_type= 22)then + t_reg1 := to_stdlogicvector(lock_reg(temp_add)); +elsif(reg_type= 23)then + t_reg1 := to_stdlogicvector(security_reg(temp_add)); +end if; + + +read_out_reg_loop : loop + for i in 7 downto 0 loop + wait until (SCK'EVENT and SCK ='0') or (CSB'EVENT and CSB='1'); + exit read_out_reg_loop when (CSB='1' ) ; + wait for Tv; + so_reg <= t_reg1(i); + so_on1 <= '1'; + end loop; + temp_add := temp_add + 1; + if ( temp_add > high)then + t_reg1 := (others => 'X' ); + else + if (reg_type=21) then + t_reg1 := to_stdlogicvector(prot_reg(temp_add)); + elsif (reg_type=22) then + t_reg1 := to_stdlogicvector(lock_reg(temp_add)); + elsif (reg_type=23) then + if (temp_add < 64) then + t_reg1 := to_stdlogicvector(security_reg(temp_add)); + else + t_reg1 := to_stdlogicvector(factory_reg(temp_add-64)); + end if; + end if; + end if; +end loop; + wait for Tdis; + so_reg <= '0'; + so_on1 <= '0'; + report " Read out reg loop exited "; +end read_out_reg; + + + +function getbyte ( + signal IP : in bit_vector(511 downto 0); + byte_num : in integer + ) return bit_vector is + +variable temp : bit_vector( 7 downto 0); +begin + + for i in 0 to 7 loop + report"entering into getbyte"; + temp(i) := IP((byte_num-1)*8+i); + end loop; +report"getbyte exited"; +return temp; + +end getbyte; + +--******************************************--- +--******************************************-- +------shared variable declarations----------- + +shared variable buf_temp_reg1 : std_logic_vector(7 downto 0); +shared variable message : string(1 to 21); +shared variable message2 : string(1 to 30); +shared variable current_address : integer; +shared variable page_boundary_low : integer; +shared variable page_boundary_high : integer; +shared variable mem_no : integer; + + + +signal temp_prot_status_program : bit_vector(sec_tors(device)-2 downto 0); +signal temp_reg1 : std_logic_vector(7 downto 0); + +signal reset_sig : std_logic:= '0'; +signal skip : std_logic := '1'; +signal skip_be : std_logic := '0'; +signal skip_end : std_logic := '0'; +signal opcode_temp : std_logic_vector(7 downto 0) := "00000000"; +signal page_addr0 : std_logic_vector(7 downto 0) := "00000000"; +signal page_addr1 : std_logic_vector(7 downto 0) := "00000000"; +signal byte_addr : std_logic_vector(7 downto 0) := "00000000"; +signal t : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; +signal prot_temp_reg : std_logic_vector(7 downto 0) ; +signal lock_temp_reg : std_logic_vector(7 downto 0) ; +signal rd_data1 : std_logic_vector(7 downto 0); +signal less_than_60mhz : std_logic:='0'; + +signal buffer1read : std_logic:='0'; + +signal oPC7 : std_logic; + +signal arr_rd_dummybyte : integer := 0; +signal buff_rd_dummybyte : integer:= 0; + +signal RDPD : std_logic :='0'; +signal EDPD : std_logic :='0'; +signal MMPR : std_logic:='0'; + +signal updating_buffer1 : std_logic:='0'; +signal updating_buffer2 : std_logic:='0'; +---------------UPDATING MEMORY----------- +signal updating_memory : std_logic:='0'; + +signal comparing : std_logic:='0'; +signal erasing_page : std_logic:='0'; +signal erasing_block : std_logic:='0'; +signal erasing_sector : std_logic:='0'; +signal erasing_chip : std_logic:='0'; +signal fast_mode : std_logic:='0'; +signal IntCSb : std_logic ; +constant valid : Boolean := TRUE ; +signal MIR : std_logic :='0'; +signal SRR : std_logic:='0'; +signal mem_initialized : std_logic; +signal deep_power_down : std_logic := '0'; +signal SR : std_logic:= '0'; +signal RDYBSY_reg : std_logic :='1'; + + + +signal foreground_op_enable : std_logic :='0'; +signal background_op_enable : std_logic:='0'; + +signal status_read : std_logic :='0'; +signal so_reg : std_logic := '1'; +signal so_on : std_logic :='0'; +signal so_reg1 : std_logic := '1'; +signal so_on1 : std_logic :='0'; +signal so_reg2 : std_logic := '1'; +signal so_on2 : std_logic :='0'; +signal so_reg3 : std_logic := '1'; +signal so_on3 : std_logic :='0'; +signal status : std_logic_vector(7 downto 0) +:= ('1' & '0' & Device_sel3(DEVICE) & Device_sel2(DEVICE) & Device_sel1(DEVICE)& '1' & '0' & '0'); + +-----------status signal------------- + +signal status_B1C_s6 : std_logic; +signal status_B2C_s6 : std_logic; + +--------- +signal lock_status : std_logic_vector(sec_tors(device) downto 0); + +--**************** begin of Architecture **************--- + + +begin + +--comparing the opcodes-- +process(SCK,SI,CSB) +begin + if ( CSB ='1') then + t <="00000000000000000000000000000000"; + rd_data1 <= "00000000"; + elsif(SCK = '1' and SCK'event) then + + t(0) <= '1'; + t(1) <= t(0); + t(2) <= t(1); + t(3) <= t(2); + t(4) <= t(3); + t(5) <= t(4); + t(6) <= t(5); + t(7) <= t(6); -- t(6) == 1 and t(7) ==0 opcode + t(8) <= t(7); + t(9) <= t(8); + t(10) <= t(9); + t(11) <= t(10); + t(12) <= t(11); + t(13) <= t(12); + t(14) <= t(13); + t(15) <= t(14); -- t(14) == 1 and t(15) ==0 page address + t(16) <= t(15); + t(17) <= t(16); + t(18) <= t(17); + t(19) <= t(18); + t(20) <= t(19); + t(21) <= t(20); + t(22) <= t(21); + t(23) <= t(22); -- t(22) == 1 and t(23) ==0 page address + t(24) <= t(23); + t(25) <= t(24); + t(26) <= t(25); + t(27) <= t(26); + t(28) <= t(27); + t(29) <= t(28); + t(30) <= t(29); + t(31) <= t(30); -- t(30) == 1 and t(31) == 0 byte address + rd_data1(0) <= SI; + rd_data1(1) <= rd_data1(0); + rd_data1(2) <= rd_data1(1); + rd_data1(3) <= rd_data1(2); + rd_data1(4) <= rd_data1(3); + rd_data1(5) <= rd_data1(4); + rd_data1(6) <= rd_data1(5); + rd_data1(7) <= rd_data1(6); + + end if; +end process ; + +opcode_temp <= rd_data1(6) & rd_data1(5) & rd_data1(4) & rd_data1(3) & rd_data1(2) & rd_data1(1) & rd_data1(0) & SI ; +process(SCK,opcode_temp, t) +begin + if (CSB = '1' ) then + page_addr0 <= "00000000"; + page_addr1 <= "00000000"; + byte_addr <= "00000000"; + + elsif ((SCK = '1' and SCK'event)) then + if (t(14) = '1' and t(15) = '0') then + page_addr0 <= opcode_temp; + end if; + if (t(22) = '1' and t(23) = '0') then + page_addr1 <= opcode_temp; + end if; + if (t(30) = '1' and t(31) = '0') then + byte_addr <= opcode_temp; + end if; + end if; +end process; + + +process(SCK,opcode_temp, t) +begin +if (CSB = '1') then + skip <='1'; + arr_rd_dummybyte <= 0; --not used in their code + buff_rd_dummybyte <= 0; + MMPR <='0'; + MMCAR <='0'; + EDPD <='0'; + buffer1read <= '0';--buffer1read legacy command + buffer2read <='0';--buffer 2 read for low frequency + MMPTB1T <='0'; --Main Memory Page To Buffer 1 Transfer + MMPTB2T<='0'; --Main Memory Page To Buffer 2 Transfer + MMPTB1C <='0';--Main Memory Page To Buffer 1 Compare + MMPTB2C <='0';--Main Memory Page To Buffer 2 Compare + B1W <='0'; -- Buffer 1 Write + B2W <='0'; + B1TMMPPWBIE <= '0' ;--Buffer 1 To Main Memory Page Prog With Built-In Erase + fast_mode <= '0'; + B2TMMPPWBIE <= '0';--Buffer 2 To Main Memory Page Prog With Built-In Erase + B1TMMPPWOBIE<='0';--Buffer 1 To Main Memory Page Prog Without Built-In Erase + B2TMMPPWOBIE<='0' ;--Buffer 2 To Main Memory Page Prog Without Built-In Erase + PE<='0'; -- Page Erase + BE<='0'; -- Block Erase + SE <='0'; -- Sector Erase + oPC7<='0' ; -- 4-byte command starting with C7 + MMPPB1<='0'; -- Main Memory Page Prog. Through Buffer 1 + MMPPB2<='0' ; -- Main Memory Page Prog. Through Buffer 2 + APRB1<='0'; -- Auto Page Rewrite Through Buffer 1 + APRB2<='0'; -- Auto Page Rewrite Through Buffer 2 + SR<='0' ; -- Status Register Read + MIR<='0'; -- Manufecturing ID Read + oP3D<='0'; -- 4-Byte Opcode Starting From 3d + PRR<='0'; -- Protection Register Read + LRR<='0'; -- Lock_down Register Read + SRR<='0'; -- Security Register Read + OP9B<='0'; -- 4-Byte Opcode Starting From 9B + RDPD <='0'; +elsif (SCK = '1' and SCK'event) then + if (t(6) = '1' and t(7) = '0' ) then + if(foreground_op_enable='0')then + message := "opcode is not allowed"; + elsif (deep_power_down='1') then + if (opcode_temp = X"AB") then + RDPD <='1'; + else + message := "opcode is not allowed"; + end if; + else + case opcode_temp is + when X"D2" => + if(RDYBSY_reg='1')then + skip <='0'; + arr_rd_dummybyte <= 4; + MMPR <='1'; + end if; + + when X"52" => + if(RDYBSY_reg='1')then + skip <='0'; + arr_rd_dummybyte <= 4; + MMPR <='1'; + end if; + + + when X"03" => + if(RDYBSY_reg='1')then + skip <='0'; + arr_rd_dummybyte <= 0; + MMCAR <='1'; + end if; + when X"0B" => + if(RDYBSY_reg='1')then + skip <='0'; + arr_rd_dummybyte <= 1; + MMCAR <='1'; + end if; + when X"E8" => + if(RDYBSY_reg='1')then + skip <='0'; + arr_rd_dummybyte <= 4; + MMCAR <='1'; + end if; + when X"68" => + if(RDYBSY_reg='1')then + skip <='0'; + arr_rd_dummybyte <= 4; + MMCAR <='1'; + end if; + when X"54" => + skip <='0'; + arr_rd_dummybyte <= 0; + buffer1read <= '1';--buffer1read legacy command + when X"D1" => + buff_rd_dummybyte <= 0; + skip <='0'; + buffer1read <='1'; --buffer1read with low frequency + when X"D4" => + skip <='0'; + buff_rd_dummybyte <= 1; + buffer1read <='1'; + when X"56" => + buffer2read <='1'; + when X"D3" => + skip <='0'; + buffer2read <='1';--buffer 2 read for low frequency + buff_rd_dummybyte <= 0; + when X"D6" => + skip <='0'; + buff_rd_dummybyte <= 1 ; + buffer2read <= '1' ; + when X"53" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + MMPTB1T <='1'; --Main Memory Page To Buffer 1 Transfer + end if; + when X"55" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + MMPTB2T<='1'; --Main Memory Page To Buffer 2 Transfer + end if; + when X"60" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + MMPTB1C <='1';--Main Memory Page To Buffer 1 Compare + end if; + when X"61" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + MMPTB2C <='1';--Main Memory Page To Buffer 2 Compare + end if; + when X"84" => + B1W <='1'; -- Buffer 1 Write + when X"87" => + B2W <='1'; -- Buffer 2 Write + when X"83" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + B1TMMPPWBIE <= '1' ;--Buffer 1 To Main Memory Page Prog With Built-In Erase + end if; + when X"93" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + fast_mode <= '1'; + B1TMMPPWBIE <= '1'; --Buffer 1 To Main Memory Page Prog With Built-In Erase + end if; -- t(14) == 1 and t(15) ==0 page address + when X"86" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + B2TMMPPWBIE <= '1';-- t(14) == 1 and t(15) ==0 page address --Buffer 2 To + -- Main Memory Page Prog With Built-In Erase + end if; + when X"96" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + fast_mode <= '1'; -- t(14) == 1 and t(15) ==0 page address + B2TMMPPWBIE <='1'; --Buffer 2 To Main Memory Page Prog With Built-In Erase + end if; + + when X"88" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + B1TMMPPWOBIE<='1';--- t(14) == 1 and t(15) ==0 page address -Buffer 1 To + --Main Memory Page Prog Without Built-In Erase + end if; + when X"98" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then -- t(14) == 1 and t(15) ==0 page address hen + message := "opcode is not allowed"; + else + fast_mode <= '1'; + B1TMMPPWOBIE<='1' ;--Buffer 1 To Main Memory Page Prog Without Built-In Erase + -- t(14) == 1 and t(15) ==0 page address -- not in document + end if; + when X"89" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + fast_mode <= '1'; + B2TMMPPWOBIE<='1' ;--Buffer 2 To Main Memory Page Prog Without Built-In Erase + end if; + when X"99" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + B2TMMPPWOBIE<='1';--Buffer 2 To Main Memory Page Prog Without Built-In Erase + -- not in document + end if; + when X"81" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + PE<='1'; -- Page Erase + end if; + when X"50" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + BE<='1'; -- Block Erase + end if; + when X"7C" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + SE <='1'; -- Sector Erase + end if; + when X"C7" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + oPC7<= '1' ; -- 4-byte command starting with C7 + end if; + when X"82" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + MMPPB1<='1'; -- Main Memory Page Prog. Through Buffer 1 + end if; + when X"92" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + fast_mode <= '1'; + MMPPB1<='1'; -- Main Memory Page Prog. Through Buffer 1 + + end if; + when X"85" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + MMPPB2<='1' ; -- Main Memory Page Prog. Through Buffer 2 + end if; + when X"95" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + fast_mode <= '1'; + MMPPB2<='1'; -- Main Memory Page Prog. Through Buffer 2 + end if; + when X"58" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + APRB1<='1'; -- Auto Page Rewrite Through Buffer 1 + end if; + when X"59" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + elsif(RDYBSY_reg='0')then + message := "opcode is not allowed"; + else + APRB2<='1'; -- Auto Page Rewrite Through Buffer 2 + end if; + when X"57" => + SR<='1' ; -- Status Register Read + + when X"D7" => + skip <='0'; + SR<='1'; -- Status Register Read + when X"9F" => + skip <='0'; + MIR<='1'; -- Manufecturing ID Read + when X"3D" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + else + oP3D<='1'; -- 4-Byte Opcode Starting From 3d + end if; + when X"32" => + if(RDYBSY_reg='1')then + PRR<='1'; -- Protection Register Read + end if; + when X"35" => + if(RDYBSY_reg='1')then + LRR<='1'; -- Lock_down Register Read + end if; + when X"77" => + if(RDYBSY_reg='1')then + SRR<='1'; -- Security Register Read + end if; + when X"9B" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + else + oP9B<='1'; -- 4-Byte Opcode Starting From 9B + end if; + when X"B9" => + if(background_op_enable='0') then + message := "opcode is not allowed"; + else + EDPD<='1'; -- enable deep power down + end if; + when others => + message := "Unrecognized opcode "; + end case; + + end if; + + end if; + +end if; +end process; + + + + +process(SCK,CSB) +begin + + if(CSB='0' and CSB'event)then + if (SCK = '0') then + skip_be <= '1'; + else + skip_be <= '0'; + end if; + end if; +end process ; + +skip_end <= skip_be and skip; + + +background_op_enable <= '1' after tPUW ; + + +reset_sig <= '0', '1' after 1 ns; + +process + +variable inbuf : line; +variable outbuf : line; +--file LOAD_FILE1 : text open read_mode is "./memory.txt"; +file LOAD_FILE1 : text open read_mode is flashmemory; +file OUT_FILE : text open write_mode is "./memory_out.txt"; +variable numword : integer := 0; +variable word : string(1 to 8); +variable mem : memtype; +variable i : integer; +variable value : bit_vector(7 downto 0); +---------- +variable inbuf1 : line; +--file LOAD_FILE2 : text open read_mode is "protection.txt"; +--file LOAD_FILE2 : text open read_mode is protection; +variable numword1 : integer := 0; +variable value1 : bit_vector(7 downto 0); +variable protect : prot_type; + + variable jerase : integer; + variable temp_prot : bit_vector(sec_tors(device) downto 0); + --------------- +variable inbuf2 : line; +variable outbuf12 : line; +--file LOAD_FILE3 : text open read_mode is "lockdown.txt"; +--file LOAD_FILE3 : text open read_mode is lockdown; +variable numword2 : integer := 0; +variable value2 : bit_vector(7 downto 0); +--------------------- + +variable inbuf3 : line; +--file LOAD_FILE4 : text open read_mode is "factory.txt"; +--file LOAD_FILE4 : text open read_mode is factory; +variable numword3 : integer := 0; +variable value3 : bit_vector(7 downto 0); +------------------ + +variable locked : std_logic:='0'; +variable protecteds : std_logic:='0'; +variable MMPPB1_mem_page : std_logic_vector(p_address(device)-1 downto 0); +variable MMPPB1_buf_page : std_logic_vector(p_address(device)-1 downto 0); +variable MMPPB2_mem_page : std_logic_vector(p_address(device)-1 downto 0); +variable MMPPB2_buf_page : std_logic_vector(p_address(device)-1 downto 0); +variable temp_lock : bit_vector(sec_tors(device) downto 0); +variable temp_lock_reg : lock_type; + +begin +if (foreground_op_enable = '0') then ---- Enable foreground op_codes +wait on reset_sig ; +report " initialization"; +wait for 1 ps; +for i in 0 to (memsize(pagesize(device,binary_page),page_cal(device))-1) loop +memory(i) <= (others=>'1'); +end loop; +mem_initialized <= '0'; + +wait for 1 ps; + +while not ENDFILE(LOAD_FILE1) loop + report " memory initialization"; +READLINE(LOAD_FILE1,inbuf); +hexa_to_bit_vector(inbuf, 8, value); +memory(numword) <= value; +WRITE(outbuf,memory(numword)); +WRITELINE(OUT_FILE, outbuf); +numword := numword + 1; +if(numword = (N-1)) then + + exit; +end if; +mem_initialized <= '1'; +end loop; + + + + +wait for 1 ps; + +if (mem_initialized = '1') then + for j in 0 to page_cal(device)-1 loop + page_status(j) <= '1'; -- memory was initialized, so, Pages are Not Erased. + end loop; + else + for j in 0 to page_cal(device)-1 loop + page_status(j) <= '0'; + end loop; + +end if; + + + +wait for 1 ps; +------------initialization of protection reg------------- +--while not ENDFILE(LOAD_FILE2) loop + --report " protection reg initialization"; +--READLINE(LOAD_FILE2,inbuf1); +--hexa_to_bit_vector(inbuf1, 8, value1); +--prot_reg(numword1) <= value1; +--numword1 := numword1 + 1; +--if(numword1 > (p-1)) then +--exit; +--end if; +--end loop; + + +for i in 0 to SEC_TORS(device)-1 loop +report"protection intialization"; + prot_reg(i) <= getbyte(protection,i+1); +report "lockdown initialization"; + lock_reg(i) <= getbyte(lockdown,i+1); +end loop; + + + +wait for 1 ps; +prot_temp_reg <= To_stdlogicvector(prot_reg(0)); + + prot_status(0) <= prot_temp_reg(7) and prot_temp_reg(6); + prot_status(1) <= prot_temp_reg(5) and prot_temp_reg(4); + for j in 1 to SEC_TORS(device)-1 loop + temp_prot(j+1) := prot_reg(j)(0)and prot_reg(j)(1) + and prot_reg(j)(2)and prot_reg(j)(3) + and prot_reg(j)(4)and prot_reg(j)(5) + and prot_reg(j)(6)and prot_reg(j)(7); + end loop; + + prot_status <= To_stdlogicvector(temp_prot); + + +wait for 10 ps; +-------------initialization of lock reg----------- + +--while not ENDFILE(LOAD_FILE3) loop + --report " lock reg initialization"; +--READLINE(LOAD_FILE3,inbuf2); +--hexa_to_bit_vector(inbuf2, 8, value2); +--lock_reg(numword2) <= value2; +--numword2 := numword2 + 1; +--if(numword2 > (p-1)) then +--exit; +--end if; +--end loop; + + +wait for 1 ps; +lock_temp_reg <= To_stdlogicvector(lock_reg(0)); + lock_status(0) <= lock_temp_reg(7) and lock_temp_reg(6); + lock_status(1) <= lock_temp_reg(5) and lock_temp_reg(4); + for j in 1 to SEC_TORS(device)-1 loop + temp_lock(j + 1) := lock_reg(j)(0)and lock_reg(j)(1) + and lock_reg(j)(2)and lock_reg(j)(3) + and lock_reg(j)(4)and lock_reg(j)(5) + and lock_reg(j)(6)and lock_reg(j)(7); + end loop; + + lock_status <= To_stdlogicvector(temp_lock); +---------------initialization of factory reg------------ + +wait for 1 ps; +--while not ENDFILE(LOAD_FILE4) loop + --report " factory initialization"; +--READLINE(LOAD_FILE4,inbuf3); +--hexa_to_bit_vector(inbuf3, 8, value3); +--factory_reg(numword3) <= value3; +--numword3 := numword3 + 1; +--if(numword3 > 64) then +--exit; +--end if; +--end loop; + +for j in 0 to 63 loop + + factory_reg(j) <= getbyte(factory,j+1); + security_reg(j) <= getbyte(security,j+1); + wait for 1 ps; + security_flag <='0'; + if(security_reg(j) /= X"FF")then + security_flag <= '1'; + end if; +end loop; + + + +wait for 1 ps; +--************************** +wait for tVCSL ; +foreground_op_enable <= '1' ; ---- Enable foreground op_codes +report " forground enable"; + +end if; +--************************** + + wait on t(31); + report " t31 asserted"; + + + + +if(MMPR='1' and t(31) = '1')then + + report "entered into MMPR "; + message := "opcodeFis not allowed"; + if (Rapid_interface = false and fsck > 50) then + report "WARNING: Frequency should be less than 50MHz for SPI interface type . Main Memory Page Read is not allowed"; + end if; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + -- pass by 32 cycles or 4 bytes in the case of serial interface + wait for (Twl + Twl ) * 32; + if (Rapid_interface = false and fsck > 50) then + read_out_x(CSB,SCK,so_reg,so_on) ; + else + + read_out(SCK,CSB,page_boundary_low,page_boundary_high,current_address,mem_no,tbuffer1, + tbuffer2,memory,so_reg,so_on); + end if; + + report "MMPR is exited "; +elsif(MMCAR='1' and t(31) = '1')then + report "entered into MMCAR "; + + if ((Rapid_interface = false) and (fSCK > 50) and (arr_rd_dummybyte /= 0)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type . Main Memory Page Read is not allowed"; + +end if; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + + + if (((arr_rd_dummybyte = 0) and (fSCK >= 20)) or ((Rapid_interface = false) and (fSCK > 50) and (arr_rd_dummybyte/= 0)))then + read_out_x(CSB,SCK,so_reg,so_on) ; + elsif(arr_rd_dummybyte = 1) then + wait for (Twl + Twh ) * 8; + read_out_array(SCK,CSB,pagesize(device,binary_page),memsize(pagesize(device,binary_page),page_cal(device)),page_boundary_low, + page_boundary_high,current_address,memory,so_reg,so_on); + + else + wait for (Twl + Twh ) * 32; + read_out_array(SCK,CSB,pagesize(device,binary_page),memsize(pagesize(device,binary_page),page_cal(device)),page_boundary_low, + page_boundary_high,current_address,memory,so_reg,so_on); + end if; + + report "MMCAR is exited "; + +elsif(buffer1read='1'and t(31) = '1')then + report "entered into buffer1read"; + if ((Rapid_interface = false) and (fSCK > 50) and (buff_rd_dummybyte /= 0)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type . Buffer1 Read is not allowed"; + end if; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + + --if(buff_rd_dummybyte = 0 and less_than_33mhz ='0')then + if (((buff_rd_dummybyte = 0) and (fSCK >= 20)) or ((Rapid_interface = false) and (fSCK > 50) and (buff_rd_dummybyte/= 0)))then + read_out_x(CSB,SCK,so_reg,so_on) ; + else + -- pass by 8 cycles or one serial byte + wait for (Twl + Twh ) * 8; + read_out(SCK,CSB,page_boundary_low,page_boundary_high,current_address,1, + tbuffer1,tbuffer2,memory,so_reg,so_on); + end if; + report "buffer1read exited"; + + +elsif(buffer2read='1' and t(31) = '1')then + report "entered into buffer2read"; + if ((Rapid_interface = false) and (fSCK > 50) and (buff_rd_dummybyte /= 0)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type . Buffer1 Read is not allowed"; + end if; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + --if(buff_rd_dummybyte = 0 and less_than_33mhz ='0')then + if (((buff_rd_dummybyte = 0) and (fSCK >= 20)) or ((Rapid_interface = false) and (fSCK > 50) and (buff_rd_dummybyte/= 0)))then + read_out_x(CSB,SCK,so_reg,so_on) ; + else + -- pass by 8 cycles + wait for (Twl + Twh ) * 8; + read_out(SCK,CSB,page_boundary_low,page_boundary_high,current_address,2,tbuffer1, + tbuffer2,memory,so_reg,so_on); + end if; + report "buffer2read exited"; + +elsif(MMPTB1T='1'and t(31) = '1')then + report" entered into MMPTB1T"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + wait until CSB'event and CSB ='1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + transfer_to_buffer(1, page_boundary_low,memory,tbuffer1,tbuffer2); + updating_buffer1 <= '1'; + + wait for Txfr ; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + updating_buffer1 <= '0'; + + report " MMPTB1T exited"; + +elsif (MMPTB2T='1'and t(31) = '1')then + report" entered into MMPTB2T"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + wait until CSB'event and CSB = '1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + transfer_to_buffer (2, page_boundary_low,memory,tbuffer1,tbuffer2); + updating_buffer2 <= '1'; + + wait for Txfr; + RDYBSY_reg <= '1';-- after tXFR ; -- device is now ready + status(7) <= '1'; + updating_buffer2 <= '0'; + + report " MMPTB2T exited"; + +elsif(MMPTB1C='1' and t(31) = '1')then + report " entered in to MMPTB1C"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + wait until CSB'event and CSB = '1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + compare_with_buffer(1,page_boundary_low,memory,tbuffer1,tbuffer2,status_B1C_s6); + comparing <= '1'; + + wait for tXFR; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + status(6) <= status_B1C_s6; + comparing <= '0'; + report " MMPTB1C is exited"; + +elsif(MMPTB2C='1')then + report " entered in to MMPTB2C"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + wait until CSB'event and CSB = '1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + compare_with_buffer(2,page_boundary_low,memory,tbuffer1,tbuffer2,status_B2C_s6); + comparing <= '1'; + + wait for tXFR; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + status(6) <= status_B2C_s6; + comparing <= '0'; + report " MMPTB2C is exited"; + +elsif(B1W='1' and t(31) = '1')then + report "B1write"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,1,CSB,sck,SI); + report "B1write end"; + +elsif(B2W='1' and t(31) = '1')then + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + report "B2write"; + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,2,CSB,sck,SI); + +elsif(B1TMMPPWBIE='1'and t(31) = '1')then + report "B1TMMPPWBIE"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), +page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + + locked := check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))); + protecteds := check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))), WPB,soft_prot_enabled); + + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))) ='0') then + + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))), WPB,soft_prot_enabled) ='0')then + + wait until CSB ='1'; + RDYBSY_reg <= '0'; -- device is busy + status(7) <= '0'; + write_to_memory(1,comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= '1'; + + + message2 :="weCan write page is not locked"; + updating_memory <= '1'; + + wait for tEP; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + updating_memory <= '0'; + + else + wait until CSB ='1'; + message2 :="Cannot write page is protecteds"; + end if; + + else + wait until CSB ='1'; + message2 :=" Cannot write page is Locked "; + end if; + +elsif(B2TMMPPWBIE='1'and t(31) = '1')then + report "B2TMMPPWBIE"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + + + locked := check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))); + + protecteds := check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))), WPB,soft_prot_enabled); + + + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))) ='0') then + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))), WPB,soft_prot_enabled) ='0')then + wait until CSB'event and CSB ='1'; + RDYBSY_reg <= '0'; -- device is busy + status(7) <= '0'; + write_to_memory(2,comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= '1'; + updating_memory <= '1'; + + wait for tEP; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + message2 :="weCan write page is not locked"; + updating_memory <= '0'; + else + + wait until CSB'event and CSB ='1'; + message2 :=" Cannot write page isprotecteds"; + end if ; + else + wait until CSB'event and CSB ='1'; + message2 :=" Cannot write page is Locked "; + end if; + +elsif(B1TMMPPWOBIE='1' and t(31) ='1')then + report "B1TMMPPW0BIE"; + + + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + + + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device)))) ='0') then + + + + + + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) ='0')then + + wait until CSB'event and CSB = '1'; + if (page_status(conv_integer(comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device)))) = '0') then --page is already erased + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + updating_memory <= '1'; + write_to_memory(1,comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= '1'; + + if (fast_mode = '0') then + wait for tP; + RDYBSY_reg <= '1'; + status(7) <= '1'; + updating_memory <= '0'; + else + wait for tFP; + RDYBSY_reg <= '1'; + status(7) <= '1'; + updating_memory <= '0'; + end if; + + else + message :="TryingtowriteintoPage"; + end if; + + else + wait until CSB'event and CSB = '1'; + message2 :=" Cannot write page isprotecteds"; + end if; + + + else + + wait until CSB'event and CSB = '1'; + message2 :=" Cannot write page is Locked "; + end if; + report "B1TMMPPW0BIE is exited"; + +elsif(B2TMMPPWOBIE='1' and t(31) ='1')then + report " entered into B2TMMPPW0BIE"; + + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + + + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device)))) ='0') then + + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) ='0')then + + wait until CSB'event and CSB = '1'; + if (page_status(conv_integer(comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device)))) = '0') then --page is already erased + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + updating_memory <= '1'; + write_to_memory(2,comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= '1'; + + if (fast_mode = '0') then + wait for tP; + RDYBSY_reg <= '1'; + status(7) <= '1'; + updating_memory <= '0'; + else + wait for tFP; + RDYBSY_reg <= '1'; + status(7) <= '1'; + updating_memory <= '0'; + end if; + + else + message :="TryingtowriteintoPage"; + end if; + + else + wait until CSB'event and CSB = '1'; + message2 :=" Cannot write page isprotecteds"; + end if; + + + else + + wait until CSB'event and CSB = '1'; + message2 :=" Cannot write page is Locked "; + end if; + report "B2TMMPPW0BIE is exited"; + +elsif(oP3D ='1' and t(31)='1' and page_addr0 = X"2A" and page_addr1 = X"7F" and byte_addr =X"A9")then + report "entered into enable sector protection "; + SPE <='1'; + wait until CSB'event and CSB ='1'; + soft_prot_enabled <='1'; + status(1)<='1'; + SPE <='0'; + report "enable sector protection is exited"; + +elsif(oP3D ='1' and t(31)='1' and page_addr0 = X"2A" and page_addr1 = X"7F" and byte_addr =X"9A")then + report "entered into disable sector protection "; + SPD <='1'; + wait until CSB'event and CSB ='1'; + if(WPB = '1')then + soft_prot_enabled <='0'; + status(1)<='0'; + end if; + SPD <='0'; + +elsif(oP3D ='1' and t(31)='1' and page_addr0 = X"2A" and page_addr1 = X"7F" and byte_addr =X"CF")then + report "entered into erase sector protection register PRE"; + PRE <='1'; + wait until CSB'event and CSB ='1'; + RDYBSY_reg <='0';--device is busy + status(7) <= '0'; + prot_reg(0) <= (others=>'1'); + prot_status(0)<='1'; + prot_status(1)<='1'; + wait for 1 ps; + for j in 1 to sec_tors(device)-1 loop + prot_reg(j) <= (others=>'1'); + prot_status(j+1) <='1'; + end loop; + + wait for Tpe; + RDYBSY_reg <= '1'; + status(7) <= '1'; + PRE <='0'; + +elsif(oP3D ='1' and t(31)='1' and page_addr0 = X"2A" and page_addr1 = X"7F" and byte_addr =X"FC")then + report "program sector protection register PRP "; + report "entered into PRP "; + PRP <= '1'; + current_address :=0; + page_boundary_low := 0; + page_boundary_high := sec_tors(device); + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,1,CSB,sck,SI); + + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + wait for 1 ps; + for j in 0 to sec_tors(device)-1 loop + prot_reg(j) <= (prot_reg(j) and tbuffer1(j)); + end loop; + wait for 1 ps; + temp_reg1 <= To_stdlogicvector(prot_reg(0)); + wait for 1 ps; + + for j in 0 to sec_tors(device)-2 loop + temp_prot_status_program(j) <= prot_reg(j)(0) and prot_reg(j)(1) + and prot_reg(j)(2) and prot_reg(j)(3) + and prot_reg(j)(4) and prot_reg(j)(5) + and prot_reg(j)(6) and prot_reg(j)(7); + end loop; + wait for 1 ps; + + prot_status <= (To_stdlogicvector(temp_prot_status_program)) & (temp_reg1(5) and temp_reg1(4)) & (temp_reg1(7) and temp_reg1(6)) ; + wait for Tp; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + wait for 1 ps; + PRP <= '0'; + report "PRP is exited "; + +elsif(oP3D ='1' and t(31)='1' and page_addr0 = X"2A" and page_addr1 = X"7F" and byte_addr =X"30")then + report "entered into program sector lockdown register LRP "; + LRP <='1'; + wait until CSB'event and CSB ='1'; + RDYBSY_reg <= '0'; -- device is busy + status(7) <= '0'; + + if (conv_integer(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))) < 8)then + case (lock_status(1)) is + when '0' => lock_reg(0) <= X"C0"; -- Sector 0a locked, 0b unlocked + when '1' => lock_reg(0) <= X"F0"; -- Sectors 0a, 0b locked + when others => message2 :="Thismessage shouldnever appear"; + end case; + lock_status(0) <= '1'; + elsif (conv_integer(page) < PAGEPER_SECTOR(device)) then + case (lock_status(0)) is + when '0' => lock_reg(0) <= X"30"; --Sector 0a unlocked, 0b locked + when '1' => lock_reg(0) <= X"F0"; -- Sectors 0a, 0b locked + when others => message2 :="Thismessage shouldnever appear"; + end case; + lock_status(1) <= '1'; + else + lock_reg(sec_tors(device)-1) <= (others=>'1'); + lock_status(sec_tors(device)) <= '1'; + end if; + wait for Tp; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + LRP <='0'; + report "LRP is exited "; + +elsif(oP3D ='1' and t(31)='1' and page_addr0 = X"2A" and page_addr1 = X"80" and byte_addr =X"A6")then + report "entered binary page setup"; + BPS <='1'; + wait until CSB'event and CSB = '1' ; + RDYBSY_reg <= '0'; -- device is busy + status(7) <= '0'; + binary_page <= '1'; + + wait for Tp; + RDYBSY_reg <= '1'; --device is now ready + status(7) <= '1'; + status(0) <= '1'; + BPS <='0'; + report "binary page setup exited"; + + +elsif(MMPPB1='1' and t(31)='1' and RDYBSY_reg='1')then + report "MMPPB1"; + MMPPB1_mem_page := comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)); + -- page value has been stored for main memory page program + MMPPB1_buf_page := (others=>'0');--buffer has zero pages + + compute_address(MMPPB1_buf_page,pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page), + page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high,current_address,mem_no,binary_page); + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,1,CSB,sck,SI); + -- this will write to buffer + -- it will proceed to next step, when, posedge of CSB. + -- This is complicated, and, hence, explained here: + -- At posedge of CSB, the write_data will get disabled. + -- At this time, writing to buffer needs to stop, and, + -- writing into memory should start. + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), pageper_sector(device), + lock_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device)))) ='0') then + + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device))), WPB,soft_prot_enabled) ='0')then + + compute_address(MMPPB1_mem_page,pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page), + page_addr1,byte_addr,binary_page),page_boundary_low, + page_boundary_high,current_address,mem_no,binary_page); + RDYBSY_reg <= '0'; -- device is busy + status(7) <='0'; + write_to_memory(1,comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= '1'; + + updating_memory <= '1'; + + wait for Tep; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + updating_memory <= '0'; + else + message2 :=" Cannot write page is proted "; + end if; + else + message2 :=" Cannot write page is Locked "; + end if; + + report " MMPPB1 exited"; + + +elsif(MMPPB2='1' and t(31)='1' and RDYBSY_reg='1')then + report "MMPPB2"; + + MMPPB2_mem_page := comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)); + -- page value has been stored for main memory page program + MMPPB2_buf_page := (others=>'0');--buffer has zero pages + + compute_address(MMPPB2_buf_page,pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page), + page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high,current_address,mem_no,binary_page); + + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,2,CSB,sck,SI); + -- this will write to buffer + -- it will proceed to next step, when, posedge of CSB. + -- This is complicated, and, hence, explained here: + -- At posedge of CSB, the write_data will get disabled. + -- At this time, writing to buffer needs to stop, and, + -- writing into memory should start. + + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)))) ='0') then + + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) ='0')then + + compute_address(MMPPB2_mem_page,pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page), + page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high,current_address,mem_no,binary_page); + RDYBSY_reg <= '0'; -- device is busy + status(7) <='0'; + write_to_memory(2,comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= '1'; + updating_memory <= '1'; + + wait for Tep; + RDYBSY_reg <= '1'; -- device is now ready + status(7)<='1'; + updating_memory <= '0'; + else + message2 :=" Cannot write page is proted "; + end if; + else + message2 :=" Cannot write page is Locked "; + end if; + +elsif(APRB1='1' and t(31)='1')then + report "ARPB1"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + + wait until CSB'event and CSB = '1'; + transfer_to_buffer (1, page_boundary_low,memory,tbuffer1,tbuffer2); + updating_buffer1 <='1'; + + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)))) ='0') then + + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) ='0')then + + updating_memory <='1'; + RDYBSY_reg <='0'; + status(7)<='0'; + wait for Tep; + RDYBSY_reg <='1'; + status(7)<='1'; + updating_buffer1 <='0'; + updating_memory <='0'; + else + message2 :=" Cannot write page is proted "; + + end if; + else + message2 :=" Cannot write page is Locked "; + end if; + + +-- NOTE: + -- We dont need to rewrite the data back into main-memory, as the + -- data is already available in the main-memory + -- This task was exactly same as MMPTB1T, except the delay-value + -- We could have easily used the same code as MMPTB1T, using + -- an if condition for delay-selection. However, still doing + -- this way, so that the code for each opcode is independent + -- of anything else. + +report "APRB1 auto page rewrite is exited"; + +elsif(APRB2='1' and t(31)='1')then +report "entered into auto page rewrite through buffer 2 ARPB2"; + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + + wait until CSB'event and CSB = '1'; + transfer_to_buffer (2, page_boundary_low,memory,tbuffer1,tbuffer2); + updating_buffer1 <='1'; + + if(check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)))) ='0') then + + if(check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) ='0')then + + updating_memory <='1'; + RDYBSY_reg <='0'; + status(7)<='0'; + wait for Tep; + RDYBSY_reg <='1'; + status(7)<='1'; + updating_buffer1 <='0'; + updating_memory <='0'; + else + message2 :=" Cannot write page is proted "; + + end if; + else + message2 :=" Cannot write page is Locked "; + end if; + + +-- NOTE: + -- We dont need to rewrite the data back into main-memory, as the + -- data is already available in the main-memory + -- This task was exactly same as MMPTB1T, except the delay-value + -- We could have easily used the same code as MMPTB1T, using + -- an if condition for delay-selection. However, still doing + -- this way, so that the code for each opcode is independent + -- of anything else. + +report " auto page rewrite through buffer 2 is exited"; + +----------------page erase------------------ + +elsif (PE = '1')then + report "entered into page erase" ; + if (check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pageper_sector(device), + lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device)))) = '0')then + if (check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pageper_sector(device),prot_status, + comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) ='0')then + + + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + + wait until CSB'event and CSB='1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),page_boundary_low,memory,temp_page_status); + erasing_page <= '1'; + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + wait for Tpe ; + RDYBSY_reg <= '1' ; --device is now ready + status(7) <= '1' ; + erasing_page <= '0' ; + else + message2 :=" Cannot erase page is proted "; + end if; + else + message2 :=" Cannot erase page is locked "; + end if; + + report "page erase exited"; +--------------------------Block Erase------------------------- + +elsif (BE = '1')then +report "entered into block erase" ; + if (check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))) = '0')then + + if (check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1, + manid(device)),pageper_sector(device),prot_status,comp_sector_addr(p_address(device), + comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) ='0')then + + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1, + manid(device)),pagesize(device,binary_page),comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high,current_address,mem_no,binary_page); + + wait until CSB'event and CSB ='1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + + jerase := page_boundary_low; + loop_erase: loop + if (jerase < page_boundary_low+(8*pagesize(device,binary_page))) then + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device)),pagesize(device,binary_page),jerase,memory,temp_page_status); --erase 8 pages, i.e. a block + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + jerase := jerase+pagesize(device,binary_page); + else + report "--------------------------Block Eraseexit -------------------------"; + exit loop_erase; + end if; + end loop; + + for j in 0 to 7 loop --erase_page will only change the status of one-page + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))+j) <= '0'; + end loop; + erasing_block <= '1'; + wait for Tbe; + RDYBSY_reg <= '1' ; --device is now ready + status(7) <= '1'; + erasing_block <= '0'; + else + message2 :=" Cannot erase bloc is proted "; + end if; + else + message2 :=" Cannot erase bloc is locked "; + end if; + + + report "block erase exited" ; + +---------------------------Sector Erase ----------------------------- + +elsif (SE = '1')then + if (check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pageper_sector(device), + lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))) = '0')then + + if (check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pageper_sector(device), + prot_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) = '0')then + + compute_address(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pagesize(device,binary_page), + comp_byte_addr(b_address(device,binary_page),page_addr1,byte_addr,binary_page),page_boundary_low, + page_boundary_high,current_address,mem_no,binary_page); + + wait until CSB'event and CSB = '1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + --******************************-- + if (conv_integer(comp_page_addr(p_address(device),binary_page,page_addr0, + page_addr1,manid(device))) < 8 ) then + page_boundary_low := 0; + + jerase := page_boundary_low; + loop_sectorerase: loop + if (jerase < page_boundary_low+8*pagesize(device,binary_page) ) then + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),jerase,memory,temp_page_status); -- erase 8 pages, i.e. a block + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + + jerase := jerase+pagesize(device,binary_page); + else + report "--------------------------sector Eraseexit -------------------------"; + exit loop_sectorerase; + end if; + end loop; + + for j in 0 to 7 loop -- erase_page will only change the status of one-page + page_status(j) <= '0'; + end loop; + --************************************---- + elsif (comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)) < pageper_sector(device)) then + page_boundary_low := 8*pagesize(device,binary_page); + jerase := page_boundary_low; + loop_sector1erase : loop + if (jerase < page_boundary_low+((pageper_sector(device)-8)*pagesize(device,binary_page)) ) then + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),jerase,memory,temp_page_status); --erase 248/120 pages, i.e. a block + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + jerase := jerase+pagesize(device,binary_page); + else + report "--------------------------sector1 Eraseexit -------------------------"; + exit loop_sector1erase; + end if; + end loop; + + for j in 8 to pageper_sector(device)-1 loop --erase_page will only change the status of one-page + page_status(j) <= '0'; + end loop; + + --**************************** + else + page((p_address(DEVICE)- s_address(DEVICE))-1) <= '0'; + page_boundary_low :=conv_integer(page)*pagesize(device,binary_page); + jerase := page_boundary_low; + loop_sector2erase : loop + if (jerase < page_boundary_low+(pageper_sector(device)*pagesize(device,binary_page))) then + jerase := jerase+pagesize(device,binary_page); + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),jerase,memory,temp_page_status); --erase 256/128 pages, i.e. a block +page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + jerase := jerase +pagesize(device,binary_page); + else + report "--------------------------sector2 Eraseexit -------------------------"; + exit loop_sector2erase; + + end if; + end loop; + + for j in 0 to pageper_sector(device)-1 loop + page_status(conv_integer(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)))+j) <= '0'; + end loop; + erasing_sector <= '1'; + + wait for Tse; + RDYBSY_reg <= '1' ; --device is now ready + status(7) <= '1'; + erasing_sector <= '0'; + end if; + + + else + message2 :=" Cannot erase sect is proted "; + end if; + else + message2 :=" Cannot erase sect is locked "; + end if; + + +----------------------------------Chip Erase------------------------------------------- + + +elsif(oPC7 ='1' and t(31)='1')then + report "enabling chip erase"; + if (page_addr0 = X"94" and page_addr1 = X"80" and byte_addr = X"9A")then + wait until CSB'event and CSB = '1'; + RDYBSY_reg <= '0'; -- device is busy + status(7) <= '0'; + --sector x0A + page <= (others=>'0'); -- erase sector 0A + sector <= (others=>'0'); + compute_address(page=>page,page_size=>pagesize(device,binary_page),byte=>byte,page_boundary_low=>page_boundary_low, + page_boundary_high=>page_boundary_high,current_address=>current_address,mem_no=>mem_no,binary_page=>binary_page); + + if (check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))) = '0')then + if (check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))),WPB,soft_prot_enabled) = '0')then + + jerase := page_boundary_low; + loop_chiperase: loop + if (jerase < page_boundary_low+8*pagesize(device,binary_page) ) then + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),jerase,memory,temp_page_status); -- erase 8 pages, i.e. a block + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + jerase := jerase+pagesize(device,binary_page); + else + report "--------------------------chip Eraseexit -------------------------"; + exit loop_chiperase; + end if; + end loop; + + + for j in 0 to 7 loop -- erase_page will only change the status of one-page + page_status(j) <= '0'; + end loop; + end if; + end if; + + -- second sector x0B + page <= conv_std_logic_vector(8,p_address(DEVICE)); + sector <= (others=>'0'); + compute_address(page=>page,page_size=>pagesize(device,binary_page),byte=>byte,page_boundary_low=>page_boundary_low, + page_boundary_high=>page_boundary_high,current_address=>current_address,mem_no=>mem_no,binary_page=>binary_page); + --Check if sector is locked + if (check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pageper_sector(device), + lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))) = '0')then + --Check if sector is protecteds----------------------- + if (check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))),WPB,soft_prot_enabled) = '0') then + + jerase := page_boundary_low; + loop_chip_0berase: loop + if (jerase < page_boundary_low +((pageper_sector(device)-8)*pagesize(device,binary_page))) then + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),jerase,memory,temp_page_status); -- erase 8 pages, i.e. a block + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + jerase := jerase+pagesize(device,binary_page); + else + report "--------------------------chip0b Eraseexit -------------------------"; + exit loop_chip_0berase; + end if; + end loop; + + + for j in 0 to 7 loop -- erase_page will only change the status of one-page + page_status(j) <= '0'; + end loop; + end if; + end if; + + sector <= (others=>'1'); + for page in pageper_sector(device) to (PAGE_cal(device) - pageper_sector(device))-1 loop + --Check if sector is locked + if (check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))) = '0') then + --Check if sector is protecteds----------------------- + if (check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pageper_sector(device),prot_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device))),WPB,soft_prot_enabled)= '0') then + + jerase := page_boundary_low; + + loop_chip_0cerase: loop + if (jerase < page_boundary_low +(pageper_sector(device)*pagesize(device,binary_page))) then + + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),jerase,memory,temp_page_status); + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + + jerase := jerase+pagesize(device,binary_page); + else + report "--------------------------chip 0cEraseexit -------------------------"; + exit loop_chip_0cerase; + end if; + end loop; + for j in 0 to pageper_sector(device)-1 loop + page_status(conv_integer(comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))+j) <= '0'; + end loop; + end if; + else + message2 :="Cannot erase:Sector is Locked"; + sector <= sector + 1; + end if; + + end loop; + + page <=((conv_Std_Logic_Vector(PAGE_cal(device),p_address(device))) - (conv_Std_Logic_Vector(pageper_sector(device),p_address(device)))); + + sector <= conv_std_logic_vector((SEC_TORS(device)- 1),S_address(device)); + + compute_address(page=>page,page_size=>pagesize(device,binary_page),byte=>byte,page_boundary_low=>page_boundary_low, + page_boundary_high=>page_boundary_high,current_address=>current_address,mem_no=>mem_no,binary_page=>binary_page); + --Check if sector is locked + if (check_lockd(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pageper_sector(device), + lock_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) = '0')then + --Check if sector is protecteds----------------------- + if (check_protect(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)),pageper_sector(device), + prot_status,comp_sector_addr(p_address(device),comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device))), + WPB,soft_prot_enabled) = '0')then + + jerase := page_boundary_low; + + loop_chip_0derase: loop + if (jerase < page_boundary_low+(pageper_sector(device)*pagesize(device,binary_page))) then + + erase_page(comp_page_addr(p_address(device),binary_page,page_addr0,page_addr1,manid(device)), + pagesize(device,binary_page),jerase,memory,temp_page_status); + + page_status(conv_integer(comp_page_addr(p_address(device),binary_page, + page_addr0,page_addr1,manid(device)))) <= temp_page_status; + + jerase := jerase+pagesize(device,binary_page); + + else + report "--------------------------chip0d Eraseexit -------------------------"; + exit loop_chip_0derase; + end if; + + end loop; + + for j in 0 to pageper_sector(device)-1 loop + page_status(conv_integer(comp_page_addr(p_address(device), + binary_page,page_addr0,page_addr1,manid(device)))+j) <= '0'; + end loop; + + else + message2 :="Cannot erase:Sectorisprotecteds"; + end if; + else + message2 :="Cannot erase:Sector is Locked "; + end if; + + erasing_chip <= '1'; + + wait for Tce; + RDYBSY_reg <= '1'; -- device is now ready + status(7) <= '1'; + erasing_chip <= '0'; + report "chip erase complete"; + end if; + + +elsif(SRR='1' and t(31)='1')then + report "SRR entered"; + if ((Rapid_interface = false) and (fSCK > 50)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type. Security Register Read is not allowed."; + end if; + + if(rapid_interface = false and fsck > 50) then + read_out_x(CSB,SCK,so_reg,so_on) ; + else + read_out_reg(23,0,127,prot_reg,lock_reg,security_reg,CSB,SCK,so_reg,so_on); + end if; + report " SRR exited"; + +elsif(PRR='1' and t(31)='1')then + report "PRR entered"; + if ((Rapid_interface = false) and (fSCK > 50)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type. protection Register Read is not allowed."; + end if; + + if(rapid_interface = false and fsck > 50) then + read_out_x(CSB,SCK,so_reg,so_on) ; + else + read_out_reg(21,0,(sec_tors(device)-1),prot_reg,lock_reg,security_reg,CSB,SCK,so_reg,so_on); + end if; + report " PRR exited"; + +elsif(LRR='1' and t(31)='1')then + report " LRR entered"; + + if ((Rapid_interface = false) and (fSCK > 50)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type. Lockdown Register Read is not allowed."; + end if; + + if(rapid_interface = false and fsck > 50) then + read_out_x(CSB,SCK,so_reg,so_on) ; + else + read_out_reg(22,0,(sec_tors(device)-1),prot_reg,lock_reg,security_reg,CSB,SCK,so_reg,so_on); + end if; + + report "LRR exited"; + + +elsif(oP9B ='1' and t(31)='1' and page_addr0 = X"00" and page_addr1 = X"00" and byte_addr = X"00")then + report" entered program security register"; + SRP <= '1'; + current_address :=0; + page_boundary_low :=0; + page_boundary_high := 63; + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,1,CSB,sck,SI); + + -- this will write to buffer + -- it will proceed to next step, when, posedge of CSB. + -- This is complicated, and, hence, explained here: + -- At posedge of CSB, the write_data will get disabled. + -- At this time, writing to buffer needs to stop, and, + -- writing into memory should start. + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + --writing in to security_reg + if (security_flag = '0') then --Security Register has not been programmed before + for j in 0 to 63 loop + security_reg(j) <= tbuffer1(j); + end loop; + security_flag <= '1'; + wait for Tp; + RDYBSY_reg <= '1'; --device is now ready + status(7) <= '1'; + else + wait for 2000 ns; + RDYBSY_reg <= '1'; --device is now ready + status(7) <= '1'; + end if; + + + +end if; + +report "last of processd"; + +end process; + +----------------deep power down and resume deep power down---------------- + +process +begin + +wait on EDPD,RDPD; +if(EDPD='1') then + wait until CSB'event and CSB='1'; + wait for Tedpd; + deep_power_down <= '1'; +end if; +if(RDPD='1')then + wait until CSB'event and CSB ='1'; + wait for Trdpd; + deep_power_down <= '0'; +end if; +end process; + + +-----------------------status register read-------- + +process + variable j_tmp : integer := 8; +begin + +wait on SR ; +if( SR = '1' ) then +report "SR"; + if ((Rapid_interface = false) and (fSCK > 50)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type. Status Register Read is not allowed."; + end if; + status_read <='1';--reading status reg + if(fsck >= 33)then + for i in 0 to 7 loop + wait until SCK'event and SCK='0'; + wait for tv; + so_reg1 <= 'X'; + so_on1 <= '1'; + end loop; + end if; + status_loop : loop + wait until ((SCK'event and SCK ='0') or (CSB'event and CSB='1')); + exit status_loop when CSB = '1'; + if(j_tmp > 0)then + j_tmp := j_tmp - 1; + else + j_tmp := 7; + + end if; + + if ((Rapid_interface = false) and (fSCK > 50)) then + read_out_x(CSB,SCK,so_reg1,so_on1) ; + else + wait for tV; + so_reg1 <= status(j_tmp); + so_on1 <= '1'; + end if; + + end loop; + report"status register read loop exited"; + wait for tDIS; + so_on1 <= '0'; + status_read <='0'; +end if; + + +end process; +------------manufacturing ID----------- +process --(MIR)--,MANID(device)) + variable j : integer:= 32 ; + variable m_id : std_logic_vector(31 downto 0):= manid(device); +begin +wait on MIR; + if(MIR='1')then +report "MIR"; + if ((Rapid_interface = false) and (fSCK > 50)) then + report"WARNING: Frequency should be less than 50MHz for SPI interface type. Manufacture ID Register Read is not allowed."; + end if; + MIR_loop : loop + wait until ((SCK'event and SCK ='0') or (CSB'event and CSB='1')); + exit MIR_loop when CSB = '1'; + wait for Tv ; + if(J > 0)then + SO_reg2 <= m_id(j-1); + so_on2 <= '1'; + J := J - 1; + if ((Rapid_interface = false) and (fSCK > 50)) then + read_out_x(CSB,SCK,so_reg2,so_on2) ; + end if; + elsif( j = 0) then + So_on2 <= '1'; + So_reg2 <= 'X'; -- only if the cs extends more than available man ID + end if; + end loop; + wait for Tdis ; + so_on2 <= '0'; + So_reg2 <= '0'; + + end if; + + +end process; + + --------------------------- +IntCSb <= CSb or not Resetb; + ------------------------ SCK check +checkPeriod ( SCK , "SCk" , Tsck , "Tsck" , TsckRp , "SCK Frequency" , valid ) ; +checkWidth1 ( SCK , "SCK" , Twh , "Twh" , TsckRw , "SCK High Time" , valid ) ; +checkWidth0 ( SCK , "SCK" , Twl , "Twl" , TsckF , "SCK Low Time" , valid ) ; + ------------------------ IntCSb chec +checkWidth1 ( IntCSb , "IntCSb" , Tcs , "Tcs" , TcsR , "Minimum CS High Time", valid ) ; +checkSetupCS ( IntCSb , "IntCSb" , SCK , "SCK" , Tcss , "Tcss" , TcsF , "IntCSb setup Time" , valid ) ; +checkHoldCS ( IntCSb , "IntCSb" , SCK , "SCK" , Tcsh , "Tcsh" , Tsckm , "IntCSb Hold Time" , valid ) ; + ------------------------ SI check +checkSetupRise ( SI , "SI" , SCK , "SCK" , Tsu , "Tsu" , Tsim , "Data in Setup Time" , valid ) ; +checkHoldRise ( SI , "SI" , SCK , "SCK" , Th , "Th" , TsckRh, "Data in Hold Time" , valid ) ; + + +process(so_on1,so_reg1,so_on2,so_reg2,so_reg, so_on) + begin + if(so_on1='1')then + so <= so_reg1; + elsif(so_on2='1')then + so <= so_reg2; + elsif (so_on='1') then + so <= so_reg; + else + so <= 'Z'; + end if; + end process; + + process(RDYBSY_reg) + begin + if(RDYBSY_reg = '1') then + RDYBSY <= '1'; + else + RDYBSY <= '0'; + end if; + end process; + + + +--less_than_33mhz <= lthan_66mhz & lthan_33mhz; + + +end design; diff --git a/devicemodels/memory.txt b/devicemodels/memory.txt new file mode 100644 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buffer 2 read + +*************************************************8 +compiledataflashCE.do + + +for testing opcodes + + chip erase + +***************************************************** +compiledataflashE.do + + +for testing opcodes + + Page erase + Block Erase + sector erase + +************************************************ + +compiledataflashRR.do + + +for testing opcodes + + Enable sector protection + Disable sector Protection + Erase sector protection register + Program sector lock down Register + Program security register + Program sector protection register + Status Register Read + Manufacturing ID Read + Deep power down + Resume from deep power down + Read sector protection register + Read security register + Read sector lock down register +************************************************* + +compiledataflashMEM.do + + +for testing opcodes + + main memory page program through buffer 1 + Auto page rewrite through buffer 1 + main memory page read + main memory continuous array read + +*************************************************** + +compiledataflashBPS.do + + +for testing opcodes + + binary page setup + buffer 2 write + buffer 2 to main memory page program with out built in erase. + main memory page compare with buffer 1 + main memory to buffer 1 transfer + + +******************************************************** + +For all simulatcases you have simulate only one test becnh top + +vsim work.tb_Dataflashtestbench + +run -all + + +or at modelsim> prompt + +do simcommon.do + +run -all + +if needed add wave -r * to view all waveforms + + + + + + diff --git a/ip/altera/ddr3.bsf b/ip/altera/ddr3.bsf new file mode 100644 index 0000000..6050c1b --- /dev/null +++ b/ip/altera/ddr3.bsf @@ -0,0 +1,530 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Altera and sold by Altera or its +authorized distributors. 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350 92)(pt 350 116)(line_width 1)) + (line (pt 351 132)(pt 351 156)(line_width 1)) + (line (pt 350 132)(pt 350 156)(line_width 1)) + (line (pt 351 172)(pt 351 196)(line_width 1)) + (line (pt 350 172)(pt 350 196)(line_width 1)) + (line (pt 351 212)(pt 351 460)(line_width 1)) + (line (pt 350 212)(pt 350 460)(line_width 1)) + (line (pt 161 172)(pt 161 340)(line_width 1)) + (line (pt 162 172)(pt 162 340)(line_width 1)) + (line (pt 161 356)(pt 161 380)(line_width 1)) + (line (pt 162 356)(pt 162 380)(line_width 1)) + (line (pt 161 396)(pt 161 420)(line_width 1)) + (line (pt 162 396)(pt 162 420)(line_width 1)) + (line (pt 161 436)(pt 161 460)(line_width 1)) + (line (pt 162 436)(pt 162 460)(line_width 1)) + (line (pt 161 476)(pt 161 500)(line_width 1)) + (line (pt 162 476)(pt 162 500)(line_width 1)) + (line (pt 161 516)(pt 161 540)(line_width 1)) + (line (pt 162 516)(pt 162 540)(line_width 1)) + (line (pt 161 556)(pt 161 580)(line_width 1)) + (line (pt 162 556)(pt 162 580)(line_width 1)) + (line (pt 161 596)(pt 161 620)(line_width 1)) + (line (pt 162 596)(pt 162 620)(line_width 1)) + (line (pt 161 636)(pt 161 660)(line_width 1)) + (line (pt 162 636)(pt 162 660)(line_width 1)) + (line (pt 161 676)(pt 161 732)(line_width 1)) + (line (pt 162 676)(pt 162 732)(line_width 1)) + (line (pt 161 748)(pt 161 772)(line_width 1)) + (line (pt 162 748)(pt 162 772)(line_width 1)) + (line (pt 161 788)(pt 161 956)(line_width 1)) + (line (pt 162 788)(pt 162 956)(line_width 1)) + (line (pt 0 0)(pt 512 0)(line_width 1)) + (line (pt 512 0)(pt 512 984)(line_width 1)) + (line (pt 0 984)(pt 512 984)(line_width 1)) + (line (pt 0 0)(pt 0 984)(line_width 1)) + ) +) diff --git a/ip/altera/ddr3.cmp b/ip/altera/ddr3.cmp new file mode 100644 index 0000000..0b54aa7 --- /dev/null +++ b/ip/altera/ddr3.cmp @@ -0,0 +1,59 @@ + component ddr3 is + port ( + pll_ref_clk : in std_logic := 'X'; -- clk + global_reset_n : in std_logic := 'X'; -- reset_n + soft_reset_n : in std_logic := 'X'; -- reset_n + afi_clk : out std_logic; -- clk + afi_half_clk : out std_logic; -- clk + afi_reset_n : out std_logic; -- reset_n + afi_reset_export_n : out std_logic; -- reset_n + mem_a : out std_logic_vector(12 downto 0); -- mem_a + mem_ba : out std_logic_vector(2 downto 0); -- mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n + mem_reset_n : out std_logic; -- mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + avl_ready_0 : out std_logic; -- waitrequest_n + avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- address + avl_rdata_valid_0 : out std_logic; -- readdatavalid + avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata + avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + avl_read_req_0 : in std_logic := 'X'; -- read + avl_write_req_0 : in std_logic := 'X'; -- write + avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + mp_cmd_clk_0_clk : in std_logic := 'X'; -- clk + mp_cmd_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + mp_rfifo_clk_0_clk : in std_logic := 'X'; -- clk + mp_rfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + mp_wfifo_clk_0_clk : in std_logic := 'X'; -- clk + mp_wfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + csr_clk : in std_logic := 'X'; -- clk + csr_reset_n : in std_logic := 'X'; -- reset_n + local_init_done : out std_logic; -- local_init_done + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + oct_rzqin : in std_logic := 'X'; -- rzqin + pll_mem_clk : out std_logic; -- pll_mem_clk + pll_write_clk : out std_logic; -- pll_write_clk + pll_locked : out std_logic; -- pll_locked + pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk + pll_avl_clk : out std_logic; -- pll_avl_clk + pll_config_clk : out std_logic; -- pll_config_clk + pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk + afi_phy_clk : out std_logic; -- afi_phy_clk + pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk + ); + end component ddr3; + diff --git a/ip/altera/ddr3.ppf b/ip/altera/ddr3.ppf new file mode 100644 index 0000000..376fc0f --- /dev/null +++ b/ip/altera/ddr3.ppf @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ip/altera/ddr3.qip b/ip/altera/ddr3.qip new file mode 100644 index 0000000..9c34e5c --- /dev/null +++ b/ip/altera/ddr3.qip @@ -0,0 +1,5460 @@ +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_ddr3_emif" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "ddr3" -name SOPCINFO_FILE [file join $::quartus(qip_path) "ddr3.sopcinfo"] +set_global_assignment -entity "ddr3" -library "ddr3" -name SLD_INFO "QSYS_NAME ddr3 HAS_SOPCINFO 1" +set_global_assignment -library "ddr3" -name MISC_FILE [file join $::quartus(qip_path) "ddr3.cmp"] +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyMw==" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBDb250cm9sbGVyIHdpdGggVW5pUEhZ" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBDb250cm9sbGVyIHdpdGggVW5pUEhZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM18wMDAy" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBDb250cm9sbGVyIHdpdGggVW5pUEhZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBDb250cm9sbGVyIHdpdGggVW5pUEhZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDExMDAwMQ==::QUNfUk9NX01SMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMTAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDExMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMTAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMTAwMDAwMA==::QUNfUk9NX01SMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDEwMDAwMA==::QUNfUk9NX01SMV9NSVJS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMTAwMA==::QUNfUk9NX01SMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAxMDAwMA==::QUNfUk9NX01SMl9NSVJS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::dHJ1ZQ==::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::Mw==::TVIwX0NBU19MQVRFTkNZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::Mg==::TVIxX1JUVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MQ==::TVIyX0NXTA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::TUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::Mg==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTM=::TUVNX0lGX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTM=::TUVNX0lGX1JPV19BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::Mg==::TUVNX0lGX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::ZmFsc2U=::TUVNX0xFVkVMSU5H" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::Mg==::TnVtYmVyIG9mIERRUyBncm91cHM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::MTY=::TUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS41::TUVNX0NMS19NQVhfTlM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTUwMC4w::TUVNX0NMS19NQVhfUFM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTQ=::TUVNX1RGQVc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mw==::TUVNX1RSUkQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::NDUw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::Ng==::TUVNX1dUQ0xfSU5U" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::Mg==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::TWljcm9u::TWVtb3J5IHZlbmRvcg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgw::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::NjY2LjY2Nw==::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTM=::Um93IGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::MTY=::VG90YWwgaW50ZXJmYWNlIHdpZHRo" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::UlpRLzI=::T0RUIFJ0dCBub21pbmFsIHZhbHVl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::Ng==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::Nw==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTkw::dElTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTQw::dElIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MzA=::dERTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NjU=::dERIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTI1::dERRU1E=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjU1::dERRU0NL" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNQ==::dERRU1M=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4y::dERTSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4y::dERTUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzYuMA==::dFJBUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNQ==::dFJDRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNQ==::dFJQ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::NQ==::dFdUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::NDUuMA==::dEZBVw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ny41::dFJSRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURQ==::RnVsbA==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::MQ==::QUZJX1JBVEVfUkFUSU8=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::MTM=::QUZJX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Mw==::QUZJX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::MQ==::QUZJX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::MQ==::QUZJX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::MQ==::QUZJX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::MQ==::QUZJX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::ZmFsc2U=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::OA==::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::ZmFsc2U=::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::dHJ1ZQ==::SEFSRF9QSFk=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::dHJ1ZQ==::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::MTA=::Q1NSX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::OA==::Q1NSX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::MQ==::Q1NSX0JFX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTX1dJRFRI::MQ==::Q1RMX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0JFX1dJRFRI::NA==::QVZMX0JFX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX1NZTUJPTF9XSURUSA==::OA==::QVZMX1NZTUJPTF9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xT::NA==::QVZMX05VTV9TWU1CT0xT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX1NJWkVfV0lEVEg=::Mw==::QVZMX1NJWkVfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19DU1JfRU5BQkxFRA==::ZmFsc2U=::Q1RMX0VDQ19DU1JfRU5BQkxFRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFdJRFRIX1JBVElP::Mg==::RFdJRFRIX1JBVElP" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX09EVF9FTkFCTEVE::dHJ1ZQ==::Q1RMX09EVF9FTkFCTEVE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX09VVFBVVF9SRUdE::ZmFsc2U=::Q1RMX09VVFBVVF9SRUdE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::Q1RMX1JFR0RJTU1fRU5BQkxFRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TE9XX0xBVEVOQ1k=::ZmFsc2U=::TE9XX0xBVEVOQ1k=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9UWVBF::bmV4dGdlbl92MTEw::Q09OVFJPTExFUl9UWVBF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1RCUF9OVU0=::NA==::Q1RMX1RCUF9OVU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNI::MA==::Q1RMX1VTUl9SRUZSRVNI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSA==::MA==::Q1RMX1NFTEZfUkVGUkVTSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RZUEU=::Mg==::Q0ZHX1RZUEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0lOVEVSRkFDRV9XSURUSA==::MTY=::Q0ZHX0lOVEVSRkFDRV9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0JVUlNUX0xFTkdUSA==::OA==::Q0ZHX0JVUlNUX0xFTkdUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0FERFJfT1JERVI=::MA==::Q0ZHX0FERFJfT1JERVI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BETl9FWElUX0NZQ0xFUw==::MTA=::Q0ZHX1BETl9FWElUX0NZQ0xFUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw==::NQ==::Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT::MTA=::Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw==::NTEy::Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA=::MQ==::Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA==::MQ==::Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1dSSVRFX09EVF9DSElQ::MQ==::Q0ZHX1dSSVRFX09EVF9DSElQ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFQURfT0RUX0NISVA=::MA==::Q0ZHX1JFQURfT0RUX0NISVA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TE9DQUxfQ1NfV0lEVEg=::MA==::TE9DQUxfQ1NfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0NMUl9JTlRS::MA==::Q0ZHX0NMUl9JTlRS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0VOQUJMRV9OT19ETQ==::MA==::Q0ZHX0VOQUJMRV9OT19ETQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FERF9MQVQ=::MA==::TUVNX0FERF9MQVQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0VSUkNNRF9GSUZPX1JFRw==::MA==::Q0ZHX0VSUkNNRF9GSUZPX1JFRw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0VDQ19ERUNPREVSX1JFRw==::MA==::Q0ZHX0VDQ19ERUNPREVSX1JFRw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k=::ZmFsc2U=::Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1NUQVJWRV9MSU1JVA==::MTA=::Q0ZHX1NUQVJWRV9MSU1JVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fUERfQ1lDTEVT::MA==::TUVNX0FVVE9fUERfQ1lDTEVT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX1BPUlQ=::UG9ydCAw::UG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8w::MzI=::QVZMX0RBVEFfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8w::MjU=::QVZMX0FERFJfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8w::MQ==::UFJJT1JJVFlfUE9SVF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMA==::MA==::V0VJR0hUX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzA=::Mw==::Q1BPUlRfVFlQRV9QT1JUXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::NA==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMA==::MA==::TFNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMA==::MA==::TVNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMA==::MA==::TFNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMA==::MA==::TVNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8x::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8x::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8x::MQ==::UFJJT1JJVFlfUE9SVF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMQ==::MA==::V0VJR0hUX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1BPUlRfVFlQRV9QT1JUXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMQ==::NQ==::TFNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMQ==::NQ==::TVNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMQ==::NQ==::TFNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMQ==::NQ==::TVNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8y::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8y::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8y::MQ==::UFJJT1JJVFlfUE9SVF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMg==::MA==::V0VJR0hUX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1BPUlRfVFlQRV9QT1JUXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMg==::NQ==::TFNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMg==::NQ==::TVNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMg==::NQ==::TFNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMg==::NQ==::TVNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8z::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8z::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8z::MQ==::UFJJT1JJVFlfUE9SVF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMw==::MA==::V0VJR0hUX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1BPUlRfVFlQRV9QT1JUXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMw==::NQ==::TFNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMw==::NQ==::TVNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMw==::NQ==::TFNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMw==::NQ==::TVNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF80::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF80::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF80::MQ==::UFJJT1JJVFlfUE9SVF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNA==::MA==::V0VJR0hUX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1BPUlRfVFlQRV9QT1JUXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNA==::NQ==::TFNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNA==::NQ==::TVNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNA==::NQ==::TFNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNA==::NQ==::TVNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF81::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF81::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF81::MQ==::UFJJT1JJVFlfUE9SVF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNQ==::MA==::V0VJR0hUX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1BPUlRfVFlQRV9QT1JUXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNQ==::NQ==::TFNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNQ==::NQ==::TVNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNQ==::NQ==::TFNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNQ==::NQ==::TVNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfT05FX1JFU0VU::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX29uZV9yZXNldA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfWkVST19SRVNFVA==::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX3plcm9fcmVzZXQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX1NUQVRJQ19DT05GSUdfVkFMSUQ=::RElTQUJMRUQ=::YXR0cl9zdGF0aWNfY29uZmlnX3ZhbGlk" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DQUxfUkVR::RElTQUJMRUQ=::Y2FsX3JlcQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfQlVSU1RfTEVOR1RI::QkxfOA==::Y2ZnX2J1cnN0X2xlbmd0aA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfSU5URVJGQUNFX1dJRFRI::RFdJRFRIXzE2::Y2ZnX2ludGVyZmFjZV93aWR0aA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfU0VMRl9SRlNIX0VYSVRfQ1lDTEVT::U0VMRl9SRlNIX0VYSVRfQ1lDTEVTXzUxMg==::Y2ZnX3NlbGZfcmZzaF9leGl0X2N5Y2xlcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfU1RBUlZFX0xJTUlU::U1RBUlZFX0xJTUlUXzQ=::Y2ZnX3N0YXJ2ZV9saW1pdA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfVFlQRQ==::RERSMw==::Y2ZnX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMg==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMw==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTFJfSU5UUg==::Tk9fQ0xSX0lOVFI=::Y2xyX2ludHI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::VFJVRQ==::Y21kX3BvcnRfaW5fdXNlXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQwX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfVFlQRQ==::QklfRElSRUNUSU9O::Y3BvcnQwX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQxX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQyX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQzX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ0X3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ1X3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfQUREUl9PUkRFUg==::Q0hJUF9ST1dfQkFOS19DT0w=::Y3RsX2FkZHJfb3JkZXI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX0VOQUJMRUQ=::Q1RMX0VDQ19ESVNBQkxFRA==::Y3RsX2VjY19lbmFibGVk" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX1JNV19FTkFCTEVE::Q1RMX0VDQ19STVdfRElTQUJMRUQ=::Y3RsX2VjY19ybXdfZW5hYmxlZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfUkVHRElNTV9FTkFCTEVE::UkVHRElNTV9ESVNBQkxFRA==::Y3RsX3JlZ2RpbW1fZW5hYmxlZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfVVNSX1JFRlJFU0g=::Q1RMX1VTUl9SRUZSRVNIX0RJU0FCTEVE::Y3RsX3Vzcl9yZWZyZXNo" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVFJMX1dJRFRI::REFUQV9XSURUSF8zMl9CSVQ=::Y3RybF93aWR0aA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9ERUxBWV9CT05ESU5H::Qk9ORElOR19MQVRFTkNZXzA=::ZGVsYXlfYm9uZGluZw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9ERlhfQllQQVNTX0VOQUJMRQ==::REZYX0JZUEFTU19ESVNBQkxFRA==::ZGZ4X2J5cGFzc19lbmFibGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9ESVNBQkxFX01FUkdJTkc=::TUVSR0lOR19FTkFCTEVE::ZGlzYWJsZV9tZXJnaW5n" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FQ0NfRFFfV0lEVEg=::RUNDX0RRX1dJRFRIXzA=::ZWNjX2RxX3dpZHRo" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQVRQRw==::RElTQUJMRUQ=::ZW5hYmxlX2F0cGc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR19XUkFQQkFDSw==::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfd3JhcGJhY2s=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRFFTX1RSQUNLSU5H::RElTQUJMRUQ=::ZW5hYmxlX2Rxc190cmFja2luZw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRUNDX0NPREVfT1ZFUldSSVRFUw==::RElTQUJMRUQ=::ZW5hYmxlX2VjY19jb2RlX292ZXJ3cml0ZXM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRkFTVF9FWElUX1BQRA==::RElTQUJMRUQ=::ZW5hYmxlX2Zhc3RfZXhpdF9wcGQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfSU5UUg==::RElTQUJMRUQ=::ZW5hYmxlX2ludHI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfTk9fRE0=::RElTQUJMRUQ=::ZW5hYmxlX25vX2Rt" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfUElQRUxJTkVHTE9CQUw=::RElTQUJMRUQ=::ZW5hYmxlX3BpcGVsaW5lZ2xvYmFs" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9HQU5HRURfQVJG::RElTQUJMRUQ=::Z2FuZ2VkX2FyZg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fREJF::R0VOX0RCRV9ESVNBQkxFRA==::Z2VuX2RiZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fU0JF::R0VOX1NCRV9ESVNBQkxFRA==::Z2VuX3NiZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9JTkNfU1lOQw==::RklGT19TRVRfMg==::aW5jX3N5bmM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9MT0NBTF9JRl9DU19XSURUSA==::QUREUl9XSURUSF8w::bG9jYWxfaWZfY3Nfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0NPUlJfRFJPUFBFRF9JTlRS::RElTQUJMRUQ=::bWFza19jb3JyX2Ryb3BwZWRfaW50cg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0RCRV9JTlRS::RElTQUJMRUQ=::bWFza19kYmVfaW50cg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX1NCRV9JTlRS::RElTQUJMRUQ=::bWFza19zYmVfaW50cg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQUw=::QUxfMA==::bWVtX2lmX2Fs" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQkFOS0FERFJfV0lEVEg=::QUREUl9XSURUSF8z::bWVtX2lmX2JhbmthZGRyX3dpZHRo" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQlVSU1RMRU5HVEg=::TUVNX0lGX0JVUlNUTEVOR1RIXzg=::bWVtX2lmX2J1cnN0bGVuZ3Ro" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ09MQUREUl9XSURUSA==::QUREUl9XSURUSF8xMA==::bWVtX2lmX2NvbGFkZHJfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfUEVSX1JBTks=::TUVNX0lGX0NTX1BFUl9SQU5LXzE=::bWVtX2lmX2NzX3Blcl9yYW5r" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfV0lEVEg=::TUVNX0lGX0NTX1dJRFRIXzE=::bWVtX2lmX2NzX3dpZHRo" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFfUEVSX0NISVA=::TUVNX0lGX0RRX1BFUl9DSElQXzg=::bWVtX2lmX2RxX3Blcl9jaGlw" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFTX1dJRFRI::RFFTX1dJRFRIXzI=::bWVtX2lmX2Rxc193aWR0aA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFdJRFRI::TUVNX0lGX0RXSURUSF8xNg==::bWVtX2lmX2R3aWR0aA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfTUVNVFlQRQ==::RERSM19TRFJBTQ==::bWVtX2lmX21lbXR5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfUk9XQUREUl9XSURUSA==::QUREUl9XSURUSF8xMw==::bWVtX2lmX3Jvd2FkZHJfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfU1BFRURCSU4=::RERSM18xNjAwXzhfOF84::bWVtX2lmX3NwZWVkYmlu" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENDRA==::VENDRF80::bWVtX2lmX3RjY2Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENM::VENMXzc=::bWVtX2lmX3RjbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENXTA==::VENXTF82::bWVtX2lmX3Rjd2w=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVEZBVw==::VEZBV18xNA==::bWVtX2lmX3RmYXc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVE1SRA==::VE1SRF80::bWVtX2lmX3RtcmQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJBUw==::VFJBU18xMQ==::bWVtX2lmX3RyYXM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJD::VFJDXzE1::bWVtX2lmX3RyYw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJDRA==::VFJDRF81::bWVtX2lmX3RyY2Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJQ::VFJQXzU=::bWVtX2lmX3RycA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJSRA==::VFJSRF8z::bWVtX2lmX3RycmQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJUUA==::VFJUUF8z::bWVtX2lmX3RydHA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdS::VFdSXzU=::bWVtX2lmX3R3cg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdUUg==::VFdUUl81::bWVtX2lmX3R3dHI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NTVJfQ0ZHX01FTV9CTA==::TVBfQkxfOA==::bW1yX2NmZ19tZW1fYmw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9PVVRQVVRfUkVHRA==::RElTQUJMRUQ=::b3V0cHV0X3JlZ2Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QRE5fRVhJVF9DWUNMRVM=::U0xPV19FWElU::cGRuX2V4aXRfY3ljbGVz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDBfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDFfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMl9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDJfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUM19XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDNfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDRfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDVfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzMy::cmRfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8w::VFJVRQ==::cmRfZmlmb19pbl91c2VfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8x::RkFMU0U=::cmRfZmlmb19pbl91c2VfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8y::RkFMU0U=::cmRfZmlmb19pbl91c2VfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8z::RkFMU0U=::cmRfZmlmb19pbl91c2VfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFXzA=::cmRfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRUFEX09EVF9DSElQ::T0RUX0RJU0FCTEVE::cmVhZF9vZHRfY2hpcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRU9SREVSX0RBVEE=::Tk9fREFUQV9SRU9SREVSSU5H::cmVvcmRlcl9kYXRh" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMA==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMQ==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMg==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMw==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMg==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMw==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9URVNUX01PREU=::Tk9STUFMX01PREU=::dGVzdF9tb2Rl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMg==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMw==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMg==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMw==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzA=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzE=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzI=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzM=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX0VDQ19FTg==::RElTQUJMRQ==::dXNlcl9lY2NfZW4=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8wX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8xX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8yX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8zX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzMy::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8w::VFJVRQ==::d3JfZmlmb19pbl91c2VfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8x::RkFMU0U=::d3JfZmlmb19pbl91c2VfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8y::RkFMU0U=::d3JfZmlmb19pbl91c2VfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8z::RkFMU0U=::d3JfZmlmb19pbl91c2VfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFXzA=::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUklURV9PRFRfQ0hJUA==::V1JJVEVfQ0hJUDBfT0RUMF9DSElQMQ==::d3JpdGVfb2R0X2NoaXA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQVVUT19QRF9DWUNMRVM=::MA==::bWVtX2F1dG9fcGRfY3ljbGVz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMg==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMw==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1Q=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1RfRElGRl9CQU5L::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0X2RpZmZfYmFuaw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19QQ0g=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcGNo" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19SRFdS::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcmR3cg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfcGVyaW9k" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfdG9fdmFsaWQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0ZPVVJfQUNUX1RPX0FDVA==::MA==::ZXh0cmFfY3RsX2Nsa19mb3VyX2FjdF90b19hY3Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9BTExfVE9fVkFMSUQ=::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfYWxsX3RvX3ZhbGlk" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfdG9fdmFsaWQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fcGVyaW9k" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fdG9fdmFsaWQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa19yZF9hcF90b192YWxpZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19wY2g=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZF9kaWZmX2NoaXA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dS::Mg==::ZXh0cmFfY3RsX2Nsa19yZF90b193cg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0JD::Mg==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9iYw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0RJRkZfQ0hJUA==::Mg==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9kaWZmX2NoaXA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fdmFsaWQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19aUV9DQUw=::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fenFfY2Fs" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa193cl9hcF90b192YWxpZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19wY2g=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JE::Mw==::ZXh0cmFfY3RsX2Nsa193cl90b19yZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0JD::Mw==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9iYw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0RJRkZfQ0hJUA==::Mw==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9kaWZmX2NoaXA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cl9kaWZmX2NoaXA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJFRkk=::MjM0MQ==::bWVtX2lmX3RyZWZp" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJGQw==::MzQ=::bWVtX2lmX3RyZmM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BU0s=::MA==::YXR0cl9jb3VudGVyX29uZV9tYXNr" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BVENI::MA==::YXR0cl9jb3VudGVyX29uZV9tYXRjaA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVNL::MA==::YXR0cl9jb3VudGVyX3plcm9fbWFzaw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVRDSA==::MA==::YXR0cl9jb3VudGVyX3plcm9fbWF0Y2g=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0RFQlVHX1NFTEVDVF9CWVRF::MA==::YXR0cl9kZWJ1Z19zZWxlY3RfYnl0ZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19QT1dFUl9TQVZJTkdfRVhJVF9DWUNMRVM=::NQ==::cG93ZXJfc2F2aW5nX2V4aXRfY3ljbGVz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQ0xLX0VOVFJZX0NZQ0xFUw==::MTA=::bWVtX2Nsa19lbnRyeV9jeWNsZXM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfSU5URVJSVVBU::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X2ludGVycnVwdA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfVEVSTUlOQVRF::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X3Rlcm1pbmF0ZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8wX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MA==::YXZfcG9ydF8wX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8wX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MA==::Y3ZfcG9ydF8wX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w::MzI=::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w::MjU=::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA=::Mw==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::NA==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMA==::MA==::Q1ZfTFNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMA==::MA==::Q1ZfTVNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMA==::MA==::Q1ZfTFNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMA==::MA==::Q1ZfTVNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::VFJVRQ==::Y21kX3BvcnRfaW5fdXNlXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfVFlQRQ==::QklfRElSRUNUSU9O::Y3BvcnQwX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDBfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzMy::cmRfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFXzA=::cmRfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8w" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzMy::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFXzA=::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzA=::Mw==::VEdfVEVNUF9QT1JUXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8xX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MQ==::YXZfcG9ydF8xX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8xX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MQ==::Y3ZfcG9ydF8xX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDFfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8x" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzE=::MA==::VEdfVEVNUF9QT1JUXzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8yX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mg==::YXZfcG9ydF8yX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8yX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mg==::Y3ZfcG9ydF8yX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMl9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDJfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzI=::MA==::VEdfVEVNUF9QT1JUXzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8zX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mw==::YXZfcG9ydF8zX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8zX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mw==::Y3ZfcG9ydF8zX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUM19XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDNfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8z" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzM=::MA==::VEdfVEVNUF9QT1JUXzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF80X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NA==::YXZfcG9ydF80X2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF80X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NA==::Y3ZfcG9ydF80X2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDRfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV80" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzQ=::MA==::VEdfVEVNUF9QT1JUXzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF81X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NQ==::YXZfcG9ydF81X2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF81X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NQ==::Y3ZfcG9ydF81X2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDVfd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV81" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzU=::MA==::VEdfVEVNUF9QT1JUXzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw=::ZmFsc2U=::Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYMTBfQ0ZH::ZmFsc2U=::TUFYMTBfQ0ZH" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UE9XRVJfT0ZfVFdPX0JVUw==::ZmFsc2U=::R2VuZXJhdGUgcG93ZXItb2YtMiBkYXRhIGJ1cyB3aWR0aHMgZm9yIFFzeXMgb3IgU09QQyBCdWlsZGVy" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U09QQ19DT01QQVRfUkVTRVQ=::ZmFsc2U=::R2VuZXJhdGUgU09QQyBCdWlsZGVyIGNvbXBhdGlibGUgcmVzZXRz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX01BWF9TSVpF::NA==::TWF4aW11bSBBdmFsb24tTU0gYnVyc3QgbGVuZ3Ro" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEU=::dHJ1ZQ==::RW5hYmxlIEF2YWxvbi1NTSBieXRlLWVuYWJsZSBzaWduYWw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NUUkxfQVZBTE9OX0lOVEVSRkFDRQ==::dHJ1ZQ==::RW5hYmxlIEF2YWxvbiBpbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0RFRVBfUE9XRVJETl9FTg==::ZmFsc2U=::RW5hYmxlIERlZXAgUG93ZXItRG93biBDb250cm9scw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSF9FTg==::ZmFsc2U=::RW5hYmxlIFNlbGYtUmVmcmVzaCBDb250cm9scw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19QT1dFUkROX0VO::ZmFsc2U=::RW5hYmxlIEF1dG8gUG93ZXItRG93bg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNIX0VO::ZmFsc2U=::RW5hYmxlIFVzZXIgQXV0by1SZWZyZXNoIENvbnRyb2xz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0FVVE9QQ0hfRU4=::ZmFsc2U=::RW5hYmxlIEF1dG8tUHJlY2hhcmdlIENvbnRyb2w=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1pRQ0FMX0VO::ZmFsc2U=::RW5hYmxlIFpRIENhbGlicmF0aW9uIENvbnRyb2w=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9PUkRFUg==::MA==::TG9jYWwtdG8tTWVtb3J5IEFkZHJlc3MgTWFwcGluZw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9MQVRFTkNZ::NQ==::UmVkdWNlIENvbnRyb2xsZXIgTGF0ZW5jeSBCeQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFT1JERVJfREFUQQ==::ZmFsc2U=::RW5hYmxlIFJlb3JkZXJpbmc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9FTkFCTEVE::dHJ1ZQ==::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19FTkFCTEVE::ZmFsc2U=::RW5hYmxlIEVycm9yIERldGVjdGlvbiBhbmQgQ29ycmVjdGlvbiBMb2dpYw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVVMVElDQVNUX0VO::ZmFsc2U=::RW5hYmxlIE11bHRpLWNhc3QgV3JpdGUgQ29udHJvbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0RZTkFNSUNfQkFOS19BTExPQ0FUSU9O::ZmFsc2U=::RW5hYmxlIHJlZHVjZWQgYmFuayB0cmFja2luZyBmb3IgYXJlYSBvcHRpbWl6YXRpb24=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVCVUdfTU9ERQ==::ZmFsc2U=::RW5hYmxlIGludGVybmFsIGRlYnVnIHBhcmFtZXRlcg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JVUlNUX01FUkdF::ZmFsc2U=::RW5hYmxlIGJ1cnN0IG1lcmdpbmc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFQ=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IGludGVycnVwdA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEU=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IHRlcm1pbmF0ZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TE9DQUxfSURfV0lEVEg=::OA==::TG9jYWwgSUQgd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRCVUZGRVJfQUREUl9XSURUSA==::OA==::UmVhZCBidWZmZXIgYWRkcmVzcyB3aWR0aA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V1JCVUZGRVJfQUREUl9XSURUSA==::Ng==::V3JpdGUgYnVmZmVyIGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfV1JfQ01E::MTY=::TWF4IHBlbmRpbmcgd3JpdGUgY29tbWFuZHM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfUkRfQ01E::MzI=::TWF4IHBlbmRpbmcgcmVhZCBjb21tYW5kcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01NX0FEQVBUT1I=::dHJ1ZQ==::VXNlIEF2YWxvbiBNTSBBZGFwdG9y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FYSV9BREFQVE9S::ZmFsc2U=::VXNlIEFYSSBBZGFwdG9y" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NNRF9RVUVVRV9ERVBUSA==::OA==::Q1RMX0NNRF9RVUVVRV9ERVBUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9SRUFEX09OTFk=::MQ==::Q1RMX0NTUl9SRUFEX09OTFk=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX09GX1BPUlRT::MQ==::TnVtYmVyIG9mIHBvcnRz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JPTkRJTkc=::ZmFsc2U=::RXhwb3J0IGJvbmRpbmcgaW50ZXJmYWNl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1VTRVJfRUND::ZmFsc2U=::RXhwYW5kIEF2YWxvbi1NTSBkYXRhIGZvciBFQ0M=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVA==::MzIsMzIsMzIsMzIsMzIsMzI=::V2lkdGg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVA==::MSwxLDEsMSwxLDE=::UHJpb3JpdHk=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlQ=::MCwwLDAsMCwwLDA=::V2VpZ2h0" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JU::QmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWwsQmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWw=::VHlwZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::dHJ1ZQ==::R0VORVJJQ19QTEw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::ZmFsc2U=::UkVBRF9GSUZPX0hBTEZfUkFURQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTUx::UEhZX1ZFUlNJT05fTlVNQkVS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::dHJ1ZQ==::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::dHJ1ZQ==::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::dHJ1ZQ==::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::RlVMTA==::VEJfUkFURQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::MTY=::VEJfTUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::NTAuMA==::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::NTAuMCBNSHo=::UkVGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MjAuMA==::UkVGX0NMS19OUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MjAwMDAuMA==::UkVGX0NMS19QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MTAwMDAwMA==::UExMX01FTV9DTEtfRElW" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElW" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MTUwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU1RS::NjAuMCBNSHo=::UExMX05JT1NfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==::NDE2IHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::OS4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::NDYz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MTAuMA==::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=::MjAuMCBNSHo=::UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElW" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS::MzAwLjAgTUh6::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::ZmFsc2U=::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MC4w::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::MC4w::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MA==::UExMX01FTV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX01FTV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::MA==::UExMX0FGSV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::MA==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MA==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::MA==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MA==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::MA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MA==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MA==::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREVfQ0FDSEU=::OA==::U1BFRURfR1JBREVfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::TUVNX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::NTAuMA==::UkVGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::RnVsbA==::UkFURV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::TklPUw==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::ZmFsc2U=::UExMX0NMS19QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MQ==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NQ==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::dHJ1ZQ==::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::Mg==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::MA==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::MA==::RFFTX1BIQVNFX1NISUZU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::NA==::SU9fRFFTX0lOX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::NA==::SU9fRFFTX09VVF9SRVNFUlZF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MA==::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::OA==::Q0FMSUJfTEZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::Ng==::Q0FMSUJfVkZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::MjU=::REVMQVlfUEVSX0RDSEFJTl9UQVA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::MjU=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::MzE=::RFFTX0VOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MzE=::RFFTX0lOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MzE=::SU9fSU5fREVMQVlfTUFY" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MzE=::SU9fT1VUMV9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::MA==::SU9fT1VUMl9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::Ng==::TUVNX1RfV0w=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::Nw==::TUVNX1RfUkw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::dHJ1ZQ==::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::ZmFsc2U=::TUFYMTBfUlRMX1NFUQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::UXVpY2s=::QXV0by1jYWxpYnJhdGlvbiBtb2Rl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zNA==::dElT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yNA==::dElI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xOA==::dERT" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNjU=::dERI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC42::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC42::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::LTAuMDE=::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::LTAuMDE=::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wMQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wMQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wMg==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYUE9SVF9TRVFfREVCVUdfQlJJREdF::ZmFsc2U=::RW5hYmxlIEVNSUYgT24tQ2hpcCBEZWJ1ZyBQb3J0" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09SRV9ERUJVR19DT05ORUNUSU9O::RVhQT1JU::RU1JRiBPbi1DaGlwIERlYnVnIFBvcnQgaW50ZXJmYWNlIHR5cGU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREX0VYVEVSTkFMX1NFUV9ERUJVR19OSU9T::ZmFsc2U=::QWRkIGV4dGVybmFsIE5pb3MgdG8gY29ubmVjdCB0byBzZXF1ZW5jZXIgZGVidWcgaW50ZXJmYWNl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RURfRVhQT1JUX1NFUV9ERUJVRw==::ZmFsc2U=::RXhwb3J0IHNlcXVlbmNlciBkZWJ1ZyBpbnRlcmZhY2UgZnJvbSBleGFtcGxlIGRlc2lnbg==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREX0VGRklDSUVOQ1lfTU9OSVRPUg==::ZmFsc2U=::RW5hYmxlIHRoZSBFZmZpY2llbmN5IE1vbml0b3IgYW5kIFByb3RvY29sIENoZWNrZXIgb24gdGhlIENvbnRyb2xsZXIgQXZhbG9uIEludGVyZmFjZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FCU19SQU1fTUVNX0lOSVQ=::ZmFsc2U=::RW5hYmxlIHN1cHBvcnQgZm9yIE5pb3MgSUkgTW9kZWxTaW0gZmxvdyBpbiBFY2xpcHNl" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FCU19SQU1fSU5URVJOQUw=::ZmFsc2U=::RU5BQkxFX0FCU19SQU1fSU5URVJOQUw=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FCU1RSQUNUX1JBTQ==::ZmFsc2U=::RU5BQkxFX0FCU1RSQUNUX1JBTQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUJTX1JBTV9NRU1fSU5JVF9GSUxFTkFNRQ==::bWVtaW5pdA==::TWVtb3J5IGluaXRpYWxpemF0aW9uIGZpbGUgYmFzZW5hbWU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Nw==::RExMX0RFTEFZX0NUUkxfV0lEVEg=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==::MTY=::T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::T0NUIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFQkEyRjE3QTc=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX3Jlc2V0X2NvbnRyb2xsZXI=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIFJlc2V0IENvbnRyb2xsZXI=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "Rm9yIHN5c3RlbXMgd2l0aCBtdWx0aXBsZSByZXNldCBpbnB1dHMsIHRoZSBNZXJsaW4gUmVzZXQgQ29udHJvbGxlciBPUnMgYWxsIHJlc2V0IGlucHV0cyBhbmQgZ2VuZXJhdGVzIGEgc2luZ2xlIHJlc2V0IG91dHB1dC4=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1JFU0VUX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIGlucHV0cw==" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUUFVUX1JFU0VUX1NZTkNfRURHRVM=::ZGVhc3NlcnQ=::T3V0cHV0IFJlc2V0IFN5bmNocm9ub3VzIEVkZ2Vz" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lOQ19ERVBUSA==::Mg==::U3luY2hyb25pemVyIGRlcHRo" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRVUVTVF9QUkVTRU5U::MA==::UmVzZXQgcmVxdWVzdCBsb2dpYyBlbmFibGU=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX1dBSVRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCB3YWl0IHRpbWU=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUlOX1JTVF9BU1NFUlRJT05fVElNRQ==::Mw==::TWluaW11bSByZXNldCBhc3NlcnRpb24gdGltZQ==" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX0VBUkxZX0RTUlRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCBkZWFzc2VydCB0aW1pbmc=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4w::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjA=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4x::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4y::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjI=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4z::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjM=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU40::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjQ=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU41::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjU=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU42::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjY=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU43::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjc=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU44::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjg=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU45::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjk=" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEw" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEx" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMg==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEy" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMw==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEz" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE0" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE1" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU5QVVQ=::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcmVzZXRfaW5wdXRz" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURBUFRfUkVTRVRfUkVRVUVTVA==::MA==::T25seSBhZGFwdCBvbmx5IHJlc2V0IHJlcXVlc3Q=" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMg==" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TU0gSW50ZXJjb25uZWN0" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "TU0gSW50ZXJjb25uZWN0" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFQkEyRjE3QTc=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9hdmFsb25fc3RfYWRhcHRlcl8wMDE=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEFkYXB0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QWRhcHQgbWlzbWF0Y2hlZCBBdmFsb24tU1QgZW5kcG9pbnRz" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MTA=::U3ltYm9sIFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::MA==::VXNlIFBhY2tldA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5EYXRhV2lkdGg=::MTA=::U291cmNlIERhdGEgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::U291cmNlIE1heCBDaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::U291cmNlIENoYW5uZWwgUG9ydCBXaWR0aA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::U291cmNlIEVycm9yIFBvcnQgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::MA==::U291cmNlIFVzZXMgRW1wdHkgUG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FbXB0eVdpZHRo::MQ==::U291cmNlIEVtcHR5IFBvcnQgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::MQ==::U291cmNlIFVzZXMgVmFsaWQgUG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::MQ==::U291cmNlIFVzZXMgUmVhZHkgUG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::U291cmNlIFJlYWR5IExhdGVuY3k=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RGF0YVdpZHRo::MTA=::U2luayBEYXRhIFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::U2luayBNYXggQ2hhbm5lbA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::U2luayBDaGFubmVsIFBvcnQgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::U2luayBFcnJvciBQb3J0IFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlRW1wdHlQb3J0::MA==::U2luayBVc2VzIEVtcHR5IFBvcnQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RW1wdHlXaWR0aA==::MQ==::U2luayBFbXB0eSBQb3J0IFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::MQ==::U2luayBVc2VzIFZhbGlkIFBvcnQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::MQ==::U2luayBVc2VzIFJlYWR5IFBvcnQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::U2luayBSZWFkeSBMYXRlbmN5" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFQkEyRjE3QTc=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9hdmFsb25fc3RfYWRhcHRlcl8wMDFfZXJyb3JfYWRhcHRlcl8w" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEVycm9yIEFkYXB0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MTA=::RGF0YSBCaXRzIFBlciBTeW1ib2w=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::ZmFsc2U=::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9hdmFsb25fc3RfYWRhcHRlcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEFkYXB0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QWRhcHQgbWlzbWF0Y2hlZCBBdmFsb24tU1QgZW5kcG9pbnRz" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MzQ=::U3ltYm9sIFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::MA==::VXNlIFBhY2tldA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5EYXRhV2lkdGg=::MzQ=::U291cmNlIERhdGEgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::U291cmNlIE1heCBDaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::U291cmNlIENoYW5uZWwgUG9ydCBXaWR0aA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::U291cmNlIEVycm9yIFBvcnQgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::MA==::U291cmNlIFVzZXMgRW1wdHkgUG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FbXB0eVdpZHRo::MQ==::U291cmNlIEVtcHR5IFBvcnQgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::MQ==::U291cmNlIFVzZXMgVmFsaWQgUG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::MQ==::U291cmNlIFVzZXMgUmVhZHkgUG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::U291cmNlIFJlYWR5IExhdGVuY3k=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RGF0YVdpZHRo::MzQ=::U2luayBEYXRhIFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::U2luayBNYXggQ2hhbm5lbA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::U2luayBDaGFubmVsIFBvcnQgV2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::U2luayBFcnJvciBQb3J0IFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlRW1wdHlQb3J0::MA==::U2luayBVc2VzIEVtcHR5IFBvcnQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RW1wdHlXaWR0aA==::MQ==::U2luayBFbXB0eSBQb3J0IFdpZHRo" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::MQ==::U2luayBVc2VzIFZhbGlkIFBvcnQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::MQ==::U2luayBVc2VzIFJlYWR5IFBvcnQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::U2luayBSZWFkeSBMYXRlbmN5" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFQkEyRjE3QTc=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9hdmFsb25fc3RfYWRhcHRlcl9lcnJvcl9hZGFwdGVyXzA=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEVycm9yIEFkYXB0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MzQ=::RGF0YSBCaXRzIFBlciBTeW1ib2w=" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::ZmFsc2U=::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl93aWR0aF9hZGFwdGVy" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBXaWR0aCBBZGFwdGVy" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgYmV0d2VlbiBBdmFsb24tTU0gbWFzdGVyIGFuZCBzbGF2ZXMgd2l0aCBkaWZmZXJlbnQgZGF0YSBhbmQgYnl0ZSBlbmFibGUgd2lkdGhzLg==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0FERFJfSA==::NDA=::SW5wdXQgcGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0FERFJfTA==::OQ==::SW5wdXQgcGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0RBVEFfSA==::Nw==::SW5wdXQgcGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0RBVEFfTA==::MA==::SW5wdXQgcGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVFTl9I::OA==::SW5wdXQgcGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVFTl9M::OA==::SW5wdXQgcGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVfQ05UX0g=::NDk=::SW5wdXQgcGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVfQ05UX0w=::NDc=::SW5wdXQgcGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::NDE=::SW5wdXQgcGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1RSQU5TX1dSSVRF::NDM=::SW5wdXQgcGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUV1JBUF9I::NTA=::SW5wdXQgcGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUV1JBUF9M::NTA=::SW5wdXQgcGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1NJWkVfSA==::NTM=::SW5wdXQgcGFja2V0IGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1NJWkVfTA==::NTE=::SW5wdXQgcGFja2V0IGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1JFU1BPTlNFX1NUQVRVU19I::NzE=::SW5wdXQgcGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1JFU1BPTlNFX1NUQVRVU19M::NzA=::SW5wdXQgcGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1RSQU5TX0VYQ0xVU0lWRQ==::NDY=::SW5wdXQgcGFja2V0IGV4Y2x1c2l2ZSB0cmFucyBmaWVsZA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1RZUEVfSA==::NTU=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1RZUEVfTA==::NTQ=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX09SSV9CVVJTVF9TSVpFX0w=::NzI=::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fUEtUX09SSV9CVVJTVF9TSVpFX0g=::NzQ=::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fU1RfREFUQV9X::NzU=::SW5wdXQgZGF0YSB3aWR0aA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9BRERSX0g=::Njc=::T3V0cHV0IHBhY2tldCBhZGRyZXNzIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9BRERSX0w=::MzY=::T3V0cHV0IHBhY2tldCBhZGRyZXNzIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9EQVRBX0g=::MzE=::T3V0cHV0IHBhY2tldCBieXRlZW5hYmxlIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9EQVRBX0w=::MA==::T3V0cHV0IHBhY2tldCBieXRlZW5hYmxlIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFRU5fSA==::MzU=::T3V0cHV0IHBhY2tldCBieXRlIGNvdW50IGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFRU5fTA==::MzI=::T3V0cHV0IHBhY2tldCBieXRlIGNvdW50IGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFX0NOVF9I::NzY=::T3V0cHV0IHBhY2tldCBidXJzdHdyYXAgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFX0NOVF9M::NzQ=::T3V0cHV0IHBhY2tldCBidXJzdHdyYXAgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9UUkFOU19DT01QUkVTU0VEX1JFQUQ=::Njg=::T3V0cHV0IHBhY2tldCBkYXRhIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9TSVpFX0g=::ODA=::T3V0cHV0IHBhY2tldCBidXJzdCBzaXplIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9TSVpFX0w=::Nzg=::T3V0cHV0IHBhY2tldCBidXJzdCBzaXplIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9SRVNQT05TRV9TVEFUVVNfSA==::OTg=::T3V0cHV0IHBhY2tldCByZXNwb25zZSBzdGF0dXMgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9SRVNQT05TRV9TVEFUVVNfTA==::OTc=::T3V0cHV0IHBhY2tldCByZXNwb25zZSBzdGF0dXMgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9UUkFOU19FWENMVVNJVkU=::NzM=::T3V0cHV0IHBhY2tldCBleGNsdXNpdmUgdHJhbnMgZmllbGQ=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9UWVBFX0g=::ODI=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9UWVBFX0w=::ODE=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9PUklfQlVSU1RfU0laRV9M::OTk=::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9PUklfQlVSU1RfU0laRV9I::MTAx::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX1NUX0RBVEFfVw==::MTAy::T3V0cHV0IHBhY2tldCBkYXRhIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1BUSU1JWkVfRk9SX1JTUA==::MQ==::T3B0aW1pemUgZm9yIHJlc3BvbnNl" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVTUE9OU0VfUEFUSA==::MQ==::UmVzcG9uc2Ugd2lkdGggYWRhcHRlcg==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09OU1RBTlRfQlVSU1RfU0laRQ==::MQ==::U3lzdGVtIG9ubHkgaGF2ZSBjb25zdGFudCBidXJzdCBzaXpl" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFDS0lORw==::MQ==::TmFycm93LXRvLVdpZGUgcGFja2luZw==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fTUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoNzQ6NzIpIHJlc3BvbnNlX3N0YXR1cyg3MTo3MCkgY2FjaGUoNjk6NjYpIHByb3RlY3Rpb24oNjU6NjMpIHRocmVhZF9pZCg2MikgZGVzdF9pZCg2MSkgc3JjX2lkKDYwKSBxb3MoNTkpIGJlZ2luX2J1cnN0KDU4KSBkYXRhX3NpZGViYW5kKDU3KSBhZGRyX3NpZGViYW5kKDU2KSBidXJzdF90eXBlKDU1OjU0KSBidXJzdF9zaXplKDUzOjUxKSBidXJzdHdyYXAoNTApIGJ5dGVfY250KDQ5OjQ3KSB0cmFuc19leGNsdXNpdmUoNDYpIHRyYW5zX2xvY2soNDUpIHRyYW5zX3JlYWQoNDQpIHRyYW5zX3dyaXRlKDQzKSB0cmFuc19wb3N0ZWQoNDIpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg0MSkgYWRkcig0MDo5KSBieXRlZW4oOCkgZGF0YSg3OjAp::SW5wdXQgTWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX01FUkxJTl9QQUNLRVRfRk9STUFU::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvciAtIG91dHB1dA==" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9TSVpFX1c=::Mw==::Q29tbWFuZC1zaXplIGlucHV0IHdpZHRo" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FERFJFU1NfQUxJR05NRU5U::MA==::QWRkcmVzcyBhbGlnbm1lbnQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9yc3BfbXV4" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Mg==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::bm8tYXJi::QXJiaXRyYXRpb24gc2NoZW1l" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwx::QXJiaXRyYXRpb24gc2hhcmVz" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9yc3BfZGVtdXg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::UGFja2V0IGRhdGEgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::MQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9jbWRfbXV4" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MQ==::QXJiaXRyYXRpb24gc2hhcmVz" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9jbWRfZGVtdXg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::UGFja2V0IGRhdGEgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Mg==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::Mg==::VmFsaWQgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9idXJzdF9hZGFwdGVy" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBCdXJzdCBBZGFwdGVy" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QWNjb21tb2RhdGVzIHRoZSBidXJzdCBjYXBhYmlsaXRpZXMgb2YgZWFjaCBpbnRlcmZhY2UgaW4gdGhlIHN5c3RlbSwgaW5jbHVkaW5nIGludGVyZmFjZXMgdGhhdCBkbyBub3Qgc3VwcG9ydCBidXJzdCB0cmFuc2ZlcnMsIHRyYW5zbGF0aW5nIGJ1cnN0IHNpemVzIGFzIHJlcXVpcmVkLg==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NDA=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::OQ==::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::NTg=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::NDk=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NDc=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::OA==::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::OA==::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::NTM=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::NTE=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfSA==::NTU=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfTA==::NTQ=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::NTA=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::NTA=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::NDE=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NDM=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NDQ=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX05BUlJPV19TSVpF::MA==::c2xhdmUgbmFycm93IHNpemVkIG91dHB1dA==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5fTkFSUk9XX1NJWkU=::MA==::c2xhdmUgbmFycm93IHNpemVkIG91dHB1dA==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX0ZJWEVE::MA==::c2xhdmUgZml4ZWQgb3V0cHV0" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX0NPTVBMRVRFX1dSQVA=::MA==::c2xhdmUgY29tcGxldGUgd3JhcCBvdXRwdXQ=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::NzU=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX0JZVEVfQ05UX0g=::NDc=::TWF4aW11bSBvdXRwdXQgcGFja2V0IGJ5dGUgY291bnQgaW5kZXg=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "T1VUX0JVUlNUV1JBUF9I::NTA=::TWF4aW11bSBvdXRwdXQgcGFja2V0IGJ1cnN0d3JhcCBpbmRleA==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoNzQ6NzIpIHJlc3BvbnNlX3N0YXR1cyg3MTo3MCkgY2FjaGUoNjk6NjYpIHByb3RlY3Rpb24oNjU6NjMpIHRocmVhZF9pZCg2MikgZGVzdF9pZCg2MSkgc3JjX2lkKDYwKSBxb3MoNTkpIGJlZ2luX2J1cnN0KDU4KSBkYXRhX3NpZGViYW5kKDU3KSBhZGRyX3NpZGViYW5kKDU2KSBidXJzdF90eXBlKDU1OjU0KSBidXJzdF9zaXplKDUzOjUxKSBidXJzdHdyYXAoNTApIGJ5dGVfY250KDQ5OjQ3KSB0cmFuc19leGNsdXNpdmUoNDYpIHRyYW5zX2xvY2soNDUpIHRyYW5zX3JlYWQoNDQpIHRyYW5zX3dyaXRlKDQzKSB0cmFuc19wb3N0ZWQoNDIpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg0MSkgYWRkcig0MDo5KSBieXRlZW4oOCkgZGF0YSg3OjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NUFJFU1NFRF9SRUFEX1NVUFBPUlQ=::MA==::Q29tcHJlc3NlZCByZWFkIHN1cHBvcnQ=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9TWU5USEVTSVM=::MQ==::Qnl0ZWVuYWJsZSBTeW50aGVzaXMgU3VwcG9ydA==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElQRV9JTlBVVFM=::MA==::QnVyc3QgYWRhcHRlciBpbnB1dCBwaXBlbGluZQ==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9fV1JBUF9TVVBQT1JU::MA==::Tm8gd3JhcCBjYWxjdWxhdGlvbiBzdXBwb3J0" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DT01QTEVURV9XUkFQX1NVUFBPUlQ=::MA==::SW4tY29tcGxldGVkIHdyYXAgY2FsY3VsYXRpb24gc3VwcG9ydA==" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "QlVSU1RXUkFQX0NPTlNUX01BU0s=::MQ==::QnVyc3R3cmFwLWNvbnN0YW50IG1hc2s=" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "QlVSU1RXUkFQX0NPTlNUX1ZBTFVF::MQ==::QnVyc3R3cmFwLWNvbnN0YW50IHZhbHVl" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURBUFRFUl9WRVJTSU9O::MTMuMQ==::U2VsZWN0IGJ1cnN0IGFkYXB0ZXIgdmVyc2lvbg==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl90cmFmZmljX2xpbWl0ZXI=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBUcmFmZmljIExpbWl0ZXI=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RW5zdXJlcyB0aGUgcmVzcG9uc2VzIGFycml2ZSBpbiBvcmRlciwgc2ltcGxpZnlpbmcgdGhlIFFzeXMgcmVzcG9uc2UgbmV0d29yay4=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::NzY=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzQ=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::Njk=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9I::ODk=::UGFja2V0IHRocmVhZCBJRCBmaWVsZCBpbmRleCBNU0I=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9M::ODk=::UGFja2V0IHRocmVhZCBJRCBmaWVsZCBpbmRleCBMU0I=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0xFTkdUSA==::MQ==::TWF4aW11bSBidXJzdCBsZW5ndGg=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX09VVFNUQU5ESU5HX1JFU1BPTlNFUw==::Ng==::TWF4aW11bSBvdXRzdGFuZGluZyByZXNwb25zZXM=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVE::MA==::UGlwZWxpbmU=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::Mg==::VmFsaWQgd2lkdGg=" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5GT1JDRV9PUkRFUg==::MQ==::RW5mb3JjZSBvcmRlcg==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFVkVOVF9IQVpBUkRT::MA==::UHJldmVudCBoYXphcmRz" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1VQUE9SVFNfUE9TVEVEX1dSSVRFUw==::MQ==::SGF6YXJkIHByZXZlbnRpb246IHBvc3RlZCB3cml0ZSBzdXBwb3J0" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1VQUE9SVFNfTk9OUE9TVEVEX1dSSVRFUw==::MA==::SGF6YXJkIHByZXZlbnRpb246IG5vbi1wb3N0ZWQgd3JpdGUgc3VwcG9ydA==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVPUkRFUg==::MA==::RW5hYmxlIHJlb3JkZXIgYnVmZmVy" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9yb3V0ZXJfMDAy" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MA==::RGVzdGluYXRpb24gSUQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NDA=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::OQ==::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::NjU=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::NjM=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::NjE=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::NjE=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NDM=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NDQ=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::NzU=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDoxOjB4MDoweDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoNzQ6NzIpIHJlc3BvbnNlX3N0YXR1cyg3MTo3MCkgY2FjaGUoNjk6NjYpIHByb3RlY3Rpb24oNjU6NjMpIHRocmVhZF9pZCg2MikgZGVzdF9pZCg2MSkgc3JjX2lkKDYwKSBxb3MoNTkpIGJlZ2luX2J1cnN0KDU4KSBkYXRhX3NpZGViYW5kKDU3KSBhZGRyX3NpZGViYW5kKDU2KSBidXJzdF90eXBlKDU1OjU0KSBidXJzdF9zaXplKDUzOjUxKSBidXJzdHdyYXAoNTApIGJ5dGVfY250KDQ5OjQ3KSB0cmFuc19leGNsdXNpdmUoNDYpIHRyYW5zX2xvY2soNDUpIHRyYW5zX3JlYWQoNDQpIHRyYW5zX3dyaXRlKDQzKSB0cmFuc19wb3N0ZWQoNDIpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg0MSkgYWRkcig0MDo5KSBieXRlZW4oOCkgZGF0YSg3OjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9yb3V0ZXJfMDAx" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MA==::RGVzdGluYXRpb24gSUQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTA=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDoxOjB4MDoweDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMl9yb3V0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MSww::RGVzdGluYXRpb24gSUQ=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDEsMTA=::QmluYXJ5IENoYW5uZWwgU3RyaW5n" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3Ro::VHlwZSBvZiBUcmFuc2FjdGlvbg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4NDAw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHg0MDAsMHg4MDA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwx::Tm9uLXNlY3VyZWQgdGFncw==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCww::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCww::U2VjdXJlZCByYW5nZSBwYWlycw==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTA=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MTowMToweDA6MHg0MDA6Ym90aDoxOjA6MDoxLDA6MTA6MHg0MDA6MHg4MDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8=" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MQ==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zY19maWZv" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFNpbmdsZSBDbG9jayBGSUZP" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lNQk9MU19QRVJfQkVBVA==::MQ==::U3ltYm9scyBwZXIgYmVhdA==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "QklUU19QRVJfU1lNQk9M::OA==::Qml0cyBwZXIgc3ltYm9s" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "RklGT19ERVBUSA==::NjQ=::RklGTyBkZXB0aA==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSA==::MA==::Q2hhbm5lbCB3aWR0aA==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MA==::RXJyb3Igd2lkdGg=" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1BBQ0tFVFM=::MA==::VXNlIHBhY2tldHM=" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZJTExfTEVWRUw=::MA==::VXNlIGZpbGwgbGV2ZWw=" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU1QVFlfTEFURU5DWQ==::Mw==::TGF0ZW5jeQ==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTU9SWV9CTE9DS1M=::MQ==::VXNlIG1lbW9yeSBibG9ja3M=" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NUT1JFX0ZPUldBUkQ=::MA==::VXNlIHN0b3JlIGFuZCBmb3J3YXJk" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FMTU9TVF9GVUxMX0lG::MA==::VXNlIGFsbW9zdCBmdWxsIHN0YXR1cw==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FMTU9TVF9FTVBUWV9JRg==::MA==::VXNlIGFsbW9zdCBlbXB0eSBzdGF0dXM=" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYUExJQ0lUX01BWENIQU5ORUw=::ZmFsc2U=::RW5hYmxlIGV4cGxpY2l0IG1heENoYW5uZWw=" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQTElDSVRfTUFYQ0hBTk5FTA==::MA==::RXhwbGljaXQgbWF4Q2hhbm5lbA==" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9zbGF2ZV9hZ2VudA==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIFNsYXZlIEFnZW50" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjb21tYW5kIHBhY2tldHMgYW5kIGlzc3VlcyB0aGUgcmVzdWx0aW5nIHRyYW5zYWN0aW9ucyB0byB0aGUgQXZhbG9uIGludGVyZmFjZS4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgZXhwbGFuYXRpb25zIG9mIHRoZSBidXJzdGluZyBwcm9wZXJ0aWVzLg==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0g=::MTAx::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0w=::OTk=::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19I::OTg=::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19M::OTc=::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::ODA=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::Nzg=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::ODU=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTI=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTA=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::NzY=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzQ=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::Njg=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::Njk=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfSA==::MzE=::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfTA==::MA==::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1NZTUJPTF9X::OA==::UGFja2V0IHN5bWJvbCB3aWR0aA==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfU1lNQk9MUw==::MA==::YnVyc3Rjb3VudFN5bWJvbHM=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfVw==::Mw==::YnVyc3Rjb3VudCB3aWR0aA==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1VQUFJFU1NfMF9CWVRFRU5fQ01E::MA==::U3VwcHJlc3MgMC1ieXRlZW5hYmxlIHRyYW5zYWN0aW9ucw==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFVkVOVF9GSUZPX09WRVJGTE9X::MQ==::UHJldmVudCBGSUZPIG92ZXJmbG93" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX0JZVEVfQ05U::NA==::TWF4aW11bSBieXRlLWNvdW50IHZhbHVl" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUV1JBUA==::MQ==::TWF4aW11bSBidXJzdHdyYXAgdmFsdWU=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "SUQ=::MQ==::U2xhdmUgSUQ=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ==" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "RUNDX0VOQUJMRQ==::MA==::RUNDX0VOQUJMRQ==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9tYXN0ZXJfYWdlbnQ=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIE1hc3RlciBBZ2VudA==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "VHJhbnNsYXRlcyBBdmFsb24tTU0gbWFzdGVyIHRyYW5zYWN0aW9ucyBpbnRvIFFzeXMgY29tbWFuZCBwYWNrZXRzIGFuZCB0cmFuc2xhdGVzIHRoZSBRc3lzIEF2YWxvbi1NTSBzbGF2ZSByZXNwb25zZSBwYWNrZXRzIGludG8gQXZhbG9uLU1NIHJlc3BvbnNlcy4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgYW4gZXhwbGFuYXRpb24gb2YgYnVyc3RpbmcgYmVoYXZpb3Iu" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0g=::MTAx::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0w=::OTk=::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19I::OTg=::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19M::OTc=::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1FPU19I::ODY=::UGFja2V0IHFvcyBzaWRlYmFuZCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1FPU19M::ODY=::UGFja2V0IHFvcyBzaWRlYmFuZCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfU0lERUJBTkRfSA==::ODQ=::UGFja2V0IGRhdGEgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfU0lERUJBTkRfTA==::ODQ=::UGFja2V0IGRhdGEgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfU0lERUJBTkRfSA==::ODM=::UGFja2V0IGFkZHJlc3Mgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfU0lERUJBTkRfTA==::ODM=::UGFja2V0IGFkZHJlc3Mgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfSA==::ODI=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfTA==::ODE=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0NBQ0hFX0g=::OTY=::UGFja2V0IGNhY2hlIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0NBQ0hFX0w=::OTM=::UGFja2V0IGNhY2hlIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9I::ODk=::UGFja2V0IHRocmVhZCBpZCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9M::ODk=::UGFja2V0IHRocmVhZCBpZCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::ODA=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::Nzg=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0VYQ0xVU0lWRQ==::NzM=::UGFja2V0IGV4Y2x1c2l2ZSB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::ODU=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTI=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTA=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::NzY=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzQ=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::Njg=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::Njk=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfSA==::MzE=::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfTA==::MA==::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAy::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Mg==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::Mw==::QXZhbG9uLU1NIGJ1cnN0Y291bnQgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAxOjk5KSByZXNwb25zZV9zdGF0dXMoOTg6OTcpIGNhY2hlKDk2OjkzKSBwcm90ZWN0aW9uKDkyOjkwKSB0aHJlYWRfaWQoODkpIGRlc3RfaWQoODgpIHNyY19pZCg4NykgcW9zKDg2KSBiZWdpbl9idXJzdCg4NSkgZGF0YV9zaWRlYmFuZCg4NCkgYWRkcl9zaWRlYmFuZCg4MykgYnVyc3RfdHlwZSg4Mjo4MSkgYnVyc3Rfc2l6ZSg4MDo3OCkgYnVyc3R3cmFwKDc3KSBieXRlX2NudCg3Njo3NCkgdHJhbnNfZXhjbHVzaXZlKDczKSB0cmFuc19sb2NrKDcyKSB0cmFuc19yZWFkKDcxKSB0cmFuc193cml0ZSg3MCkgdHJhbnNfcG9zdGVkKDY5KSB0cmFuc19jb21wcmVzc2VkX3JlYWQoNjgpIGFkZHIoNjc6MzYpIGJ5dGVlbigzNTozMikgZGF0YSgzMTowKQ==::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1VQUFJFU1NfMF9CWVRFRU5fUlNQ::MA==::U3VwcHJlc3MgMC1ieXRlZW5hYmxlIHJlc3BvbnNlcw==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "SUQ=::MA==::TWFzdGVyIElE" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "QlVSU1RXUkFQX1ZBTFVF::MQ==::QnVyc3R3cmFwIHZhbHVl" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FDSEVfVkFMVUU=::MA==::Q2FjaGUgdmFsdWU=" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VDVVJFX0FDQ0VTU19CSVQ=::MQ==::U2VjdXJpdHkgYml0IHZhbHVl" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ==" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9zbGF2ZV90cmFuc2xhdG9y" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIFNsYXZlIFRyYW5zbGF0b3I=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgdGhlIEF2YWxvbi1NTSBzbGF2ZSBpbnRlcmZhY2UgdG8gYSBzaW1wbGlmaWVkIHJlcHJlc2VudGF0aW9uIHRoYXQgdGhlIFFzeXMgbmV0d29yayB1c2VzLiBSZWZlciB0byB0aGUgQXZhbG9uIEludGVyZmFjZSBTcGVjaWZpY2F0aW9ucyAoaHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvbWFudWFsL21ubF9hdmFsb25fc3BlYy5wZGYpIGZvciBkZWZpbml0aW9ucyBvZiB0aGUgQXZhbG9uLU1NIHNpZ25hbHMgYW5kIGV4cGxhbmF0aW9ucyBvZiB0aGUgYnVyc3RpbmcgcHJvcGVydGllcyBhbmQgYWRkcmVzcyBhbGlnbm1lbnQu" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19X::MzI=::Q29tcG9uZW50IGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9X::MzI=::Q29tcG9uZW50IERhdGEgd2lkdGg=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0RBVEFfVw==::MzI=::TmV0d29yayBEYXRhIHdpZHRo" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::MQ==::Q29tcG9uZW50IGJ1cnN0Y291bnQgd2lkdGg=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQllURUVOQUJMRV9X::NA==::Q29tcG9uZW50IGJ5dGVlbmFibGUgd2lkdGg=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0JZVEVFTkFCTEVfVw==::NA==::TmV0d29yayBieXRlZW5hYmxlIHdpZHRo" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NfVw==::MzI=::TmV0d29yayBhZGRyZXNzIHdpZHRo" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0JVUlNUQ09VTlRfVw==::Mw==::TmV0d29yayBidXJzdGNvdW50IHdpZHRo" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVBRExBVEVOQ1k=::MA==::cmVhZExhdGVuY3k=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVA==::MA==::c2V0dXBUaW1l" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVA==::MA==::d3JpdGVXYWl0VGltZQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlU::MQ==::cmVhZFdhaXRUaW1l" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xE::MA==::SG9sZCB0aW1l" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfVElNSU5HX1VOSVRT::MQ==::VGltaW5nIHVuaXRz" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRB::MQ==::VXNlIHJlYWRkYXRh" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFREFUQQ==::MQ==::VXNlIHdyaXRlZGF0YQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUQ=::MQ==::VXNlIHJlYWQ=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRF::MQ==::VXNlIHdyaXRl" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOQlVSU1RUUkFOU0ZFUg==::MA==::VXNlIGJlZ2luYnVyc3R0cmFuc2Zlcg==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOVFJBTlNGRVI=::MA==::VXNlIGJlZ2ludHJhbnNmZXI=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JZVEVFTkFCTEU=::MQ==::VXNlIGJ5dGVlbmFibGU=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0NISVBTRUxFQ1Q=::MA==::VXNlIGNoaXBzZWxlY3Q=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FERFJFU1M=::MQ==::VXNlIGFkZHJlc3M=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JVUlNUQ09VTlQ=::MQ==::VXNlIGJ1cnN0Y291bnQ=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRBVkFMSUQ=::MQ==::VXNlIHJlYWRkYXRhdmFsaWQ=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dBSVRSRVFVRVNU::MQ==::VXNlIHdhaXRyZXF1ZXN0" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFQllURUVOQUJMRQ==::MA==::VXNlIHdyaXRlYnl0ZWVuYWJsZQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xPQ0s=::MA==::VXNlIGxvY2s=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FWX0NMS0VO::MA==::VXNlIGNvbXBvbmVudCBjbGtlbg==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1VBVl9DTEtFTg==::MA==::VXNlIG5ldHdvcmsgY2xrZW4=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX09VVFBVVEVOQUJMRQ==::MA==::VXNlIG91dHB1dGVuYWJsZQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RFQlVHQUNDRVNT::MA==::VXNlIGRlYnVnYWNjZXNz" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfU1lNQk9MU19QRVJfV09SRA==::NA==::U3ltYm9scyBwZXIgd29yZA==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19TWU1CT0xT::MQ==::QWRkcmVzcyBzeW1ib2xz" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9TWU1CT0xT::MA==::QnVyc3Rjb3VudCBzeW1ib2xz" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQ09OU1RBTlRfQlVSU1RfQkVIQVZJT1I=::MA==::Q29tcG9uZW50IGNvbnN0YW50QnVyc3RCZWhhdmlvcg==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0NPTlNUQU5UX0JVUlNUX0JFSEFWSU9S::MA==::TmV0d29yayBjb25zdGFudEJ1cnN0QmVoYXZpb3I=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVRVUlSRV9VTkFMSUdORURfQUREUkVTU0VT::MA==::VW5hbGlnbmVkIGFkZHJlc3Nlcw==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTlM=::MQ==::bWF4UGVuZGluZ1JlYWRUcmFuc2FjdGlvbnM=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfV1JJVEVfVFJBTlNBQ1RJT05T::MA==::bWF4UGVuZGluZ1dyaXRlVHJhbnNhY3Rpb25z" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfSU5URVJMRUFWRUJVUlNUUw==::MA==::aW50ZXJsZWF2ZUJ1cnN0cw==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQklUU19QRVJfU1lNQk9M::OA==::Qml0cy9zeW1ib2w=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfSVNCSUdFTkRJQU4=::MA==::aXNCaWdFbmRpYW4=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU0dST1VQ::MA==::Q29tcG9uZW50IGFkZHJlc3MgZ3JvdXA=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NHUk9VUA==::MA==::TmV0d29yayBhZGRyZXNzIGdyb3Vw" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJPVVRHT0lOR1NJR05BTFM=::MA==::cmVnaXN0ZXJPdXRnb2luZ1NpZ25hbHM=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJJTkNPTUlOR1NJR05BTFM=::MA==::cmVnaXN0ZXJJbmNvbWluZ1NpZ25hbHM=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUxXQVlTQlVSU1RNQVhCVVJTVA==::MA==::QWx3YXlzIGJ1cnN0IG1heC1idXJzdA==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0hJUFNFTEVDVF9USFJPVUdIX1JFQURMQVRFTkNZ::MA==::Q2hpcHNlbGVjdCB0aHJvdWdoIHJlYWQgbGF0ZW5jeQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfUkFURQ==::NjAwMDAwMDA=::Q0xPQ0tfUkFURQ==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlUX0NZQ0xFUw==::MQ==::QVZfUkVBRF9XQUlUX0NZQ0xFUw==" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVF9DWUNMRVM=::MA==::QVZfV1JJVEVfV0FJVF9DWUNMRVM=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVF9DWUNMRVM=::MA==::QVZfU0VUVVBfV0FJVF9DWUNMRVM=" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xEX0NZQ0xFUw==::MA==::QVZfREFUQV9IT0xEX0NZQ0xFUw==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9tYXN0ZXJfdHJhbnNsYXRvcg==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIE1hc3RlciBUcmFuc2xhdG9y" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgdGhlIEF2YWxvbi1NTSBtYXN0ZXIgaW50ZXJmYWNlIHRvIGEgc2ltcGxlciByZXByZXNlbnRhdGlvbiB0aGF0IHRoZSBRc3lzIG5ldHdvcmsgdXNlcy4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgZGVmaW5pdGlvbnMgb2YgdGhlIEF2YWxvbi1NTSBzaWduYWxzIGFuZCBleHBsYW5hdGlvbnMgb2YgdGhlIGJ1cnN0aW5nIHByb3BlcnRpZXMu" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19X::MzI=::Q29tcG9uZW50IGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9X::MzI=::Q29tcG9uZW50IERhdGEgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::MQ==::Q29tcG9uZW50IGJ1cnN0Y291bnQgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQllURUVOQUJMRV9X::NA==::Q29tcG9uZW50IGJ5dGVlbmFibGUgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NfVw==::MzI=::TmV0d29yayBhZGRyZXNzIHdpZHRo" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0JVUlNUQ09VTlRfVw==::Mw==::TmV0d29yayBidXJzdGNvdW50IHdpZHRo" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVBRExBVEVOQ1k=::MA==::cmVhZExhdGVuY3k=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVA==::MA==::d3JpdGVXYWl0VGltZQ==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlU::MQ==::cmVhZFdhaXRUaW1l" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xE::MA==::SG9sZCB0aW1l" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVA==::MA==::c2V0dXBUaW1l" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRB::MQ==::VXNlIHJlYWRkYXRh" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFREFUQQ==::MQ==::VXNlIHdyaXRlZGF0YQ==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUQ=::MQ==::VXNlIHJlYWQ=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRF::MQ==::VXNlIHdyaXRl" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOQlVSU1RUUkFOU0ZFUg==::MA==::VXNlIGJlZ2luYnVyc3R0cmFuc2Zlcg==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOVFJBTlNGRVI=::MA==::VXNlIGJlZ2ludHJhbnNmZXI=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JZVEVFTkFCTEU=::MQ==::VXNlIGJ5dGVlbmFibGU=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0NISVBTRUxFQ1Q=::MA==::VXNlIGNoaXBzZWxlY3Q=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FERFJFU1M=::MQ==::VXNlIGFkZHJlc3M=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0JVUlNUQ09VTlQ=::MA==::VXNlIGJ1cnN0Y291bnQ=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RFQlVHQUNDRVNT::MA==::VXNlIGRlYnVnYWNjZXNz" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0NMS0VO::MA==::VXNlIG5ldHdvcmsgY2xrZW4=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRBVkFMSUQ=::MQ==::VXNlIHJlYWRkYXRhdmFsaWQ=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dBSVRSRVFVRVNU::MQ==::VXNlIHdhaXRyZXF1ZXN0" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xPQ0s=::MA==::VXNlIGxvY2s=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfU1lNQk9MU19QRVJfV09SRA==::NA==::U3ltYm9scyBwZXIgd29yZA==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19TWU1CT0xT::MQ==::QWRkcmVzcyBzeW1ib2xz" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9TWU1CT0xT::MA==::QnVyc3Rjb3VudCBzeW1ib2xz" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQ09OU1RBTlRfQlVSU1RfQkVIQVZJT1I=::MA==::Q29tcG9uZW50IGNvbnN0YW50QnVyc3RCZWhhdmlvcg==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0NPTlNUQU5UX0JVUlNUX0JFSEFWSU9S::MA==::TmV0d29yayBjb25zdGFudEJ1cnN0QmVoYXZpb3I=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTlM=::NjQ=::bWF4UGVuZGluZ1JlYWRUcmFuc2FjdGlvbnM=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfSU5URVJMRUFWRUJVUlNUUw==::MA==::aW50ZXJsZWF2ZUJ1cnN0cw==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQklUU19QRVJfU1lNQk9M::OA==::Qml0cy9zeW1ib2w=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfSVNCSUdFTkRJQU4=::MA==::aXNCaWdFbmRpYW4=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU0dST1VQ::MA==::Q29tcG9uZW50IGFkZHJlc3MgZ3JvdXA=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NHUk9VUA==::MA==::TmV0d29yayBhZGRyZXNzIGdyb3Vw" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJPVVRHT0lOR1NJR05BTFM=::MA==::cmVnaXN0ZXJPdXRnb2luZ1NpZ25hbHM=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJJTkNPTUlOR1NJR05BTFM=::MA==::cmVnaXN0ZXJJbmNvbWluZ1NpZ25hbHM=" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfQUxXQVlTQlVSU1RNQVhCVVJTVA==::MA==::QWx3YXlzIGJ1cnN0IG1heC1idXJzdA==" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lOQ19SRVNFVA==::MA==::VXNlIHN5bmNocm9ub3VzIHJlc2V0cw==" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19tbV9pbnRlcmNvbm5lY3RfMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "TU0gSW50ZXJjb25uZWN0" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "TU0gSW50ZXJjb25uZWN0" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFQkEyRjE3QTc=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lbV9pZl9kbGxfY3ljbG9uZXY=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "RXh0ZXJuYWwgTWVtb3J5IERMTCBibG9jaw==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RXh0ZXJuYWwgTWVtb3J5IERMTCBibG9jaw==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Nw==::RExMX0RFTEFZX0NUUkxfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::OA==::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::dHJ1ZQ==::SEFSRF9QSFk=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::dHJ1ZQ==::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs=" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX0lOUFVUX0ZSRVFVRU5DWV9QU19TVFI=::MzMzMyBwcw==::RExMX0lOUFVUX0ZSRVFVRU5DWV9QU19TVFI=" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lbV9pZl9vY3RfY3ljbG9uZXY=" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "RXh0ZXJuYWwgTWVtb3J5IE9DVCBibG9jaw==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RXh0ZXJuYWwgTWVtb3J5IE9DVCBibG9jaw==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==::MTY=::T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::T0NUIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::OA==::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::dHJ1ZQ==::SEFSRF9QSFk=" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::dHJ1ZQ==::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw==" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04=" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX21lbV9pZl9oYXJkX21lbW9yeV9jb250cm9sbGVyX3RvcF9jeWNsb25ldg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEREUjMgSGFyZCBNZW1vcnkgQ29udHJvbGxlcg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIEREUjMgSGFyZCBNZW1vcnkgQ29udHJvbGxlcg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTg==::NDg=::TUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDExMDAwMQ==::QUNfUk9NX01SMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMTAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDExMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMTAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMTAwMDAwMA==::QUNfUk9NX01SMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDEwMDAwMA==::QUNfUk9NX01SMV9NSVJS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMTAwMA==::QUNfUk9NX01SMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAxMDAwMA==::QUNfUk9NX01SMl9NSVJS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::dHJ1ZQ==::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::Mw==::TVIwX0NBU19MQVRFTkNZ" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::Mg==::TVIxX1JUVA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MQ==::TVIyX0NXTA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::TUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::Mg==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTM=::TUVNX0lGX0FERFJfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTM=::TUVNX0lGX1JPV19BRERSX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::Mg==::TUVNX0lGX0RNX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::ZmFsc2U=::TUVNX0xFVkVMSU5H" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::Mg==::TnVtYmVyIG9mIERRUyBncm91cHM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::MTY=::TUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS41::TUVNX0NMS19NQVhfTlM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTUwMC4w::TUVNX0NMS19NQVhfUFM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTQ=::TUVNX1RGQVc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mw==::TUVNX1RSUkQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::NDUw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::Ng==::TUVNX1dUQ0xfSU5U" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::Mg==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::TWljcm9u::TWVtb3J5IHZlbmRvcg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgw::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::NjY2LjY2Nw==::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTM=::Um93IGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::MTY=::VG90YWwgaW50ZXJmYWNlIHdpZHRo" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::UlpRLzI=::T0RUIFJ0dCBub21pbmFsIHZhbHVl" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::Ng==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::Nw==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTkw::dElTIChiYXNlKQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTQw::dElIIChiYXNlKQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MzA=::dERTIChiYXNlKQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NjU=::dERIIChiYXNlKQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTI1::dERRU1E=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjU1::dERRU0NL" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNQ==::dERRU1M=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4y::dERTSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4y::dERTUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzYuMA==::dFJBUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNQ==::dFJDRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNQ==::dFJQ" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::NQ==::dFdUUg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::NDUuMA==::dEZBVw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ny41::dFJSRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::MTA=::Q1NSX0FERFJfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::OA==::Q1NSX0RBVEFfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::MQ==::Q1NSX0JFX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTX1dJRFRI::MQ==::Q1RMX0NTX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0JFX1dJRFRI::NA==::QVZMX0JFX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX1NZTUJPTF9XSURUSA==::OA==::QVZMX1NZTUJPTF9XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xT::NA==::QVZMX05VTV9TWU1CT0xT" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX1NJWkVfV0lEVEg=::Mw==::QVZMX1NJWkVfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19DU1JfRU5BQkxFRA==::ZmFsc2U=::Q1RMX0VDQ19DU1JfRU5BQkxFRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFdJRFRIX1JBVElP::Mg==::RFdJRFRIX1JBVElP" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX09EVF9FTkFCTEVE::dHJ1ZQ==::Q1RMX09EVF9FTkFCTEVE" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX09VVFBVVF9SRUdE::ZmFsc2U=::Q1RMX09VVFBVVF9SRUdE" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::Q1RMX1JFR0RJTU1fRU5BQkxFRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TE9XX0xBVEVOQ1k=::ZmFsc2U=::TE9XX0xBVEVOQ1k=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9UWVBF::bmV4dGdlbl92MTEw::Q09OVFJPTExFUl9UWVBF" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1RCUF9OVU0=::NA==::Q1RMX1RCUF9OVU0=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNI::MA==::Q1RMX1VTUl9SRUZSRVNI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSA==::MA==::Q1RMX1NFTEZfUkVGUkVTSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RZUEU=::Mg==::Q0ZHX1RZUEU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0lOVEVSRkFDRV9XSURUSA==::MTY=::Q0ZHX0lOVEVSRkFDRV9XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0JVUlNUX0xFTkdUSA==::OA==::Q0ZHX0JVUlNUX0xFTkdUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0FERFJfT1JERVI=::MA==::Q0ZHX0FERFJfT1JERVI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BETl9FWElUX0NZQ0xFUw==::MTA=::Q0ZHX1BETl9FWElUX0NZQ0xFUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw==::NQ==::Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT::MTA=::Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw==::NTEy::Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA=::MQ==::Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA==::MQ==::Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1dSSVRFX09EVF9DSElQ::MQ==::Q0ZHX1dSSVRFX09EVF9DSElQ" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFQURfT0RUX0NISVA=::MA==::Q0ZHX1JFQURfT0RUX0NISVA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TE9DQUxfQ1NfV0lEVEg=::MA==::TE9DQUxfQ1NfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0NMUl9JTlRS::MA==::Q0ZHX0NMUl9JTlRS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0VOQUJMRV9OT19ETQ==::MA==::Q0ZHX0VOQUJMRV9OT19ETQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FERF9MQVQ=::MA==::TUVNX0FERF9MQVQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0VSUkNNRF9GSUZPX1JFRw==::MA==::Q0ZHX0VSUkNNRF9GSUZPX1JFRw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX0VDQ19ERUNPREVSX1JFRw==::MA==::Q0ZHX0VDQ19ERUNPREVSX1JFRw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k=::ZmFsc2U=::Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1NUQVJWRV9MSU1JVA==::MTA=::Q0ZHX1NUQVJWRV9MSU1JVA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fUERfQ1lDTEVT::MA==::TUVNX0FVVE9fUERfQ1lDTEVT" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX1BPUlQ=::UG9ydCAw::UG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8w::MzI=::QVZMX0RBVEFfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8w::MjU=::QVZMX0FERFJfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8w::MQ==::UFJJT1JJVFlfUE9SVF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMA==::MA==::V0VJR0hUX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzA=::Mw==::Q1BPUlRfVFlQRV9QT1JUXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::NA==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMA==::MA==::TFNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMA==::MA==::TVNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMA==::MA==::TFNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMA==::MA==::TVNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8x::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8x::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8x::MQ==::UFJJT1JJVFlfUE9SVF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMQ==::MA==::V0VJR0hUX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1BPUlRfVFlQRV9QT1JUXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMQ==::NQ==::TFNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMQ==::NQ==::TVNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMQ==::NQ==::TFNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMQ==::NQ==::TVNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8y::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8y::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8y::MQ==::UFJJT1JJVFlfUE9SVF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMg==::MA==::V0VJR0hUX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1BPUlRfVFlQRV9QT1JUXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMg==::NQ==::TFNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMg==::NQ==::TVNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMg==::NQ==::TFNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMg==::NQ==::TVNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8z::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8z::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8z::MQ==::UFJJT1JJVFlfUE9SVF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMw==::MA==::V0VJR0hUX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1BPUlRfVFlQRV9QT1JUXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMw==::NQ==::TFNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMw==::NQ==::TVNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMw==::NQ==::TFNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMw==::NQ==::TVNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF80::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF80::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF80::MQ==::UFJJT1JJVFlfUE9SVF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNA==::MA==::V0VJR0hUX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1BPUlRfVFlQRV9QT1JUXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNA==::NQ==::TFNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNA==::NQ==::TVNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNA==::NQ==::TFNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNA==::NQ==::TVNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF81::MQ==::QVZMX0RBVEFfV0lEVEhfUE9SVF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF81::MQ==::QVZMX0FERFJfV0lEVEhfUE9SVF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF81::MQ==::UFJJT1JJVFlfUE9SVF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNQ==::MA==::V0VJR0hUX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1BPUlRfVFlQRV9QT1JUXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::MQ==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNQ==::NQ==::TFNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNQ==::NQ==::TVNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNQ==::NQ==::TFNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNQ==::NQ==::TVNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfT05FX1JFU0VU::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX29uZV9yZXNldA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfWkVST19SRVNFVA==::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX3plcm9fcmVzZXQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX1NUQVRJQ19DT05GSUdfVkFMSUQ=::RElTQUJMRUQ=::YXR0cl9zdGF0aWNfY29uZmlnX3ZhbGlk" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DQUxfUkVR::RElTQUJMRUQ=::Y2FsX3JlcQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfQlVSU1RfTEVOR1RI::QkxfOA==::Y2ZnX2J1cnN0X2xlbmd0aA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfSU5URVJGQUNFX1dJRFRI::RFdJRFRIXzE2::Y2ZnX2ludGVyZmFjZV93aWR0aA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfU0VMRl9SRlNIX0VYSVRfQ1lDTEVT::U0VMRl9SRlNIX0VYSVRfQ1lDTEVTXzUxMg==::Y2ZnX3NlbGZfcmZzaF9leGl0X2N5Y2xlcw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfU1RBUlZFX0xJTUlU::U1RBUlZFX0xJTUlUXzQ=::Y2ZnX3N0YXJ2ZV9saW1pdA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfVFlQRQ==::RERSMw==::Y2ZnX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMg==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMw==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTFJfSU5UUg==::Tk9fQ0xSX0lOVFI=::Y2xyX2ludHI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::VFJVRQ==::Y21kX3BvcnRfaW5fdXNlXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQwX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfVFlQRQ==::QklfRElSRUNUSU9O::Y3BvcnQwX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQxX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQyX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQzX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ0X3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ1X3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfQUREUl9PUkRFUg==::Q0hJUF9ST1dfQkFOS19DT0w=::Y3RsX2FkZHJfb3JkZXI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX0VOQUJMRUQ=::Q1RMX0VDQ19ESVNBQkxFRA==::Y3RsX2VjY19lbmFibGVk" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX1JNV19FTkFCTEVE::Q1RMX0VDQ19STVdfRElTQUJMRUQ=::Y3RsX2VjY19ybXdfZW5hYmxlZA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfUkVHRElNTV9FTkFCTEVE::UkVHRElNTV9ESVNBQkxFRA==::Y3RsX3JlZ2RpbW1fZW5hYmxlZA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfVVNSX1JFRlJFU0g=::Q1RMX1VTUl9SRUZSRVNIX0RJU0FCTEVE::Y3RsX3Vzcl9yZWZyZXNo" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9DVFJMX1dJRFRI::REFUQV9XSURUSF8zMl9CSVQ=::Y3RybF93aWR0aA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9ERUxBWV9CT05ESU5H::Qk9ORElOR19MQVRFTkNZXzA=::ZGVsYXlfYm9uZGluZw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9ERlhfQllQQVNTX0VOQUJMRQ==::REZYX0JZUEFTU19ESVNBQkxFRA==::ZGZ4X2J5cGFzc19lbmFibGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9ESVNBQkxFX01FUkdJTkc=::TUVSR0lOR19FTkFCTEVE::ZGlzYWJsZV9tZXJnaW5n" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FQ0NfRFFfV0lEVEg=::RUNDX0RRX1dJRFRIXzA=::ZWNjX2RxX3dpZHRo" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQVRQRw==::RElTQUJMRUQ=::ZW5hYmxlX2F0cGc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR19XUkFQQkFDSw==::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfd3JhcGJhY2s=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRFFTX1RSQUNLSU5H::RElTQUJMRUQ=::ZW5hYmxlX2Rxc190cmFja2luZw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRUNDX0NPREVfT1ZFUldSSVRFUw==::RElTQUJMRUQ=::ZW5hYmxlX2VjY19jb2RlX292ZXJ3cml0ZXM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRkFTVF9FWElUX1BQRA==::RElTQUJMRUQ=::ZW5hYmxlX2Zhc3RfZXhpdF9wcGQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfSU5UUg==::RElTQUJMRUQ=::ZW5hYmxlX2ludHI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfTk9fRE0=::RElTQUJMRUQ=::ZW5hYmxlX25vX2Rt" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfUElQRUxJTkVHTE9CQUw=::RElTQUJMRUQ=::ZW5hYmxlX3BpcGVsaW5lZ2xvYmFs" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9HQU5HRURfQVJG::RElTQUJMRUQ=::Z2FuZ2VkX2FyZg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fREJF::R0VOX0RCRV9ESVNBQkxFRA==::Z2VuX2RiZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fU0JF::R0VOX1NCRV9ESVNBQkxFRA==::Z2VuX3NiZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9JTkNfU1lOQw==::RklGT19TRVRfMg==::aW5jX3N5bmM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9MT0NBTF9JRl9DU19XSURUSA==::QUREUl9XSURUSF8w::bG9jYWxfaWZfY3Nfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0NPUlJfRFJPUFBFRF9JTlRS::RElTQUJMRUQ=::bWFza19jb3JyX2Ryb3BwZWRfaW50cg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0RCRV9JTlRS::RElTQUJMRUQ=::bWFza19kYmVfaW50cg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX1NCRV9JTlRS::RElTQUJMRUQ=::bWFza19zYmVfaW50cg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQUw=::QUxfMA==::bWVtX2lmX2Fs" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQkFOS0FERFJfV0lEVEg=::QUREUl9XSURUSF8z::bWVtX2lmX2JhbmthZGRyX3dpZHRo" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQlVSU1RMRU5HVEg=::TUVNX0lGX0JVUlNUTEVOR1RIXzg=::bWVtX2lmX2J1cnN0bGVuZ3Ro" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ09MQUREUl9XSURUSA==::QUREUl9XSURUSF8xMA==::bWVtX2lmX2NvbGFkZHJfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfUEVSX1JBTks=::TUVNX0lGX0NTX1BFUl9SQU5LXzE=::bWVtX2lmX2NzX3Blcl9yYW5r" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfV0lEVEg=::TUVNX0lGX0NTX1dJRFRIXzE=::bWVtX2lmX2NzX3dpZHRo" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFfUEVSX0NISVA=::TUVNX0lGX0RRX1BFUl9DSElQXzg=::bWVtX2lmX2RxX3Blcl9jaGlw" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFTX1dJRFRI::RFFTX1dJRFRIXzI=::bWVtX2lmX2Rxc193aWR0aA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFdJRFRI::TUVNX0lGX0RXSURUSF8xNg==::bWVtX2lmX2R3aWR0aA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfTUVNVFlQRQ==::RERSM19TRFJBTQ==::bWVtX2lmX21lbXR5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfUk9XQUREUl9XSURUSA==::QUREUl9XSURUSF8xMw==::bWVtX2lmX3Jvd2FkZHJfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfU1BFRURCSU4=::RERSM18xNjAwXzhfOF84::bWVtX2lmX3NwZWVkYmlu" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENDRA==::VENDRF80::bWVtX2lmX3RjY2Q=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENM::VENMXzc=::bWVtX2lmX3RjbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENXTA==::VENXTF82::bWVtX2lmX3Rjd2w=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVEZBVw==::VEZBV18xNA==::bWVtX2lmX3RmYXc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVE1SRA==::VE1SRF80::bWVtX2lmX3RtcmQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJBUw==::VFJBU18xMQ==::bWVtX2lmX3RyYXM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJD::VFJDXzE1::bWVtX2lmX3RyYw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJDRA==::VFJDRF81::bWVtX2lmX3RyY2Q=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJQ::VFJQXzU=::bWVtX2lmX3RycA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJSRA==::VFJSRF8z::bWVtX2lmX3RycmQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJUUA==::VFJUUF8z::bWVtX2lmX3RydHA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdS::VFdSXzU=::bWVtX2lmX3R3cg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdUUg==::VFdUUl81::bWVtX2lmX3R3dHI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9NTVJfQ0ZHX01FTV9CTA==::TVBfQkxfOA==::bW1yX2NmZ19tZW1fYmw=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9PVVRQVVRfUkVHRA==::RElTQUJMRUQ=::b3V0cHV0X3JlZ2Q=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QRE5fRVhJVF9DWUNMRVM=::U0xPV19FWElU::cGRuX2V4aXRfY3ljbGVz" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDBfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDFfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMl9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDJfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUM19XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDNfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDRfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDVfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzMy::cmRfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8w::VFJVRQ==::cmRfZmlmb19pbl91c2VfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8x::RkFMU0U=::cmRfZmlmb19pbl91c2VfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8y::RkFMU0U=::cmRfZmlmb19pbl91c2VfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8z::RkFMU0U=::cmRfZmlmb19pbl91c2VfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFXzA=::cmRfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRUFEX09EVF9DSElQ::T0RUX0RJU0FCTEVE::cmVhZF9vZHRfY2hpcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRU9SREVSX0RBVEE=::Tk9fREFUQV9SRU9SREVSSU5H::cmVvcmRlcl9kYXRh" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMA==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMQ==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMg==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMw==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMg==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMw==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9URVNUX01PREU=::Tk9STUFMX01PREU=::dGVzdF9tb2Rl" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMg==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMw==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMg==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMw==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzA=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzE=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzI=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzM=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX0VDQ19FTg==::RElTQUJMRQ==::dXNlcl9lY2NfZW4=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8wX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8xX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8yX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8zX3JkeV9hbG1vc3RfZnVsbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzMy::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8w::VFJVRQ==::d3JfZmlmb19pbl91c2VfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8x::RkFMU0U=::d3JfZmlmb19pbl91c2VfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8y::RkFMU0U=::d3JfZmlmb19pbl91c2VfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8z::RkFMU0U=::d3JfZmlmb19pbl91c2VfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFXzA=::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9XUklURV9PRFRfQ0hJUA==::V1JJVEVfQ0hJUDBfT0RUMF9DSElQMQ==::d3JpdGVfb2R0X2NoaXA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQVVUT19QRF9DWUNMRVM=::MA==::bWVtX2F1dG9fcGRfY3ljbGVz" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMg==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMw==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1Q=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1RfRElGRl9CQU5L::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0X2RpZmZfYmFuaw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19QQ0g=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcGNo" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19SRFdS::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcmR3cg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfcGVyaW9k" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfdG9fdmFsaWQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0ZPVVJfQUNUX1RPX0FDVA==::MA==::ZXh0cmFfY3RsX2Nsa19mb3VyX2FjdF90b19hY3Q=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9BTExfVE9fVkFMSUQ=::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfYWxsX3RvX3ZhbGlk" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfdG9fdmFsaWQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fcGVyaW9k" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fdG9fdmFsaWQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa19yZF9hcF90b192YWxpZA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19wY2g=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZF9kaWZmX2NoaXA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dS::Mg==::ZXh0cmFfY3RsX2Nsa19yZF90b193cg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0JD::Mg==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9iYw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0RJRkZfQ0hJUA==::Mg==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9kaWZmX2NoaXA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fdmFsaWQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19aUV9DQUw=::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fenFfY2Fs" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa193cl9hcF90b192YWxpZA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19wY2g=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JE::Mw==::ZXh0cmFfY3RsX2Nsa193cl90b19yZA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0JD::Mw==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9iYw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0RJRkZfQ0hJUA==::Mw==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9kaWZmX2NoaXA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cl9kaWZmX2NoaXA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJFRkk=::MjM0MQ==::bWVtX2lmX3RyZWZp" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJGQw==::MzQ=::bWVtX2lmX3RyZmM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BU0s=::MA==::YXR0cl9jb3VudGVyX29uZV9tYXNr" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BVENI::MA==::YXR0cl9jb3VudGVyX29uZV9tYXRjaA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVNL::MA==::YXR0cl9jb3VudGVyX3plcm9fbWFzaw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVRDSA==::MA==::YXR0cl9jb3VudGVyX3plcm9fbWF0Y2g=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0RFQlVHX1NFTEVDVF9CWVRF::MA==::YXR0cl9kZWJ1Z19zZWxlY3RfYnl0ZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19QT1dFUl9TQVZJTkdfRVhJVF9DWUNMRVM=::NQ==::cG93ZXJfc2F2aW5nX2V4aXRfY3ljbGVz" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQ0xLX0VOVFJZX0NZQ0xFUw==::MTA=::bWVtX2Nsa19lbnRyeV9jeWNsZXM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfSU5URVJSVVBU::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X2ludGVycnVwdA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfVEVSTUlOQVRF::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X3Rlcm1pbmF0ZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8wX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MA==::YXZfcG9ydF8wX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8wX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MA==::Y3ZfcG9ydF8wX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w::MzI=::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w::MjU=::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA=::Mw==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::NA==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMA==::MA==::Q1ZfTFNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMA==::MA==::Q1ZfTVNCX1dGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMA==::MA==::Q1ZfTFNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMA==::MA==::Q1ZfTVNCX1JGSUZPX1BPUlRfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::VFJVRQ==::Y21kX3BvcnRfaW5fdXNlXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfVFlQRQ==::QklfRElSRUNUSU9O::Y3BvcnQwX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDBfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzMy::cmRfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFXzA=::cmRfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8w" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzMy::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFXzA=::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzA=::Mw==::VEdfVEVNUF9QT1JUXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8xX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MQ==::YXZfcG9ydF8xX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8xX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MQ==::Y3ZfcG9ydF8xX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDFfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8x" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzE=::MA==::VEdfVEVNUF9QT1JUXzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8yX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mg==::YXZfcG9ydF8yX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8yX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mg==::Y3ZfcG9ydF8yX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMl9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDJfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzI=::MA==::VEdfVEVNUF9QT1JUXzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8zX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mw==::YXZfcG9ydF8zX2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8zX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mw==::Y3ZfcG9ydF8zX2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUM19XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDNfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV8z" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzM=::MA==::VEdfVEVNUF9QT1JUXzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF80X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NA==::YXZfcG9ydF80X2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF80X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NA==::Y3ZfcG9ydF80X2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNF9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDRfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV80" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzQ=::MA==::VEdfVEVNUF9QT1JUXzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF81X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NQ==::YXZfcG9ydF81X2Nvbm5lY3RfdG9fY3ZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF81X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NQ==::Y3ZfcG9ydF81X2Nvbm5lY3RfdG9fYXZfcG9ydA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81::MQ==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81::MQ==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::MQ==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNV9XSURUSA==::UE9SVF8zMl9CSVQ=::cG9ydDVfd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMQ==::cmNmZ191c2VyX3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMQ==::dXNlcl9wcmlvcml0eV81" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzU=::MA==::VEdfVEVNUF9QT1JUXzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw=::ZmFsc2U=::Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYMTBfQ0ZH::ZmFsc2U=::TUFYMTBfQ0ZH" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UE9XRVJfT0ZfVFdPX0JVUw==::ZmFsc2U=::R2VuZXJhdGUgcG93ZXItb2YtMiBkYXRhIGJ1cyB3aWR0aHMgZm9yIFFzeXMgb3IgU09QQyBCdWlsZGVy" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U09QQ19DT01QQVRfUkVTRVQ=::ZmFsc2U=::R2VuZXJhdGUgU09QQyBCdWlsZGVyIGNvbXBhdGlibGUgcmVzZXRz" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX01BWF9TSVpF::NA==::TWF4aW11bSBBdmFsb24tTU0gYnVyc3QgbGVuZ3Ro" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEU=::dHJ1ZQ==::RW5hYmxlIEF2YWxvbi1NTSBieXRlLWVuYWJsZSBzaWduYWw=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NUUkxfQVZBTE9OX0lOVEVSRkFDRQ==::dHJ1ZQ==::RW5hYmxlIEF2YWxvbiBpbnRlcmZhY2U=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0RFRVBfUE9XRVJETl9FTg==::ZmFsc2U=::RW5hYmxlIERlZXAgUG93ZXItRG93biBDb250cm9scw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSF9FTg==::ZmFsc2U=::RW5hYmxlIFNlbGYtUmVmcmVzaCBDb250cm9scw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19QT1dFUkROX0VO::ZmFsc2U=::RW5hYmxlIEF1dG8gUG93ZXItRG93bg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNIX0VO::ZmFsc2U=::RW5hYmxlIFVzZXIgQXV0by1SZWZyZXNoIENvbnRyb2xz" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0FVVE9QQ0hfRU4=::ZmFsc2U=::RW5hYmxlIEF1dG8tUHJlY2hhcmdlIENvbnRyb2w=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1pRQ0FMX0VO::ZmFsc2U=::RW5hYmxlIFpRIENhbGlicmF0aW9uIENvbnRyb2w=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9PUkRFUg==::MA==::TG9jYWwtdG8tTWVtb3J5IEFkZHJlc3MgTWFwcGluZw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9MQVRFTkNZ::NQ==::UmVkdWNlIENvbnRyb2xsZXIgTGF0ZW5jeSBCeQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFT1JERVJfREFUQQ==::ZmFsc2U=::RW5hYmxlIFJlb3JkZXJpbmc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9FTkFCTEVE::dHJ1ZQ==::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19FTkFCTEVE::ZmFsc2U=::RW5hYmxlIEVycm9yIERldGVjdGlvbiBhbmQgQ29ycmVjdGlvbiBMb2dpYw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVVMVElDQVNUX0VO::ZmFsc2U=::RW5hYmxlIE11bHRpLWNhc3QgV3JpdGUgQ29udHJvbA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0RZTkFNSUNfQkFOS19BTExPQ0FUSU9O::ZmFsc2U=::RW5hYmxlIHJlZHVjZWQgYmFuayB0cmFja2luZyBmb3IgYXJlYSBvcHRpbWl6YXRpb24=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVCVUdfTU9ERQ==::ZmFsc2U=::RW5hYmxlIGludGVybmFsIGRlYnVnIHBhcmFtZXRlcg==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JVUlNUX01FUkdF::ZmFsc2U=::RW5hYmxlIGJ1cnN0IG1lcmdpbmc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFQ=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IGludGVycnVwdA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEU=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IHRlcm1pbmF0ZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TE9DQUxfSURfV0lEVEg=::OA==::TG9jYWwgSUQgd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRCVUZGRVJfQUREUl9XSURUSA==::OA==::UmVhZCBidWZmZXIgYWRkcmVzcyB3aWR0aA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V1JCVUZGRVJfQUREUl9XSURUSA==::Ng==::V3JpdGUgYnVmZmVyIGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfV1JfQ01E::MTY=::TWF4IHBlbmRpbmcgd3JpdGUgY29tbWFuZHM=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfUkRfQ01E::MzI=::TWF4IHBlbmRpbmcgcmVhZCBjb21tYW5kcw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01NX0FEQVBUT1I=::dHJ1ZQ==::VXNlIEF2YWxvbiBNTSBBZGFwdG9y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FYSV9BREFQVE9S::ZmFsc2U=::VXNlIEFYSSBBZGFwdG9y" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RF::ZmFsc2U=::SGFyZENvcHkgQ29tcGF0aWJpbGl0eSBNb2Rl" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NNRF9RVUVVRV9ERVBUSA==::OA==::Q1RMX0NNRF9RVUVVRV9ERVBUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9SRUFEX09OTFk=::MQ==::Q1RMX0NTUl9SRUFEX09OTFk=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX09GX1BPUlRT::MQ==::TnVtYmVyIG9mIHBvcnRz" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JPTkRJTkc=::ZmFsc2U=::RXhwb3J0IGJvbmRpbmcgaW50ZXJmYWNl" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1VTRVJfRUND::ZmFsc2U=::RXhwYW5kIEF2YWxvbi1NTSBkYXRhIGZvciBFQ0M=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVA==::MzIsMzIsMzIsMzIsMzIsMzI=::V2lkdGg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVA==::MSwxLDEsMSwxLDE=::UHJpb3JpdHk=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlQ=::MCwwLDAsMCwwLDA=::V2VpZ2h0" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JU::QmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWwsQmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWw=::VHlwZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURQ==::RnVsbA==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::MQ==::QUZJX1JBVEVfUkFUSU8=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::MTM=::QUZJX0FERFJfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Mw==::QUZJX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::MQ==::QUZJX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::MQ==::QUZJX0NTX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::MQ==::QUZJX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::MQ==::QUZJX09EVF9XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::OA==::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::dHJ1ZQ==::SEFSRF9QSFk=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::dHJ1ZQ==::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw==" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04=" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19kbWFzdGVy" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "SlRBRyB0byBBdmFsb24gTWFzdGVyIEJyaWRnZQ==" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "VGhlIEpUQUcgdG8gQXZhbG9uIE1hc3RlciBCcmlkZ2UgaXMgYSBjb2xsZWN0aW9uIG9mIHByZS13aXJlZCBjb21wb25lbnRzIHRoYXQgcHJvdmlkZSBhbiBBdmFsb24gTWFzdGVyIHVzaW5nIHRoZSBuZXcgSlRBRyBjaGFubmVsLg==" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1BMSQ==::MA==::VXNlIFNpbXVsYXRpb24gTGluayBNb2Rl" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NUE9ORU5UX0NMT0NL::MA==::Q09NUE9ORU5UX0NMT0NL" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkFTVF9WRVI=::MA==::RW5oYW5jZWQgdHJhbnNhY3Rpb24gbWFzdGVy" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFQkEyRjE3QTc=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19kbWFzdGVyX3AyYl9hZGFwdGVy" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIENoYW5uZWwgQWRhcHRlcg==" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw=" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::OA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MjU1::TWF4IENoYW5uZWw=" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w=" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA==" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::QVVUTw==::SW5jbHVkZSBFbXB0eSBTaWduYWw=" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ==" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ==" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ==" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19kbWFzdGVyX2IycF9hZGFwdGVy" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIENoYW5uZWwgQWRhcHRlcg==" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::OA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MjU1::TWF4IENoYW5uZWw=" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::TWF4IENoYW5uZWw=" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w=" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA==" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::QVVUTw==::SW5jbHVkZSBFbXB0eSBTaWduYWw=" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ==" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ==" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ==" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9wYWNrZXRzX3RvX21hc3Rlcg==" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFBhY2tldHMgdG8gVHJhbnNhY3Rpb24gQ29udmVydGVy" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_VERSION "MTAwLjk5Ljk4Ljk3" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uIFBhY2tldHMgdG8gVHJhbnNhY3Rpb24gQ29udmVydGVy" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX01BU1RFUl9TSUdOQUxT::MA==::RVhQT1JUX01BU1RFUl9TSUdOQUxT" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkFTVF9WRVI=::MA==::RW5oYW5jZWQgdHJhbnNhY3Rpb24gbWFzdGVy" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9wYWNrZXRzX3RvX2J5dGVz" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFBhY2tldHMgdG8gQnl0ZXMgQ29udmVydGVy" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_VERSION "MTAwLjk5Ljk4Ljk3" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLVNUIFBhY2tldHMgdG8gQnl0ZXMgQ29udmVydGVy" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSF9ERVJJVkVE::OA==::Q0hBTk5FTF9XSURUSF9ERVJJVkVE" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5DT0RJTkc=::MA==::RW5jb2Rpbmc=" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9ieXRlc190b19wYWNrZXRz" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEJ5dGVzIHRvIFBhY2tldHMgQ29udmVydGVy" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_VERSION "MTAwLjk5Ljk4Ljk3" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLVNUIEJ5dGVzIHRvIFBhY2tldHMgQ29udmVydGVy" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSF9ERVJJVkVE::OA==::Q0hBTk5FTF9XSURUSF9ERVJJVkVE" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5DT0RJTkc=::MA==::RW5jb2Rpbmc=" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19kbWFzdGVyX3RpbWluZ19hZHQ=" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFRpbWluZyBBZGFwdGVy" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw=" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w=" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::ZmFsc2U=::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA==" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ==" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::ZmFsc2U=::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::UmVhZHkgTGF0ZW5jeQ==" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ==" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::dHJ1ZQ==::SW5jbHVkZSBWYWxpZCBTaWduYWw=" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::dHJ1ZQ==::SW5jbHVkIFZhbGlkIFNpZ25hbA==" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9qdGFnX2ludGVyZmFjZQ==" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEpUQUcgSW50ZXJmYWNl" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_VERSION "MTAwLjk5Ljk4Ljk3" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFVSUE9TRQ==::MQ==::UFVSUE9TRQ==" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVBTVFJFQU1fRklGT19TSVpF::MA==::VVBTVFJFQU1fRklGT19TSVpF" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "RE9XTlNUUkVBTV9GSUZPX1NJWkU=::NjQ=::RE9XTlNUUkVBTV9GSUZPX1NJWkU=" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUdNVF9DSEFOTkVMX1dJRFRI::LTE=::TWFuYWdlbWVudCBjaGFubmVsIHdpZHRo" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0pUQUc=::MA==::RVhQT1JUX0pUQUc=" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1BMSQ==::MA==::VXNlIFNpbXVsYXRpb24gTGluayBNb2Rl" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RPV05TVFJFQU1fUkVBRFk=::MA==::VVNFX0RPV05TVFJFQU1fUkVBRFk=" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NUE9ORU5UX0NMT0NL::MA==::Q09NUE9ORU5UX0NMT0NL" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkFCUklD::Mi4w::RkFCUklD" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19zMA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBRc3lzIFNlcXVlbmNlcg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBRc3lzIFNlcXVlbmNlcg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDExMDAwMQ==::QUNfUk9NX01SMA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMTAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDExMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMTAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMTAwMDAwMA==::QUNfUk9NX01SMQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDEwMDAwMA==::QUNfUk9NX01SMV9NSVJS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMTAwMA==::QUNfUk9NX01SMg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAxMDAwMA==::QUNfUk9NX01SMl9NSVJS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::dHJ1ZQ==::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::Mw==::TVIwX0NBU19MQVRFTkNZ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::Mg==::TVIxX1JUVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MQ==::TVIyX0NXTA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::TUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::Mg==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTM=::TUVNX0lGX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTM=::TUVNX0lGX1JPV19BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::Mg==::TUVNX0lGX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::ZmFsc2U=::TUVNX0xFVkVMSU5H" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::Mg==::TnVtYmVyIG9mIERRUyBncm91cHM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::MTY=::TUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS41::TUVNX0NMS19NQVhfTlM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTUwMC4w::TUVNX0NMS19NQVhfUFM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTQ=::TUVNX1RGQVc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mw==::TUVNX1RSUkQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::NDUw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::Ng==::TUVNX1dUQ0xfSU5U" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::Mg==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::TWljcm9u::TWVtb3J5IHZlbmRvcg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgw::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::NjY2LjY2Nw==::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTM=::Um93IGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::MTY=::VG90YWwgaW50ZXJmYWNlIHdpZHRo" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::UlpRLzI=::T0RUIFJ0dCBub21pbmFsIHZhbHVl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::Ng==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::Nw==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTkw::dElTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTQw::dElIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MzA=::dERTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NjU=::dERIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTI1::dERRU1E=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjU1::dERRU0NL" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNQ==::dERRU1M=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4y::dERTSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4y::dERTUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzYuMA==::dFJBUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNQ==::dFJDRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNQ==::dFJQ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::NQ==::dFdUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::NDUuMA==::dEZBVw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ny41::dFJSRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::dHJ1ZQ==::R0VORVJJQ19QTEw=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::ZmFsc2U=::UkVBRF9GSUZPX0hBTEZfUkFURQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTUx::UEhZX1ZFUlNJT05fTlVNQkVS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::dHJ1ZQ==::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::dHJ1ZQ==::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::dHJ1ZQ==::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::RlVMTA==::VEJfUkFURQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::MTY=::VEJfTUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::NTAuMA==::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::NTAuMCBNSHo=::UkVGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MjAuMA==::UkVGX0NMS19OUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MjAwMDAuMA==::UkVGX0NMS19QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MTAwMDAwMA==::UExMX01FTV9DTEtfRElW" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElW" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVY=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVY=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MTUwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVY=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU1RS::NjAuMCBNSHo=::UExMX05JT1NfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==::NDE2IHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::OS4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::NDYz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MTAuMA==::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=::MjAuMCBNSHo=::UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElW" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS::MzAwLjAgTUh6::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MTAwMDAwMA==::UExMX01FTV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX01FTV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MzAwLjA=::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MC4w::TUVNX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::MC4w::UkVGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::VW5rbm93bg==::UkFURV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::VW5rbm93bg==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::VW5rbm93bg==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MQ==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NQ==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::dHJ1ZQ==::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::Mg==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::MA==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::MA==::RFFTX1BIQVNFX1NISUZU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::NA==::SU9fRFFTX0lOX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::NA==::SU9fRFFTX09VVF9SRVNFUlZF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MA==::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::OA==::Q0FMSUJfTEZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::Ng==::Q0FMSUJfVkZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::MjU=::REVMQVlfUEVSX0RDSEFJTl9UQVA=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::MjU=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::MzE=::RFFTX0VOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MzE=::RFFTX0lOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MzE=::SU9fSU5fREVMQVlfTUFY" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MzE=::SU9fT1VUMV9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::MA==::SU9fT1VUMl9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::Ng==::TUVNX1RfV0w=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::Nw==::TUVNX1RfUkw=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::dHJ1ZQ==::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::ZmFsc2U=::TUFYMTBfUlRMX1NFUQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::UXVpY2s=::QXV0by1jYWxpYnJhdGlvbiBtb2Rl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zNA==::dElT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yNA==::dElI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xOA==::dERT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNjU=::dERI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC42::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC42::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::LTAuMDE=::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::LTAuMDE=::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wMQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wMQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wMg==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURQ==::RnVsbA==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::MQ==::QUZJX1JBVEVfUkFUSU8=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::MTM=::QUZJX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Mw==::QUZJX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::MQ==::QUZJX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::MQ==::QUZJX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::MQ==::QUZJX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::MQ==::QUZJX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::OA==::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::dHJ1ZQ==::SEFSRF9QSFk=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::dHJ1ZQ==::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Nw==::RExMX0RFTEFZX0NUUkxfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==::MTY=::T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::T0NUIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYUE9SVF9TRVFfREVCVUdfQlJJREdF::ZmFsc2U=::RW5hYmxlIEVNSUYgT24tQ2hpcCBEZWJ1ZyBQb3J0" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09SRV9ERUJVR19DT05ORUNUSU9O::RVhQT1JU::RU1JRiBPbi1DaGlwIERlYnVnIFBvcnQgaW50ZXJmYWNlIHR5cGU=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREX0VYVEVSTkFMX1NFUV9ERUJVR19OSU9T::ZmFsc2U=::QWRkIGV4dGVybmFsIE5pb3MgdG8gY29ubmVjdCB0byBzZXF1ZW5jZXIgZGVidWcgaW50ZXJmYWNl" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RURfRVhQT1JUX1NFUV9ERUJVRw==::ZmFsc2U=::RXhwb3J0IHNlcXVlbmNlciBkZWJ1ZyBpbnRlcmZhY2UgZnJvbSBleGFtcGxlIGRlc2lnbg==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREX0VGRklDSUVOQ1lfTU9OSVRPUg==::ZmFsc2U=::RW5hYmxlIHRoZSBFZmZpY2llbmN5IE1vbml0b3IgYW5kIFByb3RvY29sIENoZWNrZXIgb24gdGhlIENvbnRyb2xsZXIgQXZhbG9uIEludGVyZmFjZQ==" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX01BWF9XUklURV9MQVRFTkNZX0NPVU5UX1dJRFRI::Ng==::QUZJX01BWF9XUklURV9MQVRFTkNZX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX01BWF9SRUFEX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::Ng==::QUZJX01BWF9SRUFEX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEg=::MzI=::QVZMX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEg=::MTM=::QVZMX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19wMA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgSGFyZCBQSFkgQ29yZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgSGFyZCBQSFkgQ29yZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDExMDAwMQ==::QUNfUk9NX01SMA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMTAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDExMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMTAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMTAwMDAwMA==::QUNfUk9NX01SMQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDEwMDAwMA==::QUNfUk9NX01SMV9NSVJS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMTAwMA==::QUNfUk9NX01SMg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAxMDAwMA==::QUNfUk9NX01SMl9NSVJS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::dHJ1ZQ==::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::Mw==::TVIwX0NBU19MQVRFTkNZ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::Mg==::TVIxX1JUVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MQ==::TVIyX0NXTA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::TUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::Mg==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTM=::TUVNX0lGX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTM=::TUVNX0lGX1JPV19BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::Mg==::TUVNX0lGX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::ZmFsc2U=::TUVNX0xFVkVMSU5H" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::Mg==::TnVtYmVyIG9mIERRUyBncm91cHM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::MTY=::TUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS41::TUVNX0NMS19NQVhfTlM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTUwMC4w::TUVNX0NMS19NQVhfUFM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTQ=::TUVNX1RGQVc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mw==::TUVNX1RSUkQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::NDUw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::Ng==::TUVNX1dUQ0xfSU5U" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::Mg==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::TWljcm9u::TWVtb3J5IHZlbmRvcg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgw::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::NjY2LjY2Nw==::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTM=::Um93IGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::MTY=::VG90YWwgaW50ZXJmYWNlIHdpZHRo" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::UlpRLzI=::T0RUIFJ0dCBub21pbmFsIHZhbHVl" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::Ng==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::Nw==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTkw::dElTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTQw::dElIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MzA=::dERTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NjU=::dERIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTI1::dERRU1E=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjU1::dERRU0NL" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNQ==::dERRU1M=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4y::dERTSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4y::dERTUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzYuMA==::dFJBUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNQ==::dFJDRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNQ==::dFJQ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::NQ==::dFdUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::NDUuMA==::dEZBVw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ny41::dFJSRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::dHJ1ZQ==::R0VORVJJQ19QTEw=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::ZmFsc2U=::UkVBRF9GSUZPX0hBTEZfUkFURQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTUx::UEhZX1ZFUlNJT05fTlVNQkVS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::dHJ1ZQ==::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::dHJ1ZQ==::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::dHJ1ZQ==::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::RlVMTA==::VEJfUkFURQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::MTY=::VEJfTUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::NTAuMA==::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::NTAuMCBNSHo=::UkVGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MjAuMA==::UkVGX0NMS19OUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MjAwMDAuMA==::UkVGX0NMS19QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MTAwMDAwMA==::UExMX01FTV9DTEtfRElW" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElW" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVY=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVY=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MTUwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVY=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU1RS::NjAuMCBNSHo=::UExMX05JT1NfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==::NDE2IHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::OS4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::NDYz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MTAuMA==::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=::MjAuMCBNSHo=::UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElW" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS::MzAwLjAgTUh6::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::ZmFsc2U=::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MC4w::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::MC4w::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MA==::UExMX01FTV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX01FTV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::MA==::UExMX0FGSV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::MA==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MA==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::MA==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MA==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::MA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MA==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MA==::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREVfQ0FDSEU=::OA==::U1BFRURfR1JBREVfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::TUVNX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::NTAuMA==::UkVGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::RnVsbA==::UkFURV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::TklPUw==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::ZmFsc2U=::UExMX0NMS19QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MQ==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NQ==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::dHJ1ZQ==::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::Mg==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::MA==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::MA==::RFFTX1BIQVNFX1NISUZU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::NA==::SU9fRFFTX0lOX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::NA==::SU9fRFFTX09VVF9SRVNFUlZF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MA==::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::OA==::Q0FMSUJfTEZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::Ng==::Q0FMSUJfVkZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::MjU=::REVMQVlfUEVSX0RDSEFJTl9UQVA=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::MjU=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::MzE=::RFFTX0VOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MzE=::RFFTX0lOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MzE=::SU9fSU5fREVMQVlfTUFY" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MzE=::SU9fT1VUMV9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::MA==::SU9fT1VUMl9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::Ng==::TUVNX1RfV0w=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::Nw==::TUVNX1RfUkw=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::dHJ1ZQ==::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::ZmFsc2U=::TUFYMTBfUlRMX1NFUQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::UXVpY2s=::QXV0by1jYWxpYnJhdGlvbiBtb2Rl" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::dHJ1ZQ==::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zNA==::dElT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yNA==::dElI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xOA==::dERT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNjU=::dERI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC42::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC42::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::LTAuMDE=::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::LTAuMDE=::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wMQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wMQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wMg==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURQ==::RnVsbA==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::MQ==::QUZJX1JBVEVfUkFUSU8=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::MTM=::QUZJX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Mw==::QUZJX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::MQ==::QUZJX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::MQ==::QUZJX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::MQ==::QUZJX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::MQ==::QUZJX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::OA==::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::dHJ1ZQ==::SEFSRF9QSFk=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::dHJ1ZQ==::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Nw==::RExMX0RFTEFZX0NUUkxfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==::MTY=::T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "T0NUX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::T0NUIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEg=::MzI=::QVZMX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEg=::MTM=::QVZMX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_NAME "ZGRyM19wbGww" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgUExML0RMTC9PQ1QgYmxvY2s=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_VERSION "MTUuMQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgUExML0RMTC9PQ1QgYmxvY2s=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDExMDAwMQ==::QUNfUk9NX01SMA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMTAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDExMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMTAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMTAwMDAwMA==::QUNfUk9NX01SMQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDEwMDAwMA==::QUNfUk9NX01SMV9NSVJS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMTAwMA==::QUNfUk9NX01SMg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAxMDAwMA==::QUNfUk9NX01SMl9NSVJS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::dHJ1ZQ==::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::Mw==::TVIwX0NBU19MQVRFTkNZ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::Mg==::TVIxX1JUVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MQ==::TVIyX0NXTA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::TUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::Mg==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTM=::TUVNX0lGX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTM=::TUVNX0lGX1JPV19BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::Mg==::TUVNX0lGX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::ZmFsc2U=::TUVNX0xFVkVMSU5H" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::Mg==::TnVtYmVyIG9mIERRUyBncm91cHM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::MTY=::TUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS41::TUVNX0NMS19NQVhfTlM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTUwMC4w::TUVNX0NMS19NQVhfUFM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTQ=::TUVNX1RGQVc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mw==::TUVNX1RSUkQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::NDUw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::Ng==::TUVNX1dUQ0xfSU5U" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::Mg==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::TWljcm9u::TWVtb3J5IHZlbmRvcg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgw::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::NjY2LjY2Nw==::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTM=::Um93IGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::MTY=::VG90YWwgaW50ZXJmYWNlIHdpZHRo" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::UlpRLzI=::T0RUIFJ0dCBub21pbmFsIHZhbHVl" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::Ng==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::Nw==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTkw::dElTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTQw::dElIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MzA=::dERTIChiYXNlKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NjU=::dERIIChiYXNlKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTI1::dERRU1E=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjU1::dERRU0NL" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNQ==::dERRU1M=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4y::dERTSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4y::dERTUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzYuMA==::dFJBUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNQ==::dFJDRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNQ==::dFJQ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::NQ==::dFdUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::NDUuMA==::dEZBVw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ny41::dFJSRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::dHJ1ZQ==::R0VORVJJQ19QTEw=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::ZmFsc2U=::UkVBRF9GSUZPX0hBTEZfUkFURQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTUx::UEhZX1ZFUlNJT05fTlVNQkVS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::dHJ1ZQ==::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::dHJ1ZQ==::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::dHJ1ZQ==::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::RlVMTA==::VEJfUkFURQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::MTY=::VEJfTUVNX0lGX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::Mg==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::NTAuMA==::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::NTAuMCBNSHo=::UkVGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MjAuMA==::UkVGX0NMS19OUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MjAwMDAuMA==::UkVGX0NMS19QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MTAwMDAwMA==::UExMX01FTV9DTEtfRElW" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElW" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVY=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVY=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MTUwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVY=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU1RS::NjAuMCBNSHo=::UExMX05JT1NfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==::NDE2IHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::OS4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::NDYz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MTAuMA==::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=::MjAuMCBNSHo=::UExMX0NPTkZJR19DTEtfRlJFUV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElW" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVE=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS::MzAwLjAgTUh6::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU1RS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NUUg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MTAwMDAwMA==::UExMX01FTV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX01FTV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MzAwLjA=::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::MTAwMDAwMA==::UExMX0FGSV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MTAwMDAwMA==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MTUwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::NjY2OCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::NjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MjAwMDAwMA==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::NjAuMA==::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MTY2NzAgcHM=::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::NDE2::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::NDYzIHBz::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::NTAwMDAwMA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MjAuMA==::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NTAwMTAgcHM=::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::NjAwMDAwMA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MTUwMDAwMDA=::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MzAwLjA=::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==::MzMzNCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTV9TVFJfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::NjAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MTAwMDAwMA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MC4w::TUVNX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::MC4w::UkVGX0NMS19GUkVRX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::VW5rbm93bg==::UkFURV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::VW5rbm93bg==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::VW5rbm93bg==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MQ==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NQ==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::dHJ1ZQ==::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::Mg==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::MA==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::MA==::RFFTX1BIQVNFX1NISUZU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::NA==::SU9fRFFTX0lOX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::NA==::SU9fRFFTX09VVF9SRVNFUlZF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MA==::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::OA==::Q0FMSUJfTEZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::Ng==::Q0FMSUJfVkZJRk9fT0ZGU0VU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::MjU=::REVMQVlfUEVSX0RDSEFJTl9UQVA=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::MjU=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::MzE=::RFFTX0VOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MzE=::RFFTX0lOX0RFTEFZX01BWA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MzE=::SU9fSU5fREVMQVlfTUFY" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MzE=::SU9fT1VUMV9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::MA==::SU9fT1VUMl9ERUxBWV9NQVg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::Ng==::TUVNX1RfV0w=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::Nw==::TUVNX1RfUkw=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::dHJ1ZQ==::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::ZmFsc2U=::TUFYMTBfUlRMX1NFUQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::UXVpY2s=::QXV0by1jYWxpYnJhdGlvbiBtb2Rl" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zNA==::dElT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yNA==::dElI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xOA==::dERT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNjU=::dERI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC42::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC42::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::LTAuMDE=::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::LTAuMDE=::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wMQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wMQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wMg==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wMg==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::MC4w::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkFURQ==::RnVsbA==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::MQ==::QUZJX1JBVEVfUkFUSU8=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::MTM=::QUZJX0FERFJfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Mw==::QUZJX0JBTktBRERSX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::MQ==::QUZJX0NPTlRST0xfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::MQ==::QUZJX0NTX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::MQ==::QUZJX0NMS19FTl9XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::MQ==::QUZJX09EVF9XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q1lDTE9ORVY=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::Q3ljbG9uZSBW::REVWSUNFX0ZBTUlMWV9QQVJBTQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::OA==::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::dHJ1ZQ==::SEFSRF9QSFk=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::dHJ1ZQ==::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Nw==::RExMX0RFTEFZX0NUUkxfV0lEVEg=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU=" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ==" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QRVJJT0RfUFM=::MjAwMDA=::UkVGX0NMS19QRVJJT0RfUFM=" + +set_global_assignment -library "ddr3" -name VHDL_FILE [file join $::quartus(qip_path) "ddr3.vhd"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_0002.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_reset_controller.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_reset_synchronizer.v"] +set_global_assignment -library "ddr3" -name SDC_FILE [file join $::quartus(qip_path) "ddr3/altera_reset_controller.sdc"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_avalon_st_adapter.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_width_adapter.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_address_alignment.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_burst_uncompressor.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_arbitrator.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_rsp_mux.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_rsp_demux.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_cmd_mux.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_cmd_demux.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_burst_adapter.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_burst_adapter_uncmpr.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_burst_adapter_13_1.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_burst_adapter_new.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_incr_burst_converter.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_wrap_burst_converter.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_default_burst_converter.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_pipeline_stage.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_pipeline_base.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_traffic_limiter.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_reorder_memory.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_sc_fifo.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_router_002.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_router_001.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_2_router.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_slave_agent.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_master_agent.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_slave_translator.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_merlin_master_translator.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_mm_interconnect_1.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_dll_cyclonev.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_oct_cyclonev.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_hard_memory_controller_top_cyclonev.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_dmaster.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_dmaster_p2b_adapter.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_dmaster_b2p_adapter.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_packets_to_master.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_packets_to_bytes.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_bytes_to_packets.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_dmaster_timing_adt.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_jtag_interface.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_jtag_dc_streaming.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_jtag_sld_node.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_jtag_streaming.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_clock_crosser.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_std_synchronizer_nocut.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_idle_remover.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_idle_inserter.v"] +set_global_assignment -library "ddr3" -name SDC_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_st_jtag_interface.sdc"] +set_global_assignment -library "ddr3" -name SOURCE_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_software/sequencer.c"] +set_global_assignment -library "ddr3" -name SOURCE_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_software/sequencer.h"] +set_global_assignment -library "ddr3" -name SOURCE_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_software/sequencer_defines.h"] +set_global_assignment -library "ddr3" -name TCL_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_make_qsys_seq.tcl"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_002.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_001.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_rsp_mux.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_003.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_001.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_003.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_001.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_cmd_mux.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_002.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_001.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_cmd_demux.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_router_006.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_router_004.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_router_003.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_router_002.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_router_001.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0_router.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_irq_mapper.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_mm_interconnect_0.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_avalon_mm_bridge.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_sequencer_mem_no_ifdef_params.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_simple_avalon_mm_bridge.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_reg_file.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_reg_file.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_acv_phase_decode.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_acv_wrapper.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_sv_phase_decode.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_sv_wrapper.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_siii_phase_decode.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_siii_wrapper.sv"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/sequencer_scc_mgr.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altera_mem_if_sequencer_rst.sv"] +set_global_assignment -library "ddr3" -name SOURCE_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_AC_ROM.hex"] +set_global_assignment -library "ddr3" -name SOURCE_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_inst_ROM.hex"] +set_global_assignment -library "ddr3" -name SOURCE_FILE [file join $::quartus(qip_path) "ddr3/ddr3_s0_sequencer_mem.hex"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_clock_pair_generator.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_acv_hard_addr_cmd_pads.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_acv_hard_memphy.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_acv_ldc.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_acv_hard_io_pads.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_generic_ddio.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_reset.v"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_reset_sync.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_phy_csr.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_iss_probe.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0.sv"] +set_global_assignment -library "ddr3" -name VERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_altdqdqs.v"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv"] +set_global_assignment -library "ddr3" -name SOURCE_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0.ppf"] +set_global_assignment -library "ddr3" -name SDC_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0.sdc"] +set_global_assignment -library "ddr3" -name TCL_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_timing.tcl"] +set_global_assignment -library "ddr3" -name TCL_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_report_timing.tcl"] +set_global_assignment -library "ddr3" -name TCL_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_report_timing_core.tcl"] +set_global_assignment -library "ddr3" -name TCL_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_pin_map.tcl"] +set_global_assignment -library "ddr3" -name TCL_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_pin_assignments.tcl"] +set_global_assignment -library "ddr3" -name TCL_FILE [file join $::quartus(qip_path) "ddr3/ddr3_p0_parameters.tcl"] +set_global_assignment -library "ddr3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "ddr3/ddr3_pll0.sv"] + +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_ddr3_emif" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_0002" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_TOOL_NAME "altera_reset_controller" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_reset_controller" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_TOOL_NAME "altera_mm_interconnect" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_TOOL_NAME "altera_avalon_st_adapter" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_TOOL_NAME "error_adapter" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_TOOL_NAME "altera_avalon_st_adapter" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_TOOL_NAME "error_adapter" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_width_adapter" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_merlin_width_adapter" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_mux" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_rsp_demux" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_mux" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_cmd_demux" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_burst_adapter" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_traffic_limiter" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_002" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_router_001" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_2_router" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_TOOL_NAME "altera_avalon_sc_fifo" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_slave_agent" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_merlin_slave_agent" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_master_agent" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_merlin_master_agent" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_slave_translator" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_merlin_slave_translator" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_TOOL_NAME "altera_merlin_master_translator" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_merlin_master_translator" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_TOOL_NAME "altera_mm_interconnect" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_mm_interconnect_1" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_dll" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_mem_if_dll_cyclonev" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_oct" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_mem_if_oct_cyclonev" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_ddr3_hard_memory_controller" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "altera_mem_if_hard_memory_controller_top_cyclonev" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_TOOL_NAME "altera_jtag_avalon_master" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_dmaster" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_TOOL_NAME "channel_adapter" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_dmaster_p2b_adapter" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_TOOL_NAME "channel_adapter" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_dmaster_b2p_adapter" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_TOOL_NAME "altera_avalon_packets_to_master" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_TOOL_VERSION "100.99.98.97" +set_global_assignment -entity "altera_avalon_packets_to_master" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_TOOL_NAME "altera_avalon_st_packets_to_bytes" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_TOOL_VERSION "100.99.98.97" +set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_TOOL_NAME "altera_avalon_st_bytes_to_packets" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_TOOL_VERSION "100.99.98.97" +set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_TOOL_NAME "timing_adapter" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_dmaster_timing_adt" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_TOOL_NAME "altera_jtag_dc_streaming" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_TOOL_VERSION "100.99.98.97" +set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_ddr3_qseq" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_s0" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_ddr3_hard_phy_core" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_p0" -library "ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_TOOL_NAME "altera_mem_if_ddr3_pll" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3_pll0" -library "ddr3" -name IP_TOOL_ENV "mwpim" diff --git a/ip/altera/ddr3.sip b/ip/altera/ddr3.sip new file mode 100644 index 0000000..12cbcb1 --- /dev/null +++ b/ip/altera/ddr3.sip @@ -0,0 +1,9 @@ +set_global_assignment -entity "ddr3" -library "lib_ddr3" -name IP_TOOL_NAME "altera_mem_if_ddr3_emif" +set_global_assignment -entity "ddr3" -library "lib_ddr3" -name IP_TOOL_VERSION "15.1" +set_global_assignment -entity "ddr3" -library "lib_ddr3" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "lib_ddr3" -name SPD_FILE [file join $::quartus(sip_path) "ddr3.spd"] + +set_global_assignment -library "lib_ddr3" -name MISC_FILE [file join $::quartus(sip_path) "ddr3_sim/ddr3.vhd"] +set_global_assignment -library "lib_ddr3" -name MISC_FILE [file join $::quartus(sip_path) "ddr3_sim/ddr3/ddr3_0002.vhd"] +set_global_assignment -library "lib_ddr3" -name MISC_FILE [file join $::quartus(sip_path) "ddr3_sim/ddr3/ddr3_pll0.vho"] +set_global_assignment -library "lib_ddr3" -name MISC_FILE [file join $::quartus(sip_path) "ddr3_sim/ddr3/ddr3_pll0_sim_delay.vhd"] diff --git a/ip/altera/ddr3.sopcinfo b/ip/altera/ddr3.sopcinfo new file mode 100644 index 0000000..cf0788f --- /dev/null +++ b/ip/altera/ddr3.sopcinfo @@ -0,0 +1,51759 @@ + + + + + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + postgeneration.simulation.init_file.param_name + ABS_RAM_MEM_INIT_FILENAME + + + postgeneration.simulation.init_file.type + MEM_INIT + + + testbench.partner.map.memory + mem_model.memory + + + testbench.partner.mem_model.class + altera_mem_if_ddr3_mem_model + + + testbench.partner.mem_model.parameter.AC_PARITY + false + + + testbench.partner.mem_model.parameter.AC_ROM_MR0 + 0001000110001 + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_CALIB + + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET + 0001100110000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET_MIRR + 0001011001000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_MIRR + 0001001001001 + + + testbench.partner.mem_model.parameter.AC_ROM_MR1 + 0000001000000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR1_CALIB + + + + testbench.partner.mem_model.parameter.AC_ROM_MR1_MIRR + 0000000100000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR1_OCD_ENABLE + + + + testbench.partner.mem_model.parameter.AC_ROM_MR2 + 0000000001000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR2_MIRR + 0000000010000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR3 + 0000000000000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR3_MIRR + 0000000000000 + + + testbench.partner.mem_model.parameter.ADDR_CMD_DDR + 0 + + + testbench.partner.mem_model.parameter.ADDR_RATE_RATIO + 1 + + + testbench.partner.mem_model.parameter.AFI_ADDR_WIDTH + 13 + + + testbench.partner.mem_model.parameter.AFI_BANKADDR_WIDTH + 3 + + + testbench.partner.mem_model.parameter.AFI_CLK_EN_WIDTH + 1 + + + testbench.partner.mem_model.parameter.AFI_CLK_PAIR_COUNT + 1 + + + testbench.partner.mem_model.parameter.AFI_CONTROL_WIDTH + 1 + + + testbench.partner.mem_model.parameter.AFI_CS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.AFI_DM_WIDTH + 4 + + + testbench.partner.mem_model.parameter.AFI_DQ_WIDTH + 32 + + + testbench.partner.mem_model.parameter.AFI_ODT_WIDTH + 1 + + + testbench.partner.mem_model.parameter.AFI_RATE_RATIO + 1 + + + testbench.partner.mem_model.parameter.AFI_RLAT_WIDTH + 6 + + + testbench.partner.mem_model.parameter.AFI_RRANK_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_WLAT_WIDTH + 6 + + + testbench.partner.mem_model.parameter.AFI_WRANK_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_WRITE_DQS_WIDTH + 2 + + + testbench.partner.mem_model.parameter.ALTMEMPHY_COMPATIBLE_MODE + false + + + testbench.partner.mem_model.parameter.AP_MODE + false + + + testbench.partner.mem_model.parameter.AP_MODE_EN + 0 + + + testbench.partner.mem_model.parameter.CFG_TCCD + 1 + + + testbench.partner.mem_model.parameter.CFG_TCCD_NS + 2.5 + + + testbench.partner.mem_model.parameter.CTL_RD_TO_PCH_EXTRA_CLK + 0 + + + testbench.partner.mem_model.parameter.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK + 1 + + + testbench.partner.mem_model.parameter.CTL_RD_TO_RD_EXTRA_CLK + 0 + + + testbench.partner.mem_model.parameter.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK + 2 + + + testbench.partner.mem_model.parameter.CTL_WR_TO_WR_EXTRA_CLK + 0 + + + testbench.partner.mem_model.parameter.CUT_NEW_FAMILY_TIMING + true + + + testbench.partner.mem_model.parameter.DATA_RATE_RATIO + 2 + + + testbench.partner.mem_model.parameter.DAT_DATA_WIDTH + 32 + + + testbench.partner.mem_model.parameter.DEVICE_DEPTH + 1 + + + testbench.partner.mem_model.parameter.DEVICE_FAMILY + Cyclone V + + + testbench.partner.mem_model.parameter.DEVICE_FAMILY_PARAM + + + + testbench.partner.mem_model.parameter.DEVICE_WIDTH + 1 + + + testbench.partner.mem_model.parameter.DISABLE_CHILD_MESSAGING + false + + + testbench.partner.mem_model.parameter.DISCRETE_FLY_BY + true + + + testbench.partner.mem_model.parameter.DQ_DDR + 1 + + + testbench.partner.mem_model.parameter.DUPLICATE_AC + false + + + testbench.partner.mem_model.parameter.FLY_BY + true + + + testbench.partner.mem_model.parameter.FORCE_DQS_TRACKING + AUTO + + + testbench.partner.mem_model.parameter.FORCE_SHADOW_REGS + AUTO + + + testbench.partner.mem_model.parameter.HARD_EMIF + true + + + testbench.partner.mem_model.parameter.HARD_PHY + true + + + testbench.partner.mem_model.parameter.HHP_HPS + false + + + testbench.partner.mem_model.parameter.HHP_HPS_SIMULATION + false + + + testbench.partner.mem_model.parameter.HHP_HPS_VERIFICATION + false + + + testbench.partner.mem_model.parameter.HPS_PROTOCOL + DEFAULT + + + testbench.partner.mem_model.parameter.IS_ES_DEVICE + false + + + testbench.partner.mem_model.parameter.LRDIMM + false + + + testbench.partner.mem_model.parameter.LRDIMM_EXTENDED_CONFIG + 0x0 + + + testbench.partner.mem_model.parameter.LRDIMM_INT + 0 + + + testbench.partner.mem_model.parameter.MEM_ASR + Manual + + + testbench.partner.mem_model.parameter.MEM_ATCL + Disabled + + + testbench.partner.mem_model.parameter.MEM_ATCL_INT + 0 + + + testbench.partner.mem_model.parameter.MEM_AUTO_LEVELING_MODE + true + + + testbench.partner.mem_model.parameter.MEM_BANKADDR_WIDTH + 3 + + + testbench.partner.mem_model.parameter.MEM_BL + OTF + + + testbench.partner.mem_model.parameter.MEM_BT + Sequential + + + testbench.partner.mem_model.parameter.MEM_BURST_LENGTH + 8 + + + testbench.partner.mem_model.parameter.MEM_CK_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_CLK_EN_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_CLK_FREQ + 300.0 + + + testbench.partner.mem_model.parameter.MEM_CLK_FREQ_MAX + 666.667 + + + testbench.partner.mem_model.parameter.MEM_CLK_MAX_NS + 1.5 + + + testbench.partner.mem_model.parameter.MEM_CLK_MAX_PS + 1500.0 + + + testbench.partner.mem_model.parameter.MEM_CLK_TO_DQS_CAPTURE_DELAY + 100000 + + + testbench.partner.mem_model.parameter.MEM_COL_ADDR_WIDTH + 10 + + + testbench.partner.mem_model.parameter.MEM_CS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_DLL_EN + true + + + testbench.partner.mem_model.parameter.MEM_DQS_TO_CLK_CAPTURE_DELAY + 450 + + + testbench.partner.mem_model.parameter.MEM_DQ_PER_DQS + 8 + + + testbench.partner.mem_model.parameter.MEM_DQ_WIDTH + 16 + + + testbench.partner.mem_model.parameter.MEM_DRV_STR + RZQ/6 + + + testbench.partner.mem_model.parameter.MEM_FORMAT + DISCRETE + + + testbench.partner.mem_model.parameter.MEM_GUARANTEED_WRITE_INIT + false + + + testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH + 13 + + + testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH_MIN + 13 + + + testbench.partner.mem_model.parameter.MEM_IF_BANKADDR_WIDTH + 3 + + + testbench.partner.mem_model.parameter.MEM_IF_BOARD_BASE_DELAY + 10 + + + testbench.partner.mem_model.parameter.MEM_IF_CHIP_BITS + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CK_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CLK_EN_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CLK_PAIR_COUNT + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_COL_ADDR_WIDTH + 10 + + + testbench.partner.mem_model.parameter.MEM_IF_CONTROL_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CS_PER_DIMM + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CS_PER_RANK + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_DM_PINS_EN + true + + + testbench.partner.mem_model.parameter.MEM_IF_DM_WIDTH + 2 + + + testbench.partner.mem_model.parameter.MEM_IF_DQSN_EN + true + + + testbench.partner.mem_model.parameter.MEM_IF_DQS_WIDTH + 2 + + + testbench.partner.mem_model.parameter.MEM_IF_DQ_WIDTH + 16 + + + testbench.partner.mem_model.parameter.MEM_IF_LRDIMM_RM + 0 + + + testbench.partner.mem_model.parameter.MEM_IF_NUMBER_OF_RANKS + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_ODT_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_RD_TO_WR_TURNAROUND_OCT + 2 + + + testbench.partner.mem_model.parameter.MEM_IF_READ_DQS_WIDTH + 2 + + + testbench.partner.mem_model.parameter.MEM_IF_ROW_ADDR_WIDTH + 13 + + + testbench.partner.mem_model.parameter.MEM_IF_SIM_VALID_WINDOW + 0 + + + testbench.partner.mem_model.parameter.MEM_IF_WRITE_DQS_WIDTH + 2 + + + testbench.partner.mem_model.parameter.MEM_IF_WR_TO_RD_TURNAROUND_OCT + 3 + + + testbench.partner.mem_model.parameter.MEM_INIT_EN + false + + + testbench.partner.mem_model.parameter.MEM_INIT_FILE + + + + testbench.partner.mem_model.parameter.MEM_LEVELING + false + + + testbench.partner.mem_model.parameter.MEM_LRDIMM_ENABLED + false + + + testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING + 0 + + + testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING_DEC + 0 + + + testbench.partner.mem_model.parameter.MEM_NUMBER_OF_DIMMS + 1 + + + testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DEVICE + 1 + + + testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DIMM + 1 + + + testbench.partner.mem_model.parameter.MEM_PD + DLL off + + + testbench.partner.mem_model.parameter.MEM_RANK_MULTIPLICATION_FACTOR + 1 + + + testbench.partner.mem_model.parameter.MEM_REGDIMM_ENABLED + false + + + testbench.partner.mem_model.parameter.MEM_ROW_ADDR_WIDTH + 13 + + + testbench.partner.mem_model.parameter.MEM_RTT_NOM + RZQ/2 + + + testbench.partner.mem_model.parameter.MEM_RTT_WR + Dynamic ODT off + + + testbench.partner.mem_model.parameter.MEM_SRT + Normal + + + testbench.partner.mem_model.parameter.MEM_TCL + 7 + + + testbench.partner.mem_model.parameter.MEM_TDQSCK + 1 + + + testbench.partner.mem_model.parameter.MEM_TFAW + 14 + + + testbench.partner.mem_model.parameter.MEM_TFAW_NS + 45.0 + + + testbench.partner.mem_model.parameter.MEM_TINIT_CK + 150000 + + + testbench.partner.mem_model.parameter.MEM_TINIT_US + 500 + + + testbench.partner.mem_model.parameter.MEM_TMRD_CK + 4 + + + testbench.partner.mem_model.parameter.MEM_TRAS + 11 + + + testbench.partner.mem_model.parameter.MEM_TRAS_NS + 36.0 + + + testbench.partner.mem_model.parameter.MEM_TRC + 15 + + + testbench.partner.mem_model.parameter.MEM_TRCD + 5 + + + testbench.partner.mem_model.parameter.MEM_TRCD_NS + 13.5 + + + testbench.partner.mem_model.parameter.MEM_TREFI + 2341 + + + testbench.partner.mem_model.parameter.MEM_TREFI_US + 7.8 + + + testbench.partner.mem_model.parameter.MEM_TRFC + 34 + + + testbench.partner.mem_model.parameter.MEM_TRFC_NS + 110.0 + + + testbench.partner.mem_model.parameter.MEM_TRP + 5 + + + testbench.partner.mem_model.parameter.MEM_TRP_NS + 13.5 + + + testbench.partner.mem_model.parameter.MEM_TRRD + 3 + + + testbench.partner.mem_model.parameter.MEM_TRRD_NS + 7.5 + + + testbench.partner.mem_model.parameter.MEM_TRTP + 3 + + + testbench.partner.mem_model.parameter.MEM_TRTP_NS + 7.5 + + + testbench.partner.mem_model.parameter.MEM_TWR + 5 + + + testbench.partner.mem_model.parameter.MEM_TWR_NS + 15.0 + + + testbench.partner.mem_model.parameter.MEM_TWTR + 5 + + + testbench.partner.mem_model.parameter.MEM_TYPE + DDR3 + + + testbench.partner.mem_model.parameter.MEM_USER_LEVELING_MODE + Leveling + + + testbench.partner.mem_model.parameter.MEM_VENDOR + Micron + + + testbench.partner.mem_model.parameter.MEM_VERBOSE + true + + + testbench.partner.mem_model.parameter.MEM_WTCL + 6 + + + testbench.partner.mem_model.parameter.MEM_WTCL_INT + 6 + + + testbench.partner.mem_model.parameter.MR0_BL + 1 + + + testbench.partner.mem_model.parameter.MR0_BT + 0 + + + testbench.partner.mem_model.parameter.MR0_CAS_LATENCY + 3 + + + testbench.partner.mem_model.parameter.MR0_DLL + 1 + + + testbench.partner.mem_model.parameter.MR0_PD + 0 + + + testbench.partner.mem_model.parameter.MR0_WR + 1 + + + testbench.partner.mem_model.parameter.MR1_AL + 0 + + + testbench.partner.mem_model.parameter.MR1_DLL + 0 + + + testbench.partner.mem_model.parameter.MR1_DQS + 0 + + + testbench.partner.mem_model.parameter.MR1_ODS + 0 + + + testbench.partner.mem_model.parameter.MR1_QOFF + 0 + + + testbench.partner.mem_model.parameter.MR1_RDQS + 0 + + + testbench.partner.mem_model.parameter.MR1_RTT + 2 + + + testbench.partner.mem_model.parameter.MR1_TDQS + 0 + + + testbench.partner.mem_model.parameter.MR1_WL + 0 + + + testbench.partner.mem_model.parameter.MR2_ASR + 0 + + + testbench.partner.mem_model.parameter.MR2_CWL + 1 + + + testbench.partner.mem_model.parameter.MR2_RTT_WR + 0 + + + testbench.partner.mem_model.parameter.MR2_SRF + 0 + + + testbench.partner.mem_model.parameter.MR2_SRT + 0 + + + testbench.partner.mem_model.parameter.MR3_MPR + 0 + + + testbench.partner.mem_model.parameter.MR3_MPR_AA + 0 + + + testbench.partner.mem_model.parameter.MR3_MPR_RF + 0 + + + testbench.partner.mem_model.parameter.MRS_MIRROR_PING_PONG_ATSO + false + + + testbench.partner.mem_model.parameter.NEXTGEN + true + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY + CYCLONEV + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID + true + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM + + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID + false + + + testbench.partner.mem_model.parameter.PINGPONGPHY_EN + false + + + testbench.partner.mem_model.parameter.PRE_V_SERIES_FAMILY + false + + + testbench.partner.mem_model.parameter.RATE + Full + + + testbench.partner.mem_model.parameter.RDIMM + false + + + testbench.partner.mem_model.parameter.RDIMM_CONFIG + 0 + + + testbench.partner.mem_model.parameter.RDIMM_INT + 0 + + + testbench.partner.mem_model.parameter.REFRESH_BURST_VALIDATION + false + + + testbench.partner.mem_model.parameter.SCC_DATA_WIDTH + 1 + + + testbench.partner.mem_model.parameter.SPEED_GRADE + 8 + + + testbench.partner.mem_model.parameter.SYS_INFO_DEVICE_FAMILY + Cyclone V + + + testbench.partner.mem_model.parameter.TIMING_TDH + 65 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCK + 255 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCKDL + 1200 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCKDM + 900 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCKDS + 450 + + + testbench.partner.mem_model.parameter.TIMING_TDQSQ + 125 + + + testbench.partner.mem_model.parameter.TIMING_TDQSS + 0.25 + + + testbench.partner.mem_model.parameter.TIMING_TDS + 30 + + + testbench.partner.mem_model.parameter.TIMING_TDSH + 0.2 + + + testbench.partner.mem_model.parameter.TIMING_TDSS + 0.2 + + + testbench.partner.mem_model.parameter.TIMING_TIH + 140 + + + testbench.partner.mem_model.parameter.TIMING_TIS + 190 + + + testbench.partner.mem_model.parameter.TIMING_TQH + 0.38 + + + testbench.partner.mem_model.parameter.TIMING_TQSH + 0.4 + + + testbench.partner.mem_model.parameter.TRK_PARALLEL_SCC_LOAD + false + + + testbench.partner.mem_model.parameter.USE_DQS_TRACKING + false + + + testbench.partner.mem_model.parameter.USE_HPS_DQS_TRACKING + false + + + testbench.partner.mem_model.parameter.USE_MEM_CLK_FREQ + false + + + testbench.partner.mem_model.parameter.USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY + true + + + testbench.partner.mem_model.parameter.USE_SHADOW_REGS + false + + + java.lang.String + 0001000110001 + true + true + false + true + + + java.lang.String + 0001001001001 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0001100110000 + true + true + false + true + + + java.lang.String + 0001011001000 + true + true + false + true + + + java.lang.String + 0000001000000 + true + true + false + true + + + java.lang.String + 0000000100000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0000000001000 + true + true + false + true + + + java.lang.String + 0000000010000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true 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+ false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 1.5 + true + true + false + true + + + double + 1500.0 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 11 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 100000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 6 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Micron + false + true + true + true + + + java.lang.String + DISCRETE + false + false + true + true + + + boolean + false + true + false + true + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + 0x0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + double + 666.667 + false + true + true + true + + + int + 13 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 3 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + OTF + false + true + false + true + + + java.lang.String + Sequential + false + true + true + true + + + java.lang.String + Manual + false + true + true + true + + + java.lang.String + Normal + false + true + true + true + + + java.lang.String + DLL off + false + true + true + true + + + java.lang.String + RZQ/6 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + RZQ/2 + false + true + true + true + + + java.lang.String + Dynamic ODT off + false + true + true + true + + + int + 6 + false + true + true + true + + + java.lang.String + Disabled + false + true + true + true + + + int + 7 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + Leveling + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + false + false + true + + + int + 32 + false + false + false + true + + + int + 190 + false + true + true + true + + + int + 140 + false + true + true + true + + + int + 30 + false + true + true + true + + + int + 65 + false + true + true + true + + + int + 125 + false + true + true + true + + + double + 0.38 + false + true + true + true + + + int + 255 + false + true + true + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + double + 0.25 + false + true + true + true + + + double + 0.4 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + int + 500 + false + true + true + true + + + int + 150000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + false + true + true + true + + + double + 36.0 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 7.8 + false + true + true + true + + + double + 110.0 + false + true + true + true + + + double + 2.5 + false + true + false + true + + + double + 15.0 + false + true + true + true + + + int + 5 + false + true + true + true + + + double + 45.0 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + java.lang.String + Full + false + true + true + true + + + double + 300.0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 25 + true + false + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + false + false + true + + + int + 8 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 3 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + nextgen_v110 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 512 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 0 + true + true + false + true + + + [Ljava.lang.String; + Port 0 + true + true + true + true + + + int + 32 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + [Ljava.lang.String; + F0,None,None,None,None,None + true + false + true + true + + + [Ljava.lang.String; + F0,None,None,None,None,None + true + false + true + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + BL_8 + true + true + false + true + + + java.lang.String + DWIDTH_16 + true + true + false + true + + + java.lang.String + SELF_RFSH_EXIT_CYCLES_512 + true + true + false + true + + + java.lang.String + STARVE_LIMIT_4 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + NO_CLR_INTR + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + BI_DIRECTION + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + CHIP_ROW_BANK_COL + true + true + false + true + + + java.lang.String + CTL_ECC_DISABLED + true + true + false + true + + + java.lang.String + CTL_ECC_RMW_DISABLED + true + true + false + true + + + java.lang.String + REGDIMM_DISABLED + true + true + false + true + + + java.lang.String + CTL_USR_REFRESH_DISABLED + true + true + false + true + + + java.lang.String + DATA_WIDTH_32_BIT + true + true + false + true + + + java.lang.String + BONDING_LATENCY_0 + true + true + false + true + + + java.lang.String + DFX_BYPASS_DISABLED + true + true + false + true + + + java.lang.String + MERGING_ENABLED + true + true + false + true + + + java.lang.String + ECC_DQ_WIDTH_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + GEN_DBE_DISABLED + true + true + false + true + + + java.lang.String + GEN_SBE_DISABLED + true + true + false + true + + + java.lang.String + FIFO_SET_2 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + AL_0 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_3 + true + true + false + true + + + java.lang.String + MEM_IF_BURSTLENGTH_8 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_10 + true + true + false + true + + + java.lang.String + MEM_IF_CS_PER_RANK_1 + true + true + false + true + + + java.lang.String + MEM_IF_CS_WIDTH_1 + true + true + false + true + + + java.lang.String + MEM_IF_DQ_PER_CHIP_8 + true + true + false + true + + + java.lang.String + DQS_WIDTH_2 + true + true + false + true + + + java.lang.String + MEM_IF_DWIDTH_16 + true + true + false + true + + + java.lang.String + DDR3_SDRAM + true + true + false + true + + + java.lang.String + ADDR_WIDTH_13 + true + true + false + true + + + java.lang.String + DDR3_1600_8_8_8 + true + true + false + true + + + java.lang.String + TCCD_4 + true + true + false + true + + + java.lang.String + TCL_7 + true + true + false + true + + + java.lang.String + TCWL_6 + true + true + false + true + + + java.lang.String + TFAW_14 + true + true + false + true + + + java.lang.String + TMRD_4 + true + true + false + true + + + java.lang.String + TRAS_11 + true + true + false + true + + + java.lang.String + TRC_15 + true + true + false + true + + + java.lang.String + TRCD_5 + true + true + false + true + + + java.lang.String + TRP_5 + true + true + false + true + + + java.lang.String + TRRD_3 + true + true + false + true + + + java.lang.String + TRTP_3 + true + true + false + true + + + java.lang.String + TWR_5 + true + true + false + true + + + java.lang.String + TWTR_5 + true + true + false + true + + + java.lang.String + MP_BL_8 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + SLOW_EXIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + ODT_DISABLED + true + true + false + true + + + java.lang.String + NO_DATA_REORDERING + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + NORMAL_MODE + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WRITE_CHIP0_ODT0_CHIP1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 10 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + BI_DIRECTION + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 4 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + false + true + true + + + java.lang.String + 5 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 10 + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + INTERNAL_JTAG + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + false + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 4 + false + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 8 + true + true + false + true + + + int + 6 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + false + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + INTER_BANK + false + false + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + [Ljava.lang.Integer; + 32,32,32,32,32,32 + false + true + true + true + + + [Ljava.lang.Integer; + 1,1,1,1,1,1 + false + true + true + true + + + [Ljava.lang.Integer; + 0,0,0,0,0,0 + false + true + true + true + + + [Ljava.lang.String; + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + false + true + true + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 151 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + FULL + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 2 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 50.0 + false + true + true + true + + + java.lang.String + 50.0 MHz + true + true + false + true + + + double + 20.0 + true + true + false + true + + + double + 20000.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 150.0 MHz + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 60.0 MHz + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 416 ps + true + true + false + true + + + double + 9.0 + true + true + false + true + + + int + 463 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + double + 10.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 20.0 MHz + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 10.0 + true + true + false + true + + + double + 500.0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + java.lang.String + 8 + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 300.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + java.lang.String + Full + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + CYCLONEV + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + NIOS + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + 0_0000_0000_0000 + false + true + false + true + + + java.lang.String + 0_0000_0000_1000 + false + true + false + true + + + int + 35100 + false + true + false + true + + + int + 15000 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 350 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + MISSING_MODEL + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 7 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 3.333 + true + true + false + true + + + double + 3333.0 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 416 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + SSTL-15 + true + true + true + true + + + boolean + true + true + true + false + true + + + java.lang.String + NIOS + false + true + false + true + + + java.lang.String + ../ + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 7 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + false + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + 1.5V DDR3 + false + true + true + true + + + java.lang.String + Top_Bottom + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + INVERTED_DQS_BUS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DIFFERENTIAL + false + true + false + true + + + int + 32 + false + true + false + true + + + java.lang.String + Quick + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 13 + true + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + INTERNAL_JTAG + false + true + false + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.34 + true + true + true + true + + + double + 0.24 + true + true + true + true + + + double + 0.18 + true + true + true + true + + + double + 0.165 + true + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.6 + false + true + true + true + + + double + 0.6 + false + true + true + true + + + double + -0.01 + false + true + true + true + + + double + -0.01 + true + true + false + true + + + double + 0.01 + false + true + true + true + + + double + 0.01 + true + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.02 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + EXPORT + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + meminit + false + true + false + true + + + int + 7 + true + true + false + true + + + int + 6 + true + true + false + true + + + java.lang.String + HIGH + true + true + false + true + + + int + 8 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + int + 16 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + java.lang.String + 5CEBA2F17A7 + false + true + false + true + DEVICE + + + java.lang.String + 7 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + false + true + true + true + CLOCK_RATE + in_clk + + + long + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk + Output + 1 + clk + + + false + pll0 + pll_ref_clk + pll0.pll_ref_clk + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + in_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_n + Output + 1 + reset_n + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + in_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_n + Output + 1 + reset_n + + + + + + + long + 300000000 + false + true + true + true + CLOCK_RATE + in_clk + + + long + 0 + false + true + true + true + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 300000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 300000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk + Output + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 300000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk_1 + Output + 1 + clk + + + + + + + long + 150000000 + false + true + true + true + CLOCK_RATE + in_clk + + + long + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 150000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 150000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk + Output + 1 + clk + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + int + 2 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + in_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_1_n + Output + 1 + reset_n + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + int + 2 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + in_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_1_n + Output + 1 + reset_n + + + + + + + java.lang.String + 0001000110001 + true + true + false + true + + + java.lang.String + 0001001001001 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0001100110000 + true + true + false + true + + + java.lang.String + 0001011001000 + true + true + false + true + + + java.lang.String + 0000001000000 + true + true + false + true + + + java.lang.String + 0000000100000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0000000001000 + true + true + false + true + + + java.lang.String + 0000000010000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 8 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 1.5 + true + true + false + true + + + double + 1500.0 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 11 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 100000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 6 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Micron + false + true + true + true + + + java.lang.String + DISCRETE + false + false + true + true + + + boolean + false + true + false + true + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + 0x0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + double + 666.667 + false + true + true + true + + + int + 13 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 3 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + OTF + false + true + false + true + + + java.lang.String + Sequential + false + true + true + true + + + java.lang.String + Manual + false + true + true + true + + + java.lang.String + Normal + false + true + true + true + + + java.lang.String + DLL off + false + true + true + true + + + java.lang.String + RZQ/6 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + RZQ/2 + false + true + true + true + + + java.lang.String + Dynamic ODT off + false + true + true + true + + + int + 6 + false + true + true + true + + + java.lang.String + Disabled + false + true + true + true + + + int + 7 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + Leveling + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + false + false + true + + + int + 32 + false + false + false + true + + + int + 190 + false + true + true + true + + + int + 140 + false + true + true + true + + + int + 30 + false + true + true + true + + + int + 65 + false + true + true + true + + + int + 125 + false + true + true + true + + + double + 0.38 + false + true + true + true + + + int + 255 + false + true + true + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + double + 0.25 + false + true + true + true + + + double + 0.4 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + int + 500 + false + true + true + true + + + int + 150000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + false + true + true + true + + + double + 36.0 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 7.8 + false + true + true + true + + + double + 110.0 + false + true + true + true + + + double + 2.5 + false + true + false + true + + + double + 15.0 + false + true + true + true + + + int + 5 + false + true + true + true + + + double + 45.0 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 151 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + FULL + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 2 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 50.0 + false + true + true + true + + + java.lang.String + 50.0 MHz + true + true + false + true + + + double + 20.0 + true + true + false + true + + + double + 20000.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 150.0 MHz + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 60.0 MHz + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 416 ps + true + true + false + true + + + double + 9.0 + true + true + false + true + + + int + 463 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + double + 10.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 20.0 MHz + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + double + 10.0 + false + true + false + true + + + double + 500.0 + false + true + false + true + + + double + 10.0 + true + true + false + true + + + double + 500.0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 2500 + false + true + false + true + + + java.lang.String + 2500 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 2500 + false + true + false + true + + + java.lang.String + 2500 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 150.0 + false + true + false + true + + + java.lang.String + 6668 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 2000000 + false + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 60.0 + false + true + false + true + + + java.lang.String + 16670 ps + false + true + false + true + + + int + 416 + false + true + false + true + + + java.lang.String + 463 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 5000000 + false + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 20.0 + false + true + false + true + + + java.lang.String + 50010 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 15000000 + false + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + Unknown + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Unknown + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + Unknown + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + 0_0000_0000_0000 + false + true + false + true + + + java.lang.String + 0_0000_0000_1000 + false + true + false + true + + + int + 35100 + false + true + false + true + + + int + 15000 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 350 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 4 + true + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + MISSING_MODEL + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 7 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 3.333 + true + true + false + true + + + double + 3333.0 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 416 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + SSTL-15 + true + true + true + true + + + boolean + true + true + true + false + true + + + java.lang.String + NIOS + false + true + false + true + + + java.lang.String + ../ + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 7 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + false + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + 1.5V DDR3 + false + true + true + true + + + boolean + false + false + false + false + true + + + java.lang.String + Top_Bottom + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + INVERTED_DQS_BUS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DIFFERENTIAL + false + true + false + true + + + int + 32 + false + true + false + true + + + java.lang.String + Quick + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 13 + true + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + java.lang.String + INTERNAL_JTAG + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.34 + true + true + true + true + + + double + 0.24 + true + true + true + true + + + double + 0.18 + true + true + true + true + + + double + 0.165 + true + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.6 + false + true + true + true + + + double + 0.6 + false + true + true + true + + + double + -0.01 + false + true + true + true + + + double + -0.01 + true + true + false + true + + + double + 0.01 + false + true + true + true + + + double + 0.01 + true + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.02 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + java.lang.String + Full + false + true + true + true + + + double + 300.0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 7 + true + true + false + true + + + int + 6 + true + true + false + true + + + java.lang.String + HIGH + true + true + false + true + + + int + 8 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + int + 20000 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + global_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + long + 300000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + afi_clk + Output + 1 + clk + + + true + afi_clk + in_clk + afi_clk.in_clk + + + false + p0 + afi_clk + p0.afi_clk + + + false + c0 + afi_clk + c0.afi_clk + + + + + + java.lang.String + + false + true + true + true + + + long + 150000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + afi_half_clk + Output + 1 + clk + + + false + afi_half_clk + in_clk + afi_half_clk.in_clk + + + false + p0 + afi_half_clk + p0.afi_half_clk + + + false + c0 + afi_half_clk + c0.afi_half_clk + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + pll_ref_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + pll_mem_clk + Output + 1 + pll_mem_clk + + + pll_write_clk + Output + 1 + pll_write_clk + + + pll_locked + Output + 1 + pll_locked + + + pll_write_clk_pre_phy_clk + Output + 1 + pll_write_clk_pre_phy_clk + + + pll_addr_cmd_clk + Output + 1 + pll_addr_cmd_clk + + + pll_avl_clk + Output + 1 + pll_avl_clk + + + pll_config_clk + Output + 1 + pll_config_clk + + + pll_mem_phy_clk + Output + 1 + pll_mem_phy_clk + + + afi_phy_clk + Output + 1 + afi_phy_clk + + + pll_avl_phy_clk + Output + 1 + pll_avl_phy_clk + + + + + + + java.lang.String + 0001000110001 + true + true + false + true + + + java.lang.String + 0001001001001 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0001100110000 + true + true + false + true + + + java.lang.String + 0001011001000 + true + true + false + true + + + java.lang.String + 0000001000000 + true + true + false + true + + + java.lang.String + 0000000100000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0000000001000 + true + true + false + true + + + java.lang.String + 0000000010000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 8 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 1.5 + true + true + false + true + + + double + 1500.0 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 11 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 100000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 6 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Micron + false + true + true + true + + + java.lang.String + DISCRETE + false + false + true + true + + + boolean + false + true + false + true + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + 0x0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + double + 666.667 + false + true + true + true + + + int + 13 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 3 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + OTF + false + true + false + true + + + java.lang.String + Sequential + false + true + true + true + + + java.lang.String + Manual + false + true + true + true + + + java.lang.String + Normal + false + true + true + true + + + java.lang.String + DLL off + false + true + true + true + + + java.lang.String + RZQ/6 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + RZQ/2 + false + true + true + true + + + java.lang.String + Dynamic ODT off + false + true + true + true + + + int + 6 + false + true + true + true + + + java.lang.String + Disabled + false + true + true + true + + + int + 7 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + Leveling + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + false + false + true + + + int + 32 + false + false + false + true + + + int + 190 + false + true + true + true + + + int + 140 + false + true + true + true + + + int + 30 + false + true + true + true + + + int + 65 + false + true + true + true + + + int + 125 + false + true + true + true + + + double + 0.38 + false + true + true + true + + + int + 255 + false + true + true + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + double + 0.25 + false + true + true + true + + + double + 0.4 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + int + 500 + false + true + true + true + + + int + 150000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + false + true + true + true + + + double + 36.0 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 7.8 + false + true + true + true + + + double + 110.0 + false + true + true + true + + + double + 2.5 + false + true + false + true + + + double + 15.0 + false + true + true + true + + + int + 5 + false + true + true + true + + + double + 45.0 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 151 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + FULL + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 2 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 50.0 + false + true + true + true + + + java.lang.String + 50.0 MHz + true + true + false + true + + + double + 20.0 + true + true + false + true + + + double + 20000.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 150.0 MHz + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 60.0 MHz + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 416 ps + true + true + false + true + + + double + 9.0 + true + true + false + true + + + int + 463 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + double + 10.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 20.0 MHz + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 10.0 + true + true + false + true + + + double + 500.0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + java.lang.String + 8 + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 300.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + java.lang.String + Full + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + CYCLONEV + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + NIOS + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + 0_0000_0000_0000 + false + true + false + true + + + java.lang.String + 0_0000_0000_1000 + false + true + false + true + + + int + 35100 + false + true + false + true + + + int + 15000 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 350 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 4 + true + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + MISSING_MODEL + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 7 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 3.333 + true + true + false + true + + + double + 3333.0 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 416 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + SSTL-15 + true + true + true + true + + + boolean + true + true + true + false + true + + + java.lang.String + NIOS + false + true + false + true + + + java.lang.String + ../ + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 7 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + false + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + 1.5V DDR3 + false + true + true + true + + + boolean + false + false + false + false + true + + + java.lang.String + Top_Bottom + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + INVERTED_DQS_BUS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DIFFERENTIAL + false + true + false + true + + + int + 32 + false + true + false + true + + + java.lang.String + Quick + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 13 + true + true + false + true + + + int + 8 + false + true + false + true + + + boolean + true + false + true + true + true + + + java.lang.String + INTERNAL_JTAG + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.34 + true + true + true + true + + + double + 0.24 + true + true + true + true + + + double + 0.18 + true + true + true + true + + + double + 0.165 + true + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.6 + false + true + true + true + + + double + 0.6 + false + true + true + true + + + double + -0.01 + false + true + true + true + + + double + -0.01 + true + true + false + true + + + double + 0.01 + false + true + true + true + + + double + 0.01 + true + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.02 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + java.lang.String + Full + false + true + true + true + + + double + 300.0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 7 + true + true + false + true + + + int + 6 + true + true + false + true + + + java.lang.String + HIGH + true + true + false + true + + + int + 8 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + int + 16 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + int + 32 + false + true + false + true + + + int + 13 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + global_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + soft_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + csr_soft_reset_req + Input + 1 + reset + + + + + + java.lang.String + afi_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + soft_reset,global_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + afi_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + afi_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + soft_reset,global_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + afi_reset_export_n + Output + 1 + reset_n + + + + + + java.lang.String + ctl_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + soft_reset,global_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + ctl_reset_n + Output + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + afi_clk + Input + 1 + clk + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + afi_half_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + long + 300000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + ctl_clk + Output + 1 + clk + + + false + c0 + ctl_clk + c0.ctl_clk + + + + + + java.lang.String + + false + true + true + true + + + long + 60000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + avl_clk + Output + 1 + clk + + + false + s0 + avl_clk + s0.avl_clk + + + false + dmaster + clk + dmaster.clk + + + + + + java.lang.String + avl_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + soft_reset,global_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + avl_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + long + 20000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + scc_clk + Output + 1 + clk + + + false + s0 + scc_clk + s0.scc_clk + + + + + + java.lang.String + scc_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + soft_reset,global_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + scc_reset_n + Output + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 262144 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + avl_clk + false + true + true + true + + + java.lang.String + avl_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + true + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avl_address + Input + 16 + address + + + avl_write + Input + 1 + write + + + avl_writedata + Input + 32 + writedata + + + avl_read + Input + 1 + read + + + avl_readdata + Output + 32 + readdata + + + avl_waitrequest + Output + 1 + waitrequest + + + + + + java.lang.String + + false + true + true + true + + + long + 300000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + dll_clk + Output + 1 + clk + + + false + dll0 + clk + dll0.clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + afi_addr + Input + 20 + afi_addr + + + afi_ba + Input + 3 + afi_ba + + + afi_cke + Input + 2 + afi_cke + + + afi_cs_n + Input + 2 + afi_cs_n + + + afi_ras_n + Input + 1 + afi_ras_n + + + afi_we_n + Input + 1 + afi_we_n + + + afi_cas_n + Input + 1 + afi_cas_n + + + afi_rst_n + Input + 1 + afi_rst_n + + + afi_odt + Input + 2 + afi_odt + + + afi_dqs_burst + Input + 5 + afi_dqs_burst + + + afi_wdata_valid + Input + 5 + afi_wdata_valid + + + afi_wdata + Input + 80 + afi_wdata + + + afi_dm + Input + 10 + afi_dm + + + afi_rdata + Output + 80 + afi_rdata + + + afi_rdata_en + Input + 5 + afi_rdata_en + + + afi_rdata_en_full + Input + 5 + afi_rdata_en_full + + + afi_rdata_valid + Output + 1 + afi_rdata_valid + + + afi_wlat + Output + 4 + afi_wlat + + + afi_rlat + Output + 5 + afi_rlat + + + afi_cal_success + Output + 1 + afi_cal_success + + + afi_cal_fail + Output + 1 + afi_cal_fail + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + scc_data + Input + 1 + scc_data + + + scc_dqs_ena + Input + 2 + scc_dqs_ena + + + scc_dqs_io_ena + Input + 2 + scc_dqs_io_ena + + + scc_dq_ena + Input + 16 + scc_dq_ena + + + scc_dm_ena + Input + 2 + scc_dm_ena + + + capture_strobe_tracking + Output + 2 + capture_strobe_tracking + + + scc_upd + Input + 1 + scc_upd + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + cfg_addlat + Input + 8 + cfg_addlat + + + cfg_bankaddrwidth + Input + 8 + cfg_bankaddrwidth + + + cfg_caswrlat + Input + 8 + cfg_caswrlat + + + cfg_coladdrwidth + Input + 8 + cfg_coladdrwidth + + + cfg_csaddrwidth + Input + 8 + cfg_csaddrwidth + + + cfg_devicewidth + Input + 8 + cfg_devicewidth + + + cfg_dramconfig + Input + 24 + cfg_dramconfig + + + cfg_interfacewidth + Input + 8 + cfg_interfacewidth + + + cfg_rowaddrwidth + Input + 8 + cfg_rowaddrwidth + + + cfg_tcl + Input + 8 + cfg_tcl + + + cfg_tmrd + Input + 8 + cfg_tmrd + + + cfg_trefi + Input + 16 + cfg_trefi + + + cfg_trfc + Input + 8 + cfg_trfc + + + cfg_twr + Input + 8 + cfg_twr + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + afi_mem_clk_disable + Input + 1 + afi_mem_clk_disable + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + pll_mem_clk + Input + 1 + pll_mem_clk + + + pll_write_clk + Input + 1 + pll_write_clk + + + pll_locked + Input + 1 + pll_locked + + + pll_write_clk_pre_phy_clk + Input + 1 + pll_write_clk_pre_phy_clk + + + pll_addr_cmd_clk + Input + 1 + pll_addr_cmd_clk + + + pll_avl_clk + Input + 1 + pll_avl_clk + + + pll_config_clk + Input + 1 + pll_config_clk + + + pll_mem_phy_clk + Input + 1 + pll_mem_phy_clk + + + afi_phy_clk + Input + 1 + afi_phy_clk + + + pll_avl_phy_clk + Input + 1 + pll_avl_phy_clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + dll_pll_locked + Output + 1 + dll_pll_locked + + + dll_delayctrl + Input + 7 + dll_delayctrl + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + seriesterminationcontrol + Input + 16 + seriesterminationcontrol + + + parallelterminationcontrol + Input + 16 + parallelterminationcontrol + + + + + + qsys.ui.export_name + memory + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + mem_a + Output + 13 + mem_a + + + mem_ba + Output + 3 + mem_ba + + + mem_ck + Output + 1 + mem_ck + + + mem_ck_n + Output + 1 + mem_ck_n + + + mem_cke + Output + 1 + mem_cke + + + mem_cs_n + Output + 1 + mem_cs_n + + + mem_dm + Output + 2 + mem_dm + + + mem_ras_n + Output + 1 + mem_ras_n + + + mem_cas_n + Output + 1 + mem_cas_n + + + mem_we_n + Output + 1 + mem_we_n + + + mem_reset_n + Output + 1 + mem_reset_n + + + mem_dq + Bidir + 16 + mem_dq + + + mem_dqs + Bidir + 2 + mem_dqs + + + mem_dqs_n + Bidir + 2 + mem_dqs_n + + + mem_odt + Output + 1 + mem_odt + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + csr_clk + Input + 1 + clk + + + + + + java.lang.String + csr_clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + csr_reset_n + Input + 1 + reset_n + + + + + + debug.visible + true + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + csr_clk + false + true + true + true + + + java.lang.String + csr_reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_write_req + Input + 1 + write + + + csr_read_req + Input + 1 + read + + + csr_waitrequest + Output + 1 + waitrequest + + + csr_addr + Input + 8 + address + + + csr_be + Input + 4 + byteenable + + + csr_wdata + Input + 32 + writedata + + + csr_rdata + Output + 32 + readdata + + + csr_rdata_valid + Output + 1 + readdatavalid + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + io_intaficalfail + Output + 1 + io_intaficalfail + + + io_intaficalsuccess + Output + 1 + io_intaficalsuccess + + + + + + + java.lang.String + 0001000110001 + true + true + false + true + + + java.lang.String + 0001001001001 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0001100110000 + true + true + false + true + + + java.lang.String + 0001011001000 + true + true + false + true + + + java.lang.String + 0000001000000 + true + true + false + true + + + java.lang.String + 0000000100000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0000000001000 + true + true + false + true + + + java.lang.String + 0000000010000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 8 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 1.5 + true + true + false + true + + + double + 1500.0 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 11 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 100000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 6 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Micron + false + true + true + true + + + java.lang.String + DISCRETE + false + false + true + true + + + boolean + false + true + false + true + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + 0x0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + double + 666.667 + false + true + true + true + + + int + 13 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 3 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + OTF + false + true + false + true + + + java.lang.String + Sequential + false + true + true + true + + + java.lang.String + Manual + false + true + true + true + + + java.lang.String + Normal + false + true + true + true + + + java.lang.String + DLL off + false + true + true + true + + + java.lang.String + RZQ/6 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + RZQ/2 + false + true + true + true + + + java.lang.String + Dynamic ODT off + false + true + true + true + + + int + 6 + false + true + true + true + + + java.lang.String + Disabled + false + true + true + true + + + int + 7 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + Leveling + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + false + false + true + + + int + 32 + false + false + false + true + + + int + 190 + false + true + true + true + + + int + 140 + false + true + true + true + + + int + 30 + false + true + true + true + + + int + 65 + false + true + true + true + + + int + 125 + false + true + true + true + + + double + 0.38 + false + true + true + true + + + int + 255 + false + true + true + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + double + 0.25 + false + true + true + true + + + double + 0.4 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + int + 500 + false + true + true + true + + + int + 150000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + false + true + true + true + + + double + 36.0 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 7.8 + false + true + true + true + + + double + 110.0 + false + true + true + true + + + double + 2.5 + false + true + false + true + + + double + 15.0 + false + true + true + true + + + int + 5 + false + true + true + true + + + double + 45.0 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + java.lang.String + Full + false + true + true + true + + + double + 300.0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + afi_addr + Input + 20 + afi_addr + + + afi_ba + Input + 3 + afi_ba + + + afi_cke + Input + 2 + afi_cke + + + afi_cs_n + Input + 2 + afi_cs_n + + + afi_ras_n + Input + 1 + afi_ras_n + + + afi_we_n + Input + 1 + afi_we_n + + + afi_cas_n + Input + 1 + afi_cas_n + + + afi_rst_n + Input + 1 + afi_rst_n + + + afi_odt + Input + 2 + afi_odt + + + afi_mem_clk_disable + Input + 1 + afi_mem_clk_disable + + + afi_init_req + Input + 1 + afi_init_req + + + afi_cal_req + Input + 1 + afi_cal_req + + + afi_dqs_burst + Input + 5 + afi_dqs_burst + + + afi_wdata_valid + Input + 5 + afi_wdata_valid + + + afi_wdata + Input + 80 + afi_wdata + + + afi_dm + Input + 10 + afi_dm + + + afi_rdata + Output + 80 + afi_rdata + + + afi_rdata_en + Input + 5 + afi_rdata_en + + + afi_rdata_en_full + Input + 5 + afi_rdata_en_full + + + afi_rdata_valid + Output + 1 + afi_rdata_valid + + + afi_wlat + Output + 4 + afi_wlat + + + afi_rlat + Output + 5 + afi_rlat + + + afi_cal_success + Output + 1 + afi_cal_success + + + afi_cal_fail + Output + 1 + afi_cal_fail + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + mux_afi_addr + Output + 20 + afi_addr + + + mux_afi_ba + Output + 3 + afi_ba + + + mux_afi_cke + Output + 2 + afi_cke + + + mux_afi_cs_n + Output + 2 + afi_cs_n + + + mux_afi_ras_n + Output + 1 + afi_ras_n + + + mux_afi_we_n + Output + 1 + afi_we_n + + + mux_afi_cas_n + Output + 1 + afi_cas_n + + + mux_afi_rst_n + Output + 1 + afi_rst_n + + + mux_afi_odt + Output + 2 + afi_odt + + + mux_afi_dqs_burst + Output + 5 + afi_dqs_burst + + + mux_afi_wdata_valid + Output + 5 + afi_wdata_valid + + + mux_afi_wdata + Output + 80 + afi_wdata + + + mux_afi_dm + Output + 10 + afi_dm + + + mux_afi_rdata + Input + 80 + afi_rdata + + + mux_afi_rdata_en + Output + 5 + afi_rdata_en + + + mux_afi_rdata_en_full + Output + 5 + afi_rdata_en_full + + + mux_afi_rdata_valid + Input + 1 + afi_rdata_valid + + + mux_afi_wlat + Input + 4 + afi_wlat + + + mux_afi_rlat + Input + 5 + afi_rlat + + + mux_afi_cal_success + Input + 1 + afi_cal_success + + + mux_afi_cal_fail + Input + 1 + afi_cal_fail + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + phy_afi_mem_clk_disable + Output + 1 + afi_mem_clk_disable + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + seq_afi_init_req + Output + 1 + afi_init_req + + + seq_afi_cal_req + Output + 1 + afi_cal_req + + + + + + + java.lang.String + 0001000110001 + true + true + false + true + + + java.lang.String + 0001001001001 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0001100110000 + true + true + false + true + + + java.lang.String + 0001011001000 + true + true + false + true + + + java.lang.String + 0000001000000 + true + true + false + true + + + java.lang.String + 0000000100000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0000000001000 + true + true + false + true + + + java.lang.String + 0000000010000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 8 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 1.5 + true + true + false + true + + + double + 1500.0 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 11 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 100000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 6 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Micron + false + true + true + true + + + java.lang.String + DISCRETE + false + false + true + true + + + boolean + false + true + false + true + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + 0x0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + double + 666.667 + false + true + true + true + + + int + 13 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 3 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + OTF + false + true + false + true + + + java.lang.String + Sequential + false + true + true + true + + + java.lang.String + Manual + false + true + true + true + + + java.lang.String + Normal + false + true + true + true + + + java.lang.String + DLL off + false + true + true + true + + + java.lang.String + RZQ/6 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + RZQ/2 + false + true + true + true + + + java.lang.String + Dynamic ODT off + false + true + true + true + + + int + 6 + false + true + true + true + + + java.lang.String + Disabled + false + true + true + true + + + int + 7 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + Leveling + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + false + false + true + + + int + 32 + false + false + false + true + + + int + 190 + false + true + true + true + + + int + 140 + false + true + true + true + + + int + 30 + false + true + true + true + + + int + 65 + false + true + true + true + + + int + 125 + false + true + true + true + + + double + 0.38 + false + true + true + true + + + int + 255 + false + true + true + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + double + 0.25 + false + true + true + true + + + double + 0.4 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + int + 500 + false + true + true + true + + + int + 150000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + false + true + true + true + + + double + 36.0 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 7.8 + false + true + true + true + + + double + 110.0 + false + true + true + true + + + double + 2.5 + false + true + false + true + + + double + 15.0 + false + true + true + true + + + int + 5 + false + true + true + true + + + double + 45.0 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 151 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + FULL + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 2 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 50.0 + false + true + true + true + + + java.lang.String + 50.0 MHz + true + true + false + true + + + double + 20.0 + true + true + false + true + + + double + 20000.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 150.0 MHz + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 60.0 MHz + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 416 ps + true + true + false + true + + + double + 9.0 + true + true + false + true + + + int + 463 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + double + 10.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 20.0 MHz + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + double + 10.0 + false + true + false + true + + + double + 500.0 + false + true + false + true + + + double + 10.0 + true + true + false + true + + + double + 500.0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 2500 + false + true + false + true + + + java.lang.String + 2500 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 2500 + false + true + false + true + + + java.lang.String + 2500 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + double + 150.0 + false + true + false + true + + + java.lang.String + 6668 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 2000000 + false + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 2000000 + true + true + false + true + + + double + 60.0 + false + true + false + true + + + java.lang.String + 16670 ps + false + true + false + true + + + int + 416 + false + true + false + true + + + java.lang.String + 463 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 5000000 + false + true + false + true + + + double + 60.0 + true + true + false + true + + + java.lang.String + 16670 ps + true + true + false + true + + + int + 416 + true + true + false + true + + + java.lang.String + 463 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 5000000 + true + true + false + true + + + double + 20.0 + false + true + false + true + + + java.lang.String + 50010 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 15000000 + false + true + false + true + + + double + 20.0 + true + true + false + true + + + java.lang.String + 50010 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 15000000 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + false + true + false + true + + + java.lang.String + 3334 ps + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + 0 ps + false + true + false + true + + + int + 6000000 + false + true + false + true + + + int + 1000000 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 6000000 + true + true + false + true + + + int + 1000000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + Unknown + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Unknown + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + Unknown + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + 0_0000_0000_0000 + false + true + false + true + + + java.lang.String + 0_0000_0000_1000 + false + true + false + true + + + int + 35100 + false + true + false + true + + + int + 15000 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 350 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 4 + true + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + MISSING_MODEL + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 7 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 3.333 + true + true + false + true + + + double + 3333.0 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 416 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 31 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + SSTL-15 + true + true + true + true + + + boolean + true + true + true + false + true + + + java.lang.String + NIOS + false + true + false + true + + + java.lang.String + ../ + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 7 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + false + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + 1.5V DDR3 + false + true + true + true + + + boolean + false + false + false + false + true + + + java.lang.String + Top_Bottom + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + INVERTED_DQS_BUS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DIFFERENTIAL + false + true + false + true + + + int + 32 + false + true + false + true + + + java.lang.String + Quick + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 13 + true + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + java.lang.String + INTERNAL_JTAG + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.34 + true + true + true + true + + + double + 0.24 + true + true + true + true + + + double + 0.18 + true + true + true + true + + + double + 0.165 + true + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.6 + false + true + true + true + + + double + 0.6 + false + true + true + true + + + double + -0.01 + false + true + true + true + + + double + -0.01 + true + true + false + true + + + double + 0.01 + false + true + true + true + + + double + 0.01 + true + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.02 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + double + 0.02 + false + true + true + true + + + double + 0.0 + false + true + true + true + + + java.lang.String + Full + false + true + true + true + + + double + 300.0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 7 + true + true + false + true + + + int + 6 + true + true + false + true + + + java.lang.String + HIGH + true + true + false + true + + + int + 8 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + int + 16 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + boolean + false + false + true + true + true + + + java.lang.String + EXPORT + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 6 + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 32 + false + true + true + true + + + int + 13 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + avl_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + avl_reset_n + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + scc_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n_scc_clk + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + scc_data + Output + 1 + scc_data + + + scc_dqs_ena + Output + 2 + scc_dqs_ena + + + scc_dqs_io_ena + Output + 2 + scc_dqs_io_ena + + + scc_dq_ena + Output + 16 + scc_dq_ena + + + scc_dm_ena + Output + 2 + scc_dm_ena + + + capture_strobe_tracking + Input + 2 + capture_strobe_tracking + + + scc_upd + Output + 1 + scc_upd + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + afi_init_req + Input + 1 + afi_init_req + + + afi_cal_req + Input + 1 + afi_cal_req + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + avl_clk + false + true + true + true + + + java.lang.String + avl_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + avl_address + Output + 16 + address + + + avl_write + Output + 1 + write + + + avl_writedata + Output + 32 + writedata + + + avl_read + Output + 1 + read + + + avl_readdata + Input + 32 + readdata + + + avl_waitrequest + Input + 1 + waitrequest + + + false + p0 + avl + p0.avl + 0 + 262144 + + + + + + debug.visible + true + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4294967296 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + avl_clk + false + true + true + true + + + java.lang.String + avl_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + seq_waitrequest + Output + 1 + waitrequest + + + seq_readdata + Output + 32 + readdata + + + seq_readdatavalid + Output + 1 + readdatavalid + + + seq_burstcount + Input + 1 + burstcount + + + seq_writedata + Input + 32 + writedata + + + seq_address + Input + 32 + address + + + seq_write + Input + 1 + write + + + seq_read + Input + 1 + read + + + seq_byteenable + Input + 4 + byteenable + + + + + + + debug.hostConnection + type jtag id 110:132 + + + int + 0 + false + true + true + true + + + int + 50000 + false + false + true + true + + + int + 0 + false + true + false + true + CLOCK_RATE + clock + + + int + 0 + false + true + true + true + + + int + 2 + false + false + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 5CEBA2F17A7 + false + true + false + true + DEVICE + + + java.lang.String + 7 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Cyclone V + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + clk_reset_reset + Input + 1 + reset + + + + + + debug.controlledBy + in_stream + + + debug.providesServices + master + + + debug.typeName + altera_jtag_avalon_master.master + + + debug.visible + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + master_address + Output + 32 + address + + + master_readdata + Input + 32 + readdata + + + master_read + Output + 1 + read + + + master_write + Output + 1 + write + + + master_writedata + Output + 32 + writedata + + + master_waitrequest + Input + 1 + waitrequest + + + master_readdatavalid + Input + 1 + readdatavalid + + + master_byteenable + Output + 4 + byteenable + + + false + s0 + seq_debug + s0.seq_debug + 0 + 4294967296 + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + master_reset_reset + Output + 1 + reset + + + + + + + int + 48 + true + true + true + true + + + java.lang.String + 0001000110001 + true + true + false + true + + + java.lang.String + 0001001001001 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0001100110000 + true + true + false + true + + + java.lang.String + 0001011001000 + true + true + false + true + + + java.lang.String + 0000001000000 + true + true + false + true + + + java.lang.String + 0000000100000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0000000001000 + true + true + false + true + + + java.lang.String + 0000000010000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + java.lang.String + 0000000000000 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 8 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 1.5 + true + true + false + true + + + double + 1500.0 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 11 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 100000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 6 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + Micron + false + true + true + true + + + java.lang.String + DISCRETE + false + false + true + true + + + boolean + false + true + false + true + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + 0x0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + double + 666.667 + false + true + true + true + + + int + 13 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 3 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + OTF + false + true + false + true + + + java.lang.String + Sequential + false + true + true + true + + + java.lang.String + Manual + false + true + true + true + + + java.lang.String + Normal + false + true + true + true + + + java.lang.String + DLL off + false + true + true + true + + + java.lang.String + RZQ/6 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + RZQ/2 + false + true + true + true + + + java.lang.String + Dynamic ODT off + false + true + true + true + + + int + 6 + false + true + true + true + + + java.lang.String + Disabled + false + true + true + true + + + int + 7 + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + Leveling + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + false + false + true + + + int + 32 + false + false + false + true + + + int + 190 + false + true + true + true + + + int + 140 + false + true + true + true + + + int + 30 + false + true + true + true + + + int + 65 + false + true + true + true + + + int + 125 + false + true + true + true + + + double + 0.38 + false + true + true + true + + + int + 255 + false + true + true + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + double + 0.25 + false + true + true + true + + + double + 0.4 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + int + 500 + false + true + true + true + + + int + 150000 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + false + true + true + true + + + double + 36.0 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 13.5 + false + true + true + true + + + double + 7.8 + false + true + true + true + + + double + 110.0 + false + true + true + true + + + double + 2.5 + false + true + false + true + + + double + 15.0 + false + true + true + true + + + int + 5 + false + true + true + true + + + double + 45.0 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + double + 7.5 + false + true + true + true + + + boolean + false + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 25 + true + false + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + false + false + true + + + int + 8 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 3 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + nextgen_v110 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 512 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 10 + true + true + false + true + + + int + 0 + true + true + false + true + + + [Ljava.lang.String; + Port 0 + true + true + true + true + + + int + 32 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + [Ljava.lang.String; + F0,None,None,None,None,None + true + false + true + true + + + [Ljava.lang.String; + F0,None,None,None,None,None + true + false + true + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + BL_8 + true + true + false + true + + + java.lang.String + DWIDTH_16 + true + true + false + true + + + java.lang.String + SELF_RFSH_EXIT_CYCLES_512 + true + true + false + true + + + java.lang.String + STARVE_LIMIT_4 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + NO_CLR_INTR + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + BI_DIRECTION + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + CHIP_ROW_BANK_COL + true + true + false + true + + + java.lang.String + CTL_ECC_DISABLED + true + true + false + true + + + java.lang.String + CTL_ECC_RMW_DISABLED + true + true + false + true + + + java.lang.String + REGDIMM_DISABLED + true + true + false + true + + + java.lang.String + CTL_USR_REFRESH_DISABLED + true + true + false + true + + + java.lang.String + DATA_WIDTH_32_BIT + true + true + false + true + + + java.lang.String + BONDING_LATENCY_0 + true + true + false + true + + + java.lang.String + DFX_BYPASS_DISABLED + true + true + false + true + + + java.lang.String + MERGING_ENABLED + true + true + false + true + + + java.lang.String + ECC_DQ_WIDTH_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + GEN_DBE_DISABLED + true + true + false + true + + + java.lang.String + GEN_SBE_DISABLED + true + true + false + true + + + java.lang.String + FIFO_SET_2 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + AL_0 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_3 + true + true + false + true + + + java.lang.String + MEM_IF_BURSTLENGTH_8 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_10 + true + true + false + true + + + java.lang.String + MEM_IF_CS_PER_RANK_1 + true + true + false + true + + + java.lang.String + MEM_IF_CS_WIDTH_1 + true + true + false + true + + + java.lang.String + MEM_IF_DQ_PER_CHIP_8 + true + true + false + true + + + java.lang.String + DQS_WIDTH_2 + true + true + false + true + + + java.lang.String + MEM_IF_DWIDTH_16 + true + true + false + true + + + java.lang.String + DDR3_SDRAM + true + true + false + true + + + java.lang.String + ADDR_WIDTH_13 + true + true + false + true + + + java.lang.String + DDR3_1600_8_8_8 + true + true + false + true + + + java.lang.String + TCCD_4 + true + true + false + true + + + java.lang.String + TCL_7 + true + true + false + true + + + java.lang.String + TCWL_6 + true + true + false + true + + + java.lang.String + TFAW_14 + true + true + false + true + + + java.lang.String + TMRD_4 + true + true + false + true + + + java.lang.String + TRAS_11 + true + true + false + true + + + java.lang.String + TRC_15 + true + true + false + true + + + java.lang.String + TRCD_5 + true + true + false + true + + + java.lang.String + TRP_5 + true + true + false + true + + + java.lang.String + TRRD_3 + true + true + false + true + + + java.lang.String + TRTP_3 + true + true + false + true + + + java.lang.String + TWR_5 + true + true + false + true + + + java.lang.String + TWTR_5 + true + true + false + true + + + java.lang.String + MP_BL_8 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + SLOW_EXIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + ODT_DISABLED + true + true + false + true + + + java.lang.String + NO_DATA_REORDERING + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + NORMAL_MODE + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WRITE_CHIP0_ODT0_CHIP1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2341 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 10 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + TRUE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + BI_DIRECTION + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + USE_0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_32_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_1 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 4 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + false + true + true + + + java.lang.String + 5 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 10 + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + INTERNAL_JTAG + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + false + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 4 + false + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 8 + true + true + false + true + + + int + 6 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + INTER_BANK + false + false + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + [Ljava.lang.Integer; + 32,32,32,32,32,32 + false + true + true + true + + + [Ljava.lang.Integer; + 1,1,1,1,1,1 + false + true + true + true + + + [Ljava.lang.Integer; + 0,0,0,0,0,0 + false + true + true + true + + + [Ljava.lang.String; + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + false + true + true + true + + + java.lang.String + Full + false + true + true + true + + + double + 300.0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + AUTO + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + afi_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + afi_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + ctl_reset_n + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + afi_half_clk + Input + 1 + clk + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + ctl_clk + Input + 1 + clk + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + mp_cmd_clk_0 + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + mp_cmd_reset_n_0 + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + mp_rfifo_clk_0 + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + mp_rfifo_reset_n_0 + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + mp_wfifo_clk_0 + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + mp_wfifo_reset_n_0 + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + csr_clk + Input + 1 + clk + + + + + + java.lang.String + csr_clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + csr_reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 134217728 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + mp_cmd_clk_0 + false + true + true + true + + + java.lang.String + mp_cmd_reset_n_0 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 48 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avl_ready_0 + Output + 1 + waitrequest_n + + + avl_burstbegin_0 + Input + 1 + beginbursttransfer + + + avl_addr_0 + Input + 25 + address + + + avl_rdata_valid_0 + Output + 1 + readdatavalid + + + avl_rdata_0 + Output + 32 + readdata + + + avl_wdata_0 + Input + 32 + writedata + + + avl_be_0 + Input + 4 + byteenable + + + avl_read_req_0 + Input + 1 + read + + + avl_write_req_0 + Input + 1 + write + + + avl_size_0 + Input + 3 + burstcount + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + local_init_done + Output + 1 + local_init_done + + + local_cal_success + Output + 1 + local_cal_success + + + local_cal_fail + Output + 1 + local_cal_fail + + + + + + debug.visible + true + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + csr_clk + false + true + true + true + + + java.lang.String + csr_reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_write_req + Input + 1 + write + + + csr_read_req + Input + 1 + read + + + csr_waitrequest + Output + 1 + waitrequest + + + csr_addr + Input + 10 + address + + + csr_be + Input + 1 + byteenable + + + csr_wdata + Input + 8 + writedata + + + csr_rdata + Output + 8 + readdata + + + csr_rdata_valid + Output + 1 + readdatavalid + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + afi_addr + Output + 20 + afi_addr + + + afi_ba + Output + 3 + afi_ba + + + afi_cke + Output + 2 + afi_cke + + + afi_cs_n + Output + 2 + afi_cs_n + + + afi_ras_n + Output + 1 + afi_ras_n + + + afi_we_n + Output + 1 + afi_we_n + + + afi_cas_n + Output + 1 + afi_cas_n + + + afi_rst_n + Output + 1 + afi_rst_n + + + afi_odt + Output + 2 + afi_odt + + + afi_mem_clk_disable + Output + 1 + afi_mem_clk_disable + + + afi_init_req + Output + 1 + afi_init_req + + + afi_cal_req + Output + 1 + afi_cal_req + + + afi_dqs_burst + Output + 5 + afi_dqs_burst + + + afi_wdata_valid + Output + 5 + afi_wdata_valid + + + afi_wdata + Output + 80 + afi_wdata + + + afi_dm + Output + 10 + afi_dm + + + afi_rdata + Input + 80 + afi_rdata + + + afi_rdata_en + Output + 5 + afi_rdata_en + + + afi_rdata_en_full + Output + 5 + afi_rdata_en_full + + + afi_rdata_valid + Input + 1 + afi_rdata_valid + + + afi_wlat + Input + 4 + afi_wlat + + + afi_rlat + Input + 5 + afi_rlat + + + afi_cal_success + Input + 1 + afi_cal_success + + + afi_cal_fail + Input + 1 + afi_cal_fail + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + cfg_addlat + Output + 8 + cfg_addlat + + + cfg_bankaddrwidth + Output + 8 + cfg_bankaddrwidth + + + cfg_caswrlat + Output + 8 + cfg_caswrlat + + + cfg_coladdrwidth + Output + 8 + cfg_coladdrwidth + + + cfg_csaddrwidth + Output + 8 + cfg_csaddrwidth + + + cfg_devicewidth + Output + 8 + cfg_devicewidth + + + cfg_dramconfig + Output + 24 + cfg_dramconfig + + + cfg_interfacewidth + Output + 8 + cfg_interfacewidth + + + cfg_rowaddrwidth + Output + 8 + cfg_rowaddrwidth + + + cfg_tcl + Output + 8 + cfg_tcl + + + cfg_tmrd + Output + 8 + cfg_tmrd + + + cfg_trefi + Output + 16 + cfg_trefi + + + cfg_trfc + Output + 8 + cfg_trfc + + + cfg_twr + Output + 8 + cfg_twr + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + io_intaficalfail + Input + 1 + io_intaficalfail + + + io_intaficalsuccess + Input + 1 + io_intaficalsuccess + + + + + + + long + 0 + false + true + true + true + CLOCK_RATE + in_clk + + + long + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk + Output + 1 + clk + + + false + c0 + mp_cmd_clk_0 + c0.mp_cmd_clk_0 + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + in_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_n + Output + 1 + reset_n + + + + + + + long + 0 + false + true + true + true + CLOCK_RATE + in_clk + + + long + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk + Output + 1 + clk + + + false + c0 + csr_clk + c0.csr_clk + + + false + p0 + csr_clk + p0.csr_clk + + + false + if_csr_m0 + clk + if_csr_m0.clk + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + in_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_n + Output + 1 + reset_n + + + + + + + int + 16 + true + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + oct + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + oct_rzqin + Input + 1 + rzqin + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + seriesterminationcontrol + Output + 16 + seriesterminationcontrol + + + parallelterminationcontrol + Output + 16 + parallelterminationcontrol + + + + + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + NIOS + false + true + true + true + + + java.lang.String + Full + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + pll_mem_clk_in + Input + 1 + pll_mem_clk + + + pll_write_clk_in + Input + 1 + pll_write_clk + + + pll_locked_in + Input + 1 + pll_locked + + + pll_write_clk_pre_phy_clk_in + Input + 1 + pll_write_clk_pre_phy_clk + + + pll_addr_cmd_clk_in + Input + 1 + pll_addr_cmd_clk + + + pll_avl_clk_in + Input + 1 + pll_avl_clk + + + pll_config_clk_in + Input + 1 + pll_config_clk + + + pll_mem_phy_clk_in + Input + 1 + pll_mem_phy_clk + + + afi_phy_clk_in + Input + 1 + afi_phy_clk + + + pll_avl_phy_clk_in + Input + 1 + pll_avl_phy_clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + pll_mem_clk + Output + 1 + pll_mem_clk + + + pll_write_clk + Output + 1 + pll_write_clk + + + pll_locked + Output + 1 + pll_locked + + + pll_write_clk_pre_phy_clk + Output + 1 + pll_write_clk_pre_phy_clk + + + pll_addr_cmd_clk + Output + 1 + pll_addr_cmd_clk + + + pll_avl_clk + Output + 1 + pll_avl_clk + + + pll_config_clk + Output + 1 + pll_config_clk + + + pll_mem_phy_clk + Output + 1 + pll_mem_phy_clk + + + afi_phy_clk + Output + 1 + afi_phy_clk + + + pll_avl_phy_clk + Output + 1 + pll_avl_phy_clk + + + + + + + int + 7 + false + true + false + true + + + int + 6 + false + true + false + true + + + java.lang.String + HIGH + false + true + false + true + + + int + 8 + false + true + false + true + + + java.lang.String + None + false + true + true + true + + + int + 1 + false + false + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEV + true + true + false + true + + + java.lang.String + Cyclone V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + java.lang.String + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DEFAULT + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 300.0 + false + true + true + true + + + boolean + false + false + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + 3333 ps + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + dll_pll_locked + Input + 1 + dll_pll_locked + + + dll_delayctrl + Output + 7 + dll_delayctrl + + + + + + + debug.hostConnection + type jtag id 110:132 + + + int + 0 + false + true + true + true + + + int + 50000 + false + false + true + true + + + int + 0 + false + true + false + true + CLOCK_RATE + clock + + + int + 0 + false + true + true + true + + + int + 2 + false + false + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 5CEBA2F17A7 + false + true + false + true + DEVICE + + + java.lang.String + 7 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Cyclone V + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + clk_reset_reset + Input + 1 + reset + + + + + + debug.controlledBy + in_stream + + + debug.providesServices + master + + + debug.typeName + altera_jtag_avalon_master.master + + + debug.visible + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + master_address + Output + 32 + address + + + master_readdata + Input + 32 + readdata + + + master_read + Output + 1 + read + + + master_write + Output + 1 + write + + + master_writedata + Output + 32 + writedata + + + master_waitrequest + Input + 1 + waitrequest + + + master_readdatavalid + Input + 1 + readdatavalid + + + master_byteenable + Output + 4 + byteenable + + + false + p0 + csr + p0.csr + 0 + 1024 + + + false + c0 + csr + c0.csr + 1024 + 1024 + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + master_reset_reset + Output + 1 + reset + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll_ref_clk + out_clk + pll0 + pll_ref_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + global_reset + out_reset + pll0 + global_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll0 + afi_clk + afi_clk + in_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll0 + afi_half_clk + afi_half_clk + in_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + soft_reset + out_reset + p0 + soft_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + global_reset + out_reset + p0 + global_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll0 + afi_clk + p0 + afi_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll0 + afi_half_clk + p0 + afi_half_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + afi_reset_export + afi_reset_export + in_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + afi_reset + afi_reset + in_reset + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + as0 + mux_afi + p0 + afi + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + as0 + afi_mem_clk_disable + p0 + afi_mem_clk_disable + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + avl_clk + s0 + avl_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + avl_reset + s0 + avl_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + scc_clk + s0 + scc_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + scc_reset + s0 + scc_reset + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + s0 + scc + p0 + scc + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + s0 + afi_init_cal_req + as0 + afi_init_cal_req + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + s0 + avl + p0 + avl + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + avl_clk + dmaster + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + avl_reset + dmaster + clk_reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + dmaster + master + s0 + seq_debug + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + dmaster + master_reset + p0 + csr_soft_reset_req + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll0 + afi_clk + c0 + afi_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll0 + afi_half_clk + c0 + afi_half_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + afi_reset + c0 + afi_reset + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + c0 + afi + as0 + afi + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + c0 + hard_phy_cfg + p0 + hard_phy_cfg + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + mp_cmd_clk_0 + out_clk + c0 + mp_cmd_clk_0 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + mp_cmd_reset_n_0 + out_reset + c0 + mp_cmd_reset_n_0 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + csr_clk + out_clk + c0 + csr_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + csr_clk + out_clk + p0 + csr_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + csr_reset_n + out_reset + c0 + csr_reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + csr_reset_n + out_reset + p0 + csr_reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + ctl_clk + c0 + ctl_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + ctl_reset + c0 + ctl_reset + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + io_int + c0 + io_int + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + oct0 + oct_sharing + p0 + oct_sharing + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll0 + pll_sharing + pll_bridge + pll_sharing_in + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pll_bridge + pll_sharing + p0 + pll_sharing + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + p0 + dll_clk + dll0 + clk + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + dll0 + dll_sharing + p0 + dll_sharing + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + csr_clk + out_clk + if_csr_m0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + csr_reset_n + out_reset + if_csr_m0 + clk_reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + if_csr_m0 + master + p0 + csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0400 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + if_csr_m0 + master + c0 + csr + + + 5 + altera_clock_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Bridge + 15.1 + + + 21 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 15.1 + + + 12 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 15.1 + + + 6 + altera_reset_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Reset Bridge + 15.1 + + + 21 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 15.1 + + + 15 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 15.1 + + + 1 + altera_mem_if_ddr3_pll + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + DDR3 SDRAM External Memory PLL/DLL/OCT block + 15.1 + + + 25 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 15.1 + + + 1 + altera_mem_if_ddr3_hard_phy_core + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + DDR3 SDRAM External Memory Hard PHY Core + 15.1 + + + 5 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 15.1 + + + 1 + altera_mem_if_ddr3_afi_splitter + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UniPHY DDR3 AFI Splitter + 15.1 + + + 1 + altera_mem_if_ddr3_qseq + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + DDR3 SDRAM Qsys Sequencer + 15.1 + + + 3 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 15.1 + + + 2 + altera_jtag_avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG to Avalon Master Bridge + 15.1 + + + 1 + altera_mem_if_ddr3_hard_memory_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Altera DDR3 Hard Memory Controller + 15.1 + + + 1 + altera_mem_if_oct + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + External Memory OCT block + 15.1 + + + 1 + altera_mem_if_pll_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + External Memory PLL block bridge + 15.1 + + + 1 + altera_mem_if_dll + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + External Memory DLL block + 15.1 + + + 16 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 15.1 + + + 15 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 15.1 + + + 11 + conduit + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Conduit Connection + 15.1 + + + 4 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 15.1 + + 15.1 185 + + diff --git a/ip/altera/ddr3.spd b/ip/altera/ddr3.spd new file mode 100644 index 0000000..18dbe10 --- /dev/null +++ b/ip/altera/ddr3.spd @@ -0,0 +1,13 @@ + + + + + + + + + + diff --git a/ip/altera/ddr3.vhd b/ip/altera/ddr3.vhd new file mode 100644 index 0000000..dd4cba7 --- /dev/null +++ b/ip/altera/ddr3.vhd @@ -0,0 +1,536 @@ +-- megafunction wizard: %DDR3 SDRAM Controller with UniPHY v15.1% +-- GENERATION: XML +-- ddr3.vhd + +-- Generated using ACDS version 15.1 185 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ddr3 is + port ( + pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk + global_reset_n : in std_logic := '0'; -- global_reset.reset_n + soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n + afi_clk : out std_logic; -- afi_clk.clk + afi_half_clk : out std_logic; -- afi_half_clk.clk + afi_reset_n : out std_logic; -- afi_reset.reset_n + afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n + mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a + mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n + mem_reset_n : out std_logic; -- .mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt + avl_ready_0 : out std_logic; -- avl_0.waitrequest_n + avl_burstbegin_0 : in std_logic := '0'; -- .beginbursttransfer + avl_addr_0 : in std_logic_vector(24 downto 0) := (others => '0'); -- .address + avl_rdata_valid_0 : out std_logic; -- .readdatavalid + avl_rdata_0 : out std_logic_vector(31 downto 0); -- .readdata + avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + avl_be_0 : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable + avl_read_req_0 : in std_logic := '0'; -- .read + avl_write_req_0 : in std_logic := '0'; -- .write + avl_size_0 : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount + mp_cmd_clk_0_clk : in std_logic := '0'; -- mp_cmd_clk_0.clk + mp_cmd_reset_n_0_reset_n : in std_logic := '0'; -- mp_cmd_reset_n_0.reset_n + mp_rfifo_clk_0_clk : in std_logic := '0'; -- mp_rfifo_clk_0.clk + mp_rfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_rfifo_reset_n_0.reset_n + mp_wfifo_clk_0_clk : in std_logic := '0'; -- mp_wfifo_clk_0.clk + mp_wfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_wfifo_reset_n_0.reset_n + csr_clk : in std_logic := '0'; -- csr_clk.clk + csr_reset_n : in std_logic := '0'; -- csr_reset_n.reset_n + local_init_done : out std_logic; -- status.local_init_done + local_cal_success : out std_logic; -- .local_cal_success + local_cal_fail : out std_logic; -- .local_cal_fail + oct_rzqin : in std_logic := '0'; -- oct.rzqin + pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk + pll_write_clk : out std_logic; -- .pll_write_clk + pll_locked : out std_logic; -- .pll_locked + pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk + pll_avl_clk : out std_logic; -- .pll_avl_clk + pll_config_clk : out std_logic; -- .pll_config_clk + pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk + afi_phy_clk : out std_logic; -- .afi_phy_clk + pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk + ); +end entity ddr3; + +architecture rtl of ddr3 is + component ddr3_0002 is + port ( + pll_ref_clk : in std_logic := 'X'; -- clk + global_reset_n : in std_logic := 'X'; -- reset_n + soft_reset_n : in std_logic := 'X'; -- reset_n + afi_clk : out std_logic; -- clk + afi_half_clk : out std_logic; -- clk + afi_reset_n : out std_logic; -- reset_n + afi_reset_export_n : out std_logic; -- reset_n + mem_a : out std_logic_vector(12 downto 0); -- mem_a + mem_ba : out std_logic_vector(2 downto 0); -- mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n + mem_reset_n : out std_logic; -- mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + avl_ready_0 : out std_logic; -- waitrequest_n + avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- address + avl_rdata_valid_0 : out std_logic; -- readdatavalid + avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata + avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + avl_read_req_0 : in std_logic := 'X'; -- read + avl_write_req_0 : in std_logic := 'X'; -- write + avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + mp_cmd_clk_0_clk : in std_logic := 'X'; -- clk + mp_cmd_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + mp_rfifo_clk_0_clk : in std_logic := 'X'; -- clk + mp_rfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + mp_wfifo_clk_0_clk : in std_logic := 'X'; -- clk + mp_wfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + csr_clk : in std_logic := 'X'; -- clk + csr_reset_n : in std_logic := 'X'; -- reset_n + local_init_done : out std_logic; -- local_init_done + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + oct_rzqin : in std_logic := 'X'; -- rzqin + pll_mem_clk : out std_logic; -- pll_mem_clk + pll_write_clk : out std_logic; -- pll_write_clk + pll_locked : out std_logic; -- pll_locked + pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk + pll_avl_clk : out std_logic; -- pll_avl_clk + pll_config_clk : out std_logic; -- pll_config_clk + pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk + afi_phy_clk : out std_logic; -- afi_phy_clk + pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk + ); + end component ddr3_0002; + +begin + + ddr3_inst : component ddr3_0002 + port map ( + pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk + global_reset_n => global_reset_n, -- global_reset.reset_n + soft_reset_n => soft_reset_n, -- soft_reset.reset_n + afi_clk => afi_clk, -- afi_clk.clk + afi_half_clk => afi_half_clk, -- afi_half_clk.clk + afi_reset_n => afi_reset_n, -- afi_reset.reset_n + afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n + mem_a => mem_a, -- memory.mem_a + mem_ba => mem_ba, -- .mem_ba + mem_ck => mem_ck, -- .mem_ck + mem_ck_n => mem_ck_n, -- .mem_ck_n + mem_cke => mem_cke, -- .mem_cke + mem_cs_n => mem_cs_n, -- .mem_cs_n + mem_dm => mem_dm, -- .mem_dm + mem_ras_n => mem_ras_n, -- .mem_ras_n + mem_cas_n => mem_cas_n, -- .mem_cas_n + mem_we_n => mem_we_n, -- .mem_we_n + mem_reset_n => mem_reset_n, -- .mem_reset_n + mem_dq => mem_dq, -- .mem_dq + mem_dqs => mem_dqs, -- .mem_dqs + mem_dqs_n => mem_dqs_n, -- .mem_dqs_n + mem_odt => mem_odt, -- .mem_odt + avl_ready_0 => avl_ready_0, -- avl_0.waitrequest_n + avl_burstbegin_0 => avl_burstbegin_0, -- .beginbursttransfer + avl_addr_0 => avl_addr_0, -- .address + avl_rdata_valid_0 => avl_rdata_valid_0, -- .readdatavalid + avl_rdata_0 => avl_rdata_0, -- .readdata + avl_wdata_0 => avl_wdata_0, -- .writedata + avl_be_0 => avl_be_0, -- .byteenable + avl_read_req_0 => avl_read_req_0, -- .read + avl_write_req_0 => avl_write_req_0, -- .write + avl_size_0 => avl_size_0, -- .burstcount + mp_cmd_clk_0_clk => mp_cmd_clk_0_clk, -- mp_cmd_clk_0.clk + mp_cmd_reset_n_0_reset_n => mp_cmd_reset_n_0_reset_n, -- mp_cmd_reset_n_0.reset_n + mp_rfifo_clk_0_clk => mp_rfifo_clk_0_clk, -- mp_rfifo_clk_0.clk + mp_rfifo_reset_n_0_reset_n => mp_rfifo_reset_n_0_reset_n, -- mp_rfifo_reset_n_0.reset_n + mp_wfifo_clk_0_clk => mp_wfifo_clk_0_clk, -- mp_wfifo_clk_0.clk + mp_wfifo_reset_n_0_reset_n => mp_wfifo_reset_n_0_reset_n, -- mp_wfifo_reset_n_0.reset_n + csr_clk => csr_clk, -- csr_clk.clk + csr_reset_n => csr_reset_n, -- csr_reset_n.reset_n + local_init_done => local_init_done, -- status.local_init_done + local_cal_success => local_cal_success, -- .local_cal_success + local_cal_fail => local_cal_fail, -- .local_cal_fail + oct_rzqin => oct_rzqin, -- oct.rzqin + pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk + pll_write_clk => pll_write_clk, -- .pll_write_clk + pll_locked => pll_locked, -- .pll_locked + pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk + pll_avl_clk => pll_avl_clk, -- .pll_avl_clk + pll_config_clk => pll_config_clk, -- .pll_config_clk + pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk + afi_phy_clk => afi_phy_clk, -- .afi_phy_clk + pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk + ); + +end architecture rtl; -- of ddr3 +-- Retrieval info: +-- +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- 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ddr3_p0_iss_probe.v, ddr3_p0.sv, ddr3_p0_altdqdqs.v, altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv, ddr3_s0.v, ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv, ddr3_s0_mm_interconnect_0_avalon_st_adapter.v, ddr3_s0_mm_interconnect_0_rsp_mux_002.sv, ddr3_s0_mm_interconnect_0_rsp_mux_001.sv, ddr3_s0_mm_interconnect_0_rsp_mux.sv, ddr3_s0_mm_interconnect_0_rsp_demux_003.sv, ddr3_s0_mm_interconnect_0_rsp_demux_001.sv, ddr3_s0_mm_interconnect_0_cmd_mux_003.sv, ddr3_s0_mm_interconnect_0_cmd_mux_001.sv, ddr3_s0_mm_interconnect_0_cmd_mux.sv, altera_merlin_arbitrator.sv, ddr3_s0_mm_interconnect_0_cmd_demux_002.sv, ddr3_s0_mm_interconnect_0_cmd_demux_001.sv, ddr3_s0_mm_interconnect_0_cmd_demux.sv, altera_merlin_reorder_memory.sv, altera_merlin_traffic_limiter.sv, ddr3_s0_mm_interconnect_0_router_006.sv, ddr3_s0_mm_interconnect_0_router_004.sv, ddr3_s0_mm_interconnect_0_router_003.sv, ddr3_s0_mm_interconnect_0_router_002.sv, ddr3_s0_mm_interconnect_0_router_001.sv, ddr3_s0_mm_interconnect_0_router.sv, altera_merlin_burst_uncompressor.sv, altera_merlin_slave_agent.sv, altera_merlin_master_agent.sv, ddr3_s0_irq_mapper.sv, ddr3_s0_mm_interconnect_0.v, altera_avalon_mm_bridge.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, altera_mem_if_simple_avalon_mm_bridge.sv, sequencer_reg_file.sv, sequencer_scc_reg_file.v, sequencer_scc_acv_phase_decode.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_sv_phase_decode.v, sequencer_scc_sv_wrapper.sv, sequencer_scc_siii_phase_decode.v, sequencer_scc_siii_wrapper.sv, sequencer_scc_mgr.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v, altera_mem_if_sequencer_rst.sv, ddr3_dmaster.v, altera_mem_if_hard_memory_controller_top_cyclonev.sv, altera_mem_if_oct_cyclonev.sv, altera_mem_if_dll_cyclonev.sv, ddr3_mm_interconnect_1.v, ddr3_mm_interconnect_2.v, altera_reset_controller.v, altera_reset_synchronizer.v, altera_avalon_st_jtag_interface.v, altera_jtag_dc_streaming.v, altera_jtag_sld_node.v, altera_jtag_streaming.v, altera_avalon_st_clock_crosser.v, altera_std_synchronizer_nocut.v, altera_avalon_st_pipeline_base.v, altera_avalon_st_idle_remover.v, altera_avalon_st_idle_inserter.v, altera_avalon_st_pipeline_stage.sv, ddr3_dmaster_timing_adt.sv, altera_avalon_sc_fifo.v, altera_avalon_st_bytes_to_packets.v, altera_avalon_st_packets_to_bytes.v, altera_avalon_packets_to_master.v, ddr3_dmaster_b2p_adapter.sv, ddr3_dmaster_p2b_adapter.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, ddr3_mm_interconnect_2_router.sv, ddr3_mm_interconnect_2_router_001.sv, ddr3_mm_interconnect_2_router_002.sv, altera_merlin_burst_adapter.sv, altera_merlin_burst_adapter_uncmpr.sv, altera_merlin_burst_adapter_13_1.sv, altera_merlin_burst_adapter_new.sv, altera_incr_burst_converter.sv, altera_wrap_burst_converter.sv, altera_default_burst_converter.sv, altera_merlin_address_alignment.sv, ddr3_mm_interconnect_2_cmd_demux.sv, ddr3_mm_interconnect_2_cmd_mux.sv, ddr3_mm_interconnect_2_rsp_demux.sv, ddr3_mm_interconnect_2_rsp_mux.sv, altera_merlin_width_adapter.sv, ddr3_mm_interconnect_2_avalon_st_adapter.v, ddr3_mm_interconnect_2_avalon_st_adapter_001.v, ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0.sv, ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0.sv diff --git a/ip/altera/ddr3/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv b/ip/altera/ddr3/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv new file mode 100644 index 0000000..521d9f4 --- /dev/null +++ b/ip/altera/ddr3/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv @@ -0,0 +1,2457 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// altera message_off 10034 10036 10030 10858 + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12161" *) +module altdq_dqs2_acv_connect_to_hard_phy_cyclonev ( + dll_delayctrl_in, + dll_offsetdelay_in, + capture_strobe_in, + capture_strobe_n_in, + capture_strobe_ena, + capture_strobe_out, + + output_strobe_ena, + output_strobe_out, + output_strobe_n_out, + oct_ena_in, + strobe_io, + strobe_n_io, + + core_clock_in, + fr_clock_in, + hr_clock_in, + dr_clock_in, + strobe_ena_hr_clock_in, + write_strobe_clock_in, + write_strobe, + reset_n_core_clock_in, + parallelterminationcontrol_in, + seriesterminationcontrol_in, + + read_data_in, + write_data_out, + read_write_data_io, + + write_oe_in, + read_data_out, + write_data_in, + extra_write_data_in, + extra_write_data_out, + capture_strobe_tracking, + + lfifo_rdata_en, + lfifo_rdata_en_full, + lfifo_rd_latency, + lfifo_reset_n, + lfifo_rdata_valid, + vfifo_qvld, + vfifo_inc_wr_ptr, + vfifo_reset_n, + rfifo_reset_n, + + config_data_in, + config_dqs_ena, + config_io_ena, + config_extra_io_ena, + config_dqs_io_ena, + config_update, + config_clock_in + +); + +parameter PIN_WIDTH = 8; +parameter PIN_TYPE = "bidir"; + +parameter USE_INPUT_PHASE_ALIGNMENT = "false"; +parameter USE_OUTPUT_PHASE_ALIGNMENT = "false"; +parameter USE_HALF_RATE_INPUT = "false"; +parameter USE_HALF_RATE_OUTPUT = "false"; + +parameter DIFFERENTIAL_CAPTURE_STROBE = "false"; +parameter SEPARATE_CAPTURE_STROBE = "false"; + +parameter INPUT_FREQ = 0.0; +parameter INPUT_FREQ_PS = "0 ps"; +parameter DELAY_CHAIN_BUFFER_MODE = "high"; +parameter DQS_PHASE_SETTING = 3; +parameter DQS_PHASE_SHIFT = 9000; +localparam DQS_DELAYCHAIN_BYPASS = (DQS_PHASE_SHIFT == 0) ? "true" : "false"; +parameter DQS_ENABLE_PHASE_SETTING = 2; +parameter USE_DYNAMIC_CONFIG = "true"; +parameter INVERT_CAPTURE_STROBE = "false"; +parameter SWAP_CAPTURE_STROBE_POLARITY = "false"; +parameter USE_TERMINATION_CONTROL = "false"; +parameter USE_OCT_ENA_IN_FOR_OCT = "false"; +parameter USE_DQS_ENABLE = "false"; +parameter USE_IO_CONFIG = "false"; +parameter USE_DQS_CONFIG = "false"; + +parameter USE_OFFSET_CTRL = "false"; +parameter HR_DDIO_OUT_HAS_THREE_REGS = "true"; + +parameter USE_OUTPUT_STROBE = "true"; +parameter DIFFERENTIAL_OUTPUT_STROBE = "false"; +parameter USE_OUTPUT_STROBE_RESET = "true"; +parameter USE_BIDIR_STROBE = "false"; +parameter REVERSE_READ_WORDS = "false"; +parameter NATURAL_ALIGNMENT = "false"; + +parameter EXTRA_OUTPUT_WIDTH = 0; +parameter PREAMBLE_TYPE = "none"; +parameter USE_DATA_OE_FOR_OCT = "false"; +parameter DQS_ENABLE_WIDTH = 1; +parameter EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false"; +parameter EMIF_BYPASS_OCT_DDIO = "false"; + +parameter USE_2X_FF = "false"; +parameter USE_DQS_TRACKING = "false"; + +parameter SEPERATE_LDC_FOR_WRITE_STROBE = "false"; + +localparam rate_mult_in = (USE_HALF_RATE_INPUT == "true") ? 4 : 2; +localparam rate_mult_out = (USE_HALF_RATE_OUTPUT == "true") ? 4 : 2; +localparam fpga_width_in = PIN_WIDTH * rate_mult_in; +localparam fpga_width_out = PIN_WIDTH * rate_mult_out; +localparam extra_fpga_width_out = EXTRA_OUTPUT_WIDTH * rate_mult_out; +localparam OS_ENA_WIDTH = rate_mult_out / 2; +localparam WRITE_OE_WIDTH = PIN_WIDTH * rate_mult_out / 2; +parameter DQS_ENABLE_PHASECTRL = "true"; + +parameter DYNAMIC_MODE = "dynamic"; + +parameter OCT_SERIES_TERM_CONTROL_WIDTH = 16; +parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = 16; +parameter DLL_WIDTH = 6; +parameter REGULAR_WRITE_BUS_ORDERING = "true"; + +parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = 0; + +parameter USE_HARD_FIFOS = "false"; +parameter CALIBRATION_SUPPORT = "false"; +parameter USE_DQSIN_FOR_VFIFO_READ = "false"; +parameter HHP_HPS = "false"; + +localparam READ_FIFO_MODE = (USE_HALF_RATE_OUTPUT == "true") ? "hrate_mode" : "frate_mode"; + +localparam DATA_RATE = 1; + + +localparam DELAY_CHAIN_WIDTH = 5; + +localparam OUTPUT_ALIGNMENT_DELAY = "two_cycle"; + +input [DLL_WIDTH-1:0] dll_delayctrl_in; +input [DLL_WIDTH-1:0] dll_offsetdelay_in; + +input core_clock_in; +input fr_clock_in; +input hr_clock_in; +input strobe_ena_hr_clock_in; +input write_strobe_clock_in; +input [3:0] write_strobe; + +input [PIN_WIDTH-1:0] read_data_in; +output [PIN_WIDTH-1:0] write_data_out; +inout [PIN_WIDTH-1:0] read_write_data_io; + +input capture_strobe_in; +input capture_strobe_n_in; +input [DQS_ENABLE_WIDTH-1:0] capture_strobe_ena; + +input reset_n_core_clock_in; +parameter USE_LDC_AS_LOW_SKEW_CLOCK = "false"; +parameter DLL_USE_2X_CLK = "false"; + +parameter DQS_ENABLE_AFTER_T7 = "true"; + +input [OS_ENA_WIDTH-1:0] output_strobe_ena; +output output_strobe_out; +output output_strobe_n_out; +input [1:0] oct_ena_in; +inout strobe_io; +inout strobe_n_io; + +output [fpga_width_out-1:0] read_data_out; +input [fpga_width_out-1:0] write_data_in; + +input [WRITE_OE_WIDTH-1:0] write_oe_in; +output capture_strobe_out; + +input [extra_fpga_width_out-1:0] extra_write_data_in; +output [EXTRA_OUTPUT_WIDTH-1:0] extra_write_data_out; + +output capture_strobe_tracking; + +parameter LFIFO_OCT_EN_MASK = 4294967295; +input [(rate_mult_out / 2)-1:0] lfifo_rdata_en; +input [(rate_mult_out / 2)-1:0] lfifo_rdata_en_full; +localparam LFIFO_RD_LATENCY_WIDTH = 5; +input [LFIFO_RD_LATENCY_WIDTH-1:0] lfifo_rd_latency; +input lfifo_reset_n; +output lfifo_rdata_valid; +input [(rate_mult_out / 2)-1:0] vfifo_qvld; +input [(rate_mult_out / 2)-1:0] vfifo_inc_wr_ptr; +input vfifo_reset_n; +input rfifo_reset_n; + +input dr_clock_in; + +input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] parallelterminationcontrol_in; +input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] seriesterminationcontrol_in; + +input config_data_in; +input config_update; +input config_dqs_ena; +input [PIN_WIDTH-1:0] config_io_ena; +input [EXTRA_OUTPUT_WIDTH-1:0] config_extra_io_ena; +input config_dqs_io_ena; +input config_clock_in; + +wire [DLL_WIDTH-1:0] dll_delay_value; +assign dll_delay_value = dll_delayctrl_in; + +wire dqsbusout; +wire dqsnbusout; + +wire capture_strobe; + + +wire [1:0] inputclkdelaysetting; +wire [1:0] inputclkndelaysetting; +wire [4:0] dqs_outputdelaysetting; +wire [4:0] dqs_outputenabledelaysetting; + +wire [DELAY_CHAIN_WIDTH-1:0] dqs_outputdelaysetting_dlc; +wire [DELAY_CHAIN_WIDTH-1:0] dqs_outputenabledelaysetting_dlc; + + + +`ifndef FAMILY_HAS_NO_DYNCONF +generate +if (USE_DYNAMIC_CONFIG =="true" && (USE_OUTPUT_STROBE == "true" || PIN_TYPE =="input" || PIN_TYPE == "bidir")) +begin + + cyclonev_io_config dqs_io_config_1 ( + .outputhalfratebypass(), + .readfiforeadclockselect(), + .readfifomode(), + .padtoinputregisterdelaysetting(), + .datain(config_data_in), + .clk(config_clock_in), + .ena(config_dqs_io_ena), + .update(config_update), + .outputregdelaysetting(dqs_outputdelaysetting), + .outputenabledelaysetting(dqs_outputenabledelaysetting), + .dataout() + ); + + assign dqs_outputdelaysetting_dlc = dqs_outputdelaysetting; + assign dqs_outputenabledelaysetting_dlc = dqs_outputenabledelaysetting; + + /* + cyclonev_io_config dqsn_io_config_1 ( + .datain(config_data_in), + .clk(config_clock_in), + .ena(config_dqs_io_ena), + .update(config_update), + .outputregdelaysetting(dqsn_outputdelaysetting), + .outputenabledelaysetting(dqsn_outputenabledelaysetting), + .padtoinputregisterdelaysetting(dqsn_inputdelaysetting), + + .dataout() + ); + */ +end +endgenerate +`endif + +wire [1:0] oct_ena; +wire fr_term; + +wire [1:0] oct_source; + +generate + if (USE_DATA_OE_FOR_OCT == "true") + begin + assign oct_source = ~write_oe_in; + end + else + begin + assign oct_source = ~output_strobe_ena; + end +endgenerate + +generate + if (USE_HARD_FIFOS == "true") + begin + if (USE_HALF_RATE_OUTPUT == "true") + begin + if (USE_OCT_ENA_IN_FOR_OCT == "true") + begin + assign oct_ena = oct_ena_in; + end + else + begin + assign oct_ena = oct_source; + end + + end + else + begin + if (USE_OCT_ENA_IN_FOR_OCT == "true") + begin + assign fr_term = oct_ena_in[0]; + end + else + begin + assign fr_term = oct_source[0]; + end + end + end + else + begin + if (USE_HALF_RATE_OUTPUT == "true") + begin : oct_ena_hr_gen + if (USE_OCT_ENA_IN_FOR_OCT == "true") + begin + assign oct_ena = oct_ena_in; + end + else + begin + reg oct_ena_hr_reg; + always @(posedge hr_clock_in) + oct_ena_hr_reg <= oct_source[1]; + assign oct_ena[1] = ~oct_source[1]; + assign oct_ena[0] = ~(oct_ena_hr_reg | oct_source[1]); + end + end + else + begin : oct_ena_fr_gen + if (USE_OCT_ENA_IN_FOR_OCT == "true") + begin + assign fr_term = oct_ena_in[0]; + end + else + begin + reg oct_ena_fr_reg; + initial + oct_ena_fr_reg = 0; + always @(posedge hr_clock_in) + oct_ena_fr_reg <= oct_source[0]; + assign fr_term = ~(oct_source[0] | oct_ena_fr_reg); + end + end + end +endgenerate + + + +localparam PINS_PER_DQS_CONFIG = 6; +localparam NUM_STROBES = (DIFFERENTIAL_CAPTURE_STROBE == "true" || SEPARATE_CAPTURE_STROBE == "true") ? 2 : 1; +localparam DQS_CONFIGS = (PIN_WIDTH + EXTRA_OUTPUT_WIDTH + NUM_STROBES) / PINS_PER_DQS_CONFIG; + +wire dividerphasesetting [DQS_CONFIGS:0]; +wire dqoutputphaseinvert [DQS_CONFIGS:0]; +wire [1:0] dqoutputphasesetting [DQS_CONFIGS:0]; +wire [4:0] dqsbusoutdelaysetting [DQS_CONFIGS:0]; +wire [1:0] dqsoutputphasesetting [DQS_CONFIGS:0]; +wire [1:0] resyncinputphasesetting [DQS_CONFIGS:0]; +wire [4:0] dqsenabledelaysetting [DQS_CONFIGS:0]; +wire [4:0] dqsdisabledelaysetting [DQS_CONFIGS:0]; +wire dqshalfratebypass [DQS_CONFIGS:0]; +wire [1:0] dqsinputphasesetting [DQS_CONFIGS:0]; +wire [1:0] dqsenablectrlphasesetting [DQS_CONFIGS:0]; +wire dqoutputpowerdown [DQS_CONFIGS:0]; +wire dqsoutputpowerdown [DQS_CONFIGS:0]; +wire resyncinputpowerdown [DQS_CONFIGS:0]; +wire dqsenablectrlpowerdown [DQS_CONFIGS:0]; + +wire [1:0] dq2xoutputphasesetting [DQS_CONFIGS:0]; +wire dq2xoutputphaseinvert [DQS_CONFIGS:0]; +wire [1:0] dqs2xoutputphasesetting [DQS_CONFIGS:0]; +wire dqs2xoutputphaseinvert [DQS_CONFIGS:0]; + +wire dqsbusoutfinedelaysetting [DQS_CONFIGS:0]; +wire dqsenablectrlphaseinvert [DQS_CONFIGS:0]; +wire dqsenablefinedelaysetting [DQS_CONFIGS:0]; +wire dqsoutputphaseinvert [DQS_CONFIGS:0]; +wire enadataoutbypass [DQS_CONFIGS:0]; +wire enadqsenablephasetransferreg [DQS_CONFIGS:0]; + +wire enainputcycledelaysetting [DQS_CONFIGS:0]; +wire enainputphasetransferreg [DQS_CONFIGS:0]; + +wire enaoctphasetransferreg [DQS_CONFIGS:0]; +wire enaoutputphasetransferreg [DQS_CONFIGS:0]; +wire enadqsphasetransferreg [DQS_CONFIGS:0]; +wire [2:0] enadqscycledelaysetting [DQS_CONFIGS:0]; +wire [2:0] enaoctcycledelaysetting [DQS_CONFIGS:0]; +wire [2:0] enaoutputcycledelaysetting [DQS_CONFIGS:0]; +wire [4:0] octdelaysetting1 [DQS_CONFIGS:0]; + +wire resyncinputphaseinvert [DQS_CONFIGS:0]; + +wire [DELAY_CHAIN_WIDTH-1:0] dqsbusoutdelaysetting_dlc[DQS_CONFIGS:0]; +wire [DELAY_CHAIN_WIDTH-1:0] dqsenabledelaysetting_dlc[DQS_CONFIGS:0]; +wire [DELAY_CHAIN_WIDTH-1:0] dqsdisabledelaysetting_dlc[DQS_CONFIGS:0]; +wire [DELAY_CHAIN_WIDTH-1:0] octdelaysetting1_dlc[DQS_CONFIGS:0]; + +`ifndef FAMILY_HAS_NO_DYNCONF +generate +if (USE_DYNAMIC_CONFIG == "true") +begin + genvar c_num; + for (c_num = 0; c_num <= DQS_CONFIGS; c_num = c_num + 1) + begin :dqs_config_gen + + cyclonev_dqs_config dqs_config_inst + ( + .clk(config_clock_in), + .datain(config_data_in), + .dataout(), + .ena(config_dqs_ena), + .update(config_update), + + .postamblephasesetting(dqsenablectrlphasesetting[c_num]), + .postamblephaseinvert(dqsenablectrlphaseinvert[c_num]), + + .dqsenablegatingdelaysetting(dqsenabledelaysetting[c_num]), + .dqsenableungatingdelaysetting(dqsdisabledelaysetting[c_num]), + .dqshalfratebypass(dqshalfratebypass[c_num]), + + .enadqsenablephasetransferreg(enadqsenablephasetransferreg[c_num]), + .octdelaysetting(octdelaysetting1[c_num]), + .dqsbusoutdelaysetting(dqsbusoutdelaysetting[c_num]) + ); + assign dqsbusoutdelaysetting_dlc[c_num] = dqsbusoutdelaysetting[c_num]; + assign dqsenabledelaysetting_dlc[c_num] = dqsenabledelaysetting[c_num]; + assign dqsdisabledelaysetting_dlc[c_num] = dqsdisabledelaysetting[c_num]; + assign octdelaysetting1_dlc[c_num] = octdelaysetting1[c_num]; + end +end +endgenerate +`endif + +generate +if (USE_BIDIR_STROBE == "true") +begin + assign output_strobe_out = 1'b0; + assign output_strobe_n_out = 1'b1; +end +else +begin + assign strobe_io = 1'b0; + assign strobe_n_io = 1'b1; +end +endgenerate + +wire dq_dr_clock; +wire dqs_dr_clock; +wire dq_shifted_clock; +wire dqs_shifted_clock; +wire write_strobe_clock; +wire hr_seq_clock; + +wire ena_clock; +wire ena_zero_phase_clock; + + +wire phy_clk_dqs_2x; +wire phy_clk_dqs; +wire phy_clk_dq; +wire phy_clk_hr; + +generate +if (HHP_HPS == "true") begin + assign phy_clk_hr = hr_clock_in; + assign phy_clk_dq = fr_clock_in; + assign phy_clk_dqs = write_strobe_clock_in; + assign phy_clk_dqs_2x = dr_clock_in; +end else begin + cyclonev_phy_clkbuf phy_clkbuf ( + .inclk ({hr_clock_in, fr_clock_in, write_strobe_clock_in, dr_clock_in}), + .outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x}) + ); +end +endgenerate + +wire [3:0] leveled_dqs_clocks; +wire [3:0] leveled_dq_clocks; +wire [3:0] leveled_hr_clocks; + +cyclonev_leveling_delay_chain leveling_delay_chain_dqs ( + .clkin (phy_clk_dqs), + .delayctrlin (dll_delay_value), + .clkout(leveled_dqs_clocks) +); +defparam leveling_delay_chain_dqs.physical_clock_source = "DQS"; + +cyclonev_clk_phase_select clk_phase_select_dqs ( + .phasectrlin(), + .phaseinvertctrl(), + .dqsin(), + .clkin (leveled_dqs_clocks[0]), + .clkout (dqs_shifted_clock) +); +defparam clk_phase_select_dqs.physical_clock_source = "DQS"; +defparam clk_phase_select_dqs.use_phasectrlin = "false"; +defparam clk_phase_select_dqs.phase_setting = 0; + +generate + if (SEPERATE_LDC_FOR_WRITE_STROBE == "true") begin + + wire extra_phy_clk_dqs_2x; + wire extra_phy_clk_dqs; + wire extra_phy_clk_dq; + wire extra_phy_clk_hr; + cyclonev_phy_clkbuf phy_clkbuf ( + .inclk ({hr_clock_in, fr_clock_in, write_strobe_clock_in, dr_clock_in}), + .outclk ({extra_phy_clk_hr, extra_phy_clk_dq, extra_phy_clk_dqs, extra_phy_clk_dqs_2x}) + ); + wire [3:0] extra_leveled_dqs_clocks; + cyclonev_leveling_delay_chain leveling_delay_chain_dqs ( + .clkin (extra_phy_clk_dqs), + .delayctrlin (dll_delay_value), + .clkout(extra_leveled_dqs_clocks) + ); + defparam leveling_delay_chain_dqs.physical_clock_source = "DQS"; + + cyclonev_clk_phase_select clk_phase_select_dqs ( + .phasectrlin(), + .phaseinvertctrl(), + .dqsin(), + .clkin (extra_leveled_dqs_clocks[0]), + .clkout (write_strobe_clock) + ); + defparam clk_phase_select_dqs.physical_clock_source = "DQS"; + defparam clk_phase_select_dqs.use_phasectrlin = "false"; + defparam clk_phase_select_dqs.phase_setting = 0; + end else begin + assign write_strobe_clock = dqs_shifted_clock; + end +endgenerate + +cyclonev_clk_phase_select clk_phase_select_pst_0p ( + .phasectrlin(), + .phaseinvertctrl(), + .dqsin(dqsbusout), + .clkin (leveled_dqs_clocks[0]), + .clkout (ena_zero_phase_clock) +); +defparam clk_phase_select_pst_0p.physical_clock_source = "PST_0P"; +defparam clk_phase_select_pst_0p.use_phasectrlin = "false"; +defparam clk_phase_select_pst_0p.phase_setting = 0; +defparam clk_phase_select_pst_0p.use_dqs_input = USE_DQSIN_FOR_VFIFO_READ; + +generate + if (USE_DYNAMIC_CONFIG == "true") + begin + cyclonev_clk_phase_select clk_phase_select_pst ( + .clkin (leveled_dqs_clocks), + .phasectrlin(dqsenablectrlphasesetting[0]), + .phaseinvertctrl(dqsenablectrlphaseinvert[0]), + .clkout (ena_clock), + .dqsin() + ); + defparam clk_phase_select_pst.physical_clock_source = "PST"; + defparam clk_phase_select_pst.invert_phase = "dynamic"; + end + else + begin + cyclonev_clk_phase_select clk_phase_select_pst ( + .clkin (leveled_dqs_clocks), + .phasectrlin(), + .phaseinvertctrl(), + .clkout (ena_clock), + .dqsin() + ); + defparam clk_phase_select_pst.physical_clock_source = "PST"; + defparam clk_phase_select_pst.use_phasectrlin = "false"; + end +endgenerate + +cyclonev_leveling_delay_chain leveling_delay_chain_dq ( + .clkin (phy_clk_dq), + .delayctrlin (), + .clkout(leveled_dq_clocks) +); +defparam leveling_delay_chain_dq.physical_clock_source = "DQ"; + +cyclonev_clk_phase_select clk_phase_select_dq ( + .phasectrlin(), + .phaseinvertctrl(), + .dqsin(), + .clkin (leveled_dq_clocks[0]), + .clkout (dq_shifted_clock) +); +defparam clk_phase_select_dq.physical_clock_source = "DQ"; +defparam clk_phase_select_dq.use_phasectrlin = "false"; +defparam clk_phase_select_dq.phase_setting = 0; + +cyclonev_leveling_delay_chain leveling_delay_chain_hr ( + .clkin (phy_clk_hr), + .delayctrlin (), + .clkout(leveled_hr_clocks) +); +defparam leveling_delay_chain_hr.physical_clock_source = "HR"; + +cyclonev_clk_phase_select clk_phase_select_hr ( + .phasectrlin(), + .phaseinvertctrl(), + .dqsin(), + .clkin (leveled_hr_clocks[0]), + .clkout (hr_seq_clock) +); +defparam clk_phase_select_hr.physical_clock_source = "HR"; +defparam clk_phase_select_hr.use_phasectrlin = "false"; +defparam clk_phase_select_hr.phase_setting = 0; + +generate +if (USE_2X_FF == "true") +begin + wire [3:0] leveled_dqs_2x_clocks; + + cyclonev_leveling_delay_chain leveling_delay_chain_dqs_2x ( + .clkin (phy_clk_dqs_2x), + .delayctrlin (), + .clkout(leveled_dqs_2x_clocks) + ); + defparam leveling_delay_chain_dqs_2x.physical_clock_source = "DQS_2X"; + + cyclonev_clk_phase_select clk_phase_select_dqs_2x ( + .phasectrlin(), + .phaseinvertctrl(), + .dqsin(), + .clkin (leveled_dqs_2x_clocks[0]), + .clkout (dqs_dr_clock) + ); + defparam clk_phase_select_dqs_2x.physical_clock_source = "DQS_2X"; + defparam clk_phase_select_dqs_2x.use_phasectrlin = "false"; + defparam clk_phase_select_dqs_2x.phase_setting = 0; + + assign dq_dr_clock = dqs_dr_clock; +end +endgenerate + +generate +wire vfifo_capture_strobe_ena; +wire lfifo_rden; +wire lfifo_oct; +if (USE_HARD_FIFOS == "true" && (PIN_TYPE == "input" || PIN_TYPE == "bidir")) +begin + wire vfifo_qvld_fr; + wire vfifo_inc_wr_ptr_fr; + wire lfifo_rdata_en_fr; + wire lfifo_rdata_en_full_fr; + if (USE_HALF_RATE_OUTPUT == "true") + begin + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_vfifo_qvld ( + .datainhi(vfifo_qvld[0]), + .datainlo(vfifo_qvld[1]), + .dataout(vfifo_qvld_fr), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dqshalfratebypass[0]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_vfifo_inc_wr_ptr ( + .datainhi(vfifo_inc_wr_ptr[0]), + .datainlo(vfifo_inc_wr_ptr[1]), + .dataout(vfifo_inc_wr_ptr_fr), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dqshalfratebypass[0]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_lfifo_rdata_en ( + .datainhi(lfifo_rdata_en[0]), + .datainlo(lfifo_rdata_en[1]), + .dataout(lfifo_rdata_en_fr), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dqshalfratebypass[0]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_lfifo_rdata_en_full ( + .datainhi(lfifo_rdata_en_full[0]), + .datainlo(lfifo_rdata_en_full[1]), + .dataout(lfifo_rdata_en_full_fr), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dqshalfratebypass[0]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + end + else + begin + assign vfifo_qvld_fr = vfifo_qvld[0]; + assign vfifo_inc_wr_ptr_fr = vfifo_inc_wr_ptr[0]; + assign lfifo_rdata_en_fr = lfifo_rdata_en[0]; + assign lfifo_rdata_en_full_fr = lfifo_rdata_en_full[0]; + end + + cyclonev_vfifo + vfifo ( + .rstn (vfifo_reset_n), + .qvldin (vfifo_qvld_fr), + .qvldreg (vfifo_capture_strobe_ena), + .incwrptr (vfifo_inc_wr_ptr_fr), + .wrclk (dqs_shifted_clock), + .rdclk (ena_zero_phase_clock) + ); + + wire [LFIFO_RD_LATENCY_WIDTH-1:0] lfifo_rd_latency_full_rate; + + assign lfifo_rd_latency_full_rate = lfifo_rd_latency << (DATA_RATE-1); + + cyclonev_lfifo + #( + .oct_lfifo_enable(LFIFO_OCT_EN_MASK) + ) lfifo ( + .rdataen (lfifo_rdata_en_fr), + .rdataenfull (lfifo_rdata_en_full_fr), + .rdlatency (lfifo_rd_latency_full_rate), + .rstn (lfifo_reset_n), + .clk (dqs_shifted_clock), + .rden (lfifo_rden), + .rdatavalid(lfifo_rdata_valid), + .octlfifo(lfifo_oct) + ); +end +else +begin + assign vfifo_capture_strobe_ena = 1'b0; + assign lfifo_rden = 1'b0; + assign lfifo_rdata_valid = 1'b0; + assign lfifo_oct = 1'b0; +end +endgenerate + +wire delayed_oct; +generate + wire fr_os_oct; + wire aligned_os_oct; + + if (USE_HALF_RATE_OUTPUT == "true") + begin + if (EMIF_BYPASS_OCT_DDIO == "true") + begin + assign fr_os_oct = oct_ena[0]; + end + else + begin + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_os_oct ( + .datainhi(oct_ena[0]), + .datainlo(oct_ena[1]), + .dataout(fr_os_oct), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dqshalfratebypass[0]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + end + end + else + begin + assign fr_os_oct = fr_term; + end + + if (USE_HARD_FIFOS == "true") + begin + if (EMIF_BYPASS_OCT_DDIO == "true") + begin + assign aligned_os_oct = fr_os_oct; + end + else + begin + cyclonev_ddio_oe # ( + .disable_second_level_register("true") + ) os_oct_ddio_oe ( + .clk (dqs_shifted_clock), + .oe (fr_os_oct), + .octreadcontrol (lfifo_oct), + .dataout (aligned_os_oct), + .ena (1'b1), + .areset (), + .sreset (), + .dfflo (), + .dffhi (), + .devpor (), + .devclrn () + ); + end + end + else + begin + reg oct_oe_reg; + always @(posedge dqs_shifted_clock) oct_oe_reg <= fr_os_oct; + assign aligned_os_oct = oct_oe_reg; + end + + wire predelayed_os_oct; + if (USE_2X_FF == "true") + begin + reg dd_os_oct; + always @(posedge dqs_dr_clock) + begin + dd_os_oct <= aligned_os_oct; + end + assign predelayed_os_oct = dd_os_oct; + end + else + begin + assign predelayed_os_oct = aligned_os_oct; + end + + if (USE_DYNAMIC_CONFIG == "true") + begin + if (EMIF_BYPASS_OCT_DDIO == "true") + begin + assign delayed_oct = predelayed_os_oct; + end + else + begin + cyclonev_delay_chain # ( + .sim_intrinsic_rising_delay(0), + .sim_intrinsic_falling_delay(0) + ) oct_delay ( + .datain (predelayed_os_oct), + .delayctrlin (octdelaysetting1_dlc[0]), + .dataout (delayed_oct) + ); + end + end + else + begin + assign delayed_oct = predelayed_os_oct; + end +endgenerate + + +generate +if (PIN_TYPE == "input" || PIN_TYPE == "bidir") +begin + + assign capture_strobe = dqsbusout; + wire dqsin; + + wire capture_strobe_ibuf_i; + wire capture_strobe_ibuf_ibar; + + if (USE_BIDIR_STROBE == "true") + begin + if (SWAP_CAPTURE_STROBE_POLARITY == "true") begin + assign capture_strobe_ibuf_i = strobe_n_io; + assign capture_strobe_ibuf_ibar = strobe_io; + end else begin + assign capture_strobe_ibuf_i = strobe_io; + assign capture_strobe_ibuf_ibar = strobe_n_io; + end + end + else + begin + if (SWAP_CAPTURE_STROBE_POLARITY == "true") begin + assign capture_strobe_ibuf_i = capture_strobe_n_in; + assign capture_strobe_ibuf_ibar = capture_strobe_in; + end else begin + assign capture_strobe_ibuf_i = capture_strobe_in; + assign capture_strobe_ibuf_ibar = capture_strobe_n_in; + end + end + + if (DIFFERENTIAL_CAPTURE_STROBE == "true") + begin + cyclonev_io_ibuf + #( + .differential_mode(DIFFERENTIAL_CAPTURE_STROBE), + .bus_hold("false") + ) strobe_in ( + .i(capture_strobe_ibuf_i), + .ibar(capture_strobe_ibuf_ibar), + .o(dqsin), + .dynamicterminationcontrol(1'b0) + ); + end + else + begin + cyclonev_io_ibuf + #( + .bus_hold("false") + ) strobe_in ( + .i(capture_strobe_ibuf_i), + .o(dqsin), + .ibar(), + .dynamicterminationcontrol(1'b0) + ); + end + + + wire capture_strobe_ena_fr; + if (USE_HARD_FIFOS == "true") + begin + assign capture_strobe_ena_fr = vfifo_capture_strobe_ena; + end + else + begin + if (DQS_ENABLE_WIDTH > 1) + begin + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_ena ( + .datainhi(capture_strobe_ena[0]), + .datainlo(capture_strobe_ena[1]), + .dataout(capture_strobe_ena_fr), + .clkhi (strobe_ena_hr_clock_in), + .clklo (strobe_ena_hr_clock_in), + .hrbypass(dqshalfratebypass[0]), + .muxsel (strobe_ena_hr_clock_in) + ); + end + else + begin + assign capture_strobe_ena_fr = capture_strobe_ena; + end + end + + + + wire dqs_enable_shifted; + wire dqs_shifted; + wire dqs_enable_int; + wire dqs_disable_int; + + if (USE_BIDIR_STROBE == "true") + begin + wire dqs_pre_delayed; + + assign dqs_pre_delayed = capture_strobe_ena_fr; + if (USE_DYNAMIC_CONFIG == "true") + begin + cyclonev_dqs_enable_ctrl + #( + .add_phase_transfer_reg(DYNAMIC_MODE), + .delay_dqs_enable("one_and_half_cycle") + ) dqs_enable_ctrl ( + .dqsenablein (dqs_pre_delayed), + .zerophaseclk (ena_zero_phase_clock), + .levelingclk (ena_clock), + .dqsenableout (dqs_enable_shifted), + .enaphasetransferreg(enadqsenablephasetransferreg[0]), + .rstn(), + .dffin() + ); + end + else + begin + cyclonev_dqs_enable_ctrl + #( + .delay_dqs_enable("one_and_half_cycle") + ) dqs_enable_ctrl ( + .dqsenablein (dqs_pre_delayed), + .zerophaseclk (ena_zero_phase_clock), + .levelingclk (ena_clock), + .dqsenableout (dqs_enable_shifted), + .rstn(), + .dffin() + ); + end + + cyclonev_dqs_delay_chain + #( + .dqs_period(INPUT_FREQ_PS), + .dqs_phase_shift(DQS_PHASE_SHIFT), + .dqs_delay_chain_bypass(DQS_DELAYCHAIN_BYPASS) + ) + dqs_delay_chain ( + .dqsin (dqsin), + .delayctrlin (dll_delay_value), + .dqsenable (dqs_enable_int), + .dqsdisablen (dqs_disable_int), + .dqsbusout (dqs_shifted), + .dqsupdateen(), + .testin(), + .dffin() + ); + end + else + begin + if (USE_DYNAMIC_CONFIG == "true") + begin + cyclonev_dqs_delay_chain + #( + .dqs_period(INPUT_FREQ_PS), + .dqs_phase_shift(DQS_PHASE_SHIFT), + .dqs_delay_chain_bypass(DQS_DELAYCHAIN_BYPASS) + ) dqs_delay_chain ( + .dqsin (dqsin), + .delayctrlin (dll_delay_value), + .dqsbusout (dqs_shifted), + .dqsenable (), + .dqsdisablen (), + .dqsupdateen(), + .testin(), + .dffin() + ); + end + else + begin + cyclonev_dqs_delay_chain + #( + .dqs_period(INPUT_FREQ_PS), + .dqs_phase_shift(DQS_PHASE_SHIFT), + .dqs_delay_chain_bypass(DQS_DELAYCHAIN_BYPASS) + ) dqs_delay_chain ( + .dqsin (dqsin), + .delayctrlin (dll_delay_value), + .dqsbusout (dqs_shifted), + .dqsenable (), + .dqsdisablen (), + .dqsupdateen(), + .testin(), + .dffin() + ); + + end + end + + if (USE_DYNAMIC_CONFIG == "true") + begin + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + dqs_in_delay_1( + .datain (dqs_shifted), + .delayctrlin (dqsbusoutdelaysetting_dlc[0]), + .dataout (dqsbusout) + ); + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + dqs_ena_delay_1( + .datain (dqs_enable_shifted), + .delayctrlin (dqsenabledelaysetting_dlc[0]), + .dataout (dqs_enable_int) + ); + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + dqs_dis_delay_1( + .datain (dqs_enable_shifted), + .delayctrlin (dqsdisabledelaysetting_dlc[0]), + .dataout (dqs_disable_int) + ); + end + else + begin + assign dqsbusout = dqs_shifted; + assign dqs_enable_int = dqs_enable_shifted; + assign dqs_disable_int = dqs_enable_shifted; + end + + if (USE_DQS_TRACKING == "true") + begin + reg dqs_ff; + always @(negedge dqs_enable_int) + dqs_ff <= dqsin; + + assign capture_strobe_tracking = dqs_ff; + end + + if (SEPARATE_CAPTURE_STROBE == "true") + begin + + wire dqsnin; + + cyclonev_io_ibuf + #( + .bus_hold("false") + ) strobe_n_in ( + .i(capture_strobe_ibuf_ibar), + .o(dqsnin) + ); + + wire dqsn_enable_int; + wire dqsn_disable_int; + wire dqsn_enable_shifted; + wire dqsn_shifted; + + if (USE_BIDIR_STROBE == "true") + begin + if (USE_DYNAMIC_CONFIG == "true") + begin + cyclonev_dqs_enable_ctrl + #( + .add_phase_transfer_reg(DYNAMIC_MODE), + .delay_dqs_enable("one_and_half_cycle") + ) dqs_enable_n_ctrl ( + .dqsenablein (capture_strobe_ena_fr), + .zerophaseclk (ena_zero_phase_clock), + .levelingclk (ena_clock), + .dqsenableout (dqsn_enable_shifted), + .enaphasetransferreg(enadqsenablephasetransferreg[0]) + ); + end + else + begin + cyclonev_dqs_enable_ctrl + #( + .add_phase_transfer_reg("false"), + .delay_dqs_enable("one_and_half_cycle") + ) dqs_enable_n_ctrl ( + .dqsenablein (capture_strobe_ena_fr), + .zerophaseclk (ena_zero_phase_clock), + .levelingclk (ena_clock), + .dqsenableout (dqsn_enable_shifted) + ); + end + + cyclonev_dqs_delay_chain + #( + .dqs_period(INPUT_FREQ_PS), + .dqs_phase_shift(DQS_PHASE_SHIFT), + .dqs_delay_chain_bypass(DQS_DELAYCHAIN_BYPASS) + ) dqs_n_delay_chain ( + .dqsin (dqsnin), + .delayctrlin (dll_delay_value), + .dqsenable (dqsn_enable_int), + .dqsdisablen (dqsn_disable_int), + .dqsbusout (dqsn_shifted) + ); + + end + else + begin + cyclonev_dqs_delay_chain + #( + .dqs_period(INPUT_FREQ_PS), + .dqs_phase_shift(DQS_PHASE_SHIFT), + .dqs_delay_chain_bypass(DQS_DELAYCHAIN_BYPASS) + ) dqs_n_delay_chain ( + .dqsin (dqsnin), + .delayctrlin (dll_delay_value), + .dqsbusout (dqsn_shifted) + ); + end + + if (USE_DYNAMIC_CONFIG == "true") + begin + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + dqs_n_delay_1( + .datain (dqsn_shifted), + .delayctrlin (dqsbusoutdelaysetting_dlc[0]), + .dataout (dqsnbusout) + ); + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + dqs_n_ena_delay_1( + .datain (dqsn_enable_shifted), + .delayctrlin (dqsenabledelaysetting_dlc[0]), + .dataout (dqsn_enable_int) + ); + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + dqs_n_dis_delay_1( + .datain (dqsn_enable_shifted), + .delayctrlin (dqsdisabledelaysetting_dlc[0]), + .dataout (dqsn_disable_int) + ); + + end + else + begin + assign dqsnbusout = dqsn_shifted; + assign dqsn_enable_int = dqsn_enable_shifted; + assign dqsn_disable_int = dqsn_enable_shifted; + end + end +end +endgenerate + +generate +if (USE_OUTPUT_STROBE == "true") +begin + wire os; + wire os_bar; + wire os_dtc; + wire os_dtc_bar; + wire os_delayed1; + wire os_delayed2; + + wire fr_os_oe; + wire aligned_os_oe; + wire aligned_strobe; + + wire fr_os_hi; + wire fr_os_lo; + + if (USE_HALF_RATE_OUTPUT == "true") + begin + if (USE_BIDIR_STROBE == "true") + begin + wire clk_gate_hi; + wire clk_gate_lo; + + if (PREAMBLE_TYPE == "low") + begin + if (EMIF_UNALIGNED_PREAMBLE_SUPPORT != "true") + begin + assign clk_gate_hi = output_strobe_ena[0]; + assign clk_gate_lo = output_strobe_ena[0]; + end + else + begin + reg [1:0] os_ena_reg; + reg [1:0] os_ena_preamble; + + always @(posedge core_clock_in) + begin + os_ena_reg[1:0] <= output_strobe_ena[1:0]; + end + + always @(*) + begin + case ({os_ena_reg[0], os_ena_reg[1], + output_strobe_ena[0], output_strobe_ena[1]}) + 4'b00_00: os_ena_preamble[1:0] <= 2'b00; + 4'b00_01: os_ena_preamble[1:0] <= 2'b00; + 4'b00_10: os_ena_preamble[1:0] <= 2'b00; + 4'b00_11: os_ena_preamble[1:0] <= 2'b01; + + 4'b01_00: os_ena_preamble[1:0] <= 2'b00; + 4'b01_01: os_ena_preamble[1:0] <= 2'b00; + 4'b01_10: os_ena_preamble[1:0] <= 2'b10; + 4'b01_11: os_ena_preamble[1:0] <= 2'b11; + + 4'b10_00: os_ena_preamble[1:0] <= 2'b00; + 4'b10_01: os_ena_preamble[1:0] <= 2'b00; + 4'b10_10: os_ena_preamble[1:0] <= 2'b00; + 4'b10_11: os_ena_preamble[1:0] <= 2'b01; + + 4'b11_00: os_ena_preamble[1:0] <= 2'b00; + 4'b11_01: os_ena_preamble[1:0] <= 2'b00; + 4'b11_10: os_ena_preamble[1:0] <= 2'b10; + 4'b11_11: os_ena_preamble[1:0] <= 2'b11; + + default: os_ena_preamble[1:0] <= 2'b00; + endcase + end + + assign clk_gate_hi = os_ena_preamble[1]; + assign clk_gate_lo = os_ena_preamble[0]; + end + end + else + begin + assign clk_gate_hi = 1'b1; + assign clk_gate_lo = 1'b1; + end + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_os_hi ( + .hrbypass(1'b1), + .datainhi(write_strobe[0]), + .datainlo(write_strobe[2]), + .dataout(fr_os_hi), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_os_lo ( + .hrbypass(1'b1), + .datainhi(write_strobe[1]), + .datainlo(write_strobe[3]), + .dataout(fr_os_lo), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_os_oe ( + .hrbypass(1'b1), + .datainhi(~output_strobe_ena [0]), + .datainlo(~output_strobe_ena [1]), + .dataout(fr_os_oe), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + end + else + begin + wire gnd_lut /* synthesis keep = 1*/; + assign gnd_lut = 1'b0; + assign fr_os_lo = gnd_lut; + + assign fr_os_oe = 1'b0; + + if (USE_OUTPUT_STROBE_RESET == "true") begin + reg clk_h /* synthesis dont_merge */; + always @(posedge write_strobe_clock_in or negedge reset_n_core_clock_in) + begin + if (~reset_n_core_clock_in) + clk_h <= 1'b0; + else + clk_h <= 1'b1; + end + assign fr_os_hi = clk_h; + end else begin + assign fr_os_hi = 1'b1; + end + end + end + else + begin + if (USE_BIDIR_STROBE == "true") + begin + assign fr_os_oe = ~output_strobe_ena[0]; + + wire gnd_lut /* synthesis keep = 1*/; + assign gnd_lut = 1'b0; + assign fr_os_lo = gnd_lut; + + if (PREAMBLE_TYPE == "low") + begin + reg os_ena_reg1; + initial + os_ena_reg1 = 0; + always @(posedge core_clock_in) + os_ena_reg1 <= output_strobe_ena[0]; + + assign fr_os_hi = os_ena_reg1 & output_strobe_ena[0]; + end + else + begin + + wire vcc_lut /* synthesis keep = 1*/; + assign vcc_lut = 1'b1; + assign fr_os_hi = vcc_lut; + end + end + else + begin + wire gnd_lut /* synthesis keep = 1*/; + assign gnd_lut = 1'b0; + assign fr_os_lo = gnd_lut; + + assign fr_os_oe = 1'b0; + + if (USE_OUTPUT_STROBE_RESET == "true") begin + reg clk_h /* synthesis dont_merge */; + always @(posedge write_strobe_clock_in or negedge reset_n_core_clock_in) + begin + if (~reset_n_core_clock_in) + clk_h <= 1'b0; + else + clk_h <= 1'b1; + end + assign fr_os_hi = clk_h; + end else begin + assign fr_os_hi = 1'b1; + end + end + end + + if (USE_OUTPUT_PHASE_ALIGNMENT == "true") + begin + end + else + begin + + /* + cyclonev_ddio_oe + os_oe_ddio_oe ( + .clk (write_strobe_clock_in), + .oe (fr_os_oe), + .dataout (aligned_os_oe) + ); + */ + reg os_oe_reg; + always @(posedge write_strobe_clock) os_oe_reg <= fr_os_oe; + assign aligned_os_oe = os_oe_reg; + + cyclonev_ddio_out + #( + .half_rate_mode("false"), + .use_new_clocking_model("true"), + .async_mode("none") + ) phase_align_os ( + .datainhi(fr_os_hi), + .datainlo(fr_os_lo), + .dataout(aligned_strobe), + .clkhi (write_strobe_clock), + .clklo (write_strobe_clock), + .muxsel (write_strobe_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn(), + .hrbypass() + ); + end + + wire delayed_os_oe; + wire predelayed_os; + wire predelayed_os_oe; + + if (USE_2X_FF == "true") + begin + reg dd_os; + reg dd_os_oe; + always @(posedge dqs_dr_clock) + begin + dd_os <= aligned_strobe; + dd_os_oe <= aligned_os_oe; + end + assign predelayed_os = dd_os; + assign predelayed_os_oe = dd_os_oe; + end + else + begin + assign predelayed_os = aligned_strobe; + assign predelayed_os_oe = aligned_os_oe; + end + + if (USE_DYNAMIC_CONFIG == "true") + begin +`ifndef FAMILY_HAS_NO_DYNCONF + wire delayed_os_oe_1; + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + dqs_out_delay_1( + .datain (predelayed_os), + .delayctrlin (dqs_outputdelaysetting_dlc), + .dataout (os_delayed1) + ); + + assign os_delayed2 = os_delayed1; + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + oe_delay_1( + .datain (predelayed_os_oe), + .delayctrlin (dqs_outputenabledelaysetting_dlc), + .dataout (delayed_os_oe_1) + ); + + assign delayed_os_oe = delayed_os_oe_1; +`endif + end + else + begin + assign os_delayed2 = aligned_strobe; + assign delayed_os_oe = aligned_os_oe; + end + + wire diff_oe; + wire diff_oe_bar; + wire diff_dtc; + wire diff_dtc_bar; + + if (DIFFERENTIAL_OUTPUT_STROBE=="true") + begin + if (USE_BIDIR_STROBE == "true") + begin + cyclonev_pseudo_diff_out pseudo_diffa_0 + ( + .oein(delayed_os_oe), + .dtcin(delayed_oct), + .oeout(diff_oe), + .oebout(diff_oe_bar), + .dtc(diff_dtc), + .dtcbar(diff_dtc_bar), + .i(os_delayed2), + .o(os), + .obar(os_bar) + ); + + cyclonev_io_obuf + #( + .sim_dynamic_termination_control_is_connected("true"), + .bus_hold("false"), + .open_drain_output("false") + ) obuf_os_bar_0 + ( + .i(os_bar), + .o(strobe_n_io), + .obar(), + .oe(~diff_oe_bar), + .parallelterminationcontrol (parallelterminationcontrol_in), + .dynamicterminationcontrol (diff_dtc_bar), + .seriesterminationcontrol (seriesterminationcontrol_in), + .devoe() + ); + end + else + begin + cyclonev_pseudo_diff_out pseudo_diffa_0 + ( + .oein(1'b0), + .oeout(diff_oe), + .oebout(diff_oe_bar), + .i(os_delayed2), + .o(os), + .obar(os_bar), + .dtcin(), + .dtc(), + .dtcbar() + ); + + cyclonev_io_obuf + #( + .bus_hold("false"), + .open_drain_output("false") + ) obuf_os_bar_0 + ( + .i(os_bar), + .o(output_strobe_n_out), + .obar(), + .oe(~diff_oe_bar), + .dynamicterminationcontrol(1'b0), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .devoe() + ); + end + end + else + begin + assign os = os_delayed2; + assign diff_dtc = delayed_oct; + assign diff_oe = delayed_os_oe; + end + + + if (USE_BIDIR_STROBE == "true") + begin + cyclonev_io_obuf + #( + .sim_dynamic_termination_control_is_connected("true"), + .bus_hold("false"), + .open_drain_output("false") + ) obuf_os_0 + ( + .i(os), + .o(strobe_io), + .obar(), + .oe(~diff_oe), + .parallelterminationcontrol (parallelterminationcontrol_in), + .dynamicterminationcontrol (diff_dtc), + .seriesterminationcontrol (seriesterminationcontrol_in), + .devoe() + ); + end + else + begin + cyclonev_io_obuf + #( + .bus_hold("false"), + .open_drain_output("false") + ) obuf_os_0 + ( + .i(os), + .o(output_strobe_out), + .obar(), + .oe(~diff_oe), + .parallelterminationcontrol (), + .dynamicterminationcontrol (1'b0), + .seriesterminationcontrol (), + .devoe() + ); + + end +end +endgenerate + + +wire [PIN_WIDTH-1:0] aligned_oe ; +wire [PIN_WIDTH-1:0] aligned_data; +wire [PIN_WIDTH-1:0] ddr_data; +wire [PIN_WIDTH-1:0] dq_outputhalfratebypass; +wire [PIN_WIDTH*2-1:0] rfifo_clock_select; +wire [PIN_WIDTH*3-1:0] rfifo_mode; + + +generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin + genvar opin_num; + for (opin_num = 0; opin_num < PIN_WIDTH; opin_num = opin_num + 1) + begin :output_path_gen + wire fr_data_hi; + wire fr_data_lo; + wire fr_oe; + + if (USE_HALF_RATE_OUTPUT == "true") + begin + wire hr_data_t0; + wire hr_data_t1; + wire hr_data_t2; + wire hr_data_t3; + wire write_oe_hi; + wire write_oe_lo; + + if (NATURAL_ALIGNMENT == "true") + begin + assign hr_data_t0 = write_data_in [opin_num * rate_mult_out]; + assign hr_data_t1 = write_data_in [opin_num * rate_mult_out + 1]; + assign hr_data_t2 = write_data_in [opin_num * rate_mult_out + 2]; + assign hr_data_t3 = write_data_in [opin_num * rate_mult_out + 3]; + assign write_oe_hi = write_oe_in [2*opin_num + 0]; + assign write_oe_lo = write_oe_in [2*opin_num + 1]; + end + else if (REGULAR_WRITE_BUS_ORDERING == "true") + begin + assign hr_data_t0 = write_data_in [opin_num + 0*PIN_WIDTH]; + assign hr_data_t1 = write_data_in [opin_num + 1*PIN_WIDTH]; + assign hr_data_t2 = write_data_in [opin_num + 2*PIN_WIDTH]; + assign hr_data_t3 = write_data_in [opin_num + 3*PIN_WIDTH]; + assign write_oe_hi = write_oe_in [opin_num + 0]; + assign write_oe_lo = write_oe_in [opin_num + PIN_WIDTH]; + end + else + begin + assign hr_data_t0 = write_data_in [opin_num + 1*PIN_WIDTH]; + assign hr_data_t1 = write_data_in [opin_num + 0*PIN_WIDTH]; + assign hr_data_t2 = write_data_in [opin_num + 3*PIN_WIDTH]; + assign hr_data_t3 = write_data_in [opin_num + 2*PIN_WIDTH]; + assign write_oe_hi = write_oe_in [opin_num + 0]; + assign write_oe_lo = write_oe_in [opin_num + PIN_WIDTH]; + end + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_hi ( + .datainhi(hr_data_t0), + .datainlo(hr_data_t2), + .dataout(fr_data_hi), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dq_outputhalfratebypass[opin_num]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_lo ( + .datainhi(hr_data_t1), + .datainlo(hr_data_t3), + .dataout(fr_data_lo), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dq_outputhalfratebypass[opin_num]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true") + ) hr_to_fr_oe ( + .datainhi(~write_oe_hi), + .datainlo(~write_oe_lo), + .dataout(fr_oe), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(dq_outputhalfratebypass[opin_num]), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + end + else + begin + if (NATURAL_ALIGNMENT == "true") + begin + assign fr_data_lo = write_data_in [opin_num * rate_mult_out + 1]; + assign fr_data_hi = write_data_in [opin_num * rate_mult_out]; + end + else + begin + assign fr_data_lo = write_data_in [opin_num+PIN_WIDTH]; + assign fr_data_hi = write_data_in [opin_num]; + end + assign fr_oe = ~write_oe_in [opin_num]; + end + + if (USE_OUTPUT_PHASE_ALIGNMENT == "true") + begin + end + else + begin + cyclonev_ddio_out + #( + .async_mode("none"), + .half_rate_mode("false"), + .sync_mode("none"), + .use_new_clocking_model("true") + ) ddio_out ( + .datainhi(fr_data_hi), + .datainlo(fr_data_lo), + .dataout(aligned_data[opin_num]), + .clkhi (dq_shifted_clock), + .clklo (dq_shifted_clock), + .muxsel (dq_shifted_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn(), + .hrbypass() + ); + + + /* + cyclonev_ddio_oe + dq_oe_ddio_oe ( + .clk (fr_clock_in), + .oe (fr_oe), + .dataout (aligned_oe [opin_num]) + ); + */ + reg oe_reg /* synthesis dont_merge altera_attribute="FAST_OUTPUT_ENABLE_REGISTER=on" */; + always @(posedge dq_shifted_clock) oe_reg <= fr_oe; + assign aligned_oe[opin_num] = oe_reg; + end + end + end +endgenerate + + +generate +if (PIN_TYPE == "input" || PIN_TYPE == "bidir") +begin + genvar ipin_num; + for (ipin_num = 0; ipin_num < PIN_WIDTH; ipin_num = ipin_num + 1) + begin :input_path_gen + + wire [1:0] sdr_data; + wire [1:0] aligned_input; + wire dqsbusout_to_ddio_in; + wire dqsnbusout_to_ddio_in; + + if (INVERT_CAPTURE_STROBE == "true") begin + assign dqsbusout_to_ddio_in = ~dqsbusout; + if (SEPARATE_CAPTURE_STROBE == "true") begin + assign dqsnbusout_to_ddio_in = ~dqsnbusout; + end + end else begin + assign dqsbusout_to_ddio_in = dqsbusout; + if (SEPARATE_CAPTURE_STROBE == "true") begin + assign dqsnbusout_to_ddio_in = dqsnbusout; + end + end + + if (SEPARATE_CAPTURE_STROBE == "true") begin + cyclonev_ddio_in + #( + .use_clkn("true"), + .async_mode("none"), + .sync_mode("none") + ) capture_reg( + .datain(ddr_data[ipin_num]), + .clk (dqsbusout_to_ddio_in), + .clkn (dqsnbusout_to_ddio_in), + .regouthi(sdr_data[1]), + .regoutlo(sdr_data[0]), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .devpor(), + .devclrn() + ); + end else begin + cyclonev_ddio_in + #( + .use_clkn("false"), + .async_mode("none"), + .sync_mode("none") + ) capture_reg( + .datain(ddr_data[ipin_num]), + .clk (dqsbusout_to_ddio_in), + .regouthi(sdr_data[1]), + .regoutlo(sdr_data[0]), + .clkn(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .devpor(), + .devclrn() + ); + end + + if (USE_INPUT_PHASE_ALIGNMENT == "true") + begin + end + else + begin + assign aligned_input = sdr_data; + end + + wire [3:0] read_fifo_out; + if (USE_HARD_FIFOS == "true") + begin + wire wren; + if (USE_BIDIR_STROBE == "true") + begin + assign wren = 1'b1; + end + else + begin + assign wren = vfifo_capture_strobe_ena; + end + + wire rfifo_rd_clk; + if(USE_DYNAMIC_CONFIG == "true") begin + cyclonev_read_fifo_read_clock_select + read_fifo_clk_sel + ( + .clkin({hr_seq_clock, dqs_shifted_clock, 1'b0}), + .clksel(rfifo_clock_select[(ipin_num+1)*2-1:ipin_num*2]), + .clkout (rfifo_rd_clk) + ); + end + else begin + if (USE_HALF_RATE_OUTPUT == "true") begin + assign rfifo_rd_clk = hr_seq_clock; + end + else begin + assign rfifo_rd_clk = dqs_shifted_clock; + end + end + + wire writeclk; + + // in skip-cal mode, the read_fifo writeclk cannot be x otherwise we pick up an + // extra edge at the beginning and there is no calibration to reset things after the first edge + // synthesis translate_off + assign writeclk = (dqsbusout_to_ddio_in === 1'b0) ? 1'b0 : 1'b1; + // synthesis translate_on + // synthesis read_comments_as_HDL on + // assign writeclk = dqsbusout_to_ddio_in; + // synthesis read_comments_as_HDL off + + localparam READ_FIFO_MODE = (USE_HALF_RATE_OUTPUT == "true") ? "hrate_mode" : "frate_mode"; + + cyclonev_ir_fifo_userdes + read_fifo + ( + .rstn (rfifo_reset_n), + .dinfiforx (aligned_input), + .writeclk (writeclk), + .writeenable (wren), + .dout (read_fifo_out), + .readclk (rfifo_rd_clk), + .dynfifomode(rfifo_mode[(ipin_num+1)*3-1:ipin_num*3]), + .readenable(lfifo_rden), + .tstclk(), + .regscanovrd(), + .bslipin(), + .txin(), + .loaden(), + .bslipctl(), + .regscan(), + .scanin(), + .lvdsmodeen(), + .lvdstxsel(), + .txout(), + .rxout(), + .bslipout(), + .bslipmax(), + .scanout(), + .observableout(), + .observablefout1(), + .observablefout2(), + .observablefout3(), + .observablefout4(), + .observablewaddrcnt(), + .observableraddrcnt() + ); + defparam read_fifo.a_use_dynamic_fifo_mode = USE_DYNAMIC_CONFIG; + defparam read_fifo.a_rb_fifo_mode = READ_FIFO_MODE; + defparam read_fifo.a_sim_wclk_pre_delay = 10; + defparam read_fifo.a_sim_readenable_pre_delay = 10; + end + else + begin + assign read_fifo_out = aligned_input; + end + + if (REVERSE_READ_WORDS == "true") + begin + if (USE_HALF_RATE_OUTPUT == "true") + begin + assign read_data_out [ipin_num] = read_fifo_out [3]; + assign read_data_out [PIN_WIDTH +ipin_num] = read_fifo_out [2]; + assign read_data_out [PIN_WIDTH*2 +ipin_num] = read_fifo_out [1]; + assign read_data_out [PIN_WIDTH*3 +ipin_num] = read_fifo_out [0]; + end + else + begin + assign read_data_out [ipin_num] = read_fifo_out [1]; + assign read_data_out [PIN_WIDTH +ipin_num] = read_fifo_out [0]; + end + end + else if (NATURAL_ALIGNMENT == "true") + begin + assign read_data_out [ipin_num*rate_mult_out] = read_fifo_out [0]; + assign read_data_out [ipin_num*rate_mult_out + 1] = read_fifo_out [1]; + if (USE_HALF_RATE_OUTPUT == "true") + begin + assign read_data_out [ipin_num*rate_mult_out + 2] = read_fifo_out [2]; + assign read_data_out [ipin_num*rate_mult_out + 3] = read_fifo_out [3]; + end + end + else + begin + assign read_data_out [ipin_num] = read_fifo_out [0]; + assign read_data_out [PIN_WIDTH +ipin_num] = read_fifo_out [1]; + if (USE_HALF_RATE_OUTPUT == "true") + begin + assign read_data_out [PIN_WIDTH*2 +ipin_num] = read_fifo_out [2]; + assign read_data_out [PIN_WIDTH*3 +ipin_num] = read_fifo_out [3]; + end + end + end +end +endgenerate + +generate + genvar pin_num; + for (pin_num = 0; pin_num < PIN_WIDTH; pin_num = pin_num + 1) + begin :pad_gen + if (PIN_TYPE == "bidir") + begin + assign write_data_out [pin_num] = 1'b0; + end + else + begin + assign read_write_data_io [pin_num] = 1'b0; + end + + + wire delayed_data_in; + wire delayed_data_out; + wire delayed_oe; + wire [4:0] dq_outputdelaysetting; + wire [4:0] dq_outputenabledelaysetting; + wire [4:0] dq_inputdelaysetting; + + wire [DELAY_CHAIN_WIDTH-1:0] dq_outputdelaysetting_dlc; + wire [DELAY_CHAIN_WIDTH-1:0] dq_outputenabledelaysetting_dlc; + wire [DELAY_CHAIN_WIDTH-1:0] dq_inputdelaysetting_dlc; + + + if (USE_DYNAMIC_CONFIG == "true") + begin +`ifndef FAMILY_HAS_NO_DYNCONF + cyclonev_io_config config_1 ( + .datain(config_data_in), + .clk(config_clock_in), + .ena(config_io_ena[pin_num]), + .update(config_update), + + .outputregdelaysetting(dq_outputdelaysetting), + .outputenabledelaysetting(dq_outputenabledelaysetting), + .outputhalfratebypass(dq_outputhalfratebypass[pin_num]), + .readfiforeadclockselect(rfifo_clock_select[(pin_num+1)*2-1:pin_num*2]), + .readfifomode(rfifo_mode[(pin_num+1)*3-1:pin_num*3]), + + .padtoinputregisterdelaysetting(dq_inputdelaysetting), + .dataout() + ); +`endif + assign dq_outputdelaysetting_dlc = dq_outputdelaysetting; + assign dq_outputenabledelaysetting_dlc = dq_outputenabledelaysetting; + assign dq_inputdelaysetting_dlc = dq_inputdelaysetting; + end + + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin + wire raw_input; + if (USE_DYNAMIC_CONFIG == "true") + begin +`ifndef FAMILY_HAS_NO_DYNCONF + cyclonev_delay_chain in_delay_1( + .datain (raw_input), + .delayctrlin (dq_inputdelaysetting_dlc), + .dataout (ddr_data[pin_num]) + ); +`endif + end + else + begin + assign ddr_data[pin_num] = raw_input; + end + + if (PIN_TYPE == "bidir") + begin + cyclonev_io_ibuf data_in ( + .i(read_write_data_io[pin_num]), + .o(raw_input), + .ibar(), + .dynamicterminationcontrol(1'b0) + ); + end + else + begin + cyclonev_io_ibuf data_in ( + .i(read_data_in[pin_num]), + .o(raw_input), + .ibar(), + .dynamicterminationcontrol(1'b0) + ); + end + end + + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin + + wire predelayed_data; + wire predelayed_oe; + + if (USE_2X_FF == "true") + begin + reg dd_data; + reg dd_oe; + always @(posedge dq_dr_clock) + begin + dd_data <= aligned_data[pin_num]; + dd_oe <= aligned_oe[pin_num]; + end + assign predelayed_data = dd_data; + assign predelayed_oe = dd_oe; + end + else + begin + assign predelayed_data = aligned_data[pin_num]; + assign predelayed_oe = aligned_oe[pin_num]; + end + + if (USE_DYNAMIC_CONFIG == "true") + begin +`ifndef FAMILY_HAS_NO_DYNCONF + wire delayed_data_1; + wire delayed_oe_1; + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + out_delay_1( + .datain (predelayed_data), + .delayctrlin (dq_outputdelaysetting_dlc), + .dataout (delayed_data_1) + ); + + assign delayed_data_out = delayed_data_1; + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + oe_delay_1( + .datain (predelayed_oe), + .delayctrlin (dq_outputenabledelaysetting_dlc), + .dataout (delayed_oe_1) + ); + + assign delayed_oe = delayed_oe_1; + +`endif + end + else + begin + assign delayed_data_out = predelayed_data; + assign delayed_oe = predelayed_oe; + end + + if (PIN_TYPE == "output") + begin + cyclonev_io_obuf data_out ( + .i (delayed_data_out), + .o (write_data_out [pin_num]), + .oe (~delayed_oe), + .parallelterminationcontrol (parallelterminationcontrol_in), + .seriesterminationcontrol (seriesterminationcontrol_in), + .obar(), + .devoe(), + .dynamicterminationcontrol(1'b0) + ); + end + else if (PIN_TYPE == "bidir") + begin + cyclonev_io_obuf + #( + .sim_dynamic_termination_control_is_connected("true") + ) data_out ( + .oe (~delayed_oe), + .i (delayed_data_out), + .o (read_write_data_io [pin_num]), + .parallelterminationcontrol (parallelterminationcontrol_in), + .dynamicterminationcontrol (delayed_oct), + .seriesterminationcontrol (seriesterminationcontrol_in), + .obar(), + .devoe() + ); + + /* synthesis translate_off */ + + assert property (@(posedge fr_clock_in or negedge fr_clock_in) (~delayed_oe === 1'b1) |-> delayed_oct === 1'b0) + else $display(1, "OE enabled but dynamic OCT ctrl is not in write mode"); + +`ifndef BOARD_DELAY_MODEL + assert property (@(posedge capture_strobe or negedge capture_strobe) (~delayed_oe === 1'b0 && read_write_data_io[pin_num] !== 1'bz) |-> delayed_oct === 1'b1) + else $display(1, "Read data comes back but dynamic OCT ctrl is not in read mode"); +`endif + + /* synthesis translate_on */ + end + end + end +endgenerate + +generate + genvar epin_num; + for (epin_num = 0; epin_num < EXTRA_OUTPUT_WIDTH; epin_num = epin_num + 1) + begin :extra_output_pad_gen + wire fr_data_hi; + wire fr_data_lo; + wire aligned_data; + wire extra_outputhalfratebypass; + + if (USE_HALF_RATE_OUTPUT == "true") + begin + wire hr_data_t0; + wire hr_data_t1; + wire hr_data_t2; + wire hr_data_t3; + + if (NATURAL_ALIGNMENT == "true") + begin + assign hr_data_t0 = extra_write_data_in [epin_num * rate_mult_out]; + assign hr_data_t1 = extra_write_data_in [epin_num * rate_mult_out + 1]; + assign hr_data_t2 = extra_write_data_in [epin_num * rate_mult_out + 2]; + assign hr_data_t3 = extra_write_data_in [epin_num * rate_mult_out + 3]; + end + else if (REGULAR_WRITE_BUS_ORDERING == "true") + begin + assign hr_data_t0 = extra_write_data_in [epin_num + 0*EXTRA_OUTPUT_WIDTH]; + assign hr_data_t1 = extra_write_data_in [epin_num + 1*EXTRA_OUTPUT_WIDTH]; + assign hr_data_t2 = extra_write_data_in [epin_num + 2*EXTRA_OUTPUT_WIDTH]; + assign hr_data_t3 = extra_write_data_in [epin_num + 3*EXTRA_OUTPUT_WIDTH]; + end + else + begin + assign hr_data_t0 = extra_write_data_in [epin_num + 2*EXTRA_OUTPUT_WIDTH]; + assign hr_data_t1 = extra_write_data_in [epin_num + 0*EXTRA_OUTPUT_WIDTH]; + assign hr_data_t2 = extra_write_data_in [epin_num + 3*EXTRA_OUTPUT_WIDTH]; + assign hr_data_t3 = extra_write_data_in [epin_num + 1*EXTRA_OUTPUT_WIDTH]; + end + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_hi ( + .datainhi(hr_data_t0), + .datainlo(hr_data_t2), + .dataout(fr_data_hi), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(extra_outputhalfratebypass), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_lo ( + .datainhi(hr_data_t1), + .datainlo(hr_data_t3), + .dataout(fr_data_lo), + .clkhi (hr_seq_clock), + .clklo (hr_seq_clock), + .hrbypass(extra_outputhalfratebypass), + .muxsel (hr_seq_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn() + ); + end + else + begin + if (NATURAL_ALIGNMENT == "true") + begin + assign fr_data_lo = extra_write_data_in [epin_num * rate_mult_out + 1]; + assign fr_data_hi = extra_write_data_in [epin_num * rate_mult_out]; + end + else + begin + assign fr_data_lo = extra_write_data_in [epin_num+EXTRA_OUTPUT_WIDTH]; + assign fr_data_hi = extra_write_data_in [epin_num]; + end + end + + if (USE_OUTPUT_PHASE_ALIGNMENT == "true") + begin + end + else + begin + + cyclonev_ddio_out + #( + .async_mode("none"), + .half_rate_mode("false"), + .sync_mode("none"), + .use_new_clocking_model("true") + ) ddio_out ( + .datainhi(fr_data_hi), + .datainlo(fr_data_lo), + .dataout(aligned_data), + .clkhi (dq_shifted_clock), + .clklo (dq_shifted_clock), + .muxsel (dq_shifted_clock), + .clk(), + .ena(1'b1), + .areset(), + .sreset(), + .dfflo(), + .dffhi(), + .devpor(), + .devclrn(), + .hrbypass() + ); + end + + wire delayed_data_out; + wire [4:0] dq_outputdelaysetting1; + wire [4:0] dq_inputdelaysetting; + wire [DELAY_CHAIN_WIDTH-1:0] dq_outputdelaysetting1_dlc; + wire [DELAY_CHAIN_WIDTH-1:0] dq_inputdelaysetting_dlc; + + if (USE_DYNAMIC_CONFIG == "true") + begin +`ifndef FAMILY_HAS_NO_DYNCONF + cyclonev_io_config config_1 ( + .datain(config_data_in), + .clk(config_clock_in), + .ena(config_extra_io_ena[epin_num]), + .update(config_update), + + .outputregdelaysetting(dq_outputdelaysetting1), + .outputhalfratebypass(extra_outputhalfratebypass), + .padtoinputregisterdelaysetting(dq_inputdelaysetting), + .dataout(), + .readfiforeadclockselect(), + .readfifomode(), + .outputenabledelaysetting() + + ); + + assign dq_outputdelaysetting1_dlc = dq_outputdelaysetting1; + assign dq_inputdelaysetting_dlc = dq_inputdelaysetting; + + wire delayed_data_1; + + cyclonev_delay_chain + #(.sim_intrinsic_rising_delay(0), .sim_intrinsic_falling_delay(0)) + out_delay_1( + .datain (aligned_data), + .delayctrlin (dq_outputdelaysetting1_dlc), + .dataout (delayed_data_1) + ); + assign delayed_data_out = delayed_data_1; +`endif + end + else + begin + assign delayed_data_out = aligned_data; + end + cyclonev_io_obuf obuf_1 ( + .i (delayed_data_out), + .o (extra_write_data_out[epin_num]), + .parallelterminationcontrol(parallelterminationcontrol_in), + .dynamicterminationcontrol(1'b0), + .seriesterminationcontrol(seriesterminationcontrol_in), + .oe (1'b1), + .obar(), + .devoe() + ); + end +endgenerate +endmodule diff --git a/ip/altera/ddr3/altera_avalon_mm_bridge.v b/ip/altera/ddr3/altera_avalon_mm_bridge.v new file mode 100644 index 0000000..e566de9 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_mm_bridge.v @@ -0,0 +1,300 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ +// -------------------------------------- +// Avalon-MM pipeline bridge +// +// Optionally registers Avalon-MM command and response signals +// -------------------------------------- + +`timescale 1 ns / 1 ns +module altera_avalon_mm_bridge +#( + parameter DATA_WIDTH = 32, + parameter SYMBOL_WIDTH = 8, + parameter RESPONSE_WIDTH = 2, + parameter HDL_ADDR_WIDTH = 10, + parameter BURSTCOUNT_WIDTH = 1, + + parameter PIPELINE_COMMAND = 1, + parameter PIPELINE_RESPONSE = 1, + + // -------------------------------------- + // Derived parameters + // -------------------------------------- + parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH +) +( + input clk, + input reset, + + output s0_waitrequest, + output [DATA_WIDTH-1:0] s0_readdata, + output s0_readdatavalid, + output [RESPONSE_WIDTH-1:0] s0_response, + input [BURSTCOUNT_WIDTH-1:0] s0_burstcount, + input [DATA_WIDTH-1:0] s0_writedata, + input [HDL_ADDR_WIDTH-1:0] s0_address, + input s0_write, + input s0_read, + input [BYTEEN_WIDTH-1:0] s0_byteenable, + input s0_debugaccess, + + input m0_waitrequest, + input [DATA_WIDTH-1:0] m0_readdata, + input m0_readdatavalid, + input [RESPONSE_WIDTH-1:0] m0_response, + output [BURSTCOUNT_WIDTH-1:0] m0_burstcount, + output [DATA_WIDTH-1:0] m0_writedata, + output [HDL_ADDR_WIDTH-1:0] m0_address, + output m0_write, + output m0_read, + output [BYTEEN_WIDTH-1:0] m0_byteenable, + output m0_debugaccess +); + // -------------------------------------- + // Registers & signals + // -------------------------------------- + reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount; + reg [DATA_WIDTH-1:0] cmd_writedata; + reg [HDL_ADDR_WIDTH-1:0] cmd_address; + reg cmd_write; + reg cmd_read; + reg [BYTEEN_WIDTH-1:0] cmd_byteenable; + wire cmd_waitrequest; + reg cmd_debugaccess; + + reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount; + reg [DATA_WIDTH-1:0] wr_writedata; + reg [HDL_ADDR_WIDTH-1:0] wr_address; + reg wr_write; + reg wr_read; + reg [BYTEEN_WIDTH-1:0] wr_byteenable; + reg wr_debugaccess; + + reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount; + reg [DATA_WIDTH-1:0] wr_reg_writedata; + reg [HDL_ADDR_WIDTH-1:0] wr_reg_address; + reg wr_reg_write; + reg wr_reg_read; + reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable; + reg wr_reg_waitrequest; + reg wr_reg_debugaccess; + + reg use_reg; + wire wait_rise; + + reg [DATA_WIDTH-1:0] rsp_readdata; + reg rsp_readdatavalid; + reg [RESPONSE_WIDTH-1:0] rsp_response; + + // -------------------------------------- + // Command pipeline + // + // Registers all command signals, including waitrequest + // -------------------------------------- + generate if (PIPELINE_COMMAND == 1) begin + + // -------------------------------------- + // Waitrequest Pipeline Stage + // + // Output waitrequest is delayed by one cycle, which means + // that a master will see waitrequest assertions one cycle + // too late. + // + // Solution: buffer the command when waitrequest transitions + // from low->high. As an optimization, we can safely assume + // waitrequest is low by default because downstream logic + // in the bridge ensures this. + // + // Note: this implementation buffers idle cycles should + // waitrequest transition on such cycles. This is a potential + // cause for throughput loss, but ye olde pipeline bridge did + // the same for years and no one complained. Not buffering idle + // cycles costs logic on the waitrequest path. + // -------------------------------------- + assign s0_waitrequest = wr_reg_waitrequest; + assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest; + + always @(posedge clk, posedge reset) begin + if (reset) begin + wr_reg_waitrequest <= 1'b1; + // -------------------------------------- + // Bit of trickiness here, deserving of a long comment. + // + // On the first cycle after reset, the pass-through + // must not be used or downstream logic may sample + // the same command twice because of the delay in + // transmitting a falling waitrequest. + // + // Using the registered command works on the condition + // that downstream logic deasserts waitrequest + // immediately after reset, which is true of the + // next stage in this bridge. + // -------------------------------------- + use_reg <= 1'b1; + + wr_reg_burstcount <= 1'b1; + wr_reg_writedata <= 0; + wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}}; + wr_reg_address <= 0; + wr_reg_write <= 1'b0; + wr_reg_read <= 1'b0; + wr_reg_debugaccess <= 1'b0; + end else begin + wr_reg_waitrequest <= cmd_waitrequest; + + if (wait_rise) begin + wr_reg_writedata <= s0_writedata; + wr_reg_byteenable <= s0_byteenable; + wr_reg_address <= s0_address; + wr_reg_write <= s0_write; + wr_reg_read <= s0_read; + wr_reg_burstcount <= s0_burstcount; + wr_reg_debugaccess <= s0_debugaccess; + end + + // stop using the buffer when waitrequest is low + if (~cmd_waitrequest) + use_reg <= 1'b0; + else if (wait_rise) begin + use_reg <= 1'b1; + end + + end + end + + always @* begin + wr_burstcount = s0_burstcount; + wr_writedata = s0_writedata; + wr_address = s0_address; + wr_write = s0_write; + wr_read = s0_read; + wr_byteenable = s0_byteenable; + wr_debugaccess = s0_debugaccess; + + if (use_reg) begin + wr_burstcount = wr_reg_burstcount; + wr_writedata = wr_reg_writedata; + wr_address = wr_reg_address; + wr_write = wr_reg_write; + wr_read = wr_reg_read; + wr_byteenable = wr_reg_byteenable; + wr_debugaccess = wr_reg_debugaccess; + end + end + + // -------------------------------------- + // Master-Slave Signal Pipeline Stage + // + // One notable detail is that cmd_waitrequest is deasserted + // when this stage is idle. This allows us to make logic + // optimizations in the waitrequest pipeline stage. + // + // Also note that cmd_waitrequest is deasserted during reset, + // which is not spec-compliant, but is ok for an internal + // signal. + // -------------------------------------- + wire no_command; + assign no_command = ~(cmd_read || cmd_write); + assign cmd_waitrequest = m0_waitrequest & ~no_command; + + always @(posedge clk, posedge reset) begin + if (reset) begin + cmd_burstcount <= 1'b1; + cmd_writedata <= 0; + cmd_byteenable <= {BYTEEN_WIDTH{1'b1}}; + cmd_address <= 0; + cmd_write <= 1'b0; + cmd_read <= 1'b0; + cmd_debugaccess <= 1'b0; + end + else begin + if (~cmd_waitrequest) begin + cmd_writedata <= wr_writedata; + cmd_byteenable <= wr_byteenable; + cmd_address <= wr_address; + cmd_write <= wr_write; + cmd_read <= wr_read; + cmd_burstcount <= wr_burstcount; + cmd_debugaccess <= wr_debugaccess; + end + end + end + + end // conditional command pipeline + else begin + + assign s0_waitrequest = m0_waitrequest; + + always @* begin + cmd_burstcount = s0_burstcount; + cmd_writedata = s0_writedata; + cmd_address = s0_address; + cmd_write = s0_write; + cmd_read = s0_read; + cmd_byteenable = s0_byteenable; + cmd_debugaccess = s0_debugaccess; + end + + end + endgenerate + + assign m0_burstcount = cmd_burstcount; + assign m0_writedata = cmd_writedata; + assign m0_address = cmd_address; + assign m0_write = cmd_write; + assign m0_read = cmd_read; + assign m0_byteenable = cmd_byteenable; + assign m0_debugaccess = cmd_debugaccess; + + // -------------------------------------- + // Response pipeline + // + // Registers all response signals + // -------------------------------------- + generate if (PIPELINE_RESPONSE == 1) begin + + always @(posedge clk, posedge reset) begin + if (reset) begin + rsp_readdatavalid <= 1'b0; + rsp_readdata <= 0; + rsp_response <= 0; + end + else begin + rsp_readdatavalid <= m0_readdatavalid; + rsp_readdata <= m0_readdata; + rsp_response <= m0_response; + end + end + + end // conditional response pipeline + else begin + + always @* begin + rsp_readdatavalid = m0_readdatavalid; + rsp_readdata = m0_readdata; + rsp_response = m0_response; + end + end + endgenerate + + assign s0_readdatavalid = rsp_readdatavalid; + assign s0_readdata = rsp_readdata; + assign s0_response = rsp_response; + +endmodule diff --git a/ip/altera/ddr3/altera_avalon_packets_to_master.v b/ip/altera/ddr3/altera_avalon_packets_to_master.v new file mode 100644 index 0000000..4f61bbe --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_packets_to_master.v @@ -0,0 +1,1240 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// -------------------------------------------------------------------------------- +//| Avalon ST Packets to MM Master Transaction Component +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps +// -------------------------------------------------------------------------------- +//| Fast Transaction Master +// -------------------------------------------------------------------------------- +module altera_avalon_packets_to_master ( + // Interface: clk + input wire clk, + input wire reset_n, + // Interface: ST in + output wire in_ready, + input wire in_valid, + input wire [ 7: 0] in_data, + input wire in_startofpacket, + input wire in_endofpacket, + + // Interface: ST out + input wire out_ready, + output wire out_valid, + output wire [ 7: 0] out_data, + output wire out_startofpacket, + output wire out_endofpacket, + + // Interface: MM out + output wire [31: 0] address, + input wire [31: 0] readdata, + output wire read, + output wire write, + output wire [ 3: 0] byteenable, + output wire [31: 0] writedata, + input wire waitrequest, + input wire readdatavalid +); + + wire [ 35: 0] fifo_readdata; + wire fifo_read; + wire fifo_empty; + wire [ 35: 0] fifo_writedata; + wire fifo_write; + wire fifo_write_waitrequest; + + // --------------------------------------------------------------------- + //| Parameter Declarations + // --------------------------------------------------------------------- + parameter EXPORT_MASTER_SIGNALS = 0; + parameter FIFO_DEPTHS = 2; + parameter FIFO_WIDTHU = 1; + parameter FAST_VER = 0; + + generate + if (FAST_VER) begin + packets_to_fifo p2f ( + .clk (clk), + .reset_n (reset_n), + .in_ready (in_ready), + .in_valid (in_valid), + .in_data (in_data), + .in_startofpacket (in_startofpacket), + .in_endofpacket (in_endofpacket), + .address (address), + .readdata (readdata), + .read (read), + .write (write), + .byteenable (byteenable), + .writedata (writedata), + .waitrequest (waitrequest), + .readdatavalid (readdatavalid), + .fifo_writedata (fifo_writedata), + .fifo_write (fifo_write), + .fifo_write_waitrequest (fifo_write_waitrequest) + ); + + fifo_to_packet f2p ( + .clk (clk), + .reset_n (reset_n), + .out_ready (out_ready), + .out_valid (out_valid), + .out_data (out_data), + .out_startofpacket (out_startofpacket), + .out_endofpacket (out_endofpacket), + .fifo_readdata (fifo_readdata), + .fifo_read (fifo_read), + .fifo_empty (fifo_empty) + ); + + fifo_buffer #( + .FIFO_DEPTHS(FIFO_DEPTHS), + .FIFO_WIDTHU(FIFO_WIDTHU) + ) fb ( + .wrclock (clk), + .reset_n (reset_n), + .avalonmm_write_slave_writedata (fifo_writedata), + .avalonmm_write_slave_write (fifo_write), + .avalonmm_write_slave_waitrequest (fifo_write_waitrequest), + .avalonmm_read_slave_readdata (fifo_readdata), + .avalonmm_read_slave_read (fifo_read), + .avalonmm_read_slave_waitrequest (fifo_empty) + ); + end else begin + packets_to_master p2m ( + .clk (clk), + .reset_n (reset_n), + .in_ready (in_ready), + .in_valid (in_valid), + .in_data (in_data), + .in_startofpacket (in_startofpacket), + .in_endofpacket (in_endofpacket), + .address (address), + .readdata (readdata), + .read (read), + .write (write), + .byteenable (byteenable), + .writedata (writedata), + .waitrequest (waitrequest), + .readdatavalid (readdatavalid), + .out_ready (out_ready), + .out_valid (out_valid), + .out_data (out_data), + .out_startofpacket (out_startofpacket), + .out_endofpacket (out_endofpacket) + ); + end + endgenerate +endmodule + +module packets_to_fifo ( + + // Interface: clk + input clk, + input reset_n, + // Interface: ST in + output reg in_ready, + input in_valid, + input [ 7: 0] in_data, + input in_startofpacket, + input in_endofpacket, + + // Interface: MM out + output reg [31: 0] address, + input [31: 0] readdata, + output reg read, + output reg write, + output reg [ 3: 0] byteenable, + output reg [31: 0] writedata, + input waitrequest, + input readdatavalid, + + // Interface: FIFO + // FIFO data format: + // | sop, eop, [1:0]valid, [31:0]data | + output reg [ 35: 0] fifo_writedata, + output reg fifo_write, + input wire fifo_write_waitrequest +); + + // --------------------------------------------------------------------- + //| Command Declarations + // --------------------------------------------------------------------- + localparam CMD_WRITE_NON_INCR = 8'h00; + localparam CMD_WRITE_INCR = 8'h04; + localparam CMD_READ_NON_INCR = 8'h10; + localparam CMD_READ_INCR = 8'h14; + + // --------------------------------------------------------------------- + //| Signal Declarations + // --------------------------------------------------------------------- + + reg [ 3: 0] state; + reg [ 7: 0] command; + reg [ 1: 0] current_byte, byte_avail; + reg [ 15: 0] counter; + reg [ 31: 0] read_data_buffer; + reg [ 31: 0] fifo_data_buffer; + reg in_ready_0; + reg first_trans, last_trans, fifo_sop; + reg [ 3: 0] unshifted_byteenable; + wire enable; + + localparam READY = 4'b0000, + GET_EXTRA = 4'b0001, + GET_SIZE1 = 4'b0010, + GET_SIZE2 = 4'b0011, + GET_ADDR1 = 4'b0100, + GET_ADDR2 = 4'b0101, + GET_ADDR3 = 4'b0110, + GET_ADDR4 = 4'b0111, + GET_WRITE_DATA = 4'b1000, + WRITE_WAIT = 4'b1001, + READ_ASSERT = 4'b1010, + READ_CMD_WAIT = 4'b1011, + READ_DATA_WAIT = 4'b1100, + PUSH_FIFO = 4'b1101, + PUSH_FIFO_WAIT = 4'b1110, + FIFO_CMD_WAIT = 4'b1111; + // --------------------------------------------------------------------- + //| Thingofamagick + // --------------------------------------------------------------------- + + assign enable = (in_ready & in_valid); + + always @* begin + in_ready = in_ready_0; + end + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + in_ready_0 <= 1'b0; + fifo_writedata <= 'b0; + fifo_write <= 1'b0; + fifo_sop <= 1'b0; + read <= 1'b0; + write <= 1'b0; + byteenable <= 'b0; + writedata <= 'b0; + address <= 'b0; + counter <= 'b0; + command <= 'b0; + first_trans <= 1'b0; + last_trans <= 1'b0; + state <= 'b0; + current_byte <= 'b0; + read_data_buffer <= 'b0; + unshifted_byteenable <= 'b0; + byte_avail <= 'b0; + fifo_data_buffer <= 'b0; + end else begin + address[1:0] <= 'b0; + in_ready_0 <= 1'b0; + + if (counter > 3) unshifted_byteenable <= 4'b1111; + else if (counter == 3) unshifted_byteenable <= 4'b0111; + else if (counter == 2) unshifted_byteenable <= 4'b0011; + else if (counter == 1) unshifted_byteenable <= 4'b0001; + + case (state) + READY : begin + in_ready_0 <= !fifo_write_waitrequest; + fifo_write <= 1'b0; + end + GET_EXTRA : begin + in_ready_0 <= 1'b1; + byteenable <= 'b0; + if (enable) state <= GET_SIZE1; + end + + GET_SIZE1 : begin + in_ready_0 <= 1'b1; + //load counter on reads only + counter[15:8] <= command[4]?in_data:8'b0; + if (enable) state <= GET_SIZE2; + end + + GET_SIZE2 : begin + in_ready_0 <= 1'b1; + //load counter on reads only + counter[7:0] <= command[4]?in_data:8'b0; + if (enable) state <= GET_ADDR1; + end + + GET_ADDR1 : begin + in_ready_0 <= 1'b1; + first_trans <= 1'b1; + last_trans <= 1'b0; + address[31:24] <= in_data; + if (enable) state <= GET_ADDR2; + end + + GET_ADDR2 : begin + in_ready_0 <= 1'b1; + address[23:16] <= in_data; + if (enable) state <= GET_ADDR3; + end + + GET_ADDR3 : begin + in_ready_0 <= 1'b1; + address[15:8] <= in_data; + if (enable) state <= GET_ADDR4; + end + + GET_ADDR4 : begin + in_ready_0 <= 1'b1; + address[7:2] <= in_data[7:2]; + current_byte <= in_data[1:0]; + if (enable) begin + if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin + state <= GET_WRITE_DATA; //writes + in_ready_0 <= 1'b1; + end + else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin + state <= READ_ASSERT; //reads + in_ready_0 <= 1'b0; + end + else begin + //nops + //treat all unrecognized commands as nops as well + in_ready_0 <= 1'b0; + state <= FIFO_CMD_WAIT; + //| sop, eop, [1:0]valid, [31:0]data | + //| 1 , 1 , 2'b11 ,{counter,reserved_byte}| + fifo_writedata[7:0] <= (8'h80 | command); + fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0}; + fifo_write <= 1'b1; + counter <= 0; + end + end + end + + GET_WRITE_DATA : begin + in_ready_0 <= 1'b1; + if (enable) begin + counter <= counter + 1'b1; + //2 bit, should wrap by itself + current_byte <= current_byte + 1'b1; + if (in_endofpacket || current_byte == 3) + begin + in_ready_0 <= 1'b0; + write <= 1'b1; + state <= WRITE_WAIT; + end + end + if (in_endofpacket) begin + last_trans <= 1'b1; + end + // handle byte writes properly + // drive data pins based on addresses + case (current_byte) + 0: begin + writedata[7:0] <= in_data; + byteenable[0] <= 1'b1; + end + 1: begin + writedata[15:8] <= in_data; + byteenable[1] <= 1'b1; + end + 2: begin + writedata[23:16] <= in_data; + byteenable[2] <= 1'b1; + end + 3: begin + writedata[31:24] <= in_data; + byteenable[3] <= 1'b1; + end + endcase + end + WRITE_WAIT : begin + in_ready_0 <= 1'b0; + write <= 1'b1; + if (~waitrequest) begin + write <= 1'b0; + state <= GET_WRITE_DATA; + in_ready_0 <= 1'b1; + byteenable <= 'b0; + if (command[2] == 1'b1) begin + //increment address, but word-align it + address[31:2] <= (address[31:2] + 1'b1); + end + if (last_trans) begin + in_ready_0 <= 1'b0; + state <= FIFO_CMD_WAIT; + //| sop, eop, [1:0]valid, [31:0]data | + //| 1 , 1 , 2'b11 ,{counter,reserved_byte}| + fifo_writedata[7:0] <= (8'h80 | command); + fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0}; + fifo_write <= 1'b1; + counter <= 0; + end + end + end + READ_ASSERT : begin + if (current_byte == 3) byteenable <= unshifted_byteenable << 3; + if (current_byte == 2) byteenable <= unshifted_byteenable << 2; + if (current_byte == 1) byteenable <= unshifted_byteenable << 1; + if (current_byte == 0) byteenable <= unshifted_byteenable; + read <= 1'b1; + fifo_write <= 1'b0; + state <= READ_CMD_WAIT; + end + READ_CMD_WAIT : begin + // number of valid byte + case (byteenable) + 4'b0000 : byte_avail <= 1'b0; + 4'b0001 : byte_avail <= 1'b0; + 4'b0010 : byte_avail <= 1'b0; + 4'b0100 : byte_avail <= 1'b0; + 4'b1000 : byte_avail <= 1'b0; + 4'b0011 : byte_avail <= 1'b1; + 4'b0110 : byte_avail <= 1'b1; + 4'b1100 : byte_avail <= 1'b1; + 4'b0111 : byte_avail <= 2'h2; + 4'b1110 : byte_avail <= 2'h2; + default : byte_avail <= 2'h3; + endcase + read_data_buffer <= readdata; + read <= 1; + // if readdatavalid, take the data and + // go directly to READ_SEND_ISSUE. This is for fixed + // latency slaves. Ignore waitrequest in this case, + // since this master does not issue pipelined reads. + // + // For variable latency slaves, once waitrequest is low + // the read command is accepted, so deassert read and + // go to READ_DATA_WAIT to wait for readdatavalid + if (readdatavalid) begin + state <= PUSH_FIFO; + read <= 0; + end else begin + if (~waitrequest) begin + state <= READ_DATA_WAIT; + read <= 0; + end + end + end + READ_DATA_WAIT : begin + read_data_buffer <= readdata; + if (readdatavalid) begin + state <= PUSH_FIFO; + end + end + PUSH_FIFO : begin + fifo_write <= 1'b0; + fifo_sop <= 1'b0; + if (first_trans) begin + first_trans <= 1'b0; + fifo_sop <= 1'b1; + end + case (current_byte) + 3 : begin + fifo_data_buffer <= read_data_buffer >> 24; + counter <= counter - 1'b1; + end + 2 : begin + fifo_data_buffer <= read_data_buffer >> 16; + if (counter == 1) counter <= 0; + else counter <= counter - 2'h2; + end + 1 : begin + fifo_data_buffer <= read_data_buffer >> 8; + if (counter < 3) counter <= 0; + else counter <= counter - 2'h3; + end + default : begin + fifo_data_buffer <= read_data_buffer; + if (counter < 4) counter <= 0; + else counter <= counter - 3'h4; + end + endcase + current_byte <= 0; + state <= PUSH_FIFO_WAIT; + end + PUSH_FIFO_WAIT : begin + // pushd return packet with data + fifo_write <= 1'b1; + fifo_writedata <= {fifo_sop,(counter == 0)?1'b1:1'b0,byte_avail,fifo_data_buffer}; + // count down on the number of bytes to read + // shift current byte location within word + // if increment address, add it, so the next read + // can use it, if more reads are required + + // no more bytes to send - go to READY state + if (counter == 0) begin + state <= FIFO_CMD_WAIT; + end else if (command[2]== 1'b1) begin + //increment address, but word-align it + state <= FIFO_CMD_WAIT; + address[31:2] <= (address[31:2] + 1'b1); + end + end + FIFO_CMD_WAIT : begin + // back pressure if fifo_write_waitrequest + if (!fifo_write_waitrequest) begin + if (counter == 0) begin + state <= READY; + end else begin + state <= READ_ASSERT; + end + fifo_write <= 1'b0; + end + end + endcase + if (enable & in_startofpacket) begin + state <= GET_EXTRA; + command <= in_data; + in_ready_0 <= !fifo_write_waitrequest; + end + end // end else + end // end always block +endmodule + +// -------------------------------------------------------------------------------- +// FIFO buffer +// -------------------------------------------------------------------------------- +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module fifo_buffer_single_clock_fifo ( + // inputs: + aclr, + clock, + data, + rdreq, + wrreq, + + // outputs: + empty, + full, + q + ) +; + + parameter FIFO_DEPTHS = 2; + parameter FIFO_WIDTHU = 1; + + output empty; + output full; + output [ 35: 0] q; + input aclr; + input clock; + input [ 35: 0] data; + input rdreq; + input wrreq; + + wire empty; + wire full; + wire [ 35: 0] q; + scfifo single_clock_fifo + ( + .aclr (aclr), + .clock (clock), + .data (data), + .empty (empty), + .full (full), + .q (q), + .rdreq (rdreq), + .wrreq (wrreq) + ); + + defparam single_clock_fifo.add_ram_output_register = "OFF", + single_clock_fifo.lpm_numwords = FIFO_DEPTHS, + single_clock_fifo.lpm_showahead = "OFF", + single_clock_fifo.lpm_type = "scfifo", + single_clock_fifo.lpm_width = 36, + single_clock_fifo.lpm_widthu = FIFO_WIDTHU, + single_clock_fifo.overflow_checking = "ON", + single_clock_fifo.underflow_checking = "ON", + single_clock_fifo.use_eab = "OFF"; + + +endmodule + + + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module fifo_buffer_scfifo_with_controls ( + // inputs: + clock, + data, + rdreq, + reset_n, + wrreq, + + // outputs: + empty, + full, + q + ) +; + + parameter FIFO_DEPTHS = 2; + parameter FIFO_WIDTHU = 1; + + output empty; + output full; + output [ 35: 0] q; + input clock; + input [ 35: 0] data; + input rdreq; + input reset_n; + input wrreq; + + wire empty; + wire full; + wire [ 35: 0] q; + wire wrreq_valid; + //the_scfifo, which is an e_instance + fifo_buffer_single_clock_fifo #( + .FIFO_DEPTHS(FIFO_DEPTHS), + .FIFO_WIDTHU(FIFO_WIDTHU) + ) the_scfifo ( + .aclr (~reset_n), + .clock (clock), + .data (data), + .empty (empty), + .full (full), + .q (q), + .rdreq (rdreq), + .wrreq (wrreq_valid) + ); + + assign wrreq_valid = wrreq & ~full; + +endmodule + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module fifo_buffer ( + // inputs: + avalonmm_read_slave_read, + avalonmm_write_slave_write, + avalonmm_write_slave_writedata, + reset_n, + wrclock, + + // outputs: + avalonmm_read_slave_readdata, + avalonmm_read_slave_waitrequest, + avalonmm_write_slave_waitrequest + ) +; + + parameter FIFO_DEPTHS = 2; + parameter FIFO_WIDTHU = 1; + + + output [ 35: 0] avalonmm_read_slave_readdata; + output avalonmm_read_slave_waitrequest; + output avalonmm_write_slave_waitrequest; + input avalonmm_read_slave_read; + input avalonmm_write_slave_write; + input [ 35: 0] avalonmm_write_slave_writedata; + input reset_n; + input wrclock; + + wire [ 35: 0] avalonmm_read_slave_readdata; + wire avalonmm_read_slave_waitrequest; + wire avalonmm_write_slave_waitrequest; + wire clock; + wire [ 35: 0] data; + wire empty; + wire full; + wire [ 35: 0] q; + wire rdreq; + wire wrreq; + //the_scfifo_with_controls, which is an e_instance + fifo_buffer_scfifo_with_controls #( + .FIFO_DEPTHS(FIFO_DEPTHS), + .FIFO_WIDTHU(FIFO_WIDTHU) + ) the_scfifo_with_controls + ( + .clock (clock), + .data (data), + .empty (empty), + .full (full), + .q (q), + .rdreq (rdreq), + .reset_n (reset_n), + .wrreq (wrreq) + ); + + //in, which is an e_avalon_slave + //out, which is an e_avalon_slave + assign data = avalonmm_write_slave_writedata; + assign wrreq = avalonmm_write_slave_write; + assign avalonmm_read_slave_readdata = q; + assign rdreq = avalonmm_read_slave_read; + assign clock = wrclock; + assign avalonmm_write_slave_waitrequest = full; + assign avalonmm_read_slave_waitrequest = empty; + +endmodule + +// -------------------------------------------------------------------------------- +// fifo_buffer to Avalon-ST interface +// -------------------------------------------------------------------------------- + +module fifo_to_packet ( + + // Interface: clk + input clk, + input reset_n, + + // Interface: ST out + input out_ready, + output reg out_valid, + output reg [ 7: 0] out_data, + output reg out_startofpacket, + output reg out_endofpacket, + + // Interface: FIFO in + input [ 35: 0] fifo_readdata, + output reg fifo_read, + input fifo_empty +); + +reg [ 1: 0] state; +reg enable, sent_all; +reg [ 1: 0] current_byte, byte_end; +reg first_trans, last_trans; +reg [ 23:0] fifo_data_buffer; + +localparam POP_FIFO = 2'b00, + POP_FIFO_WAIT = 2'b01, + FIFO_DATA_WAIT = 2'b10, + READ_SEND_ISSUE = 2'b11; + +always @* begin + enable = (!fifo_empty & sent_all); +end + +always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + fifo_data_buffer <= 'b0; + out_startofpacket <= 1'b0; + out_endofpacket <= 1'b0; + out_valid <= 1'b0; + out_data <= 'b0; + state <= 'b0; + fifo_read <= 1'b0; + current_byte <= 'b0; + byte_end <= 'b0; + first_trans <= 1'b0; + last_trans <= 1'b0; + sent_all <= 1'b1; + end else begin + if (out_ready) begin + out_startofpacket <= 1'b0; + out_endofpacket <= 1'b0; + end + + case (state) + POP_FIFO : begin + if (out_ready) begin + out_startofpacket <= 1'b0; + out_endofpacket <= 1'b0; + out_valid <= 1'b0; + first_trans <= 1'b0; + last_trans <= 1'b0; + byte_end <= 'b0; + fifo_read <= 1'b0; + sent_all <= 1'b1; + end + // start poping fifo after all data sent and data available + if (enable) begin + fifo_read <= 1'b1; + out_valid <= 1'b0; + state <= POP_FIFO_WAIT; + end + end + POP_FIFO_WAIT : begin + //fifo latency of 1 + fifo_read <= 1'b0; + state <= FIFO_DATA_WAIT; + end + FIFO_DATA_WAIT : begin + sent_all <= 1'b0; + first_trans <= fifo_readdata[35]; + last_trans <= fifo_readdata[34]; + out_data <= fifo_readdata[7:0]; + fifo_data_buffer <= fifo_readdata[31:8]; + byte_end <= fifo_readdata[33:32]; + current_byte <= 1'b1; + out_valid <= 1'b1; + + // first byte sop eop handling + if (fifo_readdata[35] & fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin + first_trans <= 1'b0; + last_trans <= 1'b0; + out_startofpacket <= 1'b1; + out_endofpacket <= 1'b1; + state <= POP_FIFO; + end else if (fifo_readdata[35] & (fifo_readdata[33:32] == 0)) begin + first_trans <= 1'b0; + out_startofpacket <= 1'b1; + state <= POP_FIFO; + end else if (fifo_readdata[35]) begin + first_trans <= 1'b0; + out_startofpacket <= 1'b1; + state <= READ_SEND_ISSUE; + end else if (fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin + last_trans <= 1'b0; + out_endofpacket <= 1'b1; + state <= POP_FIFO; + end else begin + state <= READ_SEND_ISSUE; + end + + end + READ_SEND_ISSUE : begin + out_valid <= 1'b1; + sent_all <= 1'b0; + + if (out_ready) begin + out_startofpacket <= 1'b0; + // last byte + if (last_trans & (current_byte == byte_end)) begin + last_trans <= 1'b0; + out_endofpacket <= 1'b1; + state <= POP_FIFO; + end + case (current_byte) + 3: begin + out_data <= fifo_data_buffer[23:16]; + end + 2: begin + out_data <= fifo_data_buffer[15:8]; + end + 1: begin + out_data <= fifo_data_buffer[7:0]; + end + default: begin + //out_data <= fifo_readdata[7:0]; + end + endcase + current_byte <= current_byte + 1'b1; + if (current_byte == byte_end) begin + state <= POP_FIFO; + end else begin + state <= READ_SEND_ISSUE; + end + end + end + endcase + end + end +endmodule + +// -------------------------------------------------------------------------------- +//| Economy Transaction Master +// -------------------------------------------------------------------------------- +module packets_to_master ( + + // Interface: clk + input clk, + input reset_n, + // Interface: ST in + output reg in_ready, + input in_valid, + input [ 7: 0] in_data, + input in_startofpacket, + input in_endofpacket, + + // Interface: ST out + input out_ready, + output reg out_valid, + output reg [ 7: 0] out_data, + output reg out_startofpacket, + output reg out_endofpacket, + + // Interface: MM out + output reg [31: 0] address, + input [31: 0] readdata, + output reg read, + output reg write, + output reg [ 3: 0] byteenable, + output reg [31: 0] writedata, + input waitrequest, + input readdatavalid + +); + + // --------------------------------------------------------------------- + //| Parameter Declarations + // --------------------------------------------------------------------- + parameter EXPORT_MASTER_SIGNALS = 0; + + // --------------------------------------------------------------------- + //| Command Declarations + // --------------------------------------------------------------------- + localparam CMD_WRITE_NON_INCR = 8'h00; + localparam CMD_WRITE_INCR = 8'h04; + localparam CMD_READ_NON_INCR = 8'h10; + localparam CMD_READ_INCR = 8'h14; + + // --------------------------------------------------------------------- + //| Signal Declarations + // --------------------------------------------------------------------- + + reg [ 3: 0] state; + reg [ 7: 0] command; + reg [ 1: 0] current_byte; //, result_byte; + reg [ 15: 0] counter; + reg [ 23: 0] read_data_buffer; + reg in_ready_0; + reg first_trans, last_trans; + reg [ 3: 0] unshifted_byteenable; + wire enable; + + localparam READY = 4'b0000, + GET_EXTRA = 4'b0001, + GET_SIZE1 = 4'b0010, + GET_SIZE2 = 4'b0011, + GET_ADDR1 = 4'b0100, + GET_ADDR2 = 4'b0101, + GET_ADDR3 = 4'b0110, + GET_ADDR4 = 4'b0111, + GET_WRITE_DATA = 4'b1000, + WRITE_WAIT = 4'b1001, + RETURN_PACKET = 4'b1010, + READ_ASSERT = 4'b1011, + READ_CMD_WAIT = 4'b1100, + READ_DATA_WAIT = 4'b1101, + READ_SEND_ISSUE= 4'b1110, + READ_SEND_WAIT = 4'b1111; + + + // --------------------------------------------------------------------- + //| Thingofamagick + // --------------------------------------------------------------------- + + assign enable = (in_ready & in_valid); + + always @* +// in_ready = in_ready_0 & out_ready; + in_ready = in_ready_0; + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + in_ready_0 <= 1'b0; + out_startofpacket <= 1'b0; + out_endofpacket <= 1'b0; + out_valid <= 1'b0; + out_data <= 'b0; + read <= 1'b0; + write <= 1'b0; + byteenable <= 'b0; + writedata <= 'b0; + address <= 'b0; + counter <= 'b0; + command <= 'b0; + first_trans <= 1'b0; + last_trans <= 1'b0; + state <= 'b0; + current_byte <= 'b0; + // result_byte <= 'b0; + read_data_buffer <= 'b0; + unshifted_byteenable <= 'b0; + end else begin + address[1:0] <= 'b0; + + if (out_ready) begin + out_startofpacket <= 1'b0; + out_endofpacket <= 1'b0; + out_valid <= 1'b0; + end + in_ready_0 <= 1'b0; + + if (counter >= 3) unshifted_byteenable <= 4'b1111; + else if (counter == 3) unshifted_byteenable <= 4'b0111; + else if (counter == 2) unshifted_byteenable <= 4'b0011; + else if (counter == 1) unshifted_byteenable <= 4'b0001; + + case (state) + READY : begin + out_valid <= 1'b0; + in_ready_0 <= 1'b1; + end + GET_EXTRA : begin + in_ready_0 <= 1'b1; + byteenable <= 'b0; + if (enable) state <= GET_SIZE1; + end + + GET_SIZE1 : begin + in_ready_0 <= 1'b1; + //load counter on reads only + counter[15:8] <= command[4]?in_data:8'b0; + if (enable) state <= GET_SIZE2; + end + + GET_SIZE2 : begin + in_ready_0 <= 1'b1; + //load counter on reads only + counter[7:0] <= command[4]?in_data:8'b0; + if (enable) state <= GET_ADDR1; + end + + GET_ADDR1 : begin + in_ready_0 <= 1'b1; + first_trans <= 1'b1; + last_trans <= 1'b0; + address[31:24] <= in_data; + if (enable) state <= GET_ADDR2; + end + + GET_ADDR2 : begin + in_ready_0 <= 1'b1; + address[23:16] <= in_data; + if (enable) state <= GET_ADDR3; + end + + GET_ADDR3 : begin + in_ready_0 <= 1'b1; + address[15:8] <= in_data; + if (enable) state <= GET_ADDR4; + end + + GET_ADDR4 : begin + in_ready_0 <= 1'b1; + address[7:2] <= in_data[7:2]; + current_byte <= in_data[1:0]; + if (enable) begin + if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin + state <= GET_WRITE_DATA; //writes + in_ready_0 <= 1'b1; + end + else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin + state <= READ_ASSERT; //reads + in_ready_0 <= 1'b0; + end + else begin + //nops + //treat all unrecognized commands as nops as well + state <= RETURN_PACKET; + out_startofpacket <= 1'b1; + out_data <= (8'h80 | command); + out_valid <= 1'b1; + current_byte <= 'h0; + in_ready_0 <= 1'b0; + end + end + end + + GET_WRITE_DATA : begin + in_ready_0 <= 1; + if (enable) begin + counter <= counter + 1'b1; + //2 bit, should wrap by itself + current_byte <= current_byte + 1'b1; + if (in_endofpacket || current_byte == 3) + begin + in_ready_0 <= 0; + write <= 1'b1; + state <= WRITE_WAIT; + end + end + if (in_endofpacket) begin + last_trans <= 1'b1; + end + // handle byte writes properly + // drive data pins based on addresses + case (current_byte) + 0: begin + writedata[7:0] <= in_data; + byteenable[0] <= 1; + end + 1: begin + writedata[15:8] <= in_data; + byteenable[1] <= 1; + end + 2: begin + writedata[23:16] <= in_data; + byteenable[2] <= 1; + end + 3: begin + writedata[31:24] <= in_data; + byteenable[3] <= 1; + end + endcase + end + + WRITE_WAIT : begin + in_ready_0 <= 0; + write <= 1'b1; + if (~waitrequest) begin + write <= 1'b0; + state <= GET_WRITE_DATA; + in_ready_0 <= 1; + byteenable <= 'b0; + if (command[2] == 1'b1) begin + //increment address, but word-align it + address[31:2] <= (address[31:2] + 1'b1); + end + if (last_trans) begin + state <= RETURN_PACKET; + out_startofpacket <= 1'b1; + out_data <= (8'h80 | command); + out_valid <= 1'b1; + current_byte <= 'h0; + in_ready_0 <= 1'b0; + end + end + end + + RETURN_PACKET : begin + out_valid <= 1'b1; + if (out_ready) begin + case (current_byte) + // 0: begin + // out_startofpacket <= 1'b1; + // out_data <= (8'h80 | command); + // end + 0: begin + out_data <= 8'b0; + end + 1: begin + out_data <= counter[15:8]; + end + 2: begin + out_endofpacket <= 1'b1; + out_data <= counter[7:0]; + end + default: begin + // out_data <= 8'b0; + // out_startofpacket <= 1'b0; + // out_endofpacket <= 1'b0; + end + endcase + current_byte <= current_byte + 1'b1; + if (current_byte == 3) begin + state <= READY; + out_valid <= 1'b0; + end + else state <= RETURN_PACKET; + end + end + READ_ASSERT : begin + if (current_byte == 3) byteenable <= unshifted_byteenable << 3; + if (current_byte == 2) byteenable <= unshifted_byteenable << 2; + if (current_byte == 1) byteenable <= unshifted_byteenable << 1; + if (current_byte == 0) byteenable <= unshifted_byteenable; +// byteenable <= unshifted_byteenable << current_byte; + read <= 1; + state <= READ_CMD_WAIT; + end + READ_CMD_WAIT : begin + read_data_buffer <= readdata[31:8]; + out_data <= readdata[7:0]; + read <= 1; + // if readdatavalid, take the data and + // go directly to READ_SEND_ISSUE. This is for fixed + // latency slaves. Ignore waitrequest in this case, + // since this master does not issue pipelined reads. + // + // For variable latency slaves, once waitrequest is low + // the read command is accepted, so deassert read and + // go to READ_DATA_WAIT to wait for readdatavalid + if (readdatavalid) begin + state <= READ_SEND_ISSUE; + read <= 0; + end else begin + if (~waitrequest) begin + state <= READ_DATA_WAIT; + read <= 0; + end + end + end + READ_DATA_WAIT : begin + read_data_buffer <= readdata[31:8]; + out_data <= readdata[7:0]; + if (readdatavalid) begin + state <= READ_SEND_ISSUE; + end + end + READ_SEND_ISSUE : begin + out_valid <= 1'b1; + out_startofpacket <= 'h0; + out_endofpacket <= 'h0; + if (counter == 1) begin + out_endofpacket <= 1'b1; + end + if (first_trans) begin + first_trans <= 1'b0; + out_startofpacket <= 1'b1; + end + case (current_byte) + 3: begin + out_data <= read_data_buffer[23:16]; + end + 2: begin + out_data <= read_data_buffer[15:8]; + end + 1: begin + out_data <= read_data_buffer[7:0]; + end + default: begin + out_data <= out_data; + end + endcase + state <= READ_SEND_WAIT; + end + READ_SEND_WAIT : begin + out_valid <= 1'b1; + if (out_ready) begin + counter <= counter - 1'b1; + current_byte <= current_byte + 1'b1; + out_valid <= 1'b0; + // count down on the number of bytes to read + // shift current byte location within word + // if increment address, add it, so the next read + // can use it, if more reads are required + + // no more bytes to send - go to READY state + if (counter == 1) begin + state <= READY; + // end of current word, but we have more bytes to + // read - go back to READ_ASSERT + end else if (current_byte == 3) begin + if (command[2] == 1'b1) begin + //increment address, but word-align it + address[31:2] <= (address[31:2] + 1'b1); + end + state <= READ_ASSERT; + // continue sending current word + end else begin + state <= READ_SEND_ISSUE; + end + //maybe add in_ready_0 here so we are ready to go + //right away + end + end + endcase + if (enable & in_startofpacket) begin + state <= GET_EXTRA; + command <= in_data; + in_ready_0 <= 1'b1; + end + end // end else + end // end always block +endmodule diff --git a/ip/altera/ddr3/altera_avalon_sc_fifo.v b/ip/altera/ddr3/altera_avalon_sc_fifo.v new file mode 100644 index 0000000..cf8576a --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_sc_fifo.v @@ -0,0 +1,915 @@ +// ----------------------------------------------------------- +// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your +// use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any +// output files any of the foregoing (including device programming or +// simulation files), and any associated documentation or information are +// expressly subject to the terms and conditions of the Altera Program +// License Subscription Agreement or other applicable license agreement, +// including, without limitation, that your use is for the sole purpose +// of programming logic devices manufactured by Altera and sold by Altera +// or its authorized distributors. Please refer to the applicable +// agreement for further details. +// +// Description: Single clock Avalon-ST FIFO. +// ----------------------------------------------------------- + +`timescale 1 ns / 1 ns + + +//altera message_off 10036 +module altera_avalon_sc_fifo +#( + // -------------------------------------------------- + // Parameters + // -------------------------------------------------- + parameter SYMBOLS_PER_BEAT = 1, + parameter BITS_PER_SYMBOL = 8, + parameter FIFO_DEPTH = 16, + parameter CHANNEL_WIDTH = 0, + parameter ERROR_WIDTH = 0, + parameter USE_PACKETS = 0, + parameter USE_FILL_LEVEL = 0, + parameter USE_STORE_FORWARD = 0, + parameter USE_ALMOST_FULL_IF = 0, + parameter USE_ALMOST_EMPTY_IF = 0, + + // -------------------------------------------------- + // Empty latency is defined as the number of cycles + // required for a write to deassert the empty flag. + // For example, a latency of 1 means that the empty + // flag is deasserted on the cycle after a write. + // + // Another way to think of it is the latency for a + // write to propagate to the output. + // + // An empty latency of 0 implies lookahead, which is + // only implemented for the register-based FIFO. + // -------------------------------------------------- + parameter EMPTY_LATENCY = 3, + parameter USE_MEMORY_BLOCKS = 1, + + // -------------------------------------------------- + // Internal Parameters + // -------------------------------------------------- + parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) +) +( + // -------------------------------------------------- + // Ports + // -------------------------------------------------- + input clk, + input reset, + + input [DATA_WIDTH-1: 0] in_data, + input in_valid, + input in_startofpacket, + input in_endofpacket, + input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, + input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, + input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, + output in_ready, + + output [DATA_WIDTH-1 : 0] out_data, + output reg out_valid, + output out_startofpacket, + output out_endofpacket, + output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, + output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, + output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, + input out_ready, + + input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, + input csr_write, + input csr_read, + input [31 : 0] csr_writedata, + output reg [31 : 0] csr_readdata, + + output wire almost_full_data, + output wire almost_empty_data +); + + // -------------------------------------------------- + // Local Parameters + // -------------------------------------------------- + localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); + localparam DEPTH = FIFO_DEPTH; + localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; + localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? + 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; + + // -------------------------------------------------- + // Internal Signals + // -------------------------------------------------- + genvar i; + + reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; + reg [ADDR_WIDTH-1 : 0] wr_ptr; + reg [ADDR_WIDTH-1 : 0] rd_ptr; + reg [DEPTH-1 : 0] mem_used; + + wire [ADDR_WIDTH-1 : 0] next_wr_ptr; + wire [ADDR_WIDTH-1 : 0] next_rd_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; + + wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; + + wire read; + wire write; + + reg empty; + reg next_empty; + reg full; + reg next_full; + + wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; + wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; + wire [PAYLOAD_WIDTH-1 : 0] in_payload; + reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; + reg [PAYLOAD_WIDTH-1 : 0] out_payload; + + reg internal_out_valid; + wire internal_out_ready; + + reg [ADDR_WIDTH : 0] fifo_fill_level; + reg [ADDR_WIDTH : 0] fill_level; + + reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; + wire [ADDR_WIDTH-1 : 0] curr_sop_ptr; + reg [23:0] almost_full_threshold; + reg [23:0] almost_empty_threshold; + reg [23:0] cut_through_threshold; + reg [15:0] pkt_cnt; + reg drop_on_error_en; + reg error_in_pkt; + reg pkt_has_started; + reg sop_has_left_fifo; + reg fifo_too_small_r; + reg pkt_cnt_eq_zero; + reg pkt_cnt_eq_one; + + wire wait_for_threshold; + reg pkt_mode; + wire wait_for_pkt; + wire ok_to_forward; + wire in_pkt_eop_arrive; + wire out_pkt_leave; + wire in_pkt_start; + wire in_pkt_error; + wire drop_on_error; + wire fifo_too_small; + wire out_pkt_sop_leave; + wire [31:0] max_fifo_size; + reg fifo_fill_level_lt_cut_through_threshold; + + // -------------------------------------------------- + // Define Payload + // + // Icky part where we decide which signals form the + // payload to the FIFO with generate blocks. + // -------------------------------------------------- + generate + if (EMPTY_WIDTH > 0) begin : gen_blk1 + assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; + assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; + end + else begin : gen_blk1_else + assign out_empty = in_error; + assign in_packet_signals = {in_startofpacket, in_endofpacket}; + assign {out_startofpacket, out_endofpacket} = out_packet_signals; + end + endgenerate + + generate + if (USE_PACKETS) begin : gen_blk2 + if (ERROR_WIDTH > 0) begin : gen_blk3 + if (CHANNEL_WIDTH > 0) begin : gen_blk4 + assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; + assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; + end + else begin : gen_blk4_else + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data, in_error}; + assign {out_packet_signals, out_data, out_error} = out_payload; + end + end + else begin : gen_blk3_else + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin : gen_blk5 + assign in_payload = {in_packet_signals, in_data, in_channel}; + assign {out_packet_signals, out_data, out_channel} = out_payload; + end + else begin : gen_blk5_else + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data}; + assign {out_packet_signals, out_data} = out_payload; + end + end + end + else begin : gen_blk2_else + assign out_packet_signals = 0; + if (ERROR_WIDTH > 0) begin : gen_blk6 + if (CHANNEL_WIDTH > 0) begin : gen_blk7 + assign in_payload = {in_data, in_error, in_channel}; + assign {out_data, out_error, out_channel} = out_payload; + end + else begin : gen_blk7_else + assign out_channel = in_channel; + assign in_payload = {in_data, in_error}; + assign {out_data, out_error} = out_payload; + end + end + else begin : gen_blk6_else + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin : gen_blk8 + assign in_payload = {in_data, in_channel}; + assign {out_data, out_channel} = out_payload; + end + else begin : gen_blk8_else + assign out_channel = in_channel; + assign in_payload = in_data; + assign out_data = out_payload; + end + end + end + endgenerate + + // -------------------------------------------------- + // Memory-based FIFO storage + // + // To allow a ready latency of 0, the read index is + // obtained from the next read pointer and memory + // outputs are unregistered. + // + // If the empty latency is 1, we infer bypass logic + // around the memory so writes propagate to the + // outputs on the next cycle. + // + // Do not change the way this is coded: Quartus needs + // a perfect match to the template, and any attempt to + // refactor the two always blocks into one will break + // memory inference. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9 + + if (EMPTY_LATENCY == 1) begin : gen_blk10 + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] = in_payload; + + internal_out_payload = mem[mem_rd_ptr]; + end + + end else begin : gen_blk10_else + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] <= in_payload; + + internal_out_payload <= mem[mem_rd_ptr]; + end + + end + + assign mem_rd_ptr = next_rd_ptr; + + end else begin : gen_blk9_else + + // -------------------------------------------------- + // Register-based FIFO storage + // + // Uses a shift register as the storage element. Each + // shift register slot has a bit which indicates if + // the slot is occupied (credit to Sam H for the idea). + // The occupancy bits are contiguous and start from the + // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep + // FIFO. + // + // Each slot is enabled during a read or when it + // is unoccupied. New data is always written to every + // going-to-be-empty slot (we keep track of which ones + // are actually useful with the occupancy bits). On a + // read we shift occupied slots. + // + // The exception is the last slot, which always gets + // new data when it is unoccupied. + // -------------------------------------------------- + for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg + always @(posedge clk or posedge reset) begin + if (reset) begin + mem[i] <= 0; + end + else if (read || !mem_used[i]) begin + if (!mem_used[i+1]) + mem[i] <= in_payload; + else + mem[i] <= mem[i+1]; + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + mem[DEPTH-1] <= 0; + end + else begin + if (DEPTH == 1) begin + if (write) + mem[DEPTH-1] <= in_payload; + end + else if (!mem_used[DEPTH-1]) + mem[DEPTH-1] <= in_payload; + end + end + + end + endgenerate + + assign read = internal_out_ready && internal_out_valid && ok_to_forward; + assign write = in_ready && in_valid; + + // -------------------------------------------------- + // Pointer Management + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11 + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + + end else begin : gen_blk11_else + + // -------------------------------------------------- + // Shift Register Occupancy Bits + // + // Consider a 4-deep FIFO with 2 entries: 0011 + // On a read and write, do not modify the bits. + // On a write, left-shift the bits to get 0111. + // On a read, right-shift the bits to get 0001. + // + // Also, on a write we set bit0 (the head), while + // clearing the tail on a read. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[0] <= 0; + end + else begin + if (write ^ read) begin + if (write) + mem_used[0] <= 1; + else if (read) begin + if (DEPTH > 1) + mem_used[0] <= mem_used[1]; + else + mem_used[0] <= 0; + end + end + end + end + + if (DEPTH > 1) begin : gen_blk12 + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[DEPTH-1] <= 0; + end + else begin + if (write ^ read) begin + mem_used[DEPTH-1] <= 0; + if (write) + mem_used[DEPTH-1] <= mem_used[DEPTH-2]; + end + end + end + end + + for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic + always @(posedge clk, posedge reset) begin + if (reset) begin + mem_used[i] <= 0; + end + else begin + if (write ^ read) begin + if (write) + mem_used[i] <= mem_used[i-1]; + else if (read) + mem_used[i] <= mem_used[i+1]; + end + end + end + end + + end + endgenerate + + + // -------------------------------------------------- + // Memory FIFO Status Management + // + // Generates the full and empty signals from the + // pointers. The FIFO is full when the next write + // pointer will be equal to the read pointer after + // a write. Reading from a FIFO clears full. + // + // The FIFO is empty when the next read pointer will + // be equal to the write pointer after a read. Writing + // to a FIFO clears empty. + // + // A simultaneous read and write must not change any of + // the empty or full flags unless there is a drop on error event. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13 + + always @* begin + next_full = full; + next_empty = empty; + + if (read && !write) begin + next_full = 1'b0; + + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + + if (write && !read) begin + if (!drop_on_error) + next_empty = 1'b0; + else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo + next_empty = 1'b1; + + if (incremented_wr_ptr == rd_ptr && !drop_on_error) + next_full = 1'b1; + end + + if (write && read && drop_on_error) begin + if (curr_sop_ptr == next_rd_ptr) + next_empty = 1'b1; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + empty <= 1; + full <= 0; + end + else begin + empty <= next_empty; + full <= next_full; + end + end + + end else begin : gen_blk13_else + // -------------------------------------------------- + // Register FIFO Status Management + // + // Full when the tail occupancy bit is 1. Empty when + // the head occupancy bit is 0. + // -------------------------------------------------- + always @* begin + full = mem_used[DEPTH-1]; + empty = !mem_used[0]; + + // ------------------------------------------ + // For a single slot FIFO, reading clears the + // full status immediately. + // ------------------------------------------ + if (DEPTH == 1) + full = mem_used[0] && !read; + + internal_out_payload = mem[0]; + + // ------------------------------------------ + // Writes clear empty immediately for lookahead modes. + // Note that we use in_valid instead of write to avoid + // combinational loops (in lookahead mode, qualifying + // with in_ready is meaningless). + // + // In a 1-deep FIFO, a possible combinational loop runs + // from write -> out_valid -> out_ready -> write + // ------------------------------------------ + if (EMPTY_LATENCY == 0) begin + empty = !mem_used[0] && !in_valid; + + if (!mem_used[0] && in_valid) + internal_out_payload = in_payload; + end + end + + end + endgenerate + + // -------------------------------------------------- + // Avalon-ST Signals + // + // The in_ready signal is straightforward. + // + // To match memory latency when empty latency > 1, + // out_valid assertions must be delayed by one clock + // cycle. + // + // Note: out_valid deassertions must not be delayed or + // the FIFO will underflow. + // -------------------------------------------------- + assign in_ready = !full; + assign internal_out_ready = out_ready || !out_valid; + + generate if (EMPTY_LATENCY > 1) begin : gen_blk14 + always @(posedge clk or posedge reset) begin + if (reset) + internal_out_valid <= 0; + else begin + internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; + + if (read) begin + if (incremented_rd_ptr == wr_ptr) + internal_out_valid <= 1'b0; + end + end + end + end else begin : gen_blk14_else + always @* begin + internal_out_valid = !empty & ok_to_forward; + end + end + endgenerate + + // -------------------------------------------------- + // Single Output Pipeline Stage + // + // This output pipeline stage is enabled if the FIFO's + // empty latency is set to 3 (default). It is disabled + // for all other allowed latencies. + // + // Reason: The memory outputs are unregistered, so we have to + // register the output or fmax will drop if combinatorial + // logic is present on the output datapath. + // + // Q: The Avalon-ST spec says that I have to register my outputs + // But isn't the memory counted as a register? + // A: The path from the address lookup to the memory output is + // slow. Registering the memory outputs is a good idea. + // + // The registers get packed into the memory by the fitter + // which means minimal resources are consumed (the result + // is a altsyncram with registered outputs, available on + // all modern Altera devices). + // + // This output stage acts as an extra slot in the FIFO, + // and complicates the fill level. + // -------------------------------------------------- + generate if (EMPTY_LATENCY == 3) begin : gen_blk15 + always @(posedge clk or posedge reset) begin + if (reset) begin + out_valid <= 0; + out_payload <= 0; + end + else begin + if (internal_out_ready) begin + out_valid <= internal_out_valid & ok_to_forward; + out_payload <= internal_out_payload; + end + end + end + end + else begin : gen_blk15_else + always @* begin + out_valid = internal_out_valid; + out_payload = internal_out_payload; + end + end + endgenerate + + // -------------------------------------------------- + // Fill Level + // + // The fill level is calculated from the next write + // and read pointers to avoid unnecessary latency + // and logic. + // + // However, if the store-and-forward mode of the FIFO + // is enabled, the fill level is an up-down counter + // for fmax optimization reasons. + // + // If the output pipeline is enabled, the fill level + // must account for it, or we'll always be off by one. + // This may, or may not be important depending on the + // application. + // + // For now, we'll always calculate the exact fill level + // at the cost of an extra adder when the output stage + // is enabled. + // -------------------------------------------------- + generate if (USE_FILL_LEVEL) begin : gen_blk16 + wire [31:0] depth32; + assign depth32 = DEPTH; + + if (USE_STORE_FORWARD) begin + + reg [ADDR_WIDTH : 0] curr_packet_len_less_one; + + // -------------------------------------------------- + // We only drop on endofpacket. As long as we don't add to the fill + // level on the dropped endofpacket cycle, we can simply subtract + // (packet length - 1) from the fill level for dropped packets. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + curr_packet_len_less_one <= 0; + end else begin + if (write) begin + curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1; + if (in_endofpacket) + curr_packet_len_less_one <= 0; + end + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + fifo_fill_level <= 0; + end else if (drop_on_error) begin + fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one; + if (read) + fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1; + end else if (write && !read) begin + fifo_fill_level <= fifo_fill_level + 1'b1; + end else if (read && !write) begin + fifo_fill_level <= fifo_fill_level - 1'b1; + end + end + + end else begin + + always @(posedge clk or posedge reset) begin + if (reset) + fifo_fill_level <= 0; + else if (next_full & !drop_on_error) + fifo_fill_level <= depth32[ADDR_WIDTH:0]; + else begin + fifo_fill_level[ADDR_WIDTH] <= 1'b0; + fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; + end + end + + end + + always @* begin + fill_level = fifo_fill_level; + + if (EMPTY_LATENCY == 3) + fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; + end + end + else begin : gen_blk16_else + always @* begin + fill_level = 0; + end + end + endgenerate + + generate if (USE_ALMOST_FULL_IF) begin : gen_blk17 + assign almost_full_data = (fill_level >= almost_full_threshold); + end + else + assign almost_full_data = 0; + endgenerate + + generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18 + assign almost_empty_data = (fill_level <= almost_empty_threshold); + end + else + assign almost_empty_data = 0; + endgenerate + + // -------------------------------------------------- + // Avalon-MM Status & Control Connection Point + // + // Register map: + // + // | Addr | RW | 31 - 0 | + // | 0 | R | Fill level | + // + // The registering of this connection point means + // that there is a cycle of latency between + // reads/writes and the updating of the fill level. + // -------------------------------------------------- + generate if (USE_STORE_FORWARD) begin : gen_blk19 + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + cut_through_threshold <= 0; + drop_on_error_en <= 0; + csr_readdata <= 0; + pkt_mode <= 1'b1; + end + else begin + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 5) + csr_readdata <= {31'b0, drop_on_error_en}; + else if (csr_address == 4) + csr_readdata <= {8'b0, cut_through_threshold}; + else if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + else if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + else if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + end + else if (csr_write) begin + if(csr_address == 3'b101) + drop_on_error_en <= csr_writedata[0]; + else if(csr_address == 3'b100) begin + cut_through_threshold <= csr_writedata[23:0]; + pkt_mode <= (csr_writedata[23:0] == 0); + end + else if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + else if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + end + end + end + end + else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1 + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + csr_readdata <= 0; + end + else begin + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + else if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + else if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + end + else if (csr_write) begin + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + else if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + end + end + end + end + else begin : gen_blk19_else2 + always @(posedge clk or posedge reset) begin + if (reset) begin + csr_readdata <= 0; + end + else if (csr_read) begin + csr_readdata <= 0; + + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + end + end + end + endgenerate + + // -------------------------------------------------- + // Store and forward logic + // -------------------------------------------------- + // if the fifo gets full before the entire packet or the + // cut-threshold condition is met then start sending out + // data in order to avoid dead-lock situation + + generate if (USE_STORE_FORWARD) begin : gen_blk20 + assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; + assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); + assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : + ~wait_for_threshold) | fifo_too_small_r; + assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; + assign in_pkt_start = in_valid & in_ready & in_startofpacket; + assign in_pkt_error = in_valid & in_ready & |in_error; + assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; + assign out_pkt_leave = out_valid & out_ready & out_endofpacket; + assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; + + // count packets coming and going into the fifo + always @(posedge clk or posedge reset) begin + if (reset) begin + pkt_cnt <= 0; + pkt_has_started <= 0; + sop_has_left_fifo <= 0; + fifo_too_small_r <= 0; + pkt_cnt_eq_zero <= 1'b1; + pkt_cnt_eq_one <= 1'b0; + fifo_fill_level_lt_cut_through_threshold <= 1'b1; + end + else begin + fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; + fifo_too_small_r <= fifo_too_small; + + if( in_pkt_eop_arrive ) + sop_has_left_fifo <= 1'b0; + else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) + sop_has_left_fifo <= 1'b1; + + if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin + pkt_cnt <= pkt_cnt + 1'b1; + pkt_cnt_eq_zero <= 0; + if (pkt_cnt == 0) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin + pkt_cnt <= pkt_cnt - 1'b1; + if (pkt_cnt == 1) + pkt_cnt_eq_zero <= 1'b1; + else + pkt_cnt_eq_zero <= 1'b0; + if (pkt_cnt == 2) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + + if (in_pkt_start) + pkt_has_started <= 1'b1; + else if (in_pkt_eop_arrive) + pkt_has_started <= 1'b0; + end + end + + // drop on error logic + always @(posedge clk or posedge reset) begin + if (reset) begin + sop_ptr <= 0; + error_in_pkt <= 0; + end + else begin + // save the location of the SOP + if ( in_pkt_start ) + sop_ptr <= wr_ptr; + + // remember if error in pkt + // log error only if packet has already started + if (in_pkt_eop_arrive) + error_in_pkt <= 1'b0; + else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) + error_in_pkt <= 1'b1; + end + end + + assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & + ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); + + assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr; + + end + else begin : gen_blk20_else + assign ok_to_forward = 1'b1; + assign drop_on_error = 1'b0; + if (ADDR_WIDTH <= 1) + assign curr_sop_ptr = 1'b0; + else + assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }}; + end + endgenerate + + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + reg[31:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i[30:0] << 1; + end + end + endfunction + +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_bytes_to_packets.v b/ip/altera/ddr3/altera_avalon_st_bytes_to_packets.v new file mode 100644 index 0000000..a0438b7 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_bytes_to_packets.v @@ -0,0 +1,210 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// -------------------------------------------------------------------------------- +//| Avalon ST Bytes to Packet +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps +module altera_avalon_st_bytes_to_packets +//if ENCODING ==0, CHANNEL_WIDTH must be 8 +//else CHANNEL_WIDTH can be from 0 to 127 +#( parameter CHANNEL_WIDTH = 8, + parameter ENCODING = 0 ) +( + // Interface: clk + input clk, + input reset_n, + // Interface: ST out with packets + input out_ready, + output reg out_valid, + output reg [7: 0] out_data, + output reg [CHANNEL_WIDTH-1: 0] out_channel, + output reg out_startofpacket, + output reg out_endofpacket, + + // Interface: ST in + output reg in_ready, + input in_valid, + input [7: 0] in_data +); + + // --------------------------------------------------------------------- + //| Signal Declarations + // --------------------------------------------------------------------- + + reg received_esc, received_channel, received_varchannel; + wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char; + + // data out mux. + // we need it twice (data & channel out), so use a wire here + wire [7:0] data_out; + + // --------------------------------------------------------------------- + //| Thingofamagick + // --------------------------------------------------------------------- + + assign sop_char = (in_data == 8'h7a); + assign eop_char = (in_data == 8'h7b); + assign channel_char = (in_data == 8'h7c); + assign escape_char = (in_data == 8'h7d); + + assign data_out = received_esc ? (in_data ^ 8'h20) : in_data; + +generate +if (CHANNEL_WIDTH == 0) begin + // Synchorous block -- reset and registers + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + received_esc <= 0; + out_startofpacket <= 0; + out_endofpacket <= 0; + end else begin + // we take data when in_valid and in_ready + if (in_valid & in_ready) begin + if (received_esc) begin + //if we got esc char, after next byte is consumed, quit esc mode + if (out_ready) received_esc <= 0; + end else begin + if (escape_char) received_esc <= 1; + if (sop_char) out_startofpacket <= 1; + if (eop_char) out_endofpacket <= 1; + end + if (out_ready & out_valid) begin + out_startofpacket <= 0; + out_endofpacket <= 0; + end + end + end + end + + // Combinational block for in_ready and out_valid + always @* begin + //we choose not to pipeline here. We can process special characters when + //in_ready, but in a chain of microcores, backpressure path is usually + //time critical, so we keep it simple here. + in_ready = out_ready; + + //out_valid when in_valid, except when we are processing the special + //characters. However, if we are in escape received mode, then we are + //valid + out_valid = 0; + if ((out_ready | ~out_valid) && in_valid) begin + out_valid = 1; + if (sop_char | eop_char | escape_char | channel_char) out_valid = 0; + end + out_data = data_out; + end + +end else begin + assign varchannelesc_char = in_data[7]; + // Synchorous block -- reset and registers + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + received_esc <= 0; + received_channel <= 0; + received_varchannel <= 0; + out_startofpacket <= 0; + out_endofpacket <= 0; + end else begin + // we take data when in_valid and in_ready + if (in_valid & in_ready) begin + if (received_esc) begin + //if we got esc char, after next byte is consumed, quit esc mode + if (out_ready | received_channel | received_varchannel) received_esc <= 0; + end else begin + if (escape_char) received_esc <= 1; + if (sop_char) out_startofpacket <= 1; + if (eop_char) out_endofpacket <= 1; + if (channel_char & ENCODING ) received_varchannel <= 1; + if (channel_char & ~ENCODING) received_channel <= 1; + end + if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin + received_channel <= 0; + end + if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin + received_varchannel <= 0; + end + if (out_ready & out_valid) begin + out_startofpacket <= 0; + out_endofpacket <= 0; + end + end + end + end + + // Combinational block for in_ready and out_valid + always @* begin + in_ready = out_ready; + out_valid = 0; + if ((out_ready | ~out_valid) && in_valid) begin + out_valid = 1; + if (received_esc) begin + if (received_channel | received_varchannel) out_valid = 0; + end else begin + if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0; + end + end + out_data = data_out; + end +end + +endgenerate + +// Channel block +generate +if (CHANNEL_WIDTH == 0) begin + always @(posedge clk) begin + out_channel <= 'h0; + end + +end else if (CHANNEL_WIDTH < 8) begin + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + out_channel <= 'h0; + end else begin + if (in_ready & in_valid) begin + if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin + out_channel <= 'h0; + end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin + // Shifting out only the required bits + out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0]; + end + end + end + end + +end else begin + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + out_channel <= 'h0; + end else begin + if (in_ready & in_valid) begin + if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin + out_channel <= data_out; + end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin + // Variable Channel Encoding always setting to 0 before begin to shift the channel in + out_channel <= 'h0; + end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin + // Shifting out the lower 7 bits + out_channel <= out_channel <<7; + out_channel[6:0] <= data_out[6:0]; + end + end + end + end + +end +endgenerate + +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_clock_crosser.v b/ip/altera/ddr3/altera_avalon_st_clock_crosser.v new file mode 100644 index 0000000..17ab2e2 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_clock_crosser.v @@ -0,0 +1,141 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ns + +module altera_avalon_st_clock_crosser( + in_clk, + in_reset, + in_ready, + in_valid, + in_data, + out_clk, + out_reset, + out_ready, + out_valid, + out_data + ); + + parameter SYMBOLS_PER_BEAT = 1; + parameter BITS_PER_SYMBOL = 8; + parameter FORWARD_SYNC_DEPTH = 2; + parameter BACKWARD_SYNC_DEPTH = 2; + parameter USE_OUTPUT_PIPELINE = 1; + + localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; + + input in_clk; + input in_reset; + output in_ready; + input in_valid; + input [DATA_WIDTH-1:0] in_data; + + input out_clk; + input out_reset; + input out_ready; + output out_valid; + output [DATA_WIDTH-1:0] out_data; + + // Data is guaranteed valid by control signal clock crossing. Cut data + // buffer false path. + (* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer; + reg [DATA_WIDTH-1:0] out_data_buffer; + + reg in_data_toggle; + wire in_data_toggle_returned; + wire out_data_toggle; + reg out_data_toggle_flopped; + + wire take_in_data; + wire out_data_taken; + + wire out_valid_internal; + wire out_ready_internal; + + assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle); + assign take_in_data = in_valid & in_ready; + assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped; + assign out_data_taken = out_ready_internal & out_valid_internal; + + always @(posedge in_clk or posedge in_reset) begin + if (in_reset) begin + in_data_buffer <= {DATA_WIDTH{1'b0}}; + in_data_toggle <= 1'b0; + end else begin + if (take_in_data) begin + in_data_toggle <= ~in_data_toggle; + in_data_buffer <= in_data; + end + end //in_reset + end //in_clk always block + + always @(posedge out_clk or posedge out_reset) begin + if (out_reset) begin + out_data_toggle_flopped <= 1'b0; + out_data_buffer <= {DATA_WIDTH{1'b0}}; + end else begin + out_data_buffer <= in_data_buffer; + if (out_data_taken) begin + out_data_toggle_flopped <= out_data_toggle; + end + end //end if + end //out_clk always block + + altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer ( + .clk(out_clk), + .reset_n(~out_reset), + .din(in_data_toggle), + .dout(out_data_toggle) + ); + + altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer ( + .clk(in_clk), + .reset_n(~in_reset), + .din(out_data_toggle_flopped), + .dout(in_data_toggle_returned) + ); + + generate if (USE_OUTPUT_PIPELINE == 1) begin + + altera_avalon_st_pipeline_base + #( + .BITS_PER_SYMBOL(BITS_PER_SYMBOL), + .SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT) + ) output_stage ( + .clk(out_clk), + .reset(out_reset), + .in_ready(out_ready_internal), + .in_valid(out_valid_internal), + .in_data(out_data_buffer), + .out_ready(out_ready), + .out_valid(out_valid), + .out_data(out_data) + ); + + end else begin + + assign out_valid = out_valid_internal; + assign out_ready_internal = out_ready; + assign out_data = out_data_buffer; + + end + + endgenerate + +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_idle_inserter.v b/ip/altera/ddr3/altera_avalon_st_idle_inserter.v new file mode 100644 index 0000000..f89f72b --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_idle_inserter.v @@ -0,0 +1,72 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// -------------------------------------------------------------------------------- +//| Avalon ST Idle Inserter +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps +module altera_avalon_st_idle_inserter ( + + // Interface: clk + input clk, + input reset_n, + // Interface: ST in + output reg in_ready, + input in_valid, + input [7: 0] in_data, + + // Interface: ST out + input out_ready, + output reg out_valid, + output reg [7: 0] out_data +); + + // --------------------------------------------------------------------- + //| Signal Declarations + // --------------------------------------------------------------------- + + reg received_esc; + wire escape_char, idle_char; + + // --------------------------------------------------------------------- + //| Thingofamagick + // --------------------------------------------------------------------- + + assign idle_char = (in_data == 8'h4a); + assign escape_char = (in_data == 8'h4d); + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + received_esc <= 0; + end else begin + if (in_valid & out_ready) begin + if ((idle_char | escape_char) & ~received_esc & out_ready) begin + received_esc <= 1; + end else begin + received_esc <= 0; + end + end + end + end + + always @* begin + //we are always valid + out_valid = 1'b1; + in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc)); + out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle + (received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd + (idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char + in_data; //send data + end +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_idle_remover.v b/ip/altera/ddr3/altera_avalon_st_idle_remover.v new file mode 100644 index 0000000..e86da2c --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_idle_remover.v @@ -0,0 +1,70 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// -------------------------------------------------------------------------------- +//| Avalon ST Idle Remover +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps +module altera_avalon_st_idle_remover ( + + // Interface: clk + input clk, + input reset_n, + // Interface: ST in + output reg in_ready, + input in_valid, + input [7: 0] in_data, + + // Interface: ST out + input out_ready, + output reg out_valid, + output reg [7: 0] out_data +); + + // --------------------------------------------------------------------- + //| Signal Declarations + // --------------------------------------------------------------------- + + reg received_esc; + wire escape_char, idle_char; + + // --------------------------------------------------------------------- + //| Thingofamagick + // --------------------------------------------------------------------- + + assign idle_char = (in_data == 8'h4a); + assign escape_char = (in_data == 8'h4d); + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + received_esc <= 0; + end else begin + if (in_valid & in_ready) begin + if (escape_char & ~received_esc) begin + received_esc <= 1; + end else if (out_valid) begin + received_esc <= 0; + end + end + end + end + + always @* begin + in_ready = out_ready; + //out valid when in_valid. Except when we get idle or escape + //however, if we have received an escape character, then we are valid + out_valid = in_valid & ~idle_char & (received_esc | ~escape_char); + out_data = received_esc ? (in_data ^ 8'h20) : in_data; + end +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_jtag_interface.sdc b/ip/altera/ddr3/altera_avalon_st_jtag_interface.sdc new file mode 100644 index 0000000..d94deb8 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_jtag_interface.sdc @@ -0,0 +1,14 @@ +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +set_false_path -from [get_registers *altera_jtag_src_crosser:*|sink_data_buffer*] -to [get_registers *altera_jtag_src_crosser:*|src_data*] diff --git a/ip/altera/ddr3/altera_avalon_st_jtag_interface.v b/ip/altera/ddr3/altera_avalon_st_jtag_interface.v new file mode 100644 index 0000000..c7b9734 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_jtag_interface.v @@ -0,0 +1,224 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// This top level module chooses between the original Altera-ST JTAG Interface +// component in ACDS version 8.1 and before, and the new one with the PLI +// Simulation mode turned on, which adds a wrapper over the original component. + +`timescale 1 ns / 1 ns + +module altera_avalon_st_jtag_interface #( + parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0 + // for JTAG Phy, 1 for Packets to Master + parameter UPSTREAM_FIFO_SIZE = 0, + parameter DOWNSTREAM_FIFO_SIZE = 0, + parameter MGMT_CHANNEL_WIDTH = -1, + parameter EXPORT_JTAG = 0, + parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode + parameter PLI_PORT = 50000 // PLI Simulation Port +) ( + input wire jtag_tck, + input wire jtag_tms, + input wire jtag_tdi, + output wire jtag_tdo, + input wire jtag_ena, + input wire jtag_usr1, + input wire jtag_clr, + input wire jtag_clrn, + input wire jtag_state_tlr, + input wire jtag_state_rti, + input wire jtag_state_sdrs, + input wire jtag_state_cdr, + input wire jtag_state_sdr, + input wire jtag_state_e1dr, + input wire jtag_state_pdr, + input wire jtag_state_e2dr, + input wire jtag_state_udr, + input wire jtag_state_sirs, + input wire jtag_state_cir, + input wire jtag_state_sir, + input wire jtag_state_e1ir, + input wire jtag_state_pir, + input wire jtag_state_e2ir, + input wire jtag_state_uir, + input wire [2:0] jtag_ir_in, + output wire jtag_irq, + output wire [2:0] jtag_ir_out, + input wire clk, + input wire reset_n, + input wire source_ready, + output wire [7:0] source_data, + output wire source_valid, + input wire [7:0] sink_data, + input wire sink_valid, + output wire sink_ready, + output wire resetrequest, + output wire debug_reset, + output wire mgmt_valid, + output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel, + output wire mgmt_data +); + + // Signals in the JTAG clock domain + wire tck; + wire tdi; + wire tdo; + wire [2:0] ir_in; + wire virtual_state_cdr; + wire virtual_state_sdr; + wire virtual_state_udr; + + assign jtag_irq = 1'b0; + assign jtag_ir_out = 3'b000; + + generate + if (EXPORT_JTAG == 0) begin + // SLD node instantiation + altera_jtag_sld_node node ( + .tck (tck), + .tdi (tdi), + .tdo (tdo), + .ir_out (1'b0), + .ir_in (ir_in), + .virtual_state_cdr (virtual_state_cdr), + .virtual_state_cir (), + .virtual_state_e1dr (), + .virtual_state_e2dr (), + .virtual_state_pdr (), + .virtual_state_sdr (virtual_state_sdr), + .virtual_state_udr (virtual_state_udr), + .virtual_state_uir () + ); + + assign jtag_tdo = 1'b0; + end else begin + assign tck = jtag_tck; + assign tdi = jtag_tdi; + assign jtag_tdo = tdo; + assign ir_in = jtag_ir_in; + assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr; + assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr; + assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr; + end + endgenerate + + generate + if (USE_PLI == 0) + begin : normal + altera_jtag_dc_streaming #( + .PURPOSE(PURPOSE), + .UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE), + .DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE), + .MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH) + ) jtag_dc_streaming ( + .tck (tck), + .tdi (tdi), + .tdo (tdo), + .ir_in (ir_in), + .virtual_state_cdr(virtual_state_cdr), + .virtual_state_sdr(virtual_state_sdr), + .virtual_state_udr(virtual_state_udr), + .clk(clk), + .reset_n(reset_n), + .source_data(source_data), + .source_valid(source_valid), + .sink_data(sink_data), + .sink_valid(sink_valid), + .sink_ready(sink_ready), + .resetrequest(resetrequest), + .debug_reset(debug_reset), + .mgmt_valid(mgmt_valid), + .mgmt_channel(mgmt_channel), + .mgmt_data(mgmt_data) + ); + + end + else + begin : pli_mode + + //synthesis translate_off + reg pli_out_valid; + reg pli_in_ready; + reg [7 : 0] pli_out_data; + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + pli_out_valid <= 0; + pli_out_data <= 'b0; + pli_in_ready <= 0; + end + else begin + `ifdef MODEL_TECH + $do_transaction( + PLI_PORT, + pli_out_valid, + source_ready, + pli_out_data, + sink_valid, + pli_in_ready, + sink_data + ); + `endif + end + end + + //synthesis translate_on + wire [7:0] jtag_source_data; + wire jtag_source_valid; + wire jtag_sink_ready; + wire jtag_resetrequest; + + altera_jtag_dc_streaming #( + .PURPOSE(PURPOSE), + .UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE), + .DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE), + .MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH) + ) jtag_dc_streaming ( + .tck (tck), + .tdi (tdi), + .tdo (tdo), + .ir_in (ir_in), + .virtual_state_cdr(virtual_state_cdr), + .virtual_state_sdr(virtual_state_sdr), + .virtual_state_udr(virtual_state_udr), + .clk(clk), + .reset_n(reset_n), + .source_data(jtag_source_data), + .source_valid(jtag_source_valid), + .sink_data(sink_data), + .sink_valid(sink_valid), + .sink_ready(jtag_sink_ready), + .resetrequest(jtag_resetrequest)//, + //.debug_reset(debug_reset), + //.mgmt_valid(mgmt_valid), + //.mgmt_channel(mgmt_channel), + //.mgmt_data(mgmt_data) + ); + + // synthesis read_comments_as_HDL on + // assign source_valid = jtag_source_valid; + // assign source_data = jtag_source_data; + // assign sink_ready = jtag_sink_ready; + // assign resetrequest = jtag_resetrequest; + // synthesis read_comments_as_HDL off + + //synthesis translate_off + assign source_valid = pli_out_valid; + assign source_data = pli_out_data; + assign sink_ready = pli_in_ready; + assign resetrequest = 1'b0; + //synthesis translate_on + assign jtag_tdo = 1'b0; + end + endgenerate +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_packets_to_bytes.v b/ip/altera/ddr3/altera_avalon_st_packets_to_bytes.v new file mode 100644 index 0000000..1767fb9 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_packets_to_bytes.v @@ -0,0 +1,253 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// -------------------------------------------------------------------------------- +//| Avalon ST Packets to Bytes Component +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps +module altera_avalon_st_packets_to_bytes +//if ENCODING ==0, CHANNEL_WIDTH must be 8 +//else CHANNEL_WIDTH can be from 0 to 127 +#( parameter CHANNEL_WIDTH = 8, + parameter ENCODING = 0) +( + // Interface: clk + input clk, + input reset_n, + // Interface: ST in with packets + output reg in_ready, + input in_valid, + input [7: 0] in_data, + input [CHANNEL_WIDTH-1: 0] in_channel, + input in_startofpacket, + input in_endofpacket, + + // Interface: ST out + input out_ready, + output reg out_valid, + output reg [7: 0] out_data +); + + // --------------------------------------------------------------------- + //| Signal Declarations + // --------------------------------------------------------------------- + + localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7; + localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1; + reg sent_esc, sent_sop, sent_eop; + reg sent_channel_char, channel_escaped, sent_channel; + reg [CHANNEL_WIDTH:0] stored_channel; + reg [4:0] channel_count; + reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel; + reg channel_needs_esc; + + + + wire need_sop, need_eop, need_esc, need_channel; + + // --------------------------------------------------------------------- + //| Thingofamagick + // --------------------------------------------------------------------- + + assign need_esc = (in_data === 8'h7a | + in_data === 8'h7b | + in_data === 8'h7c | + in_data === 8'h7d ); + assign need_eop = (in_endofpacket); + assign need_sop = (in_startofpacket); + + +generate +if( CHANNEL_WIDTH > 0) begin + wire channel_changed; + assign channel_changed = (in_channel != stored_channel); + assign need_channel = (need_sop | channel_changed); + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + sent_esc <= 0; + sent_sop <= 0; + sent_eop <= 0; + sent_channel <= 0; + channel_escaped <= 0; + sent_channel_char <= 0; + out_data <= 0; + out_valid <= 0; + channel_count <= 0; + channel_needs_esc <= 0; + end else begin + + if (out_ready ) + out_valid <= 0; + + if ((out_ready | ~out_valid) && in_valid ) + out_valid <= 1; + + if ((out_ready | ~out_valid) && in_valid) begin + if (need_channel & ~sent_channel) begin + if (~sent_channel_char) begin + sent_channel_char <= 1; + out_data <= 8'h7c; + channel_count <= CHN_COUNT[4:0]; + stored_varchannel <= in_channel; + if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin + channel_needs_esc <= (in_channel == 8'h7a | + in_channel == 8'h7b | + in_channel == 8'h7c | + in_channel == 8'h7d ); + end + end else if (channel_needs_esc & ~channel_escaped) begin + out_data <= 8'h7d; + channel_escaped <= 1; + end else if (~sent_channel) begin + if (ENCODING) begin + // Sending out MSB=1, while not last 7 bits of Channel + if (channel_count > 0) begin + if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20; + else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]}; + stored_varchannel <= stored_varchannel<<7; + + channel_count <= channel_count - 1'b1; + // check whether the last 7 bits need escape or not + if (channel_count ==1 & CHANNEL_WIDTH > 7) begin + channel_needs_esc <= + ((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)| + (stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) | + (stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) | + (stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) ); + end + end else begin + // Sending out MSB=0, last 7 bits of Channel + if (channel_needs_esc) begin + channel_needs_esc <= 0; + out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20; + end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]}; + sent_channel <= 1; + end + end else begin + if (channel_needs_esc) begin + channel_needs_esc <= 0; + out_data <= in_channel ^ 8'h20; + end else out_data <= in_channel; + sent_channel <= 1; + end + end + end else if (need_sop & ~sent_sop) begin + sent_sop <= 1; + out_data <= 8'h7a; + + end else if (need_eop & ~sent_eop) begin + sent_eop <= 1; + out_data <= 8'h7b; + + end else if (need_esc & ~sent_esc) begin + sent_esc <= 1; + out_data <= 8'h7d; + end else begin + if (sent_esc) out_data <= in_data ^ 8'h20; + else out_data <= in_data; + sent_esc <= 0; + sent_sop <= 0; + sent_eop <= 0; + sent_channel <= 0; + channel_escaped <= 0; + sent_channel_char <= 0; + end + end + end + end + + //channel related signals + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + //extra bit in stored_channel to force reset + stored_channel <= {CHANNEL_WIDTH{1'b1}}; + end else begin + //update stored_channel only when it is sent out + if (sent_channel) stored_channel <= in_channel; + end + end + always @* begin + + // in_ready. Low when: + // back pressured, or when + // we are outputting a control character, which means that one of + // {escape_char, start of packet, end of packet, channel} + // needs to be, but has not yet, been handled. + in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc) + & (~need_sop | sent_sop) + & (~need_eop | sent_eop) + & (~need_channel | sent_channel); + end + +end else begin + +assign need_channel = (need_sop); + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + sent_esc <= 0; + sent_sop <= 0; + sent_eop <= 0; + out_data <= 0; + out_valid <= 0; + sent_channel <= 0; + sent_channel_char <= 0; + end else begin + + if (out_ready ) + out_valid <= 0; + + if ((out_ready | ~out_valid) && in_valid ) + out_valid <= 1; + + if ((out_ready | ~out_valid) && in_valid) begin + if (need_channel & ~sent_channel) begin + if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP + sent_channel_char <= 1; + out_data <= 8'h7c; + end else if (~sent_channel) begin + out_data <= 'h0; + sent_channel <= 1; + end + end else if (need_sop & ~sent_sop) begin + sent_sop <= 1; + out_data <= 8'h7a; + end else if (need_eop & ~sent_eop) begin + sent_eop <= 1; + out_data <= 8'h7b; + end else if (need_esc & ~sent_esc) begin + sent_esc <= 1; + out_data <= 8'h7d; + end else begin + if (sent_esc) out_data <= in_data ^ 8'h20; + else out_data <= in_data; + sent_esc <= 0; + sent_sop <= 0; + sent_eop <= 0; + end + end + end + end + + always @* begin + in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc) + & (~need_sop | sent_sop) + & (~need_eop | sent_eop) + & (~need_channel | sent_channel); + end +end +endgenerate + +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_pipeline_base.v b/ip/altera/ddr3/altera_avalon_st_pipeline_base.v new file mode 100644 index 0000000..96514b0 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_pipeline_base.v @@ -0,0 +1,139 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ns + +module altera_avalon_st_pipeline_base ( + clk, + reset, + in_ready, + in_valid, + in_data, + out_ready, + out_valid, + out_data + ); + + parameter SYMBOLS_PER_BEAT = 1; + parameter BITS_PER_SYMBOL = 8; + parameter PIPELINE_READY = 1; + localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; + + input clk; + input reset; + + output in_ready; + input in_valid; + input [DATA_WIDTH-1:0] in_data; + + input out_ready; + output out_valid; + output [DATA_WIDTH-1:0] out_data; + + reg full0; + reg full1; + reg [DATA_WIDTH-1:0] data0; + reg [DATA_WIDTH-1:0] data1; + + assign out_valid = full1; + assign out_data = data1; + + generate if (PIPELINE_READY == 1) + begin : REGISTERED_READY_PLINE + + assign in_ready = !full0; + + always @(posedge clk, posedge reset) begin + if (reset) begin + data0 <= {DATA_WIDTH{1'b0}}; + data1 <= {DATA_WIDTH{1'b0}}; + end else begin + // ---------------------------- + // always load the second slot if we can + // ---------------------------- + if (~full0) + data0 <= in_data; + // ---------------------------- + // first slot is loaded either from the second, + // or with new data + // ---------------------------- + if (~full1 || (out_ready && out_valid)) begin + if (full0) + data1 <= data0; + else + data1 <= in_data; + end + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + full0 <= 1'b0; + full1 <= 1'b0; + end else begin + // no data in pipeline + if (~full0 & ~full1) begin + if (in_valid) begin + full1 <= 1'b1; + end + end // ~f1 & ~f0 + + // one datum in pipeline + if (full1 & ~full0) begin + if (in_valid & ~out_ready) begin + full0 <= 1'b1; + end + // back to empty + if (~in_valid & out_ready) begin + full1 <= 1'b0; + end + end // f1 & ~f0 + + // two data in pipeline + if (full1 & full0) begin + // go back to one datum state + if (out_ready) begin + full0 <= 1'b0; + end + end // end go back to one datum stage + end + end + + end + else + begin : UNREGISTERED_READY_PLINE + + // in_ready will be a pass through of the out_ready signal as it is not registered + assign in_ready = (~full1) | out_ready; + + always @(posedge clk or posedge reset) begin + if (reset) begin + data1 <= 'b0; + full1 <= 1'b0; + end + else begin + if (in_ready) begin + data1 <= in_data; + full1 <= in_valid; + end + end + end + end + endgenerate +endmodule diff --git a/ip/altera/ddr3/altera_avalon_st_pipeline_stage.sv b/ip/altera/ddr3/altera_avalon_st_pipeline_stage.sv new file mode 100644 index 0000000..e6c1b82 --- /dev/null +++ b/ip/altera/ddr3/altera_avalon_st_pipeline_stage.sv @@ -0,0 +1,166 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.sv $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ns + +module altera_avalon_st_pipeline_stage #( + parameter + SYMBOLS_PER_BEAT = 1, + BITS_PER_SYMBOL = 8, + USE_PACKETS = 0, + USE_EMPTY = 0, + PIPELINE_READY = 1, + + // Optional ST signal widths. Value "0" means no such port. + CHANNEL_WIDTH = 0, + ERROR_WIDTH = 0, + + // Derived parameters + DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + PACKET_WIDTH = 0, + EMPTY_WIDTH = 0 + ) + ( + input clk, + input reset, + + output in_ready, + input in_valid, + input [DATA_WIDTH - 1 : 0] in_data, + input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel, + input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error, + input in_startofpacket, + input in_endofpacket, + input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty, + + input out_ready, + output out_valid, + output [DATA_WIDTH - 1 : 0] out_data, + output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel, + output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error, + output out_startofpacket, + output out_endofpacket, + output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty +); + localparam + PAYLOAD_WIDTH = + DATA_WIDTH + + PACKET_WIDTH + + CHANNEL_WIDTH + + EMPTY_WIDTH + + ERROR_WIDTH; + + wire [PAYLOAD_WIDTH - 1: 0] in_payload; + wire [PAYLOAD_WIDTH - 1: 0] out_payload; + + // Assign in_data and other optional in_* interface signals to in_payload. + assign in_payload[DATA_WIDTH - 1 : 0] = in_data; + generate + // optional packet inputs + if (PACKET_WIDTH) begin + assign in_payload[ + DATA_WIDTH + PACKET_WIDTH - 1 : + DATA_WIDTH + ] = {in_startofpacket, in_endofpacket}; + end + // optional channel input + if (CHANNEL_WIDTH) begin + assign in_payload[ + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 : + DATA_WIDTH + PACKET_WIDTH + ] = in_channel; + end + // optional empty input + if (EMPTY_WIDTH) begin + assign in_payload[ + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 : + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + ] = in_empty; + end + // optional error input + if (ERROR_WIDTH) begin + assign in_payload[ + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 : + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ] = in_error; + end + endgenerate + + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (PAYLOAD_WIDTH), + .BITS_PER_SYMBOL (1), + .PIPELINE_READY (PIPELINE_READY) + ) core ( + .clk (clk), + .reset (reset), + .in_ready (in_ready), + .in_valid (in_valid), + .in_data (in_payload), + .out_ready (out_ready), + .out_valid (out_valid), + .out_data (out_payload) + ); + + // Assign out_data and other optional out_* interface signals from out_payload. + assign out_data = out_payload[DATA_WIDTH - 1 : 0]; + generate + // optional packet outputs + if (PACKET_WIDTH) begin + assign {out_startofpacket, out_endofpacket} = + out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH]; + end else begin + // Avoid a "has no driver" warning. + assign {out_startofpacket, out_endofpacket} = 2'b0; + end + + // optional channel output + if (CHANNEL_WIDTH) begin + assign out_channel = out_payload[ + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 : + DATA_WIDTH + PACKET_WIDTH + ]; + end else begin + // Avoid a "has no driver" warning. + assign out_channel = 1'b0; + end + // optional empty output + if (EMPTY_WIDTH) begin + assign out_empty = out_payload[ + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 : + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + ]; + end else begin + // Avoid a "has no driver" warning. + assign out_empty = 1'b0; + end + // optional error output + if (ERROR_WIDTH) begin + assign out_error = out_payload[ + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 : + DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ]; + end else begin + // Avoid a "has no driver" warning. + assign out_error = 1'b0; + end + endgenerate + +endmodule + + diff --git a/ip/altera/ddr3/altera_default_burst_converter.sv b/ip/altera/ddr3/altera_default_burst_converter.sv new file mode 100644 index 0000000..666ee56 --- /dev/null +++ b/ip/altera/ddr3/altera_default_burst_converter.sv @@ -0,0 +1,189 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_burst_adapter/new_source/altera_default_burst_converter.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// -------------------------------------------- +// Default Burst Converter +// Notes: +// 1) If burst type FIXED and slave is AXI, +// passthrough the transaction. +// 2) Else, converts burst into non-bursting +// transactions (length of 1). +// -------------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_default_burst_converter +#( + parameter PKT_BURST_TYPE_W = 2, + parameter PKT_BURSTWRAP_W = 5, + parameter PKT_ADDR_W = 12, + parameter PKT_BURST_SIZE_W = 3, + parameter IS_AXI_SLAVE = 0, + parameter LEN_W = 2 +) +( + input clk, + input reset, + input enable, + + input [PKT_BURST_TYPE_W - 1 : 0] in_bursttype, + input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg, + input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_value, + input [PKT_ADDR_W - 1 : 0] in_addr, + input [PKT_ADDR_W - 1 : 0] in_addr_reg, + input [LEN_W - 1 : 0] in_len, + input [PKT_BURST_SIZE_W - 1 : 0] in_size_value, + + input in_is_write, + + output reg [PKT_ADDR_W - 1 : 0] out_addr, + output reg [LEN_W - 1 : 0] out_len, + + output reg new_burst +); + + // --------------------------------------------------- + // AXI Burst Type Encoding + // --------------------------------------------------- + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + RESERVED = 2'b11 + } AxiBurstType; + + // ------------------------------------------- + // Internal Signals + // ------------------------------------------- + wire [LEN_W - 1 : 0] unit_len = {{LEN_W - 1 {1'b0}}, 1'b1}; + reg [LEN_W - 1 : 0] next_len; + reg [LEN_W - 1 : 0] remaining_len; + reg [PKT_ADDR_W - 1 : 0] next_incr_addr; + reg [PKT_ADDR_W - 1 : 0] incr_wrapped_addr; + reg [PKT_ADDR_W - 1 : 0] extended_burstwrap_value; + reg [PKT_ADDR_W - 1 : 0] addr_incr_variable_size_value; + + // ------------------------------------------- + // Byte Count Converter + // ------------------------------------------- + // Avalon Slave: Read/Write, the out_len is always 1 (unit_len). + // AXI Slave: Read/Write, the out_len is always the in_len (pass through) of a given cycle. + // If bursttype RESERVED, out_len is always 1 (unit_len). + generate if (IS_AXI_SLAVE == 1) + begin : axi_slave_out_len + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + out_len <= {LEN_W{1'b0}}; + end + else if (enable) begin + out_len <= (in_bursttype == FIXED) ? in_len : unit_len; + end + end + end + else // IS_AXI_SLAVE == 0 + begin : non_axi_slave_out_len + always_comb begin + out_len = unit_len; + end + end + endgenerate + + + always_comb begin : proc_extend_burstwrap + extended_burstwrap_value = {{(PKT_ADDR_W - PKT_BURSTWRAP_W){in_burstwrap_reg[PKT_BURSTWRAP_W - 1]}}, in_burstwrap_value}; + addr_incr_variable_size_value = {{(PKT_ADDR_W - 1){1'b0}}, 1'b1} << in_size_value; + end + + // ------------------------------------------- + // Address Converter + // ------------------------------------------- + // Write: out_addr = in_addr at every cycle (pass through). + // Read: out_addr = in_addr at every new_burst. Subsequent addresses calculated by converter. + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + next_incr_addr <= {PKT_ADDR_W{1'b0}}; + out_addr <= {PKT_ADDR_W{1'b0}}; + end + else if (enable) begin + next_incr_addr <= next_incr_addr + addr_incr_variable_size_value; + if (new_burst) begin + next_incr_addr <= in_addr + addr_incr_variable_size_value; + end + out_addr <= incr_wrapped_addr; + end + end + + always_comb begin + incr_wrapped_addr = in_addr; + if (!new_burst) begin + // This formula calculates addresses of WRAP bursts and works perfectly fine for other burst types too. + incr_wrapped_addr = (in_addr_reg & ~extended_burstwrap_value) | (next_incr_addr & extended_burstwrap_value); + end + end + + // ------------------------------------------- + // Control Signals + // ------------------------------------------- + + // Determine the min_len. + // 1) FIXED read to AXI slave: One-time passthrough, therefore the min_len == in_len. + // 2) FIXED write to AXI slave: min_len == 1. + // 3) FIXED read/write to Avalon slave: min_len == 1. + // 4) RESERVED read/write to AXI/Avalon slave: min_len == 1. + wire [LEN_W - 1 : 0] min_len; + generate if (IS_AXI_SLAVE == 1) + begin : axi_slave_min_len + assign min_len = (!in_is_write && (in_bursttype == FIXED)) ? in_len : unit_len; + end + else // IS_AXI_SLAVE == 0 + begin : non_axi_slave_min_len + assign min_len = unit_len; + end + endgenerate + + // last_beat calculation. + wire last_beat = (remaining_len == min_len); + + // next_len calculation. + always_comb begin + remaining_len = in_len; + if (!new_burst) remaining_len = next_len; + end + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + next_len <= 1'b0; + end + else if (enable) begin + next_len <= remaining_len - unit_len; + end + end + + // new_burst calculation. + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + new_burst <= 1'b1; + end + else if (enable) begin + new_burst <= last_beat; + end + end + +endmodule diff --git a/ip/altera/ddr3/altera_incr_burst_converter.sv b/ip/altera/ddr3/altera_incr_burst_converter.sv new file mode 100644 index 0000000..0b0f5de --- /dev/null +++ b/ip/altera/ddr3/altera_incr_burst_converter.sv @@ -0,0 +1,310 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_burst_adapter/new_source/altera_incr_burst_converter.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ---------------------------------------------------------- +// This component is used for INCR Avalon slave +// (slave which only supports INCR) or AXI slave. +// It converts burst length of input packet +// to match slave burst. +// ---------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_incr_burst_converter +#( + parameter + // ---------------------------------------- + // Burst length Parameters + // (real burst length value, not bytecount) + // ---------------------------------------- + MAX_IN_LEN = 16, + MAX_OUT_LEN = 4, + NUM_SYMBOLS = 4, + ADDR_WIDTH = 12, + BNDRY_WIDTH = 12, + BURSTSIZE_WIDTH = 3, + IN_NARROW_SIZE = 0, + PURELY_INCR_AVL_SYS = 0, + // ------------------ + // Derived Parameters + // ------------------ + LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1, + OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1, + LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS) +) +( + input clk, + input reset, + input enable, + + input is_write, + input [LEN_WIDTH - 1 : 0] in_len, + input in_sop, + + input [ADDR_WIDTH - 1 : 0] in_addr, + input [ADDR_WIDTH - 1 : 0] in_addr_reg, + input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg, + input [BURSTSIZE_WIDTH - 1 : 0] in_size_t, + input [BURSTSIZE_WIDTH - 1 : 0] in_size_reg, + + // converted output length + // out_len : compressed burst, read + // uncompressed_len: uncompressed, write + output reg [LEN_WIDTH - 1 : 0] out_len, + output reg [LEN_WIDTH - 1 : 0] uncompr_out_len, + // Compressed address output + output reg [ADDR_WIDTH - 1 : 0] out_addr, + output reg new_burst_export +); + + // ---------------------------------------- + // Signals for wrapping support + // ---------------------------------------- + reg [LEN_WIDTH - 1 : 0] remaining_len; + reg [LEN_WIDTH - 1 : 0] next_out_len; + reg [LEN_WIDTH - 1 : 0] next_rem_len; + reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len; + reg [LEN_WIDTH - 1 : 0] next_uncompr_remaining_len; + reg [LEN_WIDTH - 1 : 0] next_uncompr_rem_len; + reg new_burst; + reg uncompr_sub_burst; + + // Avoid QIS warning + wire [OUT_LEN_WIDTH - 1 : 0] max_out_length; + assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0]; + + always_comb begin + new_burst_export = new_burst; + end + + // ------------------------------------------- + // length remaining calculation + // ------------------------------------------- + + always_comb begin : proc_uncompressed_remaining_len + if ((in_len <= max_out_length) && is_write) begin + uncompr_remaining_len = in_len; + end else begin + uncompr_remaining_len = max_out_length; + end + + if (uncompr_sub_burst) + uncompr_remaining_len = next_uncompr_rem_len; + end + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + next_uncompr_rem_len <= 0; + end + else if (enable) begin + next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1 + end + end + + always_comb begin : proc_compressed_remaining_len + remaining_len = in_len; + if (!new_burst) + remaining_len = next_rem_len; + end + + always_ff@(posedge clk or posedge reset) begin : proc_next_uncompressed_remaining_len + if(reset) begin + next_uncompr_remaining_len <= '0; + end + else if (enable) begin + if (in_sop) begin + next_uncompr_remaining_len <= in_len - max_out_length; + end + else if (!uncompr_sub_burst) + next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length; + end + end + + always_comb begin + next_out_len = max_out_length; + if (remaining_len < max_out_length) begin + next_out_len = remaining_len; + end + end // always_comb + + // -------------------------------------------------- + // Length remaining calculation : compressed + // -------------------------------------------------- + // length remaining for compressed transaction + // for wrap, need special handling for first out length + + always_ff @(posedge clk, posedge reset) begin + if (reset) + next_rem_len <= 0; + else if (enable) begin + if (new_burst) + next_rem_len <= in_len - max_out_length; + else + next_rem_len <= next_rem_len - max_out_length; + end + end + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + uncompr_sub_burst <= 0; + end + else if (enable && is_write) begin + uncompr_sub_burst <= (uncompr_remaining_len > 1'b1); + end + end + + + // -------------------------------------------------- + // Control signals + // -------------------------------------------------- + wire end_compressed_sub_burst; + assign end_compressed_sub_burst = (remaining_len == next_out_len); + + // new_burst: + // the converter takes in_len for new calculation + always_ff @(posedge clk, posedge reset) begin + if (reset) + new_burst <= 1; + else if (enable) + new_burst <= end_compressed_sub_burst; + end + + // -------------------------------------------------- + // Output length + // -------------------------------------------------- + // register out_len for compressed trans + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + out_len <= 0; + end + else if (enable) begin + out_len <= next_out_len; + end + end + + // register uncompr_out_len for uncompressed trans + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + uncompr_out_len <= '0; + end + else if (enable) begin + uncompr_out_len <= uncompr_remaining_len; + end + end + + // -------------------------------------------------- + // Address Calculation + // -------------------------------------------------- + reg [ADDR_WIDTH - 1 : 0] addr_incr_sel; + reg [ADDR_WIDTH - 1 : 0] addr_incr_sel_reg; + reg [ADDR_WIDTH - 1 : 0] addr_incr_full_size; + + localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS; + + generate + if (IN_NARROW_SIZE) begin : narrow_addr_incr + reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size; + reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size_reg; + + assign addr_incr_variable_size = MAX_OUT_LEN << in_size_t; + assign addr_incr_variable_size_reg = MAX_OUT_LEN << in_size_reg; + + assign addr_incr_sel = addr_incr_variable_size; + assign addr_incr_sel_reg = addr_incr_variable_size_reg; + end + else begin : full_addr_incr + assign addr_incr_full_size = ADDR_INCR[ADDR_WIDTH - 1 : 0]; + assign addr_incr_sel = addr_incr_full_size; + assign addr_incr_sel_reg = addr_incr_full_size; + end + endgenerate + + + reg [ADDR_WIDTH - 1 : 0] next_out_addr; + reg [ADDR_WIDTH - 1 : 0] incremented_addr; + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + out_addr <= '0; + end else begin + if (enable) begin + out_addr <= (next_out_addr); + end + end + end + + generate + if (!PURELY_INCR_AVL_SYS) begin : incremented_addr_normal + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + incremented_addr <= '0; + end + else if (enable) begin + incremented_addr <= (next_out_addr + addr_incr_sel_reg); + if (new_burst) begin + incremented_addr <= (next_out_addr + addr_incr_sel); + end + end + end // always_ff @ + + always_comb begin + next_out_addr = in_addr; + if (!new_burst) begin + next_out_addr = incremented_addr; + end + end + end + else begin : incremented_addr_pure_av + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + incremented_addr <= '0; + end + else if (enable) begin + incremented_addr <= (next_out_addr + addr_incr_sel_reg); + end + end // always_ff @ + + always_comb begin + next_out_addr = in_addr; + if (!new_burst) begin + next_out_addr = (incremented_addr); + end + end + + end + endgenerate + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + reg[31:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i[30:0] << 1; + end + end + endfunction + +endmodule diff --git a/ip/altera/ddr3/altera_jtag_dc_streaming.v b/ip/altera/ddr3/altera_jtag_dc_streaming.v new file mode 100644 index 0000000..277ec67 --- /dev/null +++ b/ip/altera/ddr3/altera_jtag_dc_streaming.v @@ -0,0 +1,261 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// This module is a simple clock crosser for control signals. It will take +// the asynchronous control signal and synchronize it to the clk domain +// attached to the clk input. It does so by passing the control signal +// through a pair of registers and then sensing the level transition from +// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption +// that the control signal will always transition every time is asserted. +// i.e.: +// ____ ___________________ +// -> ___| |___ and ___| |_____ +// +// on the control signal will be seen as only one assertion of the control +// signal. In short, if your control could be asserted back-to-back, then +// don't use this module. You'll be losing data. + +`timescale 1 ns / 1 ns + +module altera_jtag_control_signal_crosser ( + clk, + reset_n, + async_control_signal, + sense_pos_edge, + sync_control_signal +); + input clk; + input reset_n; + input async_control_signal; + input sense_pos_edge; + output sync_control_signal; + + parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing + + reg sync_control_signal; + + wire synchronized_raw_signal; + reg edge_detector_register; + + altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer ( + .clk(clk), + .reset_n(reset_n), + .din(async_control_signal), + .dout(synchronized_raw_signal) + ); + + always @ (posedge clk or negedge reset_n) + if (~reset_n) + edge_detector_register <= 1'b0; + else + edge_detector_register <= synchronized_raw_signal; + + always @* begin + if (sense_pos_edge) + sync_control_signal <= ~edge_detector_register & synchronized_raw_signal; + else + sync_control_signal <= edge_detector_register & ~synchronized_raw_signal; + end +endmodule + +// This module crosses the clock domain for a given source +module altera_jtag_src_crosser ( + sink_clk, + sink_reset_n, + sink_valid, + sink_data, + src_clk, + src_reset_n, + src_valid, + src_data +); + parameter WIDTH = 8; + parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing + + input sink_clk; + input sink_reset_n; + input sink_valid; + input [WIDTH-1:0] sink_data; + input src_clk; + input src_reset_n; + output src_valid; + output [WIDTH-1:0] src_data; + + reg sink_valid_buffer; + reg [WIDTH-1:0] sink_data_buffer; + + reg src_valid; + reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */; + + wire synchronized_valid; + + altera_jtag_control_signal_crosser #( + .SYNC_DEPTH(SYNC_DEPTH) + ) crosser ( + .clk(src_clk), + .reset_n(src_reset_n), + .async_control_signal(sink_valid_buffer), + .sense_pos_edge(1'b1), + .sync_control_signal(synchronized_valid) + ); + always @ (posedge sink_clk or negedge sink_reset_n) begin + if (~sink_reset_n) begin + sink_valid_buffer <= 1'b0; + sink_data_buffer <= 'b0; + end else begin + sink_valid_buffer <= sink_valid; + if (sink_valid) begin + sink_data_buffer <= sink_data; + end + end //end if + end //always sink_clk + + always @ (posedge src_clk or negedge src_reset_n) begin + if (~src_reset_n) begin + src_valid <= 1'b0; + src_data <= {WIDTH{1'b0}}; + end else begin + src_valid <= synchronized_valid; + src_data <= synchronized_valid ? sink_data_buffer : src_data; + end + end + +endmodule + +module altera_jtag_dc_streaming #( + parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0 + // for JTAG Phy, 1 for Packets to Master + parameter UPSTREAM_FIFO_SIZE = 0, + parameter DOWNSTREAM_FIFO_SIZE = 0, + parameter MGMT_CHANNEL_WIDTH = -1 +) ( + // Signals in the JTAG clock domain + input wire tck, + input wire tdi, + output wire tdo, + input wire [2:0] ir_in, + input wire virtual_state_cdr, + input wire virtual_state_sdr, + input wire virtual_state_udr, + + input wire clk, + input wire reset_n, + output wire [7:0] source_data, + output wire source_valid, + input wire [7:0] sink_data, + input wire sink_valid, + output wire sink_ready, + output wire resetrequest, + output wire debug_reset, + output wire mgmt_valid, + output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel, + output wire mgmt_data +); + + // the tck to sysclk sync depth is fixed at 8 + // 8 is the worst case scenario from our metastability analysis, and since + // using TCK serially is so slow we should have plenty of clock cycles. + localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8; + // The clk to tck path is fixed at 3 deep for Synchronizer depth. + // Since the tck clock is so slow, no parameter is exposed. + localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3; + + wire jtag_clock_reset_n; // system reset is synchronized with tck + wire [7:0] jtag_source_data; + wire jtag_source_valid; + wire [7:0] jtag_sink_data; + wire jtag_sink_valid; + wire jtag_sink_ready; + + /* Reset Synchronizer module. + * + * The SLD Node does not provide a reset for the TCK clock domain. + * Due to the handshaking nature of the Avalon-ST Clock Crosser, + * internal states need to be reset to 0 in order to guarantee proper + * functionality throughout resets. + * + * This reset block will asynchronously assert reset, and synchronously + * deassert reset for the tck clock domain. + */ + altera_std_synchronizer #( + .depth(SYSCLK_TO_TCK_SYNC_DEPTH) + ) synchronizer ( + .clk(tck), + .reset_n(reset_n), + .din(1'b1), + .dout(jtag_clock_reset_n) + ); + + altera_jtag_streaming #( + .PURPOSE(PURPOSE), + .UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE), + .DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE), + .MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH) + ) jtag_streaming ( + .tck (tck), + .tdi (tdi), + .tdo (tdo), + .ir_in (ir_in), + .virtual_state_cdr(virtual_state_cdr), + .virtual_state_sdr(virtual_state_sdr), + .virtual_state_udr(virtual_state_udr), + + .reset_n(jtag_clock_reset_n), + .source_data(jtag_source_data), + .source_valid(jtag_source_valid), + .sink_data(jtag_sink_data), + .sink_valid(jtag_sink_valid), + .sink_ready(jtag_sink_ready), + .clock_to_sample(clk), + .reset_to_sample(reset_n), + .resetrequest(resetrequest), + .debug_reset(debug_reset), + .mgmt_valid(mgmt_valid), + .mgmt_channel(mgmt_channel), + .mgmt_data(mgmt_data) + ); + + // synchronization in both clock domain crossings takes place in the "clk" system clock domain! + + altera_avalon_st_clock_crosser #( + .SYMBOLS_PER_BEAT(1), + .BITS_PER_SYMBOL(8), + .FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH), + .BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH) + ) sink_crosser ( + .in_clk(clk), + .in_reset(~reset_n), + .in_data(sink_data), + .in_ready(sink_ready), + .in_valid(sink_valid), + .out_clk(tck), + .out_reset(~jtag_clock_reset_n), + .out_data(jtag_sink_data), + .out_ready(jtag_sink_ready), + .out_valid(jtag_sink_valid) + ); + + altera_jtag_src_crosser #( + .SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH) + ) source_crosser ( + .sink_clk(tck), + .sink_reset_n(jtag_clock_reset_n), + .sink_valid(jtag_source_valid), + .sink_data(jtag_source_data), + .src_clk(clk), + .src_reset_n(reset_n), + .src_valid(source_valid), + .src_data(source_data) + ); + +endmodule diff --git a/ip/altera/ddr3/altera_jtag_sld_node.v b/ip/altera/ddr3/altera_jtag_sld_node.v new file mode 100644 index 0000000..f3175cc --- /dev/null +++ b/ip/altera/ddr3/altera_jtag_sld_node.v @@ -0,0 +1,261 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// synopsys translate_off +`timescale 1 ns / 1 ns +// synopsys translate_on +module altera_jtag_sld_node ( + ir_out, + tdo, + ir_in, + tck, + tdi, + virtual_state_cdr, + virtual_state_cir, + virtual_state_e1dr, + virtual_state_e2dr, + virtual_state_pdr, + virtual_state_sdr, + virtual_state_udr, + virtual_state_uir +); + +parameter TCK_FREQ_MHZ = 20; +localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2; +localparam IRWIDTH = 3; + +input [IRWIDTH - 1:0] ir_out; +input tdo; +output reg [IRWIDTH - 1:0] ir_in; +output tck; +output reg tdi = 1'b0; +output virtual_state_cdr; +output virtual_state_cir; +output virtual_state_e1dr; +output virtual_state_e2dr; +output virtual_state_pdr; +output virtual_state_sdr; +output virtual_state_udr; +output virtual_state_uir; + +// PHY Simulation signals +`ifndef ALTERA_RESERVED_QIS + reg simulation_clock; + reg sdrs; + reg cdr; + reg sdr; + reg e1dr; + reg udr; + reg [7:0] bit_index; +`endif + + +// PHY Instantiation +`ifdef ALTERA_RESERVED_QIS + wire tdi_port; + wire [IRWIDTH - 1:0] ir_in_port; + always @(tdi_port) + tdi = tdi_port; + always @(ir_in_port) + ir_in = ir_in_port; + sld_virtual_jtag_basic sld_virtual_jtag_component ( + .ir_out (ir_out), + .tdo (tdo), + .tdi (tdi_port), + .tck (tck), + .ir_in (ir_in_port), + .virtual_state_cir (virtual_state_cir), + .virtual_state_pdr (virtual_state_pdr), + .virtual_state_uir (virtual_state_uir), + .virtual_state_sdr (virtual_state_sdr), + .virtual_state_cdr (virtual_state_cdr), + .virtual_state_udr (virtual_state_udr), + .virtual_state_e1dr (virtual_state_e1dr), + .virtual_state_e2dr (virtual_state_e2dr) + // synopsys translate_off + , + .jtag_state_cdr (), + .jtag_state_cir (), + .jtag_state_e1dr (), + .jtag_state_e1ir (), + .jtag_state_e2dr (), + .jtag_state_e2ir (), + .jtag_state_pdr (), + .jtag_state_pir (), + .jtag_state_rti (), + .jtag_state_sdr (), + .jtag_state_sdrs (), + .jtag_state_sir (), + .jtag_state_sirs (), + .jtag_state_tlr (), + .jtag_state_udr (), + .jtag_state_uir (), + .tms () + // synopsys translate_on + ); + defparam + sld_virtual_jtag_component.sld_mfg_id = 110, + sld_virtual_jtag_component.sld_type_id = 132, + sld_virtual_jtag_component.sld_version = 1, + sld_virtual_jtag_component.sld_auto_instance_index = "YES", + sld_virtual_jtag_component.sld_instance_index = 0, + sld_virtual_jtag_component.sld_ir_width = IRWIDTH, + sld_virtual_jtag_component.sld_sim_action = "", + sld_virtual_jtag_component.sld_sim_n_scan = 0, + sld_virtual_jtag_component.sld_sim_total_length = 0; +`endif + +// PHY Simulation +`ifndef ALTERA_RESERVED_QIS + + localparam DATA = 0; + localparam LOOPBACK = 1; + localparam DEBUG = 2; + localparam INFO = 3; + localparam CONTROL = 4; + localparam MGMT = 5; + + always + //#TCK_HALF_PERIOD_US simulation_clock = $random; + #TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock; + + assign tck = simulation_clock; + assign virtual_state_cdr = cdr; + assign virtual_state_sdr = sdr; + assign virtual_state_e1dr = e1dr; + assign virtual_state_udr = udr; + + task reset_jtag_state; + begin + simulation_clock = 0; + enter_data_mode; + clear_states_async; + end + endtask + + task enter_data_mode; + begin + ir_in = DATA; + clear_states; + end + endtask + + task enter_loopback_mode; + begin + ir_in = LOOPBACK; + clear_states; + end + endtask + + task enter_debug_mode; + begin + ir_in = DEBUG; + clear_states; + end + endtask + + task enter_info_mode; + begin + ir_in = INFO; + clear_states; + end + endtask + + task enter_control_mode; + begin + ir_in = CONTROL; + clear_states; + end + endtask + + task enter_mgmt_mode; + begin + ir_in = MGMT; + clear_states; + end + endtask + + task enter_sdrs_state; + begin + {sdrs, cdr, sdr, e1dr, udr} = 5'b10000; + tdi = 1'b0; + @(posedge tck); + end + endtask + + task enter_cdr_state; + begin + {sdrs, cdr, sdr, e1dr, udr} = 5'b01000; + tdi = 1'b0; + @(posedge tck); + end + endtask + + task enter_e1dr_state; + begin + {sdrs, cdr, sdr, e1dr, udr} = 5'b00010; + tdi = 1'b0; + @(posedge tck); + end + endtask + + task enter_udr_state; + begin + {sdrs, cdr, sdr, e1dr, udr} = 5'b00001; + tdi = 1'b0; + @(posedge tck); + end + endtask + + task clear_states; + begin + clear_states_async; + @(posedge tck); + end + endtask + + task clear_states_async; + begin + {cdr, sdr, e1dr, udr} = 4'b0000; + end + endtask + + task shift_one_bit; + input bit_to_send; + output reg bit_received; + begin + {cdr, sdr, e1dr, udr} = 4'b0100; + tdi = bit_to_send; + @(posedge tck); + bit_received = tdo; + end + endtask + + task shift_one_byte; + input [7:0] byte_to_send; + output reg [7:0] byte_received; + integer i; + reg bit_received; + begin + for (i=0; i<8; i=i+1) + begin + bit_index = i; + shift_one_bit(byte_to_send[i], bit_received); + byte_received[i] = bit_received; + end + end + endtask + +`endif + +endmodule diff --git a/ip/altera/ddr3/altera_jtag_streaming.v b/ip/altera/ddr3/altera_jtag_streaming.v new file mode 100644 index 0000000..1fc0610 --- /dev/null +++ b/ip/altera/ddr3/altera_jtag_streaming.v @@ -0,0 +1,634 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// synopsys translate_off +`timescale 1 ns / 1 ns +// synopsys translate_on + +module altera_jtag_streaming #( + parameter PURPOSE = 0, + parameter UPSTREAM_FIFO_SIZE = 0, + parameter DOWNSTREAM_FIFO_SIZE = 0, + parameter MGMT_CHANNEL_WIDTH = -1 +) ( + // JTAG Signals + input wire tck, + input wire tdi, + output reg tdo, + input wire [2:0] ir_in, + input wire virtual_state_cdr, + input wire virtual_state_sdr, + input wire virtual_state_udr, + + input wire reset_n, + // Source Signals + output wire [7:0] source_data, + output wire source_valid, + // Sink Signals + input wire [7:0] sink_data, + input wire sink_valid, + output wire sink_ready, + // Clock Debug Signals + input wire clock_to_sample, + input wire reset_to_sample, + // Resetrequest signal + output reg resetrequest, + // Debug reset and management channel + output wire debug_reset, + output reg mgmt_valid, + output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel, + output reg mgmt_data +); + + // function to calculate log2, floored. + function integer flog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + if ( i <= 0 ) flog2 = 0; + else begin + for(flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + endfunction // flog2 + + localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE); + localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE); + + localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8; + localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3; + + // IR values determine the operating modes + localparam DATA = 0; + localparam LOOPBACK = 1; + localparam DEBUG = 2; + localparam INFO = 3; + localparam CONTROL = 4; + localparam MGMT = 5; + + // Operating Modes: + // Data - To send data which its size and valid position are encoded in the header bytes of the data stream + // Loopback - To become a JTAG loopback with a bypass register + // Debug - To read the values of the clock sensing, clock sampling and reset sampling + // Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver + // Control - To set the offset of bit-padding and to do a reset request + // Mgmt - Send management commands (resets mostly) to agents + + localparam IRWIDTH = 3; + + // State machine encoding for write_state + localparam ST_BYPASS = 'h0; + localparam ST_HEADER_1 = 'h1; + localparam ST_HEADER_2 = 'h2; + localparam ST_WRITE_DATA = 'h3; + + // State machine encoding for read_state + localparam ST_HEADER = 'h0; + localparam ST_PADDED = 'h1; + localparam ST_READ_DATA = 'h2; + + reg [1:0] write_state = ST_BYPASS; + reg [1:0] read_state = ST_HEADER; + + reg [ 7:0] dr_data_in = 'b0; + reg [ 7:0] dr_data_out = 'b0; + reg dr_loopback = 'b0; + reg [ 2:0] dr_debug = 'b0; + reg [10:0] dr_info = 'b0; + reg [ 8:0] dr_control = 'b0; + reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0; + + reg [ 8:0] padded_bit_counter = 'b0; + reg [ 7:0] bypass_bit_counter = 'b0; + reg [ 2:0] write_data_bit_counter = 'b0; + reg [ 2:0] read_data_bit_counter = 'b0; + reg [ 3:0] header_in_bit_counter = 'b0; + reg [ 3:0] header_out_bit_counter = 'b0; + reg [18:0] scan_length_byte_counter = 'b0; + reg [18:0] valid_write_data_length_byte_counter = 'b0; + + reg write_data_valid = 'b0; + reg read_data_valid = 'b0; + reg read_data_all_valid = 'b0; + + reg decode_header_1 = 'b0; + reg decode_header_2 = 'b0; + + wire write_data_byte_aligned; + wire read_data_byte_aligned; + wire padded_bit_byte_aligned; + wire bytestream_end; + + assign write_data_byte_aligned = (write_data_bit_counter == 1); + assign read_data_byte_aligned = (read_data_bit_counter == 1); + assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0); + assign bytestream_end = (scan_length_byte_counter == 'b0); + + reg [ 7:0] offset = 'b0; + reg [15:0] header_in = 'b0; + + reg [9:0] scan_length = 'b0; + reg [2:0] read_data_length = 'b0; + reg [2:0] write_data_length = 'b0; + + wire [7:0] idle_inserter_sink_data; + wire idle_inserter_sink_valid; + wire idle_inserter_sink_ready; + wire [7:0] idle_inserter_source_data; + reg idle_inserter_source_ready = 'b0; + reg [7:0] idle_remover_sink_data = 'b0; + reg idle_remover_sink_valid = 'b0; + wire [7:0] idle_remover_source_data; + wire idle_remover_source_valid; + + assign source_data = idle_remover_source_data; + assign source_valid = idle_remover_source_valid; + assign sink_ready = idle_inserter_sink_ready; + assign idle_inserter_sink_data = sink_data; + assign idle_inserter_sink_valid = sink_valid; + + reg clock_sensor = 'b0; + reg clock_to_sample_div2 = 'b0; + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1; + + wire data_available; + + assign data_available = sink_valid; + + wire [18:0] decoded_scan_length; + wire [18:0] decoded_write_data_length; + wire [18:0] decoded_read_data_length; + + assign decoded_scan_length = { scan_length, {8{1'b1}} }; + // +-------------------+----------------+---------------------+ + // | scan_length | Length (bytes) | decoded_scan_length | + // +-------------------+----------------+---------------------+ + // | 0x0 | 256 | 0x0ff (255) | + // | 0x1 | 512 | 0x1ff (511) | + // | 0x2 | 768 | 0x2ff (767) | + // | . | . | . | + // | 0x3ff | 256k | 0x3ff (256k-1) | + // +-------------------+----------------+---------------------+ + + // TODO: use look up table to save LEs? + // Decoded value is correct except for 0x7 + assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length); + assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length); + // +-------------------+---------------+---------------------------+ + // | read_data_length | Length | decoded_read_data_length | + // | write_data_length | (bytes) | decoded_write_data_length | + // +-------------------+---------------+---------------------------+ + // | 0x0 | 0 | 0x0000 (0) | + // | 0x1 | 256 | 0x0100 (256) | + // | 0x2 | 512 | 0x0200 (512) | + // | 0x3 | 1k | 0x0400 (1024) | + // | 0x4 | 2k | 0x0800 (2048) | + // | 0x5 | 4k | 0x1000 (4096) | + // | 0x6 | 8k | 0x2000 (8192) | + // | 0x7 | scan_length | invalid | + // +-------------------+---------------+---------------------------+ + + wire clock_sensor_sync; + wire reset_to_sample_sync; + wire clock_to_sample_div2_sync; + wire clock_sense_reset_n_sync; + + + altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer ( + .clk(tck), + .reset_n(1'b1), + .din(clock_sensor), + .dout(clock_sensor_sync)); + + altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer ( + .clk(tck), + .reset_n(1'b1), + .din(reset_to_sample), + .dout(reset_to_sample_sync)); + + altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer ( + .clk(tck), + .reset_n(1'b1), + .din(clock_to_sample_div2), + .dout(clock_to_sample_div2_sync)); + + altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer ( + .clk(clock_to_sample), + .reset_n(clock_sense_reset_n), + .din(1'b1), + .dout(clock_sense_reset_n_sync)); + + always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin + if (~clock_sense_reset_n_sync) begin + clock_sensor <= 1'b0; + end else begin + clock_sensor <= 1'b1; + end + end + + always @ (posedge clock_to_sample) begin + clock_to_sample_div2 <= ~clock_to_sample_div2; + end + + always @ (posedge tck) begin + + idle_remover_sink_valid <= 1'b0; + idle_inserter_source_ready <= 1'b0; + + // Data mode sourcing (write) + + // offset(rounded 8) m-i i 16 offset + // +------------+-----------+------------------+--------+------------+ + // tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit | + // +------------+-----------+------------------+--------+------------+ + // Data mode DR data stream write format (as seen by hardware) + // + if (ir_in == DATA) begin + + + if (virtual_state_cdr) begin + if (offset == 'b0) begin + write_state <= ST_HEADER_1; + end else begin + write_state <= ST_BYPASS; + end + // 8-bit bypass_bit_counter + bypass_bit_counter <= offset; + // 4-bit header_in_bit_counter + header_in_bit_counter <= 15; + // 3-bit write_data_bit_counter + write_data_bit_counter <= 0; + // Reset the registers + // TODO: not necessarily all, reduce LE + decode_header_1 <= 1'b0; + decode_header_2 <= 1'b0; + read_data_all_valid <= 1'b0; + valid_write_data_length_byte_counter <= 0; + end + + if (virtual_state_sdr) begin + // Discard bypass bits, then decode the 16-bit header + // 3 3 10 + // +-------------------+------------------+-------------+ + // | write_data_length | read_data_length | scan_length | + // +-------------------+------------------+-------------+ + // Header format + + case (write_state) + ST_BYPASS: begin + // Discard the bypass bit + bypass_bit_counter <= bypass_bit_counter - 1'b1; + if (bypass_bit_counter == 1) begin + write_state <= ST_HEADER_1; + end + end + // Shift the scan_length and read_data_length + ST_HEADER_1: begin + // TODO: header_in can be shorter + // Shift into header_in + header_in <= {tdi, header_in[15:1]}; + header_in_bit_counter <= header_in_bit_counter - 1'b1; + if (header_in_bit_counter == 3) begin + read_data_length <= {tdi, header_in[15:14]}; + scan_length <= header_in[13:4]; + write_state <= ST_HEADER_2; + decode_header_1 <= 1'b1; + end + end + // Shift the write_data_length + ST_HEADER_2: begin + // Shift into header_in + header_in <= {tdi, header_in[15:1]}; + header_in_bit_counter <= header_in_bit_counter - 1'b1; + // Decode read_data_length and scan_length + if (decode_header_1) begin + decode_header_1 <= 1'b0; + // Set read_data_all_valid + if (read_data_length == 3'b111) begin + read_data_all_valid <= 1'b1; + end + // Load scan_length_byte_counter + scan_length_byte_counter <= decoded_scan_length; + end + if (header_in_bit_counter == 0) begin + write_data_length <= {tdi, header_in[15:14]}; + write_state <= ST_WRITE_DATA; + decode_header_2 <= 1'b1; + end + end + // Shift the valid_write_data + ST_WRITE_DATA: begin + // Shift into dr_data_in + dr_data_in <= {tdi, dr_data_in[7:1]}; + // Decode write_data_length + if (decode_header_2) begin + decode_header_2 <= 1'b0; + // Load valid_write_data_length_byte_counter + case (write_data_length) + 3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1; + 3'b000: valid_write_data_length_byte_counter <= 'b0; + default: valid_write_data_length_byte_counter <= decoded_write_data_length; + endcase + end + write_data_bit_counter <= write_data_bit_counter - 1'b1; + write_data_valid <= (valid_write_data_length_byte_counter != 0); + // Feed the data to the idle remover + if (write_data_byte_aligned && write_data_valid) begin + valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1; + idle_remover_sink_valid <= 1'b1; + idle_remover_sink_data <= {tdi, dr_data_in[7:1]}; + end + end + endcase + end + + end + + // Data mode sinking (read) + + // i m-i offset(rounded 8) 16 + // +-----------------+-----------+------------+--------+ + // | valid_read_data | undefined | padded_bit | header | -> tdo + // +-----------------+-----------+------------+--------+ + // Data mode DR data stream read format (as seen by hardware) + // + if (ir_in == DATA) begin + + if (virtual_state_cdr) begin + + read_state <= ST_HEADER; + // Offset is rounded to nearest ceiling x8 to byte-align padded bits + // 9-bit padded_bit_counter + if (|offset[2:0]) begin + padded_bit_counter[8:3] <= offset[7:3] + 1'b1; + padded_bit_counter[2:0] <= 3'b0; + end else begin + padded_bit_counter <= {1'b0, offset}; + end + // 4-bit header_out_bit_counter + header_out_bit_counter <= 0; + // 3-bit read_data_bit_counter + read_data_bit_counter <= 0; + // Load the data_available bit into header + dr_data_out <= {{7{1'b0}}, data_available}; + read_data_valid <= 0; + + end + + if (virtual_state_sdr) begin + // 10 1 + // +-----------------------------------+----------------+ + // | reserved | data_available | + // +-----------------------------------+----------------+ + // Header format + + dr_data_out <= {1'b0, dr_data_out[7:1]}; + case (read_state) + // Shift the scan_length and read_data_length + ST_HEADER: begin + header_out_bit_counter <= header_out_bit_counter - 1'b1; + // Retrieve data from idle inserter for the next shift if no paddded bits + if (header_out_bit_counter == 2) begin + if (padded_bit_counter == 0) begin + idle_inserter_source_ready <= read_data_all_valid; + end + end + if (header_out_bit_counter == 1) begin + if (padded_bit_counter == 0) begin + read_state <= ST_READ_DATA; + read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1); + dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a; + end else begin + read_state <= ST_PADDED; + padded_bit_counter <= padded_bit_counter - 1'b1; + idle_inserter_source_ready <= 1'b0; + dr_data_out <= 8'h4a; + end + end + end + ST_PADDED: begin + padded_bit_counter <= padded_bit_counter - 1'b1; + if (padded_bit_byte_aligned) begin + // Load idle character into data register + dr_data_out <= 8'h4a; + end + // Retrieve data from idle inserter for the next shift when padded bits finish + if (padded_bit_counter == 1) begin + idle_inserter_source_ready <= read_data_all_valid; + end + if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned) + read_state <= ST_READ_DATA; + read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1); + dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a; + end + end + ST_READ_DATA: begin + read_data_bit_counter <= read_data_bit_counter - 1'b1; + // Retrieve data from idle inserter just before read_data_byte_aligned + if (read_data_bit_counter == 2) begin + // Assert ready to retrieve data from idle inserter only when the bytestream has not ended, + // data is valid (idle_inserter is always valid) and data is needed (read_data_valid) + idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid; + end + if (read_data_byte_aligned) begin + // Note that bytestream_end is driven by scan_length_byte_counter + if (~bytestream_end) begin + scan_length_byte_counter <= scan_length_byte_counter - 1'b1; + end + read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1); + // Load idle character if bytestream has ended, else get data from the idle inserter + dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a; + end + end + endcase + + end + + end + + // Loopback mode + if (ir_in == LOOPBACK) begin + if (virtual_state_cdr) begin + dr_loopback <= 1'b0; // capture 0 + end + if (virtual_state_sdr) begin + // Shift dr_loopback + dr_loopback <= tdi; + end + end + + // Debug mode + if (ir_in == DEBUG) begin + if (virtual_state_cdr) begin + dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync}; + end + if (virtual_state_sdr) begin + // Shift dr_debug + dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored + end + if (virtual_state_udr) begin + clock_sense_reset_n <= 1'b0; + end else begin + clock_sense_reset_n <= 1'b1; + end + end + + // Info mode + if (ir_in == INFO) begin + if (virtual_state_cdr) begin + dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]}; + end + if (virtual_state_sdr) begin + // Shift dr_info + dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored + end + end + + // Control mode + if (ir_in == CONTROL) begin + if (virtual_state_cdr) begin + dr_control <= 'b0; // capture 0 + end + if (virtual_state_sdr) begin + // Shift dr_control + dr_control <= {tdi, dr_control[8:1]}; + end + if (virtual_state_udr) begin + // Update resetrequest and offset + {resetrequest, offset} <= dr_control; + end + end + + end + + always @ * begin + if (virtual_state_sdr) begin + case (ir_in) + DATA: tdo <= dr_data_out[0]; + LOOPBACK: tdo <= dr_loopback; + DEBUG: tdo <= dr_debug[0]; + INFO: tdo <= dr_info[0]; + CONTROL: tdo <= dr_control[0]; + MGMT: tdo <= dr_mgmt[0]; + default: tdo <= 1'b0; + endcase + end else begin + tdo <= 1'b0; + end + end + + // Idle Remover + altera_avalon_st_idle_remover idle_remover ( + // Interface: clk + .clk (tck), + .reset_n (reset_n), + + // Interface: ST in + .in_ready (), // left disconnected + .in_valid (idle_remover_sink_valid), + .in_data (idle_remover_sink_data), + + // Interface: ST out + .out_ready (1'b1), // downstream is expected to be always ready + .out_valid (idle_remover_source_valid), + .out_data (idle_remover_source_data) + ); + + // Idle Inserter + altera_avalon_st_idle_inserter idle_inserter ( + // Interface: clk + .clk (tck), + .reset_n (reset_n), + + // Interface: ST in + .in_ready (idle_inserter_sink_ready), + .in_valid (idle_inserter_sink_valid), + .in_data (idle_inserter_sink_data), + + // Interface: ST out + .out_ready (idle_inserter_source_ready), + .out_valid (), + .out_data (idle_inserter_source_data) + ); + + generate + if (MGMT_CHANNEL_WIDTH > 0) + begin : has_mgmt + reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0; + reg mgmt_toggle = 1'b0; + wire mgmt_toggle_sync; + reg mgmt_toggle_prev; + always @ (posedge tck) begin + // Debug mode + if (ir_in == MGMT) begin + if (virtual_state_cdr) begin + dr_mgmt <= 'b0; + dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1; + end + if (virtual_state_sdr) begin + // Shift dr_debug + dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]}; + end + if (virtual_state_udr) begin + mgmt_out <= dr_mgmt; + mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle; + end + end + end + + altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer ( + .clk(clock_to_sample), + .reset_n(1'b1), + .din(mgmt_out[MGMT_CHANNEL_WIDTH+2]), + .dout(debug_reset)); + + altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_toggle_synchronizer ( + .clk(clock_to_sample), + .reset_n(1'b1), + .din(mgmt_toggle), + .dout(mgmt_toggle_sync)); + + always @ (posedge clock_to_sample or posedge debug_reset) begin + if (debug_reset) begin + mgmt_valid <= 1'b0; + mgmt_toggle_prev <= 1'b0; + end else begin + if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out[MGMT_CHANNEL_WIDTH+1]) begin + mgmt_valid <= 1'b1; + mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1]; + mgmt_data <= mgmt_out[0]; + end else begin + mgmt_valid <= 1'b0; + end + mgmt_toggle_prev <= mgmt_toggle_sync; + end + end + + end + else + begin : no_mgmt + always @ (posedge tck) begin + dr_mgmt[0] <= 1'b0; + end + assign debug_reset = 1'b0; + always @ (posedge clock_to_sample) begin + mgmt_valid <= 1'b0; + mgmt_data <= 'b0; + mgmt_channel <= 'b0; + end + end + endgenerate + +endmodule diff --git a/ip/altera/ddr3/altera_mem_if_dll_cyclonev.sv b/ip/altera/ddr3/altera_mem_if_dll_cyclonev.sv new file mode 100644 index 0000000..7381b7f --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_dll_cyclonev.sv @@ -0,0 +1,83 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// ******************************************************************************************************************************** +// This file instantiates the DLL. +// ******************************************************************************************************************************** + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_dll; -name IP_TOOL_VERSION 15.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) + + +module altera_mem_if_dll_cyclonev ( + clk, + + + dll_pll_locked, + dll_delayctrl +); + + +parameter DLL_DELAY_CTRL_WIDTH = 0; +parameter DELAY_BUFFER_MODE = ""; +parameter DELAY_CHAIN_LENGTH = 0; +parameter DLL_INPUT_FREQUENCY_PS_STR = ""; +parameter DLL_OFFSET_CTRL_WIDTH = 0; + + +input clk; // DLL input clock +input dll_pll_locked; +output [DLL_DELAY_CTRL_WIDTH-1:0] dll_delayctrl; + + +wire wire_dll_wys_m_offsetdelayctrlclkout; +wire [DLL_DELAY_CTRL_WIDTH-1:0] wire_dll_wys_m_offsetdelayctrlout; +wire dll_aload; + +assign dll_aload = ~dll_pll_locked; + + + + cyclonev_dll dll_wys_m( + .clk(clk), + .aload(dll_aload), + .delayctrlout(dll_delayctrl), + .dqsupdate(), + .locked(), + .upndnout(), + .dftcore() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .upndnin(1'b1), + .upndninclkena(1'b1) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + // synopsys translate_off + , + .dffin() + // synopsys translate_on + ); + defparam dll_wys_m.input_frequency = DLL_INPUT_FREQUENCY_PS_STR; + defparam dll_wys_m.jitter_reduction = "true"; + defparam dll_wys_m.static_delay_ctrl = DELAY_CHAIN_LENGTH; + defparam dll_wys_m.lpm_type = "cyclonev_dll"; + + + + +endmodule + diff --git a/ip/altera/ddr3/altera_mem_if_hard_memory_controller_top_cyclonev.sv b/ip/altera/ddr3/altera_mem_if_hard_memory_controller_top_cyclonev.sv new file mode 100644 index 0000000..0627281 --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_hard_memory_controller_top_cyclonev.sv @@ -0,0 +1,1889 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100" *) +module altera_mem_if_hard_memory_controller_top_cyclonev ( + afi_clk, + afi_half_clk, + ctl_clk, + mp_cmd_clk_0, + mp_cmd_clk_1, + mp_cmd_clk_2, + mp_cmd_clk_3, + mp_cmd_clk_4, + mp_cmd_clk_5, + mp_cmd_reset_n_0, + mp_cmd_reset_n_1, + mp_cmd_reset_n_2, + mp_cmd_reset_n_3, + mp_cmd_reset_n_4, + mp_cmd_reset_n_5, + mp_rfifo_clk_0, + mp_rfifo_clk_1, + mp_rfifo_clk_2, + mp_rfifo_clk_3, + mp_rfifo_reset_n_0, + mp_rfifo_reset_n_1, + mp_rfifo_reset_n_2, + mp_rfifo_reset_n_3, + mp_wfifo_clk_0, + mp_wfifo_clk_1, + mp_wfifo_clk_2, + mp_wfifo_clk_3, + mp_wfifo_reset_n_0, + mp_wfifo_reset_n_1, + mp_wfifo_reset_n_2, + mp_wfifo_reset_n_3, + csr_clk, + csr_reset_n, + afi_reset_n, + ctl_reset_n, + avl_ready_0, + avl_write_req_0, + avl_read_req_0, + avl_addr_0, + avl_be_0, + avl_wdata_0, + avl_size_0, + avl_burstbegin_0, + avl_rdata_0, + avl_rdata_valid_0, + avl_ready_1, + avl_write_req_1, + avl_read_req_1, + avl_addr_1, + avl_be_1, + avl_wdata_1, + avl_size_1, + avl_burstbegin_1, + avl_rdata_1, + avl_rdata_valid_1, + avl_ready_2, + avl_write_req_2, + avl_read_req_2, + avl_addr_2, + avl_be_2, + avl_wdata_2, + avl_size_2, + avl_burstbegin_2, + avl_rdata_2, + avl_rdata_valid_2, + avl_ready_3, + avl_write_req_3, + avl_read_req_3, + avl_addr_3, + avl_be_3, + avl_wdata_3, + avl_size_3, + avl_burstbegin_3, + avl_rdata_3, + avl_rdata_valid_3, + avl_ready_4, + avl_write_req_4, + avl_read_req_4, + avl_addr_4, + avl_be_4, + avl_wdata_4, + avl_size_4, + avl_burstbegin_4, + avl_rdata_4, + avl_rdata_valid_4, + avl_ready_5, + avl_write_req_5, + avl_read_req_5, + avl_addr_5, + avl_be_5, + avl_wdata_5, + avl_size_5, + avl_burstbegin_5, + avl_rdata_5, + avl_rdata_valid_5, + afi_rst_n, + afi_cs_n, + afi_cke, + afi_odt, + afi_addr, + afi_ba, + afi_ras_n, + afi_cas_n, + afi_we_n, + afi_dqs_burst, + afi_wdata_valid, + afi_wdata, + afi_dm, + afi_wlat, + afi_rdata_en, + afi_rdata_en_full, + afi_rdata, + afi_rdata_valid, + afi_rlat, + afi_cal_success, + afi_mem_clk_disable, + afi_ctl_refresh_done, + afi_seq_busy, + afi_ctl_long_idle, + afi_cal_fail, + afi_cal_req, + afi_init_req, + cfg_dramconfig, + cfg_caswrlat, + cfg_addlat, + cfg_tcl, + cfg_trfc, + cfg_trefi, + cfg_twr, + cfg_tmrd, + cfg_coladdrwidth, + cfg_rowaddrwidth, + cfg_bankaddrwidth, + cfg_csaddrwidth, + cfg_interfacewidth, + cfg_devicewidth, + local_refresh_ack, + local_powerdn_ack, + local_self_rfsh_ack, + local_deep_powerdn_ack, + local_refresh_req, + local_refresh_chip, + local_self_rfsh_req, + local_self_rfsh_chip, + local_deep_powerdn_req, + local_deep_powerdn_chip, + local_multicast, + local_priority, + local_init_done, + local_cal_success, + local_cal_fail, + csr_read_req, + csr_write_req, + csr_addr, + csr_wdata, + csr_rdata, + csr_be, + csr_rdata_valid, + csr_waitrequest, + bonding_out_1, + bonding_in_1, + bonding_out_2, + bonding_in_2, + bonding_out_3, + bonding_in_3, + io_intaficalfail, + ctl_init_req, + local_sts_ctl_empty, + io_intaficalsuccess +); + +////////////////////////////////////////////////////////////////////////////// +// BEGIN PARAMETER SECTION + +// Existing SIP parameters +parameter AVL_SIZE_WIDTH = 0; +parameter AVL_ADDR_WIDTH = 0; +parameter AVL_DATA_WIDTH = 0; +parameter MEM_IF_CLK_PAIR_COUNT = 0; +parameter MEM_IF_CS_WIDTH = 0; +parameter MEM_IF_DQS_WIDTH = 0; +parameter MEM_IF_CHIP_BITS = 0; +parameter AFI_ADDR_WIDTH = 0; +parameter AFI_BANKADDR_WIDTH = 0; +parameter AFI_CONTROL_WIDTH = 0; +parameter AFI_CS_WIDTH = 0; +parameter AFI_ODT_WIDTH = 0; +parameter AFI_DM_WIDTH = 0; +parameter AFI_DQ_WIDTH = 0; +parameter AFI_WRITE_DQS_WIDTH = 0; +parameter AFI_RATE_RATIO = 0; +parameter AFI_WLAT_WIDTH = 0; +parameter AFI_RLAT_WIDTH = 0; +parameter CSR_BE_WIDTH = 0; +parameter CSR_ADDR_WIDTH = 0; +parameter CSR_DATA_WIDTH = 0; + +// New parameters for HMC +parameter AVL_DATA_WIDTH_PORT_0 = 0; +parameter AVL_DATA_WIDTH_PORT_1 = 0; +parameter AVL_DATA_WIDTH_PORT_2 = 0; +parameter AVL_DATA_WIDTH_PORT_3 = 0; +parameter AVL_DATA_WIDTH_PORT_4 = 0; +parameter AVL_DATA_WIDTH_PORT_5 = 0; +parameter AVL_ADDR_WIDTH_PORT_0 = 0; +parameter AVL_ADDR_WIDTH_PORT_1 = 0; +parameter AVL_ADDR_WIDTH_PORT_2 = 0; +parameter AVL_ADDR_WIDTH_PORT_3 = 0; +parameter AVL_ADDR_WIDTH_PORT_4 = 0; +parameter AVL_ADDR_WIDTH_PORT_5 = 0; +parameter AVL_NUM_SYMBOLS_PORT_0 = 0; +parameter AVL_NUM_SYMBOLS_PORT_1 = 0; +parameter AVL_NUM_SYMBOLS_PORT_2 = 0; +parameter AVL_NUM_SYMBOLS_PORT_3 = 0; +parameter AVL_NUM_SYMBOLS_PORT_4 = 0; +parameter AVL_NUM_SYMBOLS_PORT_5 = 0; +parameter LSB_WFIFO_PORT_0 = 5; +parameter MSB_WFIFO_PORT_0 = 5; +parameter LSB_RFIFO_PORT_0 = 5; +parameter MSB_RFIFO_PORT_0 = 5; +parameter LSB_WFIFO_PORT_1 = 5; +parameter MSB_WFIFO_PORT_1 = 5; +parameter LSB_RFIFO_PORT_1 = 5; +parameter MSB_RFIFO_PORT_1 = 5; +parameter LSB_WFIFO_PORT_2 = 5; +parameter MSB_WFIFO_PORT_2 = 5; +parameter LSB_RFIFO_PORT_2 = 5; +parameter MSB_RFIFO_PORT_2 = 5; +parameter LSB_WFIFO_PORT_3 = 5; +parameter MSB_WFIFO_PORT_3 = 5; +parameter LSB_RFIFO_PORT_3 = 5; +parameter MSB_RFIFO_PORT_3 = 5; +parameter LSB_WFIFO_PORT_4 = 5; +parameter MSB_WFIFO_PORT_4 = 5; +parameter LSB_RFIFO_PORT_4 = 5; +parameter MSB_RFIFO_PORT_4 = 5; +parameter LSB_WFIFO_PORT_5 = 5; +parameter MSB_WFIFO_PORT_5 = 5; +parameter LSB_RFIFO_PORT_5 = 5; +parameter MSB_RFIFO_PORT_5 = 5; +parameter HARD_PHY = 0; + +// Atom defparam +// Those that mark with // SYTH & SIM is used to force MMR signals in simulation +// Those that mark with // SYTH ONLY is only used for Quartus sythesis +parameter ENUM_ATTR_COUNTER_ONE_RESET = "DISABLED"; //SYTH & SIM +parameter ENUM_ATTR_COUNTER_ZERO_RESET = "DISABLED"; //SYTH & SIM +parameter ENUM_ATTR_STATIC_CONFIG_VALID = "DISABLED"; //SYTH & SIM +parameter ENUM_AUTO_PCH_ENABLE_0 = "DISABLED"; //SYTH & SIM +parameter ENUM_AUTO_PCH_ENABLE_1 = "DISABLED"; //SYTH & SIM +parameter ENUM_AUTO_PCH_ENABLE_2 = "DISABLED"; //SYTH & SIM +parameter ENUM_AUTO_PCH_ENABLE_3 = "DISABLED"; //SYTH & SIM +parameter ENUM_AUTO_PCH_ENABLE_4 = "DISABLED"; //SYTH & SIM +parameter ENUM_AUTO_PCH_ENABLE_5 = "DISABLED"; //SYTH & SIM +parameter ENUM_CAL_REQ = "DISABLED"; //SYTH & SIM +parameter ENUM_CFG_BURST_LENGTH = "BL_8"; //SYTH & SIM +parameter ENUM_CFG_INTERFACE_WIDTH = "DWIDTH_32"; //SYTH & SIM +parameter ENUM_CFG_SELF_RFSH_EXIT_CYCLES = "SELF_RFSH_EXIT_CYCLES_512"; //SYTH & SIM +parameter ENUM_CFG_STARVE_LIMIT = "STARVE_LIMIT_32"; //SYTH & SIM +parameter ENUM_CFG_TYPE = "DDR3"; //SYTH & SIM +parameter ENUM_CLOCK_OFF_0 = "DISABLED"; //SIM ONLY +parameter ENUM_CLOCK_OFF_1 = "DISABLED"; //SIM ONLY +parameter ENUM_CLOCK_OFF_2 = "DISABLED"; //SIM ONLY +parameter ENUM_CLOCK_OFF_3 = "DISABLED"; //SIM ONLY +parameter ENUM_CLOCK_OFF_4 = "DISABLED"; //SIM ONLY +parameter ENUM_CLOCK_OFF_5 = "DISABLED"; //SIM ONLY +parameter ENUM_CLR_INTR = "NO_CLR_INTR"; //SIM ONLY +parameter ENUM_CMD_PORT_IN_USE_0 = "FALSE"; //SYTH ONLY +parameter ENUM_CMD_PORT_IN_USE_1 = "FALSE"; //SYTH ONLY +parameter ENUM_CMD_PORT_IN_USE_2 = "FALSE"; //SYTH ONLY +parameter ENUM_CMD_PORT_IN_USE_3 = "FALSE"; //SYTH ONLY +parameter ENUM_CMD_PORT_IN_USE_4 = "FALSE"; //SYTH ONLY +parameter ENUM_CMD_PORT_IN_USE_5 = "FALSE"; //SYTH ONLY +parameter ENUM_CPORT0_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_CPORT0_RFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT0_TYPE = "DISABLE"; //SYTH & SIM +parameter ENUM_CPORT0_WFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT1_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_CPORT1_RFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT1_TYPE = "DISABLE"; //SYTH & SIM +parameter ENUM_CPORT1_WFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT2_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_CPORT2_RFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT2_TYPE = "DISABLE"; //SYTH & SIM +parameter ENUM_CPORT2_WFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT3_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_CPORT3_RFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT3_TYPE = "DISABLE"; //SYTH & SIM +parameter ENUM_CPORT3_WFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT4_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_CPORT4_RFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT4_TYPE = "DISABLE"; //SYTH & SIM +parameter ENUM_CPORT4_WFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT5_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_CPORT5_RFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CPORT5_TYPE = "DISABLE"; //SYTH & SIM +parameter ENUM_CPORT5_WFIFO_MAP = "FIFO_0"; //SYTH & SIM +parameter ENUM_CTL_ADDR_ORDER = "CHIP_BANK_ROW_COL"; //SYTH & SIM +parameter ENUM_CTL_ECC_ENABLED = "CTL_ECC_DISABLED"; //SYTH & SIM +parameter ENUM_CTL_ECC_RMW_ENABLED = "CTL_ECC_RMW_DISABLED"; //SYTH & SIM +parameter ENUM_CTL_REGDIMM_ENABLED = "REGDIMM_DISABLED"; //SIM ONLY +parameter ENUM_CTL_USR_REFRESH = "CTL_USR_REFRESH_DISABLED"; //SYTH & SIM +parameter ENUM_CTRL_WIDTH = "DATA_WIDTH_64_BIT"; //SYTH & SIM +parameter ENUM_DELAY_BONDING = "BONDING_LATENCY_0"; //SYTH & SIM +parameter ENUM_DFX_BYPASS_ENABLE = "DFX_BYPASS_DISABLED"; //SYTH & SIM +parameter ENUM_DISABLE_MERGING = "MERGING_ENABLED"; //SIM ONLY +parameter ENUM_ECC_DQ_WIDTH = "ECC_DQ_WIDTH_0"; //SYTH ONLY +parameter ENUM_ENABLE_ATPG = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BONDING_0 = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BONDING_1 = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BONDING_2 = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BONDING_3 = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BONDING_4 = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BONDING_5 = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BONDING_WRAPBACK = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_DQS_TRACKING = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_ECC_CODE_OVERWRITES = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_FAST_EXIT_PPD = "DISABLED"; //SYTH ONLY +parameter ENUM_ENABLE_INTR = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_NO_DM = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_PIPELINEGLOBAL = "DISABLED"; //SYTH & SIM +parameter ENUM_GANGED_ARF = "DISABLED"; //SIM ONLY +parameter ENUM_GEN_DBE = "GEN_DBE_DISABLED"; //SIM ONLY +parameter ENUM_GEN_SBE = "GEN_SBE_DISABLED"; //SIM ONLY +parameter ENUM_INC_SYNC = "FIFO_SET_2"; //SYTH & SIM +parameter ENUM_LOCAL_IF_CS_WIDTH = "ADDR_WIDTH_2"; //SYTH & SIM +parameter ENUM_MASK_CORR_DROPPED_INTR = "DISABLED"; //SYTH & SIM +parameter ENUM_MASK_DBE_INTR = "DISABLED"; //SYTH & SIM +parameter ENUM_MASK_SBE_INTR = "DISABLED"; //SYTH & SIM +parameter ENUM_MEM_IF_AL = "AL_0"; //SYTH & SIM +parameter ENUM_MEM_IF_BANKADDR_WIDTH = "ADDR_WIDTH_3"; //SYTH & SIM +parameter ENUM_MEM_IF_BURSTLENGTH = "MEM_IF_BURSTLENGTH_8"; //SYTH ONLY +parameter ENUM_MEM_IF_COLADDR_WIDTH = "ADDR_WIDTH_12"; //SYTH & SIM +parameter ENUM_MEM_IF_CS_PER_RANK = "MEM_IF_CS_PER_RANK_1"; //SYTH ONLY +parameter ENUM_MEM_IF_CS_WIDTH = "MEM_IF_CS_WIDTH_1"; //SYTH ONLY +parameter ENUM_MEM_IF_DQ_PER_CHIP = "MEM_IF_DQ_PER_CHIP_8"; //SYTH ONLY +parameter ENUM_MEM_IF_DQS_WIDTH = "DQS_WIDTH_4"; //SYTH & SIM +parameter ENUM_MEM_IF_DWIDTH = "MEM_IF_DWIDTH_32"; //SYTH ONLY +parameter ENUM_MEM_IF_MEMTYPE = "DDR3_SDRAM"; //SYTH ONLY +parameter ENUM_MEM_IF_ROWADDR_WIDTH = "ADDR_WIDTH_16"; //SYTH & SIM +parameter ENUM_MEM_IF_SPEEDBIN = "DDR3_1066_6_6_6"; //SYTH ONLY +parameter ENUM_MEM_IF_TCCD = "TCCD_4"; //SYTH & SIM +parameter ENUM_MEM_IF_TCL = "TCL_6"; //SYTH & SIM +parameter ENUM_MEM_IF_TCWL = "TCWL_5"; //SYTH & SIM +parameter ENUM_MEM_IF_TFAW = "TFAW_16"; //SYTH & SIM +parameter ENUM_MEM_IF_TMRD = "TMRD_4"; //SYTH & SIM +parameter ENUM_MEM_IF_TRAS = "TRAS_16"; //SYTH & SIM +parameter ENUM_MEM_IF_TRC = "TRC_22"; //SYTH & SIM +parameter ENUM_MEM_IF_TRCD = "TRCD_6"; //SYTH & SIM +parameter ENUM_MEM_IF_TRP = "TRP_6"; //SYTH & SIM +parameter ENUM_MEM_IF_TRRD = "TRRD_4"; //SYTH & SIM +parameter ENUM_MEM_IF_TRTP = "TRTP_4"; //SYTH & SIM +parameter ENUM_MEM_IF_TWR = "TWR_6"; //SYTH & SIM +parameter ENUM_MEM_IF_TWTR = "TWTR_4"; //SYTH & SIM +parameter ENUM_MMR_CFG_MEM_BL = "MP_BL_8"; //SYTH & SIM +parameter ENUM_OUTPUT_REGD = "DISABLED"; //SYTH & SIM +parameter ENUM_PDN_EXIT_CYCLES = "SLOW_EXIT"; //SYTH & SIM +parameter ENUM_PORT0_WIDTH = "PORT_64_BIT"; //SYTH & SIM +parameter ENUM_PORT1_WIDTH = "PORT_64_BIT"; //SYTH & SIM +parameter ENUM_PORT2_WIDTH = "PORT_64_BIT"; //SYTH & SIM +parameter ENUM_PORT3_WIDTH = "PORT_64_BIT"; //SYTH & SIM +parameter ENUM_PORT4_WIDTH = "PORT_64_BIT"; //SYTH & SIM +parameter ENUM_PORT5_WIDTH = "PORT_64_BIT"; //SYTH & SIM +parameter ENUM_PRIORITY_0_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_0_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_0_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_0_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_0_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_0_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_1_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_1_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_1_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_1_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_1_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_1_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_2_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_2_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_2_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_2_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_2_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_2_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_3_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_3_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_3_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_3_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_3_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_3_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_4_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_4_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_4_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_4_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_4_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_4_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_5_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_5_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_5_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_5_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_5_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_5_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_6_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_6_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_6_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_6_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_6_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_6_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_7_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_7_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_7_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_7_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_7_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_PRIORITY_7_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_RCFG_STATIC_WEIGHT_0 = "WEIGHT_0"; //SYTH & SIM +parameter ENUM_RCFG_STATIC_WEIGHT_1 = "WEIGHT_0"; //SYTH & SIM +parameter ENUM_RCFG_STATIC_WEIGHT_2 = "WEIGHT_0"; //SYTH & SIM +parameter ENUM_RCFG_STATIC_WEIGHT_3 = "WEIGHT_0"; //SYTH & SIM +parameter ENUM_RCFG_STATIC_WEIGHT_4 = "WEIGHT_0"; //SYTH & SIM +parameter ENUM_RCFG_STATIC_WEIGHT_5 = "WEIGHT_0"; //SYTH & SIM +parameter ENUM_RCFG_USER_PRIORITY_0 = "PRIORITY_0"; //SYTH & SIM +parameter ENUM_RCFG_USER_PRIORITY_1 = "PRIORITY_0"; //SYTH & SIM +parameter ENUM_RCFG_USER_PRIORITY_2 = "PRIORITY_0"; //SYTH & SIM +parameter ENUM_RCFG_USER_PRIORITY_3 = "PRIORITY_0"; //SYTH & SIM +parameter ENUM_RCFG_USER_PRIORITY_4 = "PRIORITY_0"; //SYTH & SIM +parameter ENUM_RCFG_USER_PRIORITY_5 = "PRIORITY_0"; //SYTH & SIM +parameter ENUM_RD_DWIDTH_0 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_RD_DWIDTH_1 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_RD_DWIDTH_2 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_RD_DWIDTH_3 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_RD_DWIDTH_4 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_RD_DWIDTH_5 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_RD_FIFO_IN_USE_0 = "FALSE"; //SYTH ONLY +parameter ENUM_RD_FIFO_IN_USE_1 = "FALSE"; //SYTH ONLY +parameter ENUM_RD_FIFO_IN_USE_2 = "FALSE"; //SYTH ONLY +parameter ENUM_RD_FIFO_IN_USE_3 = "FALSE"; //SYTH ONLY +parameter ENUM_RD_PORT_INFO_0 = "USE_NO"; //SYTH ONLY +parameter ENUM_RD_PORT_INFO_1 = "USE_NO"; //SYTH ONLY +parameter ENUM_RD_PORT_INFO_2 = "USE_NO"; //SYTH ONLY +parameter ENUM_RD_PORT_INFO_3 = "USE_NO"; //SYTH ONLY +parameter ENUM_RD_PORT_INFO_4 = "USE_NO"; //SYTH ONLY +parameter ENUM_RD_PORT_INFO_5 = "USE_NO"; //SYTH ONLY +parameter ENUM_READ_ODT_CHIP = "ODT_DISABLED"; //SYTH & SIM +parameter ENUM_REORDER_DATA = "DATA_REORDERING"; //SYTH & SIM +parameter ENUM_RFIFO0_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_RFIFO1_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_RFIFO2_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_RFIFO3_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_SINGLE_READY_0 = "CONCATENATE_RDY"; //SYTH & SIM +parameter ENUM_SINGLE_READY_1 = "CONCATENATE_RDY"; //SYTH & SIM +parameter ENUM_SINGLE_READY_2 = "CONCATENATE_RDY"; //SYTH & SIM +parameter ENUM_SINGLE_READY_3 = "CONCATENATE_RDY"; //SYTH & SIM +parameter ENUM_STATIC_WEIGHT_0 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_STATIC_WEIGHT_1 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_STATIC_WEIGHT_2 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_STATIC_WEIGHT_3 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_STATIC_WEIGHT_4 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_STATIC_WEIGHT_5 = "WEIGHT_0"; //SYTH ONLY +parameter ENUM_SYNC_MODE_0 = "ASYNCHRONOUS"; //SYTH & SIM +parameter ENUM_SYNC_MODE_1 = "ASYNCHRONOUS"; //SYTH & SIM +parameter ENUM_SYNC_MODE_2 = "ASYNCHRONOUS"; //SYTH & SIM +parameter ENUM_SYNC_MODE_3 = "ASYNCHRONOUS"; //SYTH & SIM +parameter ENUM_SYNC_MODE_4 = "ASYNCHRONOUS"; //SYTH & SIM +parameter ENUM_SYNC_MODE_5 = "ASYNCHRONOUS"; //SYTH & SIM +parameter ENUM_TEST_MODE = "NORMAL_MODE"; //SYTH & SIM +parameter ENUM_THLD_JAR1_0 = "THRESHOLD_32"; //SYTH & SIM +parameter ENUM_THLD_JAR1_1 = "THRESHOLD_32"; //SYTH & SIM +parameter ENUM_THLD_JAR1_2 = "THRESHOLD_32"; //SYTH & SIM +parameter ENUM_THLD_JAR1_3 = "THRESHOLD_32"; //SYTH & SIM +parameter ENUM_THLD_JAR1_4 = "THRESHOLD_32"; //SYTH & SIM +parameter ENUM_THLD_JAR1_5 = "THRESHOLD_32"; //SYTH & SIM +parameter ENUM_THLD_JAR2_0 = "THRESHOLD_16"; //SYTH & SIM +parameter ENUM_THLD_JAR2_1 = "THRESHOLD_16"; //SYTH & SIM +parameter ENUM_THLD_JAR2_2 = "THRESHOLD_16"; //SYTH & SIM +parameter ENUM_THLD_JAR2_3 = "THRESHOLD_16"; //SYTH & SIM +parameter ENUM_THLD_JAR2_4 = "THRESHOLD_16"; //SYTH & SIM +parameter ENUM_THLD_JAR2_5 = "THRESHOLD_16"; //SYTH & SIM +parameter ENUM_USE_ALMOST_EMPTY_0 = "EMPTY"; //SYTH & SIM +parameter ENUM_USE_ALMOST_EMPTY_1 = "EMPTY"; //SYTH & SIM +parameter ENUM_USE_ALMOST_EMPTY_2 = "EMPTY"; //SYTH & SIM +parameter ENUM_USE_ALMOST_EMPTY_3 = "EMPTY"; //SYTH & SIM +parameter ENUM_USER_ECC_EN = "DISABLE"; //SYTH & SIM +parameter ENUM_USER_PRIORITY_0 = "PRIORITY_0"; //SYTH ONLY +parameter ENUM_USER_PRIORITY_1 = "PRIORITY_0"; //SYTH ONLY +parameter ENUM_USER_PRIORITY_2 = "PRIORITY_0"; //SYTH ONLY +parameter ENUM_USER_PRIORITY_3 = "PRIORITY_0"; //SYTH ONLY +parameter ENUM_USER_PRIORITY_4 = "PRIORITY_0"; //SYTH ONLY +parameter ENUM_USER_PRIORITY_5 = "PRIORITY_0"; //SYTH ONLY +parameter ENUM_WFIFO0_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_WFIFO0_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_WFIFO1_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_WFIFO1_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_WFIFO2_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_WFIFO2_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_WFIFO3_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM +parameter ENUM_WFIFO3_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM +parameter ENUM_WR_DWIDTH_0 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_WR_DWIDTH_1 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_WR_DWIDTH_2 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_WR_DWIDTH_3 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_WR_DWIDTH_4 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_WR_DWIDTH_5 = "DWIDTH_0"; //SYTH ONLY +parameter ENUM_WR_FIFO_IN_USE_0 = "FALSE"; //SYTH ONLY +parameter ENUM_WR_FIFO_IN_USE_1 = "FALSE"; //SYTH ONLY +parameter ENUM_WR_FIFO_IN_USE_2 = "FALSE"; //SYTH ONLY +parameter ENUM_WR_FIFO_IN_USE_3 = "FALSE"; //SYTH ONLY +parameter ENUM_WR_PORT_INFO_0 = "USE_NO"; //SYTH ONLY +parameter ENUM_WR_PORT_INFO_1 = "USE_NO"; //SYTH ONLY +parameter ENUM_WR_PORT_INFO_2 = "USE_NO"; //SYTH ONLY +parameter ENUM_WR_PORT_INFO_3 = "USE_NO"; //SYTH ONLY +parameter ENUM_WR_PORT_INFO_4 = "USE_NO"; //SYTH ONLY +parameter ENUM_WR_PORT_INFO_5 = "USE_NO"; //SYTH ONLY +parameter ENUM_WRITE_ODT_CHIP = "ODT_DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BURST_INTERRUPT = "DISABLED"; //SYTH & SIM +parameter ENUM_ENABLE_BURST_TERMINATE = "DISABLED"; //SYTH & SIM +parameter INTG_POWER_SAVING_EXIT_CYCLES = 5; //SYTH & SIM +parameter INTG_MEM_CLK_ENTRY_CYCLES = 10; //SYTH & SIM +parameter INTG_PRIORITY_REMAP = 0; //SYTH & SIM +parameter INTG_MEM_AUTO_PD_CYCLES = 0; //SYTH & SIM +parameter INTG_CYC_TO_RLD_JARS_0 = 128; //SYTH & SIM +parameter INTG_CYC_TO_RLD_JARS_1 = 128; //SYTH & SIM +parameter INTG_CYC_TO_RLD_JARS_2 = 128; //SYTH & SIM +parameter INTG_CYC_TO_RLD_JARS_3 = 128; //SYTH & SIM +parameter INTG_CYC_TO_RLD_JARS_4 = 128; //SYTH & SIM +parameter INTG_CYC_TO_RLD_JARS_5 = 128; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_ACT_TO_ACT = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_ACT_TO_PCH = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_ARF_PERIOD = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_ARF_TO_VALID = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_PCH_TO_VALID = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_PDN_PERIOD = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_PDN_TO_VALID = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_RD_TO_PCH = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_RD_TO_RD = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_RD_TO_WR = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_SRF_TO_VALID = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_WR_TO_PCH = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_WR_TO_RD = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_WR_TO_WR = 0; //SYTH & SIM +parameter INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0; //SYTH & SIM +parameter INTG_MEM_IF_TREFI = 3120; //SYTH & SIM +parameter INTG_MEM_IF_TRFC = 34; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_0 = 0; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_1 = 0; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_2 = 0; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_3 = 0; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_4 = 0; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_5 = 0; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_6 = 0; //SYTH & SIM +parameter INTG_RCFG_SUM_WT_PRIORITY_7 = 0; //SYTH & SIM +parameter INTG_SUM_WT_PRIORITY_0 = 0; //SYTH ONLY +parameter INTG_SUM_WT_PRIORITY_1 = 0; //SYTH ONLY +parameter INTG_SUM_WT_PRIORITY_2 = 0; //SYTH ONLY +parameter INTG_SUM_WT_PRIORITY_3 = 0; //SYTH ONLY +parameter INTG_SUM_WT_PRIORITY_4 = 0; //SYTH ONLY +parameter INTG_SUM_WT_PRIORITY_5 = 0; //SYTH ONLY +parameter INTG_SUM_WT_PRIORITY_6 = 0; //SYTH ONLY +parameter INTG_SUM_WT_PRIORITY_7 = 0; //SYTH ONLY +parameter VECT_ATTR_COUNTER_ONE_MASK = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM +parameter VECT_ATTR_COUNTER_ONE_MATCH = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM +parameter VECT_ATTR_COUNTER_ZERO_MASK = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM +parameter VECT_ATTR_COUNTER_ZERO_MATCH = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM +parameter VECT_ATTR_DEBUG_SELECT_BYTE = 32'b00000000000000000000000000000000; //SYTH & SIM + +// END PARAMETER SECTION +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// START LOCALPARAM + +// WIRE +localparam CFG_CFG_AVALON_DATA_BYTES = 'd1; +localparam CFG_CFG_AVALON_ADDR_WIDTH = 'd10; +localparam MAX_CMD_PT_NUM = 6; +localparam MAX_FIFO_NUM = 4; +localparam RD_FIFO_WIDTH = 80; +localparam WR_FIFO_WIDTH = 90; +localparam MAX_PORT_BL = 255; +localparam MAX_PORT_CMD_WIDTH = 2; +localparam MAX_PORT_PRI_WIDTH = 0; +localparam MAX_PORT_ADDR_WIDTH = 32; +localparam MAX_PORT_BL_WIDTH = 8; +localparam MAX_PORT_TID_WIDTH = 0; +localparam MAX_PORT_CMDE_WIDTH = 0; +localparam CMD_FIFO_DWIDTH = (MAX_PORT_CMDE_WIDTH + MAX_PORT_TID_WIDTH + MAX_PORT_BL_WIDTH + MAX_PORT_ADDR_WIDTH + MAX_PORT_PRI_WIDTH + MAX_PORT_CMD_WIDTH); +localparam CFG_MEM_IF_CHIP = 1; +localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8; +localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 8; +localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 8; +localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 8; +localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 8; +localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 8; +localparam CFG_PORT_WIDTH_CAS_WR_LAT = 8; +localparam CFG_PORT_WIDTH_ADD_LAT = 8; +localparam CFG_PORT_WIDTH_TCL = 8; +localparam CFG_PORT_WIDTH_TRFC = 8; +localparam CFG_PORT_WIDTH_TREFI = 16; +localparam CFG_PORT_WIDTH_TWR = 8; +localparam CFG_PORT_WIDTH_TMRD = 8; + +localparam HARDIP_AFI_ADDR_WIDTH = 20; +localparam HARDIP_AFI_BANKADDR_WIDTH = 3 ; +localparam HARDIP_AFI_CONTROL_WIDTH = 1 ; +localparam HARDIP_AFI_CS_WIDTH = 2 ; +localparam HARDIP_AFI_ODT_WIDTH = 2 ; +localparam HARDIP_AFI_DM_WIDTH = 10; +localparam HARDIP_AFI_DQ_WIDTH = 80; +localparam HARDIP_AFI_WRITE_DQS_WIDTH = 5 ; +// HARDIP_AFI_RATE_RATIO doesn't make sense as a normal rate ratio, +// but it does make the correct size of the afi_rdata_en and afi_rdata_en_full signals +localparam HARDIP_AFI_RATE_RATIO = 5 ; +localparam HARDIP_AFI_WLAT_WIDTH = 4 ; +localparam HARDIP_AFI_RLAT_WIDTH = 5 ; +localparam HARDIP_TRACKING_WIDTH = 2 ; + +localparam INT_AFI_ADDR_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_ADDR_WIDTH : AFI_ADDR_WIDTH ; +localparam INT_AFI_BANKADDR_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_BANKADDR_WIDTH : AFI_BANKADDR_WIDTH ; +localparam INT_AFI_CONTROL_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_CONTROL_WIDTH : AFI_CONTROL_WIDTH ; +localparam INT_AFI_CS_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_CS_WIDTH : AFI_CS_WIDTH ; +localparam INT_AFI_ODT_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_ODT_WIDTH : AFI_ODT_WIDTH ; +localparam INT_AFI_DM_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_DM_WIDTH : AFI_DM_WIDTH ; +localparam INT_AFI_DQ_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_DQ_WIDTH : AFI_DQ_WIDTH ; +localparam INT_AFI_WRITE_DQS_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_WRITE_DQS_WIDTH : AFI_WRITE_DQS_WIDTH; +localparam INT_AFI_RATE_RATIO = (HARD_PHY == 1) ? HARDIP_AFI_RATE_RATIO : AFI_RATE_RATIO ; +localparam INT_AFI_WLAT_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_WLAT_WIDTH : AFI_WLAT_WIDTH ; +localparam INT_AFI_RLAT_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_RLAT_WIDTH : AFI_RLAT_WIDTH ; + +localparam ZERO_PAD_WIDTH_BE_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 2 : 6; +localparam ZERO_PAD_WIDTH_BE_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 0 : 2; +localparam ZERO_PAD_WIDTH_DT_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 32 : 48; +localparam ZERO_PAD_WIDTH_DT_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 0 : 16; +localparam BE_WIDTH_FIFO0_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 6 : 4; +localparam BE_WIDTH_FIFO0_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 10 : 8; +localparam BE_WIDTH_FIFO1_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 20 : 16; +localparam BE_WIDTH_FIFO2_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 30 : 24; +localparam BE_WIDTH_FIFO3_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 40 : 32; +localparam DATA_WIDTH_FIFO0_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 48 : 32; +localparam DATA_WIDTH_FIFO0_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 80 : 64; +localparam DATA_WIDTH_FIFO1_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 160 :128; +localparam DATA_WIDTH_FIFO2_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 240 :192; +localparam DATA_WIDTH_FIFO3_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 320 :256; + +// END LOCALPARAM +//////////////////////////////////////////////////////////////////////////////// + +// END LOCALPARAM +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// BEGIN PORT SECTION + +// Clock and reset interface +input afi_clk; +input afi_half_clk; +input afi_reset_n; +input ctl_clk; +input ctl_reset_n; +input mp_cmd_clk_0; +input mp_cmd_clk_1; +input mp_cmd_clk_2; +input mp_cmd_clk_3; +input mp_cmd_clk_4; +input mp_cmd_clk_5; +input mp_cmd_reset_n_0; +input mp_cmd_reset_n_1; +input mp_cmd_reset_n_2; +input mp_cmd_reset_n_3; +input mp_cmd_reset_n_4; +input mp_cmd_reset_n_5; +input mp_rfifo_clk_0; +input mp_rfifo_clk_1; +input mp_rfifo_clk_2; +input mp_rfifo_clk_3; +input mp_rfifo_reset_n_0; +input mp_rfifo_reset_n_1; +input mp_rfifo_reset_n_2; +input mp_rfifo_reset_n_3; +input mp_wfifo_clk_0; +input mp_wfifo_clk_1; +input mp_wfifo_clk_2; +input mp_wfifo_clk_3; +input mp_wfifo_reset_n_0; +input mp_wfifo_reset_n_1; +input mp_wfifo_reset_n_2; +input mp_wfifo_reset_n_3; +input csr_clk; +input csr_reset_n; + +// Avalon data slave interface +output avl_ready_0; +input avl_write_req_0; +input avl_read_req_0; +input [AVL_ADDR_WIDTH_PORT_0 - 1 : 0] avl_addr_0; +input [AVL_NUM_SYMBOLS_PORT_0 - 1 : 0] avl_be_0; +input [AVL_DATA_WIDTH_PORT_0 - 1 : 0] avl_wdata_0; +input [AVL_SIZE_WIDTH - 1 : 0] avl_size_0; +input avl_burstbegin_0; +output [AVL_DATA_WIDTH_PORT_0 - 1 : 0] avl_rdata_0; +output avl_rdata_valid_0; +output avl_ready_1; +input avl_write_req_1; +input avl_read_req_1; +input [AVL_ADDR_WIDTH_PORT_1 - 1 : 0] avl_addr_1; +input [AVL_NUM_SYMBOLS_PORT_1 - 1 : 0] avl_be_1; +input [AVL_DATA_WIDTH_PORT_1 - 1 : 0] avl_wdata_1; +input [AVL_SIZE_WIDTH - 1 : 0] avl_size_1; +input avl_burstbegin_1; +output [AVL_DATA_WIDTH_PORT_1 - 1 : 0] avl_rdata_1; +output avl_rdata_valid_1; +output avl_ready_2; +input avl_write_req_2; +input avl_read_req_2; +input [AVL_ADDR_WIDTH_PORT_2 - 1 : 0] avl_addr_2; +input [AVL_NUM_SYMBOLS_PORT_2 - 1 : 0] avl_be_2; +input [AVL_DATA_WIDTH_PORT_2 - 1 : 0] avl_wdata_2; +input [AVL_SIZE_WIDTH - 1 : 0] avl_size_2; +input avl_burstbegin_2; +output [AVL_DATA_WIDTH_PORT_2 - 1 : 0] avl_rdata_2; +output avl_rdata_valid_2; +output avl_ready_3; +input avl_write_req_3; +input avl_read_req_3; +input [AVL_ADDR_WIDTH_PORT_3 - 1 : 0] avl_addr_3; +input [AVL_NUM_SYMBOLS_PORT_3 - 1 : 0] avl_be_3; +input [AVL_DATA_WIDTH_PORT_3 - 1 : 0] avl_wdata_3; +input [AVL_SIZE_WIDTH - 1 : 0] avl_size_3; +input avl_burstbegin_3; +output [AVL_DATA_WIDTH_PORT_3 - 1 : 0] avl_rdata_3; +output avl_rdata_valid_3; +output avl_ready_4; +input avl_write_req_4; +input avl_read_req_4; +input [AVL_ADDR_WIDTH_PORT_4 - 1 : 0] avl_addr_4; +input [AVL_NUM_SYMBOLS_PORT_4 - 1 : 0] avl_be_4; +input [AVL_DATA_WIDTH_PORT_4 - 1 : 0] avl_wdata_4; +input [AVL_SIZE_WIDTH - 1 : 0] avl_size_4; +input avl_burstbegin_4; +output [AVL_DATA_WIDTH_PORT_4 - 1 : 0] avl_rdata_4; +output avl_rdata_valid_4; +output avl_ready_5; +input avl_write_req_5; +input avl_read_req_5; +input [AVL_ADDR_WIDTH_PORT_5 - 1 : 0] avl_addr_5; +input [AVL_NUM_SYMBOLS_PORT_5 - 1 : 0] avl_be_5; +input [AVL_DATA_WIDTH_PORT_5 - 1 : 0] avl_wdata_5; +input [AVL_SIZE_WIDTH - 1 : 0] avl_size_5; +input avl_burstbegin_5; +output [AVL_DATA_WIDTH_PORT_5 - 1 : 0] avl_rdata_5; +output avl_rdata_valid_5; + +// AFI signals +output [INT_AFI_CS_WIDTH - 1 : 0] afi_cs_n; +output [INT_AFI_CS_WIDTH - 1 : 0] afi_cke; +output [INT_AFI_ODT_WIDTH - 1 : 0] afi_odt; +output [INT_AFI_ADDR_WIDTH - 1 : 0] afi_addr; +output [INT_AFI_BANKADDR_WIDTH - 1 : 0] afi_ba; +output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_ras_n; +output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_cas_n; +output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_we_n; +output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_rst_n; +output [INT_AFI_WRITE_DQS_WIDTH - 1 : 0] afi_dqs_burst; +output [INT_AFI_WRITE_DQS_WIDTH - 1 : 0] afi_wdata_valid; +output [INT_AFI_DQ_WIDTH - 1 : 0] afi_wdata; +output [INT_AFI_DM_WIDTH - 1 : 0] afi_dm; +input [INT_AFI_WLAT_WIDTH - 1 : 0] afi_wlat; +output [INT_AFI_RATE_RATIO - 1 : 0] afi_rdata_en; +output [INT_AFI_RATE_RATIO - 1 : 0] afi_rdata_en_full; +input [INT_AFI_DQ_WIDTH - 1 : 0] afi_rdata; +input [1 - 1 : 0] afi_rdata_valid; +input [INT_AFI_RLAT_WIDTH - 1 : 0] afi_rlat; +input afi_cal_success; +input afi_cal_fail; +output afi_cal_req; +output afi_init_req; + +output [MEM_IF_CLK_PAIR_COUNT - 1 : 0] afi_mem_clk_disable; + +// disable unused AFI signals + +wire [(MEM_IF_DQS_WIDTH*MEM_IF_CS_WIDTH) - 1 : 0] afi_cal_byte_lane_sel_n; +output [MEM_IF_CS_WIDTH - 1 : 0] afi_ctl_refresh_done; +input [MEM_IF_CS_WIDTH - 1 : 0] afi_seq_busy; +output [MEM_IF_CS_WIDTH - 1 : 0] afi_ctl_long_idle; + +// Sideband signals +output local_refresh_ack; +output local_powerdn_ack; +output local_self_rfsh_ack; +output local_deep_powerdn_ack; +input local_refresh_req; +input [MEM_IF_CS_WIDTH - 1 : 0] local_refresh_chip; + +//Ahmed: do we need this? +//input local_powerdn_req; +input local_self_rfsh_req; +input [MEM_IF_CS_WIDTH - 1 : 0] local_self_rfsh_chip; +input local_deep_powerdn_req; +input [MEM_IF_CS_WIDTH - 1 : 0] local_deep_powerdn_chip; +input local_multicast; +input local_priority; + +output local_init_done; +output local_cal_success; +output local_cal_fail; + +// Csr & ecc signals +input csr_read_req; +input csr_write_req; +input [CSR_ADDR_WIDTH - 1 : 0] csr_addr; +input [CSR_DATA_WIDTH - 1 : 0] csr_wdata; +output [CSR_DATA_WIDTH - 1 : 0] csr_rdata; +input [CSR_BE_WIDTH - 1 : 0] csr_be; +output csr_rdata_valid; +output csr_waitrequest; + +// Cfg signal to Phy +output [23:0] cfg_dramconfig; +output [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_caswrlat; +output [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_addlat; +output [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl; +output [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc; +output [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi; +output [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr; +output [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd; +output [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_coladdrwidth; +output [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_rowaddrwidth; +output [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bankaddrwidth; +output [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_csaddrwidth; +output [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interfacewidth; +output [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_devicewidth; +output ctl_init_req; + +// Bonding signals +output [MAX_FIFO_NUM - 1 : 0] bonding_out_1; +input [MAX_FIFO_NUM - 1 : 0] bonding_in_1; +output [MAX_CMD_PT_NUM - 1 : 0] bonding_out_2; +input [MAX_CMD_PT_NUM - 1 : 0] bonding_in_2; +output [MAX_CMD_PT_NUM - 1 : 0] bonding_out_3; +input [MAX_CMD_PT_NUM - 1 : 0] bonding_in_3; + +// IO_INT interface from HPHY +input io_intaficalfail; +input io_intaficalsuccess; + +// Connect to user logic +output local_sts_ctl_empty; + +// END PORT SECTION +////////////////////////////////////////////////////////////////////////////// + +wire i_avst_cmd_reset_n_0; +wire i_avst_cmd_reset_n_1; +wire i_avst_cmd_reset_n_2; +wire i_avst_cmd_reset_n_3; +wire i_avst_cmd_reset_n_4; +wire i_avst_cmd_reset_n_5; +wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_0; +wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_1; +wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_2; +wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_3; +wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_4; +wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_5; +wire o_a_mm_ready_0; +wire o_a_mm_ready_1; +wire o_a_mm_ready_2; +wire o_a_mm_ready_3; +wire o_a_mm_ready_4; +wire o_a_mm_ready_5; +wire i_avst_wrack_ready_0; +wire i_avst_wrack_ready_1; +wire i_avst_wrack_ready_2; +wire i_avst_wrack_ready_3; +wire i_avst_wrack_ready_4; +wire i_avst_wrack_ready_5; +wire o_wrack_avst_valid_0; +wire o_wrack_avst_valid_1; +wire o_wrack_avst_valid_2; +wire o_wrack_avst_valid_3; +wire o_wrack_avst_valid_4; +wire o_wrack_avst_valid_5; +wire o_wrack_avst_data_0; +wire o_wrack_avst_data_1; +wire o_wrack_avst_data_2; +wire o_wrack_avst_data_3; +wire o_wrack_avst_data_4; +wire o_wrack_avst_data_5; +wire i_avst_rd_clk_0; +wire i_avst_rd_clk_1; +wire i_avst_rd_clk_2; +wire i_avst_rd_clk_3; +wire i_avst_rd_reset_n_0; +wire i_avst_rd_reset_n_1; +wire i_avst_rd_reset_n_2; +wire i_avst_rd_reset_n_3; +wire o_rd_avst_valid_0; +wire o_rd_avst_valid_1; +wire o_rd_avst_valid_2; +wire o_rd_avst_valid_3; +wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_0; +wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_1; +wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_2; +wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_3; +wire i_avst_rd_ready_0; +wire i_avst_rd_ready_1; +wire i_avst_rd_ready_2; +wire i_avst_rd_ready_3; +wire i_avst_wr_clk_0; +wire i_avst_wr_clk_1; +wire i_avst_wr_clk_2; +wire i_avst_wr_clk_3; +wire i_avst_wr_reset_n_0; +wire i_avst_wr_reset_n_1; +wire i_avst_wr_reset_n_2; +wire i_avst_wr_reset_n_3; +wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_0; +wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_1; +wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_2; +wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_3; +wire [MAX_FIFO_NUM -1:0] bonding_out_1; +wire [MAX_FIFO_NUM -1:0] bonding_in_1; +wire [MAX_CMD_PT_NUM -1:0] bonding_out_2; +wire [MAX_CMD_PT_NUM -1:0] bonding_in_2; +wire [MAX_CMD_PT_NUM -1:0] bonding_out_3; +wire [MAX_CMD_PT_NUM -1:0] bonding_in_3; +wire local_refresh_req; +wire [2 -1:0] local_refresh_chip_wire; +wire local_deep_powerdn_req; +wire [2 -1:0] local_deep_powerdn_chip_wire; +wire local_self_rfsh_req; +wire [2 -1:0] local_self_rfsh_chip_wire; +wire local_refresh_ack; +wire local_deep_powerdn_ack; +wire local_powerdn_ack; +wire local_self_rfsh_ack; +wire local_init_done; +wire local_sts_ctl_empty; +wire ctl_init_req; +wire mmr_clk; +wire mmr_reset_n; +wire mmr_read_req; +wire mmr_write_req; +wire [2 -1:0] mmr_burst_count; +wire mmr_burst_begin; +wire [CFG_CFG_AVALON_ADDR_WIDTH -1:0] mmr_addr; +wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] mmr_wdata; +wire [CFG_CFG_AVALON_DATA_BYTES -1:0] mmr_be; +wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] mmr_rdata; +wire mmr_rdata_valid; +wire mmr_waitrequest; +wire sc_clk; +wire sc_reset_n; +wire sc_read_req; +wire sc_write_req; +wire [2 -1:0] sc_burst_count; +wire sc_burst_begin; +wire [CFG_CFG_AVALON_ADDR_WIDTH -1:0] sc_addr; +wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] sc_wdata; +wire [CFG_CFG_AVALON_DATA_BYTES -1:0] sc_be; +wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] sc_rdata; +wire sc_rdata_valid; +wire sc_waitrequest; +wire [24 -1:0] cfg_dramconfig; +wire [CFG_PORT_WIDTH_CAS_WR_LAT -1:0] cfg_caswrlat; +wire [CFG_PORT_WIDTH_ADD_LAT -1:0] cfg_addlat; +wire [CFG_PORT_WIDTH_TCL -1:0] cfg_tcl; +wire [CFG_PORT_WIDTH_TRFC -1:0] cfg_trfc; +wire [CFG_PORT_WIDTH_TREFI -1:0] cfg_trefi; +wire [CFG_PORT_WIDTH_TWR -1:0] cfg_twr; +wire [CFG_PORT_WIDTH_TMRD -1:0] cfg_tmrd; +wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH -1:0] cfg_coladdrwidth; +wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH -1:0] cfg_rowaddrwidth; +wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH -1:0] cfg_bankaddrwidth; +wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH -1:0] cfg_csaddrwidth; +wire [CFG_PORT_WIDTH_INTERFACE_WIDTH -1:0] cfg_interfacewidth; +wire [CFG_PORT_WIDTH_DEVICE_WIDTH -1:0] cfg_devicewidth; +wire csrdin; +wire csrdout; +wire csrclk; +wire csren; +wire scanenable; +wire afi_clk; +wire afi_reset_n; +wire ctl_reset_n; +wire [HARDIP_TRACKING_WIDTH -1:0] afi_seq_busy_int; + +wire [24 -1:0] cfg_dramconfig_wire; +wire [4 -1:0] cfg_caswrlat_wire; +wire [5 -1:0] cfg_addlat_wire; +wire [5 -1:0] cfg_tcl_wire; +wire [8 -1:0] cfg_trfc_wire; +wire [16 -1:0] cfg_trefi_wire; +wire [4 -1:0] cfg_twr_wire; +wire [4 -1:0] cfg_tmrd_wire; +wire [5 -1:0] cfg_coladdrwidth_wire; +wire [5 -1:0] cfg_rowaddrwidth_wire; +wire [3 -1:0] cfg_bankaddrwidth_wire; +wire [3 -1:0] cfg_csaddrwidth_wire; +wire [8 -1:0] cfg_interfacewidth_wire; +wire [4 -1:0] cfg_devicewidth_wire; + + + +//USED WITHIN THE MAPPING + +wire [256 -1:0] data_width[5:0]; +wire [32 -1:0] lsb_wfifo[5:0]; +wire [32 -1:0] msb_wfifo[5:0]; +wire [32 -1:0] lsb_rfifo[5:0]; + +wire [320 -1:0] avl_wdata_g[5:0]; +wire [40 -1:0] avl_be_g[5:0]; +reg [WR_FIFO_WIDTH -1:0] i_avst_wr_data_g [3:0]; + +reg avl_rdata_valid_g[5:0]; +reg [320 -1:0] avl_rdata_g[5:0]; + +reg [INT_AFI_DM_WIDTH -1:0] afi_dm; +reg [INT_AFI_DQ_WIDTH -1:0] afi_wdata; +reg [INT_AFI_DQ_WIDTH -1:0] afi_rdata; + +reg [HARDIP_AFI_DM_WIDTH -1:0] afi_dm_int; +reg [HARDIP_AFI_DQ_WIDTH -1:0] afi_wdata_int; +reg [HARDIP_AFI_DQ_WIDTH -1:0] afi_rdata_int; + + +//------------------------------------------------------------------------------ +// CFG Interface Assignments +//------------------------------------------------------------------------------ + +assign cfg_dramconfig = cfg_dramconfig_wire; +assign cfg_caswrlat = cfg_caswrlat_wire; +assign cfg_addlat = cfg_addlat_wire; +assign cfg_tcl = cfg_tcl_wire; +assign cfg_trfc = cfg_trfc_wire; +assign cfg_trefi = cfg_trefi_wire; +assign cfg_twr = cfg_twr_wire; +assign cfg_tmrd = cfg_tmrd_wire; +assign cfg_coladdrwidth = cfg_coladdrwidth_wire; +assign cfg_rowaddrwidth = cfg_rowaddrwidth_wire; +assign cfg_bankaddrwidth = cfg_bankaddrwidth_wire; +assign cfg_csaddrwidth = cfg_csaddrwidth_wire; +assign cfg_interfacewidth = cfg_interfacewidth_wire; +assign cfg_devicewidth = cfg_devicewidth_wire; + +//------------------------------------------------------------------------------ +// Sideband +//------------------------------------------------------------------------------ +assign local_refresh_chip_wire = {{2-MEM_IF_CS_WIDTH{local_refresh_chip}}, local_refresh_chip}; +assign local_self_rfsh_chip_wire = {{2-MEM_IF_CS_WIDTH{local_self_rfsh_chip}}, local_self_rfsh_chip}; +assign local_deep_powerdn_chip_wire = {{2-MEM_IF_CS_WIDTH{local_deep_powerdn_chip}}, local_deep_powerdn_chip}; + +//////////////////////////////////////////////////////////////////////////////// +// START HIP TO SIP MAPING + +//------------------------------------------------------------------------------ +// Passing all ports parameters into same variable +//------------------------------------------------------------------------------ + +assign data_width[0] = AVL_DATA_WIDTH_PORT_0; +assign data_width[1] = AVL_DATA_WIDTH_PORT_1; +assign data_width[2] = AVL_DATA_WIDTH_PORT_2; +assign data_width[3] = AVL_DATA_WIDTH_PORT_3; +assign data_width[4] = AVL_DATA_WIDTH_PORT_4; +assign data_width[5] = AVL_DATA_WIDTH_PORT_5; + +assign lsb_wfifo[0] = LSB_WFIFO_PORT_0; +assign lsb_wfifo[1] = LSB_WFIFO_PORT_1; +assign lsb_wfifo[2] = LSB_WFIFO_PORT_2; +assign lsb_wfifo[3] = LSB_WFIFO_PORT_3; +assign lsb_wfifo[4] = LSB_WFIFO_PORT_4; +assign lsb_wfifo[5] = LSB_WFIFO_PORT_5; + +assign msb_wfifo[0] = MSB_WFIFO_PORT_0; +assign msb_wfifo[1] = MSB_WFIFO_PORT_1; +assign msb_wfifo[2] = MSB_WFIFO_PORT_2; +assign msb_wfifo[3] = MSB_WFIFO_PORT_3; +assign msb_wfifo[4] = MSB_WFIFO_PORT_4; +assign msb_wfifo[5] = MSB_WFIFO_PORT_5; + +assign lsb_rfifo[0] = LSB_RFIFO_PORT_0; +assign lsb_rfifo[1] = LSB_RFIFO_PORT_1; +assign lsb_rfifo[2] = LSB_RFIFO_PORT_2; +assign lsb_rfifo[3] = LSB_RFIFO_PORT_3; +assign lsb_rfifo[4] = LSB_RFIFO_PORT_4; +assign lsb_rfifo[5] = LSB_RFIFO_PORT_5; + +//------------------------------------------------------------------------------ +// Command path +//------------------------------------------------------------------------------ + +assign avl_ready_0 = o_a_mm_ready_0 ; +assign avl_ready_1 = o_a_mm_ready_1 ; +assign avl_ready_2 = o_a_mm_ready_2 ; +assign avl_ready_3 = o_a_mm_ready_3 ; +assign avl_ready_4 = o_a_mm_ready_4 ; +assign avl_ready_5 = o_a_mm_ready_5 ; + +assign i_avst_cmd_data_0 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_0,{34-AVL_ADDR_WIDTH_PORT_0-2{1'b0}},avl_addr_0,avl_write_req_0,avl_read_req_0}; +assign i_avst_cmd_data_1 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_1,{34-AVL_ADDR_WIDTH_PORT_1-2{1'b0}},avl_addr_1,avl_write_req_1,avl_read_req_1}; +assign i_avst_cmd_data_2 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_2,{34-AVL_ADDR_WIDTH_PORT_2-2{1'b0}},avl_addr_2,avl_write_req_2,avl_read_req_2}; +assign i_avst_cmd_data_3 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_3,{34-AVL_ADDR_WIDTH_PORT_3-2{1'b0}},avl_addr_3,avl_write_req_3,avl_read_req_3}; +assign i_avst_cmd_data_4 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_4,{34-AVL_ADDR_WIDTH_PORT_4-2{1'b0}},avl_addr_4,avl_write_req_4,avl_read_req_4}; +assign i_avst_cmd_data_5 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_5,{34-AVL_ADDR_WIDTH_PORT_5-2{1'b0}},avl_addr_5,avl_write_req_5,avl_read_req_5}; + +//------------------------------------------------------------------------------ +// Write data path +//------------------------------------------------------------------------------ + +assign i_avst_wr_data_0 = i_avst_wr_data_g[0]; +assign i_avst_wr_data_1 = i_avst_wr_data_g[1]; +assign i_avst_wr_data_2 = i_avst_wr_data_g[2]; +assign i_avst_wr_data_3 = i_avst_wr_data_g[3]; + +assign avl_wdata_g[0] = avl_wdata_0; +assign avl_wdata_g[1] = avl_wdata_1; +assign avl_wdata_g[2] = avl_wdata_2; +assign avl_wdata_g[3] = avl_wdata_3; +assign avl_wdata_g[4] = avl_wdata_4; +assign avl_wdata_g[5] = avl_wdata_5; + +assign avl_be_g[0] = avl_be_0; +assign avl_be_g[1] = avl_be_1; +assign avl_be_g[2] = avl_be_2; +assign avl_be_g[3] = avl_be_3; +assign avl_be_g[4] = avl_be_4; +assign avl_be_g[5] = avl_be_5; + +//------------------------------------------------------------------------------ +// Read data path +//------------------------------------------------------------------------------ + +assign avl_rdata_valid_0 = avl_rdata_valid_g[0]; +assign avl_rdata_valid_1 = avl_rdata_valid_g[1]; +assign avl_rdata_valid_2 = avl_rdata_valid_g[2]; +assign avl_rdata_valid_3 = avl_rdata_valid_g[3]; +assign avl_rdata_valid_4 = avl_rdata_valid_g[4]; +assign avl_rdata_valid_5 = avl_rdata_valid_g[5]; + +assign avl_rdata_0 = avl_rdata_g[0]; +assign avl_rdata_1 = avl_rdata_g[1]; +assign avl_rdata_2 = avl_rdata_g[2]; +assign avl_rdata_3 = avl_rdata_g[3]; +assign avl_rdata_4 = avl_rdata_g[4]; +assign avl_rdata_5 = avl_rdata_g[5]; + +reg [6-1:0] multi_fact_cmd0[5:0]; +reg [6-1:0] multi_fact_cmd1[5:0]; +reg [6-1:0] multi_fact_cmd2[5:0]; +reg [6-1:0] multi_fact_cmd3[5:0]; +reg [6-1:0] multi_fact_cmd4[5:0]; +reg [6-1:0] multi_fact_cmd5[5:0]; + +integer total_used_fifo,port_i,fifo_i,idx_0,idx_1,idx_2,idx_3,idx_4,idx_5,idx_6; +always_comb +begin + + for (port_i = 0; port_i < 6; port_i = port_i + 1'b1) + begin : port_loop + + //---------------------------------------------------------------------- + // Read data path + //---------------------------------------------------------------------- + + if (lsb_rfifo[port_i] == 0) + avl_rdata_valid_g[port_i] = o_rd_avst_valid_0; + else if (lsb_rfifo[port_i] == 1) + avl_rdata_valid_g[port_i] = o_rd_avst_valid_1; + else if (lsb_rfifo[port_i] == 2) + avl_rdata_valid_g[port_i] = o_rd_avst_valid_2; + else if (lsb_rfifo[port_i] == 3) + avl_rdata_valid_g[port_i] = o_rd_avst_valid_3; + else + avl_rdata_valid_g[port_i] = 0; + + if ((data_width[port_i] == 32) || (data_width[port_i] == 48)) + if (lsb_rfifo[port_i] == 0) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_0[DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (lsb_rfifo[port_i] == 1) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_1[DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (lsb_rfifo[port_i] == 2) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_2[DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (lsb_rfifo[port_i] == 3) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else + avl_rdata_g[port_i] = 320'd0; + else if ((data_width[port_i] == 64) || (data_width[port_i] == 80)) + if (lsb_rfifo[port_i] == 0) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_0[DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (lsb_rfifo[port_i] == 1) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_1[DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (lsb_rfifo[port_i] == 2) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_2[DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (lsb_rfifo[port_i] == 3) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else + avl_rdata_g[port_i] = 320'd0; + else if ((data_width[port_i] == 128) || (data_width[port_i] == 160)) + if (lsb_rfifo[port_i] == 0) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64 * 2){1'b0}},o_rd_avst_data_1[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_0[DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (lsb_rfifo[port_i] == 2) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64 * 2){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_2[DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else + avl_rdata_g[port_i] = 320'd0; + else if ((data_width[port_i] == 256) || (data_width[port_i] == 320)) + avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64 * 4){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_2[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_1[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_0[DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else + avl_rdata_g[port_i] = 320'd0; + end + + for (fifo_i = 0; fifo_i < 4; fifo_i = fifo_i + 1) + begin : fifo_loop + + //---------------------------------------------------------------------- + // Write data path + //---------------------------------------------------------------------- + + if ((lsb_wfifo[0] <= fifo_i) && (msb_wfifo[0] >= fifo_i)) + if ((data_width[0] == 32) || (data_width[0] == 48)) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[0][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[0] == 0) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[0] == 1) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]}; + else if (fifo_i - lsb_wfifo[0] == 2) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]}; + else if (fifo_i - lsb_wfifo[0] == 3) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]}; + else + i_avst_wr_data_g[fifo_i] = 90'd0; + else if ((lsb_wfifo[1] <= fifo_i) && (msb_wfifo[1] >= fifo_i)) + if ((data_width[1] == 32) || (data_width[1] == 48)) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[1][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[1] == 0) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[1] == 1) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]}; + else if (fifo_i - lsb_wfifo[1] == 2) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]}; + else if (fifo_i - lsb_wfifo[1] == 3) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]}; + else + i_avst_wr_data_g[fifo_i] = 90'd0; + else if ((lsb_wfifo[2] <= fifo_i) && (msb_wfifo[2] >= fifo_i)) + if ((data_width[2] == 32) || (data_width[2] == 48)) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[2][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[2] == 0) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[2] == 1) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]}; + else if (fifo_i - lsb_wfifo[2] == 2) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]}; + else if (fifo_i - lsb_wfifo[2] == 3) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]}; + else + i_avst_wr_data_g[fifo_i] = 90'd0; + else if ((lsb_wfifo[3] <= fifo_i) && (msb_wfifo[3] >= fifo_i)) + if ((data_width[3] == 32) || (data_width[3] == 48)) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[3][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[3] == 0) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[3] == 1) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]}; + else if (fifo_i - lsb_wfifo[3] == 2) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]}; + else if (fifo_i - lsb_wfifo[3] == 3) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]}; + else + i_avst_wr_data_g[fifo_i] = 90'd0; + else if ((lsb_wfifo[4] <= fifo_i) && (msb_wfifo[4] >= fifo_i)) + if ((data_width[4] == 32) || (data_width[4] == 48)) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[4][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[4] == 0) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[4] == 1) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]}; + else if (fifo_i - lsb_wfifo[4] == 2) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]}; + else if (fifo_i - lsb_wfifo[4] == 3) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]}; + else + i_avst_wr_data_g[fifo_i] = 90'd0; + else if ((lsb_wfifo[5] <= fifo_i) && (msb_wfifo[5] >= fifo_i)) + if ((data_width[5] == 32) || (data_width[5] == 48)) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[5][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO0_32 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[5] == 0) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO0_64 - 1 : 0]}; + else if (fifo_i - lsb_wfifo[5] == 1) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]}; + else if (fifo_i - lsb_wfifo[5] == 2) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]}; + else if (fifo_i - lsb_wfifo[5] == 3) + i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]}; + else + i_avst_wr_data_g[fifo_i] = 90'd0; + else + i_avst_wr_data_g[fifo_i] = 90'd0; + end + + //---------------------------------------------------------------------- + // Afi + //---------------------------------------------------------------------- + + if (HARD_PHY == 1) + begin + afi_rdata_int = afi_rdata; + afi_wdata = afi_wdata_int; + afi_dm = afi_dm_int; + end + else + begin + for (idx_4 = 0; idx_4 < HARDIP_AFI_DQ_WIDTH; idx_4 = idx_4 + 1'b1) + begin : afi_rdata_hip_to_sip + if (idx_4 < INT_AFI_DQ_WIDTH/2) + afi_rdata_int[idx_4] = afi_rdata[idx_4]; + else if ((idx_4 > (HARDIP_AFI_DQ_WIDTH / 2 - 1)) && (idx_4 < (HARDIP_AFI_DQ_WIDTH / 2 + INT_AFI_DQ_WIDTH / 2))) + afi_rdata_int[idx_4] = afi_rdata[idx_4 - ((HARDIP_AFI_DQ_WIDTH /2) - (INT_AFI_DQ_WIDTH / 2))]; + else + afi_rdata_int[idx_4] = 1'b0; + end + + for (idx_5 = 0; idx_5 < INT_AFI_DQ_WIDTH; idx_5 = idx_5 + 1'b1) + begin : afi_wdata_hip_to_sip + if (idx_5 < (INT_AFI_DQ_WIDTH / 2)) + afi_wdata[idx_5] = afi_wdata_int[idx_5]; + else + afi_wdata[idx_5] = afi_wdata_int[idx_5 + ((HARDIP_AFI_DQ_WIDTH / 2) - (INT_AFI_DQ_WIDTH / 2))]; + end + + for (idx_6 = 0; idx_6 < INT_AFI_DM_WIDTH; idx_6 = idx_6 + 1'b1) + begin : afi_dm_hip_to_sip + if (idx_6 < (INT_AFI_DM_WIDTH / 2)) + afi_dm[idx_6] = afi_dm_int[idx_6]; + else + afi_dm[idx_6] = afi_dm_int[idx_6 + ((HARDIP_AFI_DM_WIDTH / 2) - (INT_AFI_DM_WIDTH / 2))]; + end + end +end + +// END HIP TO SIP MAPING +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// START OTHERS ASSIGNMENT + +assign local_cal_success = io_intaficalsuccess; +assign local_cal_fail = io_intaficalfail; + +assign afi_init_req = '0; +assign afi_seq_busy_int = {HARDIP_TRACKING_WIDTH{afi_seq_busy[0]}}; + +// END OTHERS ASSIGNMENT +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// START ATOM INSTANTIATION + +// Those that mark with //HARD NET is harden wire between controller and phy. +// ASM / Fitter will fail if they're not connected properly + +cyclonev_hmc hmc_inst ( + .portclk0 ( mp_cmd_clk_0 ), //SOFT NET + .portclk1 ( mp_cmd_clk_1 ), //SOFT NET + .portclk2 ( mp_cmd_clk_2 ), //SOFT NET + .portclk3 ( mp_cmd_clk_3 ), //SOFT NET + .portclk4 ( mp_cmd_clk_4 ), //SOFT NET + .portclk5 ( mp_cmd_clk_5 ), //SOFT NET + .iavstcmdresetn0 ( mp_cmd_reset_n_0 ), //SOFT NET + .iavstcmdresetn1 ( mp_cmd_reset_n_1 ), //SOFT NET + .iavstcmdresetn2 ( mp_cmd_reset_n_2 ), //SOFT NET + .iavstcmdresetn3 ( mp_cmd_reset_n_3 ), //SOFT NET + .iavstcmdresetn4 ( mp_cmd_reset_n_4 ), //SOFT NET + .iavstcmdresetn5 ( mp_cmd_reset_n_5 ), //SOFT NET + .iavstcmddata0 ( i_avst_cmd_data_0 ), //SOFT NET + .iavstcmddata1 ( i_avst_cmd_data_1 ), //SOFT NET + .iavstcmddata2 ( i_avst_cmd_data_2 ), //SOFT NET + .iavstcmddata3 ( i_avst_cmd_data_3 ), //SOFT NET + .iavstcmddata4 ( i_avst_cmd_data_4 ), //SOFT NET + .iavstcmddata5 ( i_avst_cmd_data_5 ), //SOFT NET + .oammready0 ( o_a_mm_ready_0 ), //SOFT NET + .oammready1 ( o_a_mm_ready_1 ), //SOFT NET + .oammready2 ( o_a_mm_ready_2 ), //SOFT NET + .oammready3 ( o_a_mm_ready_3 ), //SOFT NET + .oammready4 ( o_a_mm_ready_4 ), //SOFT NET + .oammready5 ( o_a_mm_ready_5 ), //SOFT NET + .iavstwrackready0 ( 1'b1 ), //INTERNAL USE + .iavstwrackready1 ( 1'b1 ), //INTERNAL USE + .iavstwrackready2 ( 1'b1 ), //INTERNAL USE + .iavstwrackready3 ( 1'b1 ), //INTERNAL USE + .iavstwrackready4 ( 1'b1 ), //INTERNAL USE + .iavstwrackready5 ( 1'b1 ), //INTERNAL USE + .owrackavstvalid0 ( o_wrack_avst_valid_0 ), //SOFT NET + .owrackavstvalid1 ( o_wrack_avst_valid_1 ), //SOFT NET + .owrackavstvalid2 ( o_wrack_avst_valid_2 ), //SOFT NET + .owrackavstvalid3 ( o_wrack_avst_valid_3 ), //SOFT NET + .owrackavstvalid4 ( o_wrack_avst_valid_4 ), //SOFT NET + .owrackavstvalid5 ( o_wrack_avst_valid_5 ), //SOFT NET + .owrackavstdata0 ( o_wrack_avst_data_0 ), //SOFT NET + .owrackavstdata1 ( o_wrack_avst_data_1 ), //SOFT NET + .owrackavstdata2 ( o_wrack_avst_data_2 ), //SOFT NET + .owrackavstdata3 ( o_wrack_avst_data_3 ), //SOFT NET + .owrackavstdata4 ( o_wrack_avst_data_4 ), //SOFT NET + .owrackavstdata5 ( o_wrack_avst_data_5 ), //SOFT NET + .iavstrdclk0 ( mp_rfifo_clk_0 ), //SOFT NET + .iavstrdclk1 ( mp_rfifo_clk_1 ), //SOFT NET + .iavstrdclk2 ( mp_rfifo_clk_2 ), //SOFT NET + .iavstrdclk3 ( mp_rfifo_clk_3 ), //SOFT NET + .iavstrdresetn0 ( mp_rfifo_reset_n_0 ), //SOFT NET + .iavstrdresetn1 ( mp_rfifo_reset_n_1 ), //SOFT NET + .iavstrdresetn2 ( mp_rfifo_reset_n_2 ), //SOFT NET + .iavstrdresetn3 ( mp_rfifo_reset_n_3 ), //SOFT NET + .ordavstvalid0 ( o_rd_avst_valid_0 ), //SOFT NET + .ordavstvalid1 ( o_rd_avst_valid_1 ), //SOFT NET + .ordavstvalid2 ( o_rd_avst_valid_2 ), //SOFT NET + .ordavstvalid3 ( o_rd_avst_valid_3 ), //SOFT NET + .ordavstdata0 ( o_rd_avst_data_0 ), //SOFT NET + .ordavstdata1 ( o_rd_avst_data_1 ), //SOFT NET + .ordavstdata2 ( o_rd_avst_data_2 ), //SOFT NET + .ordavstdata3 ( o_rd_avst_data_3 ), //SOFT NET + .iavstrdready0 ( 1'b1 ), //INTERNAL USE + .iavstrdready1 ( 1'b1 ), //INTERNAL USE + .iavstrdready2 ( 1'b1 ), //INTERNAL USE + .iavstrdready3 ( 1'b1 ), //INTERNAL USE + .iavstwrclk0 ( mp_wfifo_clk_0 ), //SOFT NET + .iavstwrclk1 ( mp_wfifo_clk_1 ), //SOFT NET + .iavstwrclk2 ( mp_wfifo_clk_2 ), //SOFT NET + .iavstwrclk3 ( mp_wfifo_clk_3 ), //SOFT NET + .iavstwrresetn0 ( mp_wfifo_reset_n_0 ), //SOFT NET + .iavstwrresetn1 ( mp_wfifo_reset_n_1 ), //SOFT NET + .iavstwrresetn2 ( mp_wfifo_reset_n_2 ), //SOFT NET + .iavstwrresetn3 ( mp_wfifo_reset_n_3 ), //SOFT NET + .iavstwrdata0 ( i_avst_wr_data_0 ), //SOFT NET + .iavstwrdata1 ( i_avst_wr_data_1 ), //SOFT NET + .iavstwrdata2 ( i_avst_wr_data_2 ), //SOFT NET + .iavstwrdata3 ( i_avst_wr_data_3 ), //SOFT NET + .bondingout1 ( bonding_out_1 ), //SOFT NET + .bondingin1 ( bonding_in_1 ), //SOFT NET + .bondingout2 ( bonding_out_2 ), //SOFT NET + .bondingin2 ( bonding_in_2 ), //SOFT NET + .bondingout3 ( bonding_out_3 ), //SOFT NET + .bondingin3 ( bonding_in_3 ), //SOFT NET + .localrefreshreq ( local_refresh_req ), //SOFT NET + .localrefreshchip ( local_refresh_chip_wire ), //SOFT NET + .localdeeppowerdnreq ( local_deep_powerdn_req ), //SOFT NET + .localdeeppowerdnchip ( local_deep_powerdn_chip_wire ), //SOFT NET + .localselfrfshreq ( local_self_rfsh_req ), //SOFT NET + .localselfrfshchip ( local_self_rfsh_chip_wire ), //SOFT NET + .localrefreshack ( local_refresh_ack ), //SOFT NET + .localdeeppowerdnack ( local_deep_powerdn_ack ), //SOFT NET + .localpowerdownack ( local_powerdn_ack ), //SOFT NET + .localselfrfshack ( local_self_rfsh_ack ), //SOFT NET + .localstsctlempty ( local_sts_ctl_empty ), + .ctlinitreq ( ctl_init_req ), + .localinitdone ( local_init_done ), //SOFT NET + .afirstn ( afi_rst_n ), //HARD NET + .afiba ( afi_ba ), //HARD NET + .afiaddr ( afi_addr ), //HARD NET + .aficke ( afi_cke ), //HARD NET + .aficsn ( afi_cs_n ), //HARD NET + .afirasn ( afi_ras_n ), //HARD NET + .aficasn ( afi_cas_n ), //HARD NET + .afiwen ( afi_we_n ), //HARD NET + .afiodt ( afi_odt ), //HARD NET + .afiwlat ( afi_wlat ), //HARD NET + .afidqsburst ( afi_dqs_burst ), //HARD NET + .afidm ( afi_dm_int ), //HARD NET + .afiwdata ( afi_wdata_int ), //HARD NET + .afiwdatavalid ( afi_wdata_valid ), //HARD NET + .afirdataen ( afi_rdata_en ), //HARD NET + .afirdataenfull ( afi_rdata_en_full ), //HARD NET + .afirdata ( afi_rdata_int ), //HARD NET + .afirdatavalid ( afi_rdata_valid ), //HARD NET + .ctlcalsuccess ( afi_cal_success ), //HARD NET + .ctlcalfail ( afi_cal_fail ), //HARD NET + .ctlcalreq ( afi_cal_req ), //SOFT NET + .ctlcalbytelaneseln ( afi_cal_byte_lane_sel_n ), //SOFT NET + .ctlmemclkdisable ( afi_mem_clk_disable ), //HARD NET + .afictlrefreshdone ( afi_ctl_refresh_done ), //SOFT NET + .afiseqbusy ( afi_seq_busy_int ), //SOFT NET + .afictllongidle ( afi_ctl_long_idle ), //SOFT NET + .mmrclk ( csr_clk ), //SOFT NET + .mmrresetn ( csr_reset_n ), //SOFT NET + .mmrreadreq ( csr_read_req ), //SOFT NET + .mmrwritereq ( csr_write_req ), //SOFT NET + .mmrburstcount ( 2'b01 ), //SOFT NET + .mmrburstbegin ( 1'b1 ), //SOFT NET + .mmraddr ( csr_addr ), //SOFT NET + .mmrwdata ( csr_wdata ), //SOFT NET + .mmrbe ( csr_be ), //SOFT NET + .mmrrdata ( csr_rdata ), //SOFT NET + .mmrrdatavalid ( csr_rdata_valid ), //SOFT NET + .mmrwaitrequest ( csr_waitrequest ), //SOFT NET + .scclk ( 1'b0 ), //INTERNAL USE + .scresetn ( 1'b1 ), //INTERNAL USE + .screadreq ( 1'b0 ), //INTERNAL USE + .scwritereq ( 1'b0 ), //INTERNAL USE + .scburstcount ( 2'b0 ), //INTERNAL USE + .scburstbegin ( 1'b0 ), //INTERNAL USE + .scaddr ( 10'b0000000000 ), //INTERNAL USE + .scwdata ( 8'b0 ), //INTERNAL USE + .scbe ( 1'b0 ), //INTERNAL USE + .scrdata ( ), //INTERNAL USE + .scrdatavalid ( ), //INTERNAL USE + .scwaitrequest ( ), //INTERNAL USE + .dramconfig ( cfg_dramconfig_wire ), //SOFT NET + .cfgcaswrlat ( cfg_caswrlat_wire ), //SOFT NET + .cfgaddlat ( cfg_addlat_wire ), //SOFT NET + .cfgtcl ( cfg_tcl_wire ), //SOFT NET + .cfgtrfc ( cfg_trfc_wire ), //SOFT NET + .cfgtrefi ( cfg_trefi_wire ), //SOFT NET + .cfgtwr ( cfg_twr_wire ), //SOFT NET + .cfgtmrd ( cfg_tmrd_wire ), //SOFT NET + .cfgcoladdrwidth ( cfg_coladdrwidth_wire ), //SOFT NET + .cfgrowaddrwidth ( cfg_rowaddrwidth_wire ), //SOFT NET + .cfgbankaddrwidth ( cfg_bankaddrwidth_wire ), //SOFT NET + .cfgcsaddrwidth ( cfg_csaddrwidth_wire ), //SOFT NET + .cfginterfacewidth ( cfg_interfacewidth_wire ), //SOFT NET + .cfgdevicewidth ( cfg_devicewidth_wire ), //SOFT NET + .scanenable ( 1'b0 ), //INTERNAL USE + .ctlclk ( ctl_clk ), //HARD NET + .ctlresetn ( ctl_reset_n ) //HARD NET +); + +// Those that mark with // SYTH & SIM is used to force MMR signals in simulation +// Those that mark with // SYTH ONLY is only used for Quartus sythesis +defparam hmc_inst.attr_counter_one_mask = VECT_ATTR_COUNTER_ONE_MASK; //SYTH & SIM +defparam hmc_inst.attr_counter_one_match = VECT_ATTR_COUNTER_ONE_MATCH; //SYTH & SIM +defparam hmc_inst.attr_counter_one_reset = ENUM_ATTR_COUNTER_ONE_RESET; //SYTH & SIM +defparam hmc_inst.attr_counter_zero_mask = VECT_ATTR_COUNTER_ZERO_MASK; //SYTH & SIM +defparam hmc_inst.attr_counter_zero_match = VECT_ATTR_COUNTER_ZERO_MATCH; //SYTH & SIM +defparam hmc_inst.attr_counter_zero_reset = ENUM_ATTR_COUNTER_ZERO_RESET; //SYTH & SIM +defparam hmc_inst.attr_debug_select_byte = VECT_ATTR_DEBUG_SELECT_BYTE; //SYTH & SIM +defparam hmc_inst.attr_static_config_valid = ENUM_ATTR_STATIC_CONFIG_VALID; //SYTH & SIM +defparam hmc_inst.auto_pch_enable_0 = ENUM_AUTO_PCH_ENABLE_0; //SYTH & SIM +defparam hmc_inst.auto_pch_enable_1 = ENUM_AUTO_PCH_ENABLE_1; //SYTH & SIM +defparam hmc_inst.auto_pch_enable_2 = ENUM_AUTO_PCH_ENABLE_2; //SYTH & SIM +defparam hmc_inst.auto_pch_enable_3 = ENUM_AUTO_PCH_ENABLE_3; //SYTH & SIM +defparam hmc_inst.auto_pch_enable_4 = ENUM_AUTO_PCH_ENABLE_4; //SYTH & SIM +defparam hmc_inst.auto_pch_enable_5 = ENUM_AUTO_PCH_ENABLE_5; //SYTH & SIM +defparam hmc_inst.cal_req = ENUM_CAL_REQ; //SYTH & SIM +defparam hmc_inst.cfg_burst_length = ENUM_CFG_BURST_LENGTH; //SYTH & SIM +defparam hmc_inst.cfg_interface_width = ENUM_CFG_INTERFACE_WIDTH; //SYTH & SIM +defparam hmc_inst.cfg_self_rfsh_exit_cycles = ENUM_CFG_SELF_RFSH_EXIT_CYCLES; //SYTH & SIM +defparam hmc_inst.cfg_starve_limit = ENUM_CFG_STARVE_LIMIT; //SYTH & SIM +defparam hmc_inst.cfg_type = ENUM_CFG_TYPE; //SYTH & SIM +defparam hmc_inst.clock_off_0 = ENUM_CLOCK_OFF_0; //SIM ONLY +defparam hmc_inst.clock_off_1 = ENUM_CLOCK_OFF_1; //SIM ONLY +defparam hmc_inst.clock_off_2 = ENUM_CLOCK_OFF_2; //SIM ONLY +defparam hmc_inst.clock_off_3 = ENUM_CLOCK_OFF_3; //SIM ONLY +defparam hmc_inst.clock_off_4 = ENUM_CLOCK_OFF_4; //SIM ONLY +defparam hmc_inst.clock_off_5 = ENUM_CLOCK_OFF_5; //SIM ONLY +defparam hmc_inst.clr_intr = ENUM_CLR_INTR; //SIM ONLY +defparam hmc_inst.cmd_port_in_use_0 = ENUM_CMD_PORT_IN_USE_0; //SYTH ONLY +defparam hmc_inst.cmd_port_in_use_1 = ENUM_CMD_PORT_IN_USE_1; //SYTH ONLY +defparam hmc_inst.cmd_port_in_use_2 = ENUM_CMD_PORT_IN_USE_2; //SYTH ONLY +defparam hmc_inst.cmd_port_in_use_3 = ENUM_CMD_PORT_IN_USE_3; //SYTH ONLY +defparam hmc_inst.cmd_port_in_use_4 = ENUM_CMD_PORT_IN_USE_4; //SYTH ONLY +defparam hmc_inst.cmd_port_in_use_5 = ENUM_CMD_PORT_IN_USE_5; //SYTH ONLY +defparam hmc_inst.cport0_rdy_almost_full = ENUM_CPORT0_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.cport0_rfifo_map = ENUM_CPORT0_RFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport0_type = ENUM_CPORT0_TYPE; //SYTH & SIM +defparam hmc_inst.cport0_wfifo_map = ENUM_CPORT0_WFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport1_rdy_almost_full = ENUM_CPORT1_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.cport1_rfifo_map = ENUM_CPORT1_RFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport1_type = ENUM_CPORT1_TYPE; //SYTH & SIM +defparam hmc_inst.cport1_wfifo_map = ENUM_CPORT1_WFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport2_rdy_almost_full = ENUM_CPORT2_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.cport2_rfifo_map = ENUM_CPORT2_RFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport2_type = ENUM_CPORT2_TYPE; //SYTH & SIM +defparam hmc_inst.cport2_wfifo_map = ENUM_CPORT2_WFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport3_rdy_almost_full = ENUM_CPORT3_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.cport3_rfifo_map = ENUM_CPORT3_RFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport3_type = ENUM_CPORT3_TYPE; //SYTH & SIM +defparam hmc_inst.cport3_wfifo_map = ENUM_CPORT3_WFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport4_rdy_almost_full = ENUM_CPORT4_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.cport4_rfifo_map = ENUM_CPORT4_RFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport4_type = ENUM_CPORT4_TYPE; //SYTH & SIM +defparam hmc_inst.cport4_wfifo_map = ENUM_CPORT4_WFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport5_rdy_almost_full = ENUM_CPORT5_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.cport5_rfifo_map = ENUM_CPORT5_RFIFO_MAP; //SYTH & SIM +defparam hmc_inst.cport5_type = ENUM_CPORT5_TYPE; //SYTH & SIM +defparam hmc_inst.cport5_wfifo_map = ENUM_CPORT5_WFIFO_MAP; //SYTH & SIM +defparam hmc_inst.ctl_addr_order = ENUM_CTL_ADDR_ORDER; //SYTH & SIM +defparam hmc_inst.ctl_ecc_enabled = ENUM_CTL_ECC_ENABLED; //SYTH & SIM +defparam hmc_inst.ctl_ecc_rmw_enabled = ENUM_CTL_ECC_RMW_ENABLED; //SYTH & SIM +defparam hmc_inst.ctl_regdimm_enabled = ENUM_CTL_REGDIMM_ENABLED; //SIM ONLY +defparam hmc_inst.ctl_usr_refresh = ENUM_CTL_USR_REFRESH; //SYTH & SIM +defparam hmc_inst.ctrl_width = ENUM_CTRL_WIDTH; //SYTH & SIM +defparam hmc_inst.cyc_to_rld_jars_0 = INTG_CYC_TO_RLD_JARS_0; //SYTH & SIM +defparam hmc_inst.cyc_to_rld_jars_1 = INTG_CYC_TO_RLD_JARS_1; //SYTH & SIM +defparam hmc_inst.cyc_to_rld_jars_2 = INTG_CYC_TO_RLD_JARS_2; //SYTH & SIM +defparam hmc_inst.cyc_to_rld_jars_3 = INTG_CYC_TO_RLD_JARS_3; //SYTH & SIM +defparam hmc_inst.cyc_to_rld_jars_4 = INTG_CYC_TO_RLD_JARS_4; //SYTH & SIM +defparam hmc_inst.cyc_to_rld_jars_5 = INTG_CYC_TO_RLD_JARS_5; //SYTH & SIM +defparam hmc_inst.power_saving_exit_cycles = INTG_POWER_SAVING_EXIT_CYCLES; //SYTH & SIM +defparam hmc_inst.mem_clk_entry_cycles = INTG_MEM_CLK_ENTRY_CYCLES; //SYTH & SIM +defparam hmc_inst.priority_remap = INTG_PRIORITY_REMAP; //SIM ONLY +defparam hmc_inst.enable_burst_interrupt = ENUM_ENABLE_BURST_INTERRUPT; //SYTH & SIM +defparam hmc_inst.enable_burst_terminate = ENUM_ENABLE_BURST_TERMINATE; //SYTH & SIM +defparam hmc_inst.delay_bonding = ENUM_DELAY_BONDING; //SYTH & SIM +defparam hmc_inst.dfx_bypass_enable = ENUM_DFX_BYPASS_ENABLE; //SYTH & SIM +defparam hmc_inst.disable_merging = ENUM_DISABLE_MERGING; //SIM ONLY +defparam hmc_inst.ecc_dq_width = ENUM_ECC_DQ_WIDTH; //SYTH ONLY +defparam hmc_inst.enable_atpg = ENUM_ENABLE_ATPG; //SYTH & SIM +defparam hmc_inst.enable_bonding_0 = ENUM_ENABLE_BONDING_0; //SYTH & SIM +defparam hmc_inst.enable_bonding_1 = ENUM_ENABLE_BONDING_1; //SYTH & SIM +defparam hmc_inst.enable_bonding_2 = ENUM_ENABLE_BONDING_2; //SYTH & SIM +defparam hmc_inst.enable_bonding_3 = ENUM_ENABLE_BONDING_3; //SYTH & SIM +defparam hmc_inst.enable_bonding_4 = ENUM_ENABLE_BONDING_4; //SYTH & SIM +defparam hmc_inst.enable_bonding_5 = ENUM_ENABLE_BONDING_5; //SYTH & SIM +defparam hmc_inst.enable_bonding_wrapback = ENUM_ENABLE_BONDING_WRAPBACK; //SYTH & SIM +defparam hmc_inst.enable_dqs_tracking = ENUM_ENABLE_DQS_TRACKING; //SYTH & SIM +defparam hmc_inst.enable_ecc_code_overwrites = ENUM_ENABLE_ECC_CODE_OVERWRITES; //SYTH & SIM +defparam hmc_inst.enable_fast_exit_ppd = ENUM_ENABLE_FAST_EXIT_PPD; //SYTH ONLY +defparam hmc_inst.enable_intr = ENUM_ENABLE_INTR; //SYTH & SIM +defparam hmc_inst.enable_no_dm = ENUM_ENABLE_NO_DM; //SYTH & SIM +defparam hmc_inst.enable_pipelineglobal = ENUM_ENABLE_PIPELINEGLOBAL; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_act_to_act = INTG_EXTRA_CTL_CLK_ACT_TO_ACT; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_act_to_act_diff_bank = INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_act_to_pch = INTG_EXTRA_CTL_CLK_ACT_TO_PCH; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_act_to_rdwr = INTG_EXTRA_CTL_CLK_ACT_TO_RDWR; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_arf_period = INTG_EXTRA_CTL_CLK_ARF_PERIOD; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_arf_to_valid = INTG_EXTRA_CTL_CLK_ARF_TO_VALID; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_four_act_to_act = INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_pch_all_to_valid = INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_pch_to_valid = INTG_EXTRA_CTL_CLK_PCH_TO_VALID; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_pdn_period = INTG_EXTRA_CTL_CLK_PDN_PERIOD; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_pdn_to_valid = INTG_EXTRA_CTL_CLK_PDN_TO_VALID; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_rd_ap_to_valid = INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_rd_to_pch = INTG_EXTRA_CTL_CLK_RD_TO_PCH; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_rd_to_rd = INTG_EXTRA_CTL_CLK_RD_TO_RD; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_rd_to_rd_diff_chip = INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_rd_to_wr = INTG_EXTRA_CTL_CLK_RD_TO_WR; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_rd_to_wr_bc = INTG_EXTRA_CTL_CLK_RD_TO_WR_BC; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_rd_to_wr_diff_chip = INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_srf_to_valid = INTG_EXTRA_CTL_CLK_SRF_TO_VALID; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_srf_to_zq_cal = INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_wr_ap_to_valid = INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_wr_to_pch = INTG_EXTRA_CTL_CLK_WR_TO_PCH; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_wr_to_rd = INTG_EXTRA_CTL_CLK_WR_TO_RD; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_wr_to_rd_bc = INTG_EXTRA_CTL_CLK_WR_TO_RD_BC; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_wr_to_rd_diff_chip = INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_wr_to_wr = INTG_EXTRA_CTL_CLK_WR_TO_WR; //SYTH & SIM +defparam hmc_inst.extra_ctl_clk_wr_to_wr_diff_chip = INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP; //SYTH & SIM +defparam hmc_inst.ganged_arf = ENUM_GANGED_ARF; //SIM ONLY +defparam hmc_inst.gen_dbe = ENUM_GEN_DBE; //SIM ONLY +defparam hmc_inst.gen_sbe = ENUM_GEN_SBE; //SIM ONLY +defparam hmc_inst.inc_sync = ENUM_INC_SYNC; //SYTH & SIM +defparam hmc_inst.local_if_cs_width = ENUM_LOCAL_IF_CS_WIDTH; //SYTH & SIM +defparam hmc_inst.mask_corr_dropped_intr = ENUM_MASK_CORR_DROPPED_INTR; //SYTH & SIM +defparam hmc_inst.mask_dbe_intr = ENUM_MASK_DBE_INTR; //SYTH & SIM +defparam hmc_inst.mask_sbe_intr = ENUM_MASK_SBE_INTR; //SYTH & SIM +defparam hmc_inst.mem_auto_pd_cycles = INTG_MEM_AUTO_PD_CYCLES; //SYTH & SIM +defparam hmc_inst.mem_if_al = ENUM_MEM_IF_AL; //SYTH & SIM +defparam hmc_inst.mem_if_bankaddr_width = ENUM_MEM_IF_BANKADDR_WIDTH; //SYTH & SIM +defparam hmc_inst.mem_if_burstlength = ENUM_MEM_IF_BURSTLENGTH; //SYTH ONLY +defparam hmc_inst.mem_if_coladdr_width = ENUM_MEM_IF_COLADDR_WIDTH; //SYTH & SIM +defparam hmc_inst.mem_if_cs_per_rank = ENUM_MEM_IF_CS_PER_RANK; //SYTH ONLY +defparam hmc_inst.mem_if_cs_width = ENUM_MEM_IF_CS_WIDTH; //SYTH ONLY +defparam hmc_inst.mem_if_dq_per_chip = ENUM_MEM_IF_DQ_PER_CHIP; //SYTH ONLY +defparam hmc_inst.mem_if_dqs_width = ENUM_MEM_IF_DQS_WIDTH; //SYTH & SIM +defparam hmc_inst.mem_if_dwidth = ENUM_MEM_IF_DWIDTH; //SYTH ONLY +defparam hmc_inst.mem_if_memtype = ENUM_MEM_IF_MEMTYPE; //SYTH ONLY +defparam hmc_inst.mem_if_rowaddr_width = ENUM_MEM_IF_ROWADDR_WIDTH; //SYTH & SIM +defparam hmc_inst.mem_if_speedbin = ENUM_MEM_IF_SPEEDBIN; //SYTH ONLY +defparam hmc_inst.mem_if_tccd = ENUM_MEM_IF_TCCD; //SYTH & SIM +defparam hmc_inst.mem_if_tcl = ENUM_MEM_IF_TCL; //SYTH & SIM +defparam hmc_inst.mem_if_tcwl = ENUM_MEM_IF_TCWL; //SYTH & SIM +defparam hmc_inst.mem_if_tfaw = ENUM_MEM_IF_TFAW; //SYTH & SIM +defparam hmc_inst.mem_if_tmrd = ENUM_MEM_IF_TMRD; //SYTH & SIM +defparam hmc_inst.mem_if_tras = ENUM_MEM_IF_TRAS; //SYTH & SIM +defparam hmc_inst.mem_if_trc = ENUM_MEM_IF_TRC; //SYTH & SIM +defparam hmc_inst.mem_if_trcd = ENUM_MEM_IF_TRCD; //SYTH & SIM +defparam hmc_inst.mem_if_trefi = INTG_MEM_IF_TREFI; //SYTH & SIM +defparam hmc_inst.mem_if_trfc = INTG_MEM_IF_TRFC; //SYTH & SIM +defparam hmc_inst.mem_if_trp = ENUM_MEM_IF_TRP; //SYTH & SIM +defparam hmc_inst.mem_if_trrd = ENUM_MEM_IF_TRRD; //SYTH & SIM +defparam hmc_inst.mem_if_trtp = ENUM_MEM_IF_TRTP; //SYTH & SIM +defparam hmc_inst.mem_if_twr = ENUM_MEM_IF_TWR; //SYTH & SIM +defparam hmc_inst.mem_if_twtr = ENUM_MEM_IF_TWTR; //SYTH & SIM +defparam hmc_inst.mmr_cfg_mem_bl = ENUM_MMR_CFG_MEM_BL; //SYTH & SIM +defparam hmc_inst.output_regd = ENUM_OUTPUT_REGD; //SYTH & SIM +defparam hmc_inst.pdn_exit_cycles = ENUM_PDN_EXIT_CYCLES; //SYTH & SIM +defparam hmc_inst.port0_width = ENUM_PORT0_WIDTH; //SYTH & SIM +defparam hmc_inst.port1_width = ENUM_PORT1_WIDTH; //SYTH & SIM +defparam hmc_inst.port2_width = ENUM_PORT2_WIDTH; //SYTH & SIM +defparam hmc_inst.port3_width = ENUM_PORT3_WIDTH; //SYTH & SIM +defparam hmc_inst.port4_width = ENUM_PORT4_WIDTH; //SYTH & SIM +defparam hmc_inst.port5_width = ENUM_PORT5_WIDTH; //SYTH & SIM +defparam hmc_inst.priority_0_0 = ENUM_PRIORITY_0_0; //SYTH ONLY +defparam hmc_inst.priority_0_1 = ENUM_PRIORITY_0_1; //SYTH ONLY +defparam hmc_inst.priority_0_2 = ENUM_PRIORITY_0_2; //SYTH ONLY +defparam hmc_inst.priority_0_3 = ENUM_PRIORITY_0_3; //SYTH ONLY +defparam hmc_inst.priority_0_4 = ENUM_PRIORITY_0_4; //SYTH ONLY +defparam hmc_inst.priority_0_5 = ENUM_PRIORITY_0_5; //SYTH ONLY +defparam hmc_inst.priority_1_0 = ENUM_PRIORITY_1_0; //SYTH ONLY +defparam hmc_inst.priority_1_1 = ENUM_PRIORITY_1_1; //SYTH ONLY +defparam hmc_inst.priority_1_2 = ENUM_PRIORITY_1_2; //SYTH ONLY +defparam hmc_inst.priority_1_3 = ENUM_PRIORITY_1_3; //SYTH ONLY +defparam hmc_inst.priority_1_4 = ENUM_PRIORITY_1_4; //SYTH ONLY +defparam hmc_inst.priority_1_5 = ENUM_PRIORITY_1_5; //SYTH ONLY +defparam hmc_inst.priority_2_0 = ENUM_PRIORITY_2_0; //SYTH ONLY +defparam hmc_inst.priority_2_1 = ENUM_PRIORITY_2_1; //SYTH ONLY +defparam hmc_inst.priority_2_2 = ENUM_PRIORITY_2_2; //SYTH ONLY +defparam hmc_inst.priority_2_3 = ENUM_PRIORITY_2_3; //SYTH ONLY +defparam hmc_inst.priority_2_4 = ENUM_PRIORITY_2_4; //SYTH ONLY +defparam hmc_inst.priority_2_5 = ENUM_PRIORITY_2_5; //SYTH ONLY +defparam hmc_inst.priority_3_0 = ENUM_PRIORITY_3_0; //SYTH ONLY +defparam hmc_inst.priority_3_1 = ENUM_PRIORITY_3_1; //SYTH ONLY +defparam hmc_inst.priority_3_2 = ENUM_PRIORITY_3_2; //SYTH ONLY +defparam hmc_inst.priority_3_3 = ENUM_PRIORITY_3_3; //SYTH ONLY +defparam hmc_inst.priority_3_4 = ENUM_PRIORITY_3_4; //SYTH ONLY +defparam hmc_inst.priority_3_5 = ENUM_PRIORITY_3_5; //SYTH ONLY +defparam hmc_inst.priority_4_0 = ENUM_PRIORITY_4_0; //SYTH ONLY +defparam hmc_inst.priority_4_1 = ENUM_PRIORITY_4_1; //SYTH ONLY +defparam hmc_inst.priority_4_2 = ENUM_PRIORITY_4_2; //SYTH ONLY +defparam hmc_inst.priority_4_3 = ENUM_PRIORITY_4_3; //SYTH ONLY +defparam hmc_inst.priority_4_4 = ENUM_PRIORITY_4_4; //SYTH ONLY +defparam hmc_inst.priority_4_5 = ENUM_PRIORITY_4_5; //SYTH ONLY +defparam hmc_inst.priority_5_0 = ENUM_PRIORITY_5_0; //SYTH ONLY +defparam hmc_inst.priority_5_1 = ENUM_PRIORITY_5_1; //SYTH ONLY +defparam hmc_inst.priority_5_2 = ENUM_PRIORITY_5_2; //SYTH ONLY +defparam hmc_inst.priority_5_3 = ENUM_PRIORITY_5_3; //SYTH ONLY +defparam hmc_inst.priority_5_4 = ENUM_PRIORITY_5_4; //SYTH ONLY +defparam hmc_inst.priority_5_5 = ENUM_PRIORITY_5_5; //SYTH ONLY +defparam hmc_inst.priority_6_0 = ENUM_PRIORITY_6_0; //SYTH ONLY +defparam hmc_inst.priority_6_1 = ENUM_PRIORITY_6_1; //SYTH ONLY +defparam hmc_inst.priority_6_2 = ENUM_PRIORITY_6_2; //SYTH ONLY +defparam hmc_inst.priority_6_3 = ENUM_PRIORITY_6_3; //SYTH ONLY +defparam hmc_inst.priority_6_4 = ENUM_PRIORITY_6_4; //SYTH ONLY +defparam hmc_inst.priority_6_5 = ENUM_PRIORITY_6_5; //SYTH ONLY +defparam hmc_inst.priority_7_0 = ENUM_PRIORITY_7_0; //SYTH ONLY +defparam hmc_inst.priority_7_1 = ENUM_PRIORITY_7_1; //SYTH ONLY +defparam hmc_inst.priority_7_2 = ENUM_PRIORITY_7_2; //SYTH ONLY +defparam hmc_inst.priority_7_3 = ENUM_PRIORITY_7_3; //SYTH ONLY +defparam hmc_inst.priority_7_4 = ENUM_PRIORITY_7_4; //SYTH ONLY +defparam hmc_inst.priority_7_5 = ENUM_PRIORITY_7_5; //SYTH ONLY +defparam hmc_inst.rcfg_static_weight_0 = ENUM_RCFG_STATIC_WEIGHT_0; //SYTH & SIM +defparam hmc_inst.rcfg_static_weight_1 = ENUM_RCFG_STATIC_WEIGHT_1; //SYTH & SIM +defparam hmc_inst.rcfg_static_weight_2 = ENUM_RCFG_STATIC_WEIGHT_2; //SYTH & SIM +defparam hmc_inst.rcfg_static_weight_3 = ENUM_RCFG_STATIC_WEIGHT_3; //SYTH & SIM +defparam hmc_inst.rcfg_static_weight_4 = ENUM_RCFG_STATIC_WEIGHT_4; //SYTH & SIM +defparam hmc_inst.rcfg_static_weight_5 = ENUM_RCFG_STATIC_WEIGHT_5; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_0 = INTG_RCFG_SUM_WT_PRIORITY_0; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_1 = INTG_RCFG_SUM_WT_PRIORITY_1; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_2 = INTG_RCFG_SUM_WT_PRIORITY_2; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_3 = INTG_RCFG_SUM_WT_PRIORITY_3; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_4 = INTG_RCFG_SUM_WT_PRIORITY_4; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_5 = INTG_RCFG_SUM_WT_PRIORITY_5; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_6 = INTG_RCFG_SUM_WT_PRIORITY_6; //SYTH & SIM +defparam hmc_inst.rcfg_sum_wt_priority_7 = INTG_RCFG_SUM_WT_PRIORITY_7; //SYTH & SIM +defparam hmc_inst.rcfg_user_priority_0 = ENUM_RCFG_USER_PRIORITY_0; //SYTH & SIM +defparam hmc_inst.rcfg_user_priority_1 = ENUM_RCFG_USER_PRIORITY_1; //SYTH & SIM +defparam hmc_inst.rcfg_user_priority_2 = ENUM_RCFG_USER_PRIORITY_2; //SYTH & SIM +defparam hmc_inst.rcfg_user_priority_3 = ENUM_RCFG_USER_PRIORITY_3; //SYTH & SIM +defparam hmc_inst.rcfg_user_priority_4 = ENUM_RCFG_USER_PRIORITY_4; //SYTH & SIM +defparam hmc_inst.rcfg_user_priority_5 = ENUM_RCFG_USER_PRIORITY_5; //SYTH & SIM +defparam hmc_inst.rd_dwidth_0 = ENUM_RD_DWIDTH_0; //SYTH ONLY +defparam hmc_inst.rd_dwidth_1 = ENUM_RD_DWIDTH_1; //SYTH ONLY +defparam hmc_inst.rd_dwidth_2 = ENUM_RD_DWIDTH_2; //SYTH ONLY +defparam hmc_inst.rd_dwidth_3 = ENUM_RD_DWIDTH_3; //SYTH ONLY +defparam hmc_inst.rd_dwidth_4 = ENUM_RD_DWIDTH_4; //SYTH ONLY +defparam hmc_inst.rd_dwidth_5 = ENUM_RD_DWIDTH_5; //SYTH ONLY +defparam hmc_inst.rd_fifo_in_use_0 = ENUM_RD_FIFO_IN_USE_0; //SYTH ONLY +defparam hmc_inst.rd_fifo_in_use_1 = ENUM_RD_FIFO_IN_USE_1; //SYTH ONLY +defparam hmc_inst.rd_fifo_in_use_2 = ENUM_RD_FIFO_IN_USE_2; //SYTH ONLY +defparam hmc_inst.rd_fifo_in_use_3 = ENUM_RD_FIFO_IN_USE_3; //SYTH ONLY +defparam hmc_inst.rd_port_info_0 = ENUM_RD_PORT_INFO_0; //SYTH ONLY +defparam hmc_inst.rd_port_info_1 = ENUM_RD_PORT_INFO_1; //SYTH ONLY +defparam hmc_inst.rd_port_info_2 = ENUM_RD_PORT_INFO_2; //SYTH ONLY +defparam hmc_inst.rd_port_info_3 = ENUM_RD_PORT_INFO_3; //SYTH ONLY +defparam hmc_inst.rd_port_info_4 = ENUM_RD_PORT_INFO_4; //SYTH ONLY +defparam hmc_inst.rd_port_info_5 = ENUM_RD_PORT_INFO_5; //SYTH ONLY +defparam hmc_inst.read_odt_chip = ENUM_READ_ODT_CHIP; //SYTH & SIM +defparam hmc_inst.reorder_data = ENUM_REORDER_DATA; //SYTH & SIM +defparam hmc_inst.rfifo0_cport_map = ENUM_RFIFO0_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.rfifo1_cport_map = ENUM_RFIFO1_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.rfifo2_cport_map = ENUM_RFIFO2_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.rfifo3_cport_map = ENUM_RFIFO3_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.single_ready_0 = ENUM_SINGLE_READY_0; //SYTH & SIM +defparam hmc_inst.single_ready_1 = ENUM_SINGLE_READY_1; //SYTH & SIM +defparam hmc_inst.single_ready_2 = ENUM_SINGLE_READY_2; //SYTH & SIM +defparam hmc_inst.single_ready_3 = ENUM_SINGLE_READY_3; //SYTH & SIM +defparam hmc_inst.static_weight_0 = ENUM_STATIC_WEIGHT_0; //SYTH ONLY +defparam hmc_inst.static_weight_1 = ENUM_STATIC_WEIGHT_1; //SYTH ONLY +defparam hmc_inst.static_weight_2 = ENUM_STATIC_WEIGHT_2; //SYTH ONLY +defparam hmc_inst.static_weight_3 = ENUM_STATIC_WEIGHT_3; //SYTH ONLY +defparam hmc_inst.static_weight_4 = ENUM_STATIC_WEIGHT_4; //SYTH ONLY +defparam hmc_inst.static_weight_5 = ENUM_STATIC_WEIGHT_5; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_0 = INTG_SUM_WT_PRIORITY_0; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_1 = INTG_SUM_WT_PRIORITY_1; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_2 = INTG_SUM_WT_PRIORITY_2; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_3 = INTG_SUM_WT_PRIORITY_3; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_4 = INTG_SUM_WT_PRIORITY_4; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_5 = INTG_SUM_WT_PRIORITY_5; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_6 = INTG_SUM_WT_PRIORITY_6; //SYTH ONLY +defparam hmc_inst.sum_wt_priority_7 = INTG_SUM_WT_PRIORITY_7; //SYTH ONLY +defparam hmc_inst.sync_mode_0 = ENUM_SYNC_MODE_0; //SYTH & SIM +defparam hmc_inst.sync_mode_1 = ENUM_SYNC_MODE_1; //SYTH & SIM +defparam hmc_inst.sync_mode_2 = ENUM_SYNC_MODE_2; //SYTH & SIM +defparam hmc_inst.sync_mode_3 = ENUM_SYNC_MODE_3; //SYTH & SIM +defparam hmc_inst.sync_mode_4 = ENUM_SYNC_MODE_4; //SYTH & SIM +defparam hmc_inst.sync_mode_5 = ENUM_SYNC_MODE_5; //SYTH & SIM +defparam hmc_inst.test_mode = ENUM_TEST_MODE; //SYTH & SIM +defparam hmc_inst.thld_jar1_0 = ENUM_THLD_JAR1_0; //SYTH & SIM +defparam hmc_inst.thld_jar1_1 = ENUM_THLD_JAR1_1; //SYTH & SIM +defparam hmc_inst.thld_jar1_2 = ENUM_THLD_JAR1_2; //SYTH & SIM +defparam hmc_inst.thld_jar1_3 = ENUM_THLD_JAR1_3; //SYTH & SIM +defparam hmc_inst.thld_jar1_4 = ENUM_THLD_JAR1_4; //SYTH & SIM +defparam hmc_inst.thld_jar1_5 = ENUM_THLD_JAR1_5; //SYTH & SIM +defparam hmc_inst.thld_jar2_0 = ENUM_THLD_JAR2_0; //SYTH & SIM +defparam hmc_inst.thld_jar2_1 = ENUM_THLD_JAR2_1; //SYTH & SIM +defparam hmc_inst.thld_jar2_2 = ENUM_THLD_JAR2_2; //SYTH & SIM +defparam hmc_inst.thld_jar2_3 = ENUM_THLD_JAR2_3; //SYTH & SIM +defparam hmc_inst.thld_jar2_4 = ENUM_THLD_JAR2_4; //SYTH & SIM +defparam hmc_inst.thld_jar2_5 = ENUM_THLD_JAR2_5; //SYTH & SIM +defparam hmc_inst.use_almost_empty_0 = ENUM_USE_ALMOST_EMPTY_0; //SYTH & SIM +defparam hmc_inst.use_almost_empty_1 = ENUM_USE_ALMOST_EMPTY_1; //SYTH & SIM +defparam hmc_inst.use_almost_empty_2 = ENUM_USE_ALMOST_EMPTY_2; //SYTH & SIM +defparam hmc_inst.use_almost_empty_3 = ENUM_USE_ALMOST_EMPTY_3; //SYTH & SIM +defparam hmc_inst.user_ecc_en = ENUM_USER_ECC_EN; //SYTH & SIM +defparam hmc_inst.user_priority_0 = ENUM_USER_PRIORITY_0; //SYTH ONLY +defparam hmc_inst.user_priority_1 = ENUM_USER_PRIORITY_1; //SYTH ONLY +defparam hmc_inst.user_priority_2 = ENUM_USER_PRIORITY_2; //SYTH ONLY +defparam hmc_inst.user_priority_3 = ENUM_USER_PRIORITY_3; //SYTH ONLY +defparam hmc_inst.user_priority_4 = ENUM_USER_PRIORITY_4; //SYTH ONLY +defparam hmc_inst.user_priority_5 = ENUM_USER_PRIORITY_5; //SYTH ONLY +defparam hmc_inst.wfifo0_cport_map = ENUM_WFIFO0_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.wfifo0_rdy_almost_full = ENUM_WFIFO0_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.wfifo1_cport_map = ENUM_WFIFO1_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.wfifo1_rdy_almost_full = ENUM_WFIFO1_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.wfifo2_cport_map = ENUM_WFIFO2_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.wfifo2_rdy_almost_full = ENUM_WFIFO2_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.wfifo3_cport_map = ENUM_WFIFO3_CPORT_MAP; //SYTH & SIM +defparam hmc_inst.wfifo3_rdy_almost_full = ENUM_WFIFO3_RDY_ALMOST_FULL; //SYTH & SIM +defparam hmc_inst.wr_dwidth_0 = ENUM_WR_DWIDTH_0; //SYTH ONLY +defparam hmc_inst.wr_dwidth_1 = ENUM_WR_DWIDTH_1; //SYTH ONLY +defparam hmc_inst.wr_dwidth_2 = ENUM_WR_DWIDTH_2; //SYTH ONLY +defparam hmc_inst.wr_dwidth_3 = ENUM_WR_DWIDTH_3; //SYTH ONLY +defparam hmc_inst.wr_dwidth_4 = ENUM_WR_DWIDTH_4; //SYTH ONLY +defparam hmc_inst.wr_dwidth_5 = ENUM_WR_DWIDTH_5; //SYTH ONLY +defparam hmc_inst.wr_fifo_in_use_0 = ENUM_WR_FIFO_IN_USE_0; //SYTH ONLY +defparam hmc_inst.wr_fifo_in_use_1 = ENUM_WR_FIFO_IN_USE_1; //SYTH ONLY +defparam hmc_inst.wr_fifo_in_use_2 = ENUM_WR_FIFO_IN_USE_2; //SYTH ONLY +defparam hmc_inst.wr_fifo_in_use_3 = ENUM_WR_FIFO_IN_USE_3; //SYTH ONLY +defparam hmc_inst.wr_port_info_0 = ENUM_WR_PORT_INFO_0; //SYTH ONLY +defparam hmc_inst.wr_port_info_1 = ENUM_WR_PORT_INFO_1; //SYTH ONLY +defparam hmc_inst.wr_port_info_2 = ENUM_WR_PORT_INFO_2; //SYTH ONLY +defparam hmc_inst.wr_port_info_3 = ENUM_WR_PORT_INFO_3; //SYTH ONLY +defparam hmc_inst.wr_port_info_4 = ENUM_WR_PORT_INFO_4; //SYTH ONLY +defparam hmc_inst.wr_port_info_5 = ENUM_WR_PORT_INFO_5; //SYTH ONLY +defparam hmc_inst.write_odt_chip = ENUM_WRITE_ODT_CHIP; //SYTH & SIM + +// END ATOM INSTANTIATION +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// START LOCAL FUNCTIONS + +// END LOCAL FUNCTIONS +//////////////////////////////////////////////////////////////////////////////// + +endmodule diff --git a/ip/altera/ddr3/altera_mem_if_oct_cyclonev.sv b/ip/altera/ddr3/altera_mem_if_oct_cyclonev.sv new file mode 100644 index 0000000..9535b86 --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_oct_cyclonev.sv @@ -0,0 +1,105 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// ******************************************************************************************************************************** +// This file instantiates the OCT block. +// ******************************************************************************************************************************** + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_oct; -name IP_TOOL_VERSION 15.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) + + +module altera_mem_if_oct_cyclonev ( + oct_rzqin, + parallelterminationcontrol, + seriesterminationcontrol +); + + +parameter OCT_TERM_CONTROL_WIDTH = 0; + + +// These should be connected to reference resistance pins on the board, via OCT control block if instantiated by user +input oct_rzqin; + +// for OCT master, termination control signals will be available to top level +output [OCT_TERM_CONTROL_WIDTH-1:0] parallelterminationcontrol; +output [OCT_TERM_CONTROL_WIDTH-1:0] seriesterminationcontrol; + + + + + + `ifndef ALTERA_RESERVED_QIS + // synopsys translate_off + `endif + tri0 oct_rzqin; + `ifndef ALTERA_RESERVED_QIS + // synopsys translate_on + `endif + + wire [0:0] wire_sd1a_serdataout; + + cyclonev_termination sd1a_0 + ( + .clkusrdftout(), + .compoutrdn(), + .compoutrup(), + .enserout(), + .rzqin(oct_rzqin), + .scanout(), + .serdataout(wire_sd1a_serdataout[0:0]), + .serdatatocore() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .clkenusr(1'b0), + .clkusr(1'b0), + .enserusr(1'b0), + .nclrusr(1'b0), + .otherenser({10{1'b0}}), + .scanclk(1'b0), + .scanen(1'b0), + .scanin(1'b0), + .serdatafromcore(1'b0), + .serdatain(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + + cyclonev_termination_logic sd2a_0 + ( + .parallelterminationcontrol(parallelterminationcontrol), + .serdata(wire_sd1a_serdataout), + .seriesterminationcontrol(seriesterminationcontrol) + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .enser(1'b0), + .s2pload(1'b0), + .scanclk(1'b0), + .scanenable(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + // synopsys translate_off + + // synopsys translate_on + ); + +endmodule + diff --git a/ip/altera/ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v b/ip/altera/ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v new file mode 100644 index 0000000..dd42276 --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v @@ -0,0 +1,2616 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + parameter intended_device_family = "Stratix V"; + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5, + the_altsyncram.intended_device_family = intended_device_family; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + parameter intended_device_family = "Stratix V"; + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5, + the_altsyncram.intended_device_family = intended_device_family; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst ( + // inputs: + clk, + d_irq, + d_readdata, + d_waitrequest, + i_readdata, + i_waitrequest, + reset_n, + + // outputs: + d_address, + d_byteenable, + d_read, + d_write, + d_writedata, + i_address, + i_read, + no_ci_readra + ) +; + + output [ 19: 0] d_address; + output [ 3: 0] d_byteenable; + output d_read; + output d_write; + output [ 31: 0] d_writedata; + output [ 16: 0] i_address; + output i_read; + output no_ci_readra; + input clk; + input [ 31: 0] d_irq; + input [ 31: 0] d_readdata; + input d_waitrequest; + input [ 31: 0] i_readdata; + input i_waitrequest; + input reset_n; + + wire [ 1: 0] D_compare_op; + wire D_ctrl_alu_force_xor; + wire D_ctrl_alu_signed_comparison; + wire D_ctrl_alu_subtract; + wire D_ctrl_b_is_dst; + wire D_ctrl_br; + wire D_ctrl_br_cmp; + wire D_ctrl_br_uncond; + wire D_ctrl_break; + wire D_ctrl_crst; + wire D_ctrl_custom; + wire D_ctrl_custom_multi; + wire D_ctrl_exception; + wire D_ctrl_force_src2_zero; + wire D_ctrl_hi_imm16; + wire D_ctrl_ignore_dst; + wire D_ctrl_implicit_dst_eretaddr; + wire D_ctrl_implicit_dst_retaddr; + wire D_ctrl_jmp_direct; + wire D_ctrl_jmp_indirect; + wire D_ctrl_ld; + wire D_ctrl_ld_io; + wire D_ctrl_ld_non_io; + wire D_ctrl_ld_signed; + wire D_ctrl_logic; + wire D_ctrl_rdctl_inst; + wire D_ctrl_retaddr; + wire D_ctrl_rot_right; + wire D_ctrl_shift_logical; + wire D_ctrl_shift_right_arith; + wire D_ctrl_shift_rot; + wire D_ctrl_shift_rot_right; + wire D_ctrl_src2_choose_imm; + wire D_ctrl_st; + wire D_ctrl_uncond_cti_non_br; + wire D_ctrl_unsigned_lo_imm16; + wire D_ctrl_wrctl_inst; + wire [ 4: 0] D_dst_regnum; + wire [ 55: 0] D_inst; + reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 4: 0] D_iw_a; + wire [ 4: 0] D_iw_b; + wire [ 4: 0] D_iw_c; + wire [ 2: 0] D_iw_control_regnum; + wire [ 7: 0] D_iw_custom_n; + wire D_iw_custom_readra; + wire D_iw_custom_readrb; + wire D_iw_custom_writerc; + wire [ 15: 0] D_iw_imm16; + wire [ 25: 0] D_iw_imm26; + wire [ 4: 0] D_iw_imm5; + wire [ 1: 0] D_iw_memsz; + wire [ 5: 0] D_iw_op; + wire [ 5: 0] D_iw_opx; + wire [ 4: 0] D_iw_shift_imm5; + wire [ 4: 0] D_iw_trap_break_imm5; + wire [ 14: 0] D_jmp_direct_target_waddr; + wire [ 1: 0] D_logic_op; + wire [ 1: 0] D_logic_op_raw; + wire D_mem16; + wire D_mem32; + wire D_mem8; + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + reg D_valid; + wire [ 55: 0] D_vinst; + wire D_wr_dst_reg; + wire [ 31: 0] E_alu_result; + reg E_alu_sub; + wire [ 32: 0] E_arith_result; + wire [ 31: 0] E_arith_src1; + wire [ 31: 0] E_arith_src2; + wire E_ci_multi_stall; + wire [ 31: 0] E_ci_result; + wire E_cmp_result; + wire [ 31: 0] E_control_rd_data; + wire E_eq; + reg E_invert_arith_src_msb; + wire E_ld_stall; + wire [ 31: 0] E_logic_result; + wire E_logic_result_is_0; + wire E_lt; + wire [ 19: 0] E_mem_baddr; + wire [ 3: 0] E_mem_byte_en; + reg E_new_inst; + reg [ 4: 0] E_shift_rot_cnt; + wire [ 4: 0] E_shift_rot_cnt_nxt; + wire E_shift_rot_done; + wire E_shift_rot_fill_bit; + reg [ 31: 0] E_shift_rot_result; + wire [ 31: 0] E_shift_rot_result_nxt; + wire E_shift_rot_stall; + reg [ 31: 0] E_src1; + reg [ 31: 0] E_src2; + wire [ 31: 0] E_st_data; + wire E_st_stall; + wire E_stall; + reg E_valid; + wire [ 55: 0] E_vinst; + wire E_wrctl_bstatus; + wire E_wrctl_estatus; + wire E_wrctl_ienable; + wire E_wrctl_status; + wire [ 31: 0] F_av_iw; + wire [ 4: 0] F_av_iw_a; + wire [ 4: 0] F_av_iw_b; + wire [ 4: 0] F_av_iw_c; + wire [ 2: 0] F_av_iw_control_regnum; + wire [ 7: 0] F_av_iw_custom_n; + wire F_av_iw_custom_readra; + wire F_av_iw_custom_readrb; + wire F_av_iw_custom_writerc; + wire [ 15: 0] F_av_iw_imm16; + wire [ 25: 0] F_av_iw_imm26; + wire [ 4: 0] F_av_iw_imm5; + wire [ 1: 0] F_av_iw_memsz; + wire [ 5: 0] F_av_iw_op; + wire [ 5: 0] F_av_iw_opx; + wire [ 4: 0] F_av_iw_shift_imm5; + wire [ 4: 0] F_av_iw_trap_break_imm5; + wire F_av_mem16; + wire F_av_mem32; + wire F_av_mem8; + wire [ 55: 0] F_inst; + wire [ 31: 0] F_iw; + wire [ 4: 0] F_iw_a; + wire [ 4: 0] F_iw_b; + wire [ 4: 0] F_iw_c; + wire [ 2: 0] F_iw_control_regnum; + wire [ 7: 0] F_iw_custom_n; + wire F_iw_custom_readra; + wire F_iw_custom_readrb; + wire F_iw_custom_writerc; + wire [ 15: 0] F_iw_imm16; + wire [ 25: 0] F_iw_imm26; + wire [ 4: 0] F_iw_imm5; + wire [ 1: 0] F_iw_memsz; + wire [ 5: 0] F_iw_op; + wire [ 5: 0] F_iw_opx; + wire [ 4: 0] F_iw_shift_imm5; + wire [ 4: 0] F_iw_trap_break_imm5; + wire F_mem16; + wire F_mem32; + wire F_mem8; + wire F_op_add; + wire F_op_addi; + wire F_op_and; + wire F_op_andhi; + wire F_op_andi; + wire F_op_beq; + wire F_op_bge; + wire F_op_bgeu; + wire F_op_blt; + wire F_op_bltu; + wire F_op_bne; + wire F_op_br; + wire F_op_break; + wire F_op_bret; + wire F_op_call; + wire F_op_callr; + wire F_op_cmpeq; + wire F_op_cmpeqi; + wire F_op_cmpge; + wire F_op_cmpgei; + wire F_op_cmpgeu; + wire F_op_cmpgeui; + wire F_op_cmplt; + wire F_op_cmplti; + wire F_op_cmpltu; + wire F_op_cmpltui; + wire F_op_cmpne; + wire F_op_cmpnei; + wire F_op_crst; + wire F_op_custom; + wire F_op_div; + wire F_op_divu; + wire F_op_eret; + wire F_op_flushd; + wire F_op_flushda; + wire F_op_flushi; + wire F_op_flushp; + wire F_op_hbreak; + wire F_op_initd; + wire F_op_initda; + wire F_op_initi; + wire F_op_intr; + wire F_op_jmp; + wire F_op_jmpi; + wire F_op_ldb; + wire F_op_ldbio; + wire F_op_ldbu; + wire F_op_ldbuio; + wire F_op_ldh; + wire F_op_ldhio; + wire F_op_ldhu; + wire F_op_ldhuio; + wire F_op_ldl; + wire F_op_ldw; + wire F_op_ldwio; + wire F_op_mul; + wire F_op_muli; + wire F_op_mulxss; + wire F_op_mulxsu; + wire F_op_mulxuu; + wire F_op_nextpc; + wire F_op_nor; + wire F_op_opx; + wire F_op_or; + wire F_op_orhi; + wire F_op_ori; + wire F_op_rdctl; + wire F_op_rdprs; + wire F_op_ret; + wire F_op_rol; + wire F_op_roli; + wire F_op_ror; + wire F_op_rsv02; + wire F_op_rsv09; + wire F_op_rsv10; + wire F_op_rsv17; + wire F_op_rsv18; + wire F_op_rsv25; + wire F_op_rsv26; + wire F_op_rsv33; + wire F_op_rsv34; + wire F_op_rsv41; + wire F_op_rsv42; + wire F_op_rsv49; + wire F_op_rsv57; + wire F_op_rsv61; + wire F_op_rsv62; + wire F_op_rsv63; + wire F_op_rsvx00; + wire F_op_rsvx10; + wire F_op_rsvx15; + wire F_op_rsvx17; + wire F_op_rsvx21; + wire F_op_rsvx25; + wire F_op_rsvx33; + wire F_op_rsvx34; + wire F_op_rsvx35; + wire F_op_rsvx42; + wire F_op_rsvx43; + wire F_op_rsvx44; + wire F_op_rsvx47; + wire F_op_rsvx50; + wire F_op_rsvx51; + wire F_op_rsvx55; + wire F_op_rsvx56; + wire F_op_rsvx60; + wire F_op_rsvx63; + wire F_op_sll; + wire F_op_slli; + wire F_op_sra; + wire F_op_srai; + wire F_op_srl; + wire F_op_srli; + wire F_op_stb; + wire F_op_stbio; + wire F_op_stc; + wire F_op_sth; + wire F_op_sthio; + wire F_op_stw; + wire F_op_stwio; + wire F_op_sub; + wire F_op_sync; + wire F_op_trap; + wire F_op_wrctl; + wire F_op_wrprs; + wire F_op_xor; + wire F_op_xorhi; + wire F_op_xori; + reg [ 14: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire F_pc_en; + wire [ 14: 0] F_pc_no_crst_nxt; + wire [ 14: 0] F_pc_nxt; + wire [ 14: 0] F_pc_plus_one; + wire [ 1: 0] F_pc_sel_nxt; + wire [ 16: 0] F_pcb; + wire [ 16: 0] F_pcb_nxt; + wire [ 16: 0] F_pcb_plus_four; + wire F_valid; + wire [ 55: 0] F_vinst; + reg [ 1: 0] R_compare_op; + reg R_ctrl_alu_force_xor; + wire R_ctrl_alu_force_xor_nxt; + reg R_ctrl_alu_signed_comparison; + wire R_ctrl_alu_signed_comparison_nxt; + reg R_ctrl_alu_subtract; + wire R_ctrl_alu_subtract_nxt; + reg R_ctrl_b_is_dst; + wire R_ctrl_b_is_dst_nxt; + reg R_ctrl_br; + reg R_ctrl_br_cmp; + wire R_ctrl_br_cmp_nxt; + wire R_ctrl_br_nxt; + reg R_ctrl_br_uncond; + wire R_ctrl_br_uncond_nxt; + reg R_ctrl_break; + wire R_ctrl_break_nxt; + reg R_ctrl_crst; + wire R_ctrl_crst_nxt; + reg R_ctrl_custom; + reg R_ctrl_custom_multi; + wire R_ctrl_custom_multi_nxt; + wire R_ctrl_custom_nxt; + reg R_ctrl_exception; + wire R_ctrl_exception_nxt; + reg R_ctrl_force_src2_zero; + wire R_ctrl_force_src2_zero_nxt; + reg R_ctrl_hi_imm16; + wire R_ctrl_hi_imm16_nxt; + reg R_ctrl_ignore_dst; + wire R_ctrl_ignore_dst_nxt; + reg R_ctrl_implicit_dst_eretaddr; + wire R_ctrl_implicit_dst_eretaddr_nxt; + reg R_ctrl_implicit_dst_retaddr; + wire R_ctrl_implicit_dst_retaddr_nxt; + reg R_ctrl_jmp_direct; + wire R_ctrl_jmp_direct_nxt; + reg R_ctrl_jmp_indirect; + wire R_ctrl_jmp_indirect_nxt; + reg R_ctrl_ld; + reg R_ctrl_ld_io; + wire R_ctrl_ld_io_nxt; + reg R_ctrl_ld_non_io; + wire R_ctrl_ld_non_io_nxt; + wire R_ctrl_ld_nxt; + reg R_ctrl_ld_signed; + wire R_ctrl_ld_signed_nxt; + reg R_ctrl_logic; + wire R_ctrl_logic_nxt; + reg R_ctrl_rdctl_inst; + wire R_ctrl_rdctl_inst_nxt; + reg R_ctrl_retaddr; + wire R_ctrl_retaddr_nxt; + reg R_ctrl_rot_right; + wire R_ctrl_rot_right_nxt; + reg R_ctrl_shift_logical; + wire R_ctrl_shift_logical_nxt; + reg R_ctrl_shift_right_arith; + wire R_ctrl_shift_right_arith_nxt; + reg R_ctrl_shift_rot; + wire R_ctrl_shift_rot_nxt; + reg R_ctrl_shift_rot_right; + wire R_ctrl_shift_rot_right_nxt; + reg R_ctrl_src2_choose_imm; + wire R_ctrl_src2_choose_imm_nxt; + reg R_ctrl_st; + wire R_ctrl_st_nxt; + reg R_ctrl_uncond_cti_non_br; + wire R_ctrl_uncond_cti_non_br_nxt; + reg R_ctrl_unsigned_lo_imm16; + wire R_ctrl_unsigned_lo_imm16_nxt; + reg R_ctrl_wrctl_inst; + wire R_ctrl_wrctl_inst_nxt; + reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire R_en; + reg [ 1: 0] R_logic_op; + wire [ 31: 0] R_rf_a; + wire [ 31: 0] R_rf_b; + wire [ 31: 0] R_src1; + wire [ 31: 0] R_src2; + wire [ 15: 0] R_src2_hi; + wire [ 15: 0] R_src2_lo; + reg R_src2_use_imm; + wire [ 7: 0] R_stb_data; + wire [ 15: 0] R_sth_data; + reg R_valid; + wire [ 55: 0] R_vinst; + reg R_wr_dst_reg; + reg [ 31: 0] W_alu_result; + wire W_br_taken; + reg W_bstatus_reg; + wire W_bstatus_reg_inst_nxt; + wire W_bstatus_reg_nxt; + reg W_cmp_result; + reg [ 31: 0] W_control_rd_data; + reg W_estatus_reg; + wire W_estatus_reg_inst_nxt; + wire W_estatus_reg_nxt; + reg [ 31: 0] W_ienable_reg; + wire [ 31: 0] W_ienable_reg_nxt; + reg [ 31: 0] W_ipending_reg; + wire [ 31: 0] W_ipending_reg_nxt; + wire [ 19: 0] W_mem_baddr; + wire [ 31: 0] W_rf_wr_data; + wire W_rf_wren; + wire W_status_reg; + reg W_status_reg_pie; + wire W_status_reg_pie_inst_nxt; + wire W_status_reg_pie_nxt; + reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 55: 0] W_vinst; + wire [ 31: 0] W_wr_data; + wire [ 31: 0] W_wr_data_non_zero; + wire av_fill_bit; + reg [ 1: 0] av_ld_align_cycle; + wire [ 1: 0] av_ld_align_cycle_nxt; + wire av_ld_align_one_more_cycle; + reg av_ld_aligning_data; + wire av_ld_aligning_data_nxt; + reg [ 7: 0] av_ld_byte0_data; + wire [ 7: 0] av_ld_byte0_data_nxt; + reg [ 7: 0] av_ld_byte1_data; + wire av_ld_byte1_data_en; + wire [ 7: 0] av_ld_byte1_data_nxt; + reg [ 7: 0] av_ld_byte2_data; + wire [ 7: 0] av_ld_byte2_data_nxt; + reg [ 7: 0] av_ld_byte3_data; + wire [ 7: 0] av_ld_byte3_data_nxt; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire [ 31: 0] av_ld_data_aligned_unfiltered; + wire av_ld_done; + wire av_ld_extend; + wire av_ld_getting_data; + wire av_ld_rshift8; + reg av_ld_waiting_for_data; + wire av_ld_waiting_for_data_nxt; + wire av_sign_bit; + wire [ 19: 0] d_address; + reg [ 3: 0] d_byteenable; + reg d_read; + wire d_read_nxt; + wire d_write; + wire d_write_nxt; + reg [ 31: 0] d_writedata; + wire hbreak_req; + wire [ 16: 0] i_address; + reg i_read; + wire i_read_nxt; + wire [ 31: 0] iactive; + wire intr_req; + wire no_ci_readra; + wire [ 31: 0] oci_ienable; + wire test_has_ended; + parameter DEVICE_FAMILY = "Cyclone V"; + //the_altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench, which is an e_instance + altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench the_altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench + ( + .D_iw (D_iw), + .D_iw_op (D_iw_op), + .D_iw_opx (D_iw_opx), + .D_valid (D_valid), + .E_alu_result (E_alu_result), + .E_mem_byte_en (E_mem_byte_en), + .E_st_data (E_st_data), + .E_valid (E_valid), + .F_pcb (F_pcb), + .F_valid (F_valid), + .R_ctrl_exception (R_ctrl_exception), + .R_ctrl_ld (R_ctrl_ld), + .R_ctrl_ld_non_io (R_ctrl_ld_non_io), + .R_dst_regnum (R_dst_regnum), + .R_wr_dst_reg (R_wr_dst_reg), + .W_bstatus_reg (W_bstatus_reg), + .W_cmp_result (W_cmp_result), + .W_estatus_reg (W_estatus_reg), + .W_ienable_reg (W_ienable_reg), + .W_ipending_reg (W_ipending_reg), + .W_mem_baddr (W_mem_baddr), + .W_rf_wr_data (W_rf_wr_data), + .W_status_reg (W_status_reg), + .W_valid (W_valid), + .W_vinst (W_vinst), + .W_wr_data (W_wr_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), + .clk (clk), + .d_address (d_address), + .d_byteenable (d_byteenable), + .d_read (d_read), + .d_write (d_write), + .d_write_nxt (d_write_nxt), + .i_address (i_address), + .i_read (i_read), + .i_readdata (i_readdata), + .i_waitrequest (i_waitrequest), + .reset_n (reset_n), + .test_has_ended (test_has_ended) + ); + + assign F_av_iw_a = F_av_iw[31 : 27]; + assign F_av_iw_b = F_av_iw[26 : 22]; + assign F_av_iw_c = F_av_iw[21 : 17]; + assign F_av_iw_custom_n = F_av_iw[13 : 6]; + assign F_av_iw_custom_readra = F_av_iw[16]; + assign F_av_iw_custom_readrb = F_av_iw[15]; + assign F_av_iw_custom_writerc = F_av_iw[14]; + assign F_av_iw_opx = F_av_iw[16 : 11]; + assign F_av_iw_op = F_av_iw[5 : 0]; + assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm16 = F_av_iw[21 : 6]; + assign F_av_iw_imm26 = F_av_iw[31 : 6]; + assign F_av_iw_memsz = F_av_iw[4 : 3]; + assign F_av_iw_control_regnum = F_av_iw[8 : 6]; + assign F_av_mem8 = F_av_iw_memsz == 2'b00; + assign F_av_mem16 = F_av_iw_memsz == 2'b01; + assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; + assign F_iw_a = F_iw[31 : 27]; + assign F_iw_b = F_iw[26 : 22]; + assign F_iw_c = F_iw[21 : 17]; + assign F_iw_custom_n = F_iw[13 : 6]; + assign F_iw_custom_readra = F_iw[16]; + assign F_iw_custom_readrb = F_iw[15]; + assign F_iw_custom_writerc = F_iw[14]; + assign F_iw_opx = F_iw[16 : 11]; + assign F_iw_op = F_iw[5 : 0]; + assign F_iw_shift_imm5 = F_iw[10 : 6]; + assign F_iw_trap_break_imm5 = F_iw[10 : 6]; + assign F_iw_imm5 = F_iw[10 : 6]; + assign F_iw_imm16 = F_iw[21 : 6]; + assign F_iw_imm26 = F_iw[31 : 6]; + assign F_iw_memsz = F_iw[4 : 3]; + assign F_iw_control_regnum = F_iw[8 : 6]; + assign F_mem8 = F_iw_memsz == 2'b00; + assign F_mem16 = F_iw_memsz == 2'b01; + assign F_mem32 = F_iw_memsz[1] == 1'b1; + assign D_iw_a = D_iw[31 : 27]; + assign D_iw_b = D_iw[26 : 22]; + assign D_iw_c = D_iw[21 : 17]; + assign D_iw_custom_n = D_iw[13 : 6]; + assign D_iw_custom_readra = D_iw[16]; + assign D_iw_custom_readrb = D_iw[15]; + assign D_iw_custom_writerc = D_iw[14]; + assign D_iw_opx = D_iw[16 : 11]; + assign D_iw_op = D_iw[5 : 0]; + assign D_iw_shift_imm5 = D_iw[10 : 6]; + assign D_iw_trap_break_imm5 = D_iw[10 : 6]; + assign D_iw_imm5 = D_iw[10 : 6]; + assign D_iw_imm16 = D_iw[21 : 6]; + assign D_iw_imm26 = D_iw[31 : 6]; + assign D_iw_memsz = D_iw[4 : 3]; + assign D_iw_control_regnum = D_iw[8 : 6]; + assign D_mem8 = D_iw_memsz == 2'b00; + assign D_mem16 = D_iw_memsz == 2'b01; + assign D_mem32 = D_iw_memsz[1] == 1'b1; + assign F_op_call = F_iw_op == 0; + assign F_op_jmpi = F_iw_op == 1; + assign F_op_ldbu = F_iw_op == 3; + assign F_op_addi = F_iw_op == 4; + assign F_op_stb = F_iw_op == 5; + assign F_op_br = F_iw_op == 6; + assign F_op_ldb = F_iw_op == 7; + assign F_op_cmpgei = F_iw_op == 8; + assign F_op_ldhu = F_iw_op == 11; + assign F_op_andi = F_iw_op == 12; + assign F_op_sth = F_iw_op == 13; + assign F_op_bge = F_iw_op == 14; + assign F_op_ldh = F_iw_op == 15; + assign F_op_cmplti = F_iw_op == 16; + assign F_op_initda = F_iw_op == 19; + assign F_op_ori = F_iw_op == 20; + assign F_op_stw = F_iw_op == 21; + assign F_op_blt = F_iw_op == 22; + assign F_op_ldw = F_iw_op == 23; + assign F_op_cmpnei = F_iw_op == 24; + assign F_op_flushda = F_iw_op == 27; + assign F_op_xori = F_iw_op == 28; + assign F_op_stc = F_iw_op == 29; + assign F_op_bne = F_iw_op == 30; + assign F_op_ldl = F_iw_op == 31; + assign F_op_cmpeqi = F_iw_op == 32; + assign F_op_ldbuio = F_iw_op == 35; + assign F_op_muli = F_iw_op == 36; + assign F_op_stbio = F_iw_op == 37; + assign F_op_beq = F_iw_op == 38; + assign F_op_ldbio = F_iw_op == 39; + assign F_op_cmpgeui = F_iw_op == 40; + assign F_op_ldhuio = F_iw_op == 43; + assign F_op_andhi = F_iw_op == 44; + assign F_op_sthio = F_iw_op == 45; + assign F_op_bgeu = F_iw_op == 46; + assign F_op_ldhio = F_iw_op == 47; + assign F_op_cmpltui = F_iw_op == 48; + assign F_op_initd = F_iw_op == 51; + assign F_op_orhi = F_iw_op == 52; + assign F_op_stwio = F_iw_op == 53; + assign F_op_bltu = F_iw_op == 54; + assign F_op_ldwio = F_iw_op == 55; + assign F_op_rdprs = F_iw_op == 56; + assign F_op_flushd = F_iw_op == 59; + assign F_op_xorhi = F_iw_op == 60; + assign F_op_rsv02 = F_iw_op == 2; + assign F_op_rsv09 = F_iw_op == 9; + assign F_op_rsv10 = F_iw_op == 10; + assign F_op_rsv17 = F_iw_op == 17; + assign F_op_rsv18 = F_iw_op == 18; + assign F_op_rsv25 = F_iw_op == 25; + assign F_op_rsv26 = F_iw_op == 26; + assign F_op_rsv33 = F_iw_op == 33; + assign F_op_rsv34 = F_iw_op == 34; + assign F_op_rsv41 = F_iw_op == 41; + assign F_op_rsv42 = F_iw_op == 42; + assign F_op_rsv49 = F_iw_op == 49; + assign F_op_rsv57 = F_iw_op == 57; + assign F_op_rsv61 = F_iw_op == 61; + assign F_op_rsv62 = F_iw_op == 62; + assign F_op_rsv63 = F_iw_op == 63; + assign F_op_eret = F_op_opx & (F_iw_opx == 1); + assign F_op_roli = F_op_opx & (F_iw_opx == 2); + assign F_op_rol = F_op_opx & (F_iw_opx == 3); + assign F_op_flushp = F_op_opx & (F_iw_opx == 4); + assign F_op_ret = F_op_opx & (F_iw_opx == 5); + assign F_op_nor = F_op_opx & (F_iw_opx == 6); + assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); + assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); + assign F_op_bret = F_op_opx & (F_iw_opx == 9); + assign F_op_ror = F_op_opx & (F_iw_opx == 11); + assign F_op_flushi = F_op_opx & (F_iw_opx == 12); + assign F_op_jmp = F_op_opx & (F_iw_opx == 13); + assign F_op_and = F_op_opx & (F_iw_opx == 14); + assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); + assign F_op_slli = F_op_opx & (F_iw_opx == 18); + assign F_op_sll = F_op_opx & (F_iw_opx == 19); + assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); + assign F_op_or = F_op_opx & (F_iw_opx == 22); + assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); + assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); + assign F_op_srli = F_op_opx & (F_iw_opx == 26); + assign F_op_srl = F_op_opx & (F_iw_opx == 27); + assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); + assign F_op_callr = F_op_opx & (F_iw_opx == 29); + assign F_op_xor = F_op_opx & (F_iw_opx == 30); + assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); + assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); + assign F_op_divu = F_op_opx & (F_iw_opx == 36); + assign F_op_div = F_op_opx & (F_iw_opx == 37); + assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); + assign F_op_mul = F_op_opx & (F_iw_opx == 39); + assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); + assign F_op_initi = F_op_opx & (F_iw_opx == 41); + assign F_op_trap = F_op_opx & (F_iw_opx == 45); + assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); + assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); + assign F_op_add = F_op_opx & (F_iw_opx == 49); + assign F_op_break = F_op_opx & (F_iw_opx == 52); + assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); + assign F_op_sync = F_op_opx & (F_iw_opx == 54); + assign F_op_sub = F_op_opx & (F_iw_opx == 57); + assign F_op_srai = F_op_opx & (F_iw_opx == 58); + assign F_op_sra = F_op_opx & (F_iw_opx == 59); + assign F_op_intr = F_op_opx & (F_iw_opx == 61); + assign F_op_crst = F_op_opx & (F_iw_opx == 62); + assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); + assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); + assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); + assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); + assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); + assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); + assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); + assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); + assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); + assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); + assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); + assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); + assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); + assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); + assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); + assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); + assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); + assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); + assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); + assign F_op_opx = F_iw_op == 58; + assign F_op_custom = F_iw_op == 50; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + assign R_en = 1'b1; + assign E_ci_result = 0; + //custom_instruction_master, which is an e_custom_instruction_master + assign no_ci_readra = 1'b0; + assign E_ci_multi_stall = 1'b0; + assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000000; + assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : + R_ctrl_break ? 2'b01 : + (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : + 2'b11; + + assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 16392 : + (F_pc_sel_nxt == 2'b01)? 16392 : + (F_pc_sel_nxt == 2'b10)? E_arith_result[16 : 2] : + F_pc_plus_one; + + assign F_pc_nxt = F_pc_no_crst_nxt; + assign F_pcb_nxt = {F_pc_nxt, 2'b00}; + assign F_pc_en = W_valid; + assign F_pc_plus_one = F_pc + 1; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + F_pc <= 16384; + else if (F_pc_en) + F_pc <= F_pc_nxt; + end + + + assign F_pcb = {F_pc, 2'b00}; + assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; + assign F_valid = i_read & ~i_waitrequest; + assign i_read_nxt = W_valid | (i_read & i_waitrequest); + assign i_address = {F_pc, 2'b00}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + i_read <= 1'b1; + else + i_read <= i_read_nxt; + end + + + assign hbreak_req = 1'b0; + assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); + assign F_av_iw = i_readdata; + assign F_iw = hbreak_req ? 4040762 : + 1'b0 ? 127034 : + intr_req ? 3926074 : + F_av_iw; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_iw <= 0; + else if (F_valid) + D_iw <= F_iw; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_valid <= 0; + else + D_valid <= F_valid; + end + + + assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : + D_ctrl_implicit_dst_eretaddr ? 5'd29 : + D_ctrl_b_is_dst ? D_iw_b : + D_iw_c; + + assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; + assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; + assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_jmp_direct_target_waddr = D_iw[31 : 6]; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_valid <= 0; + else + R_valid <= D_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_wr_dst_reg <= 0; + else + R_wr_dst_reg <= D_wr_dst_reg; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_dst_regnum <= 0; + else + R_dst_regnum <= D_dst_regnum; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_logic_op <= 0; + else + R_logic_op <= D_logic_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_compare_op <= 0; + else + R_compare_op <= D_compare_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_src2_use_imm <= 0; + else + R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); + end + + + assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; + assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; +//altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a, which is an nios_sdp_ram +altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_a), + .rdaddress (D_iw_a), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_a.dat"; +`else +defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_a.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_a.mif"; +//synthesis read_comments_as_HDL off +//altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b, which is an nios_sdp_ram +defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.intended_device_family = DEVICE_FAMILY; +altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_b), + .rdaddress (D_iw_b), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_b.dat"; +`else +defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_b.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_b.mif"; +//synthesis read_comments_as_HDL off +defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.intended_device_family = DEVICE_FAMILY; + assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : + ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : + R_rf_a; + + assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : + (R_src2_use_imm)? D_iw_imm16 : + R_rf_b[15 : 0]; + + assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : + (R_ctrl_hi_imm16)? D_iw_imm16 : + (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : + R_rf_b[31 : 16]; + + assign R_src2 = {R_src2_hi, R_src2_lo}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_valid <= 0; + else + E_valid <= R_valid | E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_new_inst <= 0; + else + E_new_inst <= R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src1 <= 0; + else + E_src1 <= R_src1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src2 <= 0; + else + E_src2 <= R_src2; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_invert_arith_src_msb <= 0; + else + E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_alu_sub <= 0; + else + E_alu_sub <= D_ctrl_alu_subtract & R_valid; + end + + + assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; + assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, + E_src1[30 : 0]}; + + assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, + E_src2[30 : 0]}; + + assign E_arith_result = E_alu_sub ? + E_arith_src1 - E_arith_src2 : + E_arith_src1 + E_arith_src2; + + assign E_mem_baddr = E_arith_result[19 : 0]; + assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : + (R_logic_op == 2'b01)? (E_src1 & E_src2) : + (R_logic_op == 2'b10)? (E_src1 | E_src2) : + (E_src1 ^ E_src2); + + assign E_logic_result_is_0 = E_logic_result == 0; + assign E_eq = E_logic_result_is_0; + assign E_lt = E_arith_result[32]; + assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : + (R_compare_op == 2'b01)? ~E_lt : + (R_compare_op == 2'b10)? E_lt : + ~E_eq; + + assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; + assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; + assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; + assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : + (R_ctrl_rot_right ? E_shift_rot_result[0] : + E_shift_rot_result[31]); + + assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : + (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : + {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_result <= 0; + else + E_shift_rot_result <= E_shift_rot_result_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_cnt <= 0; + else + E_shift_rot_cnt <= E_shift_rot_cnt_nxt; + end + + + assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : + (D_iw_control_regnum == 3'd1)? W_estatus_reg : + (D_iw_control_regnum == 3'd2)? W_bstatus_reg : + (D_iw_control_regnum == 3'd3)? W_ienable_reg : + (D_iw_control_regnum == 3'd4)? W_ipending_reg : + 0; + + assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : + (R_ctrl_shift_rot)? E_shift_rot_result : + (R_ctrl_logic)? E_logic_result : + (R_ctrl_custom)? E_ci_result : + E_arith_result; + + assign R_stb_data = R_rf_b[7 : 0]; + assign R_sth_data = R_rf_b[15 : 0]; + assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : + (D_mem16)? {R_sth_data, R_sth_data} : + R_rf_b; + + assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : + 4'b1111; + + assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); + assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); + assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); + assign E_st_stall = d_write_nxt; + assign d_address = W_mem_baddr; + assign av_ld_getting_data = d_read & ~d_waitrequest; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_read <= 0; + else + d_read <= d_read_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_writedata <= 0; + else + d_writedata <= E_st_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_byteenable <= 0; + else + d_byteenable <= E_mem_byte_en; + end + + + assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); + assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); + assign av_ld_aligning_data_nxt = av_ld_aligning_data ? + ~av_ld_align_one_more_cycle : + (~D_mem32 & av_ld_getting_data); + + assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? + ~av_ld_getting_data : + (R_ctrl_ld & E_new_inst); + + assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); + assign av_ld_rshift8 = av_ld_aligning_data & + (av_ld_align_cycle < (W_mem_baddr[1 : 0])); + + assign av_ld_extend = av_ld_aligning_data; + assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : + av_ld_extend ? av_ld_byte0_data : + d_readdata[7 : 0]; + + assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[15 : 8]; + + assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[23 : 16]; + + assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[31 : 24]; + + assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); + assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, + av_ld_byte1_data, av_ld_byte0_data}; + + assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; + assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_align_cycle <= 0; + else + av_ld_align_cycle <= av_ld_align_cycle_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_waiting_for_data <= 0; + else + av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_aligning_data <= 0; + else + av_ld_aligning_data <= av_ld_aligning_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte0_data <= 0; + else + av_ld_byte0_data <= av_ld_byte0_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte1_data <= 0; + else if (av_ld_byte1_data_en) + av_ld_byte1_data <= av_ld_byte1_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte2_data <= 0; + else + av_ld_byte2_data <= av_ld_byte2_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte3_data <= 0; + else + av_ld_byte3_data <= av_ld_byte3_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_valid <= 0; + else + W_valid <= E_valid & ~E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_control_rd_data <= 0; + else + W_control_rd_data <= E_control_rd_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_cmp_result <= 0; + else + W_cmp_result <= E_cmp_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_alu_result <= 0; + else + W_alu_result <= E_alu_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_status_reg_pie <= 0; + else + W_status_reg_pie <= W_status_reg_pie_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_estatus_reg <= 0; + else + W_estatus_reg <= W_estatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_bstatus_reg <= 0; + else + W_bstatus_reg <= W_bstatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ienable_reg <= 0; + else + W_ienable_reg <= W_ienable_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ipending_reg <= 0; + else + W_ipending_reg <= W_ipending_reg_nxt; + end + + + assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : + R_ctrl_rdctl_inst ? W_control_rd_data : + W_alu_result[31 : 0]; + + assign W_wr_data = W_wr_data_non_zero; + assign W_br_taken = R_ctrl_br & W_cmp_result; + assign W_mem_baddr = W_alu_result[19 : 0]; + assign W_status_reg = W_status_reg_pie; + assign E_wrctl_status = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd0); + + assign E_wrctl_estatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd1); + + assign E_wrctl_bstatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd2); + + assign E_wrctl_ienable = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd3); + + assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : + (D_op_eret) ? W_estatus_reg : + (D_op_bret) ? W_bstatus_reg : + (E_wrctl_status) ? E_src1[0] : + W_status_reg_pie; + + assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; + assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : + (R_ctrl_exception) ? W_status_reg : + (E_wrctl_estatus) ? E_src1[0] : + W_estatus_reg; + + assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; + assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : + (E_wrctl_bstatus) ? E_src1[0] : + W_bstatus_reg; + + assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; + assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? + E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000000; + + assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000000; + assign oci_ienable = {32{1'b1}}; + assign D_ctrl_custom = 1'b0; + assign R_ctrl_custom_nxt = D_ctrl_custom; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom <= 0; + else if (R_en) + R_ctrl_custom <= R_ctrl_custom_nxt; + end + + + assign D_ctrl_custom_multi = 1'b0; + assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom_multi <= 0; + else if (R_en) + R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; + end + + + assign D_ctrl_jmp_indirect = D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_indirect <= 0; + else if (R_en) + R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; + end + + + assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; + assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_direct <= 0; + else if (R_en) + R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; + end + + + assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; + assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_retaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; + end + + + assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; + assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_eretaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; + end + + + assign D_ctrl_exception = D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60; + + assign R_ctrl_exception_nxt = D_ctrl_exception; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_exception <= 0; + else if (R_en) + R_ctrl_exception <= R_ctrl_exception_nxt; + end + + + assign D_ctrl_break = D_op_break|D_op_hbreak; + assign R_ctrl_break_nxt = D_ctrl_break; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_break <= 0; + else if (R_en) + R_ctrl_break <= R_ctrl_break_nxt; + end + + + assign D_ctrl_crst = D_op_crst|D_op_rsvx63; + assign R_ctrl_crst_nxt = D_ctrl_crst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_crst <= 0; + else if (R_en) + R_ctrl_crst <= R_ctrl_crst_nxt; + end + + + assign D_ctrl_uncond_cti_non_br = D_op_call| + D_op_jmpi| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_uncond_cti_non_br <= 0; + else if (R_en) + R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; + end + + + assign D_ctrl_retaddr = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak; + + assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_retaddr <= 0; + else if (R_en) + R_ctrl_retaddr <= R_ctrl_retaddr_nxt; + end + + + assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; + assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_logical <= 0; + else if (R_en) + R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; + end + + + assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; + assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_right_arith <= 0; + else if (R_en) + R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; + end + + + assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; + assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rot_right <= 0; + else if (R_en) + R_ctrl_rot_right <= R_ctrl_rot_right_nxt; + end + + + assign D_ctrl_shift_rot_right = D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot_right <= 0; + else if (R_en) + R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; + end + + + assign D_ctrl_shift_rot = D_op_slli| + D_op_rsvx50| + D_op_sll| + D_op_rsvx51| + D_op_roli| + D_op_rsvx34| + D_op_rol| + D_op_rsvx35| + D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot <= 0; + else if (R_en) + R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; + end + + + assign D_ctrl_logic = D_op_and| + D_op_or| + D_op_xor| + D_op_nor| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori; + + assign R_ctrl_logic_nxt = D_ctrl_logic; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_logic <= 0; + else if (R_en) + R_ctrl_logic <= R_ctrl_logic_nxt; + end + + + assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; + assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_hi_imm16 <= 0; + else if (R_en) + R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; + end + + + assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| + D_op_cmpltui| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_unsigned_lo_imm16 <= 0; + else if (R_en) + R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; + end + + + assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; + assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_uncond <= 0; + else if (R_en) + R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; + end + + + assign D_ctrl_br = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62; + + assign R_ctrl_br_nxt = D_ctrl_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br <= 0; + else if (R_en) + R_ctrl_br <= R_ctrl_br_nxt; + end + + + assign D_ctrl_alu_subtract = D_op_sub| + D_op_rsvx25| + D_op_cmplti| + D_op_cmpltui| + D_op_cmplt| + D_op_cmpltu| + D_op_blt| + D_op_bltu| + D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpge| + D_op_cmpgeu| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42; + + assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_subtract <= 0; + else if (R_en) + R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; + end + + + assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; + assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_signed_comparison <= 0; + else if (R_en) + R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; + end + + + assign D_ctrl_br_cmp = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_rsvx00| + D_op_cmpge| + D_op_cmplt| + D_op_cmpne| + D_op_cmpgeu| + D_op_cmpltu| + D_op_cmpeq| + D_op_rsvx56; + + assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_cmp <= 0; + else if (R_en) + R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; + end + + + assign D_ctrl_ld_signed = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63; + + assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_signed <= 0; + else if (R_en) + R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; + end + + + assign D_ctrl_ld = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio; + + assign R_ctrl_ld_nxt = D_ctrl_ld; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld <= 0; + else if (R_en) + R_ctrl_ld <= R_ctrl_ld_nxt; + end + + + assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; + assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_non_io <= 0; + else if (R_en) + R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; + end + + + assign D_ctrl_st = D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61; + + assign R_ctrl_st_nxt = D_ctrl_st; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_st <= 0; + else if (R_en) + R_ctrl_st <= R_ctrl_st_nxt; + end + + + assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; + assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_io <= 0; + else if (R_en) + R_ctrl_ld_io <= R_ctrl_ld_io_nxt; + end + + + assign D_ctrl_b_is_dst = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda; + + assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_b_is_dst <= 0; + else if (R_en) + R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; + end + + + assign D_ctrl_ignore_dst = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57; + + assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ignore_dst <= 0; + else if (R_en) + R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; + end + + + assign D_ctrl_src2_choose_imm = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_src2_choose_imm <= 0; + else if (R_en) + R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; + end + + + assign D_ctrl_wrctl_inst = D_op_wrctl; + assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_wrctl_inst <= 0; + else if (R_en) + R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; + end + + + assign D_ctrl_rdctl_inst = D_op_rdctl; + assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rdctl_inst <= 0; + else if (R_en) + R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; + end + + + assign D_ctrl_force_src2_zero = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_jmpi; + + assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_force_src2_zero <= 0; + else if (R_en) + R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; + end + + + assign D_ctrl_alu_force_xor = D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpeqi| + D_op_cmpge| + D_op_cmpgeu| + D_op_cmpeq| + D_op_cmpnei| + D_op_cmpne| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42| + D_op_beq| + D_op_rsv34| + D_op_bne| + D_op_rsv62| + D_op_br| + D_op_rsv02; + + assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_force_xor <= 0; + else if (R_en) + R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; + end + + + //data_master, which is an e_avalon_master + //instruction_master, which is an e_avalon_master + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign F_inst = (F_op_call)? 56'h20202063616c6c : + (F_op_jmpi)? 56'h2020206a6d7069 : + (F_op_ldbu)? 56'h2020206c646275 : + (F_op_addi)? 56'h20202061646469 : + (F_op_stb)? 56'h20202020737462 : + (F_op_br)? 56'h20202020206272 : + (F_op_ldb)? 56'h202020206c6462 : + (F_op_cmpgei)? 56'h20636d70676569 : + (F_op_ldhu)? 56'h2020206c646875 : + (F_op_andi)? 56'h202020616e6469 : + (F_op_sth)? 56'h20202020737468 : + (F_op_bge)? 56'h20202020626765 : + (F_op_ldh)? 56'h202020206c6468 : + (F_op_cmplti)? 56'h20636d706c7469 : + (F_op_initda)? 56'h20696e69746461 : + (F_op_ori)? 56'h202020206f7269 : + (F_op_stw)? 56'h20202020737477 : + (F_op_blt)? 56'h20202020626c74 : + (F_op_ldw)? 56'h202020206c6477 : + (F_op_cmpnei)? 56'h20636d706e6569 : + (F_op_flushda)? 56'h666c7573686461 : + (F_op_xori)? 56'h202020786f7269 : + (F_op_bne)? 56'h20202020626e65 : + (F_op_cmpeqi)? 56'h20636d70657169 : + (F_op_ldbuio)? 56'h206c646275696f : + (F_op_muli)? 56'h2020206d756c69 : + (F_op_stbio)? 56'h2020737462696f : + (F_op_beq)? 56'h20202020626571 : + (F_op_ldbio)? 56'h20206c6462696f : + (F_op_cmpgeui)? 56'h636d7067657569 : + (F_op_ldhuio)? 56'h206c646875696f : + (F_op_andhi)? 56'h2020616e646869 : + (F_op_sthio)? 56'h2020737468696f : + (F_op_bgeu)? 56'h20202062676575 : + (F_op_ldhio)? 56'h20206c6468696f : + (F_op_cmpltui)? 56'h636d706c747569 : + (F_op_initd)? 56'h2020696e697464 : + (F_op_orhi)? 56'h2020206f726869 : + (F_op_stwio)? 56'h2020737477696f : + (F_op_bltu)? 56'h202020626c7475 : + (F_op_ldwio)? 56'h20206c6477696f : + (F_op_flushd)? 56'h20666c75736864 : + (F_op_xorhi)? 56'h2020786f726869 : + (F_op_eret)? 56'h20202065726574 : + (F_op_roli)? 56'h202020726f6c69 : + (F_op_rol)? 56'h20202020726f6c : + (F_op_flushp)? 56'h20666c75736870 : + (F_op_ret)? 56'h20202020726574 : + (F_op_nor)? 56'h202020206e6f72 : + (F_op_mulxuu)? 56'h206d756c787575 : + (F_op_cmpge)? 56'h2020636d706765 : + (F_op_bret)? 56'h20202062726574 : + (F_op_ror)? 56'h20202020726f72 : + (F_op_flushi)? 56'h20666c75736869 : + (F_op_jmp)? 56'h202020206a6d70 : + (F_op_and)? 56'h20202020616e64 : + (F_op_cmplt)? 56'h2020636d706c74 : + (F_op_slli)? 56'h202020736c6c69 : + (F_op_sll)? 56'h20202020736c6c : + (F_op_or)? 56'h20202020206f72 : + (F_op_mulxsu)? 56'h206d756c787375 : + (F_op_cmpne)? 56'h2020636d706e65 : + (F_op_srli)? 56'h20202073726c69 : + (F_op_srl)? 56'h2020202073726c : + (F_op_nextpc)? 56'h206e6578747063 : + (F_op_callr)? 56'h202063616c6c72 : + (F_op_xor)? 56'h20202020786f72 : + (F_op_mulxss)? 56'h206d756c787373 : + (F_op_cmpeq)? 56'h2020636d706571 : + (F_op_divu)? 56'h20202064697675 : + (F_op_div)? 56'h20202020646976 : + (F_op_rdctl)? 56'h2020726463746c : + (F_op_mul)? 56'h202020206d756c : + (F_op_cmpgeu)? 56'h20636d70676575 : + (F_op_initi)? 56'h2020696e697469 : + (F_op_trap)? 56'h20202074726170 : + (F_op_wrctl)? 56'h2020777263746c : + (F_op_cmpltu)? 56'h20636d706c7475 : + (F_op_add)? 56'h20202020616464 : + (F_op_break)? 56'h2020627265616b : + (F_op_sync)? 56'h20202073796e63 : + (F_op_sub)? 56'h20202020737562 : + (F_op_srai)? 56'h20202073726169 : + (F_op_sra)? 56'h20202020737261 : + (F_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign D_inst = (D_op_call)? 56'h20202063616c6c : + (D_op_jmpi)? 56'h2020206a6d7069 : + (D_op_ldbu)? 56'h2020206c646275 : + (D_op_addi)? 56'h20202061646469 : + (D_op_stb)? 56'h20202020737462 : + (D_op_br)? 56'h20202020206272 : + (D_op_ldb)? 56'h202020206c6462 : + (D_op_cmpgei)? 56'h20636d70676569 : + (D_op_ldhu)? 56'h2020206c646875 : + (D_op_andi)? 56'h202020616e6469 : + (D_op_sth)? 56'h20202020737468 : + (D_op_bge)? 56'h20202020626765 : + (D_op_ldh)? 56'h202020206c6468 : + (D_op_cmplti)? 56'h20636d706c7469 : + (D_op_initda)? 56'h20696e69746461 : + (D_op_ori)? 56'h202020206f7269 : + (D_op_stw)? 56'h20202020737477 : + (D_op_blt)? 56'h20202020626c74 : + (D_op_ldw)? 56'h202020206c6477 : + (D_op_cmpnei)? 56'h20636d706e6569 : + (D_op_flushda)? 56'h666c7573686461 : + (D_op_xori)? 56'h202020786f7269 : + (D_op_bne)? 56'h20202020626e65 : + (D_op_cmpeqi)? 56'h20636d70657169 : + (D_op_ldbuio)? 56'h206c646275696f : + (D_op_muli)? 56'h2020206d756c69 : + (D_op_stbio)? 56'h2020737462696f : + (D_op_beq)? 56'h20202020626571 : + (D_op_ldbio)? 56'h20206c6462696f : + (D_op_cmpgeui)? 56'h636d7067657569 : + (D_op_ldhuio)? 56'h206c646875696f : + (D_op_andhi)? 56'h2020616e646869 : + (D_op_sthio)? 56'h2020737468696f : + (D_op_bgeu)? 56'h20202062676575 : + (D_op_ldhio)? 56'h20206c6468696f : + (D_op_cmpltui)? 56'h636d706c747569 : + (D_op_initd)? 56'h2020696e697464 : + (D_op_orhi)? 56'h2020206f726869 : + (D_op_stwio)? 56'h2020737477696f : + (D_op_bltu)? 56'h202020626c7475 : + (D_op_ldwio)? 56'h20206c6477696f : + (D_op_flushd)? 56'h20666c75736864 : + (D_op_xorhi)? 56'h2020786f726869 : + (D_op_eret)? 56'h20202065726574 : + (D_op_roli)? 56'h202020726f6c69 : + (D_op_rol)? 56'h20202020726f6c : + (D_op_flushp)? 56'h20666c75736870 : + (D_op_ret)? 56'h20202020726574 : + (D_op_nor)? 56'h202020206e6f72 : + (D_op_mulxuu)? 56'h206d756c787575 : + (D_op_cmpge)? 56'h2020636d706765 : + (D_op_bret)? 56'h20202062726574 : + (D_op_ror)? 56'h20202020726f72 : + (D_op_flushi)? 56'h20666c75736869 : + (D_op_jmp)? 56'h202020206a6d70 : + (D_op_and)? 56'h20202020616e64 : + (D_op_cmplt)? 56'h2020636d706c74 : + (D_op_slli)? 56'h202020736c6c69 : + (D_op_sll)? 56'h20202020736c6c : + (D_op_or)? 56'h20202020206f72 : + (D_op_mulxsu)? 56'h206d756c787375 : + (D_op_cmpne)? 56'h2020636d706e65 : + (D_op_srli)? 56'h20202073726c69 : + (D_op_srl)? 56'h2020202073726c : + (D_op_nextpc)? 56'h206e6578747063 : + (D_op_callr)? 56'h202063616c6c72 : + (D_op_xor)? 56'h20202020786f72 : + (D_op_mulxss)? 56'h206d756c787373 : + (D_op_cmpeq)? 56'h2020636d706571 : + (D_op_divu)? 56'h20202064697675 : + (D_op_div)? 56'h20202020646976 : + (D_op_rdctl)? 56'h2020726463746c : + (D_op_mul)? 56'h202020206d756c : + (D_op_cmpgeu)? 56'h20636d70676575 : + (D_op_initi)? 56'h2020696e697469 : + (D_op_trap)? 56'h20202074726170 : + (D_op_wrctl)? 56'h2020777263746c : + (D_op_cmpltu)? 56'h20636d706c7475 : + (D_op_add)? 56'h20202020616464 : + (D_op_break)? 56'h2020627265616b : + (D_op_sync)? 56'h20202073796e63 : + (D_op_sub)? 56'h20202020737562 : + (D_op_srai)? 56'h20202073726169 : + (D_op_sra)? 56'h20202020737261 : + (D_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; + assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; + assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; + assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; + assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + diff --git a/ip/altera/ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v b/ip/altera/ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v new file mode 100644 index 0000000..6d76f47 --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v @@ -0,0 +1,718 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench ( + // inputs: + D_iw, + D_iw_op, + D_iw_opx, + D_valid, + E_alu_result, + E_mem_byte_en, + E_st_data, + E_valid, + F_pcb, + F_valid, + R_ctrl_exception, + R_ctrl_ld, + R_ctrl_ld_non_io, + R_dst_regnum, + R_wr_dst_reg, + W_bstatus_reg, + W_cmp_result, + W_estatus_reg, + W_ienable_reg, + W_ipending_reg, + W_mem_baddr, + W_rf_wr_data, + W_status_reg, + W_valid, + W_vinst, + W_wr_data, + av_ld_data_aligned_unfiltered, + clk, + d_address, + d_byteenable, + d_read, + d_write_nxt, + i_address, + i_read, + i_readdata, + i_waitrequest, + reset_n, + + // outputs: + av_ld_data_aligned_filtered, + d_write, + test_has_ended + ) +; + + output [ 31: 0] av_ld_data_aligned_filtered; + output d_write; + output test_has_ended; + input [ 31: 0] D_iw; + input [ 5: 0] D_iw_op; + input [ 5: 0] D_iw_opx; + input D_valid; + input [ 31: 0] E_alu_result; + input [ 3: 0] E_mem_byte_en; + input [ 31: 0] E_st_data; + input E_valid; + input [ 16: 0] F_pcb; + input F_valid; + input R_ctrl_exception; + input R_ctrl_ld; + input R_ctrl_ld_non_io; + input [ 4: 0] R_dst_regnum; + input R_wr_dst_reg; + input W_bstatus_reg; + input W_cmp_result; + input W_estatus_reg; + input [ 31: 0] W_ienable_reg; + input [ 31: 0] W_ipending_reg; + input [ 19: 0] W_mem_baddr; + input [ 31: 0] W_rf_wr_data; + input W_status_reg; + input W_valid; + input [ 55: 0] W_vinst; + input [ 31: 0] W_wr_data; + input [ 31: 0] av_ld_data_aligned_unfiltered; + input clk; + input [ 19: 0] d_address; + input [ 3: 0] d_byteenable; + input d_read; + input d_write_nxt; + input [ 16: 0] i_address; + input i_read; + input [ 31: 0] i_readdata; + input i_waitrequest; + input reset_n; + + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire av_ld_data_aligned_unfiltered_0_is_x; + wire av_ld_data_aligned_unfiltered_10_is_x; + wire av_ld_data_aligned_unfiltered_11_is_x; + wire av_ld_data_aligned_unfiltered_12_is_x; + wire av_ld_data_aligned_unfiltered_13_is_x; + wire av_ld_data_aligned_unfiltered_14_is_x; + wire av_ld_data_aligned_unfiltered_15_is_x; + wire av_ld_data_aligned_unfiltered_16_is_x; + wire av_ld_data_aligned_unfiltered_17_is_x; + wire av_ld_data_aligned_unfiltered_18_is_x; + wire av_ld_data_aligned_unfiltered_19_is_x; + wire av_ld_data_aligned_unfiltered_1_is_x; + wire av_ld_data_aligned_unfiltered_20_is_x; + wire av_ld_data_aligned_unfiltered_21_is_x; + wire av_ld_data_aligned_unfiltered_22_is_x; + wire av_ld_data_aligned_unfiltered_23_is_x; + wire av_ld_data_aligned_unfiltered_24_is_x; + wire av_ld_data_aligned_unfiltered_25_is_x; + wire av_ld_data_aligned_unfiltered_26_is_x; + wire av_ld_data_aligned_unfiltered_27_is_x; + wire av_ld_data_aligned_unfiltered_28_is_x; + wire av_ld_data_aligned_unfiltered_29_is_x; + wire av_ld_data_aligned_unfiltered_2_is_x; + wire av_ld_data_aligned_unfiltered_30_is_x; + wire av_ld_data_aligned_unfiltered_31_is_x; + wire av_ld_data_aligned_unfiltered_3_is_x; + wire av_ld_data_aligned_unfiltered_4_is_x; + wire av_ld_data_aligned_unfiltered_5_is_x; + wire av_ld_data_aligned_unfiltered_6_is_x; + wire av_ld_data_aligned_unfiltered_7_is_x; + wire av_ld_data_aligned_unfiltered_8_is_x; + wire av_ld_data_aligned_unfiltered_9_is_x; + reg d_write; + wire test_has_ended; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_write <= 0; + else + d_write <= d_write_nxt; + end + + + assign test_has_ended = 1'b0; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //Clearing 'X' data bits + assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; + + assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; + assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; + assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; + assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; + assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; + assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; + assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; + assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; + assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; + assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; + assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; + assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; + assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; + assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; + assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; + assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; + assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; + assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; + assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; + assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; + assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; + assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; + assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; + assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; + assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; + assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; + assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; + assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; + assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; + assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; + assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; + assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; + assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; + assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; + assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; + assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; + assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; + assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; + assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; + assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; + assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; + assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; + assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; + assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; + assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; + assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; + assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; + assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; + assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; + assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; + assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; + assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; + assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; + assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; + assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; + assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; + assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; + assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; + assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; + assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; + assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; + assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; + assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; + always @(posedge clk) + begin + if (reset_n) + if (^(F_valid) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/F_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(D_valid) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/D_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(E_valid) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/E_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(W_valid) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid) + if (^(R_wr_dst_reg) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(R_dst_regnum) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_write) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_write is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write) + if (^(d_byteenable) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_byteenable is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write | d_read) + if (^(d_address) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_read) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(i_read) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read) + if (^(i_address) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read & ~i_waitrequest) + if (^(i_readdata) === 1'bx) + begin + $write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_readdata is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_ctrl_ld) + if (^(av_ld_data_aligned_unfiltered) === 1'bx) + begin + $write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time); + end + end + + + + reg [31:0] trace_handle; // for $fopen + initial + begin + trace_handle = $fopen("altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.tr"); + $fwrite(trace_handle, "version 3\nnumThreads 1\n"); + end + always @(posedge clk) + begin + if ((~reset_n || (W_valid)) && ~test_has_ended) + $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0); + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// +// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/ip/altera/ddr3/altera_mem_if_sequencer_mem_no_ifdef_params.sv b/ip/altera/ddr3/altera_mem_if_sequencer_mem_no_ifdef_params.sv new file mode 100644 index 0000000..ef73122 --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_sequencer_mem_no_ifdef_params.sv @@ -0,0 +1,99 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module altera_mem_if_sequencer_mem_no_ifdef_params ( + clk1, + reset1, + clken1, + s1_address, + s1_be, + s1_chipselect, + s1_write, + s1_writedata, + s1_readdata +); + +parameter AVL_ADDR_WIDTH = 0; +parameter AVL_DATA_WIDTH = 0; +parameter AVL_SYMBOL_WIDTH = 0; +parameter AVL_NUM_SYMBOLS = 0; +parameter MEM_SIZE = 0; +parameter INIT_FILE = ""; +parameter RAM_BLOCK_TYPE = ""; + +localparam NUM_WORDS = MEM_SIZE / AVL_NUM_SYMBOLS; + +input clk1; +input reset1; +input clken1; +input [AVL_ADDR_WIDTH - 1:0] s1_address; +input [AVL_NUM_SYMBOLS - 1:0] s1_be; +input s1_chipselect; +input s1_write; +input [AVL_DATA_WIDTH - 1:0] s1_writedata; +output [AVL_DATA_WIDTH - 1:0] s1_readdata; + +wire wren; +assign wren = s1_chipselect & s1_write; + + altsyncram the_altsyncram + ( + .address_a (s1_address), + .byteena_a (s1_be), + .clock0 (clk1), + .clocken0 (clken1), + .data_a (s1_writedata), + .q_a (s1_readdata), + .wren_a (wren), + .rden_a(), + .rden_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .eccstatus(), + .address_b (), + .byteena_b (), + .clock1 (), + .clocken1 (), + .data_b (), + .q_b (), + .wren_b () + ); + defparam the_altsyncram.byte_size = AVL_SYMBOL_WIDTH; + defparam the_altsyncram.lpm_type = "altsyncram"; + defparam the_altsyncram.maximum_depth = NUM_WORDS; + defparam the_altsyncram.numwords_a = NUM_WORDS; + defparam the_altsyncram.outdata_reg_a = "UNREGISTERED"; + defparam the_altsyncram.ram_block_type = RAM_BLOCK_TYPE; + defparam the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE"; + defparam the_altsyncram.width_a = AVL_DATA_WIDTH; + defparam the_altsyncram.width_byteena_a = AVL_NUM_SYMBOLS; + defparam the_altsyncram.widthad_a = AVL_ADDR_WIDTH; + defparam the_altsyncram.init_file = INIT_FILE; + defparam the_altsyncram.operation_mode = "SINGLE_PORT"; + + +endmodule + diff --git a/ip/altera/ddr3/altera_mem_if_sequencer_rst.sv b/ip/altera/ddr3/altera_mem_if_sequencer_rst.sv new file mode 100644 index 0000000..ff51e00 --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_sequencer_rst.sv @@ -0,0 +1,117 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module altera_mem_if_sequencer_rst +( + clk, + rst, + clken_out, + reset_out +); + timeunit 1ns; + timeprecision 1ps; + + parameter DEPTH = 2; + parameter CLKEN_LAGS_RESET = 0; + + localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; + + input clk; + input rst; + output clken_out; + output reset_out; + + (*preserve*) reg [2: 0] altera_reset_synchronizer_int_chain; + + wire w_sync_rst_input; + reg [(DEPTH-1): 0] r_sync_rst_chain; + + reg r_sync_rst_dly; + reg r_sync_rst; + reg r_early_rst; + + assign w_sync_rst_input = altera_reset_synchronizer_int_chain[2]; + + + + assign clken_out =~r_early_rst; + assign reset_out = r_sync_rst; + + + +initial +begin + altera_reset_synchronizer_int_chain <= '1; +end + +always @(posedge clk) +begin + altera_reset_synchronizer_int_chain[2:0] + <= {altera_reset_synchronizer_int_chain[1:0], ~rst}; +end + + +initial +begin + r_sync_rst_chain <= {DEPTH{1'b1}}; +end + +always @(posedge clk) +begin + if (w_sync_rst_input == 1'b1) + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; + end +end + +initial +begin + r_sync_rst_dly <= 1'b1; + r_sync_rst <= 1'b1; + r_early_rst <= 1'b1; +end +always @(posedge clk) +begin + r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; + + case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) + 2'b00: r_early_rst <= 1'b0; + 2'b01: r_early_rst <= 1'b1; + 2'b10: r_early_rst <= 1'b0; + 2'b11: r_early_rst <= 1'b1; + default: r_early_rst <= 1'b1; + endcase +end + +endmodule + diff --git a/ip/altera/ddr3/altera_mem_if_simple_avalon_mm_bridge.sv b/ip/altera/ddr3/altera_mem_if_simple_avalon_mm_bridge.sv new file mode 100644 index 0000000..c3cdb16 --- /dev/null +++ b/ip/altera/ddr3/altera_mem_if_simple_avalon_mm_bridge.sv @@ -0,0 +1,122 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + +`timescale 1ps/1ps + +module altera_mem_if_simple_avalon_mm_bridge ( + clk, + reset_n, + s0_address, + s0_read, + s0_readdata, + s0_write, + s0_writedata, + s0_waitrequest, + s0_waitrequest_n, + s0_byteenable, + s0_beginbursttransfer, + s0_burstcount, + s0_readdatavalid, + m0_address, + m0_read, + m0_readdata, + m0_write, + m0_writedata, + m0_waitrequest, + m0_byteenable, + m0_beginbursttransfer, + m0_burstcount, + m0_readdatavalid +); + + parameter DATA_WIDTH = 32; + parameter MASTER_DATA_WIDTH = 32; + parameter SLAVE_DATA_WIDTH = 32; + parameter SYMBOL_WIDTH = 8; + parameter ADDRESS_WIDTH = 10; + parameter BURSTCOUNT_WIDTH = 1; + parameter MASTER_ADDRESS_WIDTH = 10; + parameter SLAVE_ADDRESS_WIDTH = 10; + parameter WORKAROUND_HARD_PHY_ISSUE = 0; + + localparam USE_DIFFERENT_MASTER_SLAVE_ADDR = (MASTER_ADDRESS_WIDTH != SLAVE_ADDRESS_WIDTH ? 1 : 0); + localparam S0_ADDR_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_ADDR ? SLAVE_ADDRESS_WIDTH : ADDRESS_WIDTH); + localparam M0_ADDR_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_ADDR ? MASTER_ADDRESS_WIDTH : ADDRESS_WIDTH); + localparam USE_DIFFERENT_MASTER_SLAVE_DATA = (MASTER_DATA_WIDTH != SLAVE_DATA_WIDTH ? 1 : 0); + localparam S0_DATA_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_DATA ? SLAVE_DATA_WIDTH : DATA_WIDTH); + localparam M0_DATA_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_DATA ? MASTER_DATA_WIDTH : DATA_WIDTH); + localparam S0_BYTEEN_WIDTH = S0_DATA_WIDTH / SYMBOL_WIDTH; + localparam M0_BYTEEN_WIDTH = M0_DATA_WIDTH / SYMBOL_WIDTH; + + input clk; + input reset_n; + + input [S0_ADDR_WIDTH-1:0] s0_address; + input s0_read; + output [S0_DATA_WIDTH-1:0] s0_readdata; + input s0_write; + input [S0_DATA_WIDTH-1:0] s0_writedata; + output s0_waitrequest; + output s0_waitrequest_n; + input [S0_BYTEEN_WIDTH-1:0] s0_byteenable; + output s0_readdatavalid; + input [BURSTCOUNT_WIDTH-1:0] s0_burstcount; + input s0_beginbursttransfer; + + output [M0_ADDR_WIDTH-1:0] m0_address; + output m0_read; + input [M0_DATA_WIDTH-1:0] m0_readdata; + output m0_write; + output [M0_DATA_WIDTH-1:0] m0_writedata; + input m0_waitrequest; + output [M0_BYTEEN_WIDTH-1:0] m0_byteenable; + input m0_readdatavalid; + output [BURSTCOUNT_WIDTH-1:0] m0_burstcount; + output m0_beginbursttransfer; + + generate + if (WORKAROUND_HARD_PHY_ISSUE) + begin + reg waitrequest_r = 0; + reg read_r = 0; + + always @(posedge clk) + begin + waitrequest_r <= s0_waitrequest; + read_r <= s0_read; + end + + assign m0_read = read_r & s0_read; + assign s0_waitrequest = m0_waitrequest | (s0_read & ~waitrequest_r); + assign s0_waitrequest_n = ~s0_waitrequest; + end + else + begin + assign m0_read = s0_read; + assign s0_waitrequest = m0_waitrequest; + assign s0_waitrequest_n = ~s0_waitrequest; + end + endgenerate + + assign m0_address = (M0_ADDR_WIDTH > S0_ADDR_WIDTH) ? { { (M0_ADDR_WIDTH - S0_ADDR_WIDTH) {1'b0} }, s0_address} : s0_address; + assign s0_readdata = m0_readdata; + assign m0_write = s0_write; + assign m0_writedata = s0_writedata; + assign m0_byteenable = s0_byteenable; + assign s0_readdatavalid = m0_readdatavalid; + assign m0_beginbursttransfer = s0_beginbursttransfer; + assign m0_burstcount = s0_burstcount; + +endmodule diff --git a/ip/altera/ddr3/altera_merlin_address_alignment.sv b/ip/altera/ddr3/altera_merlin_address_alignment.sv new file mode 100644 index 0000000..d9b3cb9 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_address_alignment.sv @@ -0,0 +1,263 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $ +// $Revision: #3 $ +// $Date: 2012/07/11 $ +// $Author: tgngo $ + +//----------------------------------------- +// Address alignment: +// This component will aglin input address with input size +// Support address increment with butst type and burstwrap value +//----------------------------------------- +`timescale 1 ns / 1 ns + +module altera_merlin_address_alignment +#( + parameter + ADDR_W = 12, + BURSTWRAP_W = 12, + TYPE_W = 2, + SIZE_W = 3, + INCREMENT_ADDRESS = 1, + NUMSYMBOLS = 8, + SELECT_BITS = log2(NUMSYMBOLS), + IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W, + OUT_DATA_W = ADDR_W + SELECT_BITS +) +( + input clk, + input reset, + + input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size} + input in_valid, + //output in_ready, + input in_sop, + input in_eop, + + output reg [OUT_DATA_W-1:0] out_data, + input out_ready + //output out_valid + +); +typedef enum bit [1:0] +{ + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + RESERVED = 2'b11 +} AxiBurstType; + //---------------------------------------------------- + // AXSIZE decoding + // + // Turns the axsize value into the actual number of bytes + // being transferred. + // --------------------------------------------------- + +function reg[9:0] bytes_in_transfer; + input [SIZE_W-1:0] axsize; + case (axsize) + 4'b0000: bytes_in_transfer = 10'b0000000001; + 4'b0001: bytes_in_transfer = 10'b0000000010; + 4'b0010: bytes_in_transfer = 10'b0000000100; + 4'b0011: bytes_in_transfer = 10'b0000001000; + 4'b0100: bytes_in_transfer = 10'b0000010000; + 4'b0101: bytes_in_transfer = 10'b0000100000; + 4'b0110: bytes_in_transfer = 10'b0001000000; + 4'b0111: bytes_in_transfer = 10'b0010000000; + 4'b1000: bytes_in_transfer = 10'b0100000000; + 4'b1001: bytes_in_transfer = 10'b1000000000; + default: bytes_in_transfer = 10'b0000000001; + endcase +endfunction + + //-------------------------------------- + // Burst type decode + //-------------------------------------- +AxiBurstType write_burst_type; + +function AxiBurstType burst_type_decode +( + input [1:0] axburst +); + AxiBurstType burst_type; + begin + case (axburst) + 2'b00 : burst_type = FIXED; + 2'b01 : burst_type = INCR; + 2'b10 : burst_type = WRAP; + 2'b11 : burst_type = RESERVED; + default : burst_type = INCR; + endcase + return burst_type; + end +endfunction + + //---------------------------------------------------- + // Ubiquitous, familiar log2 function + //---------------------------------------------------- +function integer log2; + input integer value; + + value = value - 1; + for(log2 = 0; value > 0; log2 = log2 + 1) + value = value >> 1; + +endfunction + //------------------------------------------------------------------------ + // This component will read address and size and check + // if this is aligned or not. If not then it will align this address to the size + // of the transfer: + // Check alignment: + // - With data width, can define maximun how many lower bits of address to indicate this + // address align to the size + // - Ex: 32 bits data => size can be: 1, 2, 4 bytes + // For 4 bytes: when 2 lower bits of address equal 0, this is aligned address + // addr=00|00| (0), 01|00| (4) => align to size of 4 bytes + // addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte + // For 2 bytes: use last one bit to indicate algined or not + // addr=000|0| (0), 001|0| (2) => align to size of 2 bytes + // addr=000|1| (1), 001|1| (3) => not align to 2 bytes + // As size runtime change, creat mask and change accordingly to size, can detect address alignment + // and to align to size, apply this mask with zero to the address. + //------------------------------------------------------------------------- + + // THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0] + // in which the first part contains the mask to check if this address aligned or not + // second part contains the mast to mask address to align to size + + function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address; + input [ADDR_W-1:0] address; + input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes + + integer i; + reg [SELECT_BITS-1:0] mask_address; + reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte) + mask_address = '1; + check_unaligned = '0; + for(i = 0; i < SELECT_BITS ; i = i + 1) begin + if (i < size) begin + check_unaligned[i] = address[i]; + mask_address[i] = 1'b0; + end + end + mask_select_and_align_address = {check_unaligned,mask_address}; + endfunction + + + + reg [ADDR_W-1 : 0] in_address; + reg [ADDR_W-1 : 0] first_address_aligned; + reg [SIZE_W-1 : 0] in_size; + reg [(SELECT_BITS*2)-1 : 0] output_masks; + // Extract information from input data + assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W]; + assign in_size = in_data[SIZE_W-1 : 0]; + + // Generate the masks + always_comb + begin + output_masks = mask_select_and_align_address(in_address, in_size); + end + + // Align address if needed + + generate + // SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned + if (SELECT_BITS == 0) + assign first_address_aligned = in_address; + else begin + // SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS) + wire [SELECT_BITS-1 : 0] aligned_address_bits; + if (SELECT_BITS == 1) + assign aligned_address_bits = in_address[0] & output_masks[0]; + else + assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0]; + assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits}; + end + endgenerate + + + + // Increment address base on size, first address keep the same + generate + if (INCREMENT_ADDRESS) + begin + reg [ADDR_W-1 : 0] increment_address; + reg [ADDR_W-1 : 0] out_aligned_address_burst; + reg [ADDR_W-1 : 0] address_burst; + reg [ADDR_W-1 : 0] base_address; + reg [9 : 0] number_bytes_transfer; + reg [ADDR_W-1 : 0] burstwrap_mask; + reg [ADDR_W-1 : 0] burst_address_high; + reg [ADDR_W-1 : 0] burst_address_low; + reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary; + reg [TYPE_W-1 : 0] in_type; + //------------------------------------------------ + // Use the extended burstwrap value to split the high (constant) and + // low (changing) part of the address + //----------------------------------------------- + assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W]; + assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W]; + assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary}; + assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask; + assign burst_address_low = out_aligned_address_burst; + assign number_bytes_transfer = bytes_in_transfer(in_size); + assign write_burst_type = burst_type_decode(in_type); + + always @* + begin + if (in_sop) + begin + out_aligned_address_burst = in_address; + base_address = first_address_aligned; + end + else + begin + out_aligned_address_burst = address_burst; + base_address = out_aligned_address_burst; + end + case (write_burst_type) + INCR: + increment_address = base_address + number_bytes_transfer; + WRAP: + increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high; + FIXED: + increment_address = out_aligned_address_burst; + default: + increment_address = base_address + number_bytes_transfer; + endcase // case (write_burst_type) + end // always @ * + always_ff @(posedge clk, negedge reset) + begin + if (!reset) + begin + address_burst <= '0; + end + else + begin + if (in_valid & out_ready) + address_burst <= increment_address; + end + end + // send data to output with 2 part: [mask_t0_algin][address_aligned_increment] + assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst}; + end // if (INCREMENT_ADDRESS) + else + begin + assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned}; + end // else: !if(INCREMENT_ADDRESS) + + endgenerate +endmodule diff --git a/ip/altera/ddr3/altera_merlin_arbitrator.sv b/ip/altera/ddr3/altera_merlin_arbitrator.sv new file mode 100644 index 0000000..fe1ce03 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_arbitrator.sv @@ -0,0 +1,272 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2010 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ +// $Revision: #3 $ +// $Date: 2010/07/07 $ +// $Author: jyeap $ + +/* ----------------------------------------------------------------------- +Round-robin/fixed arbitration implementation. + +Q: how do you find the least-significant set-bit in an n-bit binary number, X? + +A: M = X & (~X + 1) + +Example: X = 101000100 + 101000100 & + 010111011 + 1 = + + 101000100 & + 010111100 = + ----------- + 000000100 + +The method can be generalized to find the first set-bit +at a bit index no lower than bit-index N, simply by adding +2**N rather than 1. + + +Q: how does this relate to round-robin arbitration? +A: +Let X be the concatenation of all request signals. +Let the number to be added to X (hereafter called the +top_priority) initialize to 1, and be assigned from the +concatenation of the previous saved-grant, left-rotated +by one position, each time arbitration occurs. The +concatenation of grants is then M. + +Problem: consider this case: + +top_priority = 010000 +request = 001001 +~request + top_priority = 000110 +next_grant = 000000 <- no one is granted! + +There was no "set bit at a bit index no lower than bit-index 4", so +the result was 0. + +We need to propagate the carry out from (~request + top_priority) to the LSB, so +that the sum becomes 000111, and next_grant is 000001. This operation could be +called a "circular add". + +A bit of experimentation on the circular add reveals a significant amount of +delay in exiting and re-entering the carry chain - this will vary with device +family. Quartus also reports a combinational loop warning. Finally, +Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But +Modelsim _doesn't_ report a combinational loop!) + +An alternate solution: concatenate the request vector with itself, and OR +corresponding bits from the top and bottom halves to determine next_grant. + +Example: + +top_priority = 010000 +{request, request} = 001001 001001 +{~request, ~request} + top_priority = 110111 000110 +result of & operation = 000001 000000 +next_grant = 000001 + +Notice that if request = 0, the sum operation will overflow, but we can ignore +this; the next_grant result is 0 (no one granted), as you might expect. +In the implementation, the last-granted value must be maintained as +a non-zero value - best probably simply not to update it when no requests +occur. + +----------------------------------------------------------------------- */ + +`timescale 1 ns / 1 ns + +module altera_merlin_arbitrator +#( + parameter NUM_REQUESTERS = 8, + // -------------------------------------- + // Implemented schemes + // "round-robin" + // "fixed-priority" + // "no-arb" + // -------------------------------------- + parameter SCHEME = "round-robin", + parameter PIPELINE = 0 +) +( + input clk, + input reset, + + // -------------------------------------- + // Requests + // -------------------------------------- + input [NUM_REQUESTERS-1:0] request, + + // -------------------------------------- + // Grants + // -------------------------------------- + output [NUM_REQUESTERS-1:0] grant, + + // -------------------------------------- + // Control Signals + // -------------------------------------- + input increment_top_priority, + input save_top_priority +); + + // -------------------------------------- + // Signals + // -------------------------------------- + wire [NUM_REQUESTERS-1:0] top_priority; + reg [NUM_REQUESTERS-1:0] top_priority_reg; + reg [NUM_REQUESTERS-1:0] last_grant; + wire [2*NUM_REQUESTERS-1:0] result; + + // -------------------------------------- + // Scheme Selection + // -------------------------------------- + generate + if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin + assign top_priority = top_priority_reg; + end + else begin + // Fixed arbitration (or single-requester corner case) + assign top_priority = 1'b1; + end + endgenerate + + // -------------------------------------- + // Decision Logic + // -------------------------------------- + altera_merlin_arb_adder + #( + .WIDTH (2 * NUM_REQUESTERS) + ) + adder + ( + .a ({ ~request, ~request }), + .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), + .sum (result) + ); + + + generate if (SCHEME == "no-arb") begin + + // -------------------------------------- + // No arbitration: just wire request directly to grant + // -------------------------------------- + assign grant = request; + + end else begin + // Do the math in double-vector domain + wire [2*NUM_REQUESTERS-1:0] grant_double_vector; + assign grant_double_vector = {request, request} & result; + + // -------------------------------------- + // Extract grant from the top and bottom halves + // of the double vector. + // -------------------------------------- + assign grant = + grant_double_vector[NUM_REQUESTERS - 1 : 0] | + grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; + + end + endgenerate + + // -------------------------------------- + // Left-rotate the last grant vector to create top_priority. + // -------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + top_priority_reg <= 1'b1; + end + else begin + if (PIPELINE) begin + if (increment_top_priority) begin + top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1]} : top_priority_reg; + end + end else begin + if (increment_top_priority) begin + if (|request) + top_priority_reg <= { grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1] }; + else + top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; + end + else if (save_top_priority) begin + top_priority_reg <= grant; + end + end + end + end + +endmodule + +// ---------------------------------------------- +// Adder for the standard arbitrator +// ---------------------------------------------- +module altera_merlin_arb_adder +#( + parameter WIDTH = 8 +) +( + input [WIDTH-1:0] a, + input [WIDTH-1:0] b, + + output [WIDTH-1:0] sum +); + + wire [WIDTH:0] sum_lint; + // ---------------------------------------------- + // Benchmarks indicate that for small widths, the full + // adder has higher fmax because synthesis can merge + // it with the mux, allowing partial decisions to be + // made early. + // + // The magic number is 4 requesters, which means an + // 8 bit adder. + // ---------------------------------------------- + genvar i; + generate if (WIDTH <= 8) begin : full_adder + + wire cout[WIDTH-1:0]; + + assign sum[0] = (a[0] ^ b[0]); + assign cout[0] = (a[0] & b[0]); + + for (i = 1; i < WIDTH; i = i+1) begin : arb + + assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; + assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); + + end + + end else begin : carry_chain + + assign sum_lint = a + b; + assign sum = sum_lint[WIDTH-1:0]; + + end + endgenerate + +endmodule diff --git a/ip/altera/ddr3/altera_merlin_burst_adapter.sv b/ip/altera/ddr3/altera_merlin_burst_adapter.sv new file mode 100644 index 0000000..921d50f --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_burst_adapter.sv @@ -0,0 +1,261 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ns / 1 ns + +// ----------------------------------------------------- +// Top level for the burst adapter. This selects the +// implementation for the adapter, based on the +// parameterization. +// ----------------------------------------------------- +module altera_merlin_burst_adapter +#( + parameter + // Indicates the implementation to instantiate: + // "13.1" means the slow, inexpensive generic burst converter. + // "new" means the fast, expensive per-burst converter. + ADAPTER_VERSION = "13.1", + + // Indicates if this adapter needs to support read bursts + // (almost always true). + COMPRESSED_READ_SUPPORT = 1, + + // Standard Merlin packet parameters that indicate + // field position within the packet + PKT_BEGIN_BURST = 81, + PKT_ADDR_H = 79, + PKT_ADDR_L = 48, + PKT_BYTE_CNT_H = 5, + PKT_BYTE_CNT_L = 0, + PKT_BURSTWRAP_H = 11, + PKT_BURSTWRAP_L = 6, + PKT_TRANS_COMPRESSED_READ = 14, + PKT_TRANS_WRITE = 13, + PKT_TRANS_READ = 12, + PKT_BYTEEN_H = 83, + PKT_BYTEEN_L = 80, + PKT_BURST_TYPE_H = 88, + PKT_BURST_TYPE_L = 87, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + ST_DATA_W = 89, + ST_CHANNEL_W = 8, + + // Component-specific parameters. Explained + // in the implementation levels + IN_NARROW_SIZE = 0, + NO_WRAP_SUPPORT = 0, + INCOMPLETE_WRAP_SUPPORT = 1, + BURSTWRAP_CONST_MASK = 0, + BURSTWRAP_CONST_VALUE = -1, + + OUT_NARROW_SIZE = 0, + OUT_FIXED = 0, + OUT_COMPLETE_WRAP = 0, + BYTEENABLE_SYNTHESIS = 0, + PIPE_INPUTS = 0, + + OUT_BYTE_CNT_H = 5, + OUT_BURSTWRAP_H = 11 +) +( + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink0_valid, + input [ST_DATA_W-1 : 0] sink0_data, + input [ST_CHANNEL_W-1 : 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output reg sink0_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output wire source0_valid, + output wire [ST_DATA_W-1 : 0] source0_data, + output wire [ST_CHANNEL_W-1 : 0] source0_channel, + output wire source0_startofpacket, + output wire source0_endofpacket, + input source0_ready +); + + localparam PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + + generate if (COMPRESSED_READ_SUPPORT == 0) begin : altera_merlin_burst_adapter_uncompressed_only + + // ------------------------------------------------------------------- + // The reduced version of the adapter is only meant to be used on + // non-bursting wide to narrow links. + // ------------------------------------------------------------------- + altera_merlin_burst_adapter_uncompressed_only #( + .PKT_BYTE_CNT_H (PKT_BYTE_CNT_H), + .PKT_BYTE_CNT_L (PKT_BYTE_CNT_L), + .PKT_BYTEEN_H (PKT_BYTEEN_H), + .PKT_BYTEEN_L (PKT_BYTEEN_L), + .ST_DATA_W (ST_DATA_W), + .ST_CHANNEL_W (ST_CHANNEL_W) + ) burst_adapter ( + .clk (clk), + .reset (reset), + .sink0_valid (sink0_valid), + .sink0_data (sink0_data), + .sink0_channel (sink0_channel), + .sink0_startofpacket (sink0_startofpacket), + .sink0_endofpacket (sink0_endofpacket), + .sink0_ready (sink0_ready), + .source0_valid (source0_valid), + .source0_data (source0_data), + .source0_channel (source0_channel), + .source0_startofpacket (source0_startofpacket), + .source0_endofpacket (source0_endofpacket), + .source0_ready (source0_ready) + ); + + end + else if (ADAPTER_VERSION == "13.1") begin : altera_merlin_burst_adapter_13_1 + + // ----------------------------------------------------- + // This is the generic converter implementation, which attempts + // to convert all burst types with a generalized conversion + // function. This results in low area, but low fmax. + // ----------------------------------------------------- + altera_merlin_burst_adapter_13_1 #( + .PKT_BEGIN_BURST (PKT_BEGIN_BURST), + .PKT_ADDR_H (PKT_ADDR_H ), + .PKT_ADDR_L (PKT_ADDR_L), + .PKT_BYTE_CNT_H (PKT_BYTE_CNT_H), + .PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ), + .PKT_BURSTWRAP_H (PKT_BURSTWRAP_H), + .PKT_BURSTWRAP_L (PKT_BURSTWRAP_L), + .PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ), + .PKT_TRANS_WRITE (PKT_TRANS_WRITE), + .PKT_TRANS_READ (PKT_TRANS_READ), + .PKT_BYTEEN_H (PKT_BYTEEN_H), + .PKT_BYTEEN_L (PKT_BYTEEN_L), + .PKT_BURST_TYPE_H (PKT_BURST_TYPE_H), + .PKT_BURST_TYPE_L (PKT_BURST_TYPE_L), + .PKT_BURST_SIZE_H (PKT_BURST_SIZE_H), + .PKT_BURST_SIZE_L (PKT_BURST_SIZE_L), + .IN_NARROW_SIZE (IN_NARROW_SIZE), + .BYTEENABLE_SYNTHESIS (BYTEENABLE_SYNTHESIS), + .OUT_NARROW_SIZE (OUT_NARROW_SIZE), + .OUT_FIXED (OUT_FIXED), + .OUT_COMPLETE_WRAP (OUT_COMPLETE_WRAP), + .ST_DATA_W (ST_DATA_W), + .ST_CHANNEL_W (ST_CHANNEL_W), + .BURSTWRAP_CONST_MASK (BURSTWRAP_CONST_MASK), + .BURSTWRAP_CONST_VALUE (BURSTWRAP_CONST_VALUE), + .PIPE_INPUTS (PIPE_INPUTS), + .NO_WRAP_SUPPORT (NO_WRAP_SUPPORT), + .OUT_BYTE_CNT_H (OUT_BYTE_CNT_H), + .OUT_BURSTWRAP_H (OUT_BURSTWRAP_H) + ) burst_adapter ( + .clk (clk), + .reset (reset), + .sink0_valid (sink0_valid), + .sink0_data (sink0_data), + .sink0_channel (sink0_channel), + .sink0_startofpacket (sink0_startofpacket), + .sink0_endofpacket (sink0_endofpacket), + .sink0_ready (sink0_ready), + .source0_valid (source0_valid), + .source0_data (source0_data), + .source0_channel (source0_channel), + .source0_startofpacket (source0_startofpacket), + .source0_endofpacket (source0_endofpacket), + .source0_ready (source0_ready) + ); + + end + else begin : altera_merlin_burst_adapter_new + + // ----------------------------------------------------- + // This is the per-burst-type converter implementation. This attempts + // to convert bursts with specialized functions for each burst + // type. This typically results in higher area, but higher fmax. + // ----------------------------------------------------- + altera_merlin_burst_adapter_new #( + .PKT_BEGIN_BURST (PKT_BEGIN_BURST), + .PKT_ADDR_H (PKT_ADDR_H ), + .PKT_ADDR_L (PKT_ADDR_L), + .PKT_BYTE_CNT_H (PKT_BYTE_CNT_H), + .PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ), + .PKT_BURSTWRAP_H (PKT_BURSTWRAP_H), + .PKT_BURSTWRAP_L (PKT_BURSTWRAP_L), + .PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ), + .PKT_TRANS_WRITE (PKT_TRANS_WRITE), + .PKT_TRANS_READ (PKT_TRANS_READ), + .PKT_BYTEEN_H (PKT_BYTEEN_H), + .PKT_BYTEEN_L (PKT_BYTEEN_L), + .PKT_BURST_TYPE_H (PKT_BURST_TYPE_H), + .PKT_BURST_TYPE_L (PKT_BURST_TYPE_L), + .PKT_BURST_SIZE_H (PKT_BURST_SIZE_H), + .PKT_BURST_SIZE_L (PKT_BURST_SIZE_L), + .IN_NARROW_SIZE (IN_NARROW_SIZE), + .BYTEENABLE_SYNTHESIS (BYTEENABLE_SYNTHESIS), + .OUT_NARROW_SIZE (OUT_NARROW_SIZE), + .OUT_FIXED (OUT_FIXED), + .OUT_COMPLETE_WRAP (OUT_COMPLETE_WRAP), + .ST_DATA_W (ST_DATA_W), + .ST_CHANNEL_W (ST_CHANNEL_W), + .BURSTWRAP_CONST_MASK (BURSTWRAP_CONST_MASK), + .BURSTWRAP_CONST_VALUE (BURSTWRAP_CONST_VALUE), + .PIPE_INPUTS (PIPE_INPUTS), + .NO_WRAP_SUPPORT (NO_WRAP_SUPPORT), + .INCOMPLETE_WRAP_SUPPORT (INCOMPLETE_WRAP_SUPPORT), + .OUT_BYTE_CNT_H (OUT_BYTE_CNT_H), + .OUT_BURSTWRAP_H (OUT_BURSTWRAP_H) + ) burst_adapter ( + .clk (clk), + .reset (reset), + .sink0_valid (sink0_valid), + .sink0_data (sink0_data), + .sink0_channel (sink0_channel), + .sink0_startofpacket (sink0_startofpacket), + .sink0_endofpacket (sink0_endofpacket), + .sink0_ready (sink0_ready), + .source0_valid (source0_valid), + .source0_data (source0_data), + .source0_channel (source0_channel), + .source0_startofpacket (source0_startofpacket), + .source0_endofpacket (source0_endofpacket), + .source0_ready (source0_ready) + ); + + end + endgenerate + + // synthesis translate_off + + // ----------------------------------------------------- + // Simulation-only check for incoming burstwrap values inconsistent with + // BURSTWRAP_CONST_MASK, which would indicate a paramerization error. + // + // Should be turned into an assertion, really. + // ----------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (~reset && sink0_valid && + BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0] & + (BURSTWRAP_CONST_VALUE[PKT_BURSTWRAP_W - 1:0] ^ sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]) + ) begin + $display("%t: %m: Error: burstwrap value %X is inconsistent with BURSTWRAP_CONST_MASK value %X", $time(), sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L], BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0]); + end + end + + // synthesis translate_on + +endmodule diff --git a/ip/altera/ddr3/altera_merlin_burst_adapter_13_1.sv b/ip/altera/ddr3/altera_merlin_burst_adapter_13_1.sv new file mode 100644 index 0000000..20e64a9 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_burst_adapter_13_1.sv @@ -0,0 +1,1174 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter.sv#68 $ +// $Revision: #68 $ +// $Date: 2014/01/23 $ +// $Author: wkleong $ + +// ------------------------------------------------------- +// Merlin Burst Adapter +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +// + 1 +// By definition, burstwrap values are of the form 2^n - 1; adding 1 is a non-ripple operation. +module altera_merlin_burst_adapter_burstwrap_increment #(parameter WIDTH = 8) + ( + input [WIDTH - 1:0] mask, + output [WIDTH - 1:0] inc + ); + assign inc[0] = ~mask[0]; + + genvar i; + generate + for (i = 1; i < WIDTH; i = i+1) begin : burstwrap_increment_loop + assign inc[i] = mask[i - 1] & ~mask[i]; + end + endgenerate +endmodule + +module altera_merlin_burst_adapter_adder #(parameter WIDTH = 8) ( + input cin, + input [WIDTH-1 : 0] a, + input [WIDTH-1 : 0] b, + output [WIDTH-1 : 0] sum + ); + + genvar i; + + wire [WIDTH-1:0] carry; + assign sum[0] = a[0] ^ b[0] ^ cin; + assign carry[0] = a[0] & b[0] | a[0] & cin | b[0] & cin; + + generate + for (i = 1; i < WIDTH; i = i+1) begin : full_adder_loop + assign sum[i] = a[i] ^ b[i] ^ carry[i-1]; + assign carry[i] = a[i] & b[i] | a[i] & carry[i-1] | b[i] & carry[i-1]; + end + endgenerate +endmodule + +// a - b = a + ~b + 1 +module altera_merlin_burst_adapter_subtractor #(parameter WIDTH = 8) ( + input [WIDTH-1 : 0] a, + input [WIDTH-1 : 0] b, + output [WIDTH-1 : 0] diff + ); + + altera_merlin_burst_adapter_adder #(.WIDTH (WIDTH)) subtract ( + .cin (1'b1), + .a (a), + .b (~b), + .sum (diff) + ); +endmodule + +// Pipeline position: +// 0: register module inputs +// 1: register module output +// I would have expected that with register retiming/duplication turned on, the +// pipeline position parameter would have no effect. Not so, +// PIPELINE_POSITION=1 is significantly better than PIPELINE_POSITION=0. + +module altera_merlin_burst_adapter_min #(parameter PKT_BYTE_CNT_W=8, PKT_BURSTWRAP_W=8, PIPELINE_POSITION = 1) + ( + input clk, + input reset, + input [PKT_BYTE_CNT_W - 1 : 0] a, + input [PKT_BYTE_CNT_W - 1 : 0] b, + input [PKT_BURSTWRAP_W - 1 : 0] c, + input c_enable, + input [PKT_BYTE_CNT_W - 1 : 0] d, + output reg [PKT_BYTE_CNT_W - 1 : 0] result + ); + + wire [PKT_BYTE_CNT_W : 0] ab_diff; + wire [PKT_BYTE_CNT_W : 0] ac_diff; + wire [PKT_BYTE_CNT_W : 0] bc_diff; + wire a_lt_b; + wire a_lt_c; + wire b_lt_c; + + reg [PKT_BYTE_CNT_W - 1 : 0] a_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] b_reg; + reg [PKT_BURSTWRAP_W - 1 : 0] c_reg; + reg c_enable_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] d_reg; + + generate + if (PIPELINE_POSITION == 0) begin + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + a_reg <= '0; + b_reg <= '0; + c_reg <= '0; + c_enable_reg <= '0; + d_reg <= '0; + end + else begin + a_reg <= a; + b_reg <= b; + c_reg <= c; + c_enable_reg <= c_enable; + d_reg <= d; + end + end + end + else begin + always @* begin + a_reg = a; + b_reg = b; + c_reg = c; + c_enable_reg = c_enable; + d_reg = d; + end + end + endgenerate + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) ab_sub ( + .a ({1'b0, a_reg}), + .b ({1'b0, b_reg}), + .diff (ab_diff) + ); + assign a_lt_b = ab_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) ac_sub ( + .a ({1'b0, a_reg}), + .b ({{(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}), + .diff (ac_diff) + ); + assign a_lt_c = ac_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) bc_sub ( + .a ({1'b0, b_reg}), + .b ({ {(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}), + .diff (bc_diff) + ); + assign b_lt_c = bc_diff[PKT_BYTE_CNT_W]; + + // If d is greater than any of the values, it'll be greater than the min, + // certainly. If d is greater than the min, use d. Of course, ignore c if + // !c_enable. + + // Note: d is "number-of-symbols", of width PKT_BYTE_CNT_W. So, a constant, + // and a power of 2 (until we support non-power-of-2 symbols/interface + // here). + // wire use_d = (d > a) || (d > b) || ( (d > c) && c_enable); + // I think there's something clever I can do with masks, but my head hurts, + // so try something simpler. + // wire use_d = + // (&(~a[PKT_BYTE_CNT_W - 1:LOG2_NUMSYMBOLS])) || + // (&(~b[PKT_BYTE_CNT_W-1:LOG2_NUMSYMBOLS])) || + // ((&(~c[PKT_BURSTWRAP_W-1:LOG2_NUMSYMBOLS])) && c_enable + // ); + wire [PKT_BYTE_CNT_W : 0] da_diff; + wire [PKT_BYTE_CNT_W : 0] db_diff; + wire [PKT_BYTE_CNT_W : 0] dc_diff; + wire d_gt_a; + wire d_gt_b; + wire d_gt_c; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) da_sub ( + .a ({1'b0, d_reg}), + .b ({1'b0, a_reg}), + .diff (da_diff) + ); + assign d_gt_a = ~da_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) db_sub ( + .a ({1'b0, d_reg}), + .b ({1'b0, b_reg}), + .diff (db_diff) + ); + assign d_gt_b = ~db_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) dc_sub ( + .a ({1'b0, d_reg}), + .b ({ {(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}), + .diff (dc_diff) + ); + assign d_gt_c = ~(d_reg < c_reg); // kevtan mod ~dc_diff[PKT_BYTE_CNT_W]; + + wire use_d = d_gt_a || d_gt_b || (d_gt_c && c_enable_reg); + + wire [4:0] cmp = {a_lt_b, a_lt_c, b_lt_c, c_enable_reg, use_d}; + + reg [PKT_BYTE_CNT_W - 1 : 0] p1_result; + always @(a_reg or b_reg or c_reg or d_reg or cmp) begin + casex (cmp) + 5'b00010: p1_result = c_reg; + 5'b00110: p1_result = b_reg; + 5'b01110: p1_result = b_reg; + 5'b10010: p1_result = c_reg; + 5'b11010: p1_result = a_reg; + 5'b11110: p1_result = a_reg; + + 5'b00000: p1_result = b_reg; + 5'b00100: p1_result = b_reg; + 5'b01100: p1_result = b_reg; + 5'b10000: p1_result = a_reg; + 5'b11000: p1_result = a_reg; + 5'b11100: p1_result = a_reg; + + 5'b????1: p1_result = d_reg; + + default: p1_result = 'X; // don't-care + endcase + end + + generate + if (PIPELINE_POSITION == 1) begin + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + result <= '0; + end + else begin + result <= p1_result; + end + end + end + else begin + always @* begin + result = p1_result; + end + end + endgenerate +endmodule + + +module altera_merlin_burst_adapter_13_1 +#( + parameter // Merlin packet parameters + PKT_BEGIN_BURST = 81, + PKT_ADDR_H = 79, + PKT_ADDR_L = 48, + PKT_BYTE_CNT_H = 5, + PKT_BYTE_CNT_L = 0, + PKT_BURSTWRAP_H = 11, + PKT_BURSTWRAP_L = 6, + PKT_TRANS_COMPRESSED_READ = 14, + PKT_TRANS_WRITE = 13, + PKT_TRANS_READ = 12, + PKT_BYTEEN_H = 83, + PKT_BYTEEN_L = 80, + PKT_BURST_TYPE_H = 88, + PKT_BURST_TYPE_L = 87, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + IN_NARROW_SIZE = 0, + OUT_NARROW_SIZE = 0, + OUT_FIXED = 0, + OUT_COMPLETE_WRAP = 0, + ST_DATA_W = 89, + ST_CHANNEL_W = 8, + + // Component-specific parameters + BYTEENABLE_SYNTHESIS = 0, + BURSTWRAP_CONST_MASK = 0, + PIPE_INPUTS = 0, + NO_WRAP_SUPPORT = 0, + BURSTWRAP_CONST_VALUE = -1, + OUT_BYTE_CNT_H = 5, + OUT_BURSTWRAP_H = 11 +) +( + + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink0_valid, + input [ST_DATA_W-1 : 0] sink0_data, + input [ST_CHANNEL_W-1 : 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output reg sink0_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg source0_valid, + output reg [ST_DATA_W-1 : 0] source0_data, + output reg [ST_CHANNEL_W-1 : 0] source0_channel, + output reg source0_startofpacket, + output reg source0_endofpacket, + input source0_ready +); + localparam + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + OUT_BYTE_CNT_W = OUT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + OUT_BURSTWRAP_W = OUT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + OUT_MAX_BYTE_CNT = 1 << (OUT_BYTE_CNT_W - 1), + OUT_MAX_BURSTWRAP = (1 << OUT_BURSTWRAP_W) - 1, + NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1, + PKT_BURST_TYPE_W = PKT_BURST_TYPE_H - PKT_BURST_TYPE_L + 1, + LOG2_NUM_SYMBOLS = (NUM_SYMBOLS == 1) ? 1 :log2ceil(NUM_SYMBOLS); + + // "min" operation on burstwrap values is a bitwise AND. + // Todo: one input is always set to constant OUT_MAX_BURSTWRAP; this is a + // number of the form 2^n. Does this fact yield an optimization? + function [PKT_BURSTWRAP_W - 1 : 0] altera_merlin_burst_adapter_burstwrap_min( + input [PKT_BURSTWRAP_W - 1 : 0] a, b + ); + altera_merlin_burst_adapter_burstwrap_min = a & b; + endfunction + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function unsigned[63:0] log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + //---------------------------------------------------- + // AXSIZE encoding: run-time size of the transaction. + // --------------------------------------------------- + function reg[511:0] set_byteenable_based_on_size; + input [PKT_BURST_SIZE_W-1:0] axsize; + begin + case (axsize) + 4'b0000: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001; + 4'b0001: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003; + 4'b0010: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F; + 4'b0011: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF; + 4'b0100: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFF; + 4'b0101: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF; + 4'b0110: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF; + 4'b0111: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + 4'b1000: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + 4'b1001: set_byteenable_based_on_size = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + default: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001; + endcase + end + endfunction + + // --------------------------------------------------- + // STATE MACHINE DEFINITIONS + // --------------------------------------------------- + typedef enum bit [2:0] { // int unsigned { + ST_IDLE = 3'b000, + ST_COMP_TRANS = 3'b001, // This state is used for compressed transactions + // - Address and byte count needs to be calculated for every round internally + ST_UNCOMP_TRANS = 3'b010, // This state is used for uncompressed transaction where address is passthrough + // and bytecount is decremented based on max + ST_UNCOMP_WR_SUBBURST = 3'b100 + } t_state; + t_state state, next_state; + + // --------------------------------------------------- + // AXI Burst Type Encoding + // --------------------------------------------------- + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + RESERVED = 2'b11 + } AxiBurstType; + + // ------------------------------ + // Note on signal naming convention used + // in_* --> These signals are either coming directly from sink or a combi off the sink signals + // --> Timing - zero cycle + // d0_in_* --> Signals that are to be used in this block. It is off a mux between in_* signals + // and the 'saved' version of the signals + // --> Timing - zero cycle (IF PIPE_INPUTS == 0) + // d1_in_* --> Signals that are output of initial flop stage. + // --> Timing - always delayed by 1 clock. (vs the input) + + // ------------------------------ + // CONSTANTS + // ------------------------------ + wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS [PKT_BYTE_CNT_W - 1 : 0]; + wire [PKT_BYTE_CNT_W - 1 : 0] out_max_byte_cnt_sig = OUT_MAX_BYTE_CNT [PKT_BYTE_CNT_W - 1 : 0]; + + // quartus integration failure + wire [63:0] log2_numsymbols = log2ceil(NUM_SYMBOLS); + wire [PKT_BURST_SIZE_W - 1 : 0] encoded_numsymbols = log2_numsymbols[PKT_BURST_SIZE_W-1:0]; + + // --------------------------------------------------- + // INPUT STAGE SIGNALS CONDITIONING + // --------------------------------------------------- + + // Internal wires + reg [ST_DATA_W - 1 : 0 ] d1_in_data; + reg [ST_CHANNEL_W - 1 : 0 ] d1_in_channel; + reg [PKT_BURST_SIZE_W - 1 : 0] d1_in_size; + reg [PKT_BURST_TYPE_W - 1 : 0] d1_in_bursttype; + reg [PKT_BYTEEN_W - 1 : 0] d1_in_byteen; + reg [PKT_BURST_SIZE_W - 1 : 0] d0_in_size; + reg [PKT_BURSTWRAP_W - 1 : 0] d0_in_burstwrap; + reg [PKT_BURST_TYPE_W - 1 : 0] d0_in_bursttype; + reg [PKT_ADDR_W - 1 : 0] d0_in_addr; + reg [PKT_BYTE_CNT_W - 1 : 0] d0_in_bytecount; + reg d0_in_narrow; + reg d0_in_passthru; + reg d0_in_valid; + reg d0_in_sop; + reg d0_in_compressed_read; + reg d0_in_write; + reg d0_in_uncompressed_read; + reg d1_in_eop; + reg d1_in_uncompressed_read; + reg d1_in_narrow; + reg d1_in_passthru; + reg in_ready_hold; + + reg [PKT_BYTE_CNT_W - 1 : 0] the_min_byte_cnt_or_num_sym; + + wire [PKT_BURSTWRAP_W - 1 : 0] wrap_mask; + wire [PKT_BURSTWRAP_W - 1 : 0] incremented_wrap_mask; + reg disable_wrap_dist_calc; + + // Input stage registers + reg [ST_DATA_W - 1 : 0] in_data_reg; + reg [ST_CHANNEL_W-1 : 0] in_channel_reg; + reg [PKT_BYTEEN_W - 1 : 0] in_byteen_reg; + reg [PKT_BURST_SIZE_W - 1 : 0] in_size_reg; + reg [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg; + reg [PKT_BURST_TYPE_W - 1 : 0] in_bursttype_reg; + reg [PKT_ADDR_W - 1 : 0] in_addr_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] in_bytecount_reg; + reg in_compressed_read_reg; + reg in_uncompressed_read_reg; + reg in_narrow_reg; // Holds the flag until next burst command. + reg in_passthru_reg; // Holds flag until next start of packet command + reg in_eop_reg; + reg in_bytecount_reg_zero; + reg in_write_reg; + reg in_valid_reg; + reg in_sop_reg; + + + // Length coversion + reg [PKT_ADDR_W - 1 : 0] int_nxt_addr_reg; + reg [PKT_ADDR_W - 1 : 0] int_nxt_addr_reg_dly; + reg [PKT_BYTE_CNT_W - 1 : 0] int_bytes_remaining_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] out_uncomp_byte_cnt_reg; + reg [PKT_BURSTWRAP_W - 1 :0] int_dist_reg; + reg new_burst_reg; + reg [PKT_BYTE_CNT_W -1:0] int_byte_cnt_narrow_reg; + + reg [PKT_ADDR_W - 1 : 0 ] nxt_addr; + reg [PKT_ADDR_W - 1 : 0 ] nxt_addr2; + reg [PKT_BYTE_CNT_W - 1 : 0] nxt_byte_cnt; + reg [PKT_BYTE_CNT_W - 1 : 0] nxt_uncomp_subburst_byte_cnt; + reg [PKT_BYTE_CNT_W - 1 : 0] nxt_byte_remaining; + reg [PKT_BURSTWRAP_W - 1 : 0] nxt_dist; + reg [PKT_ADDR_W - 1 : 0] extended_burstwrap; + + reg [PKT_BYTE_CNT_W -1 :0] d0_int_bytes_remaining; + reg [PKT_ADDR_W - 1 : 0 ] d0_int_nxt_addr; + reg [PKT_BURSTWRAP_W - 1 : 0 ] d0_int_dist; + + // Output registers + reg [PKT_ADDR_W - 1 : 0] out_addr_reg; + reg out_valid_reg; + reg out_sop_reg; + reg out_eop_reg; + reg [PKT_BURSTWRAP_W - 1 : 0] out_burstwrap_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] out_byte_cnt_reg; + reg nxt_in_ready; + +// wire [PKT_ADDR_W - 1 : 0] nxt_out_addr; + wire nxt_out_valid; + wire nxt_out_sop; + wire nxt_out_eop; + wire [PKT_BURSTWRAP_W - 1 : 0] nxt_out_burstwrap; +// wire [PKT_BYTE_CNT_W - 1 : 0] nxt_bytecount; + + // ---------------- + // ALIAS INPUT MAPPINGS + // ----------------- + // cmd PKT_TRANS_COMPRESSED_READ PKT_TRANS_READ PKT_TRANS_WRITE + // read 0 1 0 + // compressed read 1 1 0 + // write 0 0 1 + // N.b. The fabric sets both PKT_TRANS_COMPRESSED_READ and PKT_TRANS_READ ??? + wire in_compressed_read = sink0_data [PKT_TRANS_COMPRESSED_READ]; + wire in_write = sink0_data [PKT_TRANS_WRITE]; + wire in_read = sink0_data [PKT_TRANS_READ]; + wire in_uncompressed_read = in_read & ~sink0_data [PKT_TRANS_COMPRESSED_READ]; + + wire [ST_DATA_W - 1 : 0] in_data = sink0_data; + wire in_valid = sink0_valid & in_ready_hold; // Fbz143820 hold ready and internal valid to zero during reset + wire in_sop = sink0_startofpacket; + wire in_eop = sink0_endofpacket; + wire [ST_CHANNEL_W - 1 : 0] in_channel = sink0_channel; + + wire [PKT_ADDR_W - 1 : 0 ] in_addr = sink0_data[PKT_ADDR_H : PKT_ADDR_L]; + wire [PKT_BYTEEN_W - 1 : 0] in_byteen = sink0_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + wire [PKT_BYTE_CNT_W - 1 : 0] in_bytecount = sink0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]; + wire [PKT_BURST_SIZE_W - 1 : 0] in_size = IN_NARROW_SIZE ? sink0_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] : encoded_numsymbols; + + // Signals decoded based on inputs + wire [PKT_BYTE_CNT_W - 1 : 0] in_burstcount = in_bytecount >> log2_numsymbols[PKT_BYTE_CNT_W -1 :0]; + wire in_narrow = in_size < log2_numsymbols[PKT_BYTE_CNT_W -1 :0]; + wire in_passthru = in_burstcount <= 16; + + wire [PKT_BURST_TYPE_W - 1 : 0] in_bursttype = sink0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]; + wire [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap; + + genvar i; + generate + for (i = 0; i < PKT_BURSTWRAP_W; i = i + 1) begin : assign_burstwrap_bit + if (BURSTWRAP_CONST_MASK[i]) begin + assign in_burstwrap[i] = BURSTWRAP_CONST_VALUE[i]; + end + else begin + assign in_burstwrap[i] = sink0_data[PKT_BURSTWRAP_L + i]; + end + end + endgenerate + + // ---------------------------------- + // Input Load control signals + // ---------------------------------- + +generate if (PIPE_INPUTS == 0) + begin : NON_PIPELINED_INPUTS + + // Used to capture sink signals as each incoming cycle is accepted. + wire load_next_cmd = d0_in_valid & sink0_ready; + + // Used to capture sink signals as each incoming transaction (currently only used by passthru generation) + wire load_next_pkt = d0_in_valid & sink0_ready & d0_in_sop; + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_channel_reg <= '0; + in_data_reg <= '0; + in_burstwrap_reg <= '0; + in_bursttype_reg <= '0; + in_byteen_reg <= '0; + in_narrow_reg <= '0; + in_size_reg <= '0; + in_passthru_reg <= '0; + in_eop_reg <= '0; + in_bytecount_reg_zero <= '0; + in_uncompressed_read_reg <= '0; + end + else begin + if (load_next_cmd) begin + in_channel_reg <= in_channel; + in_data_reg <= in_data; + in_burstwrap_reg <= in_burstwrap; + in_bursttype_reg <= in_bursttype; + in_byteen_reg <= in_byteen; + in_narrow_reg <= in_narrow; + in_size_reg <= in_size; + in_bytecount_reg_zero <= ~|in_bytecount; + in_uncompressed_read_reg <= in_uncompressed_read; + in_eop_reg <= in_eop; + end + + // Passthru is evaluated every transaction + if (load_next_pkt) begin + in_passthru_reg <= in_passthru; + end + end + end + + assign d0_in_size = new_burst_reg ? in_size : in_size_reg; + assign d0_in_addr = in_addr; + assign d0_in_bytecount = in_bytecount; + assign d0_in_burstwrap = new_burst_reg ? in_burstwrap : in_burstwrap_reg; + assign d0_in_bursttype = new_burst_reg ? in_bursttype : in_bursttype_reg; + assign d0_in_narrow = new_burst_reg ? in_narrow : in_narrow_reg; + assign d0_in_passthru = load_next_pkt ? in_passthru : in_passthru_reg; + assign d0_in_write = in_write; + assign d0_in_compressed_read = in_compressed_read; + assign d0_in_uncompressed_read = in_uncompressed_read; + assign d0_in_valid = in_valid; + assign d0_in_sop = in_sop; + assign d1_in_eop = in_eop_reg; + assign d1_in_data = in_data_reg; + assign d1_in_channel = in_channel_reg; + assign d1_in_size = in_size_reg; + assign d1_in_bursttype = in_bursttype_reg; + assign d1_in_byteen = in_byteen_reg; + assign d1_in_uncompressed_read = in_uncompressed_read_reg; + assign d1_in_narrow = in_narrow_reg; + assign d1_in_passthru = in_passthru_reg; + + end : NON_PIPELINED_INPUTS + +else + begin : PIPELINED_INPUTS + + reg [PKT_BURST_SIZE_W - 1 : 0] d0_int_size; + reg [PKT_BURSTWRAP_W - 1 : 0] d0_int_burstwrap; + reg [PKT_BURST_TYPE_W - 1 : 0] d0_int_bursttype; + reg d0_int_narrow; + reg d0_int_passthru; + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_channel_reg <= '0; + in_data_reg <= '0; + in_burstwrap_reg <= '0; + in_bursttype_reg <= '0; + in_byteen_reg <= '0; + in_narrow_reg <= '0; + in_size_reg <= '0; + in_addr_reg <= '0; + in_passthru_reg <= '0; + in_eop_reg <= '0; + in_bytecount_reg <= '0; + in_bytecount_reg_zero <= '0; + in_uncompressed_read_reg <= '0; + in_write_reg <= '0; + in_compressed_read_reg <= '0; + in_uncompressed_read_reg <= '0; + in_sop_reg <= '0; + in_valid_reg <= '0; + d1_in_eop <= '0; + d1_in_data <= '0; + d1_in_channel <= '0; + d1_in_size <= '0; + d1_in_bursttype <= '0; + d1_in_byteen <= '0; + d1_in_uncompressed_read <= '0; + d1_in_narrow <= '0; + d1_in_passthru <= '0; + d0_int_size <= '0; + d0_int_burstwrap <= '0; + d0_int_bursttype <= '0; + d0_int_narrow <= '0; + d0_int_passthru <= '0; + end + else begin + if (sink0_ready & in_valid) begin + in_channel_reg <= in_channel; + in_data_reg <= in_data; + in_burstwrap_reg <= in_burstwrap; + in_bursttype_reg <= in_bursttype; + in_byteen_reg <= in_byteen; + in_narrow_reg <= in_narrow; + in_size_reg <= in_size; + in_addr_reg <= in_addr; + in_bytecount_reg <= in_bytecount; + in_bytecount_reg_zero <= ~|in_bytecount; + in_uncompressed_read_reg <= in_uncompressed_read; + in_eop_reg <= in_eop; + in_write_reg <= in_write; + in_compressed_read_reg <= in_compressed_read; + in_uncompressed_read_reg <= in_uncompressed_read; + in_sop_reg <= in_sop; + end + // Passthru is evaluated every transaction + if (sink0_ready & in_sop & in_valid) begin + in_passthru_reg <= in_passthru; + end + + if (sink0_ready) in_valid_reg <= in_valid; + + if ( ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + d1_in_eop <= in_eop_reg; + d1_in_data <= in_data_reg; + d1_in_channel <= in_channel_reg; + d1_in_size <= in_size_reg; + d1_in_bursttype <= in_bursttype_reg; + d1_in_byteen <= in_byteen_reg; + d1_in_uncompressed_read <= in_uncompressed_read_reg; + d1_in_narrow <= in_narrow_reg; + d1_in_passthru <= in_passthru_reg; + end + + if ( ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + d0_int_size <= in_size_reg; + d0_int_burstwrap <= in_burstwrap_reg; + d0_int_bursttype <= in_bursttype_reg; + d0_int_narrow <= in_narrow_reg; + d0_int_passthru <= in_passthru_reg; + end + + + end + end + + assign d0_in_size = new_burst_reg ? in_size_reg : d0_int_size; + assign d0_in_addr = in_addr_reg; + assign d0_in_bytecount = in_bytecount_reg; + assign d0_in_burstwrap = new_burst_reg ? in_burstwrap_reg : d0_int_burstwrap; + assign d0_in_bursttype = new_burst_reg ? in_bursttype_reg : d0_int_bursttype; + assign d0_in_narrow = new_burst_reg ? in_narrow_reg : d0_int_narrow; + assign d0_in_passthru = new_burst_reg ? in_passthru_reg : d0_int_passthru; + assign d0_in_write = in_write_reg; + assign d0_in_compressed_read = in_compressed_read_reg; + assign d0_in_uncompressed_read = in_uncompressed_read_reg; + assign d0_in_valid = in_valid_reg; + assign d0_in_sop = in_sop_reg; + + end : PIPELINED_INPUTS +endgenerate + + // ------------------------------- + // Length Calculation Input Staging. + // ------------------------------- + + reg [PKT_ADDR_W -1 : 0] int_nxt_addr_with_offset; + + reg [PKT_BURSTWRAP_W - 1 : 0] no_wrap_dist; + + // These 2 values are part of break up of calculation from pre-flop to post-flop for timing optimization + assign int_nxt_addr_with_offset = int_nxt_addr_reg | extended_burstwrap & (int_nxt_addr_reg_dly + int_byte_cnt_narrow_reg); + + // Unaligned address support + //reg [PKT_ADDR_W + LOG2_NUM_SYMBOLS - 1 : 0 ] d0_in_addr_aligned_full; + reg [PKT_ADDR_W + log2ceil(NUM_SYMBOLS) - 1 : 0 ] d0_in_addr_aligned_full; + altera_merlin_address_alignment + # ( + .ADDR_W (PKT_ADDR_W), + .BURSTWRAP_W (1), // Not used in burst adapter calculation usage of this module + .TYPE_W (0), // Not used in burst adapter calculation usage of this module + .SIZE_W (PKT_BURST_SIZE_W), + .INCREMENT_ADDRESS (0), + .NUMSYMBOLS (NUM_SYMBOLS) + ) align_address_to_size + ( + .clk(1'b0), .reset(1'b0), .in_valid(1'b0), .in_sop(1'b0), .in_eop(1'b0), .out_ready(), // Dummy. Not used in INCREMENT_ADDRESS=0 settings + // This block is purely combi + .in_data ( { d0_in_addr , d0_in_size } ), + .out_data ( d0_in_addr_aligned_full ) + ); + + // On start of every new burst, take in new input values for calculations + assign d0_int_bytes_remaining = new_burst_reg ? d0_in_bytecount: int_bytes_remaining_reg - out_byte_cnt_reg; + assign d0_int_nxt_addr = new_burst_reg ? d0_in_addr_aligned_full[PKT_ADDR_W-1:0] : int_nxt_addr_with_offset; + assign d0_int_dist = NO_WRAP_SUPPORT ? no_wrap_dist : incremented_wrap_mask - ( d0_int_nxt_addr[PKT_BURSTWRAP_W-1:0] & wrap_mask); + always_comb begin + + if (OUT_BURSTWRAP_W == 0) begin // Special case: 1-symbol, fixed-burst slave. + no_wrap_dist = ~nxt_out_burstwrap[PKT_BURSTWRAP_W] ? num_symbols_sig : '1; + end + else if (OUT_BURSTWRAP_W == 1) begin + no_wrap_dist = ~nxt_out_burstwrap[PKT_BURSTWRAP_W - 1] ? num_symbols_sig : '1; + end + else if (LOG2_NUM_SYMBOLS <= OUT_BURSTWRAP_W) begin + + no_wrap_dist = (|nxt_out_burstwrap[PKT_BURSTWRAP_W - 1: 0] & ~nxt_out_burstwrap[PKT_BURSTWRAP_W - 1]) ? + num_symbols_sig : '1; + end + else begin + no_wrap_dist = num_symbols_sig; + end + + end + + // ------------------------------- + // Output Load Control Signals + // ------------------------------- + + // Used by output flops to load in next state when: + // 1. source has taken command (or ready to accept) + // 2. if no command is pending (IDLE) + wire load_next_out_cmd = source0_ready | ~source0_valid; + //wire load_next_out_pkt = (source0_ready & source0_endofpacket) | ~source0_valid; + + // --------------------------------------------------- + // INTERMEDIATE CONTROL FLAGS / HOLDING REGISTERS + // --------------------------------------------------- + + always_comb begin + + // Default case : Always try to use the slaves max byte count. If a narrow transfer occurs, follow the masters num_symbols_sig + the_min_byte_cnt_or_num_sym = d0_in_narrow ? num_symbols_sig : out_max_byte_cnt_sig; + + + if (OUT_BURSTWRAP_W == 0) begin // Special case: 1-symbol, fixed-burst slave. + disable_wrap_dist_calc = ~d0_in_burstwrap[OUT_BURSTWRAP_W]; + end + else begin + if (OUT_NARROW_SIZE || OUT_FIXED || OUT_COMPLETE_WRAP) begin //AXI Slave + // When burst type is "RESERVED" it means that a fix burst wide-to-narrow has occured + // kevtan : added highest bit of wrap mask + disable_wrap_dist_calc = (d0_in_passthru && d0_in_bursttype != RESERVED) | nxt_out_burstwrap[PKT_BURSTWRAP_W - 1]; + the_min_byte_cnt_or_num_sym = (d0_in_narrow && ~d0_in_passthru && d0_in_bursttype==WRAP) ? num_symbols_sig : out_max_byte_cnt_sig; + // kevtan : Fbz140322 : in case of narrow transfer, chop to smallest if it's not passthru + // Calculation is messed up if narrow + // : added term to only chop to smallest in case of wrapping transactions + end + else if (OUT_BURSTWRAP_W == PKT_BURSTWRAP_W) begin // Sequential slave + disable_wrap_dist_calc = d0_in_burstwrap[PKT_BURSTWRAP_W - 1]; + end + else begin + // Dont really have a full story here to tell "Default?" + // This assumes that OUT_BURSTWRAP_W < PKT_BURSTWRAP_W. Then looks at the slave's wrap boundary. + // If d0_in_burstwrap[OUT_BURSTWRAP_W] is set, this is sequential? + // If d0_in_burstwrap[OUT_BURSTWRAP_W - 1] is set, then it needs to be sequential to the slave? + disable_wrap_dist_calc = ~d0_in_burstwrap[OUT_BURSTWRAP_W] & d0_in_burstwrap[OUT_BURSTWRAP_W - 1]; + end + end + end + + + // ---------------------------------------------------- + // FSM : Finite State Machine + // For handling the control signals for burst adapter. + // Note: Arcs in the SM will only take effect is there's no backpressurring from the source + // --------------------------------------------------- + + always_comb begin : state_transition + // default + next_state = ST_IDLE; + + case (state) + ST_IDLE : begin + next_state = ST_IDLE; + + if (d0_in_valid) begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + + ST_UNCOMP_TRANS : begin + next_state = ST_UNCOMP_TRANS; + + if (source0_endofpacket) begin + if (~d0_in_valid) next_state = ST_IDLE; + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + else begin + if (|nxt_uncomp_subburst_byte_cnt) next_state = ST_UNCOMP_WR_SUBBURST; + end + end + + ST_UNCOMP_WR_SUBBURST : begin + next_state = ST_UNCOMP_WR_SUBBURST; + + if (source0_endofpacket) begin + if (~d0_in_valid) next_state = ST_IDLE; + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + else begin + if (~|nxt_uncomp_subburst_byte_cnt) next_state = ST_UNCOMP_TRANS; + end + end + + ST_COMP_TRANS : begin + next_state = ST_COMP_TRANS; + + if (source0_endofpacket) begin + if (~d0_in_valid) begin + next_state = ST_IDLE; + end + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + end + + endcase + end + + // ---------------------------------------------------- + // FSM : Controlled output control signals + // ---------------------------------------------------- + + // in_ready is asserted when: + // 1. IDLE + // 2. COMPRESSED TRANSACTION : When not being back pressured by source and sending out last cmd. + // 3. UNCOMPRESSED TRANSACTION : When not being back pressured by source + + assign nxt_in_ready = (state == ST_COMP_TRANS) ? source0_endofpacket & source0_ready | ~source0_valid : + (state == ST_UNCOMP_TRANS | state == ST_UNCOMP_WR_SUBBURST) ? source0_ready | ~source0_valid : + in_ready_hold; // Fbz143820 hold ready and internal valid to zero during reset + + // out_valid is asserted: + // 1. Following sink_valid unless in ST_COMP_TRANS, where it's always one, unless it's endofpacket. + assign nxt_out_valid = ((state == ST_COMP_TRANS) & ~source0_endofpacket ) ? 1'b1 : d0_in_valid; + + // out_startofpacket + // 1. Following sink_startofpacket unless in ST_COMP_TRANS, where it's always one for first cycle before accepted. + assign nxt_out_sop = ( (state == ST_COMP_TRANS) & source0_ready & !new_burst_reg) ? 1'b0 : d0_in_sop; + + // out_endofpacket ?? + // Follows sink_endofpacket unless in ST_COMP_TRANS, where it is a compare of whether this is the last cycle + assign nxt_out_eop = (state == ST_COMP_TRANS) ? ( source0_ready? new_burst_reg : in_bytecount_reg_zero ) : d1_in_eop; + + + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + state <= ST_IDLE; + out_valid_reg <= '0; + out_sop_reg <= '0; + in_ready_hold <= '0; + end + else begin + if (~source0_valid | source0_ready) begin + state <= next_state; + out_valid_reg <= nxt_out_valid; + out_sop_reg <= nxt_out_sop; + end + in_ready_hold <= 1'b1; + end + end + + assign sink0_ready = nxt_in_ready; // COMBI OUT?? + + // --------------------------------------------------- + // Converter + // --------------------------------------------------- + + // --------------------------------------------------- + // Wrap boundary distance calculation + // --------------------------------------------------- + + // Wrap mask takes in nxt_out_burstwrap to handle cases where there's a wrapping Avalon slave with boundary < PKT_BURSTWRAP_W + assign wrap_mask = disable_wrap_dist_calc ? '1 : nxt_out_burstwrap; + + // Must be valid in the cycle prior to each begin-subburst, for calculating begin_subburst_byte_cnt. + altera_merlin_burst_adapter_burstwrap_increment #(.WIDTH (PKT_BURSTWRAP_W)) the_burstwrap_increment + ( + .mask (wrap_mask), + .inc (incremented_wrap_mask) + ); + + // --------------------------------------------------- + // Length Converter + // --------------------------------------------------- + + always_comb + begin : EXT_BURSTWRAP + extended_burstwrap = { {(PKT_ADDR_W - PKT_BURSTWRAP_W) {d0_in_burstwrap[PKT_BURSTWRAP_W -1]}}, d0_in_burstwrap }; + end + + altera_merlin_burst_adapter_min #( + .PKT_BYTE_CNT_W (PKT_BYTE_CNT_W), + .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W), + .PIPELINE_POSITION (2) // NO PIPELINE (ALL COMBI) + ) + the_min ( + .clk (clk), + .reset (reset), + .a (d0_int_bytes_remaining), + .b (the_min_byte_cnt_or_num_sym), + .c (d0_int_dist), + .c_enable (~wrap_mask[PKT_BURSTWRAP_W - 1]), + .d (num_symbols_sig), + .result (nxt_byte_cnt) + ); + +// synthesis translate_off + +// TEMP ASSERTION FOR OWN CHECKING +//always @(posedge clk or posedge reset) begin +// if (~reset && in_bursttype==WRAP && sink0_valid && sink0_ready && NO_WRAP_SUPPORT==1) begin +// $display ("SELF_CHK: WRAP transaction seen in no wrap support settings"); +// end +//end + +// synthesis translate_on + + // --------------------------------------- + // Next Address Calculation + // --------------------------------------- + always_comb + begin : NXT_ADDR_CALC + + nxt_addr = d0_int_nxt_addr & ~extended_burstwrap; + // this part of calculation is moved to post flop (nxt_addr2 = (extended_burstwrap & (d0_int_nxt_addr + nxt_byte_cnt_narrow)); + + end + + // --------------------------------------- + // Length Converter Registers + // --------------------------------------- + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + out_byte_cnt_reg <= '0; + int_byte_cnt_narrow_reg <= '0; + int_bytes_remaining_reg <= '0; + int_nxt_addr_reg <= '0; + int_nxt_addr_reg_dly <= '0; + new_burst_reg <= '0; + out_addr_reg <= '0; + end + else begin + if (load_next_out_cmd) begin + out_byte_cnt_reg <= nxt_byte_cnt; + int_byte_cnt_narrow_reg <= (nxt_byte_cnt >> log2_numsymbols[PKT_BYTE_CNT_W -1 :0]) << d0_in_size; + int_bytes_remaining_reg <= d0_int_bytes_remaining; + int_nxt_addr_reg <= nxt_addr; + int_nxt_addr_reg_dly <= d0_int_nxt_addr; + // New burst is when next byte count is equal to bytes remaining. (Used only in COMPRESSED transaction) + new_burst_reg <= (nxt_byte_cnt == d0_int_bytes_remaining) | next_state != ST_COMP_TRANS; + // Initial address and non-COMPRESSED transaction address does not use offset. + out_addr_reg <= new_burst_reg ? d0_in_addr : int_nxt_addr_with_offset; + end + end + end + + // ---------------------------------------------------- + // Uncompressed transaction calculations + // Address : No changes, just pass through (handled in the flop in for out_addr_reg) // Make it to the output? + // Byte count : For reads, this will be just the num_symbols_sig + // : For writes, it will need to decrement for subsequent reads unless it's 0, + // in which the next calculated byte count is used. + // ---------------------------------------------------- + + always_comb + begin : UNCOMPRESSED_SUBBURST_BYTE_CNT_CALC + + // During start of uncompressed transaction, load the nxt_uncomp_subburst_byte_cnt with the "current output byte count - num_symbols_sig" + // After that, on subsequent cycles, load in the 'saved' byte count value - num_symbols_sig + // This signal is used also for transition of the state machine to ensure we will reload the byte count with the results from + // length converter if we decremented to zero. + // In essence, the wrap boundary is still observed and maintained. [Hence the use of the current output byte count when in ST_UNCOMP_TRANS. + + nxt_uncomp_subburst_byte_cnt = + (state == ST_UNCOMP_TRANS) ? + ( (source0_valid & source0_ready) ? out_byte_cnt_reg - num_symbols_sig : out_uncomp_byte_cnt_reg ) : + out_uncomp_byte_cnt_reg - ( (source0_valid & source0_ready)? num_symbols_sig : '0) ; + + end + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + out_uncomp_byte_cnt_reg <= '0; + end + else begin + if (load_next_out_cmd) begin + out_uncomp_byte_cnt_reg <= nxt_uncomp_subburst_byte_cnt; + end + end + end + + // --------------------------------------------------- + // Burst Type Generation + // AXI/Avalon masters - Avalon slave - This is pass through from packet to slave + // AXI/Avalon masters - AXI slave - It will always be converted to INCR type + // --------------------------------------------------- + reg [PKT_BURST_TYPE_W - 1 : 0 ] out_bursttype; + + // bursttype will switch to INCR if repeated wraps detected (NOTE: ??) + assign out_bursttype = ((d1_in_bursttype == RESERVED)| (~d1_in_passthru & OUT_NARROW_SIZE)) ? INCR : d1_in_bursttype; + + // --------------------------------------------------- + // Burst Wrap Generation + // Burst wrap is taken to be just the MIN between OUT_MAX_BURSTWRAP and the input burstwrap + // This is to handle cases where the slave's wrapping boundary is different from the master's + // Essentially, the master transaction characteristics are honored, but the burst wrap is modified. + // (Arguably, this can be handled by the slave) + // NOTE: Internally, this is used to generate the wrap_mask, so to calculate the correct wrapping distance. + // --------------------------------------------------- + + assign nxt_out_burstwrap = altera_merlin_burst_adapter_burstwrap_min(OUT_MAX_BURSTWRAP, d0_in_burstwrap); + + always_ff @(posedge clk or posedge reset) begin + if (reset) out_burstwrap_reg <= '0; + else + if ( ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + out_burstwrap_reg <= nxt_out_burstwrap; + end + end + + // --------------------------------------------------- + // Byte enable generation + // Follow unless : in compressed transaction. + // --------------------------------------------------- + reg [LOG2_NUM_SYMBOLS - 1 : 0 ] out_addr_masked; + wire [511:0 ] d1_initial_byteen = set_byteenable_based_on_size(d1_in_size); // To fix quartus integration error. + // Unused bits are expected to be synthesized away + reg [PKT_BYTEEN_W - 1 : 0 ] out_byteen; + + // Unaligned address changes. + // NOTE : Assumption : Byte enable is calculated for all cycles coming out from BA, and needs to be based on aligned address. + // Hence, it cannot take directly output address of BA (which sends out unaligned address for 1st cycle) + always_ff @(posedge clk or posedge reset) begin + if (reset) out_addr_masked <= '0; + else + if (load_next_out_cmd) out_addr_masked <= new_burst_reg ? d0_in_addr_aligned_full[LOG2_NUM_SYMBOLS-1:0] : int_nxt_addr_with_offset[LOG2_NUM_SYMBOLS-1:0]; + end + + always_comb begin + if (BYTEENABLE_SYNTHESIS == 1 && d1_in_narrow == 1 && (state == ST_COMP_TRANS) ) + out_byteen = d1_initial_byteen [NUM_SYMBOLS-1:0] << out_addr_masked; + else + out_byteen = d1_in_byteen; + end + + + // --------------------------------------------------- + // Mapping of output signals. This will help to see what is comb out or flop out + // --------------------------------------------------- + + always_comb begin : source0_out_assignments + + source0_valid = out_valid_reg; + source0_startofpacket = out_sop_reg; + source0_endofpacket = nxt_out_eop; // COMBI + + // Generic assign to all data + source0_data = d1_in_data; + source0_channel = d1_in_channel; + + // Override fields the component is aware of. + source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = d1_in_uncompressed_read ? num_symbols_sig : + (state == ST_UNCOMP_WR_SUBBURST) ? out_uncomp_byte_cnt_reg : + out_byte_cnt_reg; // COMBI + source0_data[PKT_ADDR_H : PKT_ADDR_L] = out_addr_reg; + source0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = out_burstwrap_reg; + source0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = out_bursttype; // COMBI + source0_data[PKT_BYTEEN_H: PKT_BYTEEN_L] = out_byteen; // COMBI + end + + +endmodule + + diff --git a/ip/altera/ddr3/altera_merlin_burst_adapter_new.sv b/ip/altera/ddr3/altera_merlin_burst_adapter_new.sv new file mode 100644 index 0000000..dafc4c0 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_burst_adapter_new.sv @@ -0,0 +1,1890 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_burst_adapter/new_source/altera_merlin_burst_adapter_new.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +`timescale 1 ns / 1 ns + +// ------------------------------------------------------------------- +// Merlin Burst Adapter: converts incoming burst packets to fit slave burst +// capabilities. +// ------------------------------------------------------------------- +module altera_merlin_burst_adapter_new +#( + parameter + // Standard merlin packet parameters that indicate + // field position within the packet + PKT_BEGIN_BURST = 81, + PKT_ADDR_H = 79, + PKT_ADDR_L = 48, + PKT_BYTE_CNT_H = 5, + PKT_BYTE_CNT_L = 0, + PKT_BURSTWRAP_H = 11, + PKT_BURSTWRAP_L = 6, + PKT_TRANS_COMPRESSED_READ = 14, + PKT_TRANS_WRITE = 13, + PKT_TRANS_READ = 12, + PKT_BYTEEN_H = 83, + PKT_BYTEEN_L = 80, + PKT_BURST_TYPE_H = 88, + PKT_BURST_TYPE_L = 87, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + ST_DATA_W = 89, + ST_CHANNEL_W = 8, + + // The values here are used to infer the slave's maximum + // burst count and constant wrapping boundary (if it exists) + OUT_BYTE_CNT_H = 5, + OUT_BURSTWRAP_H = 11, + + // Indicates if incoming packets can have sizes less + // than the data width + IN_NARROW_SIZE = 0, + + // Indicates if the endpoint slave can accept packets + // with sizes less than the data width + OUT_NARROW_SIZE = 0, + + // Indicates if the endpoint slave can accept fixed bursts + OUT_FIXED = 0, + + // Indicates if the endpoint slave can accept wrap bursts + OUT_COMPLETE_WRAP = 0, + + // Enables byteenable synthesis, used to convert size to + // byteenables + BYTEENABLE_SYNTHESIS = 0, + + // A mask that indicates which bits of the burstwrap field are + // constant. Used for optimization purposes. + BURSTWRAP_CONST_MASK = 0, + + // Indicates the value of burstwrap bits that are constant when + // used with BURSTWRAP_CONST_MASK + BURSTWRAP_CONST_VALUE = -1, + + // Controls wrapping support. For optimization purposes. + NO_WRAP_SUPPORT = 0, + INCOMPLETE_WRAP_SUPPORT = 1, + + // Pipelining options + PIPE_INPUTS = 0, + PIPE_INTERNAL = 0 +) +( + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink0_valid, + input [ST_DATA_W - 1 : 0] sink0_data, + input [ST_CHANNEL_W - 1 : 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output reg sink0_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg source0_valid, + output reg [ST_DATA_W - 1 : 0] source0_data, + output reg [ST_CHANNEL_W - 1 : 0] source0_channel, + output reg source0_startofpacket, + output reg source0_endofpacket, + input source0_ready +); + + // Widths of various fields in the packet + localparam + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + OUT_BYTE_CNT_W = OUT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + OUT_BURSTWRAP_W = OUT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1, + PKT_BURST_TYPE_W = PKT_BURST_TYPE_H - PKT_BURST_TYPE_L + 1; + + localparam + NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + LOG2_NUM_SYMBOLS = log2ceil(NUM_SYMBOLS), + ADDR_MASK_SEL = (NUM_SYMBOLS == 1) ? 1 : log2ceil(NUM_SYMBOLS); + + // We try to keep everything in terms of words (transfers) instead of + // bytes in this implementation. Cognitive ease! + localparam + IN_LEN_W = PKT_BYTE_CNT_W - LOG2_NUM_SYMBOLS, + MAX_IN_LEN = 1 << (IN_LEN_W - 1), + OUT_LEN_W = OUT_BYTE_CNT_W - LOG2_NUM_SYMBOLS, + MAX_OUT_LEN = 1 << (OUT_LEN_W - 1), + + BNDRY_WIDTH = PKT_BURSTWRAP_W, + OUT_BOUNDARY = MAX_OUT_LEN * NUM_SYMBOLS, + BYTE_TO_WORD_SHIFT = log2ceil(NUM_SYMBOLS), + BYTE_TO_WORD_SHIFT_W = log2ceil(BYTE_TO_WORD_SHIFT) + 1; + + // Determines the protocol from the features that are enabled or disabled. + // Should be moved to the code that parameterizes this adapter. + localparam + AXI_SLAVE = OUT_FIXED & OUT_NARROW_SIZE & OUT_COMPLETE_WRAP, + IS_WRAP_AVALON_SLAVE = !AXI_SLAVE & (PKT_BURSTWRAP_H != OUT_BURSTWRAP_H), + IS_INCR_SLAVE = !AXI_SLAVE & !IS_WRAP_AVALON_SLAVE, + NON_BURSTING_SLAVE = (MAX_OUT_LEN == 1), + // This parameter indicates that the system is purely INCR avalon master/slave + INCR_AVALON_SYS = IS_INCR_SLAVE && (PKT_BURSTWRAP_W == 1) && (OUT_BURSTWRAP_W == 1) && (IN_NARROW_SIZE == 0); + + // --------------------------------------------------- + // State definitions + // --------------------------------------------------- + typedef enum bit [1:0] { + + // The idle state. + ST_IDLE = 2'b00, + + // Adapter enters this state when the converters accept a compressed + // transaction (read). Address and burst length is calculated + // for every output transfer. + ST_COMP_TRANS = 2'b01, + + // Adapter enters this state when the converters accept uncompressed + // transactions (writes, generally). Address is passed through and + // burst length is decremented according to the conventions of the + // packet format. + ST_UNCOMP_TRANS = 2'b10 + } t_state; + + t_state state, next_state; + + // --------------------------------------------------- + // Merlin packet burst type encoding + // --------------------------------------------------- + typedef enum bit[1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + REP_WRAP = 2'b11 + } BurstType; + + // --------------------------------------------------- + // Here we go! + // + // An optional input pipeline stage. We typically do not use this + // because the interconnect allows users to add pipelines just + // before the burst adapter inputs. + // + // Signal prefix entering this stage: sink0_* + // Signal prefix exiting this stage: sink0_pipe_* + // --------------------------------------------------- + wire sink0_pipe_valid; + wire [ST_DATA_W - 1 : 0] sink0_pipe_data; + wire [ST_CHANNEL_W - 1 : 0] sink0_pipe_channel; + wire sink0_pipe_sop; + wire sink0_pipe_eop; + wire sink0_pipe_ready; + + generate + if (PIPE_INPUTS == 1) begin : input_pipeline + altera_avalon_st_pipeline_stage #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (ST_DATA_W), + .USE_PACKETS (1), + .USE_EMPTY (0), + .EMPTY_WIDTH (0), + .CHANNEL_WIDTH (ST_CHANNEL_W), + .PACKET_WIDTH (2), + .ERROR_WIDTH (0), + .PIPELINE_READY (1) + ) input_pipe ( + .clk (clk), + .reset (reset), + + .in_ready (sink0_ready), + .in_valid (sink0_valid), + .in_startofpacket (sink0_startofpacket), + .in_endofpacket (sink0_endofpacket), + .in_data (sink0_data), + .in_channel (sink0_channel), + + .out_ready (sink0_pipe_ready), + .out_valid (sink0_pipe_valid), + .out_startofpacket (sink0_pipe_sop), + .out_endofpacket (sink0_pipe_eop), + .out_data (sink0_pipe_data), + .out_channel (sink0_pipe_channel), + + .in_empty (1'b0), + .in_error (1'b0), + .out_empty (), + .out_error () + ); + end + else begin : no_input_pipeline + + assign sink0_pipe_valid = sink0_valid; + assign sink0_pipe_data = sink0_data; + assign sink0_pipe_channel = sink0_channel; + assign sink0_pipe_sop = sink0_startofpacket; + assign sink0_pipe_eop = sink0_endofpacket; + assign sink0_ready = sink0_pipe_ready; + + end + endgenerate + + // -------------------------------------------------- + // Signal extraction stage. We extract signals from + // the packet payload and compute some values. + // + // Signal prefix entering this stage: sink0_pipe_* + // Signal prefix exiting this stage: in_* + // -------------------------------------------------- + wire [PKT_BURST_TYPE_W - 1 : 0] in_bursttype = sink0_pipe_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]; + wire [PKT_BYTE_CNT_W - 1 : 0] in_bytecount = sink0_pipe_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]; + wire [PKT_ADDR_W - 1 : 0] in_addr = sink0_pipe_data[PKT_ADDR_H : PKT_ADDR_L]; + wire [63 : 0] log2_numsymbols = log2ceil(NUM_SYMBOLS); + wire [PKT_BYTE_CNT_W - 1 : 0] in_burstcount = in_bytecount >> log2_numsymbols[PKT_BYTE_CNT_W - 1 : 0]; + wire [IN_LEN_W - 1 : 0] in_len = in_burstcount[IN_LEN_W - 1 : 0]; + wire [PKT_BURST_SIZE_W - 1 : 0] in_size = sink0_pipe_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L]; + wire in_write = sink0_pipe_data[PKT_TRANS_WRITE]; + wire in_compressed_read = sink0_pipe_data[PKT_TRANS_COMPRESSED_READ]; + wire in_read = sink0_pipe_data[PKT_TRANS_READ]; + wire in_uncompressed_read = in_read & ~sink0_pipe_data[PKT_TRANS_COMPRESSED_READ]; + wire in_sop = sink0_pipe_sop; + wire in_eop = sink0_pipe_eop; + wire [PKT_BYTEEN_W - 1 : 0] in_byteen = sink0_pipe_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + wire in_passthru = in_burstcount <= 16; + + wire in_valid; + reg in_ready_hold; + wire in_narrow; + wire [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap; + wire [PKT_ADDR_W - 1 : 0] in_aligned_addr; + wire [PKT_BURSTWRAP_W - 1 : 0] in_boundary; + + // Used to keep ready low during reset + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_ready_hold <= '0; + end else begin + in_ready_hold <= '1; + end + end + + assign in_valid = sink0_pipe_valid & in_ready_hold; + assign in_narrow = in_size < log2_numsymbols[PKT_BYTE_CNT_W - 1 : 0]; + + // Optimization: extract burstwrap, and drive the constant bits to + // their constant values to help the synthesis tool. + genvar i; + generate + for (i = 0; i < PKT_BURSTWRAP_W; i = i+1) begin: assign_burstwrap_bit + if (BURSTWRAP_CONST_MASK[i]) begin + assign in_burstwrap[i] = BURSTWRAP_CONST_VALUE[i]; + end + else begin + assign in_burstwrap[i] = sink0_pipe_data[PKT_BURSTWRAP_L + i]; + end + end + endgenerate + + // Addresses in the packet can be unaligned. Here we align the address + // for ease of internal calculations. The initial output address may + // still be unaligned to preserve the original transaction intention. + + wire [PKT_ADDR_W + LOG2_NUM_SYMBOLS - 1 : 0] out_mask_and_aligned_addr; + altera_merlin_address_alignment + #( + .ADDR_W (PKT_ADDR_W), + .BURSTWRAP_W (1), // unused because we just want to align address + .TYPE_W (0), // unused because we just want to align address + .SIZE_W (PKT_BURST_SIZE_W), + .INCREMENT_ADDRESS (0), + .NUMSYMBOLS (NUM_SYMBOLS) + ) align_address_to_size + ( + // Not used when INCREMENT_ADDRESS = 0 + .clk (1'b0), + .reset (1'b0), + .in_valid (1'b0), + .in_sop (1'b0), + .in_eop (1'b0), + .out_ready (), + + .in_data ({ in_addr, in_size }), + .out_data (out_mask_and_aligned_addr) + ); + + assign in_aligned_addr = out_mask_and_aligned_addr[PKT_ADDR_W - 1 : 0]; + + // Incrementing the burstwrap provides the wrapping boundary for + // wrapping transactions. + altera_merlin_burst_adapter_burstwrap_increment + #( + .WIDTH (PKT_BURSTWRAP_W) + ) the_burstwrap_increment + ( + .mask (in_burstwrap), + .inc (in_boundary) + ); + + localparam OUT_BNDRY_ADDR_SEL_W = log2ceil(OUT_BOUNDARY); + localparam OUT_BOUNDARY_WIDTH = OUT_BNDRY_ADDR_SEL_W + 1; + + // address to use for distance calculations when the transaction + // boundary is less than the slave's wrapping boundary. + wire [PKT_ADDR_W - 1 : 0] in_bndry_addr_sel; + + // the length (in words) to the transaction boundary (if it exists) + wire [IN_LEN_W - 1 : 0] len_to_in_bndry; + + // the length (in words) to the slave's boundary (if it exists) + wire [OUT_BOUNDARY_WIDTH - 1 : 0] len_to_out_bndry; + + reg [IN_LEN_W - 1 : 0] first_len; + wire [BYTE_TO_WORD_SHIFT_W - 1 : 0] byte_to_word_shift; + assign byte_to_word_shift = BYTE_TO_WORD_SHIFT[BYTE_TO_WORD_SHIFT_W - 1 : 0]; + + // This part calculates the length that is required to align the burst to + // the transaction's wrapping boundary (if it exists), or to the slave's + // wrapping boundary (if it exists). We pre-compute this ahead of the + // converters to minimize the logic loops in determining the output + // burst lengths. Note that incoming addresses for wrapping transactions + // are always aligned to size by definition. + + assign in_bndry_addr_sel = in_addr & in_burstwrap; + assign len_to_in_bndry = (in_boundary - in_bndry_addr_sel) >> byte_to_word_shift; + + generate + + if (OUT_BNDRY_ADDR_SEL_W > 0) begin : len_to_out_bndry_calc + wire [OUT_BNDRY_ADDR_SEL_W - 1 : 0] out_bndry_addr_sel; + + // We have to use the aligned address, because this part may + // handle incoming incrementing bursts which can be unaligned. + assign out_bndry_addr_sel = in_aligned_addr[OUT_BNDRY_ADDR_SEL_W - 1 : 0]; + assign len_to_out_bndry = (OUT_BOUNDARY - out_bndry_addr_sel) >> byte_to_word_shift; + end + + // A nonsensical corner-case of a wrapping slave with + // MAX_OUT_LEN = 1, NUM_SYMBOLS = 1 + else begin : len_to_out_bndry_calc_corner + assign len_to_out_bndry = OUT_BOUNDARY >> byte_to_word_shift; + end + + endgenerate + + // -------------------------------------------------- + // Optional internal pipeline stage. + // + // Note that we still buffer the transfer if the pipeline stage is + // unused, because the adapter must accept read transactions before + // converting them. Failure to do this will lead to masters receiving + // responses before their commands have been accepted in unpipelined + // systems. The buffering registers are named in_*_reg. + // + // Notes on signal naming convention used: + // + // in_* --> These signals are coming directly from the previous stage. + // --> Timing - zero cycle delta + // d0_in_* --> Signals that are outputs of this stage. + // --> Timing - zero cycle delta (IF PIPE_INTERNAL == 0) else 1 clock + // d1_in_* --> Signals that are outputs of this stage. + // --> Timing - always delayed by 1 clock. (vs the input) + // -------------------------------------------------- + reg in_sop_reg; + reg in_eop_reg; + reg in_valid_reg; + reg in_compressed_read_reg; + reg in_uncompressed_read_reg; + reg in_write_reg; + reg in_passthru_reg; + reg [PKT_BURST_SIZE_W - 1 : 0] in_size_reg; + reg [ST_DATA_W - 1 : 0] in_data_reg; + reg [ST_CHANNEL_W - 1 : 0] in_channel_reg; + reg [PKT_BURST_TYPE_W - 1 : 0] in_bursttype_reg; + reg [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg; + reg [PKT_BYTEEN_W - 1 : 0] in_byteen_reg; + reg [PKT_ADDR_W - 1 : 0] in_addr_reg; + reg [PKT_ADDR_W - 1 : 0] in_aligned_addr_reg; + reg [IN_LEN_W - 1 : 0] in_len_reg; + reg in_narrow_reg; + + reg [PKT_ADDR_W - 1 : 0] d0_in_addr; + reg [PKT_ADDR_W - 1 : 0] d0_in_aligned_addr; + reg d0_in_sop; + reg d0_in_compressed_read; + reg d0_in_uncompressed_read; + reg d0_in_write; + reg [PKT_BURST_TYPE_W - 1 : 0] d0_in_bursttype; + reg [PKT_BURSTWRAP_W - 1 : 0] d0_in_burstwrap; + reg [PKT_BURSTWRAP_W - 1 : 0] d0_in_burstwrap_value; + reg [PKT_BURST_SIZE_W - 1 : 0] d0_in_size; + reg [PKT_BURST_SIZE_W - 1 : 0] d0_in_size_value; + reg [IN_LEN_W - 1 : 0] d0_in_len; + reg d0_in_valid; + + reg d1_in_narrow; + reg [PKT_ADDR_W - 1 : 0] d1_in_aligned_addr; + reg d1_in_eop; + reg d1_in_compressed_read; + reg d1_in_uncompressed_read; + reg [ST_DATA_W - 1 : 0] d1_in_data; + reg [ST_CHANNEL_W - 1 : 0] d1_in_channel; + reg d1_in_write; + reg [PKT_BURST_TYPE_W - 1 : 0] d1_in_bursttype; + reg [PKT_BURSTWRAP_W - 1 : 0] d1_in_burstwrap; + reg d1_in_passthru; + reg [PKT_BURST_SIZE_W - 1 : 0] d1_in_size; + reg [PKT_BYTEEN_W - 1 : 0] d1_in_byteen; + + reg nb; + + generate + if (PIPE_INTERNAL == 0) begin : no_internal_pipeline + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_eop_reg <= '0; + in_compressed_read_reg <= '0; + in_uncompressed_read_reg <= '0; + in_data_reg <= '0; + in_channel_reg <= '0; + in_write_reg <= '0; + in_bursttype_reg <= '0; + in_burstwrap_reg <= '0; + in_passthru_reg <= '0; + in_size_reg <= '0; + in_byteen_reg <= '0; + in_aligned_addr_reg <= '0; + in_narrow_reg <= '0; + end else begin + if (sink0_pipe_valid & sink0_pipe_ready) begin + in_eop_reg <= in_eop; + in_data_reg <= sink0_pipe_data; + in_channel_reg <= sink0_pipe_channel; + in_compressed_read_reg <= in_compressed_read; + in_uncompressed_read_reg <= in_uncompressed_read; + in_write_reg <= in_write; + in_bursttype_reg <= in_bursttype; + in_burstwrap_reg <= in_burstwrap; + in_size_reg <= in_size; + in_byteen_reg <= in_byteen; + in_aligned_addr_reg <= in_aligned_addr; + in_narrow_reg <= in_narrow; + end + // length changes during packets, so sample + // length-dependent signals at the start + if (sink0_pipe_valid & sink0_pipe_ready & in_sop) begin + in_passthru_reg <= in_passthru; + end + end // else: !if(reset) + end // always_ff @ + + always_comb begin + d0_in_sop = in_sop; + d0_in_compressed_read = in_compressed_read; + d0_in_uncompressed_read = in_uncompressed_read; + d0_in_write = in_write; + d0_in_burstwrap = in_burstwrap; + d0_in_size = in_size; + d0_in_addr = in_addr; + d0_in_aligned_addr = in_aligned_addr; + d0_in_len = in_len; + d0_in_valid = in_valid; + + d1_in_eop = in_eop_reg; + d1_in_compressed_read = in_compressed_read_reg; + d1_in_uncompressed_read = in_uncompressed_read_reg; + d1_in_write = in_write_reg; + d1_in_burstwrap = in_burstwrap_reg; + d1_in_size = in_size_reg; + d1_in_aligned_addr = in_aligned_addr_reg; + d1_in_data = in_data_reg; + d1_in_channel = in_channel_reg; + d1_in_bursttype = in_bursttype_reg; + d1_in_passthru = in_passthru_reg; + d1_in_byteen = in_byteen_reg; + d1_in_narrow = in_narrow_reg; + + // Assign after the related d1_in_* signals have been assigned. + d0_in_size_value = nb ? d0_in_size : d1_in_size; + d0_in_burstwrap_value = nb ? d0_in_burstwrap : d1_in_burstwrap; + end + + end // block: no_internal_pipeline + else begin : internal_pipeline + + reg [PKT_BURST_SIZE_W - 1 : 0] d0_in_size_dl; + reg [PKT_BURSTWRAP_W - 1 : 0] d0_in_burstwrap_dl; + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_eop_reg <= '0; + in_sop_reg <= '0; + in_compressed_read_reg <= '0; + in_uncompressed_read_reg <= '0; + in_data_reg <= '0; + in_channel_reg <= '0; + in_write_reg <= '0; + in_bursttype_reg <= '0; + in_burstwrap_reg <= '0; + in_passthru_reg <= '0; + in_size_reg <= '0; + in_byteen_reg <= '0; + in_addr_reg <= '0; + in_aligned_addr_reg <= '0; + in_len_reg <= '0; + in_narrow_reg <= '0; + in_valid_reg <= '0; + + d1_in_eop <= '0; + d1_in_compressed_read <= '0; + d1_in_data <= '0; + d1_in_channel <= '0; + d1_in_write <= '0; + d1_in_bursttype <= '0; + d1_in_burstwrap <= '0; + d1_in_passthru <= '0; + d1_in_size <= '0; + d0_in_size_dl <= '0; + d0_in_burstwrap_dl <= '0; + d1_in_byteen <= '0; + end else begin + if (sink0_pipe_valid & sink0_pipe_ready) begin + in_eop_reg <= in_eop; + in_sop_reg <= in_sop; + in_data_reg <= sink0_pipe_data; + in_channel_reg <= sink0_pipe_channel; + in_compressed_read_reg <= in_compressed_read; + in_uncompressed_read_reg <= in_uncompressed_read; + in_write_reg <= in_write; + in_bursttype_reg <= in_bursttype; + in_burstwrap_reg <= in_burstwrap; + in_size_reg <= in_size; + in_byteen_reg <= in_byteen; + in_addr_reg <= in_addr; + in_aligned_addr_reg <= in_aligned_addr; + in_len_reg <= in_len; + in_narrow_reg <= in_narrow; + end + // length changes during packets, so sample + // length-dependent signals at the start + if (in_valid & sink0_pipe_ready & in_sop) + in_passthru_reg <= in_passthru; + if (sink0_pipe_ready) + in_valid_reg <= in_valid; + if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) )) begin + d1_in_eop <= in_eop_reg; + d1_in_compressed_read <= in_compressed_read_reg; + d1_in_data <= in_data_reg; + d1_in_channel <= in_channel_reg; + d1_in_write <= in_write_reg; + d1_in_bursttype <= in_bursttype_reg; + d1_in_burstwrap <= in_burstwrap_reg; + d0_in_burstwrap_dl <= in_burstwrap_reg; + d1_in_passthru <= in_passthru_reg; + d1_in_size <= in_size_reg; + d0_in_size_dl <= in_size_reg; + d1_in_byteen <= in_byteen_reg; + d1_in_aligned_addr <= in_aligned_addr_reg; + d1_in_narrow <= in_narrow_reg; + d1_in_uncompressed_read <= in_uncompressed_read_reg; + end // if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |... + end // else: !if(reset) + end // always_ff @ + + always_comb begin + d0_in_valid = in_valid_reg; + d0_in_sop = in_sop_reg; + d0_in_compressed_read = in_compressed_read_reg; + d0_in_uncompressed_read = in_uncompressed_read_reg; + d0_in_write = in_write_reg; + d0_in_burstwrap = in_burstwrap_reg; + d0_in_size = in_size_reg; + d0_in_size_value = nb ? in_size_reg : d0_in_size_dl; + d0_in_burstwrap_value = nb ? in_burstwrap_reg : d0_in_burstwrap_dl; + d0_in_addr = in_addr_reg; + d0_in_aligned_addr = in_aligned_addr_reg; + d0_in_len = in_len_reg; + end // always_comb + end // block: internal_pipeline + + endgenerate + + // -------------------------------------------------- + // Control logic stage: state machine + // -------------------------------------------------- + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + state <= ST_IDLE; + end else begin + if (~source0_valid | source0_ready) begin + state <= next_state; + end + end + end + + always_comb begin : state_transition + next_state = ST_IDLE; // default + case (state) + ST_IDLE : begin + next_state = ST_IDLE; + + if (d0_in_valid) begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + + ST_UNCOMP_TRANS : begin + next_state = ST_UNCOMP_TRANS; + + if (source0_endofpacket) begin + if (!d0_in_valid) next_state = ST_IDLE; + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + end + ST_COMP_TRANS : begin + next_state = ST_COMP_TRANS; + + if (source0_endofpacket) begin + if (!d0_in_valid) begin + next_state = ST_IDLE; + end + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + end + endcase + end + + // -------------------------------------------------- + // Control logic stage: signals for the converters. These signals + // enable the correct converter for a burst type, and act as a + // select line when muxing the converter outputs. + // + // Each type of slave receives its own control logic stage, optimized + // for that particular type. + // -------------------------------------------------- + wire [PKT_BYTE_CNT_W - 1 : 0] out_byte_cnt; + wire [IN_LEN_W - 1 : 0] incr_out_len; + wire [IN_LEN_W - 1 : 0] wrap_out_len; + wire [IN_LEN_W - 1 : 0] incr_uncompr_out_len; + wire [IN_LEN_W - 1 : 0] wrap_uncompr_out_len; + wire [PKT_ADDR_W - 1 : 0] incr_out_addr; + wire [PKT_ADDR_W - 1 : 0] wrap_out_addr; + wire [PKT_ADDR_W - 1 : 0] fixed_out_addr; + reg [PKT_ADDR_W - 1 : 0] uncompr_out_addr; + wire [IN_LEN_W - 1 : 0] fixed_out_len; + wire [PKT_ADDR_W - 1 : 0] out_addr; + + wire in_full_size_write_wrap; + wire in_full_size_read_wrap; + wire in_default_converter; + wire in_full_size_incr; + reg in_default_converter_reg; + reg in_full_size_incr_reg; + reg in_full_size_write_wrap_reg; + reg in_full_size_read_wrap_reg; + + wire new_burst; + wire fixed_new_burst; + wire wrap_new_burst; + wire incr_new_burst; + + wire next_out_sop; + wire next_out_eop; + wire is_passthru; + wire enable_incr_converter; + wire enable_fixed_converter; + wire enable_write_wrap_converter; + wire enable_read_wrap_converter; + wire enable_incr_write_converter; + wire enable_incr_read_converter; + reg [IN_LEN_W - 1 : 0] d0_first_len; + + + // ----------------------------------------------------------------------- + // Enable the converters when: + // - (sink0_pipe_valid && (source0_ready | ~source0_valid): + // : when the BA is in idle (!source_valid) and there is a packet coming at input + // or the outpacket has been accepted and there is a packet coming + // - (source0_endofpacket ? 1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready)) + // : For compressed read, need something consider at end_of_packet, only when seeing + // end_of_packet then turn off converter. + // Each converter will be turned on with its own enable based on different type of incoming burst + // ----------------------------------------------------------------------- + generate + if (NON_BURSTING_SLAVE) begin : non_bursting_converter_control + wire [PKT_BYTE_CNT_W - 1 : 0] fixed_out_byte_cnt; + assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols; + + if (PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT + always_comb begin + d0_in_bursttype = nb ? in_bursttype : in_bursttype_reg; + end + end + else begin : PIPELINE_INPUT + reg [PKT_BURST_TYPE_W - 1 :0] d0_in_bursttype_dl; + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + d0_in_bursttype_dl <= '0; + end else begin + if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + d0_in_bursttype_dl <= in_bursttype_reg; + end + end // else: !if(reset) + end // always_ff @ + always_comb begin + d0_in_bursttype = nb ? in_bursttype_reg : d0_in_bursttype_dl; + end + end + + //nb: new burst signal + assign nb = fixed_new_burst; + + // ----------------------------------------------------------------------- + // I. Conveter enable signals: Turn on/off each conveter accordingly + // ----------------------------------------------------------------------- + assign enable_fixed_converter = (d0_in_valid && (source0_ready | !source0_valid) || (source0_endofpacket ? 1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready))); + + // ----------------------------------------------------------------------- + // II. Packet signals + // ----------------------------------------------------------------------- + assign next_out_sop = ((state == ST_COMP_TRANS) & source0_ready & !(fixed_new_burst)) ? 1'b0 : d0_in_sop; + assign next_out_eop = (state == ST_COMP_TRANS) ? fixed_new_burst : d1_in_eop; + + // ----------------------------------------------------------------------- + // III. Output select + // ----------------------------------------------------------------------- + assign out_byte_cnt = fixed_out_byte_cnt; + assign out_addr = fixed_out_addr; + end + else if (INCR_AVALON_SYS) begin : incr_avalon_converter_control + wire [PKT_BYTE_CNT_W - 1 : 0] incr_out_byte_cnt; + assign incr_out_byte_cnt = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols; + + //nb: new burst signal + assign nb = incr_new_burst; + + // ----------------------------------------------------------------------- + // I. Conveter enable signals: Turn on/off each conveter accordingly + // ----------------------------------------------------------------------- + assign enable_incr_converter = (d0_in_valid && (source0_ready | !source0_valid) || (source0_endofpacket ? 1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready))); + + // ----------------------------------------------------------------------- + // II. Packet signals + // ----------------------------------------------------------------------- + assign next_out_sop = ((state == ST_COMP_TRANS) & source0_ready & !(incr_new_burst)) ? 1'b0 : d0_in_sop; + assign next_out_eop = (state == ST_COMP_TRANS) ? incr_new_burst : d1_in_eop; + + // ----------------------------------------------------------------------- + // III. Output select + // ----------------------------------------------------------------------- + assign out_byte_cnt = incr_out_byte_cnt; + assign out_addr = incr_out_addr; + end + else begin : other_converter_control + if (IS_WRAP_AVALON_SLAVE) begin + wire in_narrow_or_fixed; + wire in_read_but_not_fixed_or_narrow; + wire in_write_but_not_fixed_or_narrow; + reg in_read_but_not_fixed_or_narrow_reg; + reg in_write_but_not_fixed_or_narrow_reg; + reg in_narrow_or_fixed_reg; + reg d0_in_read_but_not_fixed_or_narrow; + reg d0_in_write_but_not_fixed_or_narrow; + reg d0_in_default_converter; + reg d1_in_narrow_or_fixed; + reg d1_in_read_but_not_fixed_or_narrow; + reg d1_in_write_but_not_fixed_or_narrow; + reg d1_in_default_converter; + reg [IN_LEN_W - 1 : 0] first_len_reg; + + wire [PKT_BYTE_CNT_W - 1 : 0] fixed_out_byte_cnt; + wire [PKT_BYTE_CNT_W - 1 : 0] incr_out_byte_cnt; + wire in_fixed = (in_bursttype == 2'b00) || (in_bursttype == 2'b11); + + // nb: new burst + assign nb = (d1_in_narrow_or_fixed ? fixed_new_burst : new_burst); + assign in_read_but_not_fixed_or_narrow = in_compressed_read & !in_narrow_or_fixed; + assign in_write_but_not_fixed_or_narrow = in_write & !in_narrow_or_fixed; + assign in_narrow_or_fixed = in_narrow || in_fixed; + assign in_default_converter = in_fixed || in_narrow || in_uncompressed_read; + assign incr_out_byte_cnt = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols; + assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols; + + //---------------------------------------------------------------- + // I. Pipeline input stage + //---------------------------------------------------------------- + if (PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_narrow_or_fixed_reg <= '0; + in_read_but_not_fixed_or_narrow_reg <= '0; + in_write_but_not_fixed_or_narrow_reg <= '0; + in_default_converter_reg <= '0; + end else begin + if (sink0_pipe_ready & sink0_pipe_valid) begin + in_narrow_or_fixed_reg <= in_narrow_or_fixed; + in_read_but_not_fixed_or_narrow_reg <= in_read_but_not_fixed_or_narrow; + in_write_but_not_fixed_or_narrow_reg <= in_write_but_not_fixed_or_narrow; + in_default_converter_reg <= in_default_converter; + end // if (sink0_pipe_ready & sink0_pipe_valid) + end // else: !if(reset) + end // always_ff @ + always_comb begin + d0_first_len = first_len; + d0_in_read_but_not_fixed_or_narrow = in_read_but_not_fixed_or_narrow; + d0_in_write_but_not_fixed_or_narrow = in_write_but_not_fixed_or_narrow; + d0_in_default_converter = in_default_converter; + d1_in_narrow_or_fixed = in_narrow_or_fixed_reg; + d1_in_read_but_not_fixed_or_narrow = in_read_but_not_fixed_or_narrow_reg; + d1_in_write_but_not_fixed_or_narrow = in_write_but_not_fixed_or_narrow_reg; + d1_in_default_converter = in_default_converter_reg; + end // always_comb + end // block: NO_PIPELINE_INPUT + else begin : PIPELINE_INPUT + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_narrow_or_fixed_reg <= '0; + in_read_but_not_fixed_or_narrow_reg <= '0; + in_write_but_not_fixed_or_narrow_reg <= '0; + in_default_converter_reg <= '0; + d1_in_narrow_or_fixed <= '0; + d1_in_read_but_not_fixed_or_narrow <= '0; + d1_in_write_but_not_fixed_or_narrow <= '0; + d1_in_default_converter <= '0; + first_len_reg <= '0; + end else begin + if (sink0_pipe_ready & sink0_pipe_valid) begin + in_narrow_or_fixed_reg <= in_narrow_or_fixed; + in_read_but_not_fixed_or_narrow_reg <= in_read_but_not_fixed_or_narrow; + in_write_but_not_fixed_or_narrow_reg <= in_write_but_not_fixed_or_narrow; + in_default_converter_reg <= in_default_converter; + end // if (sink0_pipe_ready & sink0_pipe_valid) + if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + first_len_reg <= first_len; + d1_in_narrow_or_fixed <= in_narrow_or_fixed_reg; + d1_in_read_but_not_fixed_or_narrow <= in_read_but_not_fixed_or_narrow_reg; + d1_in_write_but_not_fixed_or_narrow <= in_write_but_not_fixed_or_narrow_reg; + d1_in_default_converter <= in_default_converter_reg; + end + end // else: !if(reset) + end // always_ff @ + always_comb begin + d0_in_default_converter = in_default_converter_reg; + d0_first_len = first_len_reg; + d0_in_read_but_not_fixed_or_narrow = in_read_but_not_fixed_or_narrow_reg; + d0_in_write_but_not_fixed_or_narrow = in_write_but_not_fixed_or_narrow_reg; + end + end // block: PIPELINE_INPUT + + // ------------------------------------------------------------------------- + // II. First length calculation + // ------------------------------------------------------------------------- + wire same_boundary; + // ---------------------------------------------------------- + // Slave is a wrapping slave, if in_burst wrap has same boundary + // pass the burst untouched. + // ---------------------------------------------------------- + if (OUT_BNDRY_ADDR_SEL_W <= PKT_BURSTWRAP_W - 1) begin + assign same_boundary = (in_boundary[OUT_BNDRY_ADDR_SEL_W] == 1); + end else begin + assign same_boundary = 0; + end + + // -------------------------------------------------------------------------- + // 1. If in_burst wrapping boundary is lager or INCR burst then always + // send first sub_burst length is aligned to slave boudary, + // 2. Else aligned to master boundary + // Notes: + // For INCR, it is tricky that the length can be any value but as the slave is + // wrapping, still needs to convert the burst at slave boundary + // (in_len <= len_to_out_bndry): can tell the in INCR burst can totally + // fit in slave boundary -> pass thru + // This works same way for INCOMPLETE wrap as well, so cannot make seperate + // optimization when dont support INCOMPLETE wrap + // -------------------------------------------------------------------------- + wire in_len_smaller_not_cross_out_bndry; + wire in_len_smaller_not_cross_in_bndry; + + assign in_len_smaller_not_cross_out_bndry = (in_len <= len_to_out_bndry); + assign in_len_smaller_not_cross_in_bndry = (in_len <= len_to_in_bndry); + always_comb begin + if ((in_boundary > OUT_BOUNDARY) || (in_burstwrap[BNDRY_WIDTH - 1] == 1)) begin + first_len = len_to_out_bndry; + if (in_len_smaller_not_cross_out_bndry || same_boundary) + first_len = in_len; + end + else begin + first_len = len_to_in_bndry; + if (in_len_smaller_not_cross_in_bndry || same_boundary) + first_len = in_len; + end + end // always_comb + + // ----------------------------------------------------------------------- + // III. Conveter enable signals: Turn on/off each conveter accordingly + // ----------------------------------------------------------------------- + // WRAPPING AVALON: two conveters: + // 1. wrap_burst_conveter -> handle full_size INCR, WRAP + // 2. default_burst_conveter -> handle narrow_size burst + // opt, seperate enable for write and reach + // ----------------------------------------------------------------------- + // fixed_new_burst && new_burst : note this for incr_write as it is write_enable, cannot turn on incase a read happen before + assign enable_incr_write_converter = (d0_in_valid && d0_in_write_but_not_fixed_or_narrow && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_write_but_not_fixed_or_narrow && !nb)); + assign enable_incr_read_converter = (d0_in_valid && d0_in_read_but_not_fixed_or_narrow && fixed_new_burst && (source0_ready || !source0_valid) || (( state == ST_COMP_TRANS) && source0_ready && d1_in_read_but_not_fixed_or_narrow && !nb)); + assign enable_fixed_converter = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb)); + + // ----------------------------------------------------------------------- + // IV. Packet signals + // ----------------------------------------------------------------------- + assign next_out_sop = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : new_burst)) ? 1'b0 : d0_in_sop; + assign next_out_eop = (state == ST_COMP_TRANS) ? (d1_in_default_converter ? fixed_new_burst : new_burst) : d1_in_eop; + + // ----------------------------------------------------------------------- + // V. Output select + // ----------------------------------------------------------------------- + assign out_byte_cnt = d1_in_default_converter ? fixed_out_byte_cnt : incr_out_byte_cnt; + assign out_addr = d1_in_default_converter ? fixed_out_addr : incr_out_addr; + end // if (IS_WRAP_AVALON_SLAVE) + + if (AXI_SLAVE) begin + reg [IN_LEN_W - 1 : 0] first_len_reg; + reg d0_in_incr; + reg d1_in_incr; + reg in_incr_reg; + wire in_read_wrap_conveter; + wire in_write_wrap_conveter; + reg in_read_wrap_conveter_reg; + reg in_write_wrap_conveter_reg; + + reg d0_in_read_wrap_conveter; + reg d0_in_write_wrap_conveter; + reg d0_in_default_converter; + reg d1_in_read_wrap_conveter; + reg d1_in_write_wrap_conveter; + reg d1_in_default_converter; + + wire in_incr = (in_bursttype == 2'b01) && !in_uncompressed_read; + wire in_wrap = (in_bursttype == 2'b10); + wire in_fixed = (in_bursttype == 2'b00) || (in_bursttype == 2'b11); + wire in_narrow_read_wrap_smaller_16 = in_narrow && in_wrap && is_passthru && in_compressed_read; + wire in_narrow_write_wrap_smaller_16 = in_narrow && in_wrap && is_passthru && in_write; + wire in_narrow_wrap_larger_16 = in_narrow && in_wrap && !is_passthru; + + wire [PKT_BYTE_CNT_W - 1 : 0] wrap_out_byte_cnt; + wire [PKT_BYTE_CNT_W - 1 : 0] fixed_out_byte_cnt; + wire [PKT_BYTE_CNT_W - 1 : 0] incr_out_byte_cnt; + + assign incr_out_byte_cnt = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols; + assign wrap_out_byte_cnt = (d1_in_compressed_read ? wrap_out_len : wrap_uncompr_out_len) << log2_numsymbols; + assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols; + + assign in_full_size_read_wrap = in_compressed_read & in_wrap & !in_narrow; + assign in_full_size_write_wrap = in_write & in_wrap & !in_narrow; + assign in_read_wrap_conveter = in_full_size_read_wrap || in_narrow_read_wrap_smaller_16; + assign in_write_wrap_conveter = in_full_size_write_wrap || in_narrow_write_wrap_smaller_16; + assign in_default_converter = in_narrow_wrap_larger_16 || in_fixed || in_uncompressed_read; + + //nb: new burst signal + assign nb = (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst)); + // is_passthru : still read from real input, as we want to shift 1 clock here, all control signal and first len + assign is_passthru = in_sop ? (in_passthru) : in_passthru_reg; + + //---------------------------------------------------------------- + // I. Pipeline input stage + //---------------------------------------------------------------- + if(PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_write_wrap_conveter_reg <= '0; + in_read_wrap_conveter_reg <= '0; + in_default_converter_reg <= '0; + in_incr_reg <= '0; + end else begin + if (sink0_pipe_ready & sink0_pipe_valid) begin + in_write_wrap_conveter_reg <= in_write_wrap_conveter; + in_read_wrap_conveter_reg <= in_read_wrap_conveter; + in_default_converter_reg <= in_default_converter; + in_incr_reg <= in_incr; + end + end // else: !if(reset) + end // always_ff @ + always_comb begin + d0_in_incr = in_incr; + d0_in_default_converter = in_default_converter; + d0_in_read_wrap_conveter = in_read_wrap_conveter; + d0_in_write_wrap_conveter = in_write_wrap_conveter; + d0_first_len = first_len; + d1_in_default_converter = in_default_converter_reg; + d1_in_read_wrap_conveter = in_read_wrap_conveter_reg; + d1_in_write_wrap_conveter = in_write_wrap_conveter_reg; + d1_in_incr = in_incr_reg; + d0_in_bursttype = nb ? in_bursttype : in_bursttype_reg; + end + end + else begin : PIPELINE_INPUT + reg [PKT_BURST_TYPE_W - 1 :0] d0_in_bursttype_dl; + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_write_wrap_conveter_reg <= '0; + in_read_wrap_conveter_reg <= '0; + in_default_converter_reg <= '0; + d1_in_default_converter <= '0; + d1_in_read_wrap_conveter <= '0; + d1_in_write_wrap_conveter <= '0; + first_len_reg <= '0; + in_incr_reg <= '0; + d0_in_bursttype_dl <= '0; + end else begin + if (sink0_pipe_ready & in_valid) begin + in_write_wrap_conveter_reg <= in_write_wrap_conveter; + in_read_wrap_conveter_reg <= in_read_wrap_conveter; + in_default_converter_reg <= in_default_converter; + first_len_reg <= first_len; + in_incr_reg <= in_incr; + end + if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + d1_in_default_converter <= in_default_converter_reg; + d1_in_read_wrap_conveter <= in_read_wrap_conveter_reg; + d1_in_write_wrap_conveter <= in_write_wrap_conveter_reg; + d1_in_incr <= in_incr_reg; + d0_in_bursttype_dl <= in_bursttype_reg; + end + end // else: !if(reset) + end // always_ff @ + always_comb begin + d0_in_incr = in_incr_reg; + d0_in_default_converter = in_default_converter_reg; + d0_in_read_wrap_conveter = in_read_wrap_conveter_reg; + d0_in_write_wrap_conveter = in_write_wrap_conveter_reg; + d0_first_len = first_len_reg; + d0_in_bursttype = nb ? in_bursttype_reg : d0_in_bursttype_dl; + end + end + + // ------------------------------------------------------------------------- + // II. First length calculation + // ------------------------------------------------------------------------- + // For AXI slave, avalon master must set alwaysBurstMaxBurst so + // INCOMPLETE wrap burst will not happen + // 1. If any wrapping burst that smaller than 16 -> pass thru + // 2. Else first sub_burst length is aligned to slave boundary + // ------------------------------------------------------------------------- + //wire passthru = (in_len < len_to_out_bndry) || is_passthru; // why compare here? Keep this until we figure out why. + always_comb begin + if (in_boundary > OUT_BOUNDARY) begin + first_len = is_passthru ? in_len : len_to_out_bndry; + end else begin + first_len = is_passthru ? in_len : len_to_in_bndry; + end + end // always_comb + + // ----------------------------------------------------------------------- + // III. Conveter enable signals: Turn on/off each conveter accordingly + // ----------------------------------------------------------------------- + // AXI slave: three conveters: + // 1. wrap_burst_conveter -> handle WRAP + // 1.1 : full size wrap --> convert to fit in slave boundary + // 1.2 : narrow size wrap + // ---> <= 16 : pass thru + // ---> > 16 : convert to non-bursting + // 2. incr_burst_convter -> handle full/narrow size INCR + // 3. default_burst_conveter -> handle FIXED + // ----------------------------------------------------------------------- + // Note: narrow wrap with length larger 16 can happen with Avalon narrow wraping + // master to AXI slave. To support this, it will hurt fmax + // also the WA adapter currently not pack data in this case, to be better support + // need to start from WA first + // ----------------------------------------------------------------------- + assign new_burst = incr_new_burst && wrap_new_burst; + assign enable_incr_converter = (d0_in_valid && d0_in_incr && fixed_new_burst && wrap_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_incr && !nb)); + assign enable_write_wrap_converter = (d0_in_valid && d0_in_write_wrap_conveter && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_write_wrap_conveter && !nb)); + assign enable_read_wrap_converter = (d0_in_valid && d0_in_read_wrap_conveter && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_read_wrap_conveter && !nb)); + assign enable_fixed_converter = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb)); + + // ----------------------------------------------------------------------- + // IV. Packet signals + // ----------------------------------------------------------------------- + assign next_out_sop = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))) ? 1'b0 : d0_in_sop; + assign next_out_eop = (state == ST_COMP_TRANS) ? (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst)) : d1_in_eop; + + // ----------------------------------------------------------------------- + // V. Output select + // ----------------------------------------------------------------------- + assign out_byte_cnt = d1_in_default_converter ? fixed_out_byte_cnt : (d1_in_incr ? incr_out_byte_cnt : wrap_out_byte_cnt); + assign out_addr = d1_in_default_converter ? fixed_out_addr : (d1_in_incr ? incr_out_addr : wrap_out_addr); + end // if (AXI_SLAVE) + + if (IS_INCR_SLAVE) begin + reg [IN_LEN_W - 1 : 0] first_len_reg; + reg d0_in_default_converter; + reg d0_in_full_size_incr; + reg d0_in_full_size_write_wrap; + reg d0_in_full_size_read_wrap; + reg d1_in_default_converter; + reg d1_in_full_size_incr; + reg d1_in_full_size_write_wrap; + reg d1_in_full_size_read_wrap; + reg d1_in_incr; + reg in_incr_reg; + wire in_incr = (in_bursttype == 2'b01); + wire in_wrap = (in_bursttype == 2'b10); + + wire [PKT_BYTE_CNT_W - 1 : 0] incr_out_byte_cnt; + wire [PKT_BYTE_CNT_W - 1 : 0] fixed_out_byte_cnt; + + assign incr_out_byte_cnt = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols; + assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols; + + if (NO_WRAP_SUPPORT) begin + assign in_default_converter = !in_full_size_incr; + assign nb = d1_in_default_converter ? fixed_new_burst : incr_new_burst; + end + else begin + wire in_narrow_incr; + wire in_fixed = (in_bursttype == 2'b00) || (in_bursttype == 2'b11); + + assign in_narrow_incr = in_incr & in_narrow; + assign in_default_converter = in_fixed || in_narrow || in_narrow_incr || in_uncompressed_read; + assign nb = (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst)); + end + + assign in_full_size_incr = in_incr & !in_narrow & !in_uncompressed_read; + assign in_full_size_write_wrap = in_write & in_wrap & !in_narrow; + assign in_full_size_read_wrap = in_compressed_read & in_wrap & !in_narrow; + + //---------------------------------------------------------------- + // I. Pipeline input stage + //---------------------------------------------------------------- + if(PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_full_size_write_wrap_reg <= '0; + in_full_size_read_wrap_reg <= '0; + in_full_size_incr_reg <= '0; + in_default_converter_reg <= '0; + in_incr_reg <= '0; + end else begin + if (sink0_pipe_ready & sink0_pipe_valid) begin + in_incr_reg <= in_incr; + in_full_size_incr_reg <= in_full_size_incr; + in_full_size_write_wrap_reg <= in_full_size_write_wrap; + in_full_size_read_wrap_reg <= in_full_size_read_wrap; + in_default_converter_reg <= in_default_converter; + end + end // else: !if(reset) + end // always_ff @ + always_comb begin + d0_in_default_converter = in_default_converter; + d0_in_full_size_incr = in_full_size_incr; + d0_in_full_size_write_wrap = in_full_size_write_wrap; + d0_in_full_size_read_wrap = in_full_size_read_wrap; + d0_first_len = first_len; + d1_in_incr = in_incr_reg; + d1_in_default_converter = in_default_converter_reg; + d1_in_full_size_incr = in_full_size_incr_reg; + d1_in_full_size_write_wrap = in_full_size_write_wrap_reg; + d1_in_full_size_read_wrap = in_full_size_read_wrap_reg; + d0_in_bursttype = nb ? in_bursttype : in_bursttype_reg; + end + end + else begin : PIPELINE_INPUT + reg [PKT_BURST_TYPE_W - 1 :0] d0_in_bursttype_dl; + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_full_size_write_wrap_reg <= '0; + in_full_size_read_wrap_reg <= '0; + in_full_size_incr_reg <= '0; + in_default_converter_reg <= '0; + d1_in_default_converter <= '0; + d1_in_full_size_incr <= '0; + d1_in_full_size_write_wrap <= '0; + d1_in_full_size_read_wrap <= '0; + d1_in_incr <= '0; + first_len_reg <= '0; + in_incr_reg <= '0; + d0_in_bursttype_dl <= '0; + end else begin + if (sink0_pipe_ready & in_valid) begin + in_full_size_incr_reg <= in_full_size_incr; + in_full_size_write_wrap_reg <= in_full_size_write_wrap; + in_full_size_read_wrap_reg <= in_full_size_read_wrap; + in_default_converter_reg <= in_default_converter; + in_incr_reg <= in_incr; + first_len_reg <= first_len; + end + if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + d1_in_default_converter <= in_default_converter_reg; + d1_in_full_size_incr <= in_full_size_incr_reg; + d1_in_full_size_write_wrap <= in_full_size_write_wrap_reg; + d1_in_full_size_read_wrap <= in_full_size_read_wrap_reg; + d1_in_incr <= in_incr_reg; + d0_in_bursttype_dl <= in_bursttype_reg; + end + end // else: !if(reset) + end // always_ff @ + always_comb begin + d0_in_default_converter = in_default_converter_reg; + d0_in_full_size_incr = in_full_size_incr_reg; + d0_in_full_size_write_wrap = in_full_size_write_wrap_reg; + d0_in_full_size_read_wrap = in_full_size_read_wrap_reg; + d0_first_len = first_len_reg; + d0_in_bursttype = nb ? in_bursttype_reg : d0_in_bursttype_dl; + end + end + + // -------------------------------------------------------------------------------------- + // II. First length calculation + // -------------------------------------------------------------------------------------- + // Note: the slave is INCR slave, in pratical is has no boundary so if in burst is wrap + // the sub burst can send out "slave max length" first fs the in burst not yet wraps back + // To simplify and optimize: the first sub_burst length stills send out aligned length first + // -------------------------------------------------------------------------------------- + // If no INCOMPLETE wrap burst + // 1. in_boundary is larger out_boundary; first sub_burst length is: aligned to out boundary + // 2. in_boundary is smaller out_boundary; first sub_burst length is: aligned to in boundary + // -------------------------------------------------------------------------------------- + if (!NO_WRAP_SUPPORT) begin : HAVE_WRAP_BURSTING_SUPPORT + if (!INCOMPLETE_WRAP_SUPPORT) begin : no_incomplete_wrap_support + assign first_len = (in_boundary > OUT_BOUNDARY) ? len_to_out_bndry : len_to_in_bndry; + end + else begin : incomplete_wrap_support + // ------------------------------------------------------------------------- + // If INCOMPLETE wrap support + // 1. The idea is still same, based on boundary and select either aligned to in/out boundary + // 2. But need to check if in_len is smaller to "aligned" in/out boundary for incomplete case + // -> the burst is pass thru is in_len is smaller + // ------------------------------------------------------------------------- + wire in_len_smaller_aligned_out_bdry = (in_len <= len_to_out_bndry); + wire in_len_smaller_aligned_in_bdry = (in_len <= len_to_in_bndry); + always_comb begin + if (in_boundary > OUT_BOUNDARY) begin + first_len = (in_len_smaller_aligned_out_bdry) ? in_len : len_to_out_bndry; + end + else begin + first_len = (in_len_smaller_aligned_in_bdry) ? in_len : len_to_in_bndry; + end + end + end // block: incomplete_wrap_support + end + + // ----------------------------------------------------------------------- + // III. Conveter enable signals: Turn on/off each conveter accordingly + // ----------------------------------------------------------------------- + // INCR slave: three conveters: + // 1. wrap_burst_conveter -> handle WRAP + // 2. incr_burst_convter -> handle INCR + // 2. default_burst_conveter -> handle narrow burst + // ----------------------------------------------------------------------- + // ----------------------------------------------------------------------- + // Purposely support AXI to Avalon: with no wrapping suppport + // all wrapping transaction witll be converted to non-bursting sub-burst + // 21-January-2014 + // ----------------------------------------------------------------------- + if (NO_WRAP_SUPPORT) begin + assign enable_incr_converter = (d0_in_valid && d0_in_full_size_incr && fixed_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_incr && !nb)); + assign enable_fixed_converter = (d0_in_valid && d0_in_default_converter && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb)); + + // ----------------------------------------------------------------------- + // IV. Packet signals + // ----------------------------------------------------------------------- + assign next_out_sop = (state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : incr_new_burst) ? 1'b0 : d0_in_sop; + assign next_out_eop = (state == ST_COMP_TRANS) ? (d1_in_default_converter ? fixed_new_burst : incr_new_burst) : d1_in_eop; + + // ----------------------------------------------------------------------- + // V. Output select + // ----------------------------------------------------------------------- + assign out_byte_cnt = d1_in_default_converter ? fixed_out_byte_cnt : incr_out_byte_cnt; + assign out_addr = d1_in_default_converter ? fixed_out_addr : incr_out_addr; + end + else begin + assign new_burst = incr_new_burst && wrap_new_burst; + assign enable_incr_converter = (d0_in_valid && d0_in_full_size_incr && fixed_new_burst && wrap_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_incr && !nb)); + assign enable_fixed_converter = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb)); + assign enable_write_wrap_converter = (d0_in_valid && d0_in_full_size_write_wrap && fixed_new_burst && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_write_wrap && !nb)); + assign enable_read_wrap_converter = (d0_in_valid && d0_in_full_size_read_wrap && fixed_new_burst && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_read_wrap && !nb)); + + // ----------------------------------------------------------------------- + // IV. Packet signals + // ----------------------------------------------------------------------- + assign next_out_sop = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))) ? 1'b0 : d0_in_sop; + assign next_out_eop = (state == ST_COMP_TRANS) ? (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst)) : d1_in_eop; + + // ----------------------------------------------------------------------- + // V. Output select + // ----------------------------------------------------------------------- + wire [PKT_BYTE_CNT_W - 1 : 0] wrap_out_byte_cnt; + assign wrap_out_byte_cnt = (d1_in_compressed_read ? wrap_out_len : wrap_uncompr_out_len) << log2_numsymbols; + + assign out_byte_cnt = d1_in_default_converter ? fixed_out_byte_cnt : (d1_in_incr ? incr_out_byte_cnt : wrap_out_byte_cnt); + assign out_addr = d1_in_default_converter ? fixed_out_addr : (d1_in_incr ? incr_out_addr : wrap_out_addr); + end + end + end + endgenerate + + // -------------------------------------------------- + // Control signals + // -------------------------------------------------- + reg source0_valid_reg; + wire next_source0_valid; + reg source0_startofpacket_reg; + + wire is_write; + assign is_write = nb ? (d0_in_write) : d1_in_write; + + //------------------------------------------------------------------------- + // Handshaking and packet signals + // ----------------------------------------------------------------------- + // source0_valid: takes from in sink_valid unless read then wait until end_of_packet + assign next_source0_valid = ((state == ST_COMP_TRANS) & !source0_endofpacket) ? 1'b1 : d0_in_valid; + + // sink0_ready needs always to be asserted first, hold one after reset + assign sink0_pipe_ready = (state == ST_UNCOMP_TRANS) ? source0_ready || !source0_valid : (state == ST_COMP_TRANS) ? nb && source0_ready || !source0_valid : in_ready_hold; + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + source0_valid_reg <= '0; + source0_startofpacket_reg <= '1; + end else begin + if (~source0_valid | source0_ready) begin + source0_valid_reg <= next_source0_valid; + source0_startofpacket_reg <= next_out_sop; + end + end // else: !if(reset) + end // always_ff @ + + // Assign output signals + always_comb begin + source0_endofpacket = next_out_eop; + source0_startofpacket = source0_startofpacket_reg; + source0_valid = source0_valid_reg; + end + + // -------------------------------------------------- + // Converters instantiation and signal mappings. + // -------------------------------------------------- + generate + if (NON_BURSTING_SLAVE) begin : non_bursting_slave_converters_sel + altera_default_burst_converter + #( + .PKT_BURST_TYPE_W (PKT_BURST_TYPE_W), + .PKT_ADDR_W (PKT_ADDR_W), + .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W), + .PKT_BURST_SIZE_W (PKT_BURST_SIZE_W), + .LEN_W (IN_LEN_W), + .IS_AXI_SLAVE (AXI_SLAVE) + ) + the_default_burst_converter + ( + .clk (clk), + .reset (reset), + .enable (enable_fixed_converter), // turn on if a fixed + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .in_bursttype (d0_in_bursttype), + .in_burstwrap_reg (d1_in_burstwrap), + .in_burstwrap_value (d0_in_burstwrap_value), + .in_len (d0_in_len), + .in_size_value (d0_in_size_value), + .in_is_write (is_write), + .out_len (fixed_out_len), + .out_addr (fixed_out_addr), + .new_burst (fixed_new_burst) + ); + end + else if (INCR_AVALON_SYS) begin : system_purely_avalon_converter_sel + //----------------------------------------------------------------- + // When system is purely INCR, only need one converter. + //----------------------------------------------------------------- + altera_incr_burst_converter + #( + .MAX_IN_LEN (MAX_IN_LEN), + .MAX_OUT_LEN (MAX_OUT_LEN), + .ADDR_WIDTH (PKT_ADDR_W), + .BNDRY_WIDTH (PKT_BURSTWRAP_W), + .BURSTSIZE_WIDTH (PKT_BURST_SIZE_W), + .IN_NARROW_SIZE (IN_NARROW_SIZE), + .NUM_SYMBOLS (NUM_SYMBOLS), + .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS) + ) + the_converter_for_avalon_incr_slave + ( + .clk (clk), + .reset (reset), + .enable (enable_incr_converter), + .in_len (d0_in_len), + .in_sop (d0_in_sop), + .in_burstwrap_reg (d1_in_burstwrap), + .in_size_t (d0_in_size), + .in_size_reg (d1_in_size), + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .is_write (is_write), + .out_len (incr_out_len), + .uncompr_out_len (incr_uncompr_out_len), + .out_addr (incr_out_addr), + .new_burst_export (incr_new_burst) + ); + end + else begin : converters_selection + if (IS_WRAP_AVALON_SLAVE) begin : wrapping_avalon_slave_converter_sel + altera_wrap_burst_converter + #( + .MAX_IN_LEN (MAX_IN_LEN), + .MAX_OUT_LEN (MAX_OUT_LEN), + .ADDR_WIDTH (PKT_ADDR_W), + .BNDRY_WIDTH (PKT_BURSTWRAP_W), + .AXI_SLAVE (AXI_SLAVE), + .NUM_SYMBOLS (NUM_SYMBOLS), + .OPTIMIZE_WRITE_BURST (0) + ) + the_converter_for_avalon_wrap_slave + ( + .clk (clk), + .reset (reset), + .enable_read (enable_incr_read_converter), + .enable_write (enable_incr_write_converter), + .in_len (d0_in_len), + .first_len (d0_first_len), + .in_sop (d0_in_sop), + .in_burstwrap (d0_in_burstwrap), + .in_burstwrap_reg (d1_in_burstwrap), + .in_boundary (in_boundary), + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .out_len (incr_out_len), + .uncompr_out_len (incr_uncompr_out_len), + .out_addr (incr_out_addr), + .new_burst_export (new_burst) + ); + + altera_default_burst_converter + #( + .PKT_BURST_TYPE_W (PKT_BURST_TYPE_W), + .PKT_ADDR_W (PKT_ADDR_W), + .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W), + .PKT_BURST_SIZE_W (PKT_BURST_SIZE_W), + .LEN_W (IN_LEN_W), + .IS_AXI_SLAVE (AXI_SLAVE) + ) + the_default_burst_converter + ( + .clk (clk), + .reset (reset), + .enable (enable_fixed_converter), // turn on if a fixed + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .in_bursttype (d0_in_bursttype), + .in_burstwrap_reg (d1_in_burstwrap), + .in_burstwrap_value (d0_in_burstwrap_value), + .in_len (d0_in_len), + .in_size_value (d0_in_size_value), + .in_is_write (is_write), + .out_len (fixed_out_len), + .out_addr (fixed_out_addr), + .new_burst (fixed_new_burst) + ); + end + if (AXI_SLAVE) begin : axi_slave_converter_sel + altera_wrap_burst_converter + #( + .MAX_IN_LEN (MAX_IN_LEN), + .MAX_OUT_LEN (MAX_OUT_LEN), + .ADDR_WIDTH (PKT_ADDR_W), + .BNDRY_WIDTH (PKT_BURSTWRAP_W), + .NUM_SYMBOLS (NUM_SYMBOLS), + .AXI_SLAVE (AXI_SLAVE), + .OPTIMIZE_WRITE_BURST (0) + ) + the_converter_for_avalon_wrap_slave + ( + .clk (clk), + .reset (reset), + .enable_read (enable_read_wrap_converter), + .enable_write (enable_write_wrap_converter), + .in_len (d0_in_len), + .first_len (d0_first_len), + .in_sop (d0_in_sop), + .in_burstwrap (d0_in_burstwrap), + .in_burstwrap_reg (d1_in_burstwrap), + .in_boundary (in_boundary), + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .out_len (wrap_out_len), + .uncompr_out_len (wrap_uncompr_out_len), + .out_addr (wrap_out_addr), + .new_burst_export (wrap_new_burst) + ); + + altera_incr_burst_converter + #( + .MAX_IN_LEN (MAX_IN_LEN), + .MAX_OUT_LEN (MAX_OUT_LEN), + .ADDR_WIDTH (PKT_ADDR_W), + .BNDRY_WIDTH (PKT_BURSTWRAP_W), + .BURSTSIZE_WIDTH (PKT_BURST_SIZE_W), + .IN_NARROW_SIZE (IN_NARROW_SIZE), + .NUM_SYMBOLS (NUM_SYMBOLS), + .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS) + ) + the_converter_for_avalon_incr_slave + ( + .clk (clk), + .reset (reset), + .enable (enable_incr_converter), + .in_len (d0_in_len), + .in_sop (d0_in_sop), + .in_burstwrap_reg (d1_in_burstwrap), + .in_size_t (d0_in_size), + .in_size_reg (d1_in_size), + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .is_write (is_write), + .out_len (incr_out_len), + .uncompr_out_len (incr_uncompr_out_len), + .out_addr (incr_out_addr), + .new_burst_export (incr_new_burst) + ); + + // -------------------------------------------------- + // The fixed burst converter module + // -------------------------------------------------- + altera_default_burst_converter + #( + .PKT_BURST_TYPE_W (PKT_BURST_TYPE_W), + .PKT_ADDR_W (PKT_ADDR_W), + .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W), + .PKT_BURST_SIZE_W (PKT_BURST_SIZE_W), + .LEN_W (IN_LEN_W), + .IS_AXI_SLAVE (AXI_SLAVE) + ) + the_default_burst_converter + ( + .clk (clk), + .reset (reset), + .enable (enable_fixed_converter), // turn on if a fixed + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .in_bursttype (d0_in_bursttype), + .in_burstwrap_reg (d1_in_burstwrap), + .in_burstwrap_value (d0_in_burstwrap_value), + .in_len (d0_in_len), + .in_size_value (d0_in_size_value), + .in_is_write (is_write), + .out_len (fixed_out_len), + .out_addr (fixed_out_addr), + .new_burst (fixed_new_burst) + ); + end + if (IS_INCR_SLAVE) begin : incr_slave_converter_sel + if (NO_WRAP_SUPPORT) begin : no_wrap_incr_slave_converter_sel + altera_incr_burst_converter + #( + .MAX_IN_LEN (MAX_IN_LEN), + .MAX_OUT_LEN (MAX_OUT_LEN), + .ADDR_WIDTH (PKT_ADDR_W), + .BNDRY_WIDTH (PKT_BURSTWRAP_W), + .BURSTSIZE_WIDTH (PKT_BURST_SIZE_W), + .IN_NARROW_SIZE (0), // not support narrow as this is INCR avalon slave + .NUM_SYMBOLS (NUM_SYMBOLS), + .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS) + ) + the_converter_for_avalon_incr_slave + ( + .clk (clk), + .reset (reset), + .enable (enable_incr_converter), + .in_len (d0_in_len), + .in_sop (d0_in_sop), + .in_burstwrap_reg (d1_in_burstwrap), + .in_size_t (d0_in_size), + .in_size_reg (d1_in_size), + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .is_write (is_write), + .out_len (incr_out_len), + .uncompr_out_len (incr_uncompr_out_len), + .out_addr (incr_out_addr), + .new_burst_export (incr_new_burst) + ); + + // -------------------------------------------------- + // The default converter + // -------------------------------------------------- + altera_default_burst_converter + #( + .PKT_BURST_TYPE_W (PKT_BURST_TYPE_W), + .PKT_ADDR_W (PKT_ADDR_W), + .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W), + .PKT_BURST_SIZE_W (PKT_BURST_SIZE_W), + .LEN_W (IN_LEN_W), + .IS_AXI_SLAVE (AXI_SLAVE) + ) + the_default_burst_converter + ( + .clk (clk), + .reset (reset), + .enable (enable_fixed_converter), // turn on if a fixed + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .in_bursttype (d0_in_bursttype), + .in_burstwrap_reg (d1_in_burstwrap), + .in_burstwrap_value (d0_in_burstwrap_value), + .in_len (d0_in_len), + .in_size_value (d0_in_size_value), + .in_is_write (is_write), + .out_len (fixed_out_len), + .out_addr (fixed_out_addr), + .new_burst (fixed_new_burst) + ); + end + else begin : wrap_incr_slave_conveter_sel + altera_wrap_burst_converter + #( + .MAX_IN_LEN (MAX_IN_LEN), + .MAX_OUT_LEN (MAX_OUT_LEN), + .ADDR_WIDTH (PKT_ADDR_W), + .BNDRY_WIDTH (PKT_BURSTWRAP_W), + .NUM_SYMBOLS (NUM_SYMBOLS), + .AXI_SLAVE (AXI_SLAVE), + .OPTIMIZE_WRITE_BURST (0) + ) + the_converter_for_avalon_wrap_slave + ( + .clk (clk), + .reset (reset), + .enable_read (enable_read_wrap_converter), + .enable_write (enable_write_wrap_converter), + .in_len (d0_in_len), + .first_len (d0_first_len), + .in_sop (d0_in_sop), + .in_burstwrap (d0_in_burstwrap), + .in_burstwrap_reg (d1_in_burstwrap), + .in_boundary (in_boundary), + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .out_len (wrap_out_len), + .uncompr_out_len (wrap_uncompr_out_len), + .out_addr (wrap_out_addr), + .new_burst_export (wrap_new_burst) + ); + + altera_incr_burst_converter + #( + .MAX_IN_LEN (MAX_IN_LEN), + .MAX_OUT_LEN (MAX_OUT_LEN), + .ADDR_WIDTH (PKT_ADDR_W), + .BNDRY_WIDTH (PKT_BURSTWRAP_W), + .BURSTSIZE_WIDTH (PKT_BURST_SIZE_W), + .IN_NARROW_SIZE (IN_NARROW_SIZE), + .NUM_SYMBOLS (NUM_SYMBOLS), + .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS) + ) + the_converter_for_avalon_incr_slave + ( + .clk (clk), + .reset (reset), + .enable (enable_incr_converter), + .in_len (d0_in_len), + .in_sop (d0_in_sop), + .in_burstwrap_reg (d1_in_burstwrap), + .in_size_t (d0_in_size), + .in_size_reg (d1_in_size), + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .is_write (is_write), + .out_len (incr_out_len), + .uncompr_out_len (incr_uncompr_out_len), + .out_addr (incr_out_addr), + .new_burst_export (incr_new_burst) + ); + + // -------------------------------------------------- + // The fixed burst converter module + // -------------------------------------------------- + altera_default_burst_converter + #( + .PKT_BURST_TYPE_W (PKT_BURST_TYPE_W), + .PKT_ADDR_W (PKT_ADDR_W), + .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W), + .PKT_BURST_SIZE_W (PKT_BURST_SIZE_W), + .LEN_W (IN_LEN_W), + .IS_AXI_SLAVE (AXI_SLAVE) + ) + the_default_burst_converter + ( + .clk (clk), + .reset (reset), + .enable (enable_fixed_converter), // turn on if a fixed + .in_addr (d0_in_aligned_addr), + .in_addr_reg (d1_in_aligned_addr), + .in_bursttype (d0_in_bursttype), + .in_burstwrap_reg (d1_in_burstwrap), + .in_burstwrap_value (d0_in_burstwrap_value), + .in_len (d0_in_len), + .in_size_value (d0_in_size_value), + .in_is_write (is_write), + .out_len (fixed_out_len), + .out_addr (fixed_out_addr), + .new_burst (fixed_new_burst) + ); + end + end + end + endgenerate + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function unsigned[63:0] log2ceil; + input reg [63:0] val; + reg [63:0] i; + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + // --------------------------------------------------- + // Mapping of output signals. + // --------------------------------------------------- + wire load_next_output_pck = source0_ready | !source0_valid; + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + uncompr_out_addr <= '0; + end + else if (load_next_output_pck) begin + uncompr_out_addr <= d0_in_addr; + end + + end + + // --------------------------------------------------- + // Out burstype + // --------------------------------------------------- + // If AXI slave, out_bursttype = INCR if either of the following 2 conditions is met: + // 1) in_passthru (i.e. the input burst count < 16). + // 2) input packet has bursttype == REP_WRAP (Repeated Wrap). + // Else, out_bursttype = in_bursttype. + // For all other slaves, change the bursttype to INCR. + wire [PKT_BURST_TYPE_W - 1 : 0] out_bursttype; + generate + if (AXI_SLAVE) begin : AXI_SLAVE_out_bursttype + assign out_bursttype = (!d1_in_passthru || d1_in_bursttype == REP_WRAP) ? INCR : d1_in_bursttype; + end + else begin : others_slave_out_bursttype + assign out_bursttype = INCR; + end + endgenerate + + // At source0_startofpacket, out_addr_read is the in_addr. + wire [PKT_ADDR_W - 1 : 0] out_addr_read; + assign out_addr_read = source0_startofpacket_reg ? uncompr_out_addr : out_addr; + + // Choose between uncompressed or compressed trans address. + wire [PKT_ADDR_W - 1 : 0] out_addr_assigned_to_packet; + assign out_addr_assigned_to_packet = (d1_in_write || d1_in_uncompressed_read) ? uncompr_out_addr : out_addr_read; + + // --------------------------------------------------- + // Byteenable Generation. + // Passthrough unless compressed transaction. + // --------------------------------------------------- + reg [PKT_BYTEEN_W - 1 : 0 ] out_byteen; + reg [ADDR_MASK_SEL - 1 : 0 ] out_addr_masked; + wire [511:0] initial_byteen = set_byteenable_based_on_size(d1_in_size); // To fix quartus integration error. Unused bits are expected to be synthesized away + + // Unaligned address changes. + // Assumption : Byte enable is calculated for all cycles coming out from BA, and needs to be based on aligned address. + // Hence, it cannot take directly output address of BA (which sends out unaligned address for 1st cycle) + always_comb begin + // Addresses from the converters (out_addr) are always aligned. + out_addr_masked = out_addr[ADDR_MASK_SEL-1:0]; + end + + always_comb begin + if (BYTEENABLE_SYNTHESIS == 1 && d1_in_narrow == 1 && (state == ST_COMP_TRANS)) + out_byteen = initial_byteen[NUM_SYMBOLS-1:0] << out_addr_masked; + else + out_byteen = d1_in_byteen; + end + // -- End of Byteenable Generation -- + + always_comb begin : source0_out_assignments + source0_data = d1_in_data; + source0_channel = d1_in_channel; + // Override fields the component is aware of. + source0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = out_bursttype; + source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L ] = out_byte_cnt; + source0_data[PKT_ADDR_H : PKT_ADDR_L ] = out_addr_assigned_to_packet; + source0_data[PKT_BYTEEN_H : PKT_BYTEEN_L ] = out_byteen; + end + + //---------------------------------------------------- + // "min" operation on burstwrap values is a bitwise AND. + //---------------------------------------------------- + function [PKT_BURSTWRAP_W - 1 : 0] altera_merlin_burst_adapter_burstwrap_min; + input [PKT_BURSTWRAP_W - 1 : 0] a, b; + begin + altera_merlin_burst_adapter_burstwrap_min = a & b; + end + endfunction + + //---------------------------------------------------- + // AXSIZE encoding: run-time size of the transaction. + // --------------------------------------------------- + function reg[511:0] set_byteenable_based_on_size; + input [3:0] axsize; + begin + case (axsize) + 4'b0000: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001; + 4'b0001: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003; + 4'b0010: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F; + 4'b0011: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF; + 4'b0100: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFF; + 4'b0101: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF; + 4'b0110: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF; + 4'b0111: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + 4'b1000: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + 4'b1001: set_byteenable_based_on_size = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + default: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001; + endcase + end + endfunction + +endmodule + diff --git a/ip/altera/ddr3/altera_merlin_burst_adapter_uncmpr.sv b/ip/altera/ddr3/altera_merlin_burst_adapter_uncmpr.sv new file mode 100644 index 0000000..74e5318 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_burst_adapter_uncmpr.sv @@ -0,0 +1,94 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter.sv#68 $ +// $Revision: #68 $ +// $Date: 2014/01/23 $ +// $Author: wkleong $ + +`timescale 1 ns / 1 ns + +// ------------------------------------------------------- +// Adapter for uncompressed transactions only. This adapter will +// typically be used to adapt burst length for non-bursting +// wide to narrow Avalon links. +// ------------------------------------------------------- +module altera_merlin_burst_adapter_uncompressed_only +#( + parameter + PKT_BYTE_CNT_H = 5, + PKT_BYTE_CNT_L = 0, + PKT_BYTEEN_H = 83, + PKT_BYTEEN_L = 80, + ST_DATA_W = 84, + ST_CHANNEL_W = 8 +) +( + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink0_valid, + input [ST_DATA_W-1 : 0] sink0_data, + input [ST_CHANNEL_W-1 : 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output reg sink0_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg source0_valid, + output reg [ST_DATA_W-1 : 0] source0_data, + output reg [ST_CHANNEL_W-1 : 0] source0_channel, + output reg source0_startofpacket, + output reg source0_endofpacket, + input source0_ready +); + localparam + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + + wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS[PKT_BYTE_CNT_W - 1 : 0]; + + always_comb begin : source0_data_assignments + source0_valid = sink0_valid; + source0_channel = sink0_channel; + source0_startofpacket = sink0_startofpacket; + source0_endofpacket = sink0_endofpacket; + + source0_data = sink0_data; + source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = num_symbols_sig; + + sink0_ready = source0_ready; + end + +endmodule + + + diff --git a/ip/altera/ddr3/altera_merlin_burst_uncompressor.sv b/ip/altera/ddr3/altera_merlin_burst_uncompressor.sv new file mode 100644 index 0000000..16c74ae --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_burst_uncompressor.sv @@ -0,0 +1,296 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Burst Uncompressor +// +// Compressed read bursts -> uncompressed +// ------------------------------------------ + +`timescale 1 ns / 1 ns + +module altera_merlin_burst_uncompressor +#( + parameter ADDR_W = 16, + parameter BURSTWRAP_W = 3, + parameter BYTE_CNT_W = 4, + parameter PKT_SYMBOLS = 4, + parameter BURST_SIZE_W = 3 +) +( + input clk, + input reset, + + // sink ST signals + input sink_startofpacket, + input sink_endofpacket, + input sink_valid, + output sink_ready, + + // sink ST "data" + input [ADDR_W - 1: 0] sink_addr, + input [BURSTWRAP_W - 1 : 0] sink_burstwrap, + input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, + input sink_is_compressed, + input [BURST_SIZE_W-1 : 0] sink_burstsize, + + // source ST signals + output source_startofpacket, + output source_endofpacket, + output source_valid, + input source_ready, + + // source ST "data" + output [ADDR_W - 1: 0] source_addr, + output [BURSTWRAP_W - 1 : 0] source_burstwrap, + output [BYTE_CNT_W - 1 : 0] source_byte_cnt, + + // Note: in the slave agent, the output should always be uncompressed. In + // other applications, it may be required to leave-compressed or not. How to + // control? Seems like a simple mux - pass-through if no uncompression is + // required. + output source_is_compressed, + output [BURST_SIZE_W-1 : 0] source_burstsize +); + +//---------------------------------------------------- +// AXSIZE decoding +// +// Turns the axsize value into the actual number of bytes +// being transferred. +// --------------------------------------------------- +function reg[63:0] bytes_in_transfer; + input [BURST_SIZE_W-1:0] axsize; + case (axsize) + 4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + 4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; + 4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; + 4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; + 4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; + 4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; + 4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; + 4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; + 4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000; + 4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000; + default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + endcase + +endfunction + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + // def: Burst Compression. In a merlin network, a compressed burst is one + // which is transmitted in a single beat. Example: read burst. In + // constrast, an uncompressed burst (example: write burst) is transmitted in + // one beat per writedata item. + // + // For compressed bursts which require response packets, burst + // uncompression is required. Concrete example: a read burst of size 8 + // occupies one response-fifo position. When that fifo position reaches the + // front of the FIFO, the slave starts providing the required 8 readdatavalid + // pulses. The 8 return response beats must be provided in a single packet, + // with incrementing address and decrementing byte_cnt fields. Upon receipt + // of the final readdata item of the burst, the response FIFO item is + // retired. + // Burst uncompression logic provides: + // a) 2-state FSM (idle, busy) + // reset to idle state + // transition to busy state for 2nd and subsequent rdv pulses + // - a single-cycle burst (aka non-burst read) causes no transition to + // busy state. + // b) response startofpacket/endofpacket logic. The response FIFO item + // will have sop asserted, and may have eop asserted. (In the case of + // multiple read bursts transmit in the command fabric in a single packet, + // the eop assertion will come in a later FIFO item.) To support packet + // conservation, and emit a well-formed packet on the response fabric, + // i) response fabric startofpacket is asserted only for the first resp. + // beat; + // ii) response fabric endofpacket is asserted only for the last resp. + // beat. + // c) response address field. The response address field contains an + // incrementing sequence, such that each readdata item is associated with + // its slave-map location. N.b. a) computing the address correctly requires + // knowledge of burstwrap behavior b) there may be no clients of the address + // field, which makes this field a good target for optimization. See + // burst_uncompress_address_counter below. + // d) response byte_cnt field. The response byte_cnt field contains a + // decrementing sequence, such that each beat of the response contains the + // count of bytes to follow. In the case of sub-bursts in a single packet, + // the byte_cnt field may decrement down to num_symbols, then back up to + // some value, multiple times in the packet. + + reg burst_uncompress_busy; + reg [BYTE_CNT_W:0] burst_uncompress_byte_counter; + wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint; + wire first_packet_beat; + wire last_packet_beat; + + assign first_packet_beat = sink_valid & ~burst_uncompress_busy; + assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0]; + + // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to + // the output. + assign source_byte_cnt = + first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint; + assign source_valid = sink_valid; + + // Last packet beat is set throughout receipt of an uncompressed read burst + // from the response FIFO - this forces all the burst uncompression machinery + // idle. + assign last_packet_beat = ~sink_is_compressed | + ( + burst_uncompress_busy ? + (sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) : + sink_valid & (sink_byte_cnt == num_symbols) + ); + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (source_valid & source_ready & sink_valid) begin + // No matter what the current state, last_packet_beat leads to + // idle. + if (last_packet_beat) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (burst_uncompress_busy) begin + burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ? + (burst_uncompress_byte_counter_lint - num_symbols) : + (sink_byte_cnt - num_symbols); + end + else begin // not busy, at least one more beat to go + burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; + // To do: should busy go true for numsymbols-size compressed + // bursts? + burst_uncompress_busy <= 1'b1; + end + end + end + end + end + + reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; + reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; + + wire [63:0] decoded_burstsize_wire; + wire [ADDR_W-1:0] decoded_burstsize; + + + localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W; + wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap; + // The input burstwrap value can be used as a mask against address values, + // but with one caveat: the address width may be (probably is) wider than + // the burstwrap width. The spec says: extend the msb of the burstwrap + // value out over the entire address width (but only if the address width + // actually is wider than the burstwrap width; otherwise it's a 0-width or + // negative range and concatenation multiplier). + generate + if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend + // Sign-extend, just wires: + assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = + {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; + assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0]; + end + else begin + assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap; + end + endgenerate + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_base <= '0; + end + else if (first_packet_beat & source_ready) begin + burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0]; + end + end + + assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits + assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed + + wire [ADDR_W : 0] p1_burst_uncompress_address_offset = + ( + (first_packet_beat ? + sink_addr : + burst_uncompress_address_offset) + decoded_burstsize + ) & + addr_width_burstwrap[ADDR_W-1:0]; + wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0]; + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_offset <= '0; + end + else begin + if (source_ready & source_valid) begin + burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint; + // if (first_packet_beat) begin + // burst_uncompress_address_offset <= + // (sink_addr + num_symbols) & addr_width_burstwrap; + // end + // else begin + // burst_uncompress_address_offset <= + // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; + // end + end + end + end + + // On the first packet beat, send the input address out unchanged, + // while values are computed/registered for 2nd and subsequent beats. + assign source_addr = first_packet_beat ? sink_addr : + burst_uncompress_address_base | burst_uncompress_address_offset; + assign source_burstwrap = sink_burstwrap; + assign source_burstsize = sink_burstsize; + + //------------------------------------------------------------------- + // A single (compressed) read burst will have sop/eop in the same beat. + // A sequence of read sub-bursts emitted by a burst adapter in response to a + // single read burst will have sop on the first sub-burst, eop on the last. + // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve + // packet conservation. + assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; + assign source_endofpacket = sink_endofpacket & last_packet_beat; + assign sink_ready = source_valid & source_ready & last_packet_beat; + + // This is correct for the slave agent usage, but won't always be true in the + // width adapter. To do: add an "please uncompress" input, and use it to + // pass-through or modify, and set source_is_compressed accordingly. + assign source_is_compressed = 1'b0; +endmodule + diff --git a/ip/altera/ddr3/altera_merlin_master_agent.sv b/ip/altera/ddr3/altera_merlin_master_agent.sv new file mode 100644 index 0000000..4b9f4cf --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_master_agent.sv @@ -0,0 +1,303 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Agent +// +// Converts Avalon-MM transactions into +// Merlin network packets. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_agent +#( + // ------------------- + // Packet Format Parameters + // ------------------- + parameter + PKT_QOS_H = 109, + PKT_QOS_L = 106, + PKT_DATA_SIDEBAND_H = 105, + PKT_DATA_SIDEBAND_L = 98, + PKT_ADDR_SIDEBAND_H = 97, + PKT_ADDR_SIDEBAND_L = 93, + PKT_CACHE_H = 92, + PKT_CACHE_L = 89, + PKT_THREAD_ID_H = 88, + PKT_THREAD_ID_L = 87, + PKT_BEGIN_BURST = 81, + PKT_PROTECTION_H = 80, + PKT_PROTECTION_L = 80, + PKT_BURSTWRAP_H = 79, + PKT_BURSTWRAP_L = 77, + PKT_BYTE_CNT_H = 76, + PKT_BYTE_CNT_L = 74, + PKT_ADDR_H = 73, + PKT_ADDR_L = 42, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + PKT_BURST_TYPE_H = 94, + PKT_BURST_TYPE_L = 93, + PKT_TRANS_EXCLUSIVE = 83, + PKT_TRANS_LOCK = 82, + PKT_TRANS_COMPRESSED_READ = 41, + PKT_TRANS_POSTED = 40, + PKT_TRANS_WRITE = 39, + PKT_TRANS_READ = 38, + PKT_DATA_H = 37, + PKT_DATA_L = 6, + PKT_BYTEEN_H = 5, + PKT_BYTEEN_L = 2, + PKT_SRC_ID_H = 1, + PKT_SRC_ID_L = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + PKT_RESPONSE_STATUS_L = 110, + PKT_RESPONSE_STATUS_H = 111, + PKT_ORI_BURST_SIZE_L = 112, + PKT_ORI_BURST_SIZE_H = 114, + ST_DATA_W = 115, + ST_CHANNEL_W = 1, + + // ------------------- + // Agent Parameters + // ------------------- + AV_BURSTCOUNT_W = 3, + ID = 1, + SUPPRESS_0_BYTEEN_RSP = 1, + BURSTWRAP_VALUE = 4, + CACHE_VALUE = 0, + SECURE_ACCESS_BIT = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + // ------------------- + // Derived Parameters + // ------------------- + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, + PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1, + PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1 +) ( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Avalon-MM Anti-Master + // ------------------- + input [PKT_ADDR_W-1 : 0] av_address, + input av_write, + input av_read, + input [PKT_DATA_W-1 : 0] av_writedata, + output reg [PKT_DATA_W-1 : 0] av_readdata, + output reg av_waitrequest, + output reg av_readdatavalid, + input [PKT_BYTEEN_W-1 : 0] av_byteenable, + input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, + input av_debugaccess, + input av_lock, + output reg [1 : 0] av_response, + output reg av_writeresponsevalid, + + // ------------------- + // Command Source + // ------------------- + output reg cp_valid, + output reg [ST_DATA_W-1 : 0] cp_data, + output wire cp_startofpacket, + output wire cp_endofpacket, + input cp_ready, + + // ------------------- + // Response Sink + // ------------------- + input rp_valid, + input [ST_DATA_W-1 : 0] rp_data, + input [ST_CHANNEL_W-1 : 0] rp_channel, + input rp_startofpacket, + input rp_endofpacket, + output reg rp_ready +); + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + function integer clogb2; + input [31 : 0] value; + begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); + localparam NUMSYMBOLS = PKT_BYTEEN_W; + localparam BURSTING = (MAX_BURST > NUMSYMBOLS); + localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); + localparam BURST_SIZE = clogb2(NUMSYMBOLS); + + typedef enum bit [1 : 0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + OTHER_WRAP = 2'b11 + } MerlinBurstType; + + // -------------------------------------- + // Potential optimization: compare in words to save bits? + // -------------------------------------- + wire is_burst; + assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); + + wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE; + wire [31 : 0] id_int = ID; + wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0]; + wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; + + // -------------------------------------- + // Address alignment + // + // The packet format requires that addresses be aligned to + // the transaction size. + // -------------------------------------- + wire [PKT_ADDR_W-1 : 0] av_address_aligned; + generate + if (NUMSYMBOLS > 1) begin + assign av_address_aligned = + {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; + end + else begin + assign av_address_aligned = av_address; + end + endgenerate + + // -------------------------------------- + // Command & Response Construction + // -------------------------------------- + always_comb begin + cp_data = '0; + + cp_data[PKT_PROTECTION_L] = av_debugaccess; + cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit + cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit + cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0]; + cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount; + cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned; + cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0; + cp_data[PKT_TRANS_LOCK] = av_lock; + cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst; + cp_data[PKT_TRANS_READ] = av_read; + cp_data[PKT_TRANS_WRITE] = av_write; + cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE; + cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata; + cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable; + cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig; + cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig; + cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value; + cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0]; + cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0; + cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0]; + cp_data[PKT_QOS_H : PKT_QOS_L] = '0; + cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0; + cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0; + + av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; + if (USE_WRITERESPONSE || USE_READRESPONSE) + av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; + else + av_response = '0; + end + + // -------------------------------------- + // Command Control + // -------------------------------------- + always_comb begin + cp_valid = 0; + + if (av_write || av_read) + cp_valid = 1; + end + + generate if (BURSTING) begin + reg sop_enable; + + always @(posedge clk, posedge reset) begin + if (reset) begin + sop_enable <= 1'b1; + end + else begin + if (cp_valid && cp_ready) begin + sop_enable <= 1'b0; + if (cp_endofpacket) + sop_enable <= 1'b1; + end + end + end + + assign cp_startofpacket = sop_enable; + assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); + + end + else begin + + assign cp_startofpacket = 1'b1; + assign cp_endofpacket = 1'b1; + + end + endgenerate + + // -------------------------------------- + // Backpressure & Readdatavalid + // -------------------------------------- + reg hold_waitrequest; + + always @ (posedge clk, posedge reset) begin + if (reset) + hold_waitrequest <= 1'b1; + else + hold_waitrequest <= 1'b0; + end + + always_comb begin + rp_ready = 1; + av_readdatavalid = 0; + av_writeresponsevalid = 0; + av_waitrequest = hold_waitrequest | !cp_ready; + + if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1)) + av_writeresponsevalid = rp_valid; + else + av_readdatavalid = rp_valid; + + if (SUPPRESS_0_BYTEEN_RSP) begin + if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0) + av_readdatavalid = 0; + end + end + +endmodule diff --git a/ip/altera/ddr3/altera_merlin_master_translator.sv b/ip/altera/ddr3/altera_merlin_master_translator.sv new file mode 100644 index 0000000..8d5f320 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_master_translator.sv @@ -0,0 +1,556 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Translator +// +// Converts an Avalon-MM master interface into an +// Avalon-MM "universal" master interface. +// +// The universal interface is defined as the superset of ports +// and parameters that can represent any legal Avalon +// interface. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_translator #( + parameter + // widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + + // optional ports + USE_BURSTCOUNT = 1, + USE_BEGINBURSTTRANSFER = 0, + USE_BEGINTRANSFER = 0, + USE_CHIPSELECT = 0, + USE_READ = 1, + USE_READDATAVALID = 1, + USE_WRITE = 1, + USE_WAITREQUEST = 1, + USE_WRITERESPONSE = 0, + USE_READRESPONSE = 0, + + AV_REGISTERINCOMINGSIGNALS = 0, + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + // must be enabled for a bursting master + AV_CONSTANT_BURST_BEHAVIOR = 1, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + AV_LINEWRAPBURSTS = 0 +)( + input wire clk, + input wire reset, + + // Universal Avalon Master + output reg uav_write, + output reg uav_read, + output reg [UAV_ADDRESS_W -1 : 0] uav_address, + output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, + output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, + output wire [AV_DATA_W -1 : 0] uav_writedata, + output wire uav_lock, + output wire uav_debugaccess, + output wire uav_clken, + + input wire [AV_DATA_W -1 : 0] uav_readdata, + input wire uav_readdatavalid, + input wire uav_waitrequest, + input wire [1 : 0] uav_response, + input wire uav_writeresponsevalid, + + // Avalon-MM Anti-master (slave) + input reg av_write, + input reg av_read, + input wire [AV_ADDRESS_W -1 : 0] av_address, + input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, + input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, + input wire [AV_DATA_W -1 : 0] av_writedata, + input wire av_begintransfer, + input wire av_beginbursttransfer, + input wire av_lock, + input wire av_chipselect, + input wire av_debugaccess, + input wire av_clken, + + output wire [AV_DATA_W -1 : 0] av_readdata, + output wire av_readdatavalid, + output reg av_waitrequest, + output reg [1 : 0] av_response, + output reg av_writeresponsevalid +); + + localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD); + localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD)); + localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0; + localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1; + localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1; + + localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD; + localparam BITS_PER_WORD_ADDRESS = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD; + + localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; + localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; + + localparam ADDRESS_HIGH = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW); + localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW); + + function integer flog2; + input [31:0] depth; + integer i; + begin + i = depth; + if ( i <= 0 ) flog2 = 0; + else begin + for (flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + endfunction // flog2 + + // ------------------------------------------------------------ + // Calculates the ceil(log2()) of the input val. + // + // Limited to a positive 32-bit input value. + // ------------------------------------------------------------ + function integer clog2; + input[31:0] val; + reg[31:0] i; + + begin + i = 1; + clog2 = 0; + + while (i < val) begin + clog2 = clog2 + 1; + i = i[30:0] << 1; + end + end + endfunction + + function integer pow2; + input [31:0] toShift; + begin + pow2 = 1; + pow2 = pow2 << toShift; + end + endfunction // pow2 + + // ------------------------------------------------- + // Assign some constants to appropriately-sized signals to + // avoid synthesis warnings. This also helps some simulators + // with their inferred sensitivity lists. + // + // The symbols per word calculation here rounds non-power of two + // symbols to the next highest power of two, which is what we want + // when calculating the decrementing byte count. + // ------------------------------------------------- + wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0])); + wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0]; + + reg internal_beginbursttransfer; + reg internal_begintransfer; + reg [UAV_ADDRESS_W -1 : 0] uav_address_pre; + reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount_pre; + + reg uav_read_pre; + reg uav_write_pre; + reg read_accepted; + + // ------------------------------------------------- + // Pass through signals that we don't touch + // ------------------------------------------------- + assign uav_writedata = av_writedata; + assign uav_byteenable = av_byteenable; + assign uav_lock = av_lock; + assign uav_debugaccess = av_debugaccess; + assign uav_clken = av_clken; + + assign av_readdata = uav_readdata; + assign av_readdatavalid = uav_readdatavalid; + + // ------------------------------------------------- + // Response signals + // ------------------------------------------------- + always_comb begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) + av_response = '0; + else + av_response = uav_response; + + if (USE_WRITERESPONSE) begin + av_writeresponsevalid = uav_writeresponsevalid; + end else begin + av_writeresponsevalid = '0; + end + end + + // ------------------------------------------------- + // Convert byte and word addresses into byte addresses + // ------------------------------------------------- + always_comb begin + uav_address_pre = {UAV_ADDRESS_W{1'b0}}; + + if (AV_ADDRESS_SYMBOLS) + uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0]; + else begin + uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0]; + end + end + + // ------------------------------------------------- + // Convert burstcount into symbol units + // ------------------------------------------------- + always_comb begin + uav_burstcount_pre = symbols_per_word; // default to a single transfer + + if (USE_BURSTCOUNT) begin + uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}}; + if (AV_BURSTCOUNT_SYMBOLS) + uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0]; + else begin + uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0]; + end + end + end + + // ------------------------------------------------- + // This is where we perform the per-transfer address and burstcount + // calculations that are required by downstream modules. + // ------------------------------------------------- + reg [UAV_ADDRESS_W -1 : 0] address_register; + wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register; + reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint; + + assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0]; + + always_comb begin + uav_address = uav_address_pre; + uav_burstcount = uav_burstcount_pre; + + if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin + uav_address = address_register; + uav_burstcount = burstcount_register; + end + end + + reg first_burst_stalled; + reg burst_stalled; + + wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg; + wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg; + + generate + if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin + if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + end + else begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + end + end + else begin + assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0]; + assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0]; + end + endgenerate + + always @(posedge clk, posedge reset) begin + if (reset) begin + address_register <= '0; + burstcount_register_lint <= '0; + end else begin + address_register <= address_register; + burstcount_register_lint <= burstcount_register_lint; + + if (internal_beginbursttransfer || first_burst_stalled) begin + if (av_waitrequest) begin + address_register <= uav_address_pre; + burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre; + end else begin + address_register <= combi_burst_addr_reg; + burstcount_register_lint <= uav_burstcount_pre - symbols_per_word; + end + end else if (internal_begintransfer || burst_stalled) begin + if (~av_waitrequest) begin + address_register <= combi_addr_reg; + burstcount_register_lint <= burstcount_register - symbols_per_word; + end + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + first_burst_stalled <= 1'b0; + burst_stalled <= 1'b0; + end else begin + if (internal_beginbursttransfer || first_burst_stalled) begin + if (av_waitrequest) begin + first_burst_stalled <= 1'b1; + end else begin + first_burst_stalled <= 1'b0; + end + end else if (internal_begintransfer || burst_stalled) begin + if (~av_waitrequest) begin + burst_stalled <= 1'b0; + end else begin + burst_stalled <= 1'b1; + end + end + end + end + + // ------------------------------------------------- + // Waitrequest translation + // ------------------------------------------------- + always @(posedge clk, posedge reset) begin + if (reset) + read_accepted <= 1'b0; + else begin + read_accepted <= read_accepted; + if (read_accepted == 0) + read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; + else if (read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives + read_accepted <= 1'b0; + end + + end + + reg write_accepted = 0; + generate if (AV_REGISTERINCOMINGSIGNALS) begin + always @(posedge clk, posedge reset) begin + if (reset) + write_accepted <= 1'b0; + else begin + write_accepted <= + ~av_waitrequest ? 1'b0 : + uav_write & ~uav_waitrequest? 1'b1 : + write_accepted; + end + end + end endgenerate + + always_comb begin + av_waitrequest = uav_waitrequest; + + if (USE_READDATAVALID == 0) begin + av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; + end + + if (AV_REGISTERINCOMINGSIGNALS) begin + av_waitrequest = + uav_read_pre ? ~uav_readdatavalid : + uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : + 1'b1; + end + + if (USE_WAITREQUEST == 0) begin + av_waitrequest = 0; + end + end + + // ------------------------------------------------- + // Determine the output read and write signals from + // the read/write/chipselect input signals. + // ------------------------------------------------- + always_comb begin + uav_write = 1'b0; + uav_write_pre = 1'b0; + uav_read = 1'b0; + uav_read_pre = 1'b0; + + if (!USE_CHIPSELECT) begin + if (USE_READ) begin + uav_read_pre = av_read; + end + + if (USE_WRITE) begin + uav_write_pre = av_write; + end + end else begin + if (!USE_WRITE && USE_READ) begin + uav_write_pre = av_chipselect & ~av_read; + uav_read_pre = av_read; + end else if (!USE_READ && USE_WRITE) begin + uav_write_pre = av_write; + uav_read_pre = av_chipselect & ~av_write; + end else if (USE_READ && USE_WRITE) begin + uav_write_pre = av_write; + uav_read_pre = av_read; + end + end + + if (USE_READDATAVALID == 0) + uav_read = uav_read_pre & ~read_accepted; + else + uav_read = uav_read_pre; + + if (AV_REGISTERINCOMINGSIGNALS == 0) + uav_write = uav_write_pre; + else + uav_write = uav_write_pre & ~write_accepted; + end + + // ------------------------------------------------- + // Begintransfer assignment + // ------------------------------------------------- + reg end_begintransfer; + + always_comb begin + if (USE_BEGINTRANSFER) begin + internal_begintransfer = av_begintransfer; + end else begin + internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + end_begintransfer <= 1'b0; + end else begin + if (internal_begintransfer == 1 && uav_waitrequest) + end_begintransfer <= 1'b1; + else if (uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + end + end + + // ------------------------------------------------- + // Beginbursttransfer assignment + // ------------------------------------------------- + reg end_beginbursttransfer; + wire last_burst_transfer_pre; + wire last_burst_transfer_reg; + wire last_burst_transfer; + + // compare values before the mux to shorten critical path; benchmark before changing + assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); + assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); + assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; + + always_comb begin + if (USE_BEGINBURSTTRANSFER) begin + internal_beginbursttransfer = av_beginbursttransfer; + end else begin + internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + end_beginbursttransfer <= 1'b0; + end else begin + end_beginbursttransfer <= end_beginbursttransfer; + if (last_burst_transfer && internal_begintransfer || uav_read) begin + end_beginbursttransfer <= 1'b0; + end + else if (uav_write && internal_begintransfer) begin + end_beginbursttransfer <= 1'b1; + end + end + end + + // synthesis translate_off + + // ------------------------------------------------ + // check_1 : for waitrequest signal violation + // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls + // Exception : begintransfer / beginbursttransfer + // : previously not in any transaction (idle) + // Note : Not checking clken which is not exactly part of Avalon controls/inputs + // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE + // ------------------------------------------------ + + reg av_waitrequest_r; + reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r; + reg [AV_ADDRESS_W-1:0] av_address_r; + reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; + reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; + reg [AV_DATA_W-1:0] av_writedata_r; + + always @(posedge clk or posedge reset) begin + if (reset) begin + av_waitrequest_r <= '0; + av_write_r <= '0; + av_read_r <= '0; + av_lock_r <= '0; + av_chipselect_r <= '0; + av_debugaccess_r <= '0; + av_address_r <= '0; + av_byteenable_r <= '0; + av_burstcount_r <= '0; + av_writedata_r <= '0; + end else begin + av_waitrequest_r <= av_waitrequest; + av_write_r <= av_write; + av_read_r <= av_read; + av_lock_r <= av_lock; + av_chipselect_r <= av_chipselect; + av_debugaccess_r <= av_debugaccess; + av_address_r <= av_address; + av_byteenable_r <= av_byteenable; + av_burstcount_r <= av_burstcount; + av_writedata_r <= av_writedata; + + if ( + av_waitrequest_r && // When waitrequest is asserted + ( + (av_write != av_write_r) || // Checks that : Input controls/data does not change + (av_read != av_read_r) || + (av_lock != av_lock_r) || + (av_debugaccess != av_debugaccess_r) || + (av_address != av_address_r) || + (av_byteenable != av_byteenable_r) || + (av_burstcount != av_burstcount_r) + ) && + (av_write_r | av_read_r) && // Check only when : previously initiated a write/read + (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) + ) begin + $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time()); + $display("av_address %x --> %x", av_address_r , av_address ); + $display("av_byteenable %x --> %x", av_byteenable_r , av_byteenable ); + $display("av_burstcount %x --> %x", av_burstcount_r , av_burstcount ); + $display("av_writedata %x --> %x", av_writedata_r , av_writedata ); + $display("av_write %x --> %x", av_write_r , av_write ); + $display("av_read %x --> %x", av_read_r , av_read ); + $display("av_lock %x --> %x", av_lock_r , av_lock ); + $display("av_chipselect %x --> %x", av_chipselect_r , av_chipselect ); + $display("av_debugaccess %x --> %x", av_debugaccess_r , av_debugaccess ); + end + end + + // end check_1 + + end + + // synthesis translate_on + + +endmodule diff --git a/ip/altera/ddr3/altera_merlin_reorder_memory.sv b/ip/altera/ddr3/altera_merlin_reorder_memory.sv new file mode 100644 index 0000000..b82a957 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_reorder_memory.sv @@ -0,0 +1,297 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_reorder_memory.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------------------ +// Merlin Order Memory: this stores responses from slave +// and do reorder. The memory structure is normal memory +// with many segments for different responses that master +// can handle. +// The number of segment is the number of MAX_OUTSTANDING_RESPONSE +// ------------------------------------------------------------------ + +`timescale 1 ns / 1 ns +module altera_merlin_reorder_memory +#( + parameter DATA_W = 32, + ADDR_H_W = 4, // width to represent how many segments + ADDR_L_W = 4, + VALID_W = 4, + NUM_SEGMENT = 4, + DEPTH = 16 + +) + +( + // ------------------- + // Clock + // ------------------- + input clk, + input reset, + // ------------------- + // Signals + // ------------------- + input [DATA_W - 1 : 0] in_data, + input in_valid, + output in_ready, + + output reg [DATA_W - 1 : 0] out_data, + output reg out_valid, + input out_ready, + // -------------------------------------------- + // wr_segment: select write portion of memory + // rd_segment: select read portion of memory + // -------------------------------------------- + input [ADDR_H_W - 1 : 0] wr_segment, + input [ADDR_H_W - 1 : 0] rd_segment + +); + + // ------------------------------------- + // Local parameter + // ------------------------------------- + localparam SEGMENT_W = ADDR_H_W; + + wire [ADDR_H_W + ADDR_L_W - 1 : 0] mem_wr_addr; + reg [ADDR_H_W + ADDR_L_W - 1 : 0] mem_rd_addr; + wire [ADDR_L_W - 1 : 0] mem_wr_ptr; + wire [ADDR_L_W - 1 : 0] mem_rd_ptr; + reg [ADDR_L_W - 1 : 0] mem_next_rd_ptr; + reg [DATA_W - 1 : 0] out_payload; + + wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_ready; + wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_valid; + wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_valid; + wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_ready; + wire [ADDR_L_W - 1 : 0] pointer_ctrl_wr_ptr [NUM_SEGMENT]; + wire [ADDR_L_W - 1 : 0] pointer_ctrl_rd_ptr [NUM_SEGMENT]; + wire [ADDR_L_W - 1 : 0] pointer_ctrl_next_rd_ptr [NUM_SEGMENT]; + + // --------------------------------- + // Memory storage + // --------------------------------- + (* ramstyle="no_rw_check" *) reg [DATA_W - 1 : 0] mem [DEPTH - 1 : 0]; + always @(posedge clk) begin + if (in_valid && in_ready) + mem[mem_wr_addr] = in_data; + out_payload = mem[mem_rd_addr]; + end + //assign mem_rd_addr = {rd_segment, mem_next_rd_ptr}; + + always_comb + begin + out_data = out_payload; + out_valid = pointer_ctrl_out_valid[rd_segment]; + end + // --------------------------------- + // Memory addresses + // --------------------------------- + assign mem_wr_ptr = pointer_ctrl_wr_ptr[wr_segment]; + //assign mem_rd_ptr = pointer_ctrl_rd_ptr[rd_segment]; + //assign mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment]; + + assign mem_wr_addr = {wr_segment, mem_wr_ptr}; + + // --------------------------------------------------------------------------- + // Bcos want, empty latency, mean assert read the data will appear on out_data. + // And need to jump around different segment of the memory. + // So when seeing endofpacket for this current segment, the read address + // will jump to next segment at first read address, so that the data will be ready + // it is okay to jump to next segment as this is the sequence of all transaction + // and they just increment. (standing at segment 0, then for sure next segment 1) + // ---------------------------------------------------------------------------- + wire endofpacket; + assign endofpacket = out_payload[0]; + wire [ADDR_H_W - 1: 0] next_rd_segment; + assign next_rd_segment = ((rd_segment + 1'b1) == NUM_SEGMENT) ? '0 : rd_segment + 1'b1; + + always_comb + begin + if (out_valid && out_ready && endofpacket) + begin + mem_next_rd_ptr = pointer_ctrl_rd_ptr[next_rd_segment]; + //mem_rd_addr = {rd_segment + 1'b1, mem_next_rd_ptr}; + mem_rd_addr = {next_rd_segment, mem_next_rd_ptr}; + + end + else + begin + mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment]; + mem_rd_addr = {rd_segment, mem_next_rd_ptr}; + end + end + + + // --------------------------------- + // Output signals + // --------------------------------- + assign in_ready = pointer_ctrl_in_ready[wr_segment]; + + // --------------------------------- + // Control signals for each segment + // --------------------------------- + genvar j; + generate + for (j = 0; j < NUM_SEGMENT; j = j + 1) + begin : pointer_signal + assign pointer_ctrl_in_valid[j] = (wr_segment == j) && in_valid; + assign pointer_ctrl_out_ready[j] = (rd_segment == j) && out_ready; + + end + endgenerate + + // --------------------------------- + // Seperate write and read pointer + // for each segment in memory + // --------------------------------- + genvar i; + generate + for (i = 0; i < NUM_SEGMENT; i = i + 1) + begin : each_segment_pointer_controller + memory_pointer_controller + #( + .ADDR_W (ADDR_L_W) + ) reorder_memory_pointer_controller + ( + .clk (clk), + .reset (reset), + .in_ready (pointer_ctrl_in_ready[i]), + .in_valid (pointer_ctrl_in_valid[i]), + .out_ready (pointer_ctrl_out_ready[i]), + .out_valid (pointer_ctrl_out_valid[i]), + .wr_pointer (pointer_ctrl_wr_ptr[i]), + .rd_pointer (pointer_ctrl_rd_ptr[i]), + .next_rd_pointer (pointer_ctrl_next_rd_ptr[i]) + ); + end // block: each_segment_pointer_controller + endgenerate +endmodule + + +module memory_pointer_controller +#( + parameter ADDR_W = 4 +) +( + // ------------------- + // Clock + // ------------------- + input clk, + input reset, + // ------------------- + // Signals + // ------------------- + output reg in_ready, + input in_valid, + input out_ready, + output reg out_valid, + // ------------------------------- + // Output write and read pointer + // ------------------------------- + output [ADDR_W - 1 : 0] wr_pointer, + output [ADDR_W - 1 : 0] rd_pointer, + output [ADDR_W - 1 : 0] next_rd_pointer +); + + reg [ADDR_W - 1 : 0] incremented_wr_ptr; + reg [ADDR_W - 1 : 0] incremented_rd_ptr; + reg [ADDR_W - 1 : 0] wr_ptr; + reg [ADDR_W - 1 : 0] rd_ptr; + reg [ADDR_W - 1 : 0] next_wr_ptr; + reg [ADDR_W - 1 : 0] next_rd_ptr; + reg full, empty, next_full, next_empty; + reg read, write, internal_out_ready, internal_out_valid; + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = read ? incremented_rd_ptr : rd_ptr; + assign wr_pointer = wr_ptr; + assign rd_pointer = rd_ptr; + assign next_rd_pointer = next_rd_ptr; + + // ------------------------------- + // Define write and read signals + // -------------------------------- + // internal read, if it has any valid data + // and output are ready to accepts data then a read will be performed. + // ------------------------------- + //assign read = internal_out_ready && internal_out_valid; + assign read = internal_out_ready && !empty; + assign write = in_ready && in_valid; + + always_ff @(posedge clk or posedge reset) + begin + if (reset) + begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else + begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + // --------------------------------------------------------------------------- + // Generate full/empty signal for memory + // if read and next read pointer same as write, set empty, write will clear empty + // if write and next write pointer same as read, set full, read will clear full + // ----------------------------------------------------------------------------- + always_comb + begin + next_full = full; + next_empty = empty; + if (read && !write) + begin + next_full = 1'b0; + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + if (write && !read) + begin + next_empty = 1'b0; + if (incremented_wr_ptr == rd_ptr) + next_full = 1'b1; + end + end // always_comb + + always_ff @(posedge clk or posedge reset) + begin + if (reset) + begin + empty <= 1; + full <= 0; + end + else + begin + empty <= next_empty; + full <= next_full; + end + end + + // -------------------- + // Control signals + // -------------------- + always_comb + begin + in_ready = !full; + out_valid = !empty; + internal_out_ready = out_ready; + end // always_comb +endmodule + diff --git a/ip/altera/ddr3/altera_merlin_slave_agent.sv b/ip/altera/ddr3/altera_merlin_slave_agent.sv new file mode 100644 index 0000000..7100ab7 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_slave_agent.sv @@ -0,0 +1,622 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2011 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_agent +#( + // Packet parameters + parameter PKT_BEGIN_BURST = 81, + parameter PKT_DATA_H = 31, + parameter PKT_DATA_L = 0, + parameter PKT_SYMBOL_W = 8, + parameter PKT_BYTEEN_H = 71, + parameter PKT_BYTEEN_L = 68, + parameter PKT_ADDR_H = 63, + parameter PKT_ADDR_L = 32, + parameter PKT_TRANS_LOCK = 87, + parameter PKT_TRANS_COMPRESSED_READ = 67, + parameter PKT_TRANS_POSTED = 66, + parameter PKT_TRANS_WRITE = 65, + parameter PKT_TRANS_READ = 64, + parameter PKT_SRC_ID_H = 74, + parameter PKT_SRC_ID_L = 72, + parameter PKT_DEST_ID_H = 77, + parameter PKT_DEST_ID_L = 75, + parameter PKT_BURSTWRAP_H = 85, + parameter PKT_BURSTWRAP_L = 82, + parameter PKT_BYTE_CNT_H = 81, + parameter PKT_BYTE_CNT_L = 78, + parameter PKT_PROTECTION_H = 86, + parameter PKT_PROTECTION_L = 86, + parameter PKT_RESPONSE_STATUS_H = 89, + parameter PKT_RESPONSE_STATUS_L = 88, + parameter PKT_BURST_SIZE_H = 92, + parameter PKT_BURST_SIZE_L = 90, + parameter PKT_ORI_BURST_SIZE_L = 93, + parameter PKT_ORI_BURST_SIZE_H = 95, + parameter ST_DATA_W = 96, + parameter ST_CHANNEL_W = 32, + + // Slave parameters + parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + parameter AVS_BURSTCOUNT_W = 4, + parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, + + // Slave agent parameters + parameter PREVENT_FIFO_OVERFLOW = 0, + parameter SUPPRESS_0_BYTEEN_CMD = 1, + parameter USE_READRESPONSE = 0, + parameter USE_WRITERESPONSE = 0, + + // Derived slave parameters + parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + parameter BURST_SIZE_W = 3, + + // Derived FIFO width + parameter FIFO_DATA_W = ST_DATA_W + 1, + + // ECC parameter + parameter ECC_ENABLE = 0 +) ( + input clk, + input reset, + + // Universal-Avalon anti-slave + output [ADDR_W-1:0] m0_address, + output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, + output [AVS_BE_W-1:0] m0_byteenable, + output m0_read, + input [AVS_DATA_W-1:0] m0_readdata, + input m0_waitrequest, + output m0_write, + output [AVS_DATA_W-1:0] m0_writedata, + input m0_readdatavalid, + output m0_debugaccess, + output m0_lock, + input [1:0] m0_response, + input m0_writeresponsevalid, + + // Avalon-ST FIFO interfaces. + // Note: there's no need to include the "data" field here, at least for + // reads, since readdata is filled in from slave info. To keep life + // simple, have a data field, but fill it with 0s. + // Av-st response fifo source interface + output reg [FIFO_DATA_W-1:0] rf_source_data, + output rf_source_valid, + output rf_source_startofpacket, + output rf_source_endofpacket, + input rf_source_ready, + + // Av-st response fifo sink interface + input [FIFO_DATA_W-1:0] rf_sink_data, + input rf_sink_valid, + input rf_sink_startofpacket, + input rf_sink_endofpacket, + output rf_sink_ready, + + // Av-st readdata fifo src interface, data and response + // extra 2 bits for storing RESPONSE STATUS + output [AVS_DATA_W+1:0] rdata_fifo_src_data, + output rdata_fifo_src_valid, + input rdata_fifo_src_ready, + + // Av-st readdata fifo sink interface + input [AVS_DATA_W+1:0] rdata_fifo_sink_data, + input rdata_fifo_sink_valid, + output rdata_fifo_sink_ready, + input rdata_fifo_sink_error, + + // Av-st sink command packet interface + output cp_ready, + input cp_valid, + input [ST_DATA_W-1:0] cp_data, + input [ST_CHANNEL_W-1:0] cp_channel, + input cp_startofpacket, + input cp_endofpacket, + + // Av-st source response packet interface + input rp_ready, + output reg rp_valid, + output reg [ST_DATA_W-1:0] rp_data, + output rp_startofpacket, + output rp_endofpacket +); + + // -------------------------------------------------- + // Ceil(log2()) function log2ceil of 4 = 2 + // -------------------------------------------------- + function integer log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + // ------------------------------------------------ + // Local Parameters + // ------------------------------------------------ + localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; + localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; + localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; + localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; + localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); + localparam MAX_BURST = 1 << (AVS_BURSTCOUNT_W - 1); + localparam BURSTING = (MAX_BURST > PKT_SYMBOLS); + + // ------------------------------------------------ + // Signals + // ------------------------------------------------ + wire [DATA_W-1:0] cmd_data; + wire [BE_W-1:0] cmd_byteen; + wire [ADDR_W-1:0] cmd_addr; + wire [MID_W-1:0] cmd_mid; + wire [SID_W-1:0] cmd_sid; + wire cmd_read; + wire cmd_write; + wire cmd_compressed; + wire cmd_posted; + wire [BYTE_CNT_W-1:0] cmd_byte_cnt; + wire [BURSTWRAP_W-1:0] cmd_burstwrap; + wire [BURSTSIZE_W-1:0] cmd_burstsize; + wire cmd_debugaccess; + + wire suppress_cmd; + wire byteen_asserted; + wire suppress_read; + wire suppress_write; + wire needs_response_synthesis; + wire generate_response; + + // Assign command fields + assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; + assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; + assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; + assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; + assign cmd_posted = cp_data[PKT_TRANS_POSTED]; + assign cmd_write = cp_data[PKT_TRANS_WRITE]; + assign cmd_read = cp_data[PKT_TRANS_READ]; + assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; + assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; + + // Local "ready_for_command" signal: deasserted when the agent is unable to accept + // another command, e.g. rdv FIFO is full, (local readdata storage is full && + // ~rp_ready), ... + // Say, this could depend on the type of command, for example, even if the + // rdv FIFO is full, a write request can be accepted. For later. + wire ready_for_command; + + wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; + wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; + wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; + wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; + wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + generate + if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block + // --------------------------------------------------- + // Backpressure if the slave says to, or if FIFO overflow may occur. + // + // All commands are backpressured once the FIFO is full + // even if they don't need storage. This breaks a long + // combinatorial path from the master read/write through + // this logic and back to the master via the backpressure + // path. + // + // To avoid a loss of throughput the FIFO will be parameterized + // one slot deeper. The extra slot should never be used in normal + // operation, but should a slave misbehave and accept one more + // read than it should then backpressure will kick in. + // + // An example: assume a slave with MPRT = 2. It can accept a + // command sequence RRWW without backpressuring. If the FIFO is + // only 2 deep, we'd backpressure the writes leading to loss of + // throughput. If the FIFO is 3 deep, we'll only backpressure when + // RRR... which is an illegal condition anyway. + // --------------------------------------------------- + + assign ready_for_command = rf_source_ready; + assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command; + + end else begin : no_prevent_fifo_overflow_block + + // Do not suppress the command or the slave will + // not be able to waitrequest + assign ready_for_command = 1'b1; + // Backpressure only if the slave says to. + assign cp_ready = ~m0_waitrequest | suppress_cmd; + + end + endgenerate + + generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting + assign byteen_asserted = |cmd_byteen; + assign suppress_read = ~byteen_asserted; + assign suppress_write = ~byteen_asserted; + assign suppress_cmd = ~byteen_asserted; + end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting + assign byteen_asserted = |cmd_byteen; + assign suppress_read = ~byteen_asserted; + assign suppress_write = 1'b0; + assign suppress_cmd = ~byteen_asserted && cmd_read; + end else begin : no_suppress_0_byteen_cmd + assign suppress_read = 1'b0; + assign suppress_write = 1'b0; + assign suppress_cmd = 1'b0; + end + endgenerate + + // ------------------------------------------------------------------- + // Extract avalon signals from command packet. + // ------------------------------------------------------------------- + // Mask off the lower bits of address. + // The burst adapter before this component will break narrow sized packets + // into sub-bursts of length 1. However, the packet addresses are preserved, + // which means this component may see size-aligned addresses. + // + // Masking ensures that the addresses seen by an Avalon slave are aligned to + // the full data width instead of the size. + // + // Example: + // output from burst adapter (datawidth=4, size=2 bytes): + // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 + // expected output from slave agent: + // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 + generate + if (BITS_TO_MASK > 0) begin : mask_address + + assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; + + end else begin : no_mask_address + + assign m0_address = cmd_addr; + + end + endgenerate + + assign m0_byteenable = cmd_byteen; + assign m0_writedata = cmd_data; + + // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - + // this sort of burst exists only in merlin fabric ST packets. What to do + // if we see such a burst? All beats in that burst need to be transmitted + // to the slave so we have enough space-time for byteenable expression. + // + // There can be multiple bursts in a packet, but only one beat per burst + // in cases. The exception is when we've decided not to insert a + // burst adapter for efficiency reasons, in which case this agent is also + // responsible for driving burstcount to 1 on each beat of an uncompressed + // read burst. + + assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read); + + generate + // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount + // from a sub-range, or 0-pad, as appropriate. + if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad + wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; + assign m0_burstcount = (local_read & ~local_compressed_read) ? + {zero_pad, num_symbols} : + {zero_pad, cmd_byte_cnt}; + end + else begin : m0_burstcount_no_pad + assign m0_burstcount = (local_read & ~local_compressed_read) ? + num_symbols[AVS_BURSTCOUNT_W-1:0] : + cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; + end + endgenerate + + assign m0_write = ready_for_command & local_write & !suppress_write; + assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); + assign m0_debugaccess = cmd_debugaccess; + + // ------------------------------------------------------------------- + // Indirection layer for response packet values. Some may always wire + // directly from the slave translator; others will no doubt emerge from + // various FIFOs. + // What to put in resp_data when a write occured? Answer: it does not + // matter, because only response status is needed for non-posted writes, + // and the packet already has a field for that. + // + // We use the rdata_fifo to store write responses as well. This allows us + // to handle backpressure on the response path, and allows write response + // merging. + assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; + assign rdata_fifo_src_data = {m0_response, m0_readdata}; + + // ------------------------------------------------------------------ + // Generate a token when read commands are suppressed. The token + // is stored in the response FIFO, and will be used to synthesize + // a read response. The same token is used for non-posted write + // response synthesis. + // + // Note: this token is not generated for suppressed uncompressed read cycles; + // the burst uncompression logic at the read side of the response FIFO + // generates the correct number of responses. + // + // When the slave can return the response, let it do its job. Don't + // synthesize a response in that case, unless we've suppressed the + // the last transfer in a write sub-burst. + // ------------------------------------------------------------------ + wire write_end_of_subburst; + assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) || + (!USE_WRITERESPONSE && nonposted_write_endofpacket) || + (USE_WRITERESPONSE && write_end_of_subburst && suppress_write); + + // Avalon-ST interfaces to external response FIFO. + // + // For efficiency, when synthesizing a write response we only store a non-posted write + // transaction at its endofpacket, even if it was split into multiple sub-bursts. + // + // When not synthesizing write responses, we store each sub-burst in the FIFO. + // Each sub-burst to the slave will return a response, which corresponds to one + // entry in the FIFO. We merge all the sub-burst responses on the final + // sub-burst and send it on the response channel. + + wire internal_cp_endofburst; + wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning + wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; + + assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; + assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); + assign write_end_of_subburst = local_write & internal_cp_endofburst; + + assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write)) + & ready_for_command & cp_ready; + assign rf_source_startofpacket = cp_startofpacket; + assign rf_source_endofpacket = cp_endofpacket; + always @* begin + // default: assign every command packet field to the response FIFO... + rf_source_data = {1'b0, cp_data}; + + // ... and override select fields as needed. + rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; + rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; + rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; + rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; + rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; + rf_source_data[PKT_TRANS_POSTED] = cmd_posted; + rf_source_data[PKT_TRANS_WRITE] = cmd_write; + rf_source_data[PKT_TRANS_READ] = cmd_read; + rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; + rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; + rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; + rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; + rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; + rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; + rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; + end + + wire uncompressor_source_valid; + wire [BURSTSIZE_W-1:0] uncompressor_burstsize; + wire last_write_response; + + // last_write_response indicates the last response of the broken-up write burst (sub-bursts). + // At this time, the final merged response is sent, and rp_valid is only asserted + // once for the whole burst. + generate + if (USE_WRITERESPONSE) begin + assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket; + always @* begin + if (rf_sink_data[PKT_TRANS_WRITE] == 1) + rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED]; + else + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end else begin + assign last_write_response = 1'b0; + always @* begin + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end + endgenerate + + // ------------------------------------------------------------------ + // Response merging + // ------------------------------------------------------------------ + reg [1:0] current_response; + reg [1:0] response_merged; + generate + if (USE_WRITERESPONSE) begin : response_merging_all + reg first_write_response; + reg reset_merged_output; + reg [1:0] previous_response_in; + reg [1:0] previous_response; + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + first_write_response <= 1'b1; + end + else begin // Merging work for write response, for read: previous_response_in = current_response + if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin + first_write_response <= 1'b0; + if (rf_sink_endofpacket) + first_write_response <= 1'b1; + end + end + end + + always_comb begin + current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}}; + reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response); + previous_response_in = reset_merged_output ? current_response : previous_response; + response_merged = current_response >= previous_response ? current_response: previous_response_in; + end + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + previous_response <= 2'b00; + end + else begin + if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin + previous_response <= response_merged; + end + end + end + end else begin : response_merging_read_only + always @* begin + current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | + {2{rdata_fifo_sink_error}}; + response_merged = current_response; + end + end + endgenerate + + assign generate_response = rf_sink_data[FIFO_DATA_W-1]; + + wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; + // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo + wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; + + wire [BYTE_CNT_W-1:0] burst_byte_cnt; + wire [BURSTWRAP_W-1:0] rp_burstwrap; + wire [ADDR_W-1:0] rp_address; + wire rp_is_compressed; + wire ready_for_response; + + // ------------------------------------------------------------------ + // We're typically ready for a response if the network is ready. There + // is one exception: + // + // If the slave issues write responses, we only issue a merged response on + // the final sub-burst. As a result, we only care about response channel + // availability on the final burst when we send out the merged response. + // ------------------------------------------------------------------ + assign ready_for_response = (USE_WRITERESPONSE) ? + rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]: + rp_ready; + + // ------------------------------------------------------------------ + // Backpressure the readdata fifo if we're supposed to synthesize a response. + // This may be a read response (for suppressed reads) or a write response + // (for non-posted writes). + // ------------------------------------------------------------------ + assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response); + + always @* begin + // By default, return all fields... + rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; + + // ... and override specific fields. + rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; + // Assignments directly from the response fifo. + rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; + rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; + rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; + rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; + + // Burst uncompressor assignments + rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; + rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; + rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; + rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; + + rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; + rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; + // bounce the original size back to the master untouched + rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L] = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L]; + end + + // ------------------------------------------------------------------ + // Note: the burst uncompressor may be asked to generate responses for + // write packets; these are treated the same as single-cycle uncompressed + // reads. + // ------------------------------------------------------------------ + altera_merlin_burst_uncompressor #( + .ADDR_W (ADDR_W), + .BURSTWRAP_W (BURSTWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (PKT_SYMBOLS), + .BURST_SIZE_W (BURSTSIZE_W) + ) uncompressor ( + .clk (clk), + .reset (reset), + .sink_startofpacket (rf_sink_startofpacket_wire), + .sink_endofpacket (rf_sink_endofpacket), + .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), + .sink_ready (rf_sink_ready), + .sink_addr (rf_sink_addr), + .sink_burstwrap (rf_sink_burstwrap), + .sink_byte_cnt (rf_sink_byte_cnt), + .sink_is_compressed (rf_sink_compressed), + .sink_burstsize (rf_sink_burstsize), + + .source_startofpacket (rp_startofpacket), + .source_endofpacket (rp_endofpacket), + .source_valid (uncompressor_source_valid), + .source_ready (ready_for_response), + .source_addr (rp_address), + .source_burstwrap (rp_burstwrap), + .source_byte_cnt (burst_byte_cnt), + .source_is_compressed (rp_is_compressed), + .source_burstsize (uncompressor_burstsize) + ); + + //-------------------------------------- + // Assertion: In case slave support response. The slave needs return response in order + // Ex: non-posted write followed by a read: write response must complete before read data + //-------------------------------------- + // synthesis translate_off + ERROR_write_response_and_read_response_cannot_happen_same_time: + assert property ( @(posedge clk) + disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) + ); + + // synthesis translate_on +endmodule + diff --git a/ip/altera/ddr3/altera_merlin_slave_translator.sv b/ip/altera/ddr3/altera_merlin_slave_translator.sv new file mode 100644 index 0000000..581b5a2 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_slave_translator.sv @@ -0,0 +1,482 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Slave Translator +// +// Translates Universal Avalon MM Slave +// to any Avalon MM Slave +// ------------------------------------- +// +//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one +//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero +//The key feature here is that no same cycle turnaround data is processed through the fabric. + +//import avalon_utilities_pkg::*; + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_translator #( + parameter + //Widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + UAV_BYTEENABLE_W = 4, + + //Read Latency + AV_READLATENCY = 1, + + //Timing + AV_READ_WAIT_CYCLES = 0, + AV_WRITE_WAIT_CYCLES = 0, + AV_SETUP_WAIT_CYCLES = 0, + AV_DATA_HOLD_CYCLES = 0, + + //Optional Port Declarations + USE_READDATAVALID = 1, + USE_WAITREQUEST = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + //Variable Addressing + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_DATA_W = 32, + + AV_CONSTANT_BURST_BEHAVIOR = 0, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + CHIPSELECT_THROUGH_READLATENCY = 0, + + // Tightly-Coupled Options + USE_UAV_CLKEN = 0, + AV_REQUIRE_UNALIGNED_ADDRESSES = 0 +) ( + + // ------------------- + // Clock & Reset + // ------------------- + input wire clk, + input wire reset, + + // ------------------- + // Universal Avalon Slave + // ------------------- + + input wire [UAV_ADDRESS_W - 1 : 0] uav_address, + input wire [UAV_DATA_W - 1 : 0] uav_writedata, + input wire uav_write, + input wire uav_read, + input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, + input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, + input wire uav_lock, + input wire uav_debugaccess, + input wire uav_clken, + + output logic uav_readdatavalid, + output logic uav_waitrequest, + output logic [UAV_DATA_W - 1 : 0] uav_readdata, + output logic [1:0] uav_response, + // input wire uav_writeresponserequest, + output logic uav_writeresponsevalid, + + // ------------------- + // Customizable Avalon Master + // ------------------- + output logic [AV_ADDRESS_W - 1 : 0] av_address, + output logic [AV_DATA_W - 1 : 0] av_writedata, + output logic av_write, + output logic av_read, + output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, + output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, + output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, + output logic av_begintransfer, + output wire av_chipselect, + output logic av_beginbursttransfer, + output logic av_lock, + output wire av_clken, + output wire av_debugaccess, + output wire av_outputenable, + + input logic [AV_DATA_W - 1 : 0] av_readdata, + input logic av_readdatavalid, + input logic av_waitrequest, + + input logic [1:0] av_response, + // output logic av_writeresponserequest, + input wire av_writeresponsevalid + +); + + function integer clog2_plusone; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) + i = i >> 1; + end + endfunction + + function integer max; + //returns the larger of two passed arguments + input [31:0] one; + input [31:0] two; + if(one > two) + max=one; + else + max=two; + endfunction // int + + localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); + localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); + localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); + localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); + localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? + AV_ADDRESS_W : + UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; + localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? + AV_BURSTCOUNT_W : + UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; + localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; + + + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); + wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0]; + + // +-------------------------------- + // |Backwards Compatibility Signals + // +-------------------------------- + assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; + assign av_debugaccess = uav_debugaccess; + + // +------------------- + // |Passthru Signals + // +------------------- + + reg [1 : 0] av_response_delayed; + + always @(posedge clk, posedge reset) begin + if (reset) begin + av_response_delayed <= 2'b0; + end else begin + av_response_delayed <= av_response; + end + end + + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin + uav_response = '0; + end else begin + if (AV_READLATENCY != 0 || USE_READDATAVALID) begin + uav_response = av_response; + end else begin + uav_response = av_response_delayed; + end + end + end + // assign av_writeresponserequest = uav_writeresponserequest; + assign uav_writeresponsevalid = av_writeresponsevalid; + + //------------------------- + //Writedata and Byteenable + //------------------------- + + always@* begin + av_byteenable = '0; + av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + always@* begin + av_writedata = '0; + av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; + end + + // +------------------- + // |Calculated Signals + // +------------------- + + logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; + + function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; + input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; + + for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin + if(byteenable[i] == 1) begin + return i; + end + end + + return '0; + + endfunction + + reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; + reg [AV_ADDRESS_W - 1 : 0] address_reg; + always@(posedge clk, posedge reset) begin + if(reset) begin + burstcount_reg <= '0; + address_reg <= '0; + end else begin + burstcount_reg <= burstcount_reg; + address_reg <= address_reg; + if(av_beginbursttransfer) begin + burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + end + end + end + + logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; + + always@* begin + if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin + temp_wire = decode_byteenable(uav_byteenable); + real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; + end else begin + real_uav_address = uav_address; + end + + av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_address = address_reg; + end + + always@* begin + av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_burstcount = burstcount_reg; + end + + always@* begin + av_lock = uav_lock; + end + + // ------------------- + // Writebyteenable Assignment + // ------------------- + always@* begin + av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + // ------------------- + // Waitrequest Assignment + // ------------------- + + reg av_waitrequest_generated; + reg av_waitrequest_generated_read; + reg av_waitrequest_generated_write; + reg waitrequest_reset_override; + reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; + + always@(posedge reset, posedge clk) begin + if(reset) begin + wait_latency_counter <= '0; + waitrequest_reset_override <= 1'h1; + end else begin + waitrequest_reset_override <= 1'h0; + wait_latency_counter <= '0; + if( ~uav_waitrequest | waitrequest_reset_override ) + wait_latency_counter <= '0; + else if( uav_read | uav_write ) + wait_latency_counter <= wait_latency_counter + 1'h1; + end + end + + + always @* begin + + av_read = uav_read; + av_write = uav_write; + av_waitrequest_generated = 1'h1; + av_waitrequest_generated_read = 1'h1; + av_waitrequest_generated_write = 1'h1; + + if(LOG2_OF_LATENCY_SUM == 1) + av_waitrequest_generated = 0; + + if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin + av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; + av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; + av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; + av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; + + if(uav_write) + av_waitrequest_generated = av_waitrequest_generated_write; + else + av_waitrequest_generated = av_waitrequest_generated_read; + + end + + if(USE_WAITREQUEST) begin + uav_waitrequest = av_waitrequest; + end else begin + uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; + end + + end + + // -------------- + // Readdata Assignment + // -------------- + + reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; + + always@(posedge clk, posedge reset) begin + if(reset) + av_readdata_pre <= 'b0; + else + av_readdata_pre <= av_readdata; + end + + always@* begin + uav_readdata = {UAV_DATA_W{1'b0}}; + if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin + uav_readdata[AV_DATA_W-1:0] = av_readdata; + end else begin + uav_readdata[AV_DATA_W-1:0] = av_readdata_pre; + end + end + + // ------------------- + // Readdatavalid Assigment + // ------------------- + reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; + reg top_read_latency_shift_reg; + + always@* begin + uav_readdatavalid=top_read_latency_shift_reg; + if(USE_READDATAVALID) begin + uav_readdatavalid = av_readdatavalid; + end + end + + always@* begin + top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; + if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin + top_read_latency_shift_reg=read_latency_shift_reg; + end + if (AV_READLATENCY > 1) begin + top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; + end + end + + always@(posedge reset, posedge clk) begin + if (reset) begin + read_latency_shift_reg <= '0; + end else if (av_clken) begin + read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; + for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin + read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; + end + end + end + + // ------------ + // Chipselect and OutputEnable + // ------------ + reg av_chipselect_pre; + wire cs_extension; + reg av_outputenable_pre; + + assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; + assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); + assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; + + always@(posedge reset, posedge clk) begin + if(reset) + av_outputenable_pre <= 1'b0; + else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) + av_outputenable_pre <= 0; + else + av_outputenable_pre <= cs_extension | uav_read; + end + + always@(posedge reset, posedge clk) begin + if(reset) begin + av_chipselect_pre <= 1'b0; + end else begin + av_chipselect_pre <= 1'b0; + if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin + //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. + //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. + if(uav_read) begin + av_chipselect_pre <= 1'b1; + end else if(cs_extension == 1) begin + av_chipselect_pre <= 1'b1; + end + end + end + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + reg end_begintransfer; + + always@* begin + av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_begintransfer <= 1'b0; + end else begin + if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + end + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + reg end_beginbursttransfer; + reg in_transfer; + + always@* begin + av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_beginbursttransfer <= 1'b0; + in_transfer <= 1'b0; + end else begin + end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); + if(uav_write && uav_burstcount == symbols_per_word) + in_transfer <=1'b0; + else if(uav_write) + in_transfer <=1'b1; + end + end + +endmodule diff --git a/ip/altera/ddr3/altera_merlin_traffic_limiter.sv b/ip/altera/ddr3/altera_merlin_traffic_limiter.sv new file mode 100644 index 0000000..1ef5d43 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_traffic_limiter.sv @@ -0,0 +1,787 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ----------------------------------------------------- +// Merlin Traffic Limiter +// +// Ensures that non-posted transaction responses are returned +// in order of request. Out-of-order responses can happen +// when a master does a non-posted transaction on a slave +// while responses are pending from a different slave. +// +// Examples: +// 1) read to any latent slave, followed by a read to a +// variable-latent slave +// 2) read to any fixed-latency slave, followed by a read +// to another fixed-latency slave whose fixed latency is smaller. +// 3) non-posted write to any latent slave, followed by a non-posted +// write or read to any variable-latent slave. +// +// This component has two implementation modes that ensure +// response order, controlled by the REORDER parameter. +// +// 0) Backpressure to prevent a master from switching slaves +// until all outstanding responses have returned. We also +// have to suppress the non-posted transaction, obviously. +// +// 1) Reorder the responses as they return using a memory +// block. +// ----------------------------------------------------- + +`timescale 1 ns / 1 ns + +// altera message_off 10036 +module altera_merlin_traffic_limiter +#( + parameter + PKT_TRANS_POSTED = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + PKT_SRC_ID_H = 0, + PKT_SRC_ID_L = 0, + PKT_BYTE_CNT_H = 0, + PKT_BYTE_CNT_L = 0, + PKT_BYTEEN_H = 0, + PKT_BYTEEN_L = 0, + PKT_TRANS_WRITE = 0, + PKT_TRANS_READ = 0, + ST_DATA_W = 72, + ST_CHANNEL_W = 32, + + MAX_OUTSTANDING_RESPONSES = 1, + PIPELINED = 0, + ENFORCE_ORDER = 1, + + // ------------------------------------- + // internal: allows optimization between this + // component and the demux + // ------------------------------------- + VALID_WIDTH = 1, + + // ------------------------------------- + // Prevents all RAW and WAR hazards by waiting for + // responses to return before issuing a command + // with different direction. + // + // This is intended for Avalon masters which are + // connected to AXI slaves, because of the differing + // ordering models for the protocols. + // + // If PREVENT_HAZARDS is 1, then the current implementation + // needs to know whether incoming writes will be posted or + // not at compile-time. Only one of SUPPORTS_POSTED_WRITES + // and SUPPORTS_NONPOSTED_WRITES can be 1. + // + // When PREVENT_HAZARDS is 0 there is no such restriction. + // + // It is possible to be less restrictive for memories. + // ------------------------------------- + PREVENT_HAZARDS = 0, + + // ------------------------------------- + // Used only when hazard prevention is on, but may be used + // for optimization work in the future. + // ------------------------------------- + SUPPORTS_POSTED_WRITES = 1, + SUPPORTS_NONPOSTED_WRITES = 0, + + // ------------------------------------------------- + // Enables the reorder buffer which allows a master to + // switch slaves while responses are pending. + // Reponses will be reordered following command issue order. + // ------------------------------------------------- + REORDER = 0 +) +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command + // ------------------- + input cmd_sink_valid, + input [ST_DATA_W-1 : 0] cmd_sink_data, + input [ST_CHANNEL_W-1 : 0] cmd_sink_channel, + input cmd_sink_startofpacket, + input cmd_sink_endofpacket, + output cmd_sink_ready, + + output reg [VALID_WIDTH-1 : 0] cmd_src_valid, + output reg [ST_DATA_W-1 : 0] cmd_src_data, + output reg [ST_CHANNEL_W-1 : 0] cmd_src_channel, + output reg cmd_src_startofpacket, + output reg cmd_src_endofpacket, + input cmd_src_ready, + + // ------------------- + // Response + // ------------------- + input rsp_sink_valid, + input [ST_DATA_W-1 : 0] rsp_sink_data, + input [ST_CHANNEL_W-1 : 0] rsp_sink_channel, + input rsp_sink_startofpacket, + input rsp_sink_endofpacket, + output reg rsp_sink_ready, + + output reg rsp_src_valid, + output reg [ST_DATA_W-1 : 0] rsp_src_data, + output reg [ST_CHANNEL_W-1 : 0] rsp_src_channel, + output reg rsp_src_startofpacket, + output reg rsp_src_endofpacket, + input rsp_src_ready +); + + // ------------------------------------- + // Local Parameters + // ------------------------------------- + localparam DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam COUNTER_W = log2ceil(MAX_OUTSTANDING_RESPONSES + 1); + localparam PAYLOAD_W = ST_DATA_W + ST_CHANNEL_W + 4; + localparam NUMSYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + localparam MAX_DEST_ID = 1 << (DEST_ID_W); + localparam PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; + + // ------------------------------------------------------- + // Memory Parameters + // ------------------------------------------------------ + localparam MAX_BYTE_CNT = 1 << (PKT_BYTE_CNT_W); + localparam MAX_BURST_LENGTH = log2ceil(MAX_BYTE_CNT/NUMSYMBOLS); + + // Memory stores packet width, including sop and eop + localparam MEM_W = ST_DATA_W + ST_CHANNEL_W + 1 + 1; + localparam MEM_DEPTH = MAX_OUTSTANDING_RESPONSES * (MAX_BYTE_CNT/NUMSYMBOLS); + + // ----------------------------------------------------- + // Input Stage + // + // Figure out if the destination id has changed + // ----------------------------------------------------- + wire stage1_dest_changed; + wire stage1_trans_changed; + wire [PAYLOAD_W-1 : 0] stage1_payload; + wire in_nonposted_cmd; + reg [ST_CHANNEL_W-1:0] last_channel; + wire [DEST_ID_W-1 : 0] dest_id; + reg [DEST_ID_W-1 : 0] last_dest_id; + reg was_write; + wire is_write; + wire suppress; + wire save_dest_id; + + wire suppress_change_dest_id; + wire suppress_max_outstanding; + wire suppress_change_trans_but_not_dest; + wire suppress_change_trans_for_one_slave; + + generate if (PREVENT_HAZARDS == 1) begin : convert_posted_to_nonposted_block + assign in_nonposted_cmd = 1'b1; + end else begin : non_posted_cmd_assignment_block + assign in_nonposted_cmd = (cmd_sink_data[PKT_TRANS_POSTED] == 0); + end + endgenerate + + // ------------------------------------ + // Optimization: for the unpipelined case, we can save the destid if + // this is an unsuppressed nonposted command. This eliminates + // dependence on the backpressure signal. + // + // Not a problem for the pipelined case. + // ------------------------------------ + generate + if (PIPELINED) begin : pipelined_save_dest_id + assign save_dest_id = cmd_sink_valid & cmd_sink_ready & in_nonposted_cmd; + end else begin : unpipelined_save_dest_id + assign save_dest_id = cmd_sink_valid & ~(suppress_change_dest_id | suppress_max_outstanding) & in_nonposted_cmd; + end + endgenerate + + always @(posedge clk, posedge reset) begin + if (reset) begin + last_dest_id <= 0; + last_channel <= 0; + was_write <= 0; + end + else if (save_dest_id) begin + last_dest_id <= dest_id; + last_channel <= cmd_sink_channel; + was_write <= is_write; + end + end + + assign dest_id = cmd_sink_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + assign is_write = cmd_sink_data[PKT_TRANS_WRITE]; + assign stage1_dest_changed = (last_dest_id != dest_id); + assign stage1_trans_changed = (was_write != is_write); + + assign stage1_payload = { + cmd_sink_data, + cmd_sink_channel, + cmd_sink_startofpacket, + cmd_sink_endofpacket, + stage1_dest_changed, + stage1_trans_changed }; + + // ----------------------------------------------------- + // (Optional) pipeline between input and output + // ----------------------------------------------------- + wire stage2_valid; + reg stage2_ready; + wire [PAYLOAD_W-1 : 0] stage2_payload; + + generate + if (PIPELINED == 1) begin : pipelined_limiter + altera_avalon_st_pipeline_base + #( + .BITS_PER_SYMBOL(PAYLOAD_W) + ) stage1_pipe ( + .clk (clk), + .reset (reset), + .in_ready (cmd_sink_ready), + .in_valid (cmd_sink_valid), + .in_data (stage1_payload), + .out_valid (stage2_valid), + .out_ready (stage2_ready), + .out_data (stage2_payload) + ); + end else begin : unpipelined_limiter + assign stage2_valid = cmd_sink_valid; + assign stage2_payload = stage1_payload; + assign cmd_sink_ready = stage2_ready; + end + endgenerate + + // ----------------------------------------------------- + // Output Stage + // ----------------------------------------------------- + wire [ST_DATA_W-1 : 0] stage2_data; + wire [ST_CHANNEL_W-1:0] stage2_channel; + wire stage2_startofpacket; + wire stage2_endofpacket; + wire stage2_dest_changed; + wire stage2_trans_changed; + reg has_pending_responses; + reg [COUNTER_W-1 : 0] pending_response_count; + reg [COUNTER_W-1 : 0] next_pending_response_count; + wire nonposted_cmd; + wire nonposted_cmd_accepted; + wire response_accepted; + wire response_sink_accepted; + wire response_src_accepted; + wire count_is_1; + wire count_is_0; + reg internal_valid; + wire [VALID_WIDTH-1:0] wide_valid; + + assign { stage2_data, + stage2_channel, + stage2_startofpacket, + stage2_endofpacket, + stage2_dest_changed, + stage2_trans_changed } = stage2_payload; + + generate if (PREVENT_HAZARDS == 1) begin : stage2_nonposted_block + assign nonposted_cmd = 1'b1; + end else begin + assign nonposted_cmd = (stage2_data[PKT_TRANS_POSTED] == 0); + end + endgenerate + + assign nonposted_cmd_accepted = nonposted_cmd && internal_valid && (cmd_src_ready && cmd_src_endofpacket); + + // ----------------------------------------------------------------------------- + // Use the sink's control signals here, because write responses may be dropped + // when hazard prevention is on. + // + // When case REORDER, move all side to rsp_source as all packets from rsp_sink will + // go in the reorder memory. + // One special case when PREVENT_HAZARD is on, need to use reorder_memory_valid + // as the rsp_source will drop + // ----------------------------------------------------------------------------- + + assign response_sink_accepted = rsp_sink_valid && rsp_sink_ready && rsp_sink_endofpacket; + // Avoid Qis warning when incase, no REORDER, the signal reorder_mem_valid is not in used. + wire reorder_mem_out_valid; + wire reorder_mem_valid; + generate + if (REORDER) begin + assign reorder_mem_out_valid = reorder_mem_valid; + end else begin + assign reorder_mem_out_valid = '0; + end + endgenerate + + assign response_src_accepted = reorder_mem_out_valid & rsp_src_ready & rsp_src_endofpacket; + assign response_accepted = (REORDER == 1) ? response_src_accepted : response_sink_accepted; + + always @* begin + next_pending_response_count = pending_response_count; + + if (nonposted_cmd_accepted) + next_pending_response_count = pending_response_count + 1'b1; + if (response_accepted) + next_pending_response_count = pending_response_count - 1'b1; + if (nonposted_cmd_accepted && response_accepted) + next_pending_response_count = pending_response_count; + end + + assign count_is_1 = (pending_response_count == 1); + assign count_is_0 = (pending_response_count == 0); + // ------------------------------------------------------------------ + // count_max_reached : count if maximum command reach to backpressure + // ------------------------------------------------------------------ + reg count_max_reached; + always @(posedge clk, posedge reset) begin + if (reset) begin + pending_response_count <= 0; + has_pending_responses <= 0; + count_max_reached <= 0; + end + else begin + pending_response_count <= next_pending_response_count; + // synthesis translate_off + if (count_is_0 && response_accepted) + $display("%t: %m: Error: unexpected response: pending_response_count underflow", $time()); + // synthesis translate_on + has_pending_responses <= has_pending_responses + && ~(count_is_1 && response_accepted && ~nonposted_cmd_accepted) + || (count_is_0 && nonposted_cmd_accepted && ~response_accepted); + count_max_reached <= (next_pending_response_count == MAX_OUTSTANDING_RESPONSES); + + end + end + + wire suppress_prevent_harzard_for_particular_destid; + wire this_destid_trans_changed; + genvar j; + generate + if (REORDER) begin: fifo_dest_id_write_read_control_reorder_on + wire [COUNTER_W - 1 : 0] current_trans_seq_of_this_destid; + wire [MAX_DEST_ID - 1 : 0] current_trans_seq_of_this_destid_valid; + wire [MAX_DEST_ID - 1 : 0] responses_arrived; + reg [COUNTER_W - 1:0] trans_sequence; + wire [MAX_DEST_ID - 1 : 0] trans_sequence_we; + + wire [COUNTER_W : 0] trans_sequence_plus_trans_type; + wire current_trans_type_of_this_destid; + wire [COUNTER_W : 0] current_trans_seq_of_this_destid_plus_trans_type [MAX_DEST_ID]; + // ------------------------------------------------------------ + // Control write trans_sequence to fifos + // + // 1. when command accepted, read destid from command packet, + // write this id to the fifo (each fifo for each desitid) + // 2. when response acepted, read the destid from response packet, + // will know which sequence of this response, write it to + // correct segment in memory. + // what if two commands go to same slave, the two sequences + // go time same fifo, this even helps us to maintain order + // when two commands same thread to one slave. + // ----------------------------------------------------------- + wire [DEST_ID_W - 1 : 0] rsp_sink_dest_id; + wire [DEST_ID_W - 1 : 0] cmd_dest_id; + assign rsp_sink_dest_id = rsp_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; + + // write in fifo the trans_sequence and type of transaction + assign trans_sequence_plus_trans_type = {stage2_data[PKT_TRANS_WRITE], trans_sequence}; + + // read the cmd_dest_id from output of pipeline stage so that either + // or not, it wont affect how we write to fifo + assign cmd_dest_id = stage2_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + // ------------------------------------- + // Get the transaction_seq for that dest_id + // ------------------------------------- + wire [COUNTER_W - 1: 0] trans_sequence_rsp; + wire [COUNTER_W : 0] trans_sequence_rsp_plus_trans_type; + wire [COUNTER_W - 1: 0] trans_sequence_rsp_this_destid_waiting; + wire [COUNTER_W : 0] sequence_and_trans_type_this_destid_waiting; + wire trans_sequence_rsp_this_destid_waiting_valid; + assign trans_sequence_rsp_plus_trans_type = current_trans_seq_of_this_destid_plus_trans_type[rsp_sink_dest_id]; + assign trans_sequence_rsp = trans_sequence_rsp_plus_trans_type[COUNTER_W - 1: 0]; + + // do I need to check if this fifo is valid, it should be always valid, unless a command not yet sent + // and response comes back which means something weird happens. + // It is worth to do an assertion but now to avoid QIS warning, just do as normal ST handshaking + // check valid and ready + + for (j = 0; j < MAX_DEST_ID; j = j+1) + begin : write_and_read_trans_sequence + assign trans_sequence_we[j] = (cmd_dest_id == j) && nonposted_cmd_accepted; + assign responses_arrived[j] = (rsp_sink_dest_id == j) && response_sink_accepted; + end + + // -------------------------------------------------------------------- + // This is array of fifos, which will be created base on how many slaves + // that this master can see (max dest_id_width) + // Each fifo, will store the trans_sequence, which go to that slave + // On the response path, based in the response from which slave + // the fifo of that slave will be read, to check the sequences. + // and this sequence is the write address to the memory + // ----------------------------------------------------------------------------------- + // There are 3 sequences run around the limiter, they have a relationship + // And this is how the key point of reorder work: + // + // trans_sequence : command sequence, each command go thru the limiter + // will have a sequence to show their order. A simple + // counter from 0 go up and repeat. + // trans_sequence_rsp : response sequence, each response that go back to limiter, + // will be read from trans_fifos to know their sequence. + // expect_trans_sequence : Expected sequences for response that the master is waiting + // The limiter will hold this sequence and wait until exactly response + // for this sequence come back (trans_sequence_rsp) + // aka: if trans_sequence_rsp back is same as expect_trans_sequence + // then it is correct order, else response store in memory and + // send out to master later, when expect_trans_sequence match. + // ------------------------------------------------------------------------------------ + for (j = 0;j < MAX_DEST_ID; j = j+1) begin : trans_sequence_per_fifo + altera_avalon_sc_fifo + #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (COUNTER_W + 1), // one bit extra to store type of transaction + .FIFO_DEPTH (MAX_OUTSTANDING_RESPONSES), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (0), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) dest_id_fifo + ( + .clk (clk), + .reset (reset), + .in_data (trans_sequence_plus_trans_type), + .in_valid (trans_sequence_we[j]), + .in_ready (), + .out_data (current_trans_seq_of_this_destid_plus_trans_type[j]), + .out_valid (current_trans_seq_of_this_destid_valid[j]), + .out_ready (responses_arrived[j]), + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_startofpacket (1'b0), // (terminated) + .in_endofpacket (1'b0), // (terminated) + .out_startofpacket (), // (terminated) + .out_endofpacket (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + end // block: trans_sequence_per_fifo + + // ------------------------------------------------------- + // Calculate the transaction sequence, just simple increase + // when each commands pass by + // -------------------------------------------------------- + always @(posedge clk or posedge reset) + begin + if (reset) begin + trans_sequence <= '0; + end else begin + if (nonposted_cmd_accepted) + trans_sequence <= ( (trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : trans_sequence + 1'b1; + end + end + + // ------------------------------------- + // Control Memory for reorder responses + // ------------------------------------- + wire [COUNTER_W - 1 : 0] next_rd_trans_sequence; + reg [COUNTER_W - 1 : 0] rd_trans_sequence; + reg [COUNTER_W - 1 : 0] next_expected_trans_sequence; + reg [COUNTER_W - 1 : 0] expect_trans_sequence; + wire [ST_DATA_W - 1 : 0] reorder_mem_data; + wire [ST_CHANNEL_W - 1 : 0] reorder_mem_channel; + wire reorder_mem_startofpacket; + wire reorder_mem_endofpacket; + wire reorder_mem_ready; + // ------------------------------------------- + // Data to write and read from reorder memory + // Store everything includes channel, sop, eop + // ------------------------------------------- + reg [MEM_W - 1 : 0] mem_in_rsp_sink_data; + reg [MEM_W - 1 : 0] reorder_mem_out_data; + always_comb + begin + mem_in_rsp_sink_data = {rsp_sink_data, rsp_sink_channel, rsp_sink_startofpacket, rsp_sink_endofpacket}; + end + + assign next_rd_trans_sequence = ((rd_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : rd_trans_sequence + 1'b1; + assign next_expected_trans_sequence = ((expect_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : expect_trans_sequence + 1'b1; + + always_ff @(posedge clk, posedge reset) + begin + if (reset) begin + rd_trans_sequence <= '0; + expect_trans_sequence <= '0; + end else begin + if (rsp_src_ready && reorder_mem_valid) begin + if (reorder_mem_endofpacket == 1) begin //endofpacket + expect_trans_sequence <= next_expected_trans_sequence; + rd_trans_sequence <= next_rd_trans_sequence; + end + end + end + end // always_ff @ + + // For PREVENT_HAZARD, + // Case: Master Write to S0, read S1, and Read S0 back but if Write for S0 + // not yet return then we need to backpressure this, else read S0 might take over write + // This is more checking after the fifo destid, as read S1 is inserted in midle + // when see new packet, try to look at the fifo for that slave id, check if it + // type of transaction + assign sequence_and_trans_type_this_destid_waiting = current_trans_seq_of_this_destid_plus_trans_type[cmd_dest_id]; + assign current_trans_type_of_this_destid = sequence_and_trans_type_this_destid_waiting[COUNTER_W]; + assign trans_sequence_rsp_this_destid_waiting_valid = current_trans_seq_of_this_destid_valid[cmd_dest_id]; + // it might waiting other sequence, check if different type of transaction as only for PREVENT HAZARD + // if comming comamnd to one slave and this slave is still waiting for response from previous command + // which has diiferent type of transaction, we back-pressure this command to avoid HAZARD + assign suppress_prevent_harzard_for_particular_destid = (current_trans_type_of_this_destid != is_write) & trans_sequence_rsp_this_destid_waiting_valid; + + // ------------------------------------- + // Memory for reorder buffer + // ------------------------------------- + altera_merlin_reorder_memory + #( + .DATA_W (MEM_W), + .ADDR_H_W (COUNTER_W), + .ADDR_L_W (MAX_BURST_LENGTH), + .NUM_SEGMENT (MAX_OUTSTANDING_RESPONSES), + .DEPTH (MEM_DEPTH) + ) reorder_memory + ( + .clk (clk), + .reset (reset), + .in_data (mem_in_rsp_sink_data), + .in_valid (rsp_sink_valid), + .in_ready (reorder_mem_ready), + .out_data (reorder_mem_out_data), + .out_valid (reorder_mem_valid), + .out_ready (rsp_src_ready), + .wr_segment (trans_sequence_rsp), + .rd_segment (expect_trans_sequence) + ); + // ------------------------------------- + // Output from reorder buffer + // ------------------------------------- + assign reorder_mem_data = reorder_mem_out_data[MEM_W -1 : ST_CHANNEL_W + 2]; + assign reorder_mem_channel = reorder_mem_out_data[ST_CHANNEL_W + 2 - 1 : 2]; + assign reorder_mem_startofpacket = reorder_mem_out_data[1]; + assign reorder_mem_endofpacket = reorder_mem_out_data[0]; + + // ------------------------------------- + // Because use generate statment + // so move all rsp_src_xxx controls here + // ------------------------------------- + always_comb begin + cmd_src_data = stage2_data; + rsp_src_valid = reorder_mem_valid; + rsp_src_data = reorder_mem_data; + rsp_src_channel = reorder_mem_channel; + rsp_src_startofpacket = reorder_mem_startofpacket; + rsp_src_endofpacket = reorder_mem_endofpacket; + // ------------------------------------- + // Forces commands to be non-posted if hazard prevention + // is on, also drops write responses + // ------------------------------------- + rsp_sink_ready = reorder_mem_ready; // now it takes ready signal from the memory not direct from master + if (PREVENT_HAZARDS == 1) begin + cmd_src_data[PKT_TRANS_POSTED] = 1'b0; + + if (rsp_src_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin + rsp_src_valid = 1'b0; + rsp_sink_ready = 1'b1; + end + end + end // always_comb + + end // block: fifo_dest_id_write_read_control_reorder_on + endgenerate + + // ------------------------------------- + // Pass-through command and response + // ------------------------------------- + + always_comb + begin + cmd_src_channel = stage2_channel; + cmd_src_startofpacket = stage2_startofpacket; + cmd_src_endofpacket = stage2_endofpacket; + end // always_comb + + // ------------------------------------- + // When there is no REORDER requirement + // Just pass through signals + // ------------------------------------- + generate + if (!REORDER) begin : use_selector_or_pass_thru_rsp + always_comb begin + cmd_src_data = stage2_data; + // pass thru almost signals + rsp_src_valid = rsp_sink_valid; + rsp_src_data = rsp_sink_data; + rsp_src_channel = rsp_sink_channel; + rsp_src_startofpacket = rsp_sink_startofpacket; + rsp_src_endofpacket = rsp_sink_endofpacket; + // ------------------------------------- + // Forces commands to be non-posted if hazard prevention + // is on, also drops write responses + // ------------------------------------- + rsp_sink_ready = rsp_src_ready; // take care this, should check memory empty + if (PREVENT_HAZARDS == 1) begin + cmd_src_data[PKT_TRANS_POSTED] = 1'b0; + + if (rsp_sink_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin + rsp_src_valid = 1'b0; + rsp_sink_ready = 1'b1; + end + end + end // always_comb + end // if (!REORDER) + endgenerate + + // -------------------------------------------------------- + // Backpressure & Suppression + // -------------------------------------------------------- + // ENFORCE_ORDER: unused option, always is 1, remove it + // Now the limiter will suppress when max_outstanding reach + // -------------------------------------------------------- + generate + if (ENFORCE_ORDER) begin : enforce_order_block + assign suppress_change_dest_id = (REORDER == 1) ? 1'b0 : nonposted_cmd && has_pending_responses && + (stage2_dest_changed || (PREVENT_HAZARDS == 1 && stage2_trans_changed)); + end else begin : no_order_block + assign suppress_change_dest_id = 1'b0; + end + endgenerate + + // ------------------------------------------------------------ + // Even we allow change slave while still have pending responses + // But one special case, when PREVENT_HAZARD=1, we still allow + // switch slave while type of transaction change (RAW, WAR) but + // only to different slaves. + // if to same slave, we still need back pressure that to make + // sure no racing + // ------------------------------------------------------------ + + generate + if (REORDER) begin : prevent_hazard_block + assign suppress_change_trans_but_not_dest = nonposted_cmd && has_pending_responses && + !stage2_dest_changed && (PREVENT_HAZARDS == 1 && stage2_trans_changed); + end else begin : no_hazard_block + assign suppress_change_trans_but_not_dest = 1'b0; // no REORDER, the suppress_changes_destid take care of this. + end + endgenerate + + generate + if (REORDER) begin : prevent_hazard_block_for_particular_slave + assign suppress_change_trans_for_one_slave = nonposted_cmd && has_pending_responses && (PREVENT_HAZARDS == 1 && suppress_prevent_harzard_for_particular_destid); + end else begin : no_hazard_block_for_particular_slave + assign suppress_change_trans_for_one_slave = 1'b0; // no REORDER, the suppress_changes_destid take care of this. + end + endgenerate + + // ------------------------------------------ + // Backpressure when max outstanding transactions are reached + // ------------------------------------------ + generate + if (REORDER) begin : max_outstanding_block + assign suppress_max_outstanding = count_max_reached; + end else begin + assign suppress_max_outstanding = 1'b0; + end + endgenerate + + assign suppress = suppress_change_trans_for_one_slave | suppress_change_dest_id | suppress_max_outstanding; + assign wide_valid = { VALID_WIDTH {stage2_valid} } & stage2_channel; + + always @* begin + stage2_ready = cmd_src_ready; + internal_valid = stage2_valid; + // -------------------------------------------------------- + // change suppress condidtion, in case REODER it will alllow changing slave + // even still have pending transactions. + // ------------------------------------------------------- + if (suppress) begin + stage2_ready = 0; + internal_valid = 0; + end + + if (VALID_WIDTH == 1) begin + cmd_src_valid = {VALID_WIDTH{1'b0}}; + cmd_src_valid[0] = internal_valid; + end else begin + // ------------------------------------- + // Use the one-hot channel to determine if the destination + // has changed. This results in a wide valid bus + // ------------------------------------- + cmd_src_valid = wide_valid; + if (nonposted_cmd & has_pending_responses) begin + if (!REORDER) begin + cmd_src_valid = wide_valid & last_channel; + // ------------------------------------- + // Mask the valid signals if the transaction type has changed + // if hazard prevention is enabled + // ------------------------------------- + if (PREVENT_HAZARDS == 1) + cmd_src_valid = wide_valid & last_channel & { VALID_WIDTH {!stage2_trans_changed} }; + end else begin // else: !if(!REORDER) if REORDER happen + if (PREVENT_HAZARDS == 1) + cmd_src_valid = wide_valid & { VALID_WIDTH {!suppress_change_trans_for_one_slave} }; + if (suppress_max_outstanding) begin + cmd_src_valid = {VALID_WIDTH {1'b0}}; + end + + end + end + end + end + + // -------------------------------------------------- + // Calculates the log2ceil of the input value. + // + // This function occurs a lot... please refactor. + // -------------------------------------------------- + function integer log2ceil; + input integer val; + integer i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/altera_merlin_width_adapter.sv b/ip/altera/ddr3/altera_merlin_width_adapter.sv new file mode 100644 index 0000000..28c4bc6 --- /dev/null +++ b/ip/altera/ddr3/altera_merlin_width_adapter.sv @@ -0,0 +1,1206 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ----------------------------------------------------- +// Merlin Width Adapter +// ----------------------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_width_adapter +#( + parameter IN_PKT_ADDR_L = 0, + parameter IN_PKT_ADDR_H = 31, + parameter IN_PKT_DATA_L = 32, + parameter IN_PKT_DATA_H = 63, + parameter IN_PKT_BYTEEN_L = 64, + parameter IN_PKT_BYTEEN_H = 67, + parameter IN_PKT_TRANS_COMPRESSED_READ = 72, + parameter IN_PKT_BYTE_CNT_L = 73, + parameter IN_PKT_BYTE_CNT_H = 77, + parameter IN_PKT_BURSTWRAP_L = 78, + parameter IN_PKT_BURSTWRAP_H = 82, + parameter IN_PKT_BURST_SIZE_L = 83, + parameter IN_PKT_BURST_SIZE_H = 85, + parameter IN_PKT_RESPONSE_STATUS_L = 86, + parameter IN_PKT_RESPONSE_STATUS_H = 87, + parameter IN_PKT_TRANS_EXCLUSIVE = 88, + parameter IN_PKT_BURST_TYPE_L = 89, + parameter IN_PKT_BURST_TYPE_H = 90, + parameter IN_PKT_ORI_BURST_SIZE_L = 91, + parameter IN_PKT_ORI_BURST_SIZE_H = 93, + parameter IN_PKT_TRANS_WRITE = 94, + parameter IN_ST_DATA_W = 110, + + parameter OUT_PKT_ADDR_L = 0, + parameter OUT_PKT_ADDR_H = 31, + parameter OUT_PKT_DATA_L = 32, + parameter OUT_PKT_DATA_H = 47, + parameter OUT_PKT_BYTEEN_L = 48, + parameter OUT_PKT_BYTEEN_H = 49, + parameter OUT_PKT_TRANS_COMPRESSED_READ = 54, + parameter OUT_PKT_BYTE_CNT_L = 55, + parameter OUT_PKT_BYTE_CNT_H = 59, + parameter OUT_PKT_BURST_SIZE_L = 60, + parameter OUT_PKT_BURST_SIZE_H = 62, + parameter OUT_PKT_RESPONSE_STATUS_L = 63, + parameter OUT_PKT_RESPONSE_STATUS_H = 64, + parameter OUT_PKT_TRANS_EXCLUSIVE = 65, + parameter OUT_PKT_BURST_TYPE_L = 66, + parameter OUT_PKT_BURST_TYPE_H = 67, + parameter OUT_PKT_ORI_BURST_SIZE_L = 68, + parameter OUT_PKT_ORI_BURST_SIZE_H = 70, + parameter OUT_ST_DATA_W = 92, + + parameter ST_CHANNEL_W = 32, + parameter OPTIMIZE_FOR_RSP = 0, + + parameter PACKING = 1, // 1: Enables packing in Avalon systems + parameter CONSTANT_BURST_SIZE = 1, // 1: Optimizes for Avalon-only systems as those always have full size transactions + parameter RESPONSE_PATH = 0, // 0: This adapter is on command path, 1: This adapter is on response path + + // Address alignment can be turned off (an optimisation) if all connected + // masters only issue aligned addresses. + parameter ENABLE_ADDRESS_ALIGNMENT = 1 +) +( + input clk, + input reset, + output reg in_ready, + input in_valid, + input [ST_CHANNEL_W-1:0] in_channel, + input [IN_ST_DATA_W-1:0] in_data, + input in_startofpacket, + input in_endofpacket, + input out_ready, + output reg out_valid, + output reg [ST_CHANNEL_W-1:0] out_channel, + output reg [OUT_ST_DATA_W-1:0] out_data, + output reg out_startofpacket, + output reg out_endofpacket, + + input [2:0] in_command_size_data +); + + // ------------------------------------------------------------ + // Local Parameters + // ------------------------------------------------------------ + localparam IN_NUMSYMBOLS = IN_PKT_BYTEEN_H - IN_PKT_BYTEEN_L + 1; + localparam IN_DATA_W = IN_PKT_DATA_H - IN_PKT_DATA_L + 1; + localparam IN_BYTEEN_W = IN_NUMSYMBOLS; + + localparam OUT_NUMSYMBOLS = OUT_PKT_BYTEEN_H - OUT_PKT_BYTEEN_L + 1; + localparam OUT_DATA_W = OUT_PKT_DATA_H - OUT_PKT_DATA_L + 1; + localparam OUT_BYTEEN_W = OUT_NUMSYMBOLS; + + localparam BURST_TYPE_W = IN_PKT_BURST_TYPE_H - IN_PKT_BURST_TYPE_L + 1; + localparam BURST_SIZE_W = IN_PKT_BURST_SIZE_H - IN_PKT_BURST_SIZE_L + 1; + localparam RESPONSE_STATUS_W = IN_PKT_RESPONSE_STATUS_H - IN_PKT_RESPONSE_STATUS_L + 1; + localparam SYMBOL_W = IN_DATA_W / IN_NUMSYMBOLS; + localparam ADDRESS_W = IN_PKT_ADDR_H - IN_PKT_ADDR_L + 1; + localparam BYTE_CNT_W = IN_PKT_BYTE_CNT_H - IN_PKT_BYTE_CNT_L + 1; + localparam OUT_BYTE_CNT_W = OUT_PKT_BYTE_CNT_H - OUT_PKT_BYTE_CNT_L + 1; + localparam BWRAP_W = IN_PKT_BURSTWRAP_H - IN_PKT_BURSTWRAP_L + 1; + localparam SIZE_W = 2 ** BURST_SIZE_W; + + localparam RATIO = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? + IN_NUMSYMBOLS / OUT_NUMSYMBOLS : + OUT_NUMSYMBOLS / IN_NUMSYMBOLS ); + localparam WIDE_NUMSYMBOLS = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? + IN_NUMSYMBOLS : OUT_NUMSYMBOLS ); + localparam WIDE_DATA = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? + IN_DATA_W - (OUT_NUMSYMBOLS*SYMBOL_W) : + OUT_DATA_W - (IN_NUMSYMBOLS*SYMBOL_W)); + localparam OUT_SEGMENT_W = OUT_NUMSYMBOLS * SYMBOL_W; + + localparam NW_BITFORSELECT_R = clogb2(IN_NUMSYMBOLS); + localparam NW_BITFORSELECT_L = clogb2(OUT_NUMSYMBOLS) - 1; + localparam ALIGNED_BITS_L = clogb2(OUT_NUMSYMBOLS) - 1; + localparam WN_ADDR_LSBS = clogb2(RATIO); + localparam WN_ADDR_SELECT = clogb2(IN_NUMSYMBOLS); + localparam LOG_OUT_NUMSYMBOLS = clogb2(OUT_NUMSYMBOLS); + + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + + function integer clogb2; + input [63:0] value; + begin + clogb2 = 0; + while (value>0) begin + value = value >> 1; + clogb2 = clogb2 + 1; + end + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + function integer min; + input [31:0] a; + input [31:0] b; + begin + return (a < b) ? a : b; + end + endfunction + + function integer max; + input [31:0] a; + input [31:0] b; + begin + return (a > b) ? a : b; + end + endfunction + + function reg [clogb2(RATIO)-1:0] mask_to_select_correct_segments_for_size; + input [clogb2(RATIO)-1:0] select_output_segment; + input [9:0] size_ratio; + input int msb_select_bit; + + integer i; + mask_to_select_correct_segments_for_size = '1; + for (i=0; i < msb_select_bit; i = i +1'b1 ) begin + if (clogb2(size_ratio) > i) + mask_to_select_correct_segments_for_size[i] = select_output_segment[i]; + end + endfunction + + function reg [ADDRESS_W-1:0] choose_packed_address_base_on_size; + input [9:0] size_ratio; + input int msb_select_bit; + + integer i; + choose_packed_address_base_on_size = '1; + for (i=0; i < msb_select_bit; i = i +1'b1 ) begin + if (clogb2(size_ratio) > i) + choose_packed_address_base_on_size[i + NW_BITFORSELECT_R] = 1'b0; + end + endfunction + + // ------------------------------------------------------------ + // Computes how many bytes are in this transfer, based on the size + // encoding. + // ------------------------------------------------------------ + function reg[9:0] bytes_in_transfer; + input [BURST_SIZE_W-1:0] axsize; + + case (axsize) + 4'b0000: bytes_in_transfer = 10'b0000000001; + 4'b0001: bytes_in_transfer = 10'b0000000010; + 4'b0010: bytes_in_transfer = 10'b0000000100; + 4'b0011: bytes_in_transfer = 10'b0000001000; + 4'b0100: bytes_in_transfer = 10'b0000010000; + 4'b0101: bytes_in_transfer = 10'b0000100000; + 4'b0110: bytes_in_transfer = 10'b0001000000; + 4'b0111: bytes_in_transfer = 10'b0010000000; + 4'b1000: bytes_in_transfer = 10'b0100000000; + 4'b1001: bytes_in_transfer = 10'b1000000000; + default: bytes_in_transfer = 10'b0000000001; + endcase + + endfunction + + // ------------------------------------------------------------ + // Pseudo-field Parameters + // + // The width adapter widens the data and byteenable fields in the + // output packet, thus changing the output packet format. By using + // pseudo-fields, we can avoid remapping each individual field to + // the output, which is a non-scalable solution. + // + // How? Assume the packet format is { FIRST, byteen, MID, data, LAST }, + // where byteen and data positions are interchangeable. FIRST, MID and + // LAST are pseudo-fields that represent the collection of fields in + // those positions. + // + // Not all the pseudo-fields may exist for a given packet format. A + // non-existent field has reversed indices, so we have to be careful + // when using them. + // ------------------------------------------------------------ + + localparam IN_FIRST_L = 0, + IN_FIRST_H = min(IN_PKT_BYTEEN_L, IN_PKT_DATA_L) - 1, + IN_MID_L = min(IN_PKT_DATA_H, IN_PKT_BYTEEN_H) + 1, + IN_MID_H = max(IN_PKT_DATA_L, IN_PKT_BYTEEN_L) - 1, + IN_LAST_L = max(IN_PKT_BYTEEN_H, IN_PKT_DATA_H) + 1, + IN_LAST_H = IN_ST_DATA_W - 1, + + FIRST_EXISTS = (IN_FIRST_H >= IN_FIRST_L), + MID_EXISTS = (IN_MID_H >= IN_MID_L), + LAST_EXISTS = (IN_LAST_H >= IN_LAST_L), + + FIRST_W = IN_FIRST_H - IN_FIRST_L + 1, + MID_W = IN_MID_H - IN_MID_L + 1, + LAST_W = IN_LAST_H - IN_LAST_L + 1, + + // ------------------------------------------------- + // We cannot split the output map into generate blocks as we + // do for the inputs because address and size are mapped over + // the pseudo-fields. We ensure that the indices are always + // legal, even if the field is unused later on. + + OUT_FIRST_L = 0, + OUT_FIRST_H = FIRST_EXISTS ? + min(OUT_PKT_BYTEEN_L, OUT_PKT_DATA_L) - 1 : + OUT_FIRST_L, + OUT_MID_L = min(OUT_PKT_DATA_H, OUT_PKT_BYTEEN_H) + 1, + OUT_MID_H = MID_EXISTS ? + max(OUT_PKT_DATA_L, OUT_PKT_BYTEEN_L) - 1 : + OUT_MID_L, + OUT_LAST_L = max(OUT_PKT_BYTEEN_H, OUT_PKT_DATA_H) + 1, + OUT_LAST_H = LAST_EXISTS ? + OUT_ST_DATA_W - 1 : + OUT_LAST_L; + + // ------------------------------------------------------------ + // Signals + // ------------------------------------------------------------ + reg [BURST_SIZE_W-1:0] in_size_field; + reg [IN_DATA_W-1:0] in_data_field; + reg [IN_BYTEEN_W-1:0] in_byteen_field; + reg [ADDRESS_W-1:0] in_address_field; + reg [ADDRESS_W-1:0] address_from_packet; + reg [BYTE_CNT_W-1:0] in_byte_cnt_field; + reg [BWRAP_W-1:0] in_burstwrap_field; + reg [RESPONSE_STATUS_W-1:0] in_response_status_field; + reg in_cmpr_read; + reg in_lock_field; + reg in_write; + reg [BURST_TYPE_W-1:0] in_burst_type_field; + reg [BYTE_CNT_W-1:0] quantized_byte_cnt_field; + + reg [BURST_SIZE_W-1:0] out_size_field; + reg [OUT_DATA_W-1:0] out_data_field; + reg [OUT_BYTEEN_W-1:0] out_byteen_field; + reg [ADDRESS_W-1:0] out_address_field; + reg out_cmpr_read; + reg [BYTE_CNT_W-1:0] out_byte_cnt_field; + reg out_lock_field; + reg [BURST_TYPE_W-1:0] out_burst_type_field; + reg [RESPONSE_STATUS_W-1:0] out_response_status_field; + + reg [FIRST_W-1:0] in_first_field; + reg [FIRST_W-1:0] out_first_field; + reg [MID_W-1:0] in_mid_field; + reg [MID_W-1:0] out_mid_field; + reg [LAST_W-1:0] in_last_field; + reg [LAST_W-1:0] out_last_field; + + reg [WIDE_DATA-1:0] data_reg; + reg [WIDE_NUMSYMBOLS-1:0] byteen_reg; + reg [ADDRESS_W-1:0] address_reg; + reg [BYTE_CNT_W-1:0] byte_cnt_reg; + reg use_reg; + reg startofpacket_reg; + reg endofpacket_reg; + reg [OUT_SEGMENT_W-1:0] mask; + reg [RESPONSE_STATUS_W-1:0] response_status_reg; + + + reg [ADDRESS_W-1:0] int_output_sel; + reg [clogb2(RATIO)-1:0] output_sel; + reg [OUT_SEGMENT_W-1:0] data_array [0:RATIO-1]; + reg [OUT_NUMSYMBOLS-1:0] byteen_array [0:RATIO-1]; + + // In narrow-to-wide adaptation, each input datum/byteenable bit maps to + // one of OUT_NUMSYMBOLS/IN_NUMSYMBOLS subfields in the wider output + // packet. (Call these subfields "segments".) A subfield of the input + // address, in_bitforselect, selects the segment. Examples: + // 8-16 adaptation: in_bitforselect = in_address_field[0] + // 8-32 adaptation: in_bitforselect = in_address_field[1:0] + // 8-64 adaptation: in_bitforselect = in_address_field[2:0] + // 16-32 adaptation: in_bitforselect = in_address_field[1] + // 32-64 adaptation: in_bitforselect = in_address_field[2] + + // The width of in_bitforselect is + // log2(OUT_NUM_SYMBOLS) - log2(IN_NUM_SYMBOLS) = + // log2(RATIO) + + // The msb of in_bitforselect is driven by + // in_adress_field[log2(OUT_NUMSYMBOLS) - 1] + // The lsb of in_adress_field is driven by + // in_adress_field[log2(IN_NUMSYMBOLS)] + + + reg [clogb2(RATIO)-1:0] in_bitforselect; + integer i, j; + + // ---------------------------------------- + // Input Field Mapping + // ---------------------------------------- + reg [ADDRESS_W-1:0] address_for_adaptation; + always @* begin + in_size_field = in_data[IN_PKT_BURST_SIZE_H :IN_PKT_BURST_SIZE_L ]; + in_data_field = in_data[IN_PKT_DATA_H :IN_PKT_DATA_L ]; + in_byteen_field = in_data[IN_PKT_BYTEEN_H :IN_PKT_BYTEEN_L ]; + address_from_packet = in_data[IN_PKT_ADDR_H :IN_PKT_ADDR_L ]; + in_byte_cnt_field = in_data[IN_PKT_BYTE_CNT_H :IN_PKT_BYTE_CNT_L ]; + in_cmpr_read = in_data[IN_PKT_TRANS_COMPRESSED_READ]; + in_write = in_data[IN_PKT_TRANS_WRITE]; + in_lock_field = in_data[IN_PKT_TRANS_EXCLUSIVE]; + in_burst_type_field = in_data[IN_PKT_BURST_TYPE_H :IN_PKT_BURST_TYPE_L ]; + in_response_status_field = in_data[IN_PKT_RESPONSE_STATUS_H :IN_PKT_RESPONSE_STATUS_L]; + end + + // ---------------------------------------- + // Process unaligned address for first address of the burst + // ---------------------------------------- + generate + if (IN_NUMSYMBOLS > OUT_NUMSYMBOLS && ENABLE_ADDRESS_ALIGNMENT) begin + reg [ADDRESS_W + (BWRAP_W-1) + BURST_SIZE_W + BURST_TYPE_W - 1 :0] address_for_alignment; + reg [ADDRESS_W + clogb2(IN_NUMSYMBOLS)-1:0] address_after_aligned; + + assign address_for_alignment = {address_from_packet, in_size_field}; + assign address_for_adaptation = address_after_aligned[ADDRESS_W-1:0]; + + altera_merlin_address_alignment + #( + .ADDR_W (ADDRESS_W), + .BURSTWRAP_W (BWRAP_W), + .INCREMENT_ADDRESS (0), + .NUMSYMBOLS (IN_NUMSYMBOLS), + .SIZE_W (BURST_SIZE_W) + ) check_and_align_address_to_size + ( + .clk (clk), + .reset (reset), + .in_data (address_for_alignment), + .out_data (address_after_aligned), + .in_valid (), + .in_sop (), + .in_eop (), + .out_ready () + ); + end else begin + assign address_for_adaptation = address_from_packet; + end + endgenerate + + generate begin + if (FIRST_EXISTS) begin + always @* begin + in_first_field = in_data[IN_FIRST_H:IN_FIRST_L]; + end + end else begin + always @* begin + in_first_field = '0; + end + end + if (MID_EXISTS) begin + always @* begin + in_mid_field = in_data[IN_MID_H:IN_MID_L]; + end + end else begin + always @* begin + in_mid_field = '0; + end + end + if (LAST_EXISTS) begin + always @* begin + in_last_field = in_data[IN_LAST_H:IN_LAST_L]; + end + end + end + endgenerate + + generate + + //------------------------------------------------------- + //------------------------------------------------------- + // Wide-to-Narrow + // + // For every input cycle, we drive out a bunch'o'output + // cycles. Nothing fancier. Yes, it could be more + // optimal, but we'll leave that for another day. + //------------------------------------------------------- + //------------------------------------------------------- + if (IN_NUMSYMBOLS > OUT_NUMSYMBOLS) begin + + wire [31:0] cmd_burst_size = CONSTANT_BURST_SIZE ? IN_NUMSYMBOLS : bytes_in_transfer(in_size_field); + + // Below mess is just to avoid Quartus warnings about mis-sized assignments. + wire [31:0] int_out_numsymbols = OUT_NUMSYMBOLS; + wire [clogb2(OUT_NUMSYMBOLS):0] sized_out_numsymbols = int_out_numsymbols[clogb2(OUT_NUMSYMBOLS):0]; + + wire [31:0] int_out_size = (cmd_burst_size < OUT_NUMSYMBOLS) ? cmd_burst_size : OUT_NUMSYMBOLS; + wire [SIZE_W-1:0] sized_out_size = int_out_size[SIZE_W-1:0]; + + wire [31:0] int_ratio_minus_1 = (cmd_burst_size / OUT_NUMSYMBOLS) - 1; + wire [clogb2(RATIO)-1:0] sized_ratio_minus_1 = int_ratio_minus_1[clogb2(RATIO)-1:0]; + + wire [31:0] int_log2_out_numsymbols = clogb2(OUT_NUMSYMBOLS); + wire [BURST_SIZE_W-1:0] log2_out_numsymbols = int_log2_out_numsymbols[BURST_SIZE_W-1:0]; + + wire [31:0] int_byte_cnt_factor = (in_size_field < log2_out_numsymbols) ? log2_out_numsymbols : in_size_field; + wire [BURST_SIZE_W-1:0] sized_byte_cnt_factor = int_byte_cnt_factor[BURST_SIZE_W-1:0]; + + reg single_response_expected; + reg only_one_segment_asserted; + reg [RATIO-1:0] segments_with_be_asserted; + reg [clogb2(RATIO)-1:0] count; + + assign single_response_expected = (RESPONSE_PATH && ((only_one_segment_asserted && in_startofpacket && in_endofpacket) || in_write)); + + always @(posedge clk, posedge reset) begin + if (reset) begin + address_reg <= '0; + byte_cnt_reg <= '0; + count <= '0; + use_reg <= '0; + endofpacket_reg <= '0; + data_reg <= '0; + byteen_reg <= '0; + end else begin + // If we're not working on a wide datum, + // then wait until one arrives. + if (~use_reg) begin + + if (CONSTANT_BURST_SIZE) begin // when the system contains ONLY Avalon masters and slaves + address_reg[ADDRESS_W -1 : WN_ADDR_SELECT] <= in_address_field[ADDRESS_W -1 : WN_ADDR_SELECT]; + address_reg[WN_ADDR_SELECT - 1 : 0] <= sized_out_numsymbols; + data_reg <= in_data_field[IN_DATA_W-1:OUT_NUMSYMBOLS*SYMBOL_W]; + byteen_reg <= in_byteen_field >> OUT_NUMSYMBOLS; + byte_cnt_reg <= in_byte_cnt_field - sized_out_numsymbols; + end else begin + address_reg <= in_address_field + sized_out_size; + byte_cnt_reg <= (in_byte_cnt_field >> clogb2(IN_NUMSYMBOLS) << sized_byte_cnt_factor) - sized_out_numsymbols; + end + + endofpacket_reg <= in_endofpacket; + + if (in_valid && out_ready && !in_cmpr_read && (cmd_burst_size > OUT_NUMSYMBOLS) && !single_response_expected) begin + // Data has arrived! + count <= sized_ratio_minus_1; + use_reg <= 1'b1; + end + + end else begin // if (count == 0) + // We have a wide datum in progress. Just wait until + // the previous datum is taken, and then set + // up the next transfer. + if (out_ready) begin + if (CONSTANT_BURST_SIZE) begin + address_reg[ADDRESS_W -1 : WN_ADDR_SELECT] <= in_address_field[ADDRESS_W -1 : WN_ADDR_SELECT]; + address_reg[WN_ADDR_SELECT - 1 : 0] <= address_reg[WN_ADDR_SELECT - 1 : 0] + sized_out_numsymbols; + data_reg <= data_reg >> (OUT_NUMSYMBOLS * SYMBOL_W); + byteen_reg <= byteen_reg >> (OUT_NUMSYMBOLS); + end else begin + address_reg <= address_reg + sized_out_size; + end + byte_cnt_reg <= byte_cnt_reg - sized_out_numsymbols; + count <= count - 1'b1; + if (count == 1'b1) + // We're at the end of this word. + use_reg <= '0; + + end // if (out_ready) + end // else: !if(count == 0) + end // if (posedge clk) + end // always @ (clk, reset) + + + always @* begin + // Calculate in_ready. + // If count is 0, then we don't have data underway, and we + // definitely won't be ready for it the first time 'round. + // If count is '1', then we're finishing a set, and we're + // ready if the output is. + // If count > 1, then we're mid set, and certainly + // not ready. + in_ready = 0; + if ( (cmd_burst_size <= OUT_NUMSYMBOLS) || count == 1 || in_cmpr_read ) + in_ready = out_ready; + + out_valid = in_valid; + out_channel = in_channel; + out_startofpacket = in_startofpacket; + out_endofpacket = 0; + + out_size_field = (cmd_burst_size < OUT_NUMSYMBOLS) ? in_size_field : log2_out_numsymbols; + if (CONSTANT_BURST_SIZE) begin // For Avalon only + out_byteen_field = in_byteen_field[OUT_NUMSYMBOLS-1:0]; + out_data_field = in_data_field[OUT_NUMSYMBOLS * SYMBOL_W-1:0]; + out_byte_cnt_field = in_byte_cnt_field; + end else begin + out_byte_cnt_field = in_byte_cnt_field >> clogb2(IN_NUMSYMBOLS) << sized_byte_cnt_factor; + end + + out_first_field = in_first_field; + out_mid_field = in_mid_field; + out_last_field = in_last_field; + out_cmpr_read = in_cmpr_read; + out_lock_field = in_lock_field; + out_burst_type_field = in_burst_type_field; + out_response_status_field = in_response_status_field; + + // Case when command size <= OUT_NUMSYMBOLS: pass the cycle + // through, unmodified + if (cmd_burst_size <= OUT_NUMSYMBOLS) begin + out_endofpacket = in_endofpacket; + in_address_field = address_from_packet; + end // (cmd_burst_size <= OUT_NUMSYMBOLS) + else begin + // Case when we need to bus size data (size > OUT_NUMSYMBOLS). + out_lock_field = 0; + // Change fixed burst type opcodes to the repeated wrap + // opcode. + if (in_burst_type_field == 2'b00) begin + out_burst_type_field = 2'b11; + end + // On the first address of the burst, align and send this + // address to the network + in_address_field = address_for_adaptation; + end // (cmd_burst_size > OUT_NUMSYMBOLS) + + out_address_field = in_address_field; + int_output_sel = in_address_field >> log2_out_numsymbols ; + if (in_cmpr_read) + out_endofpacket = 1; + + if (use_reg) begin + + out_startofpacket = 0; + // If it's the last cycle, or if there's no more data, + // we can allow an endofpacket. + if (count == 1) + out_endofpacket = endofpacket_reg; + + out_byte_cnt_field = byte_cnt_reg; + out_address_field = address_reg; + if (CONSTANT_BURST_SIZE) begin // Avalon system + out_data_field = data_reg[(OUT_NUMSYMBOLS * SYMBOL_W)-1:0]; + out_byteen_field = byteen_reg[OUT_NUMSYMBOLS-1:0]; + byteen_array = '{RATIO {0} }; + data_array = '{RATIO {0} }; + end + int_output_sel = address_reg >> log2_out_numsymbols; + end + + output_sel = int_output_sel[WN_ADDR_LSBS-1:0]; + if (!CONSTANT_BURST_SIZE) begin + out_byteen_field = byteen_array[output_sel]; + out_data_field = data_array[output_sel]; + end + + // Check each output-sized segment to see whether it + // is enabled (byteenables) + segments_with_be_asserted = 0; + for (i = 0; i < RATIO; i=i+1) begin + segments_with_be_asserted[i] = |in_byteen_field[i*OUT_BYTEEN_W +: OUT_BYTEEN_W]; + end + + // Determine whether only one segment is asserted. This code detects a power of two, + // i.e. only 1 bit is asserted. + only_one_segment_asserted = (segments_with_be_asserted && !(segments_with_be_asserted & (segments_with_be_asserted - 1))); + + //----------------------------------------- + // Optimization for non-bursting wide-narrow response. + // + // Only one segment of the wide word will have asserted + // byteenables. Just pass that segment through and drop + // the rest. This should synthesize to an and-or mux. + //----------------------------------------- + if (OPTIMIZE_FOR_RSP | single_response_expected) begin + out_startofpacket = in_startofpacket; + out_endofpacket = in_endofpacket; + in_ready = out_ready; + //----------------------------------------- + // Not correct, but nothing in the response path looks + // at these today (10.1). Must be corrected when we allow + // multiple width adapters on a path. + //----------------------------------------- + out_address_field = in_address_field; + out_byte_cnt_field = in_byte_cnt_field; + + out_data_field = '0; + out_byteen_field = '0; + for (i = 0; i < RATIO; i=i+1) begin + mask = '0; + for (j = 0; j < OUT_NUMSYMBOLS; j=j+1) begin + mask |= {SYMBOL_W{in_byteen_field[i*OUT_NUMSYMBOLS+j]}} << (j*SYMBOL_W); + end + + out_data_field |= mask & in_data_field[i*OUT_SEGMENT_W +: OUT_SEGMENT_W]; + out_byteen_field |= in_byteen_field[i*OUT_NUMSYMBOLS +: OUT_NUMSYMBOLS]; + end + end + else begin // to prevent latches + j = 0; + mask = '0; + end + + end // always @ * + + //------------------------------------------------------- + // Configuration Error Checking + //------------------------------------------------------- + // synthesis translate_off + initial begin + if (RATIO * OUT_NUMSYMBOLS != IN_NUMSYMBOLS) begin + $display("%m : The ratio of input symbols to output symbols must be an integer."); + $stop(); + end + end + // synthesis translate_on + if (!CONSTANT_BURST_SIZE) begin + integer ibyte; + always @* begin + for(ibyte=0; ibyte OUT_NUMSYMBOLS) + + //------------------------------------------------------- + //------------------------------------------------------- + // Narrow-to-Wide + //------------------------------------------------------- + //------------------------------------------------------- + if (OUT_NUMSYMBOLS > IN_NUMSYMBOLS) begin + wire p0_valid; + reg p0_startofpacket; + reg p0_endofpacket; + reg [IN_DATA_W-1:0] p0_data_field; + reg [IN_BYTEEN_W-1:0] p0_byteen_field; + reg [ADDRESS_W-1:0] p0_address_field; + reg [BWRAP_W-1:0] p0_bwrap_field; + reg [BYTE_CNT_W-1:0] p0_byte_cnt_field; + reg [clogb2(RATIO)-1:0] p0_bitforselect; + reg p0_cmpr_read; + reg [FIRST_W-1:0] p0_first_field; + reg [MID_W-1:0] p0_mid_field; + reg [LAST_W-1:0] p0_last_field; + reg p0_use_reg; + reg [ST_CHANNEL_W-1:0] p0_channel; + reg [BURST_SIZE_W-1:0] p0_burst_size; + reg [BURST_SIZE_W-1:0] p0_ori_burst_size; + reg p0_out_lock_field; + reg [BURST_TYPE_W-1:0] p0_burst_type_field; + + reg [RESPONSE_STATUS_W-1:0] p0_response_status_field; + reg p0_reg_startofpacket; + reg p0_reg_endofpacket; + reg [IN_DATA_W-1:0] p0_reg_data_field; + reg [IN_BYTEEN_W-1:0] p0_reg_byteen_field; + reg [ADDRESS_W-1:0] p0_reg_address_field; + reg [BWRAP_W-1:0] p0_reg_bwrap_field; + reg [BYTE_CNT_W-1:0] p0_reg_byte_cnt_field; + reg [clogb2(RATIO)-1:0] p0_reg_bitforselect; + reg p0_reg_cmpr_read; + reg [FIRST_W-1:0] p0_reg_first_field; + reg [MID_W-1:0] p0_reg_mid_field; + reg [LAST_W-1:0] p0_reg_last_field; + reg [ST_CHANNEL_W-1:0] p0_reg_channel; + reg [BURST_SIZE_W-1:0] p0_reg_burst_size; + reg [BURST_SIZE_W-1:0] p0_reg_ori_burst_size; + reg [BURST_TYPE_W-1:0] p0_reg_burst_type_field; + reg [RESPONSE_STATUS_W-1:0] p0_reg_response_status_field; + reg p0_reg_out_lock_field; + wire p1_valid; + reg p1_ready; + reg p1_startofpacket; + reg p1_endofpacket; + reg [IN_DATA_W-1:0] p1_data_field; + reg [IN_BYTEEN_W-1:0] p1_byteen_field; + reg [ADDRESS_W-1:0] p1_address_field; + reg [ADDRESS_W-1:0] out_address_field_mask; + reg [BYTE_CNT_W-1:0] p1_byte_cnt_field; + + reg [BURST_SIZE_W-1:0] p1_burst_size; + reg [BYTE_CNT_W-1:0] p1_byte_cnt_unpack_field; + wire response_data_packing; + reg [clogb2(RATIO)-1:0] p1_shift_correct_ouput_segments; + reg [clogb2(RATIO)-1:0] p1_push_data_to_output; + + reg p1_cmpr_read; + reg [RESPONSE_STATUS_W-1:0] p1_response_status_field; + reg unc_sink_valid; + wire unc_sink_ready; + wire unc_src_startofpacket; + wire unc_src_endofpacket; + wire unc_src_valid; + wire [ADDRESS_W-1:0] unc_src_addr; + wire [BYTE_CNT_W-1:0] unc_src_byte_cnt; + + wire aligned_addr; + wire aligned_byte_cnt; + wire unaligned_read; + + reg [BYTE_CNT_W-1:0] count; + reg count_eq_zero; + + wire [31:0] int_in_numsymbols = IN_NUMSYMBOLS; + wire [BYTE_CNT_W-1:0] byte_cnt_sized_in_num_symbols = + int_in_numsymbols[BYTE_CNT_W-1:0]; + reg [9:0] cmd_burst_size; + wire [31:0] out_numsymbols_wire = LOG_OUT_NUMSYMBOLS; + wire [31:0] int_encoded_burstsize = NW_BITFORSELECT_R; //NW_BITFORSELECT_R is the log2 of IN_NUMSYMBOLS + wire [BURST_SIZE_W-1:0] encoded_burstsize = int_encoded_burstsize[BURST_SIZE_W-1:0]; + + // Care about burstwrap on command path only + if (RESPONSE_PATH == 0) begin + assign in_burstwrap_field = in_data[IN_PKT_BURSTWRAP_H:IN_PKT_BURSTWRAP_L]; + end + else begin + assign in_burstwrap_field = {BWRAP_W{1'b1}}; + end + + // To use "read response merging" the Width adapter need to know the size of the command + // to check if downside happen. For AXI system, the fifo will store this number (non-packing: we use "combined width adapter") + // but in case system without AXI, the system use stand alone width adapter and it cannot read this value + // Make a condition incase we see stand alone WA, set this in_command_burst_size to input size + //wire [2:0] in_command_burst_size = out_numsymbols_wire[2:0]; + //if (!((PACKING == 1) & (CONSTANT_BURST_SIZE == 1))) // stand alone WA + // begin + // assign in_command_burst_size = in_command_size_data; + // end + reg [BURST_SIZE_W-1:0] in_ori_size_field; + always @* begin + in_ori_size_field = in_data[IN_PKT_ORI_BURST_SIZE_H :IN_PKT_ORI_BURST_SIZE_L ]; + end + + reg [9:0] size_ratio; + // -------------------------------------------- + // Stage 0: buffer the input cycle if read burst + // uncompression is going to happen. + // + // This avoids the possibility of a master receiving a premature + // response while its read burst is still being waitrequested. + // -------------------------------------------- + always @(posedge clk, posedge reset) begin + if (reset) begin + p0_use_reg <= 1'b0; + p0_reg_startofpacket <= 1'b0; + p0_reg_endofpacket <= 1'b0; + p0_reg_data_field <= '0; + p0_reg_bwrap_field <= '0; + p0_reg_byteen_field <= '0; + p0_reg_address_field <= '0; + p0_reg_byte_cnt_field <= '0; + p0_reg_cmpr_read <= 1'b0; + p0_reg_first_field <= '0; + p0_reg_mid_field <= '0; + p0_reg_last_field <= '0; + p0_reg_channel <= '0; + p0_reg_burst_size <= '0; + p0_reg_ori_burst_size <= '0; + p0_reg_out_lock_field <= '0; + p0_reg_burst_type_field <= '0; + p0_reg_response_status_field <= '0; + end else begin + if (unaligned_read & in_valid) + p0_use_reg <= 1'b1; + if (unc_src_endofpacket & p1_ready) + p0_use_reg <= 1'b0; + + if (unaligned_read) begin + p0_reg_startofpacket <= p0_startofpacket; + p0_reg_endofpacket <= p0_endofpacket; + p0_reg_data_field <= p0_data_field; + p0_reg_bwrap_field <= p0_bwrap_field; + p0_reg_byteen_field <= p0_byteen_field; + p0_reg_address_field <= p0_address_field; + p0_reg_byte_cnt_field <= p0_byte_cnt_field; + p0_reg_cmpr_read <= p0_cmpr_read; + p0_reg_first_field <= p0_first_field; + p0_reg_mid_field <= p0_mid_field; + p0_reg_last_field <= p0_last_field; + p0_reg_channel <= p0_channel; + p0_reg_burst_size <= p0_burst_size; + p0_reg_ori_burst_size <= p0_ori_burst_size; + p0_reg_out_lock_field <= p0_out_lock_field; + p0_reg_burst_type_field <= p0_burst_type_field; + p0_reg_response_status_field <= p0_response_status_field; + end + end + end + + always @* begin + in_ready = p1_ready; + + // accept on the first cycle + if (unaligned_read & in_valid & ~p0_use_reg) + in_ready = 1; + + if (p0_use_reg) + in_ready = 0; + end + + always @* begin + p0_startofpacket = in_startofpacket; + p0_endofpacket = in_endofpacket; + p0_data_field = in_data_field; + p0_bwrap_field = in_burstwrap_field; + p0_byteen_field = in_byteen_field; + //p0_address_field = in_address_field; + p0_address_field = address_for_adaptation; // read address from oacket + + p0_byte_cnt_field = in_byte_cnt_field; + p0_cmpr_read = in_cmpr_read; + p0_first_field = in_first_field; + p0_mid_field = in_mid_field; + p0_last_field = in_last_field; + p0_channel = in_channel; + p0_burst_size = in_size_field; + p0_ori_burst_size = in_ori_size_field; + p0_out_lock_field = in_lock_field; + p0_burst_type_field = in_burst_type_field; + p0_response_status_field = in_response_status_field; + if (p0_use_reg) begin + p0_startofpacket = p0_reg_startofpacket; + p0_endofpacket = p0_reg_endofpacket; + p0_data_field = p0_reg_data_field; + p0_bwrap_field = p0_reg_bwrap_field; + p0_byteen_field = p0_reg_byteen_field; + p0_address_field = p0_reg_address_field; + p0_byte_cnt_field = p0_reg_byte_cnt_field; + p0_cmpr_read = p0_reg_cmpr_read; + p0_first_field = p0_reg_first_field; + p0_mid_field = p0_reg_mid_field; + p0_last_field = p0_reg_last_field; + p0_channel = p0_reg_channel; + p0_burst_size = p0_reg_burst_size; + p0_ori_burst_size = p0_reg_ori_burst_size; + p0_out_lock_field = p0_reg_out_lock_field; + p0_burst_type_field = p0_reg_burst_type_field; + p0_response_status_field = p0_reg_response_status_field; + end + end + + assign p0_valid = in_valid | p0_use_reg; + + // -------------------------------------------- + // Stage 1: uncompress the input packet if necessary + // -------------------------------------------- + assign p1_valid = (unaligned_read) ? unc_src_valid : p0_valid; + assign aligned_addr = (p0_address_field[ALIGNED_BITS_L:0] == 0); + assign aligned_byte_cnt = (p0_byte_cnt_field[ALIGNED_BITS_L:0] == 0); + if ((RESPONSE_PATH == 0) && (PACKING == 1)) begin // if this is avalon then checking on aligned, + assign unaligned_read = p0_cmpr_read & (~aligned_addr || ~aligned_byte_cnt); + end else begin + assign unaligned_read = '0; + end + + always @* begin + p1_data_field = p0_data_field; + p1_byteen_field = p0_byteen_field; + p1_startofpacket = p0_startofpacket; + p1_endofpacket = p0_endofpacket; + p1_address_field = p0_address_field; + p1_byte_cnt_field = p0_byte_cnt_field; + p1_cmpr_read = p0_cmpr_read; + p1_response_status_field = p0_response_status_field; + p1_burst_size = p0_burst_size; + unc_sink_valid = 0; + + if (unaligned_read) begin + unc_sink_valid = p0_valid; + + p1_startofpacket = unc_src_startofpacket; + p1_endofpacket = unc_src_endofpacket; + p1_address_field = unc_src_addr; + p1_byte_cnt_field = unc_src_byte_cnt; + p1_cmpr_read = 0; + end + end + + altera_merlin_burst_uncompressor + #( + .ADDR_W (ADDRESS_W), + .BURSTWRAP_W (BWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (IN_NUMSYMBOLS), + .BURST_SIZE_W(BURST_SIZE_W) + ) uncompressor ( + .clk (clk), + .reset (reset), + + .sink_startofpacket (p0_startofpacket), + .sink_endofpacket (p0_endofpacket), + .sink_valid (unc_sink_valid), + .sink_ready (unc_sink_ready), + .sink_addr (p0_address_field), + .sink_burstwrap (p0_bwrap_field), + .sink_byte_cnt (p0_byte_cnt_field), + .sink_is_compressed (1'b1), // should always be compressed + .sink_burstsize (encoded_burstsize), + + .source_startofpacket (unc_src_startofpacket), + .source_endofpacket (unc_src_endofpacket), + .source_valid (unc_src_valid), + .source_ready (p1_ready), + .source_addr (unc_src_addr), + .source_burstwrap (), + .source_byte_cnt (unc_src_byte_cnt), + .source_is_compressed (), + .source_burstsize () + ); + + // -------------------------------------------- + // Stage 2: perform narrow to wide adaptation on the beats + // -------------------------------------------- + + always @(posedge clk, posedge reset) begin + if (reset) begin + data_reg <= '0; + byteen_reg <= '0; + startofpacket_reg <= '0; + count <= '0; + count_eq_zero <= '1; + response_status_reg <= '0; + end else begin + + if (p1_valid && (out_ready || ~out_valid)) begin + // Lay input data & input byte enables into + // the temp registers + data_reg <= data_reg | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + byteen_reg <= byteen_reg | (p1_byteen_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS)); + response_status_reg <= out_response_status_field; + // Capture the stuff that's to be held constant + if (count_eq_zero) begin + startofpacket_reg <= p1_startofpacket; + if (~p1_endofpacket) begin + count <= p1_byte_cnt_field - byte_cnt_sized_in_num_symbols; + count_eq_zero <= + ~|(p1_byte_cnt_field - byte_cnt_sized_in_num_symbols); + end + end else begin + count <= count - byte_cnt_sized_in_num_symbols; + count_eq_zero <= ~|(count - byte_cnt_sized_in_num_symbols); + end + + //if (p1_endofpacket || (p1_shift_correct_ouput_segments == '1)) begin + if (p1_endofpacket || (p1_push_data_to_output == '1)) begin + data_reg <= '0; + byteen_reg <= '0; + response_status_reg <= '0; + end + + if (out_valid && out_ready) begin + startofpacket_reg <= '0; + end + + end // if (p1_valid && (out_ready || ~out_valid)) + end // if (posedge clk) + end // always @ (clk, reset) + + always @* begin + // Handle narrow-size transaction from the master: + // The width of in_bitforselect is + // log2(OUT_NUM_SYMBOLS) - log2(IN_NUM_SYMBOLS) = + // log2(RATIO) + // The msb of in_bitforselect is driven by: in_adress_field[log2(OUT_NUMSYMBOLS) - 1] + // The lsb of in_adress_field is driven by: in_adress_field[log2(IN_NUMSYMBOLS)] + + // The function: mask_to_select_segments_for_size: is used to build a mask that changed at run-time + // when narrow-size transaction, It recaculates the width of in_bitforselect base on size ratio + + // EX: Full-size transaction (2 bytes)N-W: in_bitforselect = in_address[1:0] + // Narrow-size transaction(1 byte)N-W: in_bitforselect = {1, in_address[0]} + + p1_shift_correct_ouput_segments = p1_address_field[NW_BITFORSELECT_L:NW_BITFORSELECT_R]; + + // size ratio betwen command size and response size + //cmd_burst_size = bytes_in_transfer(in_command_burst_size); + cmd_burst_size = bytes_in_transfer(p0_ori_burst_size); + + size_ratio = cmd_burst_size >> in_size_field; + + if (RESPONSE_PATH == 0) begin + // if the WA is on command path, Avalon interconnect default + // bitselectfor data packing and push out data are same, compile time + p1_push_data_to_output = p1_shift_correct_ouput_segments; + end else begin + // the WA is on reponse path and default: PACKING = 1 + // on response path, need based on size, run-time, to determinite output segment + p1_push_data_to_output = mask_to_select_correct_segments_for_size(p1_shift_correct_ouput_segments, size_ratio, clogb2(RATIO)); + out_address_field_mask = choose_packed_address_base_on_size(size_ratio, clogb2(RATIO)); + end + + // We push data to the output whenever the input is + // an endofpacket, or the input drives the most-significant + // segment of the wider output word. + out_valid = 0; + if (PACKING == 1) begin + if (p1_endofpacket || (p1_push_data_to_output == '1)) begin + out_valid = p1_valid; + end + end else begin + out_valid = p1_valid; + end + + out_startofpacket = p1_startofpacket || startofpacket_reg; + out_endofpacket = p1_endofpacket; + + // Compressed read with byte_cnt > input interface width: + // this is a read burst spanning more than the originating + // interface of data, so all byteenables must be asserted. + if (p1_cmpr_read && (p1_byte_cnt_field > IN_NUMSYMBOLS)) begin + out_byteen_field = '1; + end else begin + if (PACKING == 1) begin // byteenable only affect on command path + out_byteen_field = byteen_reg | + (p1_byteen_field << (p1_shift_correct_ouput_segments*IN_NUMSYMBOLS)); + end else begin // non-packing: shift input byteenable to correct position + out_byteen_field = (p1_byteen_field << (p1_shift_correct_ouput_segments*IN_NUMSYMBOLS)); + end + end + + // caculate bytecnt "unpack" according to OUTNUMSYMBOLS + p1_byte_cnt_unpack_field = p1_byte_cnt_field << clogb2(RATIO); + out_address_field = p1_address_field; + + if (RESPONSE_PATH == 0) begin + if (PACKING == 1) begin // if the WA is on command path, Avalon interconnect default + out_data_field = data_reg | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_byte_cnt_field = quantized_byte_cnt_field; + out_address_field[NW_BITFORSELECT_L:0] = 0; + out_size_field = out_numsymbols_wire[BURST_SIZE_W-1:0]; // for Avalon the size is converted to slave side + end else begin + out_data_field = (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_byte_cnt_field = p1_byte_cnt_unpack_field; + out_size_field = p1_burst_size; + end + end else begin // the WA is on reponse path and default: PACKING = 1 + //if (in_size_field < in_command_burst_size) begin // downsize happen on command path, the response need packing + if (in_size_field < in_ori_size_field) begin // downsize happen on command path, the response need packing + out_data_field = data_reg + | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_address_field = p1_address_field & out_address_field_mask; + out_size_field = p1_burst_size; + out_byte_cnt_field = p1_byte_cnt_field; + end else begin // narrow transaction on command path, reponse packet will not packed + out_data_field = (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_byte_cnt_field = p1_byte_cnt_field; + out_size_field = p1_burst_size; + end + end + + //if (in_size_field < in_command_burst_size) begin // downsize happen on command path, the response need packing + if (in_size_field < in_ori_size_field) begin // downsize happen on command path, the response need packing + // Response merging: rules: DECERR(11) > SLVERR (10) > OKAY (00) + // EXOKAY will not happen on merging + out_response_status_field = '0; + if (response_status_reg >= p1_response_status_field) begin + out_response_status_field = response_status_reg; + end else begin + out_response_status_field = p1_response_status_field; + end + end else begin // narrow transaction on command path, reponse packet will not packed + out_response_status_field = p1_response_status_field; + end + + out_cmpr_read = p1_cmpr_read; + + // nothing touches these fields, so assign them + // directly from the input fields + out_first_field = p0_first_field; + out_mid_field = p0_mid_field; + out_last_field = p0_last_field; + out_lock_field = p0_out_lock_field; + out_channel = p0_channel; + out_burst_type_field = p0_burst_type_field; + end // always @ * + + //------------------------------------------------------- + // output byte_cnt, rounded up to alignment with the output-side + // address map footprint implied by the input-side access. + // + // See "option 3" in Appendix C of + // merlin_interconnect_architecture_fd_91.doc. + //------------------------------------------------------- + reg [NW_BITFORSELECT_L:0] low_addr_bits; + + always @* begin + low_addr_bits = p1_address_field[NW_BITFORSELECT_L:0]; + + quantized_byte_cnt_field = low_addr_bits + + p1_byte_cnt_field + + {clogb2(OUT_NUMSYMBOLS){1'b1}}; + quantized_byte_cnt_field[NW_BITFORSELECT_L:0] = '0; + end + + //------------------------------------------------------- + // Backpressure + //------------------------------------------------------- + always @ * begin + p1_ready = out_ready || ~out_valid; + end + + end // if (OUT_NUMSYMBOLS > IN_NUMSYMBOLS) + + //------------------------------------------------------- + //------------------------------------------------------- + // Same Width. Seems kind of silly, but let's be complete. + //------------------------------------------------------- + //------------------------------------------------------- + if (OUT_NUMSYMBOLS == IN_NUMSYMBOLS) begin + + always @* begin + in_ready = out_ready; + out_valid = in_valid; + out_channel = in_channel; + out_startofpacket = in_startofpacket; + out_endofpacket = in_endofpacket; + out_size_field = in_size_field; + out_data_field = in_data_field; + out_byteen_field = in_byteen_field; + out_address_field = in_address_field; + out_byte_cnt_field = in_byte_cnt_field; + out_response_status_field = in_response_status_field; + out_lock_field = in_lock_field; + out_burst_type_field = in_burst_type_field; + out_cmpr_read = in_cmpr_read; + out_first_field = in_first_field; + out_mid_field = in_mid_field; + out_last_field = in_last_field; + end // always @ * + + end // if (OUT_NUMSYMBOLS == IN_NUMSYMBOLS) + + endgenerate + + // --------------------------------------- + // Output Field Mapping + // + // Conditionally assign the pseudo-fields. Assign address and size + // last, because they partly override the pseudo-fields. + // --------------------------------------- + always @* begin + if (FIRST_EXISTS) + out_data[OUT_FIRST_H:OUT_FIRST_L] = out_first_field; + if (MID_EXISTS) + out_data[OUT_MID_H:OUT_MID_L] = out_mid_field; + if (LAST_EXISTS) + out_data[OUT_LAST_H:OUT_LAST_L] = out_last_field; + + out_data[OUT_PKT_BURST_SIZE_H : OUT_PKT_BURST_SIZE_L ] = out_size_field; + out_data[OUT_PKT_DATA_H : OUT_PKT_DATA_L ] = out_data_field; + out_data[OUT_PKT_BYTEEN_H : OUT_PKT_BYTEEN_L ] = out_byteen_field; + out_data[OUT_PKT_ADDR_H : OUT_PKT_ADDR_L ] = out_address_field; + out_data[OUT_PKT_BYTE_CNT_H : OUT_PKT_BYTE_CNT_L ] = out_byte_cnt_field; + out_data[OUT_PKT_TRANS_COMPRESSED_READ ] = out_cmpr_read; + out_data[OUT_PKT_TRANS_EXCLUSIVE ] = out_lock_field; + out_data[OUT_PKT_BURST_TYPE_H : OUT_PKT_BURST_TYPE_L ] = out_burst_type_field; + out_data[OUT_PKT_RESPONSE_STATUS_H : OUT_PKT_RESPONSE_STATUS_L] = out_response_status_field; + end // always @ * + +endmodule // width_adapter + diff --git a/ip/altera/ddr3/altera_reset_controller.sdc b/ip/altera/ddr3/altera_reset_controller.sdc new file mode 100644 index 0000000..cba3387 --- /dev/null +++ b/ip/altera/ddr3/altera_reset_controller.sdc @@ -0,0 +1,30 @@ +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +# +--------------------------------------------------- +# | Cut the async clear paths +# +--------------------------------------------------- +set aclr_counter 0 +set clrn_counter 0 +set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +set aclr_counter [get_collection_size $aclr_collection] +set clrn_counter [get_collection_size $clrn_collection] + +if {$aclr_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +} + +if {$clrn_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +} diff --git a/ip/altera/ddr3/altera_reset_controller.v b/ip/altera/ddr3/altera_reset_controller.v new file mode 100644 index 0000000..bfcbd6c --- /dev/null +++ b/ip/altera/ddr3/altera_reset_controller.v @@ -0,0 +1,319 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// ACDS13.1 - Added reset request as part of reset sequencing +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter USE_RESET_REQUEST_IN0 = 0, + parameter USE_RESET_REQUEST_IN1 = 0, + parameter USE_RESET_REQUEST_IN2 = 0, + parameter USE_RESET_REQUEST_IN3 = 0, + parameter USE_RESET_REQUEST_IN4 = 0, + parameter USE_RESET_REQUEST_IN5 = 0, + parameter USE_RESET_REQUEST_IN6 = 0, + parameter USE_RESET_REQUEST_IN7 = 0, + parameter USE_RESET_REQUEST_IN8 = 0, + parameter USE_RESET_REQUEST_IN9 = 0, + parameter USE_RESET_REQUEST_IN10 = 0, + parameter USE_RESET_REQUEST_IN11 = 0, + parameter USE_RESET_REQUEST_IN12 = 0, + parameter USE_RESET_REQUEST_IN13 = 0, + parameter USE_RESET_REQUEST_IN14 = 0, + parameter USE_RESET_REQUEST_IN15 = 0, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2, + parameter RESET_REQUEST_PRESENT = 0, + parameter RESET_REQ_WAIT_TIME = 3, + parameter MIN_RST_ASSERTION_TIME = 11, + parameter RESET_REQ_EARLY_DSRT_TIME = 4, + parameter ADAPT_RESET_REQUEST = 0 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + input reset_req_in0, + input reset_req_in1, + input reset_req_in2, + input reset_req_in3, + input reset_req_in4, + input reset_req_in5, + input reset_req_in6, + input reset_req_in7, + input reset_req_in8, + input reset_req_in9, + input reset_req_in10, + input reset_req_in11, + input reset_req_in12, + input reset_req_in13, + input reset_req_in14, + input reset_req_in15, + + + input clk, + output reg reset_out, + output reg reset_req +); + + // Always use async reset synchronizer if reset_req is used + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + // -------------------------------------- + // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1 + // -------------------------------------- + localparam MIN_METASTABLE = 3; + localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME; + + localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME; + + localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ? + MIN_RST_ASSERTION_TIME + 1 : + ( + (MIN_RST_ASSERTION_TIME > LARGER)? + MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 : + MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2 + ); + + localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1; + // -------------------------------------- + + wire merged_reset; + wire merged_reset_req_in; + wire reset_out_pre; + wire reset_req_pre; + + // Registers and Interconnect + (*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain; + reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain; + reg r_sync_rst; + reg r_early_rst; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + assign merged_reset_req_in = ( + ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) | + ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) | + ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) | + ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) | + ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) | + ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) | + ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) | + ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) | + ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) | + ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) | + ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) | + ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) | + ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) | + ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) | + ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) | + ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) + ); + + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin + + assign reset_out_pre = merged_reset; + assign reset_req_pre = merged_reset_req_in; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out_pre) + ); + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(0) + ) + alt_rst_req_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset_req_in), + .reset_out (reset_req_pre) + ); + + end + endgenerate + + generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )| + ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin + always @* begin + reset_out = reset_out_pre; + reset_req = reset_req_pre; + end + end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin + + wire reset_out_pre2; + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH+1), + .ASYNC_RESET(0) + ) + alt_rst_sync_uq2 + ( + .clk (clk), + .reset_in (reset_out_pre), + .reset_out (reset_out_pre2) + ); + + always @* begin + reset_out = reset_out_pre2; + reset_req = reset_req_pre; + end + + end + else begin + + // 3-FF Metastability Synchronizer + initial + begin + altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}}; + end + + always @(posedge clk) + begin + altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= + {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; + end + + // Synchronous reset pipe + initial + begin + r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; + end + + always @(posedge clk) + begin + if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1) + begin + r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]}; + end + end + + // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition + // matches the early input. + + always @(posedge clk) + begin + case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; // Not reset + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; // In Reset + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre}) + 2'b00: r_early_rst <= 1'b0; // Not reset + 2'b01: r_early_rst <= 1'b1; // Coming out of reset + 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. + 2'b11: r_early_rst <= 1'b1; // Held in reset + default: r_early_rst <= 1'b1; + endcase + end + + always @* begin + reset_out = r_sync_rst; + reset_req = r_early_rst; + end + + end + endgenerate + +endmodule diff --git a/ip/altera/ddr3/altera_reset_synchronizer.v b/ip/altera/ddr3/altera_reset_synchronizer.v new file mode 100644 index 0000000..5cb5cdc --- /dev/null +++ b/ip/altera/ddr3/altera_reset_synchronizer.v @@ -0,0 +1,87 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/ip/altera/ddr3/altera_std_synchronizer_nocut.v b/ip/altera/ddr3/altera_std_synchronizer_nocut.v new file mode 100644 index 0000000..9b5b6a9 --- /dev/null +++ b/ip/altera/ddr3/altera_std_synchronizer_nocut.v @@ -0,0 +1,165 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $ +// $Revision: #8 $ +// $Date: 2009/02/18 $ +// $Author: pscheidt $ +//----------------------------------------------------------------------------- +// +// File: altera_std_synchronizer_nocut.v +// +// Abstract: Single bit clock domain crossing synchronizer. Exactly the same +// as altera_std_synchronizer.v, except that the embedded false +// path constraint is removed in this module. If you use this +// module, you will have to apply the appropriate timing +// constraints. +// +// We expect to make this a standard Quartus atom eventually. +// +// Composed of two or more flip flops connected in series. +// Random metastable condition is simulated when the +// __ALTERA_STD__METASTABLE_SIM macro is defined. +// Use +define+__ALTERA_STD__METASTABLE_SIM argument +// on the Verilog simulator compiler command line to +// enable this mode. In addition, define the macro +// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output +// with every metastable event generated in the synchronizer. +// +// Copyright (C) Altera Corporation 2009, All Rights Reserved +//----------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +module altera_std_synchronizer_nocut ( + clk, + reset_n, + din, + dout + ); + + parameter depth = 3; // This value must be >= 2 ! + + input clk; + input reset_n; + input din; + output dout; + + // QuartusII synthesis directives: + // 1. Preserve all registers ie. do not touch them. + // 2. Do not merge other flip-flops with synchronizer flip-flops. + // QuartusII TimeQuest directives: + // 1. Identify all flip-flops in this module as members of the synchronizer + // to enable automatic metastability MTBF analysis. + + (* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1; + + (* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg; + + //synthesis translate_off + initial begin + if (depth <2) begin + $display("%m: Error: synchronizer length: %0d less than 2.", depth); + end + end + + // the first synchronizer register is either a simple D flop for synthesis + // and non-metastable simulation or a D flop with a method to inject random + // metastable events resulting in random delay of [0,1] cycles + +`ifdef __ALTERA_STD__METASTABLE_SIM + + reg[31:0] RANDOM_SEED = 123456; + wire next_din_s1; + wire dout; + reg din_last; + reg random; + event metastable_event; // hook for debug monitoring + + initial begin + $display("%m: Info: Metastable event injection simulation mode enabled"); + end + + always @(posedge clk) begin + if (reset_n == 0) + random <= $random(RANDOM_SEED); + else + random <= $random; + end + + assign next_din_s1 = (din_last ^ din) ? random : din; + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_last <= 1'b0; + else + din_last <= din; + end + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b0; + else + din_s1 <= next_din_s1; + end + +`else + + //synthesis translate_on + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b0; + else + din_s1 <= din; + end + //synthesis translate_off + +`endif + +`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE + always @(*) begin + if (reset_n && (din_last != din) && (random != din)) begin + $display("%m: Verbose Info: metastable event @ time %t", $time); + ->metastable_event; + end + end +`endif + + //synthesis translate_on + + // the remaining synchronizer registers form a simple shift register + // of length depth-1 + generate + if (depth < 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= din_s1; + end + end else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= {dreg[depth-3:0], din_s1}; + end + end + endgenerate + + assign dout = dreg[depth-2]; + +endmodule + + + diff --git a/ip/altera/ddr3/altera_wrap_burst_converter.sv b/ip/altera/ddr3/altera_wrap_burst_converter.sv new file mode 100644 index 0000000..8a85a88 --- /dev/null +++ b/ip/altera/ddr3/altera_wrap_burst_converter.sv @@ -0,0 +1,335 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_burst_adapter/new_source/altera_wrap_burst_converter.sv#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------ +// This component is specially for Wrapping Avalon slave. +// It converts burst length of input packet +// to match slave burst. +// ------------------------------------------------------ + +`timescale 1 ns / 1 ns + +module altera_wrap_burst_converter +#( + parameter + // ---------------------------------------- + // Burst length Parameters + // (real burst length value, not bytecount) + // ---------------------------------------- + MAX_IN_LEN = 16, + MAX_OUT_LEN = 4, + ADDR_WIDTH = 12, + BNDRY_WIDTH = 12, + NUM_SYMBOLS = 4, + AXI_SLAVE = 0, + OPTIMIZE_WRITE_BURST = 0, + // ------------------ + // Derived Parameters + // ------------------ + LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1, + OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1, + LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS) +) +( + input clk, + input reset, + input enable_write, + input enable_read, + + input [LEN_WIDTH - 1 : 0] in_len, + input [LEN_WIDTH - 1 : 0] first_len, + input in_sop, + + input [ADDR_WIDTH - 1 : 0] in_addr, + input [ADDR_WIDTH - 1 : 0] in_addr_reg, + input [BNDRY_WIDTH - 1 : 0] in_boundary, + input [BNDRY_WIDTH - 1 : 0] in_burstwrap, + input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg, + + // converted output length + // out_len : compressed burst, read + // uncompressed_len: uncompressed, write + output reg [LEN_WIDTH - 1 : 0] out_len, + output reg [LEN_WIDTH - 1 : 0] uncompr_out_len, + + // Compressed address output + output reg [ADDR_WIDTH - 1 : 0] out_addr, + output reg new_burst_export +); + + // ------------------------------ + // Local parameters + // ------------------------------ + localparam + OUT_BOUNDARY = MAX_OUT_LEN * NUM_SYMBOLS, + ADDR_SEL = log2ceil(OUT_BOUNDARY); + + // ---------------------------------------- + // Signals for wrapping support + // ---------------------------------------- + reg [LEN_WIDTH - 1 : 0] remaining_len; + reg [LEN_WIDTH - 1 : 0] next_out_len; + reg [LEN_WIDTH - 1 : 0] next_rem_len; + reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len; + reg new_burst; + reg uncompr_sub_burst; + reg [LEN_WIDTH - 1 : 0] next_uncompr_out_len; + reg [LEN_WIDTH - 1 : 0] next_uncompr_sub_len; + + // Avoid QIS warning + wire [OUT_LEN_WIDTH - 1 : 0] max_out_length; + assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0]; + + // ---------------------------------------- + // Calculate aligned length for WRAP burst + // ---------------------------------------- + reg [ADDR_WIDTH - 1 : 0] extended_burstwrap; + reg [ADDR_WIDTH - 1 : 0] extended_burstwrap_reg; + + always_comb begin + extended_burstwrap = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap[BNDRY_WIDTH - 1]}}, in_burstwrap}; + extended_burstwrap_reg = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap_reg[BNDRY_WIDTH - 1]}}, in_burstwrap_reg}; + new_burst_export = new_burst; + end + + // ------------------------------------------- + // length calculation + // ------------------------------------------- + reg [LEN_WIDTH -1 : 0] next_uncompr_remaining_len; + always_comb begin + // Signals name + // *_uncompr_* --> uncompressed transaction + // ------------------------------------------- + // Always use max_out_length as possible. + // Else use the remaining length. + // If in length smaller and not cross bndry or same, pass thru. + + if (in_sop) begin + uncompr_remaining_len = in_len; + end + else begin + uncompr_remaining_len = next_uncompr_remaining_len; + end + end // always_comb + + // compressed transactions + always_comb begin : proc_compressed_read + remaining_len = in_len; + if (!new_burst) + remaining_len = next_rem_len; + end + + always_comb begin + next_uncompr_out_len = first_len; + if (in_sop) begin + next_uncompr_out_len = first_len; + end + else begin + if (uncompr_sub_burst) + next_uncompr_out_len = next_uncompr_sub_len; + else begin + if (uncompr_remaining_len < max_out_length) + next_uncompr_out_len = uncompr_remaining_len; + else + next_uncompr_out_len = max_out_length; + end + end + end + + // Compressed transaction: Always try to send MAX out_len then remaining length. + // Seperate it as the main difference is the first out len. + // For a WRAP burst, the first beat is the aligned length, then similar to INCR. + always_comb begin + if (new_burst) begin + next_out_len = first_len; + end + else begin + next_out_len = max_out_length; + if (remaining_len < max_out_length) begin + next_out_len = remaining_len; + end + end + end // always_comb + + // -------------------------------------------------- + // Length remaining calculation : Compressed + // -------------------------------------------------- + // length remaining for compressed transaction + // for wrap, need special handling for first out length + + always_ff @(posedge clk, posedge reset) begin + if (reset) + next_rem_len <= 0; + else if (enable_read) begin + if (new_burst) + next_rem_len <= in_len - first_len; + else + next_rem_len <= next_rem_len - max_out_length; + end + end // always_ff @ + + // -------------------------------------------------- + // Length remaining calculation : Uncompressed + // -------------------------------------------------- + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + next_uncompr_remaining_len <= 0; + end + else if (enable_write) begin + if (in_sop) + next_uncompr_remaining_len <= in_len - first_len; + else if (!uncompr_sub_burst) + next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length; + end + end // always_ff @ + + // length for each sub-burst if it needs to chop the burst + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + next_uncompr_sub_len <= 0; + end + else if (enable_write) begin + next_uncompr_sub_len <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1 + end + end + + // the sub-burst still active + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + uncompr_sub_burst <= 0; + end + else if (enable_write) begin + uncompr_sub_burst <= (next_uncompr_out_len > 1'b1); + end + end + + // -------------------------------------------------- + // Control signals + // -------------------------------------------------- + wire end_compressed_sub_burst; + assign end_compressed_sub_burst = (remaining_len == next_out_len); + + // new_burst: + // the converter takes in_len for new caculation + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + new_burst <= 1; + end + else if (enable_read) begin + new_burst <= end_compressed_sub_burst; + end + end + + // -------------------------------------------------- + // Output length + // -------------------------------------------------- + // register out_len for compressed trans + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + out_len <= 0; + end + else if (enable_read) begin + out_len <= next_out_len; + end + end + + // register uncompr_out_len for uncompressed trans + generate + if (OPTIMIZE_WRITE_BURST) begin : optimized_write_burst_len + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + uncompr_out_len <= '0; + end + //else if (enable_write) begin + else if (enable_read) begin + uncompr_out_len <= first_len; + end + end + end + else begin : unoptimized_write_burst_len + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + uncompr_out_len <= '0; + end + else if (enable_write) begin + uncompr_out_len <= next_uncompr_out_len; + end + end + end + endgenerate + + // -------------------------------------------------- + // Address calculation + // -------------------------------------------------- + reg [ADDR_WIDTH - 1 : 0] addr_incr; + localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS; + assign addr_incr = ADDR_INCR[ADDR_WIDTH - 1 : 0]; + + reg [ADDR_WIDTH - 1 : 0] next_out_addr; + reg [ADDR_WIDTH - 1 : 0] incremented_addr; + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + out_addr <= '0; + end + else begin + if (enable_read) begin + out_addr <= (next_out_addr); + end + end + end // always_ff @ + + // use burstwrap/burstwrap_reg to calculate address incrementing + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + incremented_addr <= '0; + end + else if (enable_read) begin + incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg); + if (new_burst) begin + incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address + end + end + end // always_ff @ + + always_comb begin + next_out_addr = in_addr; + if (!new_burst) begin + next_out_addr = in_addr_reg & ~extended_burstwrap_reg | incremented_addr; + end + end + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + reg[31:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i[30:0] << 1; + end + end + endfunction + +endmodule diff --git a/ip/altera/ddr3/ddr3_0002.v b/ip/altera/ddr3/ddr3_0002.v new file mode 100644 index 0000000..be070b5 --- /dev/null +++ b/ip/altera/ddr3/ddr3_0002.v @@ -0,0 +1,1086 @@ +// ddr3_0002.v + +// This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_0002 ( + input wire pll_ref_clk, // pll_ref_clk.clk + input wire global_reset_n, // global_reset.reset_n + input wire soft_reset_n, // soft_reset.reset_n + output wire afi_clk, // afi_clk.clk + output wire afi_half_clk, // afi_half_clk.clk + output wire afi_reset_n, // afi_reset.reset_n + output wire afi_reset_export_n, // afi_reset_export.reset_n + output wire [12:0] mem_a, // memory.mem_a + output wire [2:0] mem_ba, // .mem_ba + output wire [0:0] mem_ck, // .mem_ck + output wire [0:0] mem_ck_n, // .mem_ck_n + output wire [0:0] mem_cke, // .mem_cke + output wire [0:0] mem_cs_n, // .mem_cs_n + output wire [1:0] mem_dm, // .mem_dm + output wire [0:0] mem_ras_n, // .mem_ras_n + output wire [0:0] mem_cas_n, // .mem_cas_n + output wire [0:0] mem_we_n, // .mem_we_n + output wire mem_reset_n, // .mem_reset_n + inout wire [15:0] mem_dq, // .mem_dq + inout wire [1:0] mem_dqs, // .mem_dqs + inout wire [1:0] mem_dqs_n, // .mem_dqs_n + output wire [0:0] mem_odt, // .mem_odt + output wire avl_ready_0, // avl_0.waitrequest_n + input wire avl_burstbegin_0, // .beginbursttransfer + input wire [24:0] avl_addr_0, // .address + output wire avl_rdata_valid_0, // .readdatavalid + output wire [31:0] avl_rdata_0, // .readdata + input wire [31:0] avl_wdata_0, // .writedata + input wire [3:0] avl_be_0, // .byteenable + input wire avl_read_req_0, // .read + input wire avl_write_req_0, // .write + input wire [2:0] avl_size_0, // .burstcount + input wire mp_cmd_clk_0_clk, // mp_cmd_clk_0.clk + input wire mp_cmd_reset_n_0_reset_n, // mp_cmd_reset_n_0.reset_n + input wire mp_rfifo_clk_0_clk, // mp_rfifo_clk_0.clk + input wire mp_rfifo_reset_n_0_reset_n, // mp_rfifo_reset_n_0.reset_n + input wire mp_wfifo_clk_0_clk, // mp_wfifo_clk_0.clk + input wire mp_wfifo_reset_n_0_reset_n, // mp_wfifo_reset_n_0.reset_n + input wire csr_clk, // csr_clk.clk + input wire csr_reset_n, // csr_reset_n.reset_n + output wire local_init_done, // status.local_init_done + output wire local_cal_success, // .local_cal_success + output wire local_cal_fail, // .local_cal_fail + input wire oct_rzqin, // oct.rzqin + output wire pll_mem_clk, // pll_sharing.pll_mem_clk + output wire pll_write_clk, // .pll_write_clk + output wire pll_locked, // .pll_locked + output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk + output wire pll_addr_cmd_clk, // .pll_addr_cmd_clk + output wire pll_avl_clk, // .pll_avl_clk + output wire pll_config_clk, // .pll_config_clk + output wire pll_mem_phy_clk, // .pll_mem_phy_clk + output wire afi_phy_clk, // .afi_phy_clk + output wire pll_avl_phy_clk // .pll_avl_phy_clk + ); + + wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat + wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success + wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata + wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat + wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail + wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid + wire p0_avl_clk_clk; // p0:avl_clk -> [dmaster:clk_clk, mm_interconnect_1:p0_avl_clk_clk, s0:avl_clk] + wire p0_avl_reset_reset; // p0:avl_reset_n -> [dmaster:clk_reset_reset, mm_interconnect_1:dmaster_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:dmaster_master_translator_reset_reset_bridge_in_reset_reset, s0:avl_reset_n] + wire p0_scc_clk_clk; // p0:scc_clk -> s0:scc_clk + wire p0_scc_reset_reset; // p0:scc_reset_n -> s0:reset_n_scc_clk + wire [15:0] s0_scc_scc_dq_ena; // s0:scc_dq_ena -> p0:scc_dq_ena + wire [0:0] s0_scc_scc_upd; // s0:scc_upd -> p0:scc_upd + wire [1:0] s0_scc_scc_dqs_io_ena; // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena + wire [1:0] s0_scc_scc_dm_ena; // s0:scc_dm_ena -> p0:scc_dm_ena + wire [1:0] p0_scc_capture_strobe_tracking; // p0:capture_strobe_tracking -> s0:capture_strobe_tracking + wire [1:0] s0_scc_scc_dqs_ena; // s0:scc_dqs_ena -> p0:scc_dqs_ena + wire [0:0] s0_scc_scc_data; // s0:scc_data -> p0:scc_data + wire [31:0] s0_avl_readdata; // p0:avl_readdata -> s0:avl_readdata + wire s0_avl_waitrequest; // p0:avl_waitrequest -> s0:avl_waitrequest + wire [15:0] s0_avl_address; // s0:avl_address -> p0:avl_address + wire s0_avl_read; // s0:avl_read -> p0:avl_read + wire s0_avl_write; // s0:avl_write -> p0:avl_write + wire [31:0] s0_avl_writedata; // s0:avl_writedata -> p0:avl_writedata + wire dmaster_master_reset_reset; // dmaster:master_reset_reset -> p0:csr_soft_reset_req + wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full + wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid + wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n + wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata + wire c0_afi_afi_cal_req; // c0:afi_cal_req -> s0:afi_cal_req + wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst + wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr + wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba + wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm + wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable + wire c0_afi_afi_init_req; // c0:afi_init_req -> s0:afi_init_req + wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n + wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n + wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n + wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en + wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt + wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n + wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke + wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd + wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig + wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth + wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth + wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi + wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl + wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth + wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth + wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc + wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat + wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth + wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth + wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr + wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat + wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk + wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n + wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail + wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess + wire [15:0] oct0_oct_sharing_parallelterminationcontrol; // oct0:parallelterminationcontrol -> p0:parallelterminationcontrol + wire [15:0] oct0_oct_sharing_seriesterminationcontrol; // oct0:seriesterminationcontrol -> p0:seriesterminationcontrol + wire p0_dll_clk_clk; // p0:dll_clk -> dll0:clk + wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll0:dll_pll_locked + wire [6:0] dll0_dll_sharing_dll_delayctrl; // dll0:dll_delayctrl -> p0:dll_delayctrl + wire [31:0] dmaster_master_readdata; // mm_interconnect_1:dmaster_master_readdata -> dmaster:master_readdata + wire dmaster_master_waitrequest; // mm_interconnect_1:dmaster_master_waitrequest -> dmaster:master_waitrequest + wire [31:0] dmaster_master_address; // dmaster:master_address -> mm_interconnect_1:dmaster_master_address + wire dmaster_master_read; // dmaster:master_read -> mm_interconnect_1:dmaster_master_read + wire [3:0] dmaster_master_byteenable; // dmaster:master_byteenable -> mm_interconnect_1:dmaster_master_byteenable + wire dmaster_master_readdatavalid; // mm_interconnect_1:dmaster_master_readdatavalid -> dmaster:master_readdatavalid + wire dmaster_master_write; // dmaster:master_write -> mm_interconnect_1:dmaster_master_write + wire [31:0] dmaster_master_writedata; // dmaster:master_writedata -> mm_interconnect_1:dmaster_master_writedata + wire [31:0] mm_interconnect_1_s0_seq_debug_readdata; // s0:seq_readdata -> mm_interconnect_1:s0_seq_debug_readdata + wire mm_interconnect_1_s0_seq_debug_waitrequest; // s0:seq_waitrequest -> mm_interconnect_1:s0_seq_debug_waitrequest + wire [31:0] mm_interconnect_1_s0_seq_debug_address; // mm_interconnect_1:s0_seq_debug_address -> s0:seq_address + wire mm_interconnect_1_s0_seq_debug_read; // mm_interconnect_1:s0_seq_debug_read -> s0:seq_read + wire [3:0] mm_interconnect_1_s0_seq_debug_byteenable; // mm_interconnect_1:s0_seq_debug_byteenable -> s0:seq_byteenable + wire mm_interconnect_1_s0_seq_debug_readdatavalid; // s0:seq_readdatavalid -> mm_interconnect_1:s0_seq_debug_readdatavalid + wire mm_interconnect_1_s0_seq_debug_write; // mm_interconnect_1:s0_seq_debug_write -> s0:seq_write + wire [31:0] mm_interconnect_1_s0_seq_debug_writedata; // mm_interconnect_1:s0_seq_debug_writedata -> s0:seq_writedata + wire [0:0] mm_interconnect_1_s0_seq_debug_burstcount; // mm_interconnect_1:s0_seq_debug_burstcount -> s0:seq_burstcount + wire [31:0] if_csr_m0_master_readdata; // mm_interconnect_2:if_csr_m0_master_readdata -> if_csr_m0:master_readdata + wire if_csr_m0_master_waitrequest; // mm_interconnect_2:if_csr_m0_master_waitrequest -> if_csr_m0:master_waitrequest + wire [31:0] if_csr_m0_master_address; // if_csr_m0:master_address -> mm_interconnect_2:if_csr_m0_master_address + wire if_csr_m0_master_read; // if_csr_m0:master_read -> mm_interconnect_2:if_csr_m0_master_read + wire [3:0] if_csr_m0_master_byteenable; // if_csr_m0:master_byteenable -> mm_interconnect_2:if_csr_m0_master_byteenable + wire if_csr_m0_master_readdatavalid; // mm_interconnect_2:if_csr_m0_master_readdatavalid -> if_csr_m0:master_readdatavalid + wire if_csr_m0_master_write; // if_csr_m0:master_write -> mm_interconnect_2:if_csr_m0_master_write + wire [31:0] if_csr_m0_master_writedata; // if_csr_m0:master_writedata -> mm_interconnect_2:if_csr_m0_master_writedata + wire [31:0] mm_interconnect_2_p0_csr_readdata; // p0:csr_rdata -> mm_interconnect_2:p0_csr_readdata + wire mm_interconnect_2_p0_csr_waitrequest; // p0:csr_waitrequest -> mm_interconnect_2:p0_csr_waitrequest + wire [7:0] mm_interconnect_2_p0_csr_address; // mm_interconnect_2:p0_csr_address -> p0:csr_addr + wire mm_interconnect_2_p0_csr_read; // mm_interconnect_2:p0_csr_read -> p0:csr_read_req + wire [3:0] mm_interconnect_2_p0_csr_byteenable; // mm_interconnect_2:p0_csr_byteenable -> p0:csr_be + wire mm_interconnect_2_p0_csr_readdatavalid; // p0:csr_rdata_valid -> mm_interconnect_2:p0_csr_readdatavalid + wire mm_interconnect_2_p0_csr_write; // mm_interconnect_2:p0_csr_write -> p0:csr_write_req + wire [31:0] mm_interconnect_2_p0_csr_writedata; // mm_interconnect_2:p0_csr_writedata -> p0:csr_wdata + wire [7:0] mm_interconnect_2_c0_csr_readdata; // c0:csr_rdata -> mm_interconnect_2:c0_csr_readdata + wire mm_interconnect_2_c0_csr_waitrequest; // c0:csr_waitrequest -> mm_interconnect_2:c0_csr_waitrequest + wire [9:0] mm_interconnect_2_c0_csr_address; // mm_interconnect_2:c0_csr_address -> c0:csr_addr + wire mm_interconnect_2_c0_csr_read; // mm_interconnect_2:c0_csr_read -> c0:csr_read_req + wire [0:0] mm_interconnect_2_c0_csr_byteenable; // mm_interconnect_2:c0_csr_byteenable -> c0:csr_be + wire mm_interconnect_2_c0_csr_readdatavalid; // c0:csr_rdata_valid -> mm_interconnect_2:c0_csr_readdatavalid + wire mm_interconnect_2_c0_csr_write; // mm_interconnect_2:c0_csr_write -> c0:csr_write_req + wire [7:0] mm_interconnect_2_c0_csr_writedata; // mm_interconnect_2:c0_csr_writedata -> c0:csr_wdata + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [c0:csr_reset_n, mm_interconnect_2:if_csr_m0_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:p0_csr_reset_n_reset_bridge_in_reset_reset, p0:csr_reset_n] + + ddr3_pll0 pll0 ( + .global_reset_n (global_reset_n), // global_reset.reset_n + .afi_clk (afi_clk), // afi_clk.clk + .afi_half_clk (afi_half_clk), // afi_half_clk.clk + .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk + .pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk + .pll_write_clk (pll_write_clk), // .pll_write_clk + .pll_locked (pll_locked), // .pll_locked + .pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk + .pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk + .pll_avl_clk (pll_avl_clk), // .pll_avl_clk + .pll_config_clk (pll_config_clk), // .pll_config_clk + .pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk + .afi_phy_clk (afi_phy_clk), // .afi_phy_clk + .pll_avl_phy_clk (pll_avl_phy_clk) // .pll_avl_phy_clk + ); + + ddr3_p0 p0 ( + .global_reset_n (global_reset_n), // global_reset.reset_n + .soft_reset_n (soft_reset_n), // soft_reset.reset_n + .csr_soft_reset_req (dmaster_master_reset_reset), // csr_soft_reset_req.reset + .afi_reset_n (afi_reset_n), // afi_reset.reset_n + .afi_reset_export_n (afi_reset_export_n), // afi_reset_export.reset_n + .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n + .afi_clk (afi_clk), // afi_clk.clk + .afi_half_clk (afi_half_clk), // afi_half_clk.clk + .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk + .avl_clk (p0_avl_clk_clk), // avl_clk.clk + .avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n + .scc_clk (p0_scc_clk_clk), // scc_clk.clk + .scc_reset_n (p0_scc_reset_reset), // scc_reset.reset_n + .avl_address (s0_avl_address), // avl.address + .avl_write (s0_avl_write), // .write + .avl_writedata (s0_avl_writedata), // .writedata + .avl_read (s0_avl_read), // .read + .avl_readdata (s0_avl_readdata), // .readdata + .avl_waitrequest (s0_avl_waitrequest), // .waitrequest + .dll_clk (p0_dll_clk_clk), // dll_clk.clk + .afi_addr (c0_afi_afi_addr), // afi.afi_addr + .afi_ba (c0_afi_afi_ba), // .afi_ba + .afi_cke (c0_afi_afi_cke), // .afi_cke + .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n + .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n + .afi_we_n (c0_afi_afi_we_n), // .afi_we_n + .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n + .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n + .afi_odt (c0_afi_afi_odt), // .afi_odt + .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst + .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid + .afi_wdata (c0_afi_afi_wdata), // .afi_wdata + .afi_dm (c0_afi_afi_dm), // .afi_dm + .afi_rdata (p0_afi_afi_rdata), // .afi_rdata + .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en + .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full + .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid + .afi_wlat (p0_afi_afi_wlat), // .afi_wlat + .afi_rlat (p0_afi_afi_rlat), // .afi_rlat + .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success + .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail + .scc_data (s0_scc_scc_data), // scc.scc_data + .scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena + .scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena + .scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena + .scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena + .capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking + .scc_upd (s0_scc_scc_upd), // .scc_upd + .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat + .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth + .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat + .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth + .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth + .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth + .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig + .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth + .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth + .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl + .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd + .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi + .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc + .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr + .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable + .pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk + .pll_write_clk (pll_write_clk), // .pll_write_clk + .pll_locked (pll_locked), // .pll_locked + .pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk + .pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk + .pll_avl_clk (pll_avl_clk), // .pll_avl_clk + .pll_config_clk (pll_config_clk), // .pll_config_clk + .pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk + .afi_phy_clk (afi_phy_clk), // .afi_phy_clk + .pll_avl_phy_clk (pll_avl_phy_clk), // .pll_avl_phy_clk + .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked + .dll_delayctrl (dll0_dll_sharing_dll_delayctrl), // .dll_delayctrl + .seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol + .parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol + .mem_a (mem_a), // memory.mem_a + .mem_ba (mem_ba), // .mem_ba + .mem_ck (mem_ck), // .mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_dm (mem_dm), // .mem_dm + .mem_ras_n (mem_ras_n), // .mem_ras_n + .mem_cas_n (mem_cas_n), // .mem_cas_n + .mem_we_n (mem_we_n), // .mem_we_n + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_dq (mem_dq), // .mem_dq + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_odt (mem_odt), // .mem_odt + .csr_clk (csr_clk), // csr_clk.clk + .csr_reset_n (~rst_controller_reset_out_reset), // csr_reset_n.reset_n + .csr_write_req (mm_interconnect_2_p0_csr_write), // csr.write + .csr_read_req (mm_interconnect_2_p0_csr_read), // .read + .csr_waitrequest (mm_interconnect_2_p0_csr_waitrequest), // .waitrequest + .csr_addr (mm_interconnect_2_p0_csr_address), // .address + .csr_be (mm_interconnect_2_p0_csr_byteenable), // .byteenable + .csr_wdata (mm_interconnect_2_p0_csr_writedata), // .writedata + .csr_rdata (mm_interconnect_2_p0_csr_readdata), // .readdata + .csr_rdata_valid (mm_interconnect_2_p0_csr_readdatavalid), // .readdatavalid + .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail + .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess + .io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .io_intbadout (12'b000000000000), // (terminated) + .io_intcasndout (4'b0000), // (terminated) + .io_intckdout (4'b0000), // (terminated) + .io_intckedout (8'b00000000), // (terminated) + .io_intckndout (4'b0000), // (terminated) + .io_intcsndout (8'b00000000), // (terminated) + .io_intdmdout (20'b00000000000000000000), // (terminated) + .io_intdqdin (), // (terminated) + .io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .io_intdqsbdout (20'b00000000000000000000), // (terminated) + .io_intdqsboe (10'b0000000000), // (terminated) + .io_intdqsdout (20'b00000000000000000000), // (terminated) + .io_intdqslogicdqsena (10'b0000000000), // (terminated) + .io_intdqslogicfiforeset (5'b00000), // (terminated) + .io_intdqslogicincrdataen (10'b0000000000), // (terminated) + .io_intdqslogicincwrptr (10'b0000000000), // (terminated) + .io_intdqslogicoct (10'b0000000000), // (terminated) + .io_intdqslogicrdatavalid (), // (terminated) + .io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated) + .io_intdqsoe (10'b0000000000), // (terminated) + .io_intodtdout (8'b00000000), // (terminated) + .io_intrasndout (4'b0000), // (terminated) + .io_intresetndout (4'b0000), // (terminated) + .io_intwendout (4'b0000), // (terminated) + .io_intafirlat (), // (terminated) + .io_intafiwlat () // (terminated) + ); + + ddr3_s0 s0 ( + .avl_clk (p0_avl_clk_clk), // avl_clk.clk + .avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n + .scc_clk (p0_scc_clk_clk), // scc_clk.clk + .reset_n_scc_clk (p0_scc_reset_reset), // scc_reset.reset_n + .scc_data (s0_scc_scc_data), // scc.scc_data + .scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena + .scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena + .scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena + .scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena + .capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking + .scc_upd (s0_scc_scc_upd), // .scc_upd + .afi_init_req (c0_afi_afi_init_req), // afi_init_cal_req.afi_init_req + .afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req + .avl_address (s0_avl_address), // avl.address + .avl_write (s0_avl_write), // .write + .avl_writedata (s0_avl_writedata), // .writedata + .avl_read (s0_avl_read), // .read + .avl_readdata (s0_avl_readdata), // .readdata + .avl_waitrequest (s0_avl_waitrequest), // .waitrequest + .seq_waitrequest (mm_interconnect_1_s0_seq_debug_waitrequest), // seq_debug.waitrequest + .seq_readdata (mm_interconnect_1_s0_seq_debug_readdata), // .readdata + .seq_readdatavalid (mm_interconnect_1_s0_seq_debug_readdatavalid), // .readdatavalid + .seq_burstcount (mm_interconnect_1_s0_seq_debug_burstcount), // .burstcount + .seq_writedata (mm_interconnect_1_s0_seq_debug_writedata), // .writedata + .seq_address (mm_interconnect_1_s0_seq_debug_address), // .address + .seq_write (mm_interconnect_1_s0_seq_debug_write), // .write + .seq_read (mm_interconnect_1_s0_seq_debug_read), // .read + .seq_byteenable (mm_interconnect_1_s0_seq_debug_byteenable), // .byteenable + .seq_debugaccess (1'b0) // (terminated) + ); + + ddr3_dmaster #( + .USE_PLI (0), + .PLI_PORT (50000), + .FIFO_DEPTHS (2) + ) dmaster ( + .clk_clk (p0_avl_clk_clk), // clk.clk + .clk_reset_reset (~p0_avl_reset_reset), // clk_reset.reset + .master_address (dmaster_master_address), // master.address + .master_readdata (dmaster_master_readdata), // .readdata + .master_read (dmaster_master_read), // .read + .master_write (dmaster_master_write), // .write + .master_writedata (dmaster_master_writedata), // .writedata + .master_waitrequest (dmaster_master_waitrequest), // .waitrequest + .master_readdatavalid (dmaster_master_readdatavalid), // .readdatavalid + .master_byteenable (dmaster_master_byteenable), // .byteenable + .master_reset_reset (dmaster_master_reset_reset) // master_reset.reset + ); + + altera_mem_if_hard_memory_controller_top_cyclonev #( + .MEM_IF_DQS_WIDTH (2), + .MEM_IF_CS_WIDTH (1), + .MEM_IF_CHIP_BITS (1), + .MEM_IF_CLK_PAIR_COUNT (1), + .CSR_ADDR_WIDTH (10), + .CSR_DATA_WIDTH (8), + .CSR_BE_WIDTH (1), + .AVL_ADDR_WIDTH (25), + .AVL_DATA_WIDTH (32), + .AVL_SIZE_WIDTH (3), + .AVL_DATA_WIDTH_PORT_0 (32), + .AVL_ADDR_WIDTH_PORT_0 (25), + .AVL_NUM_SYMBOLS_PORT_0 (4), + .LSB_WFIFO_PORT_0 (0), + .MSB_WFIFO_PORT_0 (0), + .LSB_RFIFO_PORT_0 (0), + .MSB_RFIFO_PORT_0 (0), + .AVL_DATA_WIDTH_PORT_1 (1), + .AVL_ADDR_WIDTH_PORT_1 (1), + .AVL_NUM_SYMBOLS_PORT_1 (1), + .LSB_WFIFO_PORT_1 (5), + .MSB_WFIFO_PORT_1 (5), + .LSB_RFIFO_PORT_1 (5), + .MSB_RFIFO_PORT_1 (5), + .AVL_DATA_WIDTH_PORT_2 (1), + .AVL_ADDR_WIDTH_PORT_2 (1), + .AVL_NUM_SYMBOLS_PORT_2 (1), + .LSB_WFIFO_PORT_2 (5), + .MSB_WFIFO_PORT_2 (5), + .LSB_RFIFO_PORT_2 (5), + .MSB_RFIFO_PORT_2 (5), + .AVL_DATA_WIDTH_PORT_3 (1), + .AVL_ADDR_WIDTH_PORT_3 (1), + .AVL_NUM_SYMBOLS_PORT_3 (1), + .LSB_WFIFO_PORT_3 (5), + .MSB_WFIFO_PORT_3 (5), + .LSB_RFIFO_PORT_3 (5), + .MSB_RFIFO_PORT_3 (5), + .AVL_DATA_WIDTH_PORT_4 (1), + .AVL_ADDR_WIDTH_PORT_4 (1), + .AVL_NUM_SYMBOLS_PORT_4 (1), + .LSB_WFIFO_PORT_4 (5), + .MSB_WFIFO_PORT_4 (5), + .LSB_RFIFO_PORT_4 (5), + .MSB_RFIFO_PORT_4 (5), + .AVL_DATA_WIDTH_PORT_5 (1), + .AVL_ADDR_WIDTH_PORT_5 (1), + .AVL_NUM_SYMBOLS_PORT_5 (1), + .LSB_WFIFO_PORT_5 (5), + .MSB_WFIFO_PORT_5 (5), + .LSB_RFIFO_PORT_5 (5), + .MSB_RFIFO_PORT_5 (5), + .ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"), + .ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"), + .ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"), + .ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"), + .ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"), + .ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"), + .ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"), + .ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"), + .ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"), + .ENUM_CAL_REQ ("DISABLED"), + .ENUM_CFG_BURST_LENGTH ("BL_8"), + .ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_16"), + .ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"), + .ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_4"), + .ENUM_CFG_TYPE ("DDR3"), + .ENUM_CLOCK_OFF_0 ("DISABLED"), + .ENUM_CLOCK_OFF_1 ("DISABLED"), + .ENUM_CLOCK_OFF_2 ("DISABLED"), + .ENUM_CLOCK_OFF_3 ("DISABLED"), + .ENUM_CLOCK_OFF_4 ("DISABLED"), + .ENUM_CLOCK_OFF_5 ("DISABLED"), + .ENUM_CLR_INTR ("NO_CLR_INTR"), + .ENUM_CMD_PORT_IN_USE_0 ("TRUE"), + .ENUM_CMD_PORT_IN_USE_1 ("FALSE"), + .ENUM_CMD_PORT_IN_USE_2 ("FALSE"), + .ENUM_CMD_PORT_IN_USE_3 ("FALSE"), + .ENUM_CMD_PORT_IN_USE_4 ("FALSE"), + .ENUM_CMD_PORT_IN_USE_5 ("FALSE"), + .ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_CPORT0_RFIFO_MAP ("FIFO_0"), + .ENUM_CPORT0_TYPE ("BI_DIRECTION"), + .ENUM_CPORT0_WFIFO_MAP ("FIFO_0"), + .ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_CPORT1_RFIFO_MAP ("FIFO_0"), + .ENUM_CPORT1_TYPE ("DISABLE"), + .ENUM_CPORT1_WFIFO_MAP ("FIFO_0"), + .ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_CPORT2_RFIFO_MAP ("FIFO_0"), + .ENUM_CPORT2_TYPE ("DISABLE"), + .ENUM_CPORT2_WFIFO_MAP ("FIFO_0"), + .ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_CPORT3_RFIFO_MAP ("FIFO_0"), + .ENUM_CPORT3_TYPE ("DISABLE"), + .ENUM_CPORT3_WFIFO_MAP ("FIFO_0"), + .ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_CPORT4_RFIFO_MAP ("FIFO_0"), + .ENUM_CPORT4_TYPE ("DISABLE"), + .ENUM_CPORT4_WFIFO_MAP ("FIFO_0"), + .ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_CPORT5_RFIFO_MAP ("FIFO_0"), + .ENUM_CPORT5_TYPE ("DISABLE"), + .ENUM_CPORT5_WFIFO_MAP ("FIFO_0"), + .ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"), + .ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"), + .ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"), + .ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"), + .ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"), + .ENUM_CTRL_WIDTH ("DATA_WIDTH_32_BIT"), + .ENUM_DELAY_BONDING ("BONDING_LATENCY_0"), + .ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"), + .ENUM_DISABLE_MERGING ("MERGING_ENABLED"), + .ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"), + .ENUM_ENABLE_ATPG ("DISABLED"), + .ENUM_ENABLE_BONDING_0 ("DISABLED"), + .ENUM_ENABLE_BONDING_1 ("DISABLED"), + .ENUM_ENABLE_BONDING_2 ("DISABLED"), + .ENUM_ENABLE_BONDING_3 ("DISABLED"), + .ENUM_ENABLE_BONDING_4 ("DISABLED"), + .ENUM_ENABLE_BONDING_5 ("DISABLED"), + .ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"), + .ENUM_ENABLE_DQS_TRACKING ("DISABLED"), + .ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"), + .ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"), + .ENUM_ENABLE_INTR ("DISABLED"), + .ENUM_ENABLE_NO_DM ("DISABLED"), + .ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"), + .ENUM_GANGED_ARF ("DISABLED"), + .ENUM_GEN_DBE ("GEN_DBE_DISABLED"), + .ENUM_GEN_SBE ("GEN_SBE_DISABLED"), + .ENUM_INC_SYNC ("FIFO_SET_2"), + .ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"), + .ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"), + .ENUM_MASK_DBE_INTR ("DISABLED"), + .ENUM_MASK_SBE_INTR ("DISABLED"), + .ENUM_MEM_IF_AL ("AL_0"), + .ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"), + .ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"), + .ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"), + .ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"), + .ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"), + .ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"), + .ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_2"), + .ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_16"), + .ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"), + .ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_13"), + .ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"), + .ENUM_MEM_IF_TCCD ("TCCD_4"), + .ENUM_MEM_IF_TCL ("TCL_7"), + .ENUM_MEM_IF_TCWL ("TCWL_6"), + .ENUM_MEM_IF_TFAW ("TFAW_14"), + .ENUM_MEM_IF_TMRD ("TMRD_4"), + .ENUM_MEM_IF_TRAS ("TRAS_11"), + .ENUM_MEM_IF_TRC ("TRC_15"), + .ENUM_MEM_IF_TRCD ("TRCD_5"), + .ENUM_MEM_IF_TRP ("TRP_5"), + .ENUM_MEM_IF_TRRD ("TRRD_3"), + .ENUM_MEM_IF_TRTP ("TRTP_3"), + .ENUM_MEM_IF_TWR ("TWR_5"), + .ENUM_MEM_IF_TWTR ("TWTR_5"), + .ENUM_MMR_CFG_MEM_BL ("MP_BL_8"), + .ENUM_OUTPUT_REGD ("DISABLED"), + .ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"), + .ENUM_PORT0_WIDTH ("PORT_32_BIT"), + .ENUM_PORT1_WIDTH ("PORT_32_BIT"), + .ENUM_PORT2_WIDTH ("PORT_32_BIT"), + .ENUM_PORT3_WIDTH ("PORT_32_BIT"), + .ENUM_PORT4_WIDTH ("PORT_32_BIT"), + .ENUM_PORT5_WIDTH ("PORT_32_BIT"), + .ENUM_PRIORITY_0_0 ("WEIGHT_0"), + .ENUM_PRIORITY_0_1 ("WEIGHT_0"), + .ENUM_PRIORITY_0_2 ("WEIGHT_0"), + .ENUM_PRIORITY_0_3 ("WEIGHT_0"), + .ENUM_PRIORITY_0_4 ("WEIGHT_0"), + .ENUM_PRIORITY_0_5 ("WEIGHT_0"), + .ENUM_PRIORITY_1_0 ("WEIGHT_0"), + .ENUM_PRIORITY_1_1 ("WEIGHT_0"), + .ENUM_PRIORITY_1_2 ("WEIGHT_0"), + .ENUM_PRIORITY_1_3 ("WEIGHT_0"), + .ENUM_PRIORITY_1_4 ("WEIGHT_0"), + .ENUM_PRIORITY_1_5 ("WEIGHT_0"), + .ENUM_PRIORITY_2_0 ("WEIGHT_0"), + .ENUM_PRIORITY_2_1 ("WEIGHT_0"), + .ENUM_PRIORITY_2_2 ("WEIGHT_0"), + .ENUM_PRIORITY_2_3 ("WEIGHT_0"), + .ENUM_PRIORITY_2_4 ("WEIGHT_0"), + .ENUM_PRIORITY_2_5 ("WEIGHT_0"), + .ENUM_PRIORITY_3_0 ("WEIGHT_0"), + .ENUM_PRIORITY_3_1 ("WEIGHT_0"), + .ENUM_PRIORITY_3_2 ("WEIGHT_0"), + .ENUM_PRIORITY_3_3 ("WEIGHT_0"), + .ENUM_PRIORITY_3_4 ("WEIGHT_0"), + .ENUM_PRIORITY_3_5 ("WEIGHT_0"), + .ENUM_PRIORITY_4_0 ("WEIGHT_0"), + .ENUM_PRIORITY_4_1 ("WEIGHT_0"), + .ENUM_PRIORITY_4_2 ("WEIGHT_0"), + .ENUM_PRIORITY_4_3 ("WEIGHT_0"), + .ENUM_PRIORITY_4_4 ("WEIGHT_0"), + .ENUM_PRIORITY_4_5 ("WEIGHT_0"), + .ENUM_PRIORITY_5_0 ("WEIGHT_0"), + .ENUM_PRIORITY_5_1 ("WEIGHT_0"), + .ENUM_PRIORITY_5_2 ("WEIGHT_0"), + .ENUM_PRIORITY_5_3 ("WEIGHT_0"), + .ENUM_PRIORITY_5_4 ("WEIGHT_0"), + .ENUM_PRIORITY_5_5 ("WEIGHT_0"), + .ENUM_PRIORITY_6_0 ("WEIGHT_0"), + .ENUM_PRIORITY_6_1 ("WEIGHT_0"), + .ENUM_PRIORITY_6_2 ("WEIGHT_0"), + .ENUM_PRIORITY_6_3 ("WEIGHT_0"), + .ENUM_PRIORITY_6_4 ("WEIGHT_0"), + .ENUM_PRIORITY_6_5 ("WEIGHT_0"), + .ENUM_PRIORITY_7_0 ("WEIGHT_0"), + .ENUM_PRIORITY_7_1 ("WEIGHT_0"), + .ENUM_PRIORITY_7_2 ("WEIGHT_0"), + .ENUM_PRIORITY_7_3 ("WEIGHT_0"), + .ENUM_PRIORITY_7_4 ("WEIGHT_0"), + .ENUM_PRIORITY_7_5 ("WEIGHT_0"), + .ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"), + .ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"), + .ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"), + .ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"), + .ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"), + .ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"), + .ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"), + .ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"), + .ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"), + .ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"), + .ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"), + .ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"), + .ENUM_RD_DWIDTH_0 ("DWIDTH_32"), + .ENUM_RD_DWIDTH_1 ("DWIDTH_0"), + .ENUM_RD_DWIDTH_2 ("DWIDTH_0"), + .ENUM_RD_DWIDTH_3 ("DWIDTH_0"), + .ENUM_RD_DWIDTH_4 ("DWIDTH_0"), + .ENUM_RD_DWIDTH_5 ("DWIDTH_0"), + .ENUM_RD_FIFO_IN_USE_0 ("TRUE"), + .ENUM_RD_FIFO_IN_USE_1 ("FALSE"), + .ENUM_RD_FIFO_IN_USE_2 ("FALSE"), + .ENUM_RD_FIFO_IN_USE_3 ("FALSE"), + .ENUM_RD_PORT_INFO_0 ("USE_0"), + .ENUM_RD_PORT_INFO_1 ("USE_NO"), + .ENUM_RD_PORT_INFO_2 ("USE_NO"), + .ENUM_RD_PORT_INFO_3 ("USE_NO"), + .ENUM_RD_PORT_INFO_4 ("USE_NO"), + .ENUM_RD_PORT_INFO_5 ("USE_NO"), + .ENUM_READ_ODT_CHIP ("ODT_DISABLED"), + .ENUM_REORDER_DATA ("NO_DATA_REORDERING"), + .ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"), + .ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"), + .ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"), + .ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"), + .ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"), + .ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"), + .ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"), + .ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"), + .ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"), + .ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"), + .ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"), + .ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"), + .ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"), + .ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"), + .ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"), + .ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"), + .ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"), + .ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"), + .ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"), + .ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"), + .ENUM_TEST_MODE ("NORMAL_MODE"), + .ENUM_THLD_JAR1_0 ("THRESHOLD_32"), + .ENUM_THLD_JAR1_1 ("THRESHOLD_32"), + .ENUM_THLD_JAR1_2 ("THRESHOLD_32"), + .ENUM_THLD_JAR1_3 ("THRESHOLD_32"), + .ENUM_THLD_JAR1_4 ("THRESHOLD_32"), + .ENUM_THLD_JAR1_5 ("THRESHOLD_32"), + .ENUM_THLD_JAR2_0 ("THRESHOLD_16"), + .ENUM_THLD_JAR2_1 ("THRESHOLD_16"), + .ENUM_THLD_JAR2_2 ("THRESHOLD_16"), + .ENUM_THLD_JAR2_3 ("THRESHOLD_16"), + .ENUM_THLD_JAR2_4 ("THRESHOLD_16"), + .ENUM_THLD_JAR2_5 ("THRESHOLD_16"), + .ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"), + .ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"), + .ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"), + .ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"), + .ENUM_USER_ECC_EN ("DISABLE"), + .ENUM_USER_PRIORITY_0 ("PRIORITY_1"), + .ENUM_USER_PRIORITY_1 ("PRIORITY_1"), + .ENUM_USER_PRIORITY_2 ("PRIORITY_1"), + .ENUM_USER_PRIORITY_3 ("PRIORITY_1"), + .ENUM_USER_PRIORITY_4 ("PRIORITY_1"), + .ENUM_USER_PRIORITY_5 ("PRIORITY_1"), + .ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"), + .ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"), + .ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"), + .ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"), + .ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"), + .ENUM_WR_DWIDTH_0 ("DWIDTH_32"), + .ENUM_WR_DWIDTH_1 ("DWIDTH_0"), + .ENUM_WR_DWIDTH_2 ("DWIDTH_0"), + .ENUM_WR_DWIDTH_3 ("DWIDTH_0"), + .ENUM_WR_DWIDTH_4 ("DWIDTH_0"), + .ENUM_WR_DWIDTH_5 ("DWIDTH_0"), + .ENUM_WR_FIFO_IN_USE_0 ("TRUE"), + .ENUM_WR_FIFO_IN_USE_1 ("FALSE"), + .ENUM_WR_FIFO_IN_USE_2 ("FALSE"), + .ENUM_WR_FIFO_IN_USE_3 ("FALSE"), + .ENUM_WR_PORT_INFO_0 ("USE_0"), + .ENUM_WR_PORT_INFO_1 ("USE_NO"), + .ENUM_WR_PORT_INFO_2 ("USE_NO"), + .ENUM_WR_PORT_INFO_3 ("USE_NO"), + .ENUM_WR_PORT_INFO_4 ("USE_NO"), + .ENUM_WR_PORT_INFO_5 ("USE_NO"), + .ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"), + .INTG_MEM_AUTO_PD_CYCLES (0), + .INTG_CYC_TO_RLD_JARS_0 (1), + .INTG_CYC_TO_RLD_JARS_1 (1), + .INTG_CYC_TO_RLD_JARS_2 (1), + .INTG_CYC_TO_RLD_JARS_3 (1), + .INTG_CYC_TO_RLD_JARS_4 (1), + .INTG_CYC_TO_RLD_JARS_5 (1), + .INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0), + .INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0), + .INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0), + .INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0), + .INTG_EXTRA_CTL_CLK_ARF_PERIOD (0), + .INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0), + .INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0), + .INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0), + .INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0), + .INTG_EXTRA_CTL_CLK_PDN_PERIOD (0), + .INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0), + .INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0), + .INTG_EXTRA_CTL_CLK_RD_TO_PCH (0), + .INTG_EXTRA_CTL_CLK_RD_TO_RD (0), + .INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0), + .INTG_EXTRA_CTL_CLK_RD_TO_WR (2), + .INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2), + .INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2), + .INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0), + .INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0), + .INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0), + .INTG_EXTRA_CTL_CLK_WR_TO_PCH (0), + .INTG_EXTRA_CTL_CLK_WR_TO_RD (3), + .INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3), + .INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3), + .INTG_EXTRA_CTL_CLK_WR_TO_WR (0), + .INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0), + .INTG_MEM_IF_TREFI (2341), + .INTG_MEM_IF_TRFC (34), + .INTG_RCFG_SUM_WT_PRIORITY_0 (0), + .INTG_RCFG_SUM_WT_PRIORITY_1 (0), + .INTG_RCFG_SUM_WT_PRIORITY_2 (0), + .INTG_RCFG_SUM_WT_PRIORITY_3 (0), + .INTG_RCFG_SUM_WT_PRIORITY_4 (0), + .INTG_RCFG_SUM_WT_PRIORITY_5 (0), + .INTG_RCFG_SUM_WT_PRIORITY_6 (0), + .INTG_RCFG_SUM_WT_PRIORITY_7 (0), + .INTG_SUM_WT_PRIORITY_0 (0), + .INTG_SUM_WT_PRIORITY_1 (0), + .INTG_SUM_WT_PRIORITY_2 (0), + .INTG_SUM_WT_PRIORITY_3 (0), + .INTG_SUM_WT_PRIORITY_4 (0), + .INTG_SUM_WT_PRIORITY_5 (0), + .INTG_SUM_WT_PRIORITY_6 (0), + .INTG_SUM_WT_PRIORITY_7 (0), + .INTG_POWER_SAVING_EXIT_CYCLES (5), + .INTG_MEM_CLK_ENTRY_CYCLES (10), + .ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"), + .ENUM_ENABLE_BURST_TERMINATE ("DISABLED"), + .AFI_RATE_RATIO (1), + .AFI_ADDR_WIDTH (13), + .AFI_BANKADDR_WIDTH (3), + .AFI_CONTROL_WIDTH (1), + .AFI_CS_WIDTH (1), + .AFI_DM_WIDTH (4), + .AFI_DQ_WIDTH (32), + .AFI_ODT_WIDTH (1), + .AFI_WRITE_DQS_WIDTH (2), + .AFI_RLAT_WIDTH (6), + .AFI_WLAT_WIDTH (6), + .HARD_PHY (1) + ) c0 ( + .afi_clk (afi_clk), // afi_clk.clk + .afi_reset_n (afi_reset_n), // afi_reset.reset_n + .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n + .afi_half_clk (afi_half_clk), // afi_half_clk.clk + .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk + .mp_cmd_clk_0 (mp_cmd_clk_0_clk), // mp_cmd_clk_0.clk + .mp_cmd_reset_n_0 (mp_cmd_reset_n_0_reset_n), // mp_cmd_reset_n_0.reset_n + .mp_rfifo_clk_0 (mp_rfifo_clk_0_clk), // mp_rfifo_clk_0.clk + .mp_rfifo_reset_n_0 (mp_rfifo_reset_n_0_reset_n), // mp_rfifo_reset_n_0.reset_n + .mp_wfifo_clk_0 (mp_wfifo_clk_0_clk), // mp_wfifo_clk_0.clk + .mp_wfifo_reset_n_0 (mp_wfifo_reset_n_0_reset_n), // mp_wfifo_reset_n_0.reset_n + .csr_clk (csr_clk), // csr_clk.clk + .csr_reset_n (~rst_controller_reset_out_reset), // csr_reset_n.reset_n + .avl_ready_0 (avl_ready_0), // avl_0.waitrequest_n + .avl_burstbegin_0 (avl_burstbegin_0), // .beginbursttransfer + .avl_addr_0 (avl_addr_0), // .address + .avl_rdata_valid_0 (avl_rdata_valid_0), // .readdatavalid + .avl_rdata_0 (avl_rdata_0), // .readdata + .avl_wdata_0 (avl_wdata_0), // .writedata + .avl_be_0 (avl_be_0), // .byteenable + .avl_read_req_0 (avl_read_req_0), // .read + .avl_write_req_0 (avl_write_req_0), // .write + .avl_size_0 (avl_size_0), // .burstcount + .local_init_done (local_init_done), // status.local_init_done + .local_cal_success (local_cal_success), // .local_cal_success + .local_cal_fail (local_cal_fail), // .local_cal_fail + .csr_write_req (mm_interconnect_2_c0_csr_write), // csr.write + .csr_read_req (mm_interconnect_2_c0_csr_read), // .read + .csr_waitrequest (mm_interconnect_2_c0_csr_waitrequest), // .waitrequest + .csr_addr (mm_interconnect_2_c0_csr_address), // .address + .csr_be (mm_interconnect_2_c0_csr_byteenable), // .byteenable + .csr_wdata (mm_interconnect_2_c0_csr_writedata), // .writedata + .csr_rdata (mm_interconnect_2_c0_csr_readdata), // .readdata + .csr_rdata_valid (mm_interconnect_2_c0_csr_readdatavalid), // .readdatavalid + .afi_addr (c0_afi_afi_addr), // afi.afi_addr + .afi_ba (c0_afi_afi_ba), // .afi_ba + .afi_cke (c0_afi_afi_cke), // .afi_cke + .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n + .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n + .afi_we_n (c0_afi_afi_we_n), // .afi_we_n + .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n + .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n + .afi_odt (c0_afi_afi_odt), // .afi_odt + .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable + .afi_init_req (c0_afi_afi_init_req), // .afi_init_req + .afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req + .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst + .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid + .afi_wdata (c0_afi_afi_wdata), // .afi_wdata + .afi_dm (c0_afi_afi_dm), // .afi_dm + .afi_rdata (p0_afi_afi_rdata), // .afi_rdata + .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en + .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full + .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid + .afi_wlat (p0_afi_afi_wlat), // .afi_wlat + .afi_rlat (p0_afi_afi_rlat), // .afi_rlat + .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success + .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail + .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat + .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth + .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat + .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth + .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth + .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth + .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig + .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth + .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth + .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl + .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd + .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi + .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc + .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr + .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail + .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess + .mp_cmd_clk_1 (1'b0), // (terminated) + .mp_cmd_reset_n_1 (1'b1), // (terminated) + .mp_cmd_clk_2 (1'b0), // (terminated) + .mp_cmd_reset_n_2 (1'b1), // (terminated) + .mp_cmd_clk_3 (1'b0), // (terminated) + .mp_cmd_reset_n_3 (1'b1), // (terminated) + .mp_cmd_clk_4 (1'b0), // (terminated) + .mp_cmd_reset_n_4 (1'b1), // (terminated) + .mp_cmd_clk_5 (1'b0), // (terminated) + .mp_cmd_reset_n_5 (1'b1), // (terminated) + .mp_rfifo_clk_1 (1'b0), // (terminated) + .mp_rfifo_reset_n_1 (1'b1), // (terminated) + .mp_wfifo_clk_1 (1'b0), // (terminated) + .mp_wfifo_reset_n_1 (1'b1), // (terminated) + .mp_rfifo_clk_2 (1'b0), // (terminated) + .mp_rfifo_reset_n_2 (1'b1), // (terminated) + .mp_wfifo_clk_2 (1'b0), // (terminated) + .mp_wfifo_reset_n_2 (1'b1), // (terminated) + .mp_rfifo_clk_3 (1'b0), // (terminated) + .mp_rfifo_reset_n_3 (1'b1), // (terminated) + .mp_wfifo_clk_3 (1'b0), // (terminated) + .mp_wfifo_reset_n_3 (1'b1), // (terminated) + .avl_ready_1 (), // (terminated) + .avl_burstbegin_1 (1'b0), // (terminated) + .avl_addr_1 (1'b0), // (terminated) + .avl_rdata_valid_1 (), // (terminated) + .avl_rdata_1 (), // (terminated) + .avl_wdata_1 (1'b0), // (terminated) + .avl_be_1 (1'b0), // (terminated) + .avl_read_req_1 (1'b0), // (terminated) + .avl_write_req_1 (1'b0), // (terminated) + .avl_size_1 (3'b000), // (terminated) + .avl_ready_2 (), // (terminated) + .avl_burstbegin_2 (1'b0), // (terminated) + .avl_addr_2 (1'b0), // (terminated) + .avl_rdata_valid_2 (), // (terminated) + .avl_rdata_2 (), // (terminated) + .avl_wdata_2 (1'b0), // (terminated) + .avl_be_2 (1'b0), // (terminated) + .avl_read_req_2 (1'b0), // (terminated) + .avl_write_req_2 (1'b0), // (terminated) + .avl_size_2 (3'b000), // (terminated) + .avl_ready_3 (), // (terminated) + .avl_burstbegin_3 (1'b0), // (terminated) + .avl_addr_3 (1'b0), // (terminated) + .avl_rdata_valid_3 (), // (terminated) + .avl_rdata_3 (), // (terminated) + .avl_wdata_3 (1'b0), // (terminated) + .avl_be_3 (1'b0), // (terminated) + .avl_read_req_3 (1'b0), // (terminated) + .avl_write_req_3 (1'b0), // (terminated) + .avl_size_3 (3'b000), // (terminated) + .avl_ready_4 (), // (terminated) + .avl_burstbegin_4 (1'b0), // (terminated) + .avl_addr_4 (1'b0), // (terminated) + .avl_rdata_valid_4 (), // (terminated) + .avl_rdata_4 (), // (terminated) + .avl_wdata_4 (1'b0), // (terminated) + .avl_be_4 (1'b0), // (terminated) + .avl_read_req_4 (1'b0), // (terminated) + .avl_write_req_4 (1'b0), // (terminated) + .avl_size_4 (3'b000), // (terminated) + .avl_ready_5 (), // (terminated) + .avl_burstbegin_5 (1'b0), // (terminated) + .avl_addr_5 (1'b0), // (terminated) + .avl_rdata_valid_5 (), // (terminated) + .avl_rdata_5 (), // (terminated) + .avl_wdata_5 (1'b0), // (terminated) + .avl_be_5 (1'b0), // (terminated) + .avl_read_req_5 (1'b0), // (terminated) + .avl_write_req_5 (1'b0), // (terminated) + .avl_size_5 (3'b000), // (terminated) + .afi_seq_busy (1'b0), // (terminated) + .afi_ctl_refresh_done (), // (terminated) + .afi_ctl_long_idle (), // (terminated) + .local_multicast (1'b0), // (terminated) + .local_refresh_req (1'b0), // (terminated) + .local_refresh_chip (1'b0), // (terminated) + .local_refresh_ack (), // (terminated) + .local_self_rfsh_req (1'b0), // (terminated) + .local_self_rfsh_chip (1'b0), // (terminated) + .local_self_rfsh_ack (), // (terminated) + .local_deep_powerdn_req (1'b0), // (terminated) + .local_deep_powerdn_chip (1'b0), // (terminated) + .local_deep_powerdn_ack (), // (terminated) + .local_powerdn_ack (), // (terminated) + .local_priority (1'b0), // (terminated) + .bonding_in_1 (4'b0000), // (terminated) + .bonding_in_2 (6'b000000), // (terminated) + .bonding_in_3 (6'b000000), // (terminated) + .bonding_out_1 (), // (terminated) + .bonding_out_2 (), // (terminated) + .bonding_out_3 () // (terminated) + ); + + altera_mem_if_oct_cyclonev #( + .OCT_TERM_CONTROL_WIDTH (16) + ) oct0 ( + .oct_rzqin (oct_rzqin), // oct.rzqin + .seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol + .parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol + ); + + altera_mem_if_dll_cyclonev #( + .DLL_DELAY_CTRL_WIDTH (7), + .DLL_OFFSET_CTRL_WIDTH (6), + .DELAY_BUFFER_MODE ("HIGH"), + .DELAY_CHAIN_LENGTH (8), + .DLL_INPUT_FREQUENCY_PS_STR ("3333 ps") + ) dll0 ( + .clk (p0_dll_clk_clk), // clk.clk + .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked + .dll_delayctrl (dll0_dll_sharing_dll_delayctrl) // .dll_delayctrl + ); + + ddr3_dmaster #( + .USE_PLI (0), + .PLI_PORT (50000), + .FIFO_DEPTHS (2) + ) if_csr_m0 ( + .clk_clk (csr_clk), // clk.clk + .clk_reset_reset (~csr_reset_n), // clk_reset.reset + .master_address (if_csr_m0_master_address), // master.address + .master_readdata (if_csr_m0_master_readdata), // .readdata + .master_read (if_csr_m0_master_read), // .read + .master_write (if_csr_m0_master_write), // .write + .master_writedata (if_csr_m0_master_writedata), // .writedata + .master_waitrequest (if_csr_m0_master_waitrequest), // .waitrequest + .master_readdatavalid (if_csr_m0_master_readdatavalid), // .readdatavalid + .master_byteenable (if_csr_m0_master_byteenable), // .byteenable + .master_reset_reset () // master_reset.reset + ); + + ddr3_mm_interconnect_1 mm_interconnect_1 ( + .p0_avl_clk_clk (p0_avl_clk_clk), // p0_avl_clk.clk + .dmaster_clk_reset_reset_bridge_in_reset_reset (~p0_avl_reset_reset), // dmaster_clk_reset_reset_bridge_in_reset.reset + .dmaster_master_translator_reset_reset_bridge_in_reset_reset (~p0_avl_reset_reset), // dmaster_master_translator_reset_reset_bridge_in_reset.reset + .dmaster_master_address (dmaster_master_address), // dmaster_master.address + .dmaster_master_waitrequest (dmaster_master_waitrequest), // .waitrequest + .dmaster_master_byteenable (dmaster_master_byteenable), // .byteenable + .dmaster_master_read (dmaster_master_read), // .read + .dmaster_master_readdata (dmaster_master_readdata), // .readdata + .dmaster_master_readdatavalid (dmaster_master_readdatavalid), // .readdatavalid + .dmaster_master_write (dmaster_master_write), // .write + .dmaster_master_writedata (dmaster_master_writedata), // .writedata + .s0_seq_debug_address (mm_interconnect_1_s0_seq_debug_address), // s0_seq_debug.address + .s0_seq_debug_write (mm_interconnect_1_s0_seq_debug_write), // .write + .s0_seq_debug_read (mm_interconnect_1_s0_seq_debug_read), // .read + .s0_seq_debug_readdata (mm_interconnect_1_s0_seq_debug_readdata), // .readdata + .s0_seq_debug_writedata (mm_interconnect_1_s0_seq_debug_writedata), // .writedata + .s0_seq_debug_burstcount (mm_interconnect_1_s0_seq_debug_burstcount), // .burstcount + .s0_seq_debug_byteenable (mm_interconnect_1_s0_seq_debug_byteenable), // .byteenable + .s0_seq_debug_readdatavalid (mm_interconnect_1_s0_seq_debug_readdatavalid), // .readdatavalid + .s0_seq_debug_waitrequest (mm_interconnect_1_s0_seq_debug_waitrequest) // .waitrequest + ); + + ddr3_mm_interconnect_2 mm_interconnect_2 ( + .csr_clk_out_clk_clk (csr_clk), // csr_clk_out_clk.clk + .if_csr_m0_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // if_csr_m0_clk_reset_reset_bridge_in_reset.reset + .p0_csr_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // p0_csr_reset_n_reset_bridge_in_reset.reset + .if_csr_m0_master_address (if_csr_m0_master_address), // if_csr_m0_master.address + .if_csr_m0_master_waitrequest (if_csr_m0_master_waitrequest), // .waitrequest + .if_csr_m0_master_byteenable (if_csr_m0_master_byteenable), // .byteenable + .if_csr_m0_master_read (if_csr_m0_master_read), // .read + .if_csr_m0_master_readdata (if_csr_m0_master_readdata), // .readdata + .if_csr_m0_master_readdatavalid (if_csr_m0_master_readdatavalid), // .readdatavalid + .if_csr_m0_master_write (if_csr_m0_master_write), // .write + .if_csr_m0_master_writedata (if_csr_m0_master_writedata), // .writedata + .c0_csr_address (mm_interconnect_2_c0_csr_address), // c0_csr.address + .c0_csr_write (mm_interconnect_2_c0_csr_write), // .write + .c0_csr_read (mm_interconnect_2_c0_csr_read), // .read + .c0_csr_readdata (mm_interconnect_2_c0_csr_readdata), // .readdata + .c0_csr_writedata (mm_interconnect_2_c0_csr_writedata), // .writedata + .c0_csr_byteenable (mm_interconnect_2_c0_csr_byteenable), // .byteenable + .c0_csr_readdatavalid (mm_interconnect_2_c0_csr_readdatavalid), // .readdatavalid + .c0_csr_waitrequest (mm_interconnect_2_c0_csr_waitrequest), // .waitrequest + .p0_csr_address (mm_interconnect_2_p0_csr_address), // p0_csr.address + .p0_csr_write (mm_interconnect_2_p0_csr_write), // .write + .p0_csr_read (mm_interconnect_2_p0_csr_read), // .read + .p0_csr_readdata (mm_interconnect_2_p0_csr_readdata), // .readdata + .p0_csr_writedata (mm_interconnect_2_p0_csr_writedata), // .writedata + .p0_csr_byteenable (mm_interconnect_2_p0_csr_byteenable), // .byteenable + .p0_csr_readdatavalid (mm_interconnect_2_p0_csr_readdatavalid), // .readdatavalid + .p0_csr_waitrequest (mm_interconnect_2_p0_csr_waitrequest) // .waitrequest + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (1), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (0), + .RESET_REQ_WAIT_TIME (1), + .MIN_RST_ASSERTION_TIME (3), + .RESET_REQ_EARLY_DSRT_TIME (1), + .USE_RESET_REQUEST_IN0 (0), + .USE_RESET_REQUEST_IN1 (0), + .USE_RESET_REQUEST_IN2 (0), + .USE_RESET_REQUEST_IN3 (0), + .USE_RESET_REQUEST_IN4 (0), + .USE_RESET_REQUEST_IN5 (0), + .USE_RESET_REQUEST_IN6 (0), + .USE_RESET_REQUEST_IN7 (0), + .USE_RESET_REQUEST_IN8 (0), + .USE_RESET_REQUEST_IN9 (0), + .USE_RESET_REQUEST_IN10 (0), + .USE_RESET_REQUEST_IN11 (0), + .USE_RESET_REQUEST_IN12 (0), + .USE_RESET_REQUEST_IN13 (0), + .USE_RESET_REQUEST_IN14 (0), + .USE_RESET_REQUEST_IN15 (0), + .ADAPT_RESET_REQUEST (0) + ) rst_controller ( + .reset_in0 (~csr_reset_n), // reset_in0.reset + .clk (csr_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_req (), // (terminated) + .reset_req_in0 (1'b0), // (terminated) + .reset_in1 (1'b0), // (terminated) + .reset_req_in1 (1'b0), // (terminated) + .reset_in2 (1'b0), // (terminated) + .reset_req_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_req_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_req_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_req_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_req_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_req_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_req_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_req_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_req_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_req_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_req_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_req_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_req_in14 (1'b0), // (terminated) + .reset_in15 (1'b0), // (terminated) + .reset_req_in15 (1'b0) // (terminated) + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_dmaster.v b/ip/altera/ddr3/ddr3_dmaster.v new file mode 100644 index 0000000..07d736e --- /dev/null +++ b/ip/altera/ddr3/ddr3_dmaster.v @@ -0,0 +1,354 @@ +// ddr3_dmaster.v + +// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_dmaster #( + parameter USE_PLI = 0, + parameter PLI_PORT = 50000, + parameter FIFO_DEPTHS = 2 + ) ( + input wire clk_clk, // clk.clk + input wire clk_reset_reset, // clk_reset.reset + output wire [31:0] master_address, // master.address + input wire [31:0] master_readdata, // .readdata + output wire master_read, // .read + output wire master_write, // .write + output wire [31:0] master_writedata, // .writedata + input wire master_waitrequest, // .waitrequest + input wire master_readdatavalid, // .readdatavalid + output wire [3:0] master_byteenable, // .byteenable + output wire master_reset_reset // master_reset.reset + ); + + wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid + wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data + wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid + wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data + wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready + wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid + wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data + wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready + wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid + wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data + wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready + wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel + wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket + wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket + wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid + wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data + wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready + wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket + wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket + wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid + wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data + wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready + wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket + wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket + wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid + wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data + wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready + wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel + wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket + wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket + wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid + wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data + wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n] + + generate + // If any of the display statements (or deliberately broken + // instantiations) within this generate block triggers then this module + // has been instantiated this module with a set of parameters different + // from those it was generated for. This will usually result in a + // non-functioning system. + if (USE_PLI != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + use_pli_check ( .error(1'b1) ); + end + if (PLI_PORT != 50000) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + pli_port_check ( .error(1'b1) ); + end + if (FIFO_DEPTHS != 2) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + fifo_depths_check ( .error(1'b1) ); + end + endgenerate + + altera_avalon_st_jtag_interface #( + .PURPOSE (1), + .UPSTREAM_FIFO_SIZE (0), + .DOWNSTREAM_FIFO_SIZE (64), + .MGMT_CHANNEL_WIDTH (-1), + .EXPORT_JTAG (0), + .USE_PLI (0), + .PLI_PORT (50000) + ) jtag_phy_embedded_in_jtag_master ( + .clk (clk_clk), // clock.clk + .reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n + .source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data + .source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid + .sink_data (p2b_out_bytes_stream_data), // sink.data + .sink_valid (p2b_out_bytes_stream_valid), // .valid + .sink_ready (p2b_out_bytes_stream_ready), // .ready + .resetrequest (master_reset_reset), // resetrequest.reset + .source_ready (1'b1), // (terminated) + .mgmt_valid (), // (terminated) + .mgmt_channel (), // (terminated) + .mgmt_data (), // (terminated) + .jtag_tck (1'b0), // (terminated) + .jtag_tms (1'b0), // (terminated) + .jtag_tdi (1'b0), // (terminated) + .jtag_tdo (), // (terminated) + .jtag_ena (1'b0), // (terminated) + .jtag_usr1 (1'b0), // (terminated) + .jtag_clr (1'b0), // (terminated) + .jtag_clrn (1'b0), // (terminated) + .jtag_state_tlr (1'b0), // (terminated) + .jtag_state_rti (1'b0), // (terminated) + .jtag_state_sdrs (1'b0), // (terminated) + .jtag_state_cdr (1'b0), // (terminated) + .jtag_state_sdr (1'b0), // (terminated) + .jtag_state_e1dr (1'b0), // (terminated) + .jtag_state_pdr (1'b0), // (terminated) + .jtag_state_e2dr (1'b0), // (terminated) + .jtag_state_udr (1'b0), // (terminated) + .jtag_state_sirs (1'b0), // (terminated) + .jtag_state_cir (1'b0), // (terminated) + .jtag_state_sir (1'b0), // (terminated) + .jtag_state_e1ir (1'b0), // (terminated) + .jtag_state_pir (1'b0), // (terminated) + .jtag_state_e2ir (1'b0), // (terminated) + .jtag_state_uir (1'b0), // (terminated) + .jtag_ir_in (3'b000), // (terminated) + .jtag_irq (), // (terminated) + .jtag_ir_out () // (terminated) + ); + + ddr3_dmaster_timing_adt timing_adt ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data + .in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid + .out_data (timing_adt_out_data), // out.data + .out_valid (timing_adt_out_valid), // .valid + .out_ready (timing_adt_out_ready) // .ready + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (8), + .FIFO_DEPTH (64), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (0), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (3), + .USE_MEMORY_BLOCKS (1), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (timing_adt_out_data), // in.data + .in_valid (timing_adt_out_valid), // .valid + .in_ready (timing_adt_out_ready), // .ready + .out_data (fifo_out_data), // out.data + .out_valid (fifo_out_valid), // .valid + .out_ready (fifo_out_ready), // .ready + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_startofpacket (1'b0), // (terminated) + .in_endofpacket (1'b0), // (terminated) + .out_startofpacket (), // (terminated) + .out_endofpacket (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_avalon_st_bytes_to_packets #( + .CHANNEL_WIDTH (8), + .ENCODING (0) + ) b2p ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n + .out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel + .out_ready (b2p_out_packets_stream_ready), // .ready + .out_valid (b2p_out_packets_stream_valid), // .valid + .out_data (b2p_out_packets_stream_data), // .data + .out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket + .out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket + .in_ready (fifo_out_ready), // in_bytes_stream.ready + .in_valid (fifo_out_valid), // .valid + .in_data (fifo_out_data) // .data + ); + + altera_avalon_st_packets_to_bytes #( + .CHANNEL_WIDTH (8), + .ENCODING (0) + ) p2b ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n + .in_ready (p2b_adapter_out_ready), // in_packets_stream.ready + .in_valid (p2b_adapter_out_valid), // .valid + .in_data (p2b_adapter_out_data), // .data + .in_channel (p2b_adapter_out_channel), // .channel + .in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket + .in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket + .out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready + .out_valid (p2b_out_bytes_stream_valid), // .valid + .out_data (p2b_out_bytes_stream_data) // .data + ); + + altera_avalon_packets_to_master #( + .FAST_VER (0), + .FIFO_DEPTHS (2), + .FIFO_WIDTHU (1) + ) transacto ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n + .out_ready (transacto_out_stream_ready), // out_stream.ready + .out_valid (transacto_out_stream_valid), // .valid + .out_data (transacto_out_stream_data), // .data + .out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket + .out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket + .in_ready (b2p_adapter_out_ready), // in_stream.ready + .in_valid (b2p_adapter_out_valid), // .valid + .in_data (b2p_adapter_out_data), // .data + .in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket + .in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket + .address (master_address), // avalon_master.address + .readdata (master_readdata), // .readdata + .read (master_read), // .read + .write (master_write), // .write + .writedata (master_writedata), // .writedata + .waitrequest (master_waitrequest), // .waitrequest + .readdatavalid (master_readdatavalid), // .readdatavalid + .byteenable (master_byteenable) // .byteenable + ); + + ddr3_dmaster_b2p_adapter b2p_adapter ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .in_data (b2p_out_packets_stream_data), // in.data + .in_valid (b2p_out_packets_stream_valid), // .valid + .in_ready (b2p_out_packets_stream_ready), // .ready + .in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket + .in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket + .in_channel (b2p_out_packets_stream_channel), // .channel + .out_data (b2p_adapter_out_data), // out.data + .out_valid (b2p_adapter_out_valid), // .valid + .out_ready (b2p_adapter_out_ready), // .ready + .out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket + .out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket + ); + + ddr3_dmaster_p2b_adapter p2b_adapter ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .in_data (transacto_out_stream_data), // in.data + .in_valid (transacto_out_stream_valid), // .valid + .in_ready (transacto_out_stream_ready), // .ready + .in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket + .in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket + .out_data (p2b_adapter_out_data), // out.data + .out_valid (p2b_adapter_out_valid), // .valid + .out_ready (p2b_adapter_out_ready), // .ready + .out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket + .out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket + .out_channel (p2b_adapter_out_channel) // .channel + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (1), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (0), + .RESET_REQ_WAIT_TIME (1), + .MIN_RST_ASSERTION_TIME (3), + .RESET_REQ_EARLY_DSRT_TIME (1), + .USE_RESET_REQUEST_IN0 (0), + .USE_RESET_REQUEST_IN1 (0), + .USE_RESET_REQUEST_IN2 (0), + .USE_RESET_REQUEST_IN3 (0), + .USE_RESET_REQUEST_IN4 (0), + .USE_RESET_REQUEST_IN5 (0), + .USE_RESET_REQUEST_IN6 (0), + .USE_RESET_REQUEST_IN7 (0), + .USE_RESET_REQUEST_IN8 (0), + .USE_RESET_REQUEST_IN9 (0), + .USE_RESET_REQUEST_IN10 (0), + .USE_RESET_REQUEST_IN11 (0), + .USE_RESET_REQUEST_IN12 (0), + .USE_RESET_REQUEST_IN13 (0), + .USE_RESET_REQUEST_IN14 (0), + .USE_RESET_REQUEST_IN15 (0), + .ADAPT_RESET_REQUEST (0) + ) rst_controller ( + .reset_in0 (clk_reset_reset), // reset_in0.reset + .clk (clk_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_req (), // (terminated) + .reset_req_in0 (1'b0), // (terminated) + .reset_in1 (1'b0), // (terminated) + .reset_req_in1 (1'b0), // (terminated) + .reset_in2 (1'b0), // (terminated) + .reset_req_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_req_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_req_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_req_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_req_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_req_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_req_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_req_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_req_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_req_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_req_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_req_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_req_in14 (1'b0), // (terminated) + .reset_in15 (1'b0), // (terminated) + .reset_req_in15 (1'b0) // (terminated) + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_dmaster_b2p_adapter.sv b/ip/altera/ddr3/ddr3_dmaster_b2p_adapter.sv new file mode 100644 index 0000000..f43280c --- /dev/null +++ b/ip/altera/ddr3/ddr3_dmaster_b2p_adapter.sv @@ -0,0 +1,100 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/09/09 $ +// $Author: dmunday $ + +// -------------------------------------------------------------------------------- +//| Avalon Streaming Channel Adapter +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_dmaster_b2p_adapter +// in_channel_width: 8 +// in_max_channel: 255 +// out_channel_width: 0 +// out_max_channel: 0 +// data_width: 8 +// error_width: 0 +// use_ready: true +// use_packets: true +// use_empty: 0 +// empty_width: 0 + +// ------------------------------------------ + + +module ddr3_dmaster_b2p_adapter +( + // Interface: in + output reg in_ready, + input in_valid, + input [8-1: 0] in_data, + input [8-1: 0] in_channel, + input in_startofpacket, + input in_endofpacket, + // Interface: out + input out_ready, + output reg out_valid, + output reg [8-1: 0] out_data, + output reg out_startofpacket, + output reg out_endofpacket, + // Interface: clk + input clk, + // Interface: reset + input reset_n + + +); + + reg out_channel; + + // --------------------------------------------------------------------- + //| Payload Mapping + // --------------------------------------------------------------------- + always @* begin + in_ready = out_ready; + out_valid = in_valid; + out_data = in_data; + out_startofpacket = in_startofpacket; + out_endofpacket = in_endofpacket; + + out_channel = in_channel; //TODO delete this to avoid Quartus warnings + + // Suppress channels that are higher than the destination's max_channel. + if (in_channel > 0) begin + out_valid = 0; + // Simulation Message goes here. + end + end + +endmodule + diff --git a/ip/altera/ddr3/ddr3_dmaster_p2b_adapter.sv b/ip/altera/ddr3/ddr3_dmaster_p2b_adapter.sv new file mode 100644 index 0000000..69a5555 --- /dev/null +++ b/ip/altera/ddr3/ddr3_dmaster_p2b_adapter.sv @@ -0,0 +1,96 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/09/09 $ +// $Author: dmunday $ + +// -------------------------------------------------------------------------------- +//| Avalon Streaming Channel Adapter +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_dmaster_p2b_adapter +// in_channel_width: 0 +// in_max_channel: 0 +// out_channel_width: 8 +// out_max_channel: 255 +// data_width: 8 +// error_width: 0 +// use_ready: true +// use_packets: true +// use_empty: 0 +// empty_width: 0 + +// ------------------------------------------ + + +module ddr3_dmaster_p2b_adapter +( + // Interface: in + output reg in_ready, + input in_valid, + input [8-1: 0] in_data, + input in_startofpacket, + input in_endofpacket, + // Interface: out + input out_ready, + output reg out_valid, + output reg [8-1: 0] out_data, + output reg [8-1: 0] out_channel, + output reg out_startofpacket, + output reg out_endofpacket, + // Interface: clk + input clk, + // Interface: reset + input reset_n + + +); + + reg in_channel = 0; + + // --------------------------------------------------------------------- + //| Payload Mapping + // --------------------------------------------------------------------- + always @* begin + in_ready = out_ready; + out_valid = in_valid; + out_data = in_data; + out_startofpacket = in_startofpacket; + out_endofpacket = in_endofpacket; + + out_channel = 0; + out_channel = in_channel; + + end + +endmodule + diff --git a/ip/altera/ddr3/ddr3_dmaster_timing_adt.sv b/ip/altera/ddr3/ddr3_dmaster_timing_adt.sv new file mode 100644 index 0000000..91ba207 --- /dev/null +++ b/ip/altera/ddr3/ddr3_dmaster_timing_adt.sv @@ -0,0 +1,112 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/09/27 $ +// $Author: dmunday, korthner $ + +// -------------------------------------------------------------------------------- +//| Avalon Streaming Timing Adapter +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_dmaster_timing_adt +// in_use_ready: false +// out_use_ready: true +// in_use_valid: true +// out_use_valid: true +// use_packets: false +// use_empty: 0 +// empty_width: 0 +// data_width: 8 +// channel_width: 0 +// error_width: 0 +// in_ready_latency: 0 +// out_ready_latency: 0 +// in_payload_width: 8 +// out_payload_width: 8 +// in_payload_map: in_data +// out_payload_map: out_data +// ------------------------------------------ + + + +module ddr3_dmaster_timing_adt +( + input in_valid, + input [8-1: 0] in_data, + // Interface: out + input out_ready, + output reg out_valid, + output reg [8-1: 0] out_data, + // Interface: clk + input clk, + // Interface: reset + input reset_n + + /*AUTOARG*/); + + // --------------------------------------------------------------------- + //| Signal Declarations + // --------------------------------------------------------------------- + + reg [8-1:0] in_payload; + reg [8-1:0] out_payload; + reg [1-1:0] ready; + reg in_ready; + // synthesis translate_off + always @(negedge in_ready) begin + $display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured."); + end + // synthesis translate_on + + // --------------------------------------------------------------------- + //| Payload Mapping + // --------------------------------------------------------------------- + always @* begin + in_payload = {in_data}; + {out_data} = out_payload; + end + + // --------------------------------------------------------------------- + //| Ready & valid signals. + // --------------------------------------------------------------------- + always_comb begin + ready[0] = out_ready; + out_valid = in_valid; + out_payload = in_payload; + in_ready = ready[0]; + end + + + + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_1.v b/ip/altera/ddr3/ddr3_mm_interconnect_1.v new file mode 100644 index 0000000..6998e62 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_1.v @@ -0,0 +1,168 @@ +// ddr3_mm_interconnect_1.v + +// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_mm_interconnect_1 ( + input wire p0_avl_clk_clk, // p0_avl_clk.clk + input wire dmaster_clk_reset_reset_bridge_in_reset_reset, // dmaster_clk_reset_reset_bridge_in_reset.reset + input wire dmaster_master_translator_reset_reset_bridge_in_reset_reset, // dmaster_master_translator_reset_reset_bridge_in_reset.reset + input wire [31:0] dmaster_master_address, // dmaster_master.address + output wire dmaster_master_waitrequest, // .waitrequest + input wire [3:0] dmaster_master_byteenable, // .byteenable + input wire dmaster_master_read, // .read + output wire [31:0] dmaster_master_readdata, // .readdata + output wire dmaster_master_readdatavalid, // .readdatavalid + input wire dmaster_master_write, // .write + input wire [31:0] dmaster_master_writedata, // .writedata + output wire [31:0] s0_seq_debug_address, // s0_seq_debug.address + output wire s0_seq_debug_write, // .write + output wire s0_seq_debug_read, // .read + input wire [31:0] s0_seq_debug_readdata, // .readdata + output wire [31:0] s0_seq_debug_writedata, // .writedata + output wire [0:0] s0_seq_debug_burstcount, // .burstcount + output wire [3:0] s0_seq_debug_byteenable, // .byteenable + input wire s0_seq_debug_readdatavalid, // .readdatavalid + input wire s0_seq_debug_waitrequest // .waitrequest + ); + + wire dmaster_master_translator_avalon_universal_master_0_waitrequest; // s0_seq_debug_translator:uav_waitrequest -> dmaster_master_translator:uav_waitrequest + wire [31:0] dmaster_master_translator_avalon_universal_master_0_readdata; // s0_seq_debug_translator:uav_readdata -> dmaster_master_translator:uav_readdata + wire dmaster_master_translator_avalon_universal_master_0_debugaccess; // dmaster_master_translator:uav_debugaccess -> s0_seq_debug_translator:uav_debugaccess + wire [31:0] dmaster_master_translator_avalon_universal_master_0_address; // dmaster_master_translator:uav_address -> s0_seq_debug_translator:uav_address + wire dmaster_master_translator_avalon_universal_master_0_read; // dmaster_master_translator:uav_read -> s0_seq_debug_translator:uav_read + wire [3:0] dmaster_master_translator_avalon_universal_master_0_byteenable; // dmaster_master_translator:uav_byteenable -> s0_seq_debug_translator:uav_byteenable + wire dmaster_master_translator_avalon_universal_master_0_readdatavalid; // s0_seq_debug_translator:uav_readdatavalid -> dmaster_master_translator:uav_readdatavalid + wire dmaster_master_translator_avalon_universal_master_0_lock; // dmaster_master_translator:uav_lock -> s0_seq_debug_translator:uav_lock + wire dmaster_master_translator_avalon_universal_master_0_write; // dmaster_master_translator:uav_write -> s0_seq_debug_translator:uav_write + wire [31:0] dmaster_master_translator_avalon_universal_master_0_writedata; // dmaster_master_translator:uav_writedata -> s0_seq_debug_translator:uav_writedata + wire [2:0] dmaster_master_translator_avalon_universal_master_0_burstcount; // dmaster_master_translator:uav_burstcount -> s0_seq_debug_translator:uav_burstcount + + altera_merlin_master_translator #( + .AV_ADDRESS_W (32), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (0) + ) dmaster_master_translator ( + .clk (p0_avl_clk_clk), // clk.clk + .reset (dmaster_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset + .uav_address (dmaster_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (dmaster_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (dmaster_master_translator_avalon_universal_master_0_read), // .read + .uav_write (dmaster_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (dmaster_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (dmaster_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (dmaster_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (dmaster_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (dmaster_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (dmaster_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (dmaster_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (dmaster_master_address), // avalon_anti_master_0.address + .av_waitrequest (dmaster_master_waitrequest), // .waitrequest + .av_byteenable (dmaster_master_byteenable), // .byteenable + .av_read (dmaster_master_read), // .read + .av_readdata (dmaster_master_readdata), // .readdata + .av_readdatavalid (dmaster_master_readdatavalid), // .readdatavalid + .av_write (dmaster_master_write), // .write + .av_writedata (dmaster_master_writedata), // .writedata + .av_burstcount (1'b1), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_lock (1'b0), // (terminated) + .av_debugaccess (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (32), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) s0_seq_debug_translator ( + .clk (p0_avl_clk_clk), // clk.clk + .reset (dmaster_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset + .uav_address (dmaster_master_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address + .uav_burstcount (dmaster_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (dmaster_master_translator_avalon_universal_master_0_read), // .read + .uav_write (dmaster_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (dmaster_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (dmaster_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (dmaster_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (dmaster_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (dmaster_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (dmaster_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (dmaster_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (s0_seq_debug_address), // avalon_anti_slave_0.address + .av_write (s0_seq_debug_write), // .write + .av_read (s0_seq_debug_read), // .read + .av_readdata (s0_seq_debug_readdata), // .readdata + .av_writedata (s0_seq_debug_writedata), // .writedata + .av_burstcount (s0_seq_debug_burstcount), // .burstcount + .av_byteenable (s0_seq_debug_byteenable), // .byteenable + .av_readdatavalid (s0_seq_debug_readdatavalid), // .readdatavalid + .av_waitrequest (s0_seq_debug_waitrequest), // .waitrequest + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2.v b/ip/altera/ddr3/ddr3_mm_interconnect_2.v new file mode 100644 index 0000000..0d92d42 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2.v @@ -0,0 +1,1227 @@ +// ddr3_mm_interconnect_2.v + +// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_mm_interconnect_2 ( + input wire csr_clk_out_clk_clk, // csr_clk_out_clk.clk + input wire if_csr_m0_clk_reset_reset_bridge_in_reset_reset, // if_csr_m0_clk_reset_reset_bridge_in_reset.reset + input wire p0_csr_reset_n_reset_bridge_in_reset_reset, // p0_csr_reset_n_reset_bridge_in_reset.reset + input wire [31:0] if_csr_m0_master_address, // if_csr_m0_master.address + output wire if_csr_m0_master_waitrequest, // .waitrequest + input wire [3:0] if_csr_m0_master_byteenable, // .byteenable + input wire if_csr_m0_master_read, // .read + output wire [31:0] if_csr_m0_master_readdata, // .readdata + output wire if_csr_m0_master_readdatavalid, // .readdatavalid + input wire if_csr_m0_master_write, // .write + input wire [31:0] if_csr_m0_master_writedata, // .writedata + output wire [9:0] c0_csr_address, // c0_csr.address + output wire c0_csr_write, // .write + output wire c0_csr_read, // .read + input wire [7:0] c0_csr_readdata, // .readdata + output wire [7:0] c0_csr_writedata, // .writedata + output wire [0:0] c0_csr_byteenable, // .byteenable + input wire c0_csr_readdatavalid, // .readdatavalid + input wire c0_csr_waitrequest, // .waitrequest + output wire [7:0] p0_csr_address, // p0_csr.address + output wire p0_csr_write, // .write + output wire p0_csr_read, // .read + input wire [31:0] p0_csr_readdata, // .readdata + output wire [31:0] p0_csr_writedata, // .writedata + output wire [3:0] p0_csr_byteenable, // .byteenable + input wire p0_csr_readdatavalid, // .readdatavalid + input wire p0_csr_waitrequest // .waitrequest + ); + + wire if_csr_m0_master_translator_avalon_universal_master_0_waitrequest; // if_csr_m0_master_agent:av_waitrequest -> if_csr_m0_master_translator:uav_waitrequest + wire [31:0] if_csr_m0_master_translator_avalon_universal_master_0_readdata; // if_csr_m0_master_agent:av_readdata -> if_csr_m0_master_translator:uav_readdata + wire if_csr_m0_master_translator_avalon_universal_master_0_debugaccess; // if_csr_m0_master_translator:uav_debugaccess -> if_csr_m0_master_agent:av_debugaccess + wire [31:0] if_csr_m0_master_translator_avalon_universal_master_0_address; // if_csr_m0_master_translator:uav_address -> if_csr_m0_master_agent:av_address + wire if_csr_m0_master_translator_avalon_universal_master_0_read; // if_csr_m0_master_translator:uav_read -> if_csr_m0_master_agent:av_read + wire [3:0] if_csr_m0_master_translator_avalon_universal_master_0_byteenable; // if_csr_m0_master_translator:uav_byteenable -> if_csr_m0_master_agent:av_byteenable + wire if_csr_m0_master_translator_avalon_universal_master_0_readdatavalid; // if_csr_m0_master_agent:av_readdatavalid -> if_csr_m0_master_translator:uav_readdatavalid + wire if_csr_m0_master_translator_avalon_universal_master_0_lock; // if_csr_m0_master_translator:uav_lock -> if_csr_m0_master_agent:av_lock + wire if_csr_m0_master_translator_avalon_universal_master_0_write; // if_csr_m0_master_translator:uav_write -> if_csr_m0_master_agent:av_write + wire [31:0] if_csr_m0_master_translator_avalon_universal_master_0_writedata; // if_csr_m0_master_translator:uav_writedata -> if_csr_m0_master_agent:av_writedata + wire [2:0] if_csr_m0_master_translator_avalon_universal_master_0_burstcount; // if_csr_m0_master_translator:uav_burstcount -> if_csr_m0_master_agent:av_burstcount + wire [31:0] p0_csr_agent_m0_readdata; // p0_csr_translator:uav_readdata -> p0_csr_agent:m0_readdata + wire p0_csr_agent_m0_waitrequest; // p0_csr_translator:uav_waitrequest -> p0_csr_agent:m0_waitrequest + wire p0_csr_agent_m0_debugaccess; // p0_csr_agent:m0_debugaccess -> p0_csr_translator:uav_debugaccess + wire [31:0] p0_csr_agent_m0_address; // p0_csr_agent:m0_address -> p0_csr_translator:uav_address + wire [3:0] p0_csr_agent_m0_byteenable; // p0_csr_agent:m0_byteenable -> p0_csr_translator:uav_byteenable + wire p0_csr_agent_m0_read; // p0_csr_agent:m0_read -> p0_csr_translator:uav_read + wire p0_csr_agent_m0_readdatavalid; // p0_csr_translator:uav_readdatavalid -> p0_csr_agent:m0_readdatavalid + wire p0_csr_agent_m0_lock; // p0_csr_agent:m0_lock -> p0_csr_translator:uav_lock + wire [31:0] p0_csr_agent_m0_writedata; // p0_csr_agent:m0_writedata -> p0_csr_translator:uav_writedata + wire p0_csr_agent_m0_write; // p0_csr_agent:m0_write -> p0_csr_translator:uav_write + wire [2:0] p0_csr_agent_m0_burstcount; // p0_csr_agent:m0_burstcount -> p0_csr_translator:uav_burstcount + wire p0_csr_agent_rf_source_valid; // p0_csr_agent:rf_source_valid -> p0_csr_agent_rsp_fifo:in_valid + wire [102:0] p0_csr_agent_rf_source_data; // p0_csr_agent:rf_source_data -> p0_csr_agent_rsp_fifo:in_data + wire p0_csr_agent_rf_source_ready; // p0_csr_agent_rsp_fifo:in_ready -> p0_csr_agent:rf_source_ready + wire p0_csr_agent_rf_source_startofpacket; // p0_csr_agent:rf_source_startofpacket -> p0_csr_agent_rsp_fifo:in_startofpacket + wire p0_csr_agent_rf_source_endofpacket; // p0_csr_agent:rf_source_endofpacket -> p0_csr_agent_rsp_fifo:in_endofpacket + wire p0_csr_agent_rsp_fifo_out_valid; // p0_csr_agent_rsp_fifo:out_valid -> p0_csr_agent:rf_sink_valid + wire [102:0] p0_csr_agent_rsp_fifo_out_data; // p0_csr_agent_rsp_fifo:out_data -> p0_csr_agent:rf_sink_data + wire p0_csr_agent_rsp_fifo_out_ready; // p0_csr_agent:rf_sink_ready -> p0_csr_agent_rsp_fifo:out_ready + wire p0_csr_agent_rsp_fifo_out_startofpacket; // p0_csr_agent_rsp_fifo:out_startofpacket -> p0_csr_agent:rf_sink_startofpacket + wire p0_csr_agent_rsp_fifo_out_endofpacket; // p0_csr_agent_rsp_fifo:out_endofpacket -> p0_csr_agent:rf_sink_endofpacket + wire cmd_mux_src_valid; // cmd_mux:src_valid -> p0_csr_agent:cp_valid + wire [101:0] cmd_mux_src_data; // cmd_mux:src_data -> p0_csr_agent:cp_data + wire cmd_mux_src_ready; // p0_csr_agent:cp_ready -> cmd_mux:src_ready + wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> p0_csr_agent:cp_channel + wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> p0_csr_agent:cp_startofpacket + wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> p0_csr_agent:cp_endofpacket + wire [7:0] c0_csr_agent_m0_readdata; // c0_csr_translator:uav_readdata -> c0_csr_agent:m0_readdata + wire c0_csr_agent_m0_waitrequest; // c0_csr_translator:uav_waitrequest -> c0_csr_agent:m0_waitrequest + wire c0_csr_agent_m0_debugaccess; // c0_csr_agent:m0_debugaccess -> c0_csr_translator:uav_debugaccess + wire [31:0] c0_csr_agent_m0_address; // c0_csr_agent:m0_address -> c0_csr_translator:uav_address + wire [0:0] c0_csr_agent_m0_byteenable; // c0_csr_agent:m0_byteenable -> c0_csr_translator:uav_byteenable + wire c0_csr_agent_m0_read; // c0_csr_agent:m0_read -> c0_csr_translator:uav_read + wire c0_csr_agent_m0_readdatavalid; // c0_csr_translator:uav_readdatavalid -> c0_csr_agent:m0_readdatavalid + wire c0_csr_agent_m0_lock; // c0_csr_agent:m0_lock -> c0_csr_translator:uav_lock + wire [7:0] c0_csr_agent_m0_writedata; // c0_csr_agent:m0_writedata -> c0_csr_translator:uav_writedata + wire c0_csr_agent_m0_write; // c0_csr_agent:m0_write -> c0_csr_translator:uav_write + wire [0:0] c0_csr_agent_m0_burstcount; // c0_csr_agent:m0_burstcount -> c0_csr_translator:uav_burstcount + wire c0_csr_agent_rf_source_valid; // c0_csr_agent:rf_source_valid -> c0_csr_agent_rsp_fifo:in_valid + wire [75:0] c0_csr_agent_rf_source_data; // c0_csr_agent:rf_source_data -> c0_csr_agent_rsp_fifo:in_data + wire c0_csr_agent_rf_source_ready; // c0_csr_agent_rsp_fifo:in_ready -> c0_csr_agent:rf_source_ready + wire c0_csr_agent_rf_source_startofpacket; // c0_csr_agent:rf_source_startofpacket -> c0_csr_agent_rsp_fifo:in_startofpacket + wire c0_csr_agent_rf_source_endofpacket; // c0_csr_agent:rf_source_endofpacket -> c0_csr_agent_rsp_fifo:in_endofpacket + wire c0_csr_agent_rsp_fifo_out_valid; // c0_csr_agent_rsp_fifo:out_valid -> c0_csr_agent:rf_sink_valid + wire [75:0] c0_csr_agent_rsp_fifo_out_data; // c0_csr_agent_rsp_fifo:out_data -> c0_csr_agent:rf_sink_data + wire c0_csr_agent_rsp_fifo_out_ready; // c0_csr_agent:rf_sink_ready -> c0_csr_agent_rsp_fifo:out_ready + wire c0_csr_agent_rsp_fifo_out_startofpacket; // c0_csr_agent_rsp_fifo:out_startofpacket -> c0_csr_agent:rf_sink_startofpacket + wire c0_csr_agent_rsp_fifo_out_endofpacket; // c0_csr_agent_rsp_fifo:out_endofpacket -> c0_csr_agent:rf_sink_endofpacket + wire c0_csr_agent_rdata_fifo_src_valid; // c0_csr_agent:rdata_fifo_src_valid -> c0_csr_agent_rdata_fifo:in_valid + wire [9:0] c0_csr_agent_rdata_fifo_src_data; // c0_csr_agent:rdata_fifo_src_data -> c0_csr_agent_rdata_fifo:in_data + wire c0_csr_agent_rdata_fifo_src_ready; // c0_csr_agent_rdata_fifo:in_ready -> c0_csr_agent:rdata_fifo_src_ready + wire if_csr_m0_master_agent_cp_valid; // if_csr_m0_master_agent:cp_valid -> router:sink_valid + wire [101:0] if_csr_m0_master_agent_cp_data; // if_csr_m0_master_agent:cp_data -> router:sink_data + wire if_csr_m0_master_agent_cp_ready; // router:sink_ready -> if_csr_m0_master_agent:cp_ready + wire if_csr_m0_master_agent_cp_startofpacket; // if_csr_m0_master_agent:cp_startofpacket -> router:sink_startofpacket + wire if_csr_m0_master_agent_cp_endofpacket; // if_csr_m0_master_agent:cp_endofpacket -> router:sink_endofpacket + wire p0_csr_agent_rp_valid; // p0_csr_agent:rp_valid -> router_001:sink_valid + wire [101:0] p0_csr_agent_rp_data; // p0_csr_agent:rp_data -> router_001:sink_data + wire p0_csr_agent_rp_ready; // router_001:sink_ready -> p0_csr_agent:rp_ready + wire p0_csr_agent_rp_startofpacket; // p0_csr_agent:rp_startofpacket -> router_001:sink_startofpacket + wire p0_csr_agent_rp_endofpacket; // p0_csr_agent:rp_endofpacket -> router_001:sink_endofpacket + wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid + wire [101:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data + wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready + wire [1:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel + wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket + wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket + wire c0_csr_agent_rp_valid; // c0_csr_agent:rp_valid -> router_002:sink_valid + wire [74:0] c0_csr_agent_rp_data; // c0_csr_agent:rp_data -> router_002:sink_data + wire c0_csr_agent_rp_ready; // router_002:sink_ready -> c0_csr_agent:rp_ready + wire c0_csr_agent_rp_startofpacket; // c0_csr_agent:rp_startofpacket -> router_002:sink_startofpacket + wire c0_csr_agent_rp_endofpacket; // c0_csr_agent:rp_endofpacket -> router_002:sink_endofpacket + wire router_src_valid; // router:src_valid -> if_csr_m0_master_limiter:cmd_sink_valid + wire [101:0] router_src_data; // router:src_data -> if_csr_m0_master_limiter:cmd_sink_data + wire router_src_ready; // if_csr_m0_master_limiter:cmd_sink_ready -> router:src_ready + wire [1:0] router_src_channel; // router:src_channel -> if_csr_m0_master_limiter:cmd_sink_channel + wire router_src_startofpacket; // router:src_startofpacket -> if_csr_m0_master_limiter:cmd_sink_startofpacket + wire router_src_endofpacket; // router:src_endofpacket -> if_csr_m0_master_limiter:cmd_sink_endofpacket + wire [101:0] if_csr_m0_master_limiter_cmd_src_data; // if_csr_m0_master_limiter:cmd_src_data -> cmd_demux:sink_data + wire if_csr_m0_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> if_csr_m0_master_limiter:cmd_src_ready + wire [1:0] if_csr_m0_master_limiter_cmd_src_channel; // if_csr_m0_master_limiter:cmd_src_channel -> cmd_demux:sink_channel + wire if_csr_m0_master_limiter_cmd_src_startofpacket; // if_csr_m0_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket + wire if_csr_m0_master_limiter_cmd_src_endofpacket; // if_csr_m0_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket + wire rsp_mux_src_valid; // rsp_mux:src_valid -> if_csr_m0_master_limiter:rsp_sink_valid + wire [101:0] rsp_mux_src_data; // rsp_mux:src_data -> if_csr_m0_master_limiter:rsp_sink_data + wire rsp_mux_src_ready; // if_csr_m0_master_limiter:rsp_sink_ready -> rsp_mux:src_ready + wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> if_csr_m0_master_limiter:rsp_sink_channel + wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> if_csr_m0_master_limiter:rsp_sink_startofpacket + wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> if_csr_m0_master_limiter:rsp_sink_endofpacket + wire if_csr_m0_master_limiter_rsp_src_valid; // if_csr_m0_master_limiter:rsp_src_valid -> if_csr_m0_master_agent:rp_valid + wire [101:0] if_csr_m0_master_limiter_rsp_src_data; // if_csr_m0_master_limiter:rsp_src_data -> if_csr_m0_master_agent:rp_data + wire if_csr_m0_master_limiter_rsp_src_ready; // if_csr_m0_master_agent:rp_ready -> if_csr_m0_master_limiter:rsp_src_ready + wire [1:0] if_csr_m0_master_limiter_rsp_src_channel; // if_csr_m0_master_limiter:rsp_src_channel -> if_csr_m0_master_agent:rp_channel + wire if_csr_m0_master_limiter_rsp_src_startofpacket; // if_csr_m0_master_limiter:rsp_src_startofpacket -> if_csr_m0_master_agent:rp_startofpacket + wire if_csr_m0_master_limiter_rsp_src_endofpacket; // if_csr_m0_master_limiter:rsp_src_endofpacket -> if_csr_m0_master_agent:rp_endofpacket + wire c0_csr_burst_adapter_source0_valid; // c0_csr_burst_adapter:source0_valid -> c0_csr_agent:cp_valid + wire [74:0] c0_csr_burst_adapter_source0_data; // c0_csr_burst_adapter:source0_data -> c0_csr_agent:cp_data + wire c0_csr_burst_adapter_source0_ready; // c0_csr_agent:cp_ready -> c0_csr_burst_adapter:source0_ready + wire [1:0] c0_csr_burst_adapter_source0_channel; // c0_csr_burst_adapter:source0_channel -> c0_csr_agent:cp_channel + wire c0_csr_burst_adapter_source0_startofpacket; // c0_csr_burst_adapter:source0_startofpacket -> c0_csr_agent:cp_startofpacket + wire c0_csr_burst_adapter_source0_endofpacket; // c0_csr_burst_adapter:source0_endofpacket -> c0_csr_agent:cp_endofpacket + wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid + wire [101:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data + wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready + wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel + wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket + wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket + wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid + wire [101:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data + wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready + wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel + wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket + wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket + wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid + wire [101:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data + wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready + wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel + wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket + wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket + wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid + wire [101:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data + wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready + wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel + wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket + wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket + wire router_002_src_valid; // router_002:src_valid -> c0_csr_rsp_width_adapter:in_valid + wire [74:0] router_002_src_data; // router_002:src_data -> c0_csr_rsp_width_adapter:in_data + wire router_002_src_ready; // c0_csr_rsp_width_adapter:in_ready -> router_002:src_ready + wire [1:0] router_002_src_channel; // router_002:src_channel -> c0_csr_rsp_width_adapter:in_channel + wire router_002_src_startofpacket; // router_002:src_startofpacket -> c0_csr_rsp_width_adapter:in_startofpacket + wire router_002_src_endofpacket; // router_002:src_endofpacket -> c0_csr_rsp_width_adapter:in_endofpacket + wire c0_csr_rsp_width_adapter_src_valid; // c0_csr_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid + wire [101:0] c0_csr_rsp_width_adapter_src_data; // c0_csr_rsp_width_adapter:out_data -> rsp_demux_001:sink_data + wire c0_csr_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> c0_csr_rsp_width_adapter:out_ready + wire [1:0] c0_csr_rsp_width_adapter_src_channel; // c0_csr_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel + wire c0_csr_rsp_width_adapter_src_startofpacket; // c0_csr_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket + wire c0_csr_rsp_width_adapter_src_endofpacket; // c0_csr_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket + wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> c0_csr_cmd_width_adapter:in_valid + wire [101:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> c0_csr_cmd_width_adapter:in_data + wire cmd_mux_001_src_ready; // c0_csr_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready + wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> c0_csr_cmd_width_adapter:in_channel + wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> c0_csr_cmd_width_adapter:in_startofpacket + wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> c0_csr_cmd_width_adapter:in_endofpacket + wire c0_csr_cmd_width_adapter_src_valid; // c0_csr_cmd_width_adapter:out_valid -> c0_csr_burst_adapter:sink0_valid + wire [74:0] c0_csr_cmd_width_adapter_src_data; // c0_csr_cmd_width_adapter:out_data -> c0_csr_burst_adapter:sink0_data + wire c0_csr_cmd_width_adapter_src_ready; // c0_csr_burst_adapter:sink0_ready -> c0_csr_cmd_width_adapter:out_ready + wire [1:0] c0_csr_cmd_width_adapter_src_channel; // c0_csr_cmd_width_adapter:out_channel -> c0_csr_burst_adapter:sink0_channel + wire c0_csr_cmd_width_adapter_src_startofpacket; // c0_csr_cmd_width_adapter:out_startofpacket -> c0_csr_burst_adapter:sink0_startofpacket + wire c0_csr_cmd_width_adapter_src_endofpacket; // c0_csr_cmd_width_adapter:out_endofpacket -> c0_csr_burst_adapter:sink0_endofpacket + wire [1:0] if_csr_m0_master_limiter_cmd_valid_data; // if_csr_m0_master_limiter:cmd_src_valid -> cmd_demux:sink_valid + wire p0_csr_agent_rdata_fifo_src_valid; // p0_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid + wire [33:0] p0_csr_agent_rdata_fifo_src_data; // p0_csr_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data + wire p0_csr_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> p0_csr_agent:rdata_fifo_src_ready + wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> p0_csr_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> p0_csr_agent:rdata_fifo_sink_data + wire avalon_st_adapter_out_0_ready; // p0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready + wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> p0_csr_agent:rdata_fifo_sink_error + wire c0_csr_agent_rdata_fifo_out_valid; // c0_csr_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid + wire [9:0] c0_csr_agent_rdata_fifo_out_data; // c0_csr_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data + wire c0_csr_agent_rdata_fifo_out_ready; // avalon_st_adapter_001:in_0_ready -> c0_csr_agent_rdata_fifo:out_ready + wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> c0_csr_agent:rdata_fifo_sink_valid + wire [9:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> c0_csr_agent:rdata_fifo_sink_data + wire avalon_st_adapter_001_out_0_ready; // c0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready + wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> c0_csr_agent:rdata_fifo_sink_error + + altera_merlin_master_translator #( + .AV_ADDRESS_W (32), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (0) + ) if_csr_m0_master_translator ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (if_csr_m0_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (if_csr_m0_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (if_csr_m0_master_translator_avalon_universal_master_0_read), // .read + .uav_write (if_csr_m0_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (if_csr_m0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (if_csr_m0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (if_csr_m0_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (if_csr_m0_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (if_csr_m0_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (if_csr_m0_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (if_csr_m0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (if_csr_m0_master_address), // avalon_anti_master_0.address + .av_waitrequest (if_csr_m0_master_waitrequest), // .waitrequest + .av_byteenable (if_csr_m0_master_byteenable), // .byteenable + .av_read (if_csr_m0_master_read), // .read + .av_readdata (if_csr_m0_master_readdata), // .readdata + .av_readdatavalid (if_csr_m0_master_readdatavalid), // .readdatavalid + .av_write (if_csr_m0_master_write), // .write + .av_writedata (if_csr_m0_master_writedata), // .writedata + .av_burstcount (1'b1), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_lock (1'b0), // (terminated) + .av_debugaccess (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (8), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) p0_csr_translator ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (p0_csr_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (p0_csr_agent_m0_burstcount), // .burstcount + .uav_read (p0_csr_agent_m0_read), // .read + .uav_write (p0_csr_agent_m0_write), // .write + .uav_waitrequest (p0_csr_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (p0_csr_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (p0_csr_agent_m0_byteenable), // .byteenable + .uav_readdata (p0_csr_agent_m0_readdata), // .readdata + .uav_writedata (p0_csr_agent_m0_writedata), // .writedata + .uav_lock (p0_csr_agent_m0_lock), // .lock + .uav_debugaccess (p0_csr_agent_m0_debugaccess), // .debugaccess + .av_address (p0_csr_address), // avalon_anti_slave_0.address + .av_write (p0_csr_write), // .write + .av_read (p0_csr_read), // .read + .av_readdata (p0_csr_readdata), // .readdata + .av_writedata (p0_csr_writedata), // .writedata + .av_byteenable (p0_csr_byteenable), // .byteenable + .av_readdatavalid (p0_csr_readdatavalid), // .readdatavalid + .av_waitrequest (p0_csr_waitrequest), // .waitrequest + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (10), + .AV_DATA_W (8), + .UAV_DATA_W (8), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (1), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (1), + .AV_READLATENCY (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (1), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) c0_csr_translator ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (c0_csr_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (c0_csr_agent_m0_burstcount), // .burstcount + .uav_read (c0_csr_agent_m0_read), // .read + .uav_write (c0_csr_agent_m0_write), // .write + .uav_waitrequest (c0_csr_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (c0_csr_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (c0_csr_agent_m0_byteenable), // .byteenable + .uav_readdata (c0_csr_agent_m0_readdata), // .readdata + .uav_writedata (c0_csr_agent_m0_writedata), // .writedata + .uav_lock (c0_csr_agent_m0_lock), // .lock + .uav_debugaccess (c0_csr_agent_m0_debugaccess), // .debugaccess + .av_address (c0_csr_address), // avalon_anti_slave_0.address + .av_write (c0_csr_write), // .write + .av_read (c0_csr_read), // .read + .av_readdata (c0_csr_readdata), // .readdata + .av_writedata (c0_csr_writedata), // .writedata + .av_byteenable (c0_csr_byteenable), // .byteenable + .av_readdatavalid (c0_csr_readdatavalid), // .readdatavalid + .av_waitrequest (c0_csr_waitrequest), // .waitrequest + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_ORI_BURST_SIZE_H (101), + .PKT_ORI_BURST_SIZE_L (99), + .PKT_RESPONSE_STATUS_H (98), + .PKT_RESPONSE_STATUS_L (97), + .PKT_QOS_H (86), + .PKT_QOS_L (86), + .PKT_DATA_SIDEBAND_H (84), + .PKT_DATA_SIDEBAND_L (84), + .PKT_ADDR_SIDEBAND_H (83), + .PKT_ADDR_SIDEBAND_L (83), + .PKT_BURST_TYPE_H (82), + .PKT_BURST_TYPE_L (81), + .PKT_CACHE_H (96), + .PKT_CACHE_L (93), + .PKT_THREAD_ID_H (89), + .PKT_THREAD_ID_L (89), + .PKT_BURST_SIZE_H (80), + .PKT_BURST_SIZE_L (78), + .PKT_TRANS_EXCLUSIVE (73), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (85), + .PKT_PROTECTION_H (92), + .PKT_PROTECTION_L (90), + .PKT_BURSTWRAP_H (77), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (87), + .PKT_SRC_ID_L (87), + .PKT_DEST_ID_H (88), + .PKT_DEST_ID_L (88), + .ST_DATA_W (102), + .ST_CHANNEL_W (2), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (0), + .BURSTWRAP_VALUE (1), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) if_csr_m0_master_agent ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .av_address (if_csr_m0_master_translator_avalon_universal_master_0_address), // av.address + .av_write (if_csr_m0_master_translator_avalon_universal_master_0_write), // .write + .av_read (if_csr_m0_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (if_csr_m0_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (if_csr_m0_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (if_csr_m0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (if_csr_m0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (if_csr_m0_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (if_csr_m0_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (if_csr_m0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (if_csr_m0_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (if_csr_m0_master_agent_cp_valid), // cp.valid + .cp_data (if_csr_m0_master_agent_cp_data), // .data + .cp_startofpacket (if_csr_m0_master_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (if_csr_m0_master_agent_cp_endofpacket), // .endofpacket + .cp_ready (if_csr_m0_master_agent_cp_ready), // .ready + .rp_valid (if_csr_m0_master_limiter_rsp_src_valid), // rp.valid + .rp_data (if_csr_m0_master_limiter_rsp_src_data), // .data + .rp_channel (if_csr_m0_master_limiter_rsp_src_channel), // .channel + .rp_startofpacket (if_csr_m0_master_limiter_rsp_src_startofpacket), // .startofpacket + .rp_endofpacket (if_csr_m0_master_limiter_rsp_src_endofpacket), // .endofpacket + .rp_ready (if_csr_m0_master_limiter_rsp_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_ORI_BURST_SIZE_H (101), + .PKT_ORI_BURST_SIZE_L (99), + .PKT_RESPONSE_STATUS_H (98), + .PKT_RESPONSE_STATUS_L (97), + .PKT_BURST_SIZE_H (80), + .PKT_BURST_SIZE_L (78), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (85), + .PKT_PROTECTION_H (92), + .PKT_PROTECTION_L (90), + .PKT_BURSTWRAP_H (77), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (87), + .PKT_SRC_ID_L (87), + .PKT_DEST_ID_H (88), + .PKT_DEST_ID_L (88), + .PKT_SYMBOL_W (8), + .ST_CHANNEL_W (2), + .ST_DATA_W (102), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .ECC_ENABLE (0) + ) p0_csr_agent ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .m0_address (p0_csr_agent_m0_address), // m0.address + .m0_burstcount (p0_csr_agent_m0_burstcount), // .burstcount + .m0_byteenable (p0_csr_agent_m0_byteenable), // .byteenable + .m0_debugaccess (p0_csr_agent_m0_debugaccess), // .debugaccess + .m0_lock (p0_csr_agent_m0_lock), // .lock + .m0_readdata (p0_csr_agent_m0_readdata), // .readdata + .m0_readdatavalid (p0_csr_agent_m0_readdatavalid), // .readdatavalid + .m0_read (p0_csr_agent_m0_read), // .read + .m0_waitrequest (p0_csr_agent_m0_waitrequest), // .waitrequest + .m0_writedata (p0_csr_agent_m0_writedata), // .writedata + .m0_write (p0_csr_agent_m0_write), // .write + .rp_endofpacket (p0_csr_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (p0_csr_agent_rp_ready), // .ready + .rp_valid (p0_csr_agent_rp_valid), // .valid + .rp_data (p0_csr_agent_rp_data), // .data + .rp_startofpacket (p0_csr_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_mux_src_ready), // cp.ready + .cp_valid (cmd_mux_src_valid), // .valid + .cp_data (cmd_mux_src_data), // .data + .cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_src_channel), // .channel + .rf_sink_ready (p0_csr_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (p0_csr_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (p0_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (p0_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (p0_csr_agent_rsp_fifo_out_data), // .data + .rf_source_ready (p0_csr_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (p0_csr_agent_rf_source_valid), // .valid + .rf_source_startofpacket (p0_csr_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (p0_csr_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (p0_csr_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error + .rdata_fifo_src_ready (p0_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (p0_csr_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (p0_csr_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (103), + .FIFO_DEPTH (5), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) p0_csr_agent_rsp_fifo ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (p0_csr_agent_rf_source_data), // in.data + .in_valid (p0_csr_agent_rf_source_valid), // .valid + .in_ready (p0_csr_agent_rf_source_ready), // .ready + .in_startofpacket (p0_csr_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (p0_csr_agent_rf_source_endofpacket), // .endofpacket + .out_data (p0_csr_agent_rsp_fifo_out_data), // out.data + .out_valid (p0_csr_agent_rsp_fifo_out_valid), // .valid + .out_ready (p0_csr_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (p0_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (p0_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_ORI_BURST_SIZE_H (74), + .PKT_ORI_BURST_SIZE_L (72), + .PKT_RESPONSE_STATUS_H (71), + .PKT_RESPONSE_STATUS_L (70), + .PKT_BURST_SIZE_H (53), + .PKT_BURST_SIZE_L (51), + .PKT_TRANS_LOCK (45), + .PKT_BEGIN_BURST (58), + .PKT_PROTECTION_H (65), + .PKT_PROTECTION_L (63), + .PKT_BURSTWRAP_H (50), + .PKT_BURSTWRAP_L (50), + .PKT_BYTE_CNT_H (49), + .PKT_BYTE_CNT_L (47), + .PKT_ADDR_H (40), + .PKT_ADDR_L (9), + .PKT_TRANS_COMPRESSED_READ (41), + .PKT_TRANS_POSTED (42), + .PKT_TRANS_WRITE (43), + .PKT_TRANS_READ (44), + .PKT_DATA_H (7), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (8), + .PKT_BYTEEN_L (8), + .PKT_SRC_ID_H (60), + .PKT_SRC_ID_L (60), + .PKT_DEST_ID_H (61), + .PKT_DEST_ID_L (61), + .PKT_SYMBOL_W (8), + .ST_CHANNEL_W (2), + .ST_DATA_W (75), + .AVS_BURSTCOUNT_W (1), + .SUPPRESS_0_BYTEEN_CMD (1), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .ECC_ENABLE (0) + ) c0_csr_agent ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .m0_address (c0_csr_agent_m0_address), // m0.address + .m0_burstcount (c0_csr_agent_m0_burstcount), // .burstcount + .m0_byteenable (c0_csr_agent_m0_byteenable), // .byteenable + .m0_debugaccess (c0_csr_agent_m0_debugaccess), // .debugaccess + .m0_lock (c0_csr_agent_m0_lock), // .lock + .m0_readdata (c0_csr_agent_m0_readdata), // .readdata + .m0_readdatavalid (c0_csr_agent_m0_readdatavalid), // .readdatavalid + .m0_read (c0_csr_agent_m0_read), // .read + .m0_waitrequest (c0_csr_agent_m0_waitrequest), // .waitrequest + .m0_writedata (c0_csr_agent_m0_writedata), // .writedata + .m0_write (c0_csr_agent_m0_write), // .write + .rp_endofpacket (c0_csr_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (c0_csr_agent_rp_ready), // .ready + .rp_valid (c0_csr_agent_rp_valid), // .valid + .rp_data (c0_csr_agent_rp_data), // .data + .rp_startofpacket (c0_csr_agent_rp_startofpacket), // .startofpacket + .cp_ready (c0_csr_burst_adapter_source0_ready), // cp.ready + .cp_valid (c0_csr_burst_adapter_source0_valid), // .valid + .cp_data (c0_csr_burst_adapter_source0_data), // .data + .cp_startofpacket (c0_csr_burst_adapter_source0_startofpacket), // .startofpacket + .cp_endofpacket (c0_csr_burst_adapter_source0_endofpacket), // .endofpacket + .cp_channel (c0_csr_burst_adapter_source0_channel), // .channel + .rf_sink_ready (c0_csr_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (c0_csr_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (c0_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (c0_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (c0_csr_agent_rsp_fifo_out_data), // .data + .rf_source_ready (c0_csr_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (c0_csr_agent_rf_source_valid), // .valid + .rf_source_startofpacket (c0_csr_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (c0_csr_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (c0_csr_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error + .rdata_fifo_src_ready (c0_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (c0_csr_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (c0_csr_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (76), + .FIFO_DEPTH (5), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) c0_csr_agent_rsp_fifo ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (c0_csr_agent_rf_source_data), // in.data + .in_valid (c0_csr_agent_rf_source_valid), // .valid + .in_ready (c0_csr_agent_rf_source_ready), // .ready + .in_startofpacket (c0_csr_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (c0_csr_agent_rf_source_endofpacket), // .endofpacket + .out_data (c0_csr_agent_rsp_fifo_out_data), // out.data + .out_valid (c0_csr_agent_rsp_fifo_out_valid), // .valid + .out_ready (c0_csr_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (c0_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (c0_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (10), + .FIFO_DEPTH (8), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (0), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (3), + .USE_MEMORY_BLOCKS (1), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) c0_csr_agent_rdata_fifo ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (c0_csr_agent_rdata_fifo_src_data), // in.data + .in_valid (c0_csr_agent_rdata_fifo_src_valid), // .valid + .in_ready (c0_csr_agent_rdata_fifo_src_ready), // .ready + .out_data (c0_csr_agent_rdata_fifo_out_data), // out.data + .out_valid (c0_csr_agent_rdata_fifo_out_valid), // .valid + .out_ready (c0_csr_agent_rdata_fifo_out_ready), // .ready + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_startofpacket (1'b0), // (terminated) + .in_endofpacket (1'b0), // (terminated) + .out_startofpacket (), // (terminated) + .out_endofpacket (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + ddr3_mm_interconnect_2_router router ( + .sink_ready (if_csr_m0_master_agent_cp_ready), // sink.ready + .sink_valid (if_csr_m0_master_agent_cp_valid), // .valid + .sink_data (if_csr_m0_master_agent_cp_data), // .data + .sink_startofpacket (if_csr_m0_master_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (if_csr_m0_master_agent_cp_endofpacket), // .endofpacket + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_src_ready), // src.ready + .src_valid (router_src_valid), // .valid + .src_data (router_src_data), // .data + .src_channel (router_src_channel), // .channel + .src_startofpacket (router_src_startofpacket), // .startofpacket + .src_endofpacket (router_src_endofpacket) // .endofpacket + ); + + ddr3_mm_interconnect_2_router_001 router_001 ( + .sink_ready (p0_csr_agent_rp_ready), // sink.ready + .sink_valid (p0_csr_agent_rp_valid), // .valid + .sink_data (p0_csr_agent_rp_data), // .data + .sink_startofpacket (p0_csr_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (p0_csr_agent_rp_endofpacket), // .endofpacket + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_001_src_ready), // src.ready + .src_valid (router_001_src_valid), // .valid + .src_data (router_001_src_data), // .data + .src_channel (router_001_src_channel), // .channel + .src_startofpacket (router_001_src_startofpacket), // .startofpacket + .src_endofpacket (router_001_src_endofpacket) // .endofpacket + ); + + ddr3_mm_interconnect_2_router_002 router_002 ( + .sink_ready (c0_csr_agent_rp_ready), // sink.ready + .sink_valid (c0_csr_agent_rp_valid), // .valid + .sink_data (c0_csr_agent_rp_data), // .data + .sink_startofpacket (c0_csr_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (c0_csr_agent_rp_endofpacket), // .endofpacket + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_002_src_ready), // src.ready + .src_valid (router_002_src_valid), // .valid + .src_data (router_002_src_data), // .data + .src_channel (router_002_src_channel), // .channel + .src_startofpacket (router_002_src_startofpacket), // .startofpacket + .src_endofpacket (router_002_src_endofpacket) // .endofpacket + ); + + altera_merlin_traffic_limiter #( + .PKT_DEST_ID_H (88), + .PKT_DEST_ID_L (88), + .PKT_SRC_ID_H (87), + .PKT_SRC_ID_L (87), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .MAX_OUTSTANDING_RESPONSES (6), + .PIPELINED (0), + .ST_DATA_W (102), + .ST_CHANNEL_W (2), + .VALID_WIDTH (2), + .ENFORCE_ORDER (1), + .PREVENT_HAZARDS (0), + .SUPPORTS_POSTED_WRITES (1), + .SUPPORTS_NONPOSTED_WRITES (0), + .REORDER (0) + ) if_csr_m0_master_limiter ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .cmd_sink_ready (router_src_ready), // cmd_sink.ready + .cmd_sink_valid (router_src_valid), // .valid + .cmd_sink_data (router_src_data), // .data + .cmd_sink_channel (router_src_channel), // .channel + .cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket + .cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket + .cmd_src_ready (if_csr_m0_master_limiter_cmd_src_ready), // cmd_src.ready + .cmd_src_data (if_csr_m0_master_limiter_cmd_src_data), // .data + .cmd_src_channel (if_csr_m0_master_limiter_cmd_src_channel), // .channel + .cmd_src_startofpacket (if_csr_m0_master_limiter_cmd_src_startofpacket), // .startofpacket + .cmd_src_endofpacket (if_csr_m0_master_limiter_cmd_src_endofpacket), // .endofpacket + .rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready + .rsp_sink_valid (rsp_mux_src_valid), // .valid + .rsp_sink_channel (rsp_mux_src_channel), // .channel + .rsp_sink_data (rsp_mux_src_data), // .data + .rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket + .rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket + .rsp_src_ready (if_csr_m0_master_limiter_rsp_src_ready), // rsp_src.ready + .rsp_src_valid (if_csr_m0_master_limiter_rsp_src_valid), // .valid + .rsp_src_data (if_csr_m0_master_limiter_rsp_src_data), // .data + .rsp_src_channel (if_csr_m0_master_limiter_rsp_src_channel), // .channel + .rsp_src_startofpacket (if_csr_m0_master_limiter_rsp_src_startofpacket), // .startofpacket + .rsp_src_endofpacket (if_csr_m0_master_limiter_rsp_src_endofpacket), // .endofpacket + .cmd_src_valid (if_csr_m0_master_limiter_cmd_valid_data) // cmd_valid.data + ); + + altera_merlin_burst_adapter #( + .PKT_ADDR_H (40), + .PKT_ADDR_L (9), + .PKT_BEGIN_BURST (58), + .PKT_BYTE_CNT_H (49), + .PKT_BYTE_CNT_L (47), + .PKT_BYTEEN_H (8), + .PKT_BYTEEN_L (8), + .PKT_BURST_SIZE_H (53), + .PKT_BURST_SIZE_L (51), + .PKT_BURST_TYPE_H (55), + .PKT_BURST_TYPE_L (54), + .PKT_BURSTWRAP_H (50), + .PKT_BURSTWRAP_L (50), + .PKT_TRANS_COMPRESSED_READ (41), + .PKT_TRANS_WRITE (43), + .PKT_TRANS_READ (44), + .OUT_NARROW_SIZE (0), + .IN_NARROW_SIZE (0), + .OUT_FIXED (0), + .OUT_COMPLETE_WRAP (0), + .ST_DATA_W (75), + .ST_CHANNEL_W (2), + .OUT_BYTE_CNT_H (47), + .OUT_BURSTWRAP_H (50), + .COMPRESSED_READ_SUPPORT (0), + .BYTEENABLE_SYNTHESIS (1), + .PIPE_INPUTS (0), + .NO_WRAP_SUPPORT (0), + .INCOMPLETE_WRAP_SUPPORT (0), + .BURSTWRAP_CONST_MASK (1), + .BURSTWRAP_CONST_VALUE (1), + .ADAPTER_VERSION ("13.1") + ) c0_csr_burst_adapter ( + .clk (csr_clk_out_clk_clk), // cr0.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset + .sink0_valid (c0_csr_cmd_width_adapter_src_valid), // sink0.valid + .sink0_data (c0_csr_cmd_width_adapter_src_data), // .data + .sink0_channel (c0_csr_cmd_width_adapter_src_channel), // .channel + .sink0_startofpacket (c0_csr_cmd_width_adapter_src_startofpacket), // .startofpacket + .sink0_endofpacket (c0_csr_cmd_width_adapter_src_endofpacket), // .endofpacket + .sink0_ready (c0_csr_cmd_width_adapter_src_ready), // .ready + .source0_valid (c0_csr_burst_adapter_source0_valid), // source0.valid + .source0_data (c0_csr_burst_adapter_source0_data), // .data + .source0_channel (c0_csr_burst_adapter_source0_channel), // .channel + .source0_startofpacket (c0_csr_burst_adapter_source0_startofpacket), // .startofpacket + .source0_endofpacket (c0_csr_burst_adapter_source0_endofpacket), // .endofpacket + .source0_ready (c0_csr_burst_adapter_source0_ready) // .ready + ); + + ddr3_mm_interconnect_2_cmd_demux cmd_demux ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (if_csr_m0_master_limiter_cmd_src_ready), // sink.ready + .sink_channel (if_csr_m0_master_limiter_cmd_src_channel), // .channel + .sink_data (if_csr_m0_master_limiter_cmd_src_data), // .data + .sink_startofpacket (if_csr_m0_master_limiter_cmd_src_startofpacket), // .startofpacket + .sink_endofpacket (if_csr_m0_master_limiter_cmd_src_endofpacket), // .endofpacket + .sink_valid (if_csr_m0_master_limiter_cmd_valid_data), // sink_valid.data + .src0_ready (cmd_demux_src0_ready), // src0.ready + .src0_valid (cmd_demux_src0_valid), // .valid + .src0_data (cmd_demux_src0_data), // .data + .src0_channel (cmd_demux_src0_channel), // .channel + .src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket + .src1_ready (cmd_demux_src1_ready), // src1.ready + .src1_valid (cmd_demux_src1_valid), // .valid + .src1_data (cmd_demux_src1_data), // .data + .src1_channel (cmd_demux_src1_channel), // .channel + .src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket + ); + + ddr3_mm_interconnect_2_cmd_mux cmd_mux ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (cmd_mux_src_ready), // src.ready + .src_valid (cmd_mux_src_valid), // .valid + .src_data (cmd_mux_src_data), // .data + .src_channel (cmd_mux_src_channel), // .channel + .src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket + .sink0_ready (cmd_demux_src0_ready), // sink0.ready + .sink0_valid (cmd_demux_src0_valid), // .valid + .sink0_channel (cmd_demux_src0_channel), // .channel + .sink0_data (cmd_demux_src0_data), // .data + .sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket + ); + + ddr3_mm_interconnect_2_cmd_mux cmd_mux_001 ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (cmd_mux_001_src_ready), // src.ready + .src_valid (cmd_mux_001_src_valid), // .valid + .src_data (cmd_mux_001_src_data), // .data + .src_channel (cmd_mux_001_src_channel), // .channel + .src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (cmd_demux_src1_ready), // sink0.ready + .sink0_valid (cmd_demux_src1_valid), // .valid + .sink0_channel (cmd_demux_src1_channel), // .channel + .sink0_data (cmd_demux_src1_data), // .data + .sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket + ); + + ddr3_mm_interconnect_2_rsp_demux rsp_demux ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_001_src_ready), // sink.ready + .sink_channel (router_001_src_channel), // .channel + .sink_data (router_001_src_data), // .data + .sink_startofpacket (router_001_src_startofpacket), // .startofpacket + .sink_endofpacket (router_001_src_endofpacket), // .endofpacket + .sink_valid (router_001_src_valid), // .valid + .src0_ready (rsp_demux_src0_ready), // src0.ready + .src0_valid (rsp_demux_src0_valid), // .valid + .src0_data (rsp_demux_src0_data), // .data + .src0_channel (rsp_demux_src0_channel), // .channel + .src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket + ); + + ddr3_mm_interconnect_2_rsp_demux rsp_demux_001 ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (c0_csr_rsp_width_adapter_src_ready), // sink.ready + .sink_channel (c0_csr_rsp_width_adapter_src_channel), // .channel + .sink_data (c0_csr_rsp_width_adapter_src_data), // .data + .sink_startofpacket (c0_csr_rsp_width_adapter_src_startofpacket), // .startofpacket + .sink_endofpacket (c0_csr_rsp_width_adapter_src_endofpacket), // .endofpacket + .sink_valid (c0_csr_rsp_width_adapter_src_valid), // .valid + .src0_ready (rsp_demux_001_src0_ready), // src0.ready + .src0_valid (rsp_demux_001_src0_valid), // .valid + .src0_data (rsp_demux_001_src0_data), // .data + .src0_channel (rsp_demux_001_src0_channel), // .channel + .src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket + ); + + ddr3_mm_interconnect_2_rsp_mux rsp_mux ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (rsp_mux_src_ready), // src.ready + .src_valid (rsp_mux_src_valid), // .valid + .src_data (rsp_mux_src_data), // .data + .src_channel (rsp_mux_src_channel), // .channel + .src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket + .sink0_ready (rsp_demux_src0_ready), // sink0.ready + .sink0_valid (rsp_demux_src0_valid), // .valid + .sink0_channel (rsp_demux_src0_channel), // .channel + .sink0_data (rsp_demux_src0_data), // .data + .sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket + .sink1_ready (rsp_demux_001_src0_ready), // sink1.ready + .sink1_valid (rsp_demux_001_src0_valid), // .valid + .sink1_channel (rsp_demux_001_src0_channel), // .channel + .sink1_data (rsp_demux_001_src0_data), // .data + .sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket + ); + + altera_merlin_width_adapter #( + .IN_PKT_ADDR_H (40), + .IN_PKT_ADDR_L (9), + .IN_PKT_DATA_H (7), + .IN_PKT_DATA_L (0), + .IN_PKT_BYTEEN_H (8), + .IN_PKT_BYTEEN_L (8), + .IN_PKT_BYTE_CNT_H (49), + .IN_PKT_BYTE_CNT_L (47), + .IN_PKT_TRANS_COMPRESSED_READ (41), + .IN_PKT_TRANS_WRITE (43), + .IN_PKT_BURSTWRAP_H (50), + .IN_PKT_BURSTWRAP_L (50), + .IN_PKT_BURST_SIZE_H (53), + .IN_PKT_BURST_SIZE_L (51), + .IN_PKT_RESPONSE_STATUS_H (71), + .IN_PKT_RESPONSE_STATUS_L (70), + .IN_PKT_TRANS_EXCLUSIVE (46), + .IN_PKT_BURST_TYPE_H (55), + .IN_PKT_BURST_TYPE_L (54), + .IN_PKT_ORI_BURST_SIZE_L (72), + .IN_PKT_ORI_BURST_SIZE_H (74), + .IN_ST_DATA_W (75), + .OUT_PKT_ADDR_H (67), + .OUT_PKT_ADDR_L (36), + .OUT_PKT_DATA_H (31), + .OUT_PKT_DATA_L (0), + .OUT_PKT_BYTEEN_H (35), + .OUT_PKT_BYTEEN_L (32), + .OUT_PKT_BYTE_CNT_H (76), + .OUT_PKT_BYTE_CNT_L (74), + .OUT_PKT_TRANS_COMPRESSED_READ (68), + .OUT_PKT_BURST_SIZE_H (80), + .OUT_PKT_BURST_SIZE_L (78), + .OUT_PKT_RESPONSE_STATUS_H (98), + .OUT_PKT_RESPONSE_STATUS_L (97), + .OUT_PKT_TRANS_EXCLUSIVE (73), + .OUT_PKT_BURST_TYPE_H (82), + .OUT_PKT_BURST_TYPE_L (81), + .OUT_PKT_ORI_BURST_SIZE_L (99), + .OUT_PKT_ORI_BURST_SIZE_H (101), + .OUT_ST_DATA_W (102), + .ST_CHANNEL_W (2), + .OPTIMIZE_FOR_RSP (1), + .RESPONSE_PATH (1), + .CONSTANT_BURST_SIZE (1), + .PACKING (1), + .ENABLE_ADDRESS_ALIGNMENT (0) + ) c0_csr_rsp_width_adapter ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_valid (router_002_src_valid), // sink.valid + .in_channel (router_002_src_channel), // .channel + .in_startofpacket (router_002_src_startofpacket), // .startofpacket + .in_endofpacket (router_002_src_endofpacket), // .endofpacket + .in_ready (router_002_src_ready), // .ready + .in_data (router_002_src_data), // .data + .out_endofpacket (c0_csr_rsp_width_adapter_src_endofpacket), // src.endofpacket + .out_data (c0_csr_rsp_width_adapter_src_data), // .data + .out_channel (c0_csr_rsp_width_adapter_src_channel), // .channel + .out_valid (c0_csr_rsp_width_adapter_src_valid), // .valid + .out_ready (c0_csr_rsp_width_adapter_src_ready), // .ready + .out_startofpacket (c0_csr_rsp_width_adapter_src_startofpacket), // .startofpacket + .in_command_size_data (3'b000) // (terminated) + ); + + altera_merlin_width_adapter #( + .IN_PKT_ADDR_H (67), + .IN_PKT_ADDR_L (36), + .IN_PKT_DATA_H (31), + .IN_PKT_DATA_L (0), + .IN_PKT_BYTEEN_H (35), + .IN_PKT_BYTEEN_L (32), + .IN_PKT_BYTE_CNT_H (76), + .IN_PKT_BYTE_CNT_L (74), + .IN_PKT_TRANS_COMPRESSED_READ (68), + .IN_PKT_TRANS_WRITE (70), + .IN_PKT_BURSTWRAP_H (77), + .IN_PKT_BURSTWRAP_L (77), + .IN_PKT_BURST_SIZE_H (80), + .IN_PKT_BURST_SIZE_L (78), + .IN_PKT_RESPONSE_STATUS_H (98), + .IN_PKT_RESPONSE_STATUS_L (97), + .IN_PKT_TRANS_EXCLUSIVE (73), + .IN_PKT_BURST_TYPE_H (82), + .IN_PKT_BURST_TYPE_L (81), + .IN_PKT_ORI_BURST_SIZE_L (99), + .IN_PKT_ORI_BURST_SIZE_H (101), + .IN_ST_DATA_W (102), + .OUT_PKT_ADDR_H (40), + .OUT_PKT_ADDR_L (9), + .OUT_PKT_DATA_H (7), + .OUT_PKT_DATA_L (0), + .OUT_PKT_BYTEEN_H (8), + .OUT_PKT_BYTEEN_L (8), + .OUT_PKT_BYTE_CNT_H (49), + .OUT_PKT_BYTE_CNT_L (47), + .OUT_PKT_TRANS_COMPRESSED_READ (41), + .OUT_PKT_BURST_SIZE_H (53), + .OUT_PKT_BURST_SIZE_L (51), + .OUT_PKT_RESPONSE_STATUS_H (71), + .OUT_PKT_RESPONSE_STATUS_L (70), + .OUT_PKT_TRANS_EXCLUSIVE (46), + .OUT_PKT_BURST_TYPE_H (55), + .OUT_PKT_BURST_TYPE_L (54), + .OUT_PKT_ORI_BURST_SIZE_L (72), + .OUT_PKT_ORI_BURST_SIZE_H (74), + .OUT_ST_DATA_W (75), + .ST_CHANNEL_W (2), + .OPTIMIZE_FOR_RSP (0), + .RESPONSE_PATH (0), + .CONSTANT_BURST_SIZE (1), + .PACKING (1), + .ENABLE_ADDRESS_ALIGNMENT (0) + ) c0_csr_cmd_width_adapter ( + .clk (csr_clk_out_clk_clk), // clk.clk + .reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_valid (cmd_mux_001_src_valid), // sink.valid + .in_channel (cmd_mux_001_src_channel), // .channel + .in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket + .in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket + .in_ready (cmd_mux_001_src_ready), // .ready + .in_data (cmd_mux_001_src_data), // .data + .out_endofpacket (c0_csr_cmd_width_adapter_src_endofpacket), // src.endofpacket + .out_data (c0_csr_cmd_width_adapter_src_data), // .data + .out_channel (c0_csr_cmd_width_adapter_src_channel), // .channel + .out_valid (c0_csr_cmd_width_adapter_src_valid), // .valid + .out_ready (c0_csr_cmd_width_adapter_src_ready), // .ready + .out_startofpacket (c0_csr_cmd_width_adapter_src_startofpacket), // .startofpacket + .in_command_size_data (3'b000) // (terminated) + ); + + ddr3_mm_interconnect_2_avalon_st_adapter #( + .inBitsPerSymbol (34), + .inUsePackets (0), + .inDataWidth (34), + .inChannelWidth (0), + .inErrorWidth (0), + .inUseEmptyPort (0), + .inUseValid (1), + .inUseReady (1), + .inReadyLatency (0), + .outDataWidth (34), + .outChannelWidth (0), + .outErrorWidth (1), + .outUseEmptyPort (0), + .outUseValid (1), + .outUseReady (1), + .outReadyLatency (0) + ) avalon_st_adapter ( + .in_clk_0_clk (csr_clk_out_clk_clk), // in_clk_0.clk + .in_rst_0_reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (p0_csr_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (p0_csr_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (p0_csr_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_out_0_error) // .error + ); + + ddr3_mm_interconnect_2_avalon_st_adapter_001 #( + .inBitsPerSymbol (10), + .inUsePackets (0), + .inDataWidth (10), + .inChannelWidth (0), + .inErrorWidth (0), + .inUseEmptyPort (0), + .inUseValid (1), + .inUseReady (1), + .inReadyLatency (0), + .outDataWidth (10), + .outChannelWidth (0), + .outErrorWidth (1), + .outUseEmptyPort (0), + .outUseValid (1), + .outUseReady (1), + .outReadyLatency (0) + ) avalon_st_adapter_001 ( + .in_clk_0_clk (csr_clk_out_clk_clk), // in_clk_0.clk + .in_rst_0_reset (p0_csr_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (c0_csr_agent_rdata_fifo_out_data), // in_0.data + .in_0_valid (c0_csr_agent_rdata_fifo_out_valid), // .valid + .in_0_ready (c0_csr_agent_rdata_fifo_out_ready), // .ready + .out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_001_out_0_error) // .error + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter.v b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter.v new file mode 100644 index 0000000..08a70e2 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter.v @@ -0,0 +1,202 @@ +// ddr3_mm_interconnect_2_avalon_st_adapter.v + +// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_mm_interconnect_2_avalon_st_adapter #( + parameter inBitsPerSymbol = 34, + parameter inUsePackets = 0, + parameter inDataWidth = 34, + parameter inChannelWidth = 0, + parameter inErrorWidth = 0, + parameter inUseEmptyPort = 0, + parameter inUseValid = 1, + parameter inUseReady = 1, + parameter inReadyLatency = 0, + parameter outDataWidth = 34, + parameter outChannelWidth = 0, + parameter outErrorWidth = 1, + parameter outUseEmptyPort = 0, + parameter outUseValid = 1, + parameter outUseReady = 1, + parameter outReadyLatency = 0 + ) ( + input wire in_clk_0_clk, // in_clk_0.clk + input wire in_rst_0_reset, // in_rst_0.reset + input wire [33:0] in_0_data, // in_0.data + input wire in_0_valid, // .valid + output wire in_0_ready, // .ready + output wire [33:0] out_0_data, // out_0.data + output wire out_0_valid, // .valid + input wire out_0_ready, // .ready + output wire [0:0] out_0_error // .error + ); + + generate + // If any of the display statements (or deliberately broken + // instantiations) within this generate block triggers then this module + // has been instantiated this module with a set of parameters different + // from those it was generated for. This will usually result in a + // non-functioning system. + if (inBitsPerSymbol != 34) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inbitspersymbol_check ( .error(1'b1) ); + end + if (inUsePackets != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inusepackets_check ( .error(1'b1) ); + end + if (inDataWidth != 34) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + indatawidth_check ( .error(1'b1) ); + end + if (inChannelWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inchannelwidth_check ( .error(1'b1) ); + end + if (inErrorWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inerrorwidth_check ( .error(1'b1) ); + end + if (inUseEmptyPort != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inuseemptyport_check ( .error(1'b1) ); + end + if (inUseValid != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inusevalid_check ( .error(1'b1) ); + end + if (inUseReady != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inuseready_check ( .error(1'b1) ); + end + if (inReadyLatency != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inreadylatency_check ( .error(1'b1) ); + end + if (outDataWidth != 34) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outdatawidth_check ( .error(1'b1) ); + end + if (outChannelWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outchannelwidth_check ( .error(1'b1) ); + end + if (outErrorWidth != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outerrorwidth_check ( .error(1'b1) ); + end + if (outUseEmptyPort != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outuseemptyport_check ( .error(1'b1) ); + end + if (outUseValid != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outusevalid_check ( .error(1'b1) ); + end + if (outUseReady != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outuseready_check ( .error(1'b1) ); + end + if (outReadyLatency != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outreadylatency_check ( .error(1'b1) ); + end + endgenerate + + ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0 error_adapter_0 ( + .clk (in_clk_0_clk), // clk.clk + .reset_n (~in_rst_0_reset), // reset.reset_n + .in_data (in_0_data), // in.data + .in_valid (in_0_valid), // .valid + .in_ready (in_0_ready), // .ready + .out_data (out_0_data), // out.data + .out_valid (out_0_valid), // .valid + .out_ready (out_0_ready), // .ready + .out_error (out_0_error) // .error + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001.v b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001.v new file mode 100644 index 0000000..2504e6e --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001.v @@ -0,0 +1,202 @@ +// ddr3_mm_interconnect_2_avalon_st_adapter_001.v + +// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_mm_interconnect_2_avalon_st_adapter_001 #( + parameter inBitsPerSymbol = 10, + parameter inUsePackets = 0, + parameter inDataWidth = 10, + parameter inChannelWidth = 0, + parameter inErrorWidth = 0, + parameter inUseEmptyPort = 0, + parameter inUseValid = 1, + parameter inUseReady = 1, + parameter inReadyLatency = 0, + parameter outDataWidth = 10, + parameter outChannelWidth = 0, + parameter outErrorWidth = 1, + parameter outUseEmptyPort = 0, + parameter outUseValid = 1, + parameter outUseReady = 1, + parameter outReadyLatency = 0 + ) ( + input wire in_clk_0_clk, // in_clk_0.clk + input wire in_rst_0_reset, // in_rst_0.reset + input wire [9:0] in_0_data, // in_0.data + input wire in_0_valid, // .valid + output wire in_0_ready, // .ready + output wire [9:0] out_0_data, // out_0.data + output wire out_0_valid, // .valid + input wire out_0_ready, // .ready + output wire [0:0] out_0_error // .error + ); + + generate + // If any of the display statements (or deliberately broken + // instantiations) within this generate block triggers then this module + // has been instantiated this module with a set of parameters different + // from those it was generated for. This will usually result in a + // non-functioning system. + if (inBitsPerSymbol != 10) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inbitspersymbol_check ( .error(1'b1) ); + end + if (inUsePackets != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inusepackets_check ( .error(1'b1) ); + end + if (inDataWidth != 10) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + indatawidth_check ( .error(1'b1) ); + end + if (inChannelWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inchannelwidth_check ( .error(1'b1) ); + end + if (inErrorWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inerrorwidth_check ( .error(1'b1) ); + end + if (inUseEmptyPort != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inuseemptyport_check ( .error(1'b1) ); + end + if (inUseValid != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inusevalid_check ( .error(1'b1) ); + end + if (inUseReady != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inuseready_check ( .error(1'b1) ); + end + if (inReadyLatency != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inreadylatency_check ( .error(1'b1) ); + end + if (outDataWidth != 10) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outdatawidth_check ( .error(1'b1) ); + end + if (outChannelWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outchannelwidth_check ( .error(1'b1) ); + end + if (outErrorWidth != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outerrorwidth_check ( .error(1'b1) ); + end + if (outUseEmptyPort != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outuseemptyport_check ( .error(1'b1) ); + end + if (outUseValid != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outusevalid_check ( .error(1'b1) ); + end + if (outUseReady != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outuseready_check ( .error(1'b1) ); + end + if (outReadyLatency != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outreadylatency_check ( .error(1'b1) ); + end + endgenerate + + ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0 error_adapter_0 ( + .clk (in_clk_0_clk), // clk.clk + .reset_n (~in_rst_0_reset), // reset.reset_n + .in_data (in_0_data), // in.data + .in_valid (in_0_valid), // .valid + .in_ready (in_0_ready), // .ready + .out_data (out_0_data), // out.data + .out_valid (out_0_valid), // .valid + .out_ready (out_0_ready), // .ready + .out_error (out_0_error) // .error + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0.sv new file mode 100644 index 0000000..68de908 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0.sv @@ -0,0 +1,107 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/09/09 $ +// $Author: dmunday $ + + +// -------------------------------------------------------------------------------- +//| Avalon Streaming Error Adapter +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0 +// use_ready: true +// use_packets: false +// use_empty: 0 +// empty_width: 0 +// data_width: 10 +// channel_width: 0 +// in_error_width: 0 +// out_error_width: 1 +// in_errors_list +// in_errors_indices 0 +// out_errors_list +// has_in_error_desc: FALSE +// has_out_error_desc: FALSE +// out_has_other: FALSE +// out_other_index: -1 +// dumpVar: +// inString: in_error[ +// closeString: ] | + +// ------------------------------------------ + + + + +module ddr3_mm_interconnect_2_avalon_st_adapter_001_error_adapter_0 +( + // Interface: in + output reg in_ready, + input in_valid, + input [10-1: 0] in_data, + // Interface: out + input out_ready, + output reg out_valid, + output reg [10-1: 0] out_data, + output reg [0:0] out_error, + // Interface: clk + input clk, + // Interface: reset + input reset_n + + /*AUTOARG*/); + + reg in_error = 0; + initial in_error = 0; + + // --------------------------------------------------------------------- + //| Pass-through Mapping + // --------------------------------------------------------------------- + always_comb begin + in_ready = out_ready; + out_valid = in_valid; + out_data = in_data; + + end + + // --------------------------------------------------------------------- + //| Error Mapping + // --------------------------------------------------------------------- + always_comb begin + out_error = 0; + + out_error = in_error; + + end //always @* +endmodule + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0.sv new file mode 100644 index 0000000..faf632a --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0.sv @@ -0,0 +1,107 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/09/09 $ +// $Author: dmunday $ + + +// -------------------------------------------------------------------------------- +//| Avalon Streaming Error Adapter +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0 +// use_ready: true +// use_packets: false +// use_empty: 0 +// empty_width: 0 +// data_width: 34 +// channel_width: 0 +// in_error_width: 0 +// out_error_width: 1 +// in_errors_list +// in_errors_indices 0 +// out_errors_list +// has_in_error_desc: FALSE +// has_out_error_desc: FALSE +// out_has_other: FALSE +// out_other_index: -1 +// dumpVar: +// inString: in_error[ +// closeString: ] | + +// ------------------------------------------ + + + + +module ddr3_mm_interconnect_2_avalon_st_adapter_error_adapter_0 +( + // Interface: in + output reg in_ready, + input in_valid, + input [34-1: 0] in_data, + // Interface: out + input out_ready, + output reg out_valid, + output reg [34-1: 0] out_data, + output reg [0:0] out_error, + // Interface: clk + input clk, + // Interface: reset + input reset_n + + /*AUTOARG*/); + + reg in_error = 0; + initial in_error = 0; + + // --------------------------------------------------------------------- + //| Pass-through Mapping + // --------------------------------------------------------------------- + always_comb begin + in_ready = out_ready; + out_valid = in_valid; + out_data = in_data; + + end + + // --------------------------------------------------------------------- + //| Error Mapping + // --------------------------------------------------------------------- + always_comb begin + out_error = 0; + + out_error = in_error; + + end //always @* +endmodule + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_cmd_demux.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_cmd_demux.sv new file mode 100644 index 0000000..02ade3d --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_cmd_demux.sv @@ -0,0 +1,116 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_mm_interconnect_2_cmd_demux +// ST_DATA_W: 102 +// ST_CHANNEL_W: 2 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 2 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module ddr3_mm_interconnect_2_cmd_demux +( + // ------------------- + // Sink + // ------------------- + input [2-1 : 0] sink_valid, + input [102-1 : 0] sink_data, // ST_DATA_W=102 + input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [102-1 : 0] src0_data, // ST_DATA_W=102 + output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [102-1 : 0] src1_data, // ST_DATA_W=102 + output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid[0]; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid[1]; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & ready_vector); + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_cmd_mux.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_cmd_mux.sv new file mode 100644 index 0000000..c9fdbd0 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_cmd_mux.sv @@ -0,0 +1,97 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_mm_interconnect_2_cmd_mux +// NUM_INPUTS: 1 +// ARBITRATION_SHARES: 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 102 +// ST_CHANNEL_W: 2 +// ------------------------------------------ + +module ddr3_mm_interconnect_2_cmd_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [102-1 : 0] sink0_data, + input [2-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [102-1 : 0] src_data, + output [2-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 102 + 2 + 2; + localparam NUM_INPUTS = 1; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 102; + localparam ST_CHANNEL_W = 2; + localparam PKT_TRANS_LOCK = 72; + + assign src_valid = sink0_valid; + assign src_data = sink0_data; + assign src_channel = sink0_channel; + assign src_startofpacket = sink0_startofpacket; + assign src_endofpacket = sink0_endofpacket; + assign sink0_ready = src_ready; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_router.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_router.sv new file mode 100644 index 0000000..dc916b0 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_router.sv @@ -0,0 +1,227 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_mm_interconnect_2_router_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 1 + ) + (output [88 - 88 : 0] default_destination_id, + output [2-1 : 0] default_wr_channel, + output [2-1 : 0] default_rd_channel, + output [2-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[88 - 88 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 2'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_mm_interconnect_2_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [102-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [102-1 : 0] src_data, + output reg [2-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 88; + localparam PKT_DEST_ID_L = 88; + localparam PKT_PROTECTION_H = 92; + localparam PKT_PROTECTION_L = 90; + localparam ST_DATA_W = 102; + localparam ST_CHANNEL_W = 2; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h400 - 64'h0); + localparam PAD1 = log2ceil(64'h800 - 64'h400); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h800; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_ADDR_W-1 : 0] address; + always @* begin + address = {PKT_ADDR_W{1'b0}}; + address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + end + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [2-1 : 0] default_src_channel; + + + + + + + ddr3_mm_interconnect_2_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x400 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 11'h0 ) begin + src_channel = 2'b01; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x400 .. 0x800 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 11'h400 ) begin + src_channel = 2'b10; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_router_001.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_router_001.sv new file mode 100644 index 0000000..b59bbc6 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_router_001.sv @@ -0,0 +1,215 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_mm_interconnect_2_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [88 - 88 : 0] default_destination_id, + output [2-1 : 0] default_wr_channel, + output [2-1 : 0] default_rd_channel, + output [2-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[88 - 88 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 2'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_mm_interconnect_2_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [102-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [102-1 : 0] src_data, + output reg [2-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 88; + localparam PKT_DEST_ID_L = 88; + localparam PKT_PROTECTION_H = 92; + localparam PKT_PROTECTION_L = 90; + localparam ST_DATA_W = 102; + localparam ST_CHANNEL_W = 2; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [2-1 : 0] default_src_channel; + + + + + + + ddr3_mm_interconnect_2_router_001_default_decode the_default_decode( + .default_destination_id (), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 2'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_router_002.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_router_002.sv new file mode 100644 index 0000000..f36aed2 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_router_002.sv @@ -0,0 +1,215 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_mm_interconnect_2_router_002_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [61 - 61 : 0] default_destination_id, + output [2-1 : 0] default_wr_channel, + output [2-1 : 0] default_rd_channel, + output [2-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[61 - 61 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 2'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_mm_interconnect_2_router_002 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [75-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [75-1 : 0] src_data, + output reg [2-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 40; + localparam PKT_ADDR_L = 9; + localparam PKT_DEST_ID_H = 61; + localparam PKT_DEST_ID_L = 61; + localparam PKT_PROTECTION_H = 65; + localparam PKT_PROTECTION_L = 63; + localparam ST_DATA_W = 75; + localparam ST_CHANNEL_W = 2; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 43; + localparam PKT_TRANS_READ = 44; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [2-1 : 0] default_src_channel; + + + + + + + ddr3_mm_interconnect_2_router_002_default_decode the_default_decode( + .default_destination_id (), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 2'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_rsp_demux.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_rsp_demux.sv new file mode 100644 index 0000000..af6ae1c --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_rsp_demux.sv @@ -0,0 +1,101 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_mm_interconnect_2_rsp_demux +// ST_DATA_W: 102 +// ST_CHANNEL_W: 2 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module ddr3_mm_interconnect_2_rsp_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [102-1 : 0] sink_data, // ST_DATA_W=102 + input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [102-1 : 0] src0_data, // ST_DATA_W=102 + output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_mm_interconnect_2_rsp_mux.sv b/ip/altera/ddr3/ddr3_mm_interconnect_2_rsp_mux.sv new file mode 100644 index 0000000..bd85771 --- /dev/null +++ b/ip/altera/ddr3/ddr3_mm_interconnect_2_rsp_mux.sv @@ -0,0 +1,346 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_mm_interconnect_2_rsp_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 102 +// ST_CHANNEL_W: 2 +// ------------------------------------------ + +module ddr3_mm_interconnect_2_rsp_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [102-1 : 0] sink0_data, + input [2-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [102-1 : 0] sink1_data, + input [2-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [102-1 : 0] src_data, + output [2-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 102 + 2 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 102; + localparam ST_CHANNEL_W = 2; + localparam PKT_TRANS_LOCK = 72; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[72]; + lock[1] = sink1_data[72]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (last_cycle) + packet_in_progress <= 1'b0; + else if (src_valid) + packet_in_progress <= 1'b1; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid)); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid)); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + wire [NUM_INPUTS - 1 : 0] next_grant_from_arb; + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant_from_arb), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + assign next_grant = next_grant_from_arb; + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_p0.ppf b/ip/altera/ddr3/ddr3_p0.ppf new file mode 100644 index 0000000..4fc630c --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0.ppf @@ -0,0 +1,1512 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ip/altera/ddr3/ddr3_p0.sdc b/ip/altera/ddr3/ddr3_p0.sdc new file mode 100644 index 0000000..70e6d84 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0.sdc @@ -0,0 +1,716 @@ +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains the timing constraints for the UniPHY memory +# interface. +# * The timing parameters used by this file are assigned +# in the ddr3_p0_timing.tcl script. +# * The helper routines are defined in ddr3_p0_pin_map.tcl +# +# NOTE +# ---- + +set script_dir [file dirname [info script]] + +source "$script_dir/ddr3_p0_parameters.tcl" +source "$script_dir/ddr3_p0_timing.tcl" +source "$script_dir/ddr3_p0_pin_map.tcl" + +load_package ddr_timing_model + +set synthesis_flow 0 +set sta_flow 0 +set fit_flow 0 +if { $::TimeQuestInfo(nameofexecutable) == "quartus_map" } { + set synthesis_flow 1 +} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_sta" } { + set sta_flow 1 +} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_fit" } { + set fit_flow 1 +} + +#################### +# # +# GENERAL SETTINGS # +# # +#################### + +# This is a global setting and will apply to the whole design. +# This setting is required for the memory interface to be +# properly constrained. +derive_clock_uncertainty + +# Debug switch. Change to 1 to get more run-time debug information +set debug 0 + +# All timing requirements will be represented in nanoseconds with up to 3 decimal places of precision +set_time_format -unit ns -decimal_places 3 + +# Determine if entity names are on +set entity_names_on [ ddr3_p0_are_entity_names_on ] + +################## +# # +# QUERIED TIMING # +# # +################## + +set io_standard "DIFFERENTIAL 1.5-V SSTL CLASS I" + +# This is the peak-to-peak jitter on the whole read capture path +set DQSpathjitter [expr [get_micro_node_delay -micro DQDQS_JITTER -parameters [list IO] -in_fitter]/1000.0] + +# This is the proportion of the DQ-DQS read capture path jitter that applies to setup +set DQSpathjitter_setup_prop [expr [get_micro_node_delay -micro DQDQS_JITTER_DIVISION -parameters [list IO] -in_fitter]/100.0] + +# This is the peak-to-peak jitter, of which half is considered to be tJITper +set tJITper [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -in_fitter -period $t(CK)]/2000.0 + $SSN(pullin_o)] + +################## +# # +# DERIVED TIMING # +# # +################## + +# These parameters are used to make constraints more readeable + +# Half of memory clock cycle +set half_period [ ddr3_p0_round_3dp [ expr $t(CK) / 2.0 ] ] + +# Half of reference clock +set ref_half_period [ ddr3_p0_round_3dp [ expr $t(refCK) / 2.0 ] ] + +# Minimum delay on data output pins +set t(wru_output_min_delay_external) [expr $t(DH) + $board(intra_DQS_group_skew) + $ISI(DQ)/2 + $ISI(DQS)/2 - $board(DQ_DQS_skew)] +set t(wru_output_min_delay_internal) [expr $t(WL_DCD) + $t(WL_JITTER)*(1.0-$t(WL_JITTER_DIVISION)) + $SSN(rel_pullin_o)] +set data_output_min_delay [ ddr3_p0_round_3dp [ expr - $t(wru_output_min_delay_external) - $t(wru_output_min_delay_internal)]] + +# Maximum delay on data output pins +set t(wru_output_max_delay_external) [expr $t(DS) + $board(intra_DQS_group_skew) + $ISI(DQ)/2 + $ISI(DQS)/2 + $board(DQ_DQS_skew)] +set t(wru_output_max_delay_internal) [expr $t(WL_DCD) + $t(WL_JITTER)*$t(WL_JITTER_DIVISION) + $SSN(rel_pushout_o)] +set data_output_max_delay [ ddr3_p0_round_3dp [ expr $t(wru_output_max_delay_external) + $t(wru_output_max_delay_internal)]] + +# Maximum delay on data input pins +set t(rdu_input_max_delay_external) [expr $t(DQSQ) + $board(intra_DQS_group_skew) + $board(DQ_DQS_skew) + $ISI(READ_DQ)/2 + $ISI(READ_DQS)/2] +set t(rdu_input_max_delay_internal) [expr $DQSpathjitter*$DQSpathjitter_setup_prop + $SSN(rel_pushout_i)] +set data_input_max_delay [ ddr3_p0_round_3dp [ expr $t(rdu_input_max_delay_external) + $t(rdu_input_max_delay_internal) ]] + +# Minimum delay on data input pins +set t(rdu_input_min_delay_external) [expr $board(intra_DQS_group_skew) - $board(DQ_DQS_skew) + $ISI(READ_DQ)/2 + $ISI(READ_DQS)/2] +set t(rdu_input_min_delay_internal) [expr $t(DCD) + $DQSpathjitter*(1.0-$DQSpathjitter_setup_prop) + $SSN(rel_pullin_i)] +set data_input_min_delay [ ddr3_p0_round_3dp [ expr - $t(rdu_input_min_delay_external) - $t(rdu_input_min_delay_internal) ]] + +# Minimum delay on address and command paths +set ac_min_delay [ ddr3_p0_round_3dp [ expr - $t(IH) -$fpga(tPLL_JITTER) - $fpga(tPLL_PSERR) - $board(intra_addr_ctrl_skew) + $board(addresscmd_CK_skew) - $ISI(addresscmd_hold) ]] + +# Maximum delay on address and command paths +set ac_max_delay [ ddr3_p0_round_3dp [ expr $t(IS) +$fpga(tPLL_JITTER) + $fpga(tPLL_PSERR) + $board(intra_addr_ctrl_skew) + $board(addresscmd_CK_skew) + $ISI(addresscmd_setup) ]] + +if { $debug } { + post_message -type info "SDC: Computed Parameters:" + post_message -type info "SDC: --------------------" + post_message -type info "SDC: half_period: $half_period" + post_message -type info "SDC: data_output_min_delay: $data_output_min_delay" + post_message -type info "SDC: data_output_max_delay: $data_output_max_delay" + post_message -type info "SDC: data_input_min_delay: $data_input_min_delay" + post_message -type info "SDC: data_input_max_delay: $data_input_max_delay" + post_message -type info "SDC: ac_min_delay: $ac_min_delay" + post_message -type info "SDC: ac_max_delay: $ac_max_delay" + post_message -type info "SDC: Using Timing Models: Micro" +} + +# This is the main call to the netlist traversal routines +# that will automatically find all pins and registers required +# to apply timing constraints. +# During the fitter, the routines will be called only once +# and cached data will be used in all subsequent calls. +if { ! [ info exists ddr3_p0_sdc_cache ] } { + set ddr3_p0_sdc_cache 1 + ddr3_p0_initialize_ddr_db ddr3_p0_ddr_db +} else { + if { $debug } { + post_message -type info "SDC: reusing cached DDR DB" + } +} + +# If multiple instances of this core are present in the +# design they will all be constrained through the +# following loop +set instances [ array names ddr3_p0_ddr_db ] +foreach { inst } $instances { + if { [ info exists pins ] } { + # Clean-up stale content + unset pins + } + array set pins $ddr3_p0_ddr_db($inst) + + set prefix $inst + if { $entity_names_on } { + set prefix [ string map "| |*:" $inst ] + set prefix "*:$prefix" + } + + ##################################################### + # # + # Transfer the pin names to more readable variables # + # # + ##################################################### + + set dqs_pins $pins(dqs_pins) + set dqsn_pins $pins(dqsn_pins) + set q_groups [ list ] + foreach { q_group } $pins(q_groups) { + set q_group $q_group + lappend q_groups $q_group + } + set all_dq_pins [ join [ join $q_groups ] ] + + set ck_pins $pins(ck_pins) + set ckn_pins $pins(ckn_pins) + set add_pins $pins(add_pins) + set ba_pins $pins(ba_pins) + set cmd_pins $pins(cmd_pins) + set reset_pins $pins(reset_pins) + set ac_pins [ concat $add_pins $ba_pins $cmd_pins ] + set dm_pins $pins(dm_pins) + set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ] + + set pll_ref_clock $pins(pll_ref_clock) + set pll_afi_clock $pins(pll_afi_clock) + set pll_dq_write_clock $pins(pll_dq_write_clock) + set pll_ck_clock $pins(pll_ck_clock) + set pll_write_clock $pins(pll_write_clock) + set pll_avl_clock $pins(pll_avl_clock) + set pll_avl_phy_clock $pins(pll_avl_phy_clock) + set pll_config_clock $pins(pll_config_clock) + set pll_driver_core_clock $pins(pll_driver_core_clock) + + set dqs_in_clocks $pins(dqs_in_clocks) + set dqs_out_clocks $pins(dqs_out_clocks) + set dqsn_out_clocks $pins(dqsn_out_clocks) + + set afi_reset_reg $pins(afi_reset_reg) + set seq_reset_reg $pins(seq_reset_reg) + set sync_reg $pins(sync_reg) + set read_capture_ddio $pins(read_capture_ddio) + set fifo_wraddress_reg $pins(fifo_wraddress_reg) + set fifo_rdaddress_reg $pins(fifo_rdaddress_reg) + set fifo_wrdata_reg $pins(fifo_wrdata_reg) + set fifo_rddata_reg $pins(fifo_rddata_reg) + + ################## + # # + # QUERIED TIMING # + # # + ################## + + # Phase Jitter on DQS paths. This parameter is queried at run time + set fpga(tDQS_PHASE_JITTER) [ expr [ get_integer_node_delay -integer $::GLOBAL_ddr3_p0_dqs_delay_chain_length -parameters {IO MAX HIGH} -src DQS_PHASE_JITTER -in_fitter ] / 1000.0 ] + + # Phase Error on DQS paths. This parameter is queried at run time + set fpga(tDQS_PSERR) [ expr [ get_integer_node_delay -integer $::GLOBAL_ddr3_p0_dqs_delay_chain_length -parameters {IO MAX HIGH} -src DQS_PSERR -in_fitter ] / 1000.0 ] + + # Correct input min/max delay for queried parameters + set t(rdu_input_min_delay_external) [expr $t(rdu_input_min_delay_external) + ($t(CK)/2.0 - $t(QH_time))] + set t(rdu_input_min_delay_internal) [expr $t(rdu_input_min_delay_internal) + $fpga(tDQS_PSERR) + $tJITper] + set t(rdu_input_max_delay_external) [expr $t(rdu_input_max_delay_external)] + set t(rdu_input_max_delay_internal) [expr $t(rdu_input_max_delay_internal) + $fpga(tDQS_PSERR)] + + set final_data_input_max_delay [ ddr3_p0_round_3dp [ expr $data_input_max_delay + $fpga(tDQS_PSERR) ]] + set final_data_input_min_delay [ ddr3_p0_round_3dp [ expr $data_input_min_delay - $t(CK) / 2.0 + $t(QH_time) - $fpga(tDQS_PSERR) - $tJITper]] + + if { $debug } { + post_message -type info "SDC: Jitter Parameters" + post_message -type info "SDC: -----------------" + post_message -type info "SDC: DQS Phase: $::GLOBAL_ddr3_p0_dqs_delay_chain_length" + post_message -type info "SDC: fpga(tDQS_PHASE_JITTER): $fpga(tDQS_PHASE_JITTER)" + post_message -type info "SDC: fpga(tDQS_PSERR): $fpga(tDQS_PSERR)" + post_message -type info "SDC: t(QH_time): $t(QH_time)" + post_message -type info "SDC:" + post_message -type info "SDC: Derived Parameters:" + post_message -type info "SDC: -----------------" + post_message -type info "SDC: Corrected data_input_max_delay: $final_data_input_max_delay" + post_message -type info "SDC: Corrected data_input_min_delay: $final_data_input_min_delay" + post_message -type info "SDC: -----------------" + } + + # ----------------------- # + # - - # + # --- REFERENCE CLOCK --- # + # - - # + # ----------------------- # + + # This is the reference clock used by the PLL to derive any other clock in the core + if { [get_collection_size [get_clocks -nowarn $pll_ref_clock]] > 0 } { remove_clock $pll_ref_clock } + create_clock -period $t(refCK) -waveform [ list 0 $ref_half_period ] $pll_ref_clock + + # ------------------ # + # - - # + # --- PLL CLOCKS --- # + # - - # + # ------------------ # + + # AFI clock + set local_pll_afi_clk [ ddr3_p0_get_or_add_clock_vseries \ + -target $pll_afi_clock \ + -suffix "afi_clk" \ + -source $pll_ref_clock \ + -multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_AFI_CLK) \ + -divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_AFI_CLK) \ + -phase $::GLOBAL_ddr3_p0_pll_phase(PLL_AFI_CLK) ] + + + + # DQ write clock + set local_pll_dq_write_clk [ ddr3_p0_get_or_add_clock_vseries \ + -target $pll_dq_write_clock \ + -suffix "dq_write_clk" \ + -source $pll_ref_clock \ + -multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_WRITE_CLK) \ + -divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_WRITE_CLK) \ + -phase $::GLOBAL_ddr3_p0_pll_phase(PLL_WRITE_CLK) ] + + # DQS write clock + set local_pll_write_clk [ ddr3_p0_get_or_add_clock_vseries \ + -target $pll_write_clock \ + -suffix "write_clk" \ + -source $pll_ref_clock \ + -multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_MEM_CLK) \ + -divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_MEM_CLK) \ + -phase $::GLOBAL_ddr3_p0_pll_phase(PLL_MEM_CLK) ] + + + # NIOS clock + set local_pll_avl_clock [ ddr3_p0_get_or_add_clock_vseries \ + -target $pll_avl_clock \ + -suffix "avl_clk" \ + -source $pll_ref_clock \ + -multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK) \ + -divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK) \ + -phase $::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) ] + + set mem_factor [expr double($::GLOBAL_ddr3_p0_pll_mult(PLL_MEM_CLK)) / $::GLOBAL_ddr3_p0_pll_div(PLL_MEM_CLK)] + set avl_factor [expr double($::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK)) / $::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK)] + set write_to_avl_clk_ratio [expr int($mem_factor / $avl_factor)] + + # AVL PHY clock + if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} { + set local_pll_avl_phy_clk [ ddr3_p0_get_or_add_clock_vseries \ + -target $pll_avl_phy_clock \ + -suffix "avl_phy_clk" \ + -source $pll_ref_clock \ + -multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK) \ + -divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK) \ + -phase $::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) ] + } + + # I/O scan chain clock + set local_pll_config_clock [ ddr3_p0_get_or_add_clock_vseries \ + -target $pll_config_clock \ + -suffix "config_clk" \ + -source $pll_ref_clock \ + -multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_CONFIG_CLK) \ + -divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_CONFIG_CLK) \ + -phase $::GLOBAL_ddr3_p0_pll_phase(PLL_CONFIG_CLK) ] + + + + # Pulse-generator used by DQS tracking + set local_sampling_clock "${inst}|ddr3_p0_sampling_clock" + + if {[get_collection_size [get_registers -nowarn $pins(dqs_enable_regs_pins)]] > 0} { + create_generated_clock \ + -add \ + -name $local_sampling_clock \ + -source $pll_write_clock \ + -multiply_by 1 \ + -divide_by 1 \ + -phase 0 \ + $pins(dqs_enable_regs_pins) + } + + # If this is the example design, then we need to find the PLL output which is used in the core by the driver and MPFE ports. + # The node name is known; check to see if it exists (implying the example design) before creating the clock. + if {[string compare -nocase $pll_driver_core_clock "_UNDEFINED_PIN_"] != 0} { + set local_pll_driver_core_clk [ ddr3_p0_get_or_add_clock_vseries \ + -target $pll_driver_core_clock \ + -suffix "driver_core_clk" \ + -source $pll_ref_clock \ + -multiply_by 1 \ + -divide_by 1 \ + -phase 0 ] + } + + + # -------------------- # + # - - # + # --- SYSTEM CLOCK --- # + # - - # + # -------------------- # + + # This is the CK clock + foreach { ck_pin } $ck_pins { + create_generated_clock -multiply_by 1 -source $pll_write_clock -master_clock "$local_pll_write_clk" $ck_pin -name $ck_pin + set_clock_uncertainty -to [ get_clocks $ck_pin ] $t(WL_JITTER) + } + + # This is the CK#clock + foreach { ckn_pin } $ckn_pins { + create_generated_clock -multiply_by 1 -invert -source $pll_write_clock -master_clock "$local_pll_write_clk" $ckn_pin -name $ckn_pin + set_clock_uncertainty -to [ get_clocks $ckn_pin ] $t(WL_JITTER) + } + + # ------------------- # + # - - # + # --- READ CLOCKS --- # + # - - # + # ------------------- # + + foreach dqs_in_clock_struct $dqs_in_clocks { + array set dqs_in_clock $dqs_in_clock_struct + # This is the DQS clock for Read Capture analysis (micro model) + create_clock -period $t(CK) -waveform [ list 0 $half_period ] $dqs_in_clock(dqs_pin) -name $dqs_in_clock(dqs_pin)_IN -add + + # Clock Uncertainty is accounted for by the ...pathjitter parameters + set_clock_uncertainty -from [ get_clocks $dqs_in_clock(dqs_pin)_IN ] 0 + } + + # -------------------- # + # - - # + # --- WRITE CLOCKS --- # + # - - # + # -------------------- # + + # This is the DQS clock for Data Write analysis (micro model) + foreach dqs_out_clock_struct $dqs_out_clocks { + array set dqs_out_clock $dqs_out_clock_struct + create_generated_clock -multiply_by 1 -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqs_out_clock(dst) -name $dqs_out_clock(dst)_OUT -add + + # Clock Uncertainty is accounted for by the ...pathjitter parameters + set_clock_uncertainty -to [ get_clocks $dqs_out_clock(dst)_OUT ] 0 + } + + # This is the DQS#clock for Data Write analysis (micro model) + foreach dqsn_out_clock_struct $dqsn_out_clocks { + array set dqsn_out_clock $dqsn_out_clock_struct + create_generated_clock -multiply_by 1 -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqsn_out_clock(dst) -name $dqsn_out_clock(dst)_OUT -add + + # Clock Uncertainty is accounted for by the ...pathjitter parameters + set_clock_uncertainty -to [ get_clocks $dqsn_out_clock(dst)_OUT ] 0 + } + + ################## + # # + # READ DATA PATH # + # # + ################## + + foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups { + foreach { dq_pin } $dq_pins { + if {[get_collection_size [get_registers -nowarn $read_capture_ddio]] > 0} { + set_max_delay -from [get_ports $dq_pin] -to $read_capture_ddio 0 + set_min_delay -from [get_ports $dq_pin] -to $read_capture_ddio [expr 0-$half_period] + } + + # Specifies the maximum delay difference between the DQ pin and the DQS pin: + set_input_delay -max $final_data_input_max_delay -clock [get_clocks ${dqs_pin}_IN ] [get_ports $dq_pin] -add_delay + + # Specifies the minimum delay difference between the DQ pin and the DQS pin: + set_input_delay -min $final_data_input_min_delay -clock [get_clocks ${dqs_pin}_IN ] [get_ports $dq_pin] -add_delay + } + } + + ################### + # # + # WRITE DATA PATH # + # # + ################### + + foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups { + foreach { dq_pin } $dq_pins { + # Specifies the minimum delay difference between the DQS pin and the DQ pins: + set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay + + # Specifies the maximum delay difference between the DQS pin and the DQ pins: + set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay + } + } + + foreach { dqsn_pin } $dqsn_pins { dq_pins } $q_groups { + foreach { dq_pin } $dq_pins { + # Specifies the minimum delay difference between the DQS#pin and the DQ pins: + set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay + + # Specifies the maximum delay difference between the DQS#pin and the DQ pins: + set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay + } + } + + foreach dqs_out_clock_struct $dqs_out_clocks { + array set dqs_out_clock $dqs_out_clock_struct + + if { [string length $dqs_out_clock(dm_pin)] > 0 } { + # Specifies the minimum delay difference between the DQS and the DM pins: + set_output_delay -min $data_output_min_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay + + # Specifies the maximum delay difference between the DQS and the DM pins: + set_output_delay -max $data_output_max_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay + } + } + + foreach dqsn_out_clock_struct $dqsn_out_clocks { + array set dqsn_out_clock $dqsn_out_clock_struct + + if { [string length $dqsn_out_clock(dm_pin)] > 0 } { + # Specifies the minimum delay difference between the DQS and the DM pins: + set_output_delay -min $data_output_min_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay + + # Specifies the maximum delay difference between the DQS and the DM pins: + set_output_delay -max $data_output_max_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay + } + } + + ################## + # # + # DQS vs CK PATH # + # # + ################## + + foreach { ck_pin } $ck_pins { + set_output_delay -add_delay -clock [get_clocks $ck_pin] -max [ddr3_p0_round_3dp [expr $t(CK) - $t(DQSS)*$t(CK) - $board(minCK_DQS_skew) ]] $dqs_pins + set_output_delay -add_delay -clock [get_clocks $ck_pin] -min [ddr3_p0_round_3dp [expr $t(DQSS)*$t(CK) - $board(maxCK_DQS_skew) ]] $dqs_pins + set_false_path -to [get_clocks $ck_pin] -fall_from [get_clocks $local_pll_write_clk ] + } + + ############ + # # + # A/C PATH # + # # + ############ + + foreach { ck_pin } $ck_pins { + # ac_pins can contain input ports such as mem_err_out_n + # Loop through each ac pin to make sure we only apply set_output_delay to output ports + foreach { ac_pin } $ac_pins { + set ac_port [ get_ports $ac_pin ] + if {[get_collection_size $ac_port] > 0} { + if [ get_port_info -is_output_port $ac_port ] { + # Specifies the minimum delay difference between the DQS pin and the address/control pins: + set_output_delay -min [ddr3_p0_round_3dp [expr {$ac_min_delay + $t(CK)/2}]] -clock [get_clocks $ck_pin] $ac_port -add_delay + + # Specifies the maximum delay difference between the DQS pin and the address/control pins: + set_output_delay -max [ddr3_p0_round_3dp [expr {$ac_max_delay + $t(CK)/2}]] -clock [get_clocks $ck_pin] $ac_port -add_delay + } + } + } + } + + # Only the rising edge-launched control data needs to be timing analyzed in full rate + set_false_path -fall_from [ get_clocks ${local_pll_write_clk} ] -to [ get_ports $ac_pins ] + + ########################## + # # + # MULTICYCLE CONSTRAINTS # + # # + ########################## + + + # If powerdown feature is enabled, multicycle path from core logic to the CK generator. + # The PHY must be idle several cycles before entering and after exiting powerdown mode. + if { [get_collection_size [get_registers -nowarn ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*]] > 0 } { + set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*] -end -setup 4 + set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*] -end -hold 4 + } + + + + # These transfers are from a full-rate clock to a "half-rate" clock (this may be even slower than half-rate). + # The transfer should be allowed up to the entire slow (latch) period, but the STA analysis + # is interpreted as one fast period. We can at least force it to use 2 fast periods. + set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_clock] -start -setup $write_to_avl_clk_ratio + set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_clock] -start -hold [expr $write_to_avl_clk_ratio - 1] + + + + set read_fifo_read_dff ${prefix}|*p0|*altdq_dqs2_inst|*read_fifo~OUTPUT_DFF_* + set read_fifo_write_address_dff ${prefix}|*p0|*altdq_dqs2_inst|*read_fifo~WRITE_ADDRESS_DFF + set read_fifo_read_address_dff ${prefix}|*p0|*altdq_dqs2_inst|*read_fifo~READ_ADDRESS_DFF + set lfifo_in_read_en_dff ${prefix}|*p0|*lfifo~LFIFO_IN_READ_EN_DFF + set lfifo_in_read_en_full_dff ${prefix}|*p0|*lfifo~LFIFO_IN_READ_EN_FULL_DFF + set lfifo_dff_reg ${prefix}|*p0|*lfifo~LFIFO_OUT_OCT_LFIFO_DFF + set lfifo_out_rden_dff ${prefix}|*p0|*lfifo~LFIFO_OUT_RDEN_DFF + set lfifo_out_rdata_valid_dff ${prefix}|*p0|*lfifo~LFIFO_OUT_RDATA_VALID_DFF + set os_oct_ddio_oe_reg ${prefix}|*p0|*os_oct_ddio_oe~DFF + set lfifo_rd_latency_dff ${prefix}|*p0|*lfifo~RD_LATENCY_DFF* + set vfifo_qvld_in_dff ${prefix}|*p0|*altdq_dqs2_inst|vfifo~QVLD_IN_DFF + set vfifo_inc_wr_ptr_dff ${prefix}|*p0|*vfifo~INC_WR_PTR_DFF + set phase_align_dff ${prefix}|*p0|*altdq_dqs2_inst|phase_align_os~DFF* + set os_oe_reg ${prefix}|*p0|*os_oe_reg + set phase_align_dff ${prefix}|*p0|*phase_align_os~DFF* + set hphy_ff ${prefix}|*p0|*umemphy|hphy_inst~FF_* + set hmc_ff ${prefix}|*c0|hmc_inst~FF_* + set phy_read_latency_counter $hphy_ff + set read_fifo_reset $hphy_ff + set phy_reset_mem_stable $hphy_ff + + set after_u2b 0 + if {[get_collection_size [get_registers -nowarn $read_fifo_write_address_dff]] > 0} { + set after_u2b 1 + } + + if {$after_u2b} { + + set_multicycle_path -from $hphy_ff -to $lfifo_in_read_en_full_dff -end -setup 2 + set_multicycle_path -from $hphy_ff -to $lfifo_in_read_en_full_dff -end -hold 1 + + set_multicycle_path -from $read_fifo_reset -to $read_fifo_read_address_dff -end -setup 2 + set_multicycle_path -from $read_fifo_reset -to $read_fifo_read_address_dff -end -hold 1 + + if {$::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) > 0} { + if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} { + set_multicycle_path -from [get_clocks $local_pll_afi_clk] -to [get_clocks $local_pll_avl_phy_clk] -setup 2 + set_multicycle_path -from [get_clocks $local_pll_afi_clk] -to [get_clocks $local_pll_avl_phy_clk] -hold 1 + + set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_phy_clk] -setup 2 + set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_phy_clk] -hold 1 + } + + set_multicycle_path -from [get_clocks $local_pll_config_clock] -to [get_clocks $local_pll_avl_clock] -setup 2 + set_multicycle_path -from [get_clocks $local_pll_config_clock] -to [get_clocks $local_pll_avl_clock] -hold 1 + } + + set_false_path -from $hmc_ff -to ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out* + set_false_path -from $hphy_ff -to $lfifo_in_read_en_dff + set_false_path -from $hmc_ff -to $lfifo_in_read_en_dff + set_false_path -from $hphy_ff -to $vfifo_inc_wr_ptr_dff + set_false_path -from $hmc_ff -to $vfifo_qvld_in_dff + set_false_path -from $lfifo_out_rdata_valid_dff -to $hphy_ff + set_false_path -from $phy_reset_mem_stable -to $vfifo_qvld_in_dff + set_false_path -from $phy_read_latency_counter -to $lfifo_rd_latency_dff + set_false_path -from $hphy_ff -to ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out* + set_false_path -from $hphy_ff -to ${prefix}|*p0|*umemphy|*altdq_dqs2_inst|*output_path_gen[*].ddio_out* + set_false_path -from $hphy_ff -to ${prefix}|*p0|*umemphy|*altdq_dqs2_inst|extra_output_pad_gen[*].ddio_out* + set_false_path -from $hphy_ff -to $hphy_ff + set_false_path -from $hmc_ff -to $hphy_ff + set_false_path -from $hphy_ff -to $hmc_ff + set_false_path -from $hphy_ff -to $phase_align_dff + set_false_path -from ${prefix}|*s0|* -to [get_clocks $local_pll_write_clk] + set_false_path -from [get_clocks $local_pll_write_clk] -to ${prefix}|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*] + + set_false_path -from [get_clocks $local_pll_avl_phy_clk] -to [get_clocks $local_pll_write_clk] + + } + + + if { [get_collection_size [get_registers -nowarn ${prefix}|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]]] > 0 } { + set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]] -end -setup 2 + set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]] -end -hold 1 + } + + ########################## + # # + # FALSE PATH CONSTRAINTS # + # # + ########################## + + # Cut paths for memory clocks / async resets to avoid unconstrained warnings + foreach { pin } [concat $dqsn_pins $ck_pins $ckn_pins $reset_pins] { + set_false_path -to [get_ports $pin] + } + + if { ! $synthesis_flow } { + foreach dqs_in_clock_struct $dqs_in_clocks dqsn_out_clock_struct $dqsn_out_clocks { + array set dqs_in_clock $dqs_in_clock_struct + array set dqsn_out_clock $dqsn_out_clock_struct + + set_clock_groups -physically_exclusive -group "$dqs_in_clock(dqs_pin)_IN" -group "$dqs_in_clock(dqs_pin)_OUT $dqsn_out_clock(dst)_OUT" + + # Cut paths between AFI Clock and Read Capture Registers + set_false_path -from [get_clocks $local_pll_afi_clk] -to [get_clocks $dqs_in_clock(dqs_pin)_IN] + + } + } + + foreach dqs_out_clock_struct $dqs_out_clocks { + array set dqs_out_clock $dqs_out_clock_struct + set_false_path -from $read_fifo_reset -to [ get_clocks $dqs_out_clock(dst)_OUT ] + } + + # The paths between DQS_ENA_CLK and DQS_IN are calibrated, so they must not be analyzed + set_false_path -from [get_clocks $local_pll_write_clk] -to [get_clocks {*_IN}] + + + + # The following registers serve as anchors for the pin_map.tcl + # script and are not used by the IP during memory operation + + # Cut internal calibrated paths + set dqs_delay_chain_pst_dff ${prefix}|*p0|*altdq_dqs2_inst|dqs_delay_chain~POSTAMBLE_DFF + if {$after_u2b} { + set_false_path -from ${prefix}|*p0|*altdq_dqs2_inst|dqs_enable_ctrl~* -to $dqs_delay_chain_pst_dff + } + + + # ------------------------------ # + # - - # + # --- FITTER OVERCONSTRAINTS --- # + # - - # + # ------------------------------ # + if {$fit_flow} { + + + if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} { + set_clock_uncertainty -from [get_clocks $local_pll_afi_clk] -to [get_clocks $local_pll_avl_phy_clk] -add -setup 0.300 + } + if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} { + set_clock_uncertainty -from [get_clocks $local_pll_avl_phy_clk] -to [get_clocks $local_pll_avl_clock] -add -hold 0.150 + set_clock_uncertainty -from [get_clocks $local_pll_avl_clock] -to [get_clocks $local_pll_avl_phy_clk] -add -hold 0.150 + } + set_min_delay -to $hmc_ff 0.500 + + } + + # -------------------------------- # + # - - # + # --- TIMING MODEL ADJUSTMENTS --- # + # - - # + # -------------------------------- # + +} + +if {(($::quartus(nameofexecutable) ne "quartus_fit") && ($::quartus(nameofexecutable) ne "quartus_map"))} { + set dqs_clocks [ddr3_p0_get_all_instances_dqs_pins ddr3_p0_ddr_db] + # Leave clocks active when in debug mode + if {[llength $dqs_clocks] > 0 && !$debug} { + post_sdc_message info "Setting DQS clocks as inactive; use Report DDR to timing analyze DQS clocks" + set_active_clocks [remove_from_collection [get_active_clocks] [get_clocks $dqs_clocks]] + } +} + +###################### +# # +# REPORT DDR COMMAND # +# # +###################### + +add_ddr_report_command "source [list [file join [file dirname [info script]] ${::GLOBAL_ddr3_p0_corename}_report_timing.tcl]]" + diff --git a/ip/altera/ddr3/ddr3_p0.sv b/ip/altera/ddr3/ddr3_p0.sv new file mode 100644 index 0000000..c530bbf --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0.sv @@ -0,0 +1,615 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_ddr3_hard_phy_core; -name IP_TOOL_VERSION 15.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100" *) +module ddr3_p0 ( + global_reset_n, + soft_reset_n, + csr_soft_reset_req, + parallelterminationcontrol, + seriesterminationcontrol, + pll_mem_clk, + pll_write_clk, + pll_write_clk_pre_phy_clk, + pll_addr_cmd_clk, + pll_avl_clk, + pll_config_clk, + pll_mem_phy_clk, + afi_phy_clk, + pll_avl_phy_clk, + pll_locked, + dll_pll_locked, + dll_delayctrl, + dll_clk, + ctl_reset_n, + afi_reset_n, + afi_reset_export_n, + afi_clk, + afi_half_clk, + afi_addr, + afi_ba, + afi_cke, + afi_cs_n, + afi_ras_n, + afi_we_n, + afi_cas_n, + afi_rst_n, + afi_odt, + afi_mem_clk_disable, + afi_dqs_burst, + afi_wdata, + afi_wdata_valid, + afi_dm, + afi_rdata, + afi_rdata_en, + afi_rdata_en_full, + afi_rdata_valid, + afi_cal_success, + afi_cal_fail, + afi_wlat, + afi_rlat, + csr_clk, + csr_reset_n, + csr_addr, + csr_be, + csr_rdata, + csr_read_req, + csr_wdata, + csr_write_req, + csr_rdata_valid, + csr_waitrequest, + avl_read, + avl_write, + avl_address, + avl_writedata, + avl_waitrequest, + avl_readdata, + cfg_addlat, + cfg_bankaddrwidth, + cfg_caswrlat, + cfg_coladdrwidth, + cfg_csaddrwidth, + cfg_devicewidth, + cfg_dramconfig, + cfg_interfacewidth, + cfg_rowaddrwidth, + cfg_tcl, + cfg_tmrd, + cfg_trefi, + cfg_trfc, + cfg_twr, + io_intaddrdout, + io_intbadout, + io_intcasndout, + io_intckdout, + io_intckedout, + io_intckndout, + io_intcsndout, + io_intdmdout, + io_intdqdin, + io_intdqdout, + io_intdqoe, + io_intdqsbdout, + io_intdqsboe, + io_intdqsdout, + io_intdqslogicdqsena, + io_intdqslogicfiforeset, + io_intdqslogicincrdataen, + io_intdqslogicincwrptr, + io_intdqslogicoct, + io_intdqslogicrdatavalid, + io_intdqslogicreadlatency, + io_intdqsoe, + io_intodtdout, + io_intrasndout, + io_intresetndout, + io_intwendout, + io_intafirlat, + io_intafiwlat, + io_intaficalfail, + io_intaficalsuccess, + mem_a, + mem_ba, + mem_ck, + mem_ck_n, + mem_cke, + mem_cs_n, + mem_dm, + mem_ras_n, + mem_cas_n, + mem_we_n, + mem_dq, + mem_dqs, + mem_dqs_n, + mem_reset_n, + mem_odt, + avl_clk, + scc_clk, + avl_reset_n, + scc_reset_n, + scc_data, + scc_dqs_ena, + scc_dqs_io_ena, + scc_dq_ena, + scc_dm_ena, + scc_upd, + capture_strobe_tracking, + phy_clk, + ctl_clk, + phy_reset_n +); + + +// ******************************************************************************************************************************** +// BEGIN PARAMETER SECTION +// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver. +parameter DEVICE_FAMILY = "Cyclone V"; +parameter IS_HHP_HPS = "false"; + +// choose between abstract (fast) and regular model +`ifndef ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL + `define ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL 0 +`endif + +parameter ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL = `ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL; + +localparam FAST_SIM_MODEL = ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL; + + +// On-chip termination +parameter OCT_TERM_CONTROL_WIDTH = 16; + +// PHY-Memory Interface +// Memory device specific parameters, they are set according to the memory spec. +parameter MEM_IF_ADDR_WIDTH = 13; +parameter MEM_IF_BANKADDR_WIDTH = 3; +parameter MEM_IF_CK_WIDTH = 1; +parameter MEM_IF_CLK_EN_WIDTH = 1; +parameter MEM_IF_CS_WIDTH = 1; +parameter MEM_IF_DM_WIDTH = 2; +parameter MEM_IF_CONTROL_WIDTH = 1; +parameter MEM_IF_DQ_WIDTH = 16; +parameter MEM_IF_DQS_WIDTH = 2; +parameter MEM_IF_READ_DQS_WIDTH = 2; +parameter MEM_IF_WRITE_DQS_WIDTH = 2; +parameter MEM_IF_ODT_WIDTH = 1; + + +// DLL Interface +parameter DLL_DELAY_CTRL_WIDTH = 7; + +parameter SCC_DATA_WIDTH = 1; + +// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture. +// Read valid prediction FIFO +parameter READ_VALID_FIFO_SIZE = 16; + +// Data resynchronization FIFO +parameter READ_FIFO_SIZE = 8; + +parameter MR1_ODS = 0; +parameter MR1_RTT = 2; +parameter MR2_RTT_WR = 0; + + +// The DLL offset control width +parameter DLL_OFFSET_CTRL_WIDTH = 6; + +parameter CALIB_REG_WIDTH = 8; + + +parameter TB_PROTOCOL = "DDR3"; +parameter TB_MEM_CLK_FREQ = "300.0"; +parameter TB_RATE = "FULL"; +parameter TB_MEM_DQ_WIDTH = "16"; +parameter TB_MEM_DQS_WIDTH = "2"; +parameter TB_PLL_DLL_MASTER = "true"; + +parameter FAST_SIM_CALIBRATION = "false"; + +// CSR Port parameters +parameter CSR_ADDR_WIDTH = 8; +parameter CSR_DATA_WIDTH = 32; +parameter CSR_BE_WIDTH = 4; + +parameter AC_ROM_INIT_FILE_NAME = "ddr3_s0_AC_ROM.hex"; +parameter INST_ROM_INIT_FILE_NAME = "ddr3_s0_inst_ROM.hex"; + +localparam SIM_FILESET = ("false" == "true"); + + +// END PARAMETER SECTION +// ******************************************************************************************************************************** + + +// ******************************************************************************************************************************** +// BEGIN PORT SECTION + + +// When the PHY is selected to be a PLL/DLL SLAVE, the PLL and DLL are instantied at the top level of the example design +input pll_mem_clk; +input pll_write_clk; +input pll_write_clk_pre_phy_clk; +input pll_addr_cmd_clk; +input pll_avl_clk; +input pll_config_clk; +input pll_locked; +input pll_mem_phy_clk; +input afi_phy_clk; +input pll_avl_phy_clk; + + + + +input [DLL_DELAY_CTRL_WIDTH-1:0] dll_delayctrl; +output dll_pll_locked; +output dll_clk; + + + +// Reset Interface, AFI 2.0 +input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL) +input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset +output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain +output afi_reset_export_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain + // should be used to reset system level afi_clk domain logic +output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain + // should be used by hard controller only +input csr_soft_reset_req; // Reset request (active_high) being driven by external debug master + +// OCT termination control signals +input [OCT_TERM_CONTROL_WIDTH-1:0] parallelterminationcontrol; +input [OCT_TERM_CONTROL_WIDTH-1:0] seriesterminationcontrol; + + +// PHY-Controller Interface, AFI 2.0 +// Control Interface +input [19:0] afi_addr; // address +input [2:0] afi_ba; // bank +input [1:0] afi_cke; // clock enable +input [1:0] afi_cs_n; // chip select +input [0:0] afi_ras_n; +input [0:0] afi_we_n; +input [0:0] afi_cas_n; +input [1:0] afi_odt; +input [0:0] afi_rst_n; +input [0:0] afi_mem_clk_disable; + + +// Write data interface +input [4:0] afi_dqs_burst; +input [79:0] afi_wdata; // write data +input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec +input [9:0] afi_dm; // write data mask + +// Read data interface +output [79:0] afi_rdata; // read data +input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY +input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable +output [0:0] afi_rdata_valid; // read data valid + +// Status interface +output afi_cal_success; // calibration success +output afi_cal_fail; // calibration failure + +output [3:0] afi_wlat; +output [4:0] afi_rlat; + + +// Avalon interface to the sequencer +input [15:0] avl_address; +input avl_read; +output [31:0] avl_readdata; +output avl_waitrequest; +input avl_write; +input [31:0] avl_writedata; + + +// Configuration interface to the memory controller +input [7:0] cfg_addlat; +input [7:0] cfg_bankaddrwidth; +input [7:0] cfg_caswrlat; +input [7:0] cfg_coladdrwidth; +input [7:0] cfg_csaddrwidth; +input [7:0] cfg_devicewidth; +input [23:0] cfg_dramconfig; +input [7:0] cfg_interfacewidth; +input [7:0] cfg_rowaddrwidth; +input [7:0] cfg_tcl; +input [7:0] cfg_tmrd; +input [15:0] cfg_trefi; +input [7:0] cfg_trfc; +input [7:0] cfg_twr; + + +// IO/bypass interface to the core (or soft controller) +input [63:0] io_intaddrdout; +input [11:0] io_intbadout; +input [3:0] io_intcasndout; +input [3:0] io_intckdout; +input [7:0] io_intckedout; +input [3:0] io_intckndout; +input [7:0] io_intcsndout; +input [19:0] io_intdmdout; +output [179:0] io_intdqdin; +input [179:0] io_intdqdout; +input [89:0] io_intdqoe; +input [19:0] io_intdqsbdout; +input [9:0] io_intdqsboe; +input [19:0] io_intdqsdout; +input [9:0] io_intdqslogicdqsena; +input [4:0] io_intdqslogicfiforeset; +input [9:0] io_intdqslogicincrdataen; +input [9:0] io_intdqslogicincwrptr; +input [9:0] io_intdqslogicoct; +output [4:0] io_intdqslogicrdatavalid; +input [24:0] io_intdqslogicreadlatency; +input [9:0] io_intdqsoe; +input [7:0] io_intodtdout; +input [3:0] io_intrasndout; +input [3:0] io_intresetndout; +input [3:0] io_intwendout; +output [4:0] io_intafirlat; +output [3:0] io_intafiwlat; +output io_intaficalfail; +output io_intaficalsuccess; + + +// PHY-Memory Interface + +output [MEM_IF_ADDR_WIDTH-1:0] mem_a; // address +output [MEM_IF_BANKADDR_WIDTH-1:0] mem_ba; // bank +output [MEM_IF_CK_WIDTH-1:0] mem_ck; // differential address and command clock +output [MEM_IF_CK_WIDTH-1:0] mem_ck_n; +output [MEM_IF_CLK_EN_WIDTH-1:0] mem_cke; // clock enable +output [MEM_IF_CS_WIDTH-1:0] mem_cs_n; // chip select +output [MEM_IF_DM_WIDTH-1:0] mem_dm; // data mask +output [MEM_IF_CONTROL_WIDTH-1:0] mem_ras_n; +output [MEM_IF_CONTROL_WIDTH-1:0] mem_cas_n; +output [MEM_IF_CONTROL_WIDTH-1:0] mem_we_n; +inout [MEM_IF_DQ_WIDTH-1:0] mem_dq; // bidirectional data bus +inout [MEM_IF_DQS_WIDTH-1:0] mem_dqs; // bidirectional data strobe +inout [MEM_IF_DQS_WIDTH-1:0] mem_dqs_n; // differential bidirectional data strobe +output [MEM_IF_ODT_WIDTH-1:0] mem_odt; +output mem_reset_n; + + +// PLL Interface +input afi_clk; +input afi_half_clk; + +wire pll_dqs_ena_clk; + +// CSR Port input/output +input csr_clk; +input csr_reset_n; +input [CSR_ADDR_WIDTH - 1: 0] csr_addr; +input [CSR_BE_WIDTH - 1: 0] csr_be; +input csr_read_req; +input [CSR_DATA_WIDTH - 1: 0] csr_wdata; +input csr_write_req; +output [CSR_DATA_WIDTH - 1: 0] csr_rdata; +output csr_rdata_valid; +output csr_waitrequest; + + +output avl_clk; +output scc_clk; +output avl_reset_n; +output scc_reset_n; + +input [SCC_DATA_WIDTH-1:0] scc_data; +input [MEM_IF_READ_DQS_WIDTH-1:0] scc_dqs_ena; +input [MEM_IF_READ_DQS_WIDTH-1:0] scc_dqs_io_ena; +input [MEM_IF_DQ_WIDTH-1:0] scc_dq_ena; +input [MEM_IF_DM_WIDTH-1:0] scc_dm_ena; +input [0:0] scc_upd; +output [MEM_IF_READ_DQS_WIDTH-1:0] capture_strobe_tracking; + +output phy_clk; +output ctl_clk; +output phy_reset_n; + + +// END PORT SECTION + + +initial $display("Using %0s core emif simulation models", FAST_SIM_MODEL ? "Fast" : "Regular"); + + + + +assign avl_clk = pll_avl_clk; +assign scc_clk = pll_config_clk; + + + +assign pll_dqs_ena_clk = pll_write_clk; + +ddr3_p0_acv_hard_memphy #( + .DEVICE_FAMILY(DEVICE_FAMILY), + .IS_HHP_HPS(IS_HHP_HPS), + .OCT_SERIES_TERM_CONTROL_WIDTH(OCT_TERM_CONTROL_WIDTH), + .OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_TERM_CONTROL_WIDTH), + .MEM_ADDRESS_WIDTH(MEM_IF_ADDR_WIDTH), + .MEM_BANK_WIDTH(MEM_IF_BANKADDR_WIDTH), + .MEM_CLK_EN_WIDTH(MEM_IF_CLK_EN_WIDTH), + .MEM_CK_WIDTH(MEM_IF_CK_WIDTH), + .MEM_ODT_WIDTH(MEM_IF_ODT_WIDTH), + .MEM_DQS_WIDTH(MEM_IF_DQS_WIDTH), + .MEM_IF_CS_WIDTH(MEM_IF_CS_WIDTH), + .MEM_DM_WIDTH(MEM_IF_DM_WIDTH), + .MEM_CONTROL_WIDTH(MEM_IF_CONTROL_WIDTH), + .MEM_DQ_WIDTH(MEM_IF_DQ_WIDTH), + .MEM_READ_DQS_WIDTH(MEM_IF_READ_DQS_WIDTH), + .MEM_WRITE_DQS_WIDTH(MEM_IF_WRITE_DQS_WIDTH), + .DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH), + .MR1_ODS(MR1_ODS), + .MR1_RTT(MR1_RTT), + .MR2_RTT_WR(MR2_RTT_WR), + .CSR_ADDR_WIDTH(CSR_ADDR_WIDTH), + .CSR_DATA_WIDTH(CSR_DATA_WIDTH), + .CSR_BE_WIDTH(CSR_BE_WIDTH), + .CALIB_REG_WIDTH(CALIB_REG_WIDTH), + .TB_PROTOCOL(TB_PROTOCOL), + .TB_MEM_CLK_FREQ(TB_MEM_CLK_FREQ), + .TB_RATE(TB_RATE), + .TB_MEM_DQ_WIDTH(TB_MEM_DQ_WIDTH), + .TB_MEM_DQS_WIDTH(TB_MEM_DQS_WIDTH), + .TB_PLL_DLL_MASTER(TB_PLL_DLL_MASTER), + .FAST_SIM_MODEL(FAST_SIM_MODEL), + .FAST_SIM_CALIBRATION(FAST_SIM_CALIBRATION), + .AC_ROM_INIT_FILE_NAME(AC_ROM_INIT_FILE_NAME), + .INST_ROM_INIT_FILE_NAME(INST_ROM_INIT_FILE_NAME) +) umemphy ( + .global_reset_n(global_reset_n), + .soft_reset_n(soft_reset_n & ~csr_soft_reset_req), + .ctl_reset_n(ctl_reset_n), + .ctl_reset_export_n(afi_reset_export_n), + .afi_reset_n(afi_reset_n), + .pll_locked(pll_locked), + .oct_ctl_rt_value(parallelterminationcontrol), + .oct_ctl_rs_value(seriesterminationcontrol), + .afi_addr(afi_addr), + .afi_ba(afi_ba), + .afi_cke(afi_cke), + .afi_cs_n(afi_cs_n), + .afi_ras_n(afi_ras_n), + .afi_we_n(afi_we_n), + .afi_cas_n(afi_cas_n), + .afi_rst_n(afi_rst_n), + .afi_odt(afi_odt), + .afi_mem_clk_disable(afi_mem_clk_disable), + .afi_dqs_burst(afi_dqs_burst), + .afi_wdata(afi_wdata), + .afi_wdata_valid(afi_wdata_valid), + .afi_dm(afi_dm), + .afi_rdata(afi_rdata), + .afi_rdata_en(afi_rdata_en), + .afi_rdata_en_full(afi_rdata_en_full), + .afi_rdata_valid(afi_rdata_valid), + .afi_wlat(afi_wlat), + .afi_rlat(afi_rlat), + .afi_cal_success(afi_cal_success), + .afi_cal_fail(afi_cal_fail), + .avl_read(avl_read), + .avl_write(avl_write), + .avl_address(avl_address), + .avl_writedata(avl_writedata), + .avl_waitrequest(avl_waitrequest), + .avl_readdata(avl_readdata), + .cfg_addlat(cfg_addlat), + .cfg_bankaddrwidth(cfg_bankaddrwidth), + .cfg_caswrlat(cfg_caswrlat), + .cfg_coladdrwidth(cfg_coladdrwidth), + .cfg_csaddrwidth(cfg_csaddrwidth), + .cfg_devicewidth(cfg_devicewidth), + .cfg_dramconfig(cfg_dramconfig), + .cfg_interfacewidth(cfg_interfacewidth), + .cfg_rowaddrwidth(cfg_rowaddrwidth), + .cfg_tcl(cfg_tcl), + .cfg_tmrd(cfg_tmrd), + .cfg_trefi(cfg_trefi), + .cfg_trfc(cfg_trfc), + .cfg_twr(cfg_twr), + .io_intaddrdout(io_intaddrdout), + .io_intbadout(io_intbadout), + .io_intcasndout(io_intcasndout), + .io_intckdout(io_intckdout), + .io_intckedout(io_intckedout), + .io_intckndout(io_intckndout), + .io_intcsndout(io_intcsndout), + .io_intdmdout(io_intdmdout), + .io_intdqdin(io_intdqdin), + .io_intdqdout(io_intdqdout), + .io_intdqoe(io_intdqoe), + .io_intdqsbdout(io_intdqsbdout), + .io_intdqsboe(io_intdqsboe), + .io_intdqsdout(io_intdqsdout), + .io_intdqslogicdqsena(io_intdqslogicdqsena), + .io_intdqslogicfiforeset(io_intdqslogicfiforeset), + .io_intdqslogicincrdataen(io_intdqslogicincrdataen), + .io_intdqslogicincwrptr(io_intdqslogicincwrptr), + .io_intdqslogicoct(io_intdqslogicoct), + .io_intdqslogicrdatavalid(io_intdqslogicrdatavalid), + .io_intdqslogicreadlatency(io_intdqslogicreadlatency), + .io_intdqsoe(io_intdqsoe), + .io_intodtdout(io_intodtdout), + .io_intrasndout(io_intrasndout), + .io_intresetndout(io_intresetndout), + .io_intwendout(io_intwendout), + .io_intafirlat(io_intafirlat), + .io_intafiwlat(io_intafiwlat), + .io_intaficalfail(io_intaficalfail), + .io_intaficalsuccess(io_intaficalsuccess), + .mem_a(mem_a), + .mem_ba(mem_ba), + .mem_ck(mem_ck), + .mem_ck_n(mem_ck_n), + .mem_cke(mem_cke), + .mem_cs_n(mem_cs_n), + .mem_dm(mem_dm), + .mem_ras_n(mem_ras_n), + .mem_cas_n(mem_cas_n), + .mem_we_n(mem_we_n), + .mem_reset_n(mem_reset_n), + .mem_dq(mem_dq), + .mem_dqs(mem_dqs), + .mem_dqs_n(mem_dqs_n), + .mem_odt(mem_odt), + .pll_afi_clk(afi_clk), + .pll_mem_clk(pll_mem_clk), + .pll_mem_phy_clk(pll_mem_phy_clk), + .pll_afi_phy_clk(afi_phy_clk), + .pll_avl_phy_clk(pll_avl_phy_clk), + .pll_write_clk(pll_write_clk), + .pll_write_clk_pre_phy_clk(pll_write_clk_pre_phy_clk), + .pll_addr_cmd_clk(pll_addr_cmd_clk), + .pll_afi_half_clk(afi_half_clk), + .pll_dqs_ena_clk(pll_dqs_ena_clk), + .seq_clk(afi_clk), + .csr_clk(csr_clk), + .csr_reset_n(csr_reset_n), + .csr_write_req(csr_write_req), + .csr_read_req(csr_read_req), + .csr_addr(csr_addr), + .csr_be(csr_be), + .csr_wdata(csr_wdata), + .csr_waitrequest(csr_waitrequest), + .csr_rdata(csr_rdata), + .csr_rdata_valid(csr_rdata_valid), + .reset_n_avl_clk(avl_reset_n), + .reset_n_scc_clk(scc_reset_n), + .scc_data(scc_data), + .scc_dqs_ena(scc_dqs_ena), + .scc_dqs_io_ena(scc_dqs_io_ena), + .scc_dq_ena(scc_dq_ena), + .scc_dm_ena(scc_dm_ena), + .scc_upd(scc_upd), + .capture_strobe_tracking(capture_strobe_tracking), + .phy_clk(phy_clk), + .ctl_clk(ctl_clk), + .phy_reset_n(phy_reset_n), + .pll_avl_clk(pll_avl_clk), + .pll_config_clk(pll_config_clk), + .dll_clk(dll_clk), + .dll_pll_locked(dll_pll_locked), + .dll_phy_delayctrl(dll_delayctrl) +); + + +endmodule + diff --git a/ip/altera/ddr3/ddr3_p0_acv_hard_addr_cmd_pads.v b/ip/altera/ddr3/ddr3_p0_acv_hard_addr_cmd_pads.v new file mode 100644 index 0000000..b748444 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_acv_hard_addr_cmd_pads.v @@ -0,0 +1,342 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module ddr3_p0_acv_hard_addr_cmd_pads( + /* + config_data_in, + config_clock_in, + config_io_ena, + config_update, + */ + reset_n, + reset_n_afi_clk, + pll_hr_clk, + pll_avl_phy_clk, + pll_afi_clk, + pll_mem_clk, + pll_write_clk, + phy_ddio_address, + dll_delayctrl_in, + phy_ddio_bank, + phy_ddio_cs_n, + phy_ddio_cke, + phy_ddio_odt, + phy_ddio_we_n, + phy_ddio_ras_n, + phy_ddio_cas_n, + phy_ddio_ck, + phy_ddio_reset_n, + phy_mem_address, + phy_mem_bank, + phy_mem_cs_n, + phy_mem_cke, + phy_mem_odt, + phy_mem_we_n, + phy_mem_ras_n, + phy_mem_cas_n, + phy_mem_reset_n, + phy_mem_ck, + phy_mem_ck_n +); + + parameter DEVICE_FAMILY = ""; + parameter MEM_ADDRESS_WIDTH = ""; + parameter MEM_BANK_WIDTH = ""; + parameter MEM_CHIP_SELECT_WIDTH = ""; + parameter MEM_CLK_EN_WIDTH = ""; + parameter MEM_CK_WIDTH = ""; + parameter MEM_ODT_WIDTH = ""; + parameter MEM_CONTROL_WIDTH = ""; + + parameter AFI_ADDRESS_WIDTH = ""; + parameter AFI_BANK_WIDTH = ""; + parameter AFI_CHIP_SELECT_WIDTH = ""; + parameter AFI_CLK_EN_WIDTH = ""; + parameter AFI_ODT_WIDTH = ""; + parameter AFI_CONTROL_WIDTH = ""; + parameter DLL_WIDTH = ""; + parameter ADC_PHASE_SETTING = ""; + parameter ADC_INVERT_PHASE = ""; + parameter IS_HHP_HPS = ""; + + /* + input config_data_in; + input config_clock_in; + input config_io_ena; + input config_update; + */ + input reset_n; + input reset_n_afi_clk; + input pll_afi_clk; + input pll_hr_clk; + input pll_avl_phy_clk; + input pll_mem_clk; + input pll_write_clk; + input [DLL_WIDTH-1:0] dll_delayctrl_in; + + input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address; + + input [AFI_BANK_WIDTH-1:0] phy_ddio_bank; + input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n; + input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke; + input [AFI_ODT_WIDTH-1:0] phy_ddio_odt; + input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n; + input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n; + input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck; + input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n; + input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n; + + output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address; + output [MEM_BANK_WIDTH-1:0] phy_mem_bank; + output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n; + output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke; + output [MEM_ODT_WIDTH-1:0] phy_mem_odt; + output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n; + output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n; + output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n; + output phy_mem_reset_n; + output [MEM_CK_WIDTH-1:0] phy_mem_ck; + output [MEM_CK_WIDTH-1:0] phy_mem_ck_n; + + /* ********* * + * A/C Logic * + * ********* */ + + localparam CMD_WIDTH = + MEM_CHIP_SELECT_WIDTH + + MEM_CLK_EN_WIDTH + + MEM_ODT_WIDTH + + MEM_CONTROL_WIDTH + + MEM_CONTROL_WIDTH + + MEM_CONTROL_WIDTH; + + localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1; + + localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false"; + + wire [AC_CLK_WIDTH-1:0] ac_clk; + generate + genvar i; + for (i = 0; i < AC_CLK_WIDTH; i = i + 1) + begin: address_gen + wire addr_cmd_clk; + ddr3_p0_acv_ldc # ( + .DLL_DELAY_CTRL_WIDTH(DLL_WIDTH), + .ADC_PHASE_SETTING(ADC_PHASE_SETTING), + .ADC_INVERT_PHASE(ADC_INVERT_PHASE), + .IS_HHP_HPS(IS_HHP_HPS) + ) acv_ac_ldc ( + .pll_hr_clk(pll_avl_phy_clk), + .pll_dq_clk(pll_write_clk), + .pll_dqs_clk (pll_mem_clk), + .dll_phy_delayctrl(dll_delayctrl_in), + .adc_clk_cps(ac_clk[i]) + ); + end + endgenerate + + ddr3_p0_generic_ddio uaddress_pad( + .datain(phy_ddio_address), + .halfratebypass(1'b1), + .dataout(phy_mem_address), + .clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}), + .clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0]) + ); + defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH; + + ddr3_p0_generic_ddio ubank_pad( + .datain(phy_ddio_bank), + .halfratebypass(1'b1), + .dataout(phy_mem_bank), + .clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}), + .clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH]) + ); + defparam ubank_pad.WIDTH = MEM_BANK_WIDTH; + + ddr3_p0_generic_ddio ucmd_pad( + .datain({ + phy_ddio_we_n, + phy_ddio_cas_n, + phy_ddio_ras_n, + phy_ddio_odt, + phy_ddio_cke, + phy_ddio_cs_n + }), + .halfratebypass(1'b1), + .dataout({ + phy_mem_we_n, + phy_mem_cas_n, + phy_mem_ras_n, + phy_mem_odt, + phy_mem_cke, + phy_mem_cs_n + }), + .clk_hr({CMD_WIDTH{pll_hr_clk}}), + .clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH]) + ); + defparam ucmd_pad.WIDTH = CMD_WIDTH; + + ddr3_p0_generic_ddio ureset_n_pad( + .datain(phy_ddio_reset_n), + .halfratebypass(1'b1), + .dataout(phy_mem_reset_n), + .clk_hr(pll_hr_clk), + .clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH]) + ); + defparam ureset_n_pad.WIDTH = 1; + + /* ************ * + * Config Logic * + * ************ */ + + wire [4:0] outputdelaysetting; + wire [4:0] outputenabledelaysetting; + wire outputhalfratebypass; + wire [4:0] inputdelaysetting; + + wire [1:0] rfifo_clock_select; + wire [2:0] rfifo_mode; + + /* + cyclonev_io_config ioconfig ( + .datain(config_data_in), + .clk(config_clock_in), + .ena(config_io_ena), + .update(config_update), + + .outputregdelaysetting(outputdelaysetting), + .outputenabledelaysetting(outputenabledelaysetting), + .outputhalfratebypass(outputhalfratebypass), + .readfiforeadclockselect(rfifo_clock_select), + .readfifomode(rfifo_mode), + + .padtoinputregisterdelaysetting(inputdelaysetting), + .dataout() + ); + */ + + /* *************** * + * Mem Clock Logic * + * *************** */ + + wire [MEM_CK_WIDTH-1:0] mem_ck_source; + wire [MEM_CK_WIDTH-1:0] mem_ck; + + generate + genvar clock_width; + for (clock_width=0; clock_width 0; ceil_log2 = ceil_log2 + 1) + value = value >> 1; + end +endfunction + +endmodule diff --git a/ip/altera/ddr3/ddr3_p0_acv_ldc.v b/ip/altera/ddr3/ddr3_p0_acv_ldc.v new file mode 100644 index 0000000..6a78865 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_acv_ldc.v @@ -0,0 +1,120 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module ddr3_p0_acv_ldc +( + pll_hr_clk, + pll_dq_clk, + pll_dqs_clk, + dll_phy_delayctrl, + afi_clk, + avl_clk, + adc_clk, + adc_clk_cps, + hr_clk +); +parameter DLL_DELAY_CTRL_WIDTH = ""; +parameter ADC_PHASE_SETTING = 0; +parameter ADC_INVERT_PHASE = "false"; +parameter IS_HHP_HPS = "false"; + +input pll_hr_clk; +input pll_dq_clk; +input pll_dqs_clk; +input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; +output afi_clk; +output avl_clk; +output adc_clk; +output adc_clk_cps; +output hr_clk; + +wire phy_clk_dqs; +wire phy_clk_dq; +wire phy_clk_hr; +wire phy_clk_dqs_2x; +wire phy_clk_addr_cmd; +wire phy_clk_addr_cmd_cps; + + +generate +if (IS_HHP_HPS == "true") begin + assign phy_clk_hr = pll_hr_clk; + assign phy_clk_dq = pll_dq_clk; + assign phy_clk_dqs = pll_dqs_clk; + assign phy_clk_dqs_2x = 1'b0; +end else begin + cyclonev_phy_clkbuf phy_clkbuf ( + .inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}), + .outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x}) + ); +end +endgenerate + +wire [3:0] leveled_dqs_clocks; +wire [3:0] leveled_hr_clocks; +wire hr_seq_clock; + +cyclonev_leveling_delay_chain leveling_delay_chain_dqs ( + .clkin (phy_clk_dqs), + .delayctrlin (dll_phy_delayctrl), + .clkout(leveled_dqs_clocks) +); +defparam leveling_delay_chain_dqs.physical_clock_source = "DQS"; +assign afi_clk = leveled_dqs_clocks[0]; + +cyclonev_leveling_delay_chain leveling_delay_chain_hr ( + .clkin (phy_clk_hr), + .delayctrlin (), + .clkout(leveled_hr_clocks) +); +defparam leveling_delay_chain_hr.physical_clock_source = "HR"; +assign avl_clk = leveled_hr_clocks[0]; + +cyclonev_clk_phase_select clk_phase_select_addr_cmd ( + .clkin(leveled_dqs_clocks), + .clkout(adc_clk_cps) +); +defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD"; +defparam clk_phase_select_addr_cmd.use_phasectrlin = "false"; +defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING; +defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE; + +cyclonev_clk_phase_select clk_phase_select_hr ( + .phasectrlin(), + .phaseinvertctrl(), + .dqsin(), +`ifndef SIMGEN + .clkin (leveled_hr_clocks[0]), +`else + .clkin (leveled_hr_clocks), +`endif + .clkout (hr_seq_clock) +); +defparam clk_phase_select_hr.physical_clock_source = "HR"; +defparam clk_phase_select_hr.use_phasectrlin = "false"; +defparam clk_phase_select_hr.phase_setting = 0; +assign hr_clk = hr_seq_clock; + +generate +if (ADC_INVERT_PHASE == "true") +begin + assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING]; +end else begin + assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING]; +end +endgenerate + +endmodule diff --git a/ip/altera/ddr3/ddr3_p0_altdqdqs.v b/ip/altera/ddr3/ddr3_p0_altdqdqs.v new file mode 100644 index 0000000..6d76659 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_altdqdqs.v @@ -0,0 +1,195 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module ddr3_p0_altdqdqs ( + core_clock_in, + reset_n_core_clock_in, + fr_clock_in, + hr_clock_in, + write_strobe_clock_in, + write_strobe, + strobe_ena_hr_clock_in, + read_write_data_io, + write_oe_in, + strobe_io, + output_strobe_ena, + strobe_n_io, + oct_ena_in, + read_data_out, + capture_strobe_out, + write_data_in, + extra_write_data_in, + extra_write_data_out, + parallelterminationcontrol_in, + seriesterminationcontrol_in, + config_data_in, + config_update, + config_dqs_ena, + config_io_ena, + config_extra_io_ena, + config_dqs_io_ena, + config_clock_in, + lfifo_rdata_en, + lfifo_rdata_en_full, + lfifo_rd_latency, + lfifo_reset_n, + lfifo_rdata_valid, + vfifo_qvld, + vfifo_inc_wr_ptr, + vfifo_reset_n, + rfifo_reset_n, + dll_delayctrl_in +); + + +input [7-1:0] dll_delayctrl_in; + +input core_clock_in; +input reset_n_core_clock_in; +input fr_clock_in; +input hr_clock_in; + +input write_strobe_clock_in; +input [3:0] write_strobe; +input strobe_ena_hr_clock_in; +inout [8-1:0] read_write_data_io; +input [2*8-1:0] write_oe_in; +inout strobe_io; +input [2-1:0] output_strobe_ena; +inout strobe_n_io; +input [2-1:0] oct_ena_in; +output [2 * 2 * 8-1:0] read_data_out; +output capture_strobe_out; +input [2 * 2 * 8-1:0] write_data_in; +input [2 * 2 * 1-1:0] extra_write_data_in; +output [1-1:0] extra_write_data_out; +input [16-1:0] parallelterminationcontrol_in; +input [16-1:0] seriesterminationcontrol_in; +input config_data_in; +input config_update; +input config_dqs_ena; +input [8-1:0] config_io_ena; +input [1-1:0] config_extra_io_ena; +input config_dqs_io_ena; +input config_clock_in; + +input [2-1:0] lfifo_rdata_en; +input [2-1:0] lfifo_rdata_en_full; +input [4:0] lfifo_rd_latency; +input lfifo_reset_n; +output lfifo_rdata_valid; +input [2-1:0] vfifo_qvld; +input [2-1:0] vfifo_inc_wr_ptr; +input vfifo_reset_n; +input rfifo_reset_n; + +parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = ""; + + + + + altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst ( + .core_clock_in( core_clock_in), + .reset_n_core_clock_in (reset_n_core_clock_in), + .fr_clock_in( fr_clock_in), + .hr_clock_in( hr_clock_in), + .write_strobe_clock_in (write_strobe_clock_in), + .write_strobe(write_strobe), + .strobe_ena_hr_clock_in( strobe_ena_hr_clock_in), + .read_write_data_io( read_write_data_io), + .write_oe_in( write_oe_in), + .strobe_io( strobe_io), + .output_strobe_ena( output_strobe_ena), + .strobe_n_io( strobe_n_io), + .oct_ena_in( oct_ena_in), + .read_data_out( read_data_out), + .capture_strobe_out( capture_strobe_out), + .write_data_in( write_data_in), + .extra_write_data_in( extra_write_data_in), + .extra_write_data_out( extra_write_data_out), + .parallelterminationcontrol_in( parallelterminationcontrol_in), + .seriesterminationcontrol_in( seriesterminationcontrol_in), + .config_data_in( config_data_in), + .config_update( config_update), + .config_dqs_ena( config_dqs_ena), + .config_io_ena( config_io_ena), + .config_extra_io_ena( config_extra_io_ena), + .config_dqs_io_ena( config_dqs_io_ena), + .config_clock_in( config_clock_in), + .lfifo_rdata_en(lfifo_rdata_en), + .lfifo_rdata_en_full(lfifo_rdata_en_full), + .lfifo_rd_latency(lfifo_rd_latency), + .lfifo_reset_n(lfifo_reset_n), + .lfifo_rdata_valid(lfifo_rdata_valid), + .vfifo_qvld(vfifo_qvld), + .vfifo_inc_wr_ptr(vfifo_inc_wr_ptr), + .vfifo_reset_n(vfifo_reset_n), + .rfifo_reset_n(rfifo_reset_n), + .dll_delayctrl_in(dll_delayctrl_in) + + ); + defparam altdq_dqs2_inst.PIN_WIDTH = 8; + defparam altdq_dqs2_inst.PIN_TYPE = "bidir"; + defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false"; + defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false"; + defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false"; + defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false"; + defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true"; + defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true"; + defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false"; + defparam altdq_dqs2_inst.INPUT_FREQ = 300.0; + defparam altdq_dqs2_inst.INPUT_FREQ_PS = "3333 ps"; + defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high"; + defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0; + defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0; + defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3; + defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true"; + defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true"; + defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false"; + defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true"; + defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true"; + defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true"; + defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false"; + defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true"; + defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true"; + defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false"; + defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1; + defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic"; + defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16; + defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16; + defparam altdq_dqs2_inst.DLL_WIDTH = 7; + defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false"; + defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1; + defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true"; + defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high"; + defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false"; + defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false"; + defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false"; + defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false"; + defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true"; + defparam altdq_dqs2_inst.USE_2X_FF = "false"; + defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false"; + defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false"; + defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true"; + defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false"; + defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false"; + defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true"; + defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false"; + defparam altdq_dqs2_inst.HHP_HPS = "false"; + + + +endmodule diff --git a/ip/altera/ddr3/ddr3_p0_clock_pair_generator.v b/ip/altera/ddr3/ddr3_p0_clock_pair_generator.v new file mode 100644 index 0000000..8731499 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_clock_pair_generator.v @@ -0,0 +1,129 @@ +//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b +//VERSION_BEGIN 15.1 cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ VERSION_END +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, the Altera Quartus Prime License Agreement, +// the Altera MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Altera and sold by Altera or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + + + +//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module ddr3_p0_clock_pair_generator + ( + datain, + dataout, + dataout_b) /* synthesis synthesis_clearbox=1 */; + input [0:0] datain; + output [0:0] dataout; + output [0:0] dataout_b; + + wire [0:0] wire_obuf_ba_o; + wire [0:0] wire_obuf_ba_oe; + wire [0:0] wire_obufa_o; + wire [0:0] wire_obufa_oe; + wire [0:0] wire_pseudo_diffa_o; + wire [0:0] wire_pseudo_diffa_obar; + wire [0:0] wire_pseudo_diffa_oebout; + wire [0:0] wire_pseudo_diffa_oein; + wire [0:0] wire_pseudo_diffa_oeout; + wire [0:0] oe_w; + + cyclonev_io_obuf obuf_ba_0 + ( + .i(wire_pseudo_diffa_obar), + .o(wire_obuf_ba_o[0:0]), + .obar(), + .oe(wire_obuf_ba_oe[0:0]) + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .dynamicterminationcontrol(1'b0), + .parallelterminationcontrol({16{1'b0}}), + .seriesterminationcontrol({16{1'b0}}) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + // synopsys translate_off + , + .devoe(1'b1) + // synopsys translate_on + ); + defparam + obuf_ba_0.bus_hold = "false", + obuf_ba_0.open_drain_output = "false", + obuf_ba_0.lpm_type = "cyclonev_io_obuf"; + assign + wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])}; + cyclonev_io_obuf obufa_0 + ( + .i(wire_pseudo_diffa_o), + .o(wire_obufa_o[0:0]), + .obar(), + .oe(wire_obufa_oe[0:0]) + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .dynamicterminationcontrol(1'b0), + .parallelterminationcontrol({16{1'b0}}), + .seriesterminationcontrol({16{1'b0}}) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + // synopsys translate_off + , + .devoe(1'b1) + // synopsys translate_on + ); + defparam + obufa_0.bus_hold = "false", + obufa_0.open_drain_output = "false", + obufa_0.lpm_type = "cyclonev_io_obuf"; + assign + wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])}; + cyclonev_pseudo_diff_out pseudo_diffa_0 + ( + .dtc(), + .dtcbar(), + .i(datain), + .o(wire_pseudo_diffa_o[0:0]), + .obar(wire_pseudo_diffa_obar[0:0]), + .oebout(wire_pseudo_diffa_oebout[0:0]), + .oein(wire_pseudo_diffa_oein[0:0]), + .oeout(wire_pseudo_diffa_oeout[0:0]) + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .dtcin(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + assign + wire_pseudo_diffa_oein = {(~ oe_w[0])}; + assign + dataout = wire_obufa_o, + dataout_b = wire_obuf_ba_o, + oe_w = 1'b1; +endmodule //ddr3_p0_clock_pair_generator +//VALID FILE diff --git a/ip/altera/ddr3/ddr3_p0_generic_ddio.v b/ip/altera/ddr3/ddr3_p0_generic_ddio.v new file mode 100644 index 0000000..b88fa73 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_generic_ddio.v @@ -0,0 +1,89 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module ddr3_p0_generic_ddio( + datain, + halfratebypass, + dataout, + clk_hr, + clk_fr +); + + parameter WIDTH = 1; + localparam DATA_IN_WIDTH = 4 * WIDTH; + localparam DATA_OUT_WIDTH = WIDTH; + + input [DATA_IN_WIDTH-1:0] datain; + input halfratebypass; + input [WIDTH-1:0] clk_hr; + input [WIDTH-1:0] clk_fr; + output [DATA_OUT_WIDTH-1:0] dataout; + + + generate + genvar pin; + for (pin = 0; pin < WIDTH; pin = pin + 1) + begin:acblock + wire fr_data_hi; + wire fr_data_lo; + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_hi ( + .datainhi(datain[pin * 4]), + .datainlo(datain[pin * 4 + 2]), + .dataout(fr_data_hi), + .clkhi (clk_hr[pin]), + .clklo (clk_hr[pin]), + .hrbypass(halfratebypass), + .muxsel (clk_hr[pin]) + ); + + cyclonev_ddio_out + #( + .half_rate_mode("true"), + .use_new_clocking_model("true"), + .async_mode("none") + ) hr_to_fr_lo ( + .datainhi(datain[pin * 4 + 1]), + .datainlo(datain[pin * 4 + 3]), + .dataout(fr_data_lo), + .clkhi (clk_hr[pin]), + .clklo (clk_hr[pin]), + .hrbypass(halfratebypass), + .muxsel (clk_hr[pin]) + ); + + cyclonev_ddio_out + #( + .async_mode("none"), + .half_rate_mode("false"), + .sync_mode("none"), + .use_new_clocking_model("true") + ) ddio_out ( + .datainhi(fr_data_hi), + .datainlo(fr_data_lo), + .dataout(dataout[pin]), + .clkhi (clk_fr[pin]), + .clklo (clk_fr[pin]), + .muxsel (clk_fr[pin]) + ); + end + endgenerate +endmodule diff --git a/ip/altera/ddr3/ddr3_p0_iss_probe.v b/ip/altera/ddr3/ddr3_p0_iss_probe.v new file mode 100644 index 0000000..4100624 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_iss_probe.v @@ -0,0 +1,60 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module ddr3_p0_iss_probe ( + probe_input +); +parameter WIDTH = 1; +parameter ID_NAME = "PROB"; + +input [WIDTH-1:0] probe_input; + + +altsource_probe iss_probe_inst ( + .probe (probe_input), + .source () + // synopsys translate_off + , + .clr (), + .ena (), + .ir_in (), + .ir_out (), + .jtag_state_cdr (), + .jtag_state_cir (), + .jtag_state_e1dr (), + .jtag_state_sdr (), + .jtag_state_tlr (), + .jtag_state_udr (), + .jtag_state_uir (), + .raw_tck (), + .source_clk (), + .source_ena (), + .tdi (), + .tdo (), + .usr1 () + // synopsys translate_on + ); + defparam + iss_probe_inst.enable_metastability = "NO", + iss_probe_inst.instance_id = ID_NAME, + iss_probe_inst.probe_width = WIDTH, + iss_probe_inst.sld_auto_instance_index = "YES", + iss_probe_inst.sld_instance_index = 0, + iss_probe_inst.source_initial_value = "0", + iss_probe_inst.source_width = 0; + + +endmodule diff --git a/ip/altera/ddr3/ddr3_p0_parameters.tcl b/ip/altera/ddr3/ddr3_p0_parameters.tcl new file mode 100644 index 0000000..597b793 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_parameters.tcl @@ -0,0 +1,105 @@ +# +# AUTO-GENERATED FILE: Do not edit ! ! ! +# + +set ::GLOBAL_ddr3_p0_corename "ddr3_p0" +set ::GLOBAL_ddr3_p0_io_standard "SSTL-15" +set ::GLOBAL_ddr3_p0_io_interface_type "HPAD" +set ::GLOBAL_ddr3_p0_io_standard_differential "1.5-V SSTL" +set ::GLOBAL_ddr3_p0_io_standard_cmos "1.5V" +set ::GLOBAL_ddr3_p0_number_of_dqs_groups 2 +set ::GLOBAL_ddr3_p0_dqs_group_size 8 +set ::GLOBAL_ddr3_p0_number_of_ck_pins 1 +set ::GLOBAL_ddr3_p0_number_of_dm_pins 2 +set ::GLOBAL_ddr3_p0_dqs_delay_chain_length 0 +set ::GLOBAL_ddr3_p0_uniphy_temp_ver_code 1003457432 +# PLL Parameters + +#USER W A R N I N G ! +#USER The PLL parameters are statically defined in this +#USER file at generation time! +#USER To ensure timing constraints and timing reports are correct, when you make +#USER any changes to the PLL component using the MegaWizard Plug-In, +#USER apply those changes to the PLL parameters in this file + +set ::GLOBAL_ddr3_p0_num_pll_clock 7 +set ::GLOBAL_ddr3_p0_pll_mult(0) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(0) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(0) 0.0 +set ::GLOBAL_ddr3_p0_pll_mult(PLL_AFI_CLK) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(PLL_AFI_CLK) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(PLL_AFI_CLK) 0.0 +set ::GLOBAL_ddr3_p0_pll_mult(1) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(1) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(1) 0.0 +set ::GLOBAL_ddr3_p0_pll_mult(PLL_MEM_CLK) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(PLL_MEM_CLK) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(PLL_MEM_CLK) 0.0 +set ::GLOBAL_ddr3_p0_pll_mult(2) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(2) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(2) 270.0 +set ::GLOBAL_ddr3_p0_pll_mult(PLL_WRITE_CLK) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(PLL_WRITE_CLK) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(PLL_WRITE_CLK) 270.0 +set ::GLOBAL_ddr3_p0_pll_mult(3) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(3) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(3) 270.0 +set ::GLOBAL_ddr3_p0_pll_mult(PLL_ADDR_CMD_CLK) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(PLL_ADDR_CMD_CLK) 1000000 +set ::GLOBAL_ddr3_p0_pll_phase(PLL_ADDR_CMD_CLK) 270.0 +set ::GLOBAL_ddr3_p0_pll_mult(4) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(4) 2000000 +set ::GLOBAL_ddr3_p0_pll_phase(4) 0.0 +set ::GLOBAL_ddr3_p0_pll_mult(PLL_AFI_HALF_CLK) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(PLL_AFI_HALF_CLK) 2000000 +set ::GLOBAL_ddr3_p0_pll_phase(PLL_AFI_HALF_CLK) 0.0 +set ::GLOBAL_ddr3_p0_pll_mult(5) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(5) 5000000 +set ::GLOBAL_ddr3_p0_pll_phase(5) 9.0 +set ::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK) 5000000 +set ::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) 9.0 +set ::GLOBAL_ddr3_p0_pll_mult(6) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(6) 15000000 +set ::GLOBAL_ddr3_p0_pll_phase(6) 0.0 +set ::GLOBAL_ddr3_p0_pll_mult(PLL_CONFIG_CLK) 6000000 +set ::GLOBAL_ddr3_p0_pll_div(PLL_CONFIG_CLK) 15000000 +set ::GLOBAL_ddr3_p0_pll_phase(PLL_CONFIG_CLK) 0.0 + +set ::GLOBAL_ddr3_p0_leveling_capture_phase 90.0 + +############################################################## +## IP options +############################################################## + +set IP(write_dcc) "static" +set IP(write_deskew_range) 31 +set IP(read_deskew_range) 31 +set IP(write_deskew_range_setup) 4 +set IP(write_deskew_range_hold) 31 +set IP(read_deskew_range_setup) 31 +set IP(read_deskew_range_hold) 31 +set IP(mem_if_memtype) "ddr3" +set IP(RDIMM) 0 +set IP(LRDIMM) 0 +set IP(mp_calibration) 1 +set IP(quantization_T9) 0.025 +set IP(quantization_T1) 0.025 +set IP(quantization_DCC) 0.025 +set IP(quantization_T7) 0.025 +set IP(quantization_WL) 0.0125 +set IP(quantization_T11) 0.025 +set IP(eol_reduction_factor_addr) 2.0 +set IP(eol_reduction_factor_read) 2.1 +set IP(eol_reduction_factor_write) 2.35 +# Can be either dynamic or static +set IP(write_deskew_mode) "dynamic" +set IP(read_deskew_mode) "dynamic" +set IP(discrete_device) 0 +set IP(num_ranks) 1 +set IP(num_shadow_registers) 1 +set IP(tracking_enabled) 0 + +set IP(num_report_paths) 10 +set IP(epr) 0.058 +set IP(epw) 0.076 diff --git a/ip/altera/ddr3/ddr3_p0_phy_csr.sv b/ip/altera/ddr3/ddr3_p0_phy_csr.sv new file mode 100644 index 0000000..50a23dd --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_phy_csr.sv @@ -0,0 +1,231 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// ******************************************************************************************************************************** +// File name: phy_csr.v +// This file instantiates the PHY configuration and status register port +// ******************************************************************************************************************************** + + +// PHY CSR ports. The CSR port operates where all reads respond in +// the next clock cycle and only ever take 1 clock cycle. The writes are cached +// and are processed in the following clock cycle to when they are initially +// captured. + +// altera message_off 10036 + +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on + +module ddr3_p0_phy_csr( + clk, + reset_n, + + csr_addr, + csr_be, + csr_write_req, + csr_wdata, + csr_read_req, + csr_rdata, + csr_rdata_valid, + csr_waitrequest, + + pll_locked, + afi_cal_success, + afi_cal_fail, + seq_fom_in, + seq_fom_out, + cal_init_failing_stage, + cal_init_failing_substage, + cal_init_failing_group + +); + +localparam RESET_REQUEST_DELAY = 4; + +localparam CSR_IP_VERSION_NUMBER = 151; + +parameter CSR_ADDR_WIDTH = 8; +parameter CSR_DATA_WIDTH = 32; +parameter CSR_BE_WIDTH = 4; + +parameter MEM_READ_DQS_WIDTH = 64; + +parameter MR1_RTT = 0; +parameter MR1_ODS = 0; +parameter MR2_RTT_WR = 0; + +input clk; + +input reset_n; + +input [CSR_ADDR_WIDTH - 1 : 0] csr_addr; +input [CSR_BE_WIDTH - 1 : 0] csr_be; +input csr_write_req; +input [CSR_DATA_WIDTH - 1 : 0] csr_wdata; +input csr_read_req; +output [CSR_DATA_WIDTH - 1 : 0] csr_rdata; +output csr_rdata_valid; +output csr_waitrequest; + +input pll_locked; +input afi_cal_success; +input afi_cal_fail; +input [7:0] seq_fom_in; +input [7:0] seq_fom_out; +input [7:0] cal_init_failing_stage; +input [7:0] cal_init_failing_substage; +input [7:0] cal_init_failing_group; + + + +reg int_write_req; +reg int_read_req; +reg [CSR_ADDR_WIDTH-1:0] int_addr; +reg [CSR_BE_WIDTH - 1 : 0] int_be; +reg [CSR_DATA_WIDTH - 1 : 0] int_rdata; +reg int_rdata_valid; +reg int_waitrequest; +reg [CSR_DATA_WIDTH - 1 : 0] int_wdata; + +reg [31:0] csr_register_0001; +reg [31:0] csr_register_0002; +reg [31:0] csr_register_0004; +reg [31:0] csr_register_0005; +reg [31:0] csr_register_0006; +reg [31:0] csr_register_0007; +reg [31:0] csr_register_0008; + + + +always @ (posedge clk) begin + csr_register_0001 <= 0; + csr_register_0001 <= 32'hdeadbeef; + + csr_register_0002 <= 0; + csr_register_0002 <= {CSR_IP_VERSION_NUMBER[15:0],16'h4}; + + csr_register_0004 <= 0; + csr_register_0004[24] <= afi_cal_success; + csr_register_0004[25] <= afi_cal_fail; + csr_register_0004[26] <= pll_locked; + + csr_register_0005 <= 0; + csr_register_0005[7:0] <= seq_fom_in; + csr_register_0005[23:16] <= seq_fom_out; + + csr_register_0006 <= 0; + csr_register_0006[7:0] <= cal_init_failing_stage; + csr_register_0006[15:8] <= cal_init_failing_substage; + csr_register_0006[23:16] <= cal_init_failing_group; + + csr_register_0007 <= 0; + + csr_register_0008 <= 0; + csr_register_0008[2:0] <= MR1_RTT[2:0] & 3'b111; + csr_register_0008[6:5] <= MR1_ODS[1:0] & 2'b11; + csr_register_0008[10:9] <= MR2_RTT_WR[1:0] & 2'b11; + +end + +always @ (posedge clk or negedge reset_n) begin + if (!reset_n) begin + int_write_req <= 0; + int_read_req <= 0; + int_addr <= 0; + int_wdata <= 0; + int_be <= 0; + end + else begin + + int_addr <= csr_addr; + int_wdata <= csr_wdata; + + int_be <= csr_be; + + if (csr_write_req) + int_write_req <= 1'b1; + else + int_write_req <= 1'b0; + + if (csr_read_req) + int_read_req <= 1'b1; + else + int_read_req <= 1'b0; + end +end + +always @ (posedge clk or negedge reset_n) begin + if (!reset_n) begin + int_rdata <= 0; + int_rdata_valid <= 0; + int_waitrequest <= 1; + end + else begin + int_waitrequest <= 1'b0; + + if (int_read_req) + case (int_addr) + 'h1 : + int_rdata <= csr_register_0001; + 'h2 : + int_rdata <= csr_register_0002; + 'h4 : + int_rdata <= csr_register_0004; + 'h5 : + int_rdata <= csr_register_0005; + 'h6 : + int_rdata <= csr_register_0006; + 'h7 : + int_rdata <= csr_register_0007; + 'h8 : + int_rdata <= csr_register_0008; + default : + int_rdata <= 0; + endcase + + if (int_read_req) + int_rdata_valid <= 1'b1; + else + int_rdata_valid <= 1'b0; + end +end + + +always @ (posedge clk or negedge reset_n) begin + if (!reset_n) begin + + + + + end + else begin + + if (int_write_req) begin + end + end +end + +`ifndef SYNTH_FOR_SIM +ddr3_p0_iss_probe pll_probe ( + .probe_input(pll_locked) +); +`endif + +assign csr_waitrequest = int_waitrequest; +assign csr_rdata = int_rdata; +assign csr_rdata_valid = int_rdata_valid; + + +endmodule diff --git a/ip/altera/ddr3/ddr3_p0_pin_assignments.tcl b/ip/altera/ddr3/ddr3_p0_pin_assignments.tcl new file mode 100644 index 0000000..4c4f0a3 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_pin_assignments.tcl @@ -0,0 +1,424 @@ +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains a simple script to automatically apply +# IO standards and other IO assignments for the UniPHY memory +# interface pins that connect to the memory device. The pins +# are automatically detected using the routines defined in +# the ddr3_p0_pin_map.tcl script. +# All the memory interface parameters are defined in the +# ddr3_p0_parameters.tcl script + + +set available_options { + { c.arg "#_ignore_#" "Option to specify the revision name" } +} +package require cmdline + +set script_dir [file dirname [info script]] + +global ::GLOBAL_ddr3_p0_corename +global ::GLOBAL_ddr3_p0_io_standard +global ::GLOBAL_ddr3_p0_io_standard_differential +global ::GLOBAL_ddr3_p0_dqs_group_size +global ::GLOBAL_ddr3_p0_number_of_dqs_groups +global ::GLOBAL_ddr3_p0_uniphy_temp_ver_code + +################# +# # +# SETUP SECTION # +# # +################# + +global options +set argument_list $quartus(args) +set argv0 "quartus_sta -t [info script]" +set usage "\[\] :" + +if [catch {array set options [cmdline::getoptions argument_list $::available_options]} result] { + if {[llength $argument_list] > 0 } { + post_message -type error "Illegal Options" + post_message -type error [::cmdline::usage $::available_options $usage] + qexit -error + } else { + post_message -type info "Usage:" + post_message -type info [::cmdline::usage $::available_options $usage] + qexit -success + } +} +if {$options(c) != "#_ignore_#"} { + if [string compare [file extension $options(c)] ""] { + set options(c) [file rootname $options(c)] + } +} + +if {[llength $argument_list] == 1 } { + set options(project_name) [lindex $argument_list 0] + + if [string compare [file extension $options(project_name)] ""] { + set project_name [file rootname $options(project_name)] + } + + set project_name [file normalize $options(project_name)] + +} elseif { [llength $argument_list] == 2 } { + set options(project_name) [lindex $argument_list 0] + set options(rev) [lindex $argument_list 1] + + if [string compare [file extension $options(project_name)] ""] { + set project_name [file rootname $options(project_name)] + } + if [string compare [file extension $options(c)] ""] { + set revision_name [file rootname $options(c)] + } + + set project_name [file normalize $options(project_name)] + set revision_name [file normalize $options(rev)] + +} elseif { [ is_project_open ] } { + set project_name $::quartus(project) + set options(rev) $::quartus(settings) + +} else { + post_message -type error "Project name is missing" + post_message -type info [::cmdline::usage $::available_options $usage] + post_message -type info "For more details, use \"quartus_sta --help\"" + qexit -error +} + + + # If this script is called from outside quartus_sta/map, it will re-launch itself in quartus_sta +if { ![info exists quartus(nameofexecutable)] || ($quartus(nameofexecutable) != "quartus_sta" && $quartus(nameofexecutable) != "quartus_map") } { + post_message -type info "Restarting in quartus_sta..." + + set cmd quartus_sta + if { [info exists quartus(binpath)] } { + set cmd [file join $quartus(binpath) $cmd] + } + + if { [ is_project_open ] } { + set project_name [ get_current_revision ] + } elseif { ! [ string compare $project_name "" ] } { + post_message -type error "Missing project_name argument" + + return 1 + } + + set output [ exec $cmd -t [ info script ] $project_name ] + + foreach line [split $output \n] { + set type info + set matched_line [ regexp {^\W*(Info|Extra Info|Warning|Critical Warning|Error): (.*)$} $line x type msg ] + regsub " " $type _ type + + if { $matched_line } { + post_message -type $type $msg + } else { + puts "$line" + } + } + + return 0 +} + +if { ! [ is_project_open ] } { + if { ! [ string compare $project_name "" ] } { + post_message -type error "Missing project_name argument" + + return 1 + } + + if {$options(c) == "#_ignore_#"} { + project_open $project_name + } else { + project_open $project_name -revision $options(c) + } + +} + +source "$script_dir/ddr3_p0_parameters.tcl" +source "$script_dir/ddr3_p0_pin_map.tcl" + +set family_name [string tolower [regsub -all " +" [get_global_assignment -name FAMILY] ""]] + +####################################### +# Check if user is using a SOC Device # +####################################### +set device_name [string tolower [regsub -all " +" [get_global_assignment -name DEVICE] ""]] +set is_av_soc_device 0 +set is_speedgrade_i5 0 +set is_speedgrade_c5 0 +set soc_device_regexp "5as" +set i5_regexp "i5" +set c5_regexp "c5" + +if {[regexp $soc_device_regexp $device_name]} { + set is_av_soc_device 1 +} + +if {[regexp $i5_regexp $device_name]} { + set is_speedgrade_i5 1 +} elseif {[regexp $c5_regexp $device_name]} { + set is_speedgrade_c5 1 +} + +############################## +# Clean up stale assignments # +############################## +post_message -type info "Cleaning up stale assignments..." + +set asgn_types [ list IO_STANDARD INPUT_TERMINATION OUTPUT_TERMINATION CURRENT_STRENGTH_NEW DQ_GROUP TERMINATION_CONTROL_BLOCK ] +foreach asgn_type $asgn_types { + remove_all_instance_assignments -tag __$::GLOBAL_ddr3_p0_corename -name $asgn_type +} + +if { ! [ timing_netlist_exist ] } { + create_timing_netlist -post_map +} + +####################### +# # +# ASSIGNMENTS SECTION # +# # +####################### + +# This is the main call to the netlist traversal routines +# that will automatically find all pins and registers required +# to apply pin settings. +ddr3_p0_initialize_ddr_db ddr_db + +# If multiple instances of this core are present in the +# design they will all be constrained through the +# following loop + +set instances [ array names ddr_db ] +foreach inst $instances { + if { [ info exists pins ] } { + # Clean-up stale content + unset pins + } + array set pins $ddr_db($inst) + + if {$is_av_soc_device} { + set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING ON + } + + ddr3_p0_get_rzq_pins $inst all_rzq_pins + # Set rzq pin I/O standard + foreach rzq_pin $all_rzq_pins { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $rzq_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + # 1.35V DDR3L pin assignments + if { ! [ string compare $::GLOBAL_ddr3_p0_io_standard "SSTL-135" ] } { + foreach dq_pin $pins(all_dq_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] { + set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name D5_DELAY 4 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name D6_DELAY 0 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] { + set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + + if {$is_av_soc_device} { + if {$is_speedgrade_i5} { + set_instance_assignment -name D5_DELAY 5 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } elseif {$is_speedgrade_c5} { + set_instance_assignment -name D5_DELAY 10 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } else { + set_instance_assignment -name D5_DELAY 8 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } + } else { + set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } + } + + foreach ac_pin $pins(ac_wo_reset_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + foreach reset_pin $pins(reset_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + foreach dm_pin $pins(dm_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename + } + } else { + # 1.5V DDR3 pin assignments + + foreach dq_pin $pins(all_dq_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard CLASS I" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] { + set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential CLASS I" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name D5_DELAY 4 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name D6_DELAY 0 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] { + set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential CLASS I" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + + if {$is_av_soc_device} { + if {$is_speedgrade_i5} { + set_instance_assignment -name D5_DELAY 5 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } elseif {$is_speedgrade_c5} { + set_instance_assignment -name D5_DELAY 10 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } else { + set_instance_assignment -name D5_DELAY 8 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } + } else { + set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } + } + + foreach ac_pin $pins(ac_wo_reset_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard CLASS I" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + foreach reset_pin $pins(reset_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard_cmos" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + + foreach dm_pin $pins(dm_pins) { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard CLASS I" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename + } + } + + foreach refclk_pin $pins(pll_ref_clock) { + if {![string compare [get_instance_assignment -to $refclk_pin -name IO_STANDARD] ""]} { + set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $refclk_pin -tag __$::GLOBAL_ddr3_p0_corename + } + } + + set ::GLOBAL_ddr3_p0_dqs_group_size_constraint $::GLOBAL_ddr3_p0_dqs_group_size + if { $::GLOBAL_ddr3_p0_dqs_group_size == 8 } { + set ::GLOBAL_ddr3_p0_dqs_group_size_constraint 9 + } + + set delay_chain_config FLEXIBLE_TIMING + + # Disable package skew compensation for data pins in timing analysis + foreach dq_pin $pins(all_dq_pins) { + set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename + } + foreach dm_pin $pins(dm_pins) { + set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename + } + foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] { + set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + # Disable package skew compensation for address/command pins in timing analysis + foreach ac_pin $pins(ac_pins) { + set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename + } + foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] { + set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename + } + + set seq_clks 2 + + set qr_related_clks 0 + + set dr_clk 0 + + # Create the global and regional clocks + + # PLL clocks + + + + # Avalon Clock + set pll_avl_clock [ ddr3_p0_get_pll_clock_name_for_acf $pins(pll_avl_clock) "pll_avl_clk" ] + + # Scan Chain Configuration CLock + set pll_config_clock [ ddr3_p0_get_pll_clock_name_for_acf $pins(pll_config_clock) "pll_config_clk" ] + + + if { $::GLOBAL_ddr3_p0_num_pll_clock == [ expr 5 + $seq_clks + $dr_clk + $qr_related_clks ] } { + set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to $pll_avl_clock -tag __$::GLOBAL_ddr3_p0_corename + + set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to $pll_config_clock -tag __$::GLOBAL_ddr3_p0_corename + } else { + post_message -type critical_warning "Expected [ expr 5 + $seq_clks + $dr_clk + $qr_related_clks ] PLL clocks but found $::GLOBAL_ddr3_p0_num_pll_clock!" + } + + set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|ureset|phy_reset_n" -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __$::GLOBAL_ddr3_p0_corename + + for {set i 0} {$i < $::GLOBAL_ddr3_p0_number_of_dqs_groups} {incr i 1} { + set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uio_pads|dq_ddio[$i].read_capture_clk_buffer" -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uread_datapath|reset_n_fifo_write_side[$i]" -tag __$::GLOBAL_ddr3_p0_corename + set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[$i]" -tag __$::GLOBAL_ddr3_p0_corename + } + + set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to $inst -tag __$::GLOBAL_ddr3_p0_corename + + # Use direct compensation mode to minimize jitter + set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "${inst}|pll0|fbout" -tag __$::GLOBAL_ddr3_p0_corename +} + +ddr3_p0_dump_all_pins ddr_db + +if { [ llength $quartus(args) ] > 1 } { + set param [lindex $quartus(args) 1] + + if { [ string match -dump_static_pin_map $param ] } { + set filename "${::GLOBAL_ddr3_p0_corename}_static_pin_map.tcl" + + ddr3_p0_dump_static_pin_map ddr_db $filename + } +} + +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON + +set_global_assignment -name ECO_REGENERATE_REPORT ON diff --git a/ip/altera/ddr3/ddr3_p0_pin_map.tcl b/ip/altera/ddr3/ddr3_p0_pin_map.tcl new file mode 100644 index 0000000..75b4256 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_pin_map.tcl @@ -0,0 +1,2683 @@ +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains the traversal routines that are used by both +# ddr3_p0_pin_assignments.tcl and ddr3_p0.sdc scripts. +# +# These routines are only meant to support these two scripts. +# Trying to using them in a different context can have unexpected +# results. + +set script_dir [file dirname [info script]] + +source [file join $script_dir ddr3_p0_parameters.tcl] +load_package sdc_ext + +proc ddr3_p0_find_all_pins { mystring } { + set allpins [get_pins -compatibility_mode $mystring ] + + foreach_in_collection pin $allpins { + set pinname [ get_pin_info -name $pin ] + + puts "$pinname" + } +} + + +proc ddr3_p0_index_in_collection { col j } { + set i 0 + foreach_in_collection path $col { + if {$i == $j} { + return $path + } + set i [expr $i + 1] + } + return "" +} + + +proc ddr3_p0_get_clock_to_pin_name_mapping {} { + set result [list] + set clocks_collection [get_clocks] + foreach_in_collection clock $clocks_collection { + set clock_name [get_clock_info -name $clock] + set clock_target [get_clock_info -targets $clock] + set first_index [ddr3_p0_index_in_collection $clock_target 0] + set catch_exception [catch {get_pin_info -name $first_index} pin_name] + if {$catch_exception == 0} { + lappend result [list $clock_name $pin_name] + } + } + return $result +} + + +proc ddr3_p0_get_clock_name_from_pin_name { pin_name } { + set table [ddr3_p0_get_clock_to_pin_name_mapping] + foreach entry $table { + if {[string compare [lindex [lindex [split $entry] 1] 0] $pin_name] == 0} { + return [lindex $entry 0] + } + } + return "" +} + + +proc ddr3_p0_get_clock_name_from_pin_name_vseries {pin_name suffix} { + set name [ddr3_p0_get_clock_name_from_pin_name $pin_name] + if {[string compare -nocase $name ""] == 0} { + set pll_clock $pin_name + regsub {~PLL_OUTPUT_COUNTER\|divclk$} $pll_clock "" pll_clock + regsub {_phy$} $pll_clock "" pll_clock + regsub {[0-9]+$} $pll_clock "" pll_clock + set pll_clock "${pll_clock}_${suffix}" + } else { + set pll_clock $name + } + return $pll_clock +} + + +proc ddr3_p0_get_clock_name_from_pin_name_pre_vseries {pin_name suffix} { + set name [ddr3_p0_get_clock_name_from_pin_name $pin_name] + if {[string compare -nocase $name ""] == 0} { + set pll_clock $pin_name + regsub {upll_memphy\|auto_generated\|pll1\|clk\[[0-9]+\]$} $pll_clock "pll" pll_clock + set pll_clock "${pll_clock}_${suffix}" + } else { + set pll_clock $name + } + return $pll_clock +} + +proc ddr3_p0_get_or_add_clock_vseries_from_virtual_refclk {args} { + array set opts { / + -suffix "" / + -target "" / + -period "" / + -phase 0 } + + array set opts $args + + set clock_name [ddr3_p0_get_clock_name_from_pin_name $opts(-target)] + + + if {[string compare -nocase $clock_name ""] == 0} { + set clock_name $opts(-target) + set suffix $opts(-suffix) + + regsub {~PLL_OUTPUT_COUNTER\|divclk$} $clock_name "" clock_name + regsub {_phy$} $clock_name "" clock_name + regsub {[0-9]+$} $clock_name "" clock_name + set clock_name "${clock_name}_${suffix}" + set re [expr $opts(-period) * $opts(-phase)/360] + set fe [expr $opts(-period) * $opts(-phase)/360 + $opts(-period)/2] + + create_clock \ + -name $clock_name \ + -period $opts(-period) \ + -waveform [ list $re $fe ] \ + $opts(-target) + } + + return $clock_name +} + +proc ddr3_p0_get_or_add_clock_vseries {args} { + array set opts { / + -suffix "" / + -target "" / + -source "" / + -multiply_by 1 / + -divide_by 1 / + -phase 0 } + + array set opts $args + set target $opts(-target) + + set clock_name [ddr3_p0_get_clock_name_from_pin_name $opts(-target)] + + if {[string compare -nocase $clock_name ""] == 0} { + set clock_name $opts(-target) + set suffix $opts(-suffix) + + regsub {~PLL_OUTPUT_COUNTER\|divclk$} $clock_name "" clock_name + regsub {_phy$} $clock_name "" clock_name + regsub {[0-9]+$} $clock_name "" clock_name + regsub -all {\\} $clock_name "" clock_name + set clock_name "${clock_name}_${suffix}" + set source_name "\{$opts(-source)\}" + + create_generated_clock \ + -name ${clock_name} \ + -source ${source_name} \ + -multiply_by $opts(-multiply_by) \ + -divide_by $opts(-divide_by) \ + -phase $opts(-phase) \ + $target + } + + return $clock_name +} + +proc ddr3_p0_get_or_add_clock_pre_vseries {args} { + array set opts { / + -suffix "" / + -target "" / + -source "" / + -multiply_by 1 / + -divide_by 1 / + -phase 0 } + + array set opts $args + + set clock_name [ddr3_p0_get_clock_name_from_pin_name $opts(-target)] + + if {[string compare -nocase $clock_name ""] == 0} { + set clock_name $opts(-target) + set suffix $opts(-suffix) + + regsub {upll_memphy\|auto_generated\|pll1\|clk\[[0-9]+\]$} $clock_name "pll" clock_name + set clock_name "${clock_name}_${suffix}" + + create_generated_clock \ + -name $clock_name \ + -source $opts(-source) \ + -multiply_by $opts(-multiply_by) \ + -divide_by $opts(-divide_by) \ + -phase $opts(-phase) \ + $opts(-target) + } + + return $clock_name +} + + +proc ddr3_p0_get_source_clock_pin_name {node_name} { + + set nodename "" + set nodes [get_nodes $node_name] + ddr3_p0_traverse_fanin_up_to_depth [ddr3_p0_index_in_collection $nodes 0] ddr3_p0_is_node_type_pll_clk clock results_array 10 + if {[array size results_array] == 1} { + set pin_id [lindex [array names results_array] 0] + if {[string compare -nocase $pin_id ""] != 0} { + set nodename [get_node_info -name $pin_id] + } + } + return $nodename +} + + +proc ddr3_p0_find_all_keepers { mystring } { + set allkeepers [get_keepers $mystring ] + + foreach_in_collection keeper $allkeepers { + set keepername [ get_node_info -name $keeper ] + + puts "$keepername" + } +} + +proc ddr3_p0_round_3dp { x } { + return [expr { round($x * 1000) / 1000.0 } ] +} + +proc ddr3_p0_get_timequest_name {hier_name} { + set sta_name "" + for {set inst_start [string first ":" $hier_name]} {$inst_start != -1} {} { + incr inst_start + set inst_end [string first "|" $hier_name $inst_start] + if {$inst_end == -1} { + append sta_name [string range $hier_name $inst_start end] + set inst_start -1 + } else { + append sta_name [string range $hier_name $inst_start $inst_end] + set inst_start [string first ":" $hier_name $inst_end] + } + } + return $sta_name +} + +proc ddr3_p0_are_entity_names_on { } { + set entity_names_on 1 + + + return [set_project_mode -is_show_entity] +} + +proc ddr3_p0_get_core_instance_list {corename} { + set full_instance_list [ddr3_p0_get_core_full_instance_list $corename] + set instance_list [list] + + foreach inst $full_instance_list { + set sta_name [ddr3_p0_get_timequest_name $inst] + if {[lsearch $instance_list [escape_brackets $sta_name]] == -1} { + lappend instance_list $sta_name + } + } + return $instance_list +} + +proc ddr3_p0_get_core_full_instance_list {corename} { + set allkeepers [get_keepers * ] + + set_project_mode -always_show_entity_name on + + set instance_list [list] + + set inst_regexp {(^.*} + append inst_regexp {:[A-Za-z0-9\.\\_\[\]\-\$():]+)\|} + append inst_regexp ${corename} + append inst_regexp {:[A-Za-z0-9\.\\_\[\]\-\$():]+\|} + append inst_regexp "${corename}_acv_hard_memphy" + append inst_regexp {:umemphy} + + foreach_in_collection keeper $allkeepers { + set name [ get_node_info -name $keeper ] + + if {[regexp -- $inst_regexp $name -> hier_name] == 1} { + if {[lsearch $instance_list [escape_brackets $hier_name]] == -1} { + lappend instance_list $hier_name + } + } + } + + set_project_mode -always_show_entity_name qsf + + if {[ llength $instance_list ] == 0} { + post_message -type error "The auto-constraining script was not able to detect any instance for core < $corename >" + post_message -type error "Verify the following:" + post_message -type error " The core < $corename > is instantiated within another component (wrapper)" + post_message -type error " The core is not the top-level of the project" + post_message -type error " The memory interface pins are exported to the top-level of the project" + post_message -type error "Alternatively, if you are no longer instantiating core < $corename >," + post_message -type error " clean up any stale SDC_FILE references from the QSF/QIP files." + } + + return $instance_list +} + + +proc ddr3_p0_traverse_fanin_up_to_depth { node_id match_command edge_type results_array_name depth} { + upvar 1 $results_array_name results + + if {$depth < 0} { + error "Internal error: Bad timing netlist search depth" + } + set fanin_edges [get_node_info -${edge_type}_edges $node_id] + set number_of_fanin_edges [llength $fanin_edges] + for {set i 0} {$i != $number_of_fanin_edges} {incr i} { + set fanin_edge [lindex $fanin_edges $i] + set fanin_id [get_edge_info -src $fanin_edge] + if {$match_command == "" || [eval $match_command $fanin_id] != 0} { + set results($fanin_id) 1 + } elseif {$depth == 0} { + } else { + ddr3_p0_traverse_fanin_up_to_depth $fanin_id $match_command $edge_type results [expr {$depth - 1}] + } + } +} +proc ddr3_p0_is_node_type_pll_inclk { node_id } { + set cell_id [get_node_info -cell $node_id] + + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "FRACTIONAL_PLL"} { + set node_name [get_node_info -name $node_id] + set fanin_edges [get_node_info -clock_edges $node_id] + if {([string match "*|refclkin" $node_name] || [string match "*|refclkin\\\[0\\\]" $node_name]) && [llength $fanin_edges] > 0} { + set result 1 + } else { + set result 0 + } + } elseif {$atom_type == "HPS_SDRAM_PLL"} { + set node_name [get_node_info -name $node_id] + set fanin_edges [get_node_info -clock_edges $node_id] + if {[string match "*|ref_clk" $node_name] && [llength $fanin_edges] > 0} { + set result 1 + } else { + set result 0 + } + } elseif {$atom_type == "PLL"} { + set node_name [get_node_info -name $node_id] + set fanin_edges [get_node_info -clock_edges $node_id] + if {([string match "*|refclk" $node_name] || [string match "*|refclk\\\[0\\\]" $node_name]) && [llength $fanin_edges] > 0} { + set result 1 + } else { + set result 0 + } + } else { + set result 0 + } + } + return $result +} + +proc ddr3_p0_is_node_type_pin { node_id } { + set node_type [get_node_info -type $node_id] + if {$node_type == "port"} { + set result 1 + } else { + set result 0 + } + return $result +} + +proc ddr3_p0_get_input_clk_id { pll_output_node_id } { + if {[ddr3_p0_is_node_type_pll_clk $pll_output_node_id]} { + array set results_array [list] + ddr3_p0_traverse_fanin_up_to_depth $pll_output_node_id ddr3_p0_is_node_type_pll_inclk clock results_array 2 + if {[array size results_array] == 1} { + # Found PLL inclk, now find the input pin + set pll_inclk_id [lindex [array names results_array] 0] + array unset results_array + # If fed by a pin, it should be fed by a dedicated input pin, + # and not a global clock network. Limit the search depth to + # prevent finding pins fed by global clock (only allow io_ibuf pins) + ddr3_p0_traverse_fanin_up_to_depth $pll_inclk_id ddr3_p0_is_node_type_pin clock results_array 5 + if {[array size results_array] == 1} { + # Fed by a dedicated input pin + set pin_id [lindex [array names results_array] 0] + set result $pin_id + } else { + ddr3_p0_traverse_fanin_up_to_depth $pll_inclk_id ddr3_p0_is_node_type_pll_clk clock pll_clk_results_array 1 + ddr3_p0_traverse_fanin_up_to_depth $pll_inclk_id ddr3_p0_is_node_type_pll_clk clock pll_clk_results_array2 2 + if {[array size pll_clk_results_array] == 1} { + # Fed by a neighboring PLL via cascade path. + # Should be okay as long as that PLL has its input clock + # fed by a dedicated input. If there isn't, TimeQuest will give its own warning about undefined clocks. + set source_pll_clk_id [lindex [array names pll_clk_results_array] 0] + set source_pll_clk [get_node_info -name $source_pll_clk_id] + set result [ddr3_p0_get_input_clk_id $source_pll_clk_id] + if {$result != -1} { + post_message -type info "Please ensure source clock is defined for PLL with output $source_pll_clk" + } else { + # Fed from core + post_message -type critical_warning "PLL clock $source_pll_clk not driven by a dedicated clock pin. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin. Timing analyses may not be valid." + } + + } elseif {[array size pll_clk_results_array2] == 1} { + # Fed by a neighboring PLL via global clocks + # This is not ok + set source_pll_clk_id [lindex [array names pll_clk_results_array2] 0] + set source_pll_clk [get_node_info -name $source_pll_clk_id] + post_message -type critical_warning "PLL clock [get_node_info -name $pll_output_node_id] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL, and not go through a global clock network. Timing analyses may not be valid." + set result [ddr3_p0_get_input_clk_id $source_pll_clk_id] + + } else { + # If you got here it's because there's a buffer between the PLL input and the PIN. Issue a warning + # but keep searching for the pin anyways, otherwise all the timing constraining scripts will + # crash + post_message -type critical_warning "PLL clock [get_node_info -name $pll_output_node_id] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid." + ddr3_p0_traverse_fanin_up_to_depth $pll_inclk_id ddr3_p0_is_node_type_pin clock results_array 20 + if {[array size results_array] == 1} { + set pin_id [lindex [array names results_array] 0] + set result $pin_id + } else { + post_message -type critical_warning "Could not find PLL clock for [get_node_info -name $pll_output_node_id]" + set result -1 + } + } + } + } else { + post_message -type critical_warning "Could not find PLL clock for [get_node_info -name $pll_output_node_id]" + set result -1 + } + } else { + error "Internal error: ddr3_p0_get_input_clk_id only works on PLL output clocks" + } + return $result +} + +proc ddr3_p0_is_node_type_pll_clk { node_id } { + set cell_id [get_node_info -cell $node_id] + + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "PLL_OUTPUT_COUNTER"} { + set node_name [get_node_info -name $node_id] + if {[string match "*|pll*~PLL_OUTPUT_COUNTER*|divclk" $node_name]} { + set result 1 + } else { + set result 0 + } + } elseif {$atom_type == "HPS_SDRAM_PLL"} { + set node_name [get_node_info -name $node_id] + if {[string match "*|*pll|*_clk" $node_name]} { + set result 1 + } else { + set result 0 + } + } elseif {$atom_type == "PLL"} { + set node_name [get_node_info -name $node_id] + if {[string match "*|pll*|divclk" $node_name]} { + set result 1 + } else { + set result 0 + } + } else { + set result 0 + } + } + return $result +} + +proc ddr3_p0_get_pll_clock { dest_id_list node_type clock_id_name search_depth} { + if {$clock_id_name != ""} { + upvar 1 $clock_id_name clock_id + } + set clock_id -1 + + array set clk_array [list] + foreach node_id $dest_id_list { + ddr3_p0_traverse_fanin_up_to_depth $node_id ddr3_p0_is_node_type_pll_clk clock clk_array $search_depth + } + if {[array size clk_array] == 1} { + set clock_id [lindex [array names clk_array] 0] + set clk [get_node_info -name $clock_id] + } elseif {[array size clk_array] > 1} { + puts "Found more than 1 clock driving the $node_type" + set clk "" + } else { + set clk "" + } + + return $clk +} + +proc ddr3_p0_get_pll_clock_name { clock_id } { + set clock_name [get_node_info -name $clock_id] + + return $clock_name +} + +proc ddr3_p0_get_pll_clock_name_for_acf { clock_id pll_output_wire_name } { + set clock_name [get_node_info -name $clock_id] + regexp {(.*)\|pll\d+\~PLL_OUTPUT_COUNTER} $clock_name matched clock_name + regexp {(.*)\|pll\d+_phy\~PLL_OUTPUT_COUNTER} $clock_name matched clock_name + set clock_name "$clock_name|$pll_output_wire_name" + return $clock_name +} + +proc ddr3_p0_get_output_clock_id { ddio_output_pin_list pin_type msg_list_name {max_search_depth 20} } { + upvar 1 $msg_list_name msg_list + set output_clock_id -1 + + set output_id_list [list] + set pin_collection [get_keepers -no_duplicates $ddio_output_pin_list] + if {[get_collection_size $pin_collection] == [llength $ddio_output_pin_list]} { + foreach_in_collection id $pin_collection { + lappend output_id_list $id + } + } elseif {[get_collection_size $pin_collection] == 0} { + lappend msg_list "warning" "Could not find any $pin_type pins" + } else { + lappend msg_list "warning" "Could not find all $pin_type pins" + } + ddr3_p0_get_pll_clock $output_id_list $pin_type output_clock_id $max_search_depth + return $output_clock_id +} + +proc ddr3_p0_get_output_clock_id2 { ddio_output_pin_list pin_type msg_list_name {max_search_depth 20} } { + upvar 1 $msg_list_name msg_list + set output_clock_id -1 + + set output_id_list [list] + set pin_collection [get_pins -no_duplicates $ddio_output_pin_list] + if {[get_collection_size $pin_collection] == [llength $ddio_output_pin_list]} { + foreach_in_collection id $pin_collection { + lappend output_id_list $id + } + } elseif {[get_collection_size $pin_collection] == 0} { + lappend msg_list "warning" "Could not find any $pin_type pins" + } else { + lappend msg_list "warning" "Could not find all $pin_type pins" + } + ddr3_p0_get_pll_clock $output_id_list $pin_type output_clock_id $max_search_depth + return $output_clock_id +} + +proc ddr3_p0_is_node_type_clkbuf { node_id } { + set cell_id [get_node_info -cell $node_id] + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "CLKBUF" || $atom_type == "PHY_CLKBUF"} { + set result 1 + } else { + set result 0 + } + } + return $result +} + +proc ddr3_p0_get_clkbuf_clock { dest_id_list node_type clock_id_name search_depth} { + if {$clock_id_name != ""} { + upvar 1 $clock_id_name clock_id + } + set clock_id -1 + + array set clk_array [list] + foreach node_id $dest_id_list { + ddr3_p0_traverse_fanin_up_to_depth $node_id ddr3_p0_is_node_type_clkbuf clock clk_array $search_depth + } + if {[array size clk_array] == 1} { + set clock_id [lindex [array names clk_array] 0] + set clk [get_node_info -name $clock_id] + } elseif {[array size clk_array] > 1} { + set clk "" + } else { + set clk "" + } + + return $clk +} + +proc ddr3_p0_get_output_clock_clkbuf_id { ddio_output_pin_list pin_type msg_list_name {max_search_depth 20} } { + upvar 1 $msg_list_name msg_list + set output_clock_id -1 + + set output_id_list [list] + set pin_collection [get_keepers -no_duplicates $ddio_output_pin_list] + if {[get_collection_size $pin_collection] == [llength $ddio_output_pin_list]} { + foreach_in_collection id $pin_collection { + lappend output_id_list $id + } + } elseif {[get_collection_size $pin_collection] == 0} { + lappend msg_list "warning" "Could not find any $pin_type pins" + } else { + lappend msg_list "warning" "Could not find all $pin_type pins" + } + ddr3_p0_get_clkbuf_clock $output_id_list $pin_type output_clock_id $max_search_depth + return $output_clock_id +} + + +proc ddr3_p0_is_node_type_clk_phase_select { node_id } { + set cell_id [get_node_info -cell $node_id] + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "CLK_PHASE_SELECT"} { + set result 1 + } else { + set result 0 + } + } + return $result +} + +proc ddr3_p0_get_clk_phase_select_clock { dest_id_list node_type clock_id_name search_depth} { + if {$clock_id_name != ""} { + upvar 1 $clock_id_name clock_id + } + set clock_id -1 + + array set clk_array [list] + foreach node_id $dest_id_list { + ddr3_p0_traverse_fanin_up_to_depth $node_id ddr3_p0_is_node_type_clk_phase_select clock clk_array $search_depth + } + if {[array size clk_array] == 1} { + set clock_id [lindex [array names clk_array] 0] + set clk [get_node_info -name $clock_id] + } elseif {[array size clk_array] > 1} { + set clk "" + } else { + set clk "" + } + + return $clk +} + +proc ddr3_p0_get_output_clock_clk_phase_select_id { ddio_output_pin_list pin_type msg_list_name {max_search_depth 20} } { + upvar 1 $msg_list_name msg_list + set output_clock_id -1 + + set output_id_list [list] + set pin_collection [get_keepers -no_duplicates $ddio_output_pin_list] + if {[get_collection_size $pin_collection] == [llength $ddio_output_pin_list]} { + foreach_in_collection id $pin_collection { + lappend output_id_list $id + } + } elseif {[get_collection_size $pin_collection] == 0} { + lappend msg_list "warning" "Could not find any $pin_type pins" + } else { + lappend msg_list "warning" "Could not find all $pin_type pins" + } + ddr3_p0_get_clk_phase_select_clock $output_id_list $pin_type output_clock_id $max_search_depth + return $output_clock_id +} + +proc post_sdc_message {msg_type msg} { + if { $::TimeQuestInfo(nameofexecutable) != "quartus_fit"} { + post_message -type $msg_type $msg + } +} + +proc ddr3_p0_get_names_in_collection { col } { + set res [list] + foreach_in_collection node $col { + lappend res [ get_node_info -name $node ] + } + return $res +} + +proc ddr3_p0_static_map_expand_list { FH listname pinname } { + upvar $listname local_list + + puts $FH "" + puts $FH " # $pinname" + puts $FH " set pins($pinname) \[ list \]" + foreach pin $local_list($pinname) { + puts $FH " lappend pins($pinname) $pin" + } +} + +proc ddr3_p0_static_map_expand_list_of_list { FH listname pinname } { + upvar $listname local_list + + puts $FH "" + puts $FH " # $pinname" + puts $FH " set pins($pinname) \[ list \]" + set count_groups 0 + foreach sublist $local_list($pinname) { + puts $FH "" + puts $FH " # GROUP - ${count_groups}" + puts $FH " set group_${count_groups} \[ list \]" + foreach pin $sublist { + puts $FH " lappend group_${count_groups} $pin" + } + puts $FH "" + puts $FH " lappend pins($pinname) \$group_${count_groups}" + + incr count_groups + } +} + +proc ddr3_p0_static_map_expand_string { FH stringname pinname } { + upvar $stringname local_string + + puts $FH "" + puts $FH " # $pinname" + puts $FH " set pins($pinname) $local_string($pinname)" +} + +proc ddr3_p0_format_3dp { x } { + return [format %.3f $x] +} + +proc ddr3_p0_get_colours { x y } { + + set fcolour [list "black"] + if {$x < 0} { + lappend fcolour "red" + } else { + lappend fcolour "blue" + } + if {$y < 0} { + lappend fcolour "red" + } else { + lappend fcolour "blue" + } + + return $fcolour +} + +proc min { a b } { + if { $a == "" } { + return $b + } elseif { $a < $b } { + return $a + } else { + return $b + } +} + +proc max { a b } { + if { $a == "" } { + return $b + } elseif { $a > $b } { + return $a + } else { + return $b + } +} + +proc ddr3_p0_max_in_collection { col attribute } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + return $max +} + +proc ddr3_p0_min_in_collection { col attribute } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + return $min +} + +proc ddr3_p0_min_in_collection_to_name { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -to]] == $name} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ddr3_p0_min_in_collection_from_name { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -from]] == $name} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ddr3_p0_max_in_collection_to_name { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -to]] == $name} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + +proc ddr3_p0_max_in_collection_from_name { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -from]] == $name} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + + +proc ddr3_p0_min_in_collection_to_name2 { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -to]]]} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ddr3_p0_min_in_collection_from_name2 { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -from]]]} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ddr3_p0_max_in_collection_to_name2 { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -to]]]} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + +proc ddr3_p0_max_in_collection_from_name2 { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -from]]]} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + + +proc ddr3_p0_get_max_clock_path_delay_through_clock_node {from through to} { + set init 0 + set max_delay 0 + set paths [get_path -rise_from $through -rise_to $to] + foreach_in_collection path1 $paths { + set delay [get_path_info $path1 -arrival_time] + set clock_node [get_node_info -name [get_path_info $path1 -from]] + + set paths2 [get_path -rise_from $from -rise_to $clock_node] + foreach_in_collection path2 $paths2 { + set total_delay [expr $delay + [get_path_info $path2 -arrival_time]] + if {$init == 0 || $total_delay > $max_delay} { + set init 1 + set max_delay $total_delay + } + } + } + return $max_delay +} + +proc ddr3_p0_get_min_clock_path_delay_through_clock_node {from through to} { + set init 0 + set min_delay 0 + set paths [get_path -rise_from $through -rise_to $to -min_path] + foreach_in_collection path1 $paths { + set delay [get_path_info $path1 -arrival_time] + set clock_node [get_node_info -name [get_path_info $path1 -from]] + + set paths2 [get_path -rise_from $from -rise_to $clock_node -min_path] + foreach_in_collection path2 $paths2 { + set total_delay [expr $delay + [get_path_info $path2 -arrival_time]] + if {$init == 0 || $total_delay < $min_delay} { + set init 1 + set min_delay $total_delay + } + } + } + return $min_delay +} + +proc ddr3_p0_get_model_corner {} { + + set operating_conditions [get_operating_conditions] + set return_value [list] + if {[regexp {^([0-9])_H([0-9])_([a-z]+)_([a-z0-9_\-]+)} $operating_conditions matched speedgrade transceiver model corner]} { + + } elseif {[regexp {^([A-Z0-9]+)_([a-z]+)_([a-z0-9_\-]+)} $operating_conditions matched speedgrade model corner]} { + + } + regsub {\-} $corner "n" corner + set return_value [list $model $corner] + return $return_value +} + +proc ddr3_p0_get_min_aiot_delay {pinname} { + + set atom_id [get_atom_node_by_name -name $pinname] + set sin_pin [create_pin_object -atom $atom_id] + set results [get_simulation_results -pin $sin_pin -aiot] + + set rise 0 + set fall 0 + foreach { key value } $results { + if {$key == "Absolute Rise Delay to Far-end"} { + set rise $value + } elseif {$key == "Absolute Fall Delay to Far-end"} { + set fall $value + } + } + return [min $rise $fall] +} + +proc ddr3_p0_get_rise_aiot_delay {pinname} { + + set atom_id [get_atom_node_by_name -name $pinname] + set sin_pin [create_pin_object -atom $atom_id] + set results [get_simulation_results -pin $sin_pin -aiot] + + set rise 0 + foreach { key value } $results { + if {$key == "Absolute Rise Delay to Far-end"} { + set rise $value + } + } + return $rise +} + +proc ddr3_p0_get_fall_aiot_delay {pinname} { + + set atom_id [get_atom_node_by_name -name $pinname] + set sin_pin [create_pin_object -atom $atom_id] + set results [get_simulation_results -pin $sin_pin -aiot] + + set fall 0 + foreach { key value } $results { + if {$key == "Absolute Fall Delay to Far-end"} { + set fall $value + } + } + return $fall +} + + +proc ddr3_p0_get_aiot_attr {pinname attr} { + + set atom_id [get_atom_node_by_name -name $pinname] + set sin_pin [create_pin_object -atom $atom_id] + set results [get_simulation_results -pin $sin_pin -aiot] + + set value 0 + foreach { key value } $results { + if {$key == $attr} { + return $value + } + } + return $value +} + +proc ddr3_p0_get_pll_phase_shift {output_counter_name} { + load_package atoms + read_atom_netlist + set phase_shift "" + + # Remove possible "|divclk" at the end of the name + regsub {\|divclk$} $output_counter_name "" output_counter_name + + # Get all PLL output counters + set pll_output_counter_atoms [get_atom_nodes -type PLL_OUTPUT_COUNTER] + + # Go through the output counters and find the one that matches the above and return the phase + foreach_in_collection atom $pll_output_counter_atoms { + set name [get_atom_node_info -key name -node $atom] + regsub {^[^\:]+\:} $name "" name + regsub -all {\|[^\:]+\:} $name "|" name + + # If the name matches return the phase shift + if {$name == $output_counter_name} { + set phase_shift [get_atom_node_info -key TIME_PHASE_SHIFT -node $atom] + regsub { ps} $phase_shift "" phase_shift + break + } + } + return $phase_shift +} + +# ---------------------------------------------------------------- +# +proc ddr3_p0_get_io_standard {target_pin} { +# +# Description: Gets the I/O standard of the given memory interface pin +# This function assumes the fitter has already completed and the +# compiler report has been loaded. +# +# ---------------------------------------------------------------- + # Look through the pin report + set io_std [ddr3_p0_get_fitter_report_pin_info $target_pin "I/O Standard" -1] + if {$io_std == ""} { + return "UNKNOWN" + } + set result "" + switch -exact -- $io_std { + "SSTL-2 Class I" {set result "SSTL_2_I"} + "Differential 2.5-V SSTL Class I" {set result "DIFF_SSTL_2_I"} + "SSTL-2 Class II" {set result "SSTL_2_II"} + "Differential 2.5-V SSTL Class II" {set result "DIFF_SSTL_2_II"} + "SSTL-18 Class I" {set result "SSTL_18_I"} + "Differential 1.8-V SSTL Class I" {set result "DIFF_SSTL_18_I"} + "SSTL-18 Class II" {set result "SSTL_18_II"} + "Differential 1.8-V SSTL Class II" {set result "DIFF_SSTL_18_II"} + "SSTL-15 Class I" {set result "SSTL_15_I"} + "Differential 1.5-V SSTL Class I" {set result "DIFF_SSTL_15_I"} + "SSTL-15 Class II" {set result "SSTL_15_II"} + "Differential 1.5-V SSTL Class II" {set result "DIFF_SSTL_15_II"} + "1.8-V HSTL Class I" {set result "HSTL_18_I"} + "Differential 1.8-V HSTL Class I" {set result "DIFF_HSTL_18_I"} + "1.8-V HSTL Class II" {set result "HSTL_18_II"} + "Differential 1.8-V HSTL Class II" {set result "DIFF_HSTL_18_II"} + "1.5-V HSTL Class I" {set result "HSTL_I"} + "Differential 1.5-V HSTL Class I" {set result "DIFF_HSTL"} + "1.5-V HSTL Class II" {set result "HSTL_II"} + "Differential 1.5-V HSTL Class II" {set result "DIFF_HSTL_II"} + "1.2-V HSTL Class I" {set result "SSTL_125"} + "Differential 1.2-V HSTL Class I" {set result "DIFF_SSTL_125"} + "1.2-V HSTL Class II" {set result "SSTL_125"} + "Differential 1.2-V HSTL Class II" {set result "DIFF_SSTL_125"} + "SSTL-15" {set result "SSTL_15"} + "Differential 1.5-V SSTL" {set result "DIFF_SSTL_15"} + "SSTL-135" {set result "SSTL_135"} + "Differential 1.35-V SSTL" {set result "DIFF_SSTL_135"} + "SSTL-125" {set result "SSTL_125"} + "Differential 1.25-V SSTL" {set result "DIFF_SSTL_125"} + "SSTL-12" {set result "DIFF_SSTL_125"} + "Differential 1.2-V HSUL" {set result "DIFF_HSUL_12"} + default { + post_message -type error "Found unsupported Memory I/O standard $io_std on pin $target_pin" + set result "UNKNOWN" + } + } + return $result +} + +# Routine to find the termination pins +proc ddr3_p0_get_rzq_pins { instname all_rzq_pins } { + upvar $all_rzq_pins rzqpins + load_package atoms + read_atom_netlist + set rzq_pins [ list ] + set entity_names_on [ ddr3_p0_are_entity_names_on ] + + # Get all termination atoms, to which rzqpin should be attached + set_project_mode -always_show_entity_name off + set instance ${instname}* + set atoms [get_atom_nodes -type TERMINATION -matching [escape_brackets $instance] ] + post_message -type info "Number of Termination Atoms are [get_collection_size $atoms]" + foreach_in_collection term_atom $atoms { + set rzq_pin "" + set atom $term_atom + set term_atom_name [get_atom_node_info -key name -node $term_atom] + post_message -type info "Found Termination Atom $term_atom_name" + set type [get_atom_node_info -key type -node $term_atom] + + # Check until you traverse to an IO_PAD for the RZQ Pin + while { ![regexp IO_PAD $type ] } { + set name [get_atom_node_info -key name -node $atom] + set iterms [get_atom_iports -node $atom] + set iterm_size [llength $iterms] + # Check for Multiple Inputs + if { $iterm_size > 1 } { + post_message -type error " Multiple inputs to a node:$name attached to a Termination_Atom:$term_atom_name " + break + + } + + foreach iterm $iterms { + set fanin [get_atom_port_info -node $atom -type iport -port_id $iterm -key fanin] + set atom [lindex $fanin 0] + set type [get_atom_node_info -key type -node $atom] + set rzq_pin [get_atom_node_info -key name -node $atom] + } + } + + lappend rzq_pins [ join $rzq_pin ] + } + + set_project_mode -always_show_entity_name qsf + set rzqpins $rzq_pins +} + + +proc ddr3_p0_get_acv_read_offset { period dqs_phase dqs_period } { + + set offset [expr abs(90/360.0*$period - $dqs_phase/360.0*$dqs_period)] + if {$offset != 0} { + set part_period [expr $dqs_phase/360.0*$dqs_period - 0.469/2.0 - 0.12] + set offset [max 0.120 $part_period] + } + + return $offset +} +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +proc ddr3_p0_sort_proc {a b} { + set idxs [list 1 2 0] + foreach i $idxs { + set ai [lindex $a $i] + set bi [lindex $b $i] + if {$ai > $bi} { + return 1 + } elseif { $ai < $bi } { + return -1 + } + } + return 0 +} + +proc ddr3_p0_traverse_atom_path {atom_id atom_oport_id path} { + # Return list of {atom oterm_id} pairs by tracing the atom netlist starting from the given atom_id through the given path + # Path consists of list of {atom_type fanin|fanout|end <-optional>} + set result [list] + if {[llength $path] > 0} { + set path_point [lindex $path 0] + set atom_type [lindex $path_point 0] + set next_direction [lindex $path_point 1] + set port_type [lindex $path_point 2] + set atom_optional [lindex $path_point 3] + if {[get_atom_node_info -key type -node $atom_id] == $atom_type} { + if {$next_direction == "end"} { + if {[get_atom_port_info -key type -node $atom_id -port_id $atom_oport_id -type oport] == $port_type} { + lappend result [list $atom_id $atom_oport_id] + } + } elseif {$next_direction == "atom"} { + lappend result [list $atom_id] + } elseif {$next_direction == "fanin"} { + set atom_iport [get_atom_iport_by_type -node $atom_id -type $port_type] + if {$atom_iport != -1} { + set iport_fanin [get_atom_port_info -key fanin -node $atom_id -port_id $atom_iport -type iport] + set source_atom [lindex $iport_fanin 0] + set source_oterm [lindex $iport_fanin 1] + set result [ddr3_p0_traverse_atom_path $source_atom $source_oterm [lrange $path 1 end]] + } elseif {$atom_optional == "-optional"} { + set result [ddr3_p0_traverse_atom_path $atom_id $atom_oport_id [lrange $path 1 end]] + } + } elseif {$next_direction == "fanout"} { + set atom_oport [get_atom_oport_by_type -node $atom_id -type $port_type] + if {$atom_oport != -1} { + set oport_fanout [get_atom_port_info -key fanout -node $atom_id -port_id $atom_oport -type oport] + foreach dest $oport_fanout { + set dest_atom [lindex $dest 0] + set dest_iterm [lindex $dest 1] + set fanout_result_list [ddr3_p0_traverse_atom_path $dest_atom -1 [lrange $path 1 end]] + foreach fanout_result $fanout_result_list { + if {[lsearch $result $fanout_result] == -1} { + lappend result $fanout_result + } + } + } + } + } else { + error "Unexpected path" + } + } elseif {$atom_optional == "-optional"} { + set result [ddr3_p0_traverse_atom_path $atom_id $atom_oport_id [lrange $path 1 end]] + } + } + return $result +} + +# Get the fitter name of the PLL output driving the given pin +proc ddr3_p0_traverse_to_ddio_out_pll_clock {pin msg_list_name} { + upvar 1 $msg_list_name msg_list + set result "" + if {$pin != ""} { + set pin_id [get_atom_node_by_name -name $pin] + set pin_to_pll_path [list {IO_PAD fanin PADIN} {IO_OBUF fanin I} {PSEUDO_DIFF_OUT fanin I -optional} {DELAY_CHAIN fanin DATAIN -optional} {DELAY_CHAIN fanin DATAIN -optional} {DDIO_OUT fanin CLKHI -optional} {OUTPUT_PHASE_ALIGNMENT fanin CLK -optional} {CLKBUF fanin INCLK -optional} {PLL end CLK}] + set pll_id_list [ddr3_p0_traverse_atom_path $pin_id -1 $pin_to_pll_path] + if {[llength $pll_id_list] == 1} { + set atom_oterm_pair [lindex $pll_id_list 0] + set result [get_atom_port_info -key name -node [lindex $atom_oterm_pair 0] -port_id [lindex $atom_oterm_pair 1] -type oport] + } else { + lappend msg_list "Error: PLL clock not found for $pin" + } + } + return $result +} + +proc ddr3_p0_traverse_to_leveling_delay_chain {pin msg_list_name} { + upvar 1 $msg_list_name msg_list + set result "" + if {$pin != ""} { + set pin_id [get_atom_node_by_name -name $pin] + set pin_to_leveling_path [list {IO_PAD fanin PADIN} {IO_OBUF fanin I} {PSEUDO_DIFF_OUT fanin I -optional} {DELAY_CHAIN fanin DATAIN -optional} {DELAY_CHAIN fanin DATAIN -optional} {DDIO_OUT fanin CLK -optional} {FF fanin CLK -optional} {DDIO_OUT fanin CLKHI -optional} {CLK_PHASE_SELECT fanin CLKIN -optional} {LEVELING_DELAY_CHAIN end CLKOUT} ] + set leveling_id_list [ddr3_p0_traverse_atom_path $pin_id -1 $pin_to_leveling_path] + if {[llength $leveling_id_list] == 1} { + set atom_oterm_pair [lindex $leveling_id_list 0] + set result [get_atom_node_info -key name -node [lindex $atom_oterm_pair 0]] + } else { + lappend msg_list "Error: Leveling delay chain not found for $pin" + } + } + + regsub {^[^\:]+\:} $result "" result + regsub -all {\|[^\:]+\:} $result "|" result + + return $result +} + +proc ddr3_p0_traverse_to_clock_phase_select {pin msg_list_name} { + upvar 1 $msg_list_name msg_list + set result "" + if {$pin != ""} { + set pin_id [get_atom_node_by_name -name $pin] + set pin_to_cps_path [list {IO_PAD fanin PADIN} {IO_OBUF fanin I} {PSEUDO_DIFF_OUT fanin I -optional} {DELAY_CHAIN fanin DATAIN -optional} {DELAY_CHAIN fanin DATAIN -optional} {DDIO_OUT fanin CLK -optional} {FF fanin CLK -optional} {DDIO_OUT fanin CLKHI -optional} {CLK_PHASE_SELECT end CLKOUT} ] + set cps_id_list [ddr3_p0_traverse_atom_path $pin_id -1 $pin_to_cps_path] + if {[llength $cps_id_list] == 1} { + set atom_oterm_pair [lindex $cps_id_list 0] + set result [get_atom_node_info -key name -node [lindex $atom_oterm_pair 0]] + } else { + lappend msg_list "Error: Clock phase select not found for $pin" + } + } + + regsub {^[^\:]+\:} $result "" result + regsub -all {\|[^\:]+\:} $result "|" result + + return $result +} + +proc ddr3_p0_traverse_to_clkbuf {pin msg_list_name} { + upvar 1 $msg_list_name msg_list + set result "" + if {$pin != ""} { + set pin_id [get_atom_node_by_name -name $pin] + set pin_to_clkbuf_path [list {IO_PAD fanin PADIN} {IO_OBUF fanin I} {PSEUDO_DIFF_OUT fanin I -optional} {DELAY_CHAIN fanin DATAIN -optional} {DELAY_CHAIN fanin DATAIN -optional} {DDIO_OUT fanin CLK -optional} {FF fanin CLK -optional} {DDIO_OUT fanin CLKHI -optional} {CLKBUF end OUTCLK} ] + set clkbuf_id_list [ddr3_p0_traverse_atom_path $pin_id -1 $pin_to_clkbuf_path] + if {[llength $clkbuf_id_list] == 1} { + set atom_oterm_pair [lindex $clkbuf_id_list 0] + set result [get_atom_node_info -key name -node [lindex $atom_oterm_pair 0]] + } else { + lappend msg_list "Error: Clock buffer not found for $pin" + } + } + + regsub {^[^\:]+\:} $result "" result + regsub -all {\|[^\:]+\:} $result "|" result + + return $result +} + +proc ddr3_p0_traverse_to_dll {dqs_pin msg_list_name} { + upvar 1 $msg_list_name msg_list + set dqs_pin_id [get_atom_node_by_name -name $dqs_pin] + set dqs_to_dll_path [list {IO_PAD fanout PADOUT} {IO_IBUF fanout O} {DQS_DELAY_CHAIN fanin DELAYCTRLIN} {DLL end DELAYCTRLOUT}] + set dll_id_list [ddr3_p0_traverse_atom_path $dqs_pin_id -1 $dqs_to_dll_path] + set result "" + if {[llength $dll_id_list] == 1} { + set dll_atom_oterm_pair [lindex $dll_id_list 0] + set result [get_atom_node_info -key name -node [lindex $dll_atom_oterm_pair 0]] + } elseif {[llength $dll_id_list] > 1} { + lappend msg_list "Error: Found more than 1 DLL" + } else { + lappend msg_list "Error: DLL not found" + } + return $result +} + +proc ddr3_p0_check_hybrid_interface { inst pins_array_name mem_if_memtype } { + upvar $pins_array_name pins + + foreach q_group $pins(q_groups) { + set q_group $q_group + lappend q_groups $q_group + } + set all_dq_pins [ join [ join $q_groups ] ] + set dm_pins $pins(dm_pins) + + set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ] + foreach dq_dm_pin $all_dq_dm_pins { + set io_type [ddr3_p0_get_fitter_report_pin_io_type_info $dq_dm_pin] + if {[string compare -nocase "Column I/O" $io_type] == 0} { + set io_types("column") 1 + } elseif {[string compare -nocase "Row I/O" $io_type] == 0} { + set io_types("row") 1 + } else { + post_message -type warning "Could not determine IO type for pin $dq_dm_pin" + } + } + + if {[llength [array names io_types]] == 0} { + post_message -type warning "Could not determine if memory interface $inst is implemented in hybrid mode. Assuming memory interface is implemented in non-hybrid mode" + return 0 + } elseif {[llength [array names io_types]] == 1} { + return 0 + } elseif {[llength [array names io_types]] == 2} { + return 1 + } else { + post_message -type error "Internal Error: Found IO types [array names io_types]" + qexit -error + } + +} + +proc ddr3_p0_verify_flexible_timing_assumptions { inst pins_array_name mem_if_memtype } { + return 1 +} + +proc ddr3_p0_verify_high_performance_timing_assumptions { inst pins_array_name mem_if_memtype } { + upvar $pins_array_name pins + + set num_errors 0 + load_package verify_ddr + set ck_ckn_pairs [list] + set failed_assumptions [list] + if {[llength $pins(ck_pins)] > 0 && [llength $pins(ck_pins)] == [llength $pins(ckn_pins)]} { + for {set ck_index 0} {$ck_index != [llength $pins(ck_pins)]} {incr ck_index} { + lappend ck_ckn_pairs [list [lindex $pins(ck_pins) $ck_index] [lindex $pins(ckn_pins) $ck_index]] + } + } else { + incr num_errors + lappend failed_assumptions "Error: Could not locate same number of CK pins as CK# pins" + } + + set read_pins_list [list] + set write_pins_list [list] + set read_clock_pairs [list] + set write_clock_pairs [list] + foreach { dqs } $pins(dqs_pins) { dqsn } $pins(dqsn_pins) { dq_list } $pins(q_groups) { + lappend read_pins_list [list $dqs $dq_list] + lappend read_clock_pairs [list $dqs $dqsn] + } + + foreach { dqs } $pins(dqs_pins) { dqsn } $pins(dqsn_pins) { dm_list } $pins(dm_pins) { dq_list } $pins(q_groups) { + lappend write_pins_list [list $dqs [concat $dq_list $dm_list]] + lappend write_clock_pairs [list $dqs $dqsn] + } + + set all_write_dqs_list $pins(dqs_pins) + set all_d_list $pins(all_dq_pins) + if {[llength $pins(q_groups)] == 0} { + incr num_errors + lappend failed_assumptions "Error: Could not locate DQS pins" + } + + if {$num_errors == 0} { + set msg_list [list] + set dll_name [ddr3_p0_traverse_to_dll $dqs msg_list] + set clk_to_write_d [ddr3_p0_traverse_to_ddio_out_pll_clock [lindex $all_d_list 0] msg_list] + set clk_to_write_clock [ddr3_p0_traverse_to_ddio_out_pll_clock [lindex $all_write_dqs_list 0] msg_list] + set clk_to_ck_ckn [ddr3_p0_traverse_to_ddio_out_pll_clock [lindex $pins(ck_pins) 0] msg_list] + foreach msg $msg_list { + set verify_assumptions_exception 1 + incr num_errors + lappend failed_assumptions $msg + } + if {$num_errors == 0} { + set verify_assumptions_exception 0 + set verify_assumptions_result {0} + set verify_assumptions_exception [catch {verify_assumptions -uniphy -memory_type $mem_if_memtype \ + -read_pins_list $read_pins_list -write_pins_list $write_pins_list -ck_ckn_pairs $ck_ckn_pairs \ + -clk_to_write_d $clk_to_write_d -clk_to_write_clock $clk_to_write_clock -clk_to_ck_ckn $clk_to_ck_ckn \ + -dll $dll_name -read_clock_pairs $read_clock_pairs -write_clock_pairs $write_clock_pairs} verify_assumptions_result] + if {$verify_assumptions_exception == 0} { + incr num_errors [lindex $verify_assumptions_result 0] + set failed_assumptions [concat $failed_assumptions [lrange $verify_assumptions_result 1 end]] + } + } + if {$verify_assumptions_exception != 0} { + lappend failed_assumptions "Error: MACRO timing assumptions could not be verified" + incr num_errors + } + } + + if {$num_errors != 0} { + for {set i 0} {$i != [llength $failed_assumptions]} {incr i} { + set raw_msg [lindex $failed_assumptions $i] + if {[regexp {^\W*(Info|Extra Info|Warning|Critical Warning|Error): (.*)$} $raw_msg -- msg_type msg]} { + regsub " " $msg_type _ msg_type + if {$msg_type == "Error"} { + set msg_type "critical_warning" + } + post_message -type $msg_type $msg + } else { + post_message -type info $raw_msg + } + } + post_message -type critical_warning "Read Capture and Write timing analyses may not be valid due to violated timing model assumptions" + } + + return [expr $num_errors == 0] +} + +# Return a tuple of the tCCS value for a given device +proc ddr3_p0_get_tccs { mem_if_memtype dqs_list period args} { + global TimeQuestInfo + array set options [list "-write_deskew" "none" "-dll_length" 0 "-config_period" 0 "-ddr3_discrete" 0] + foreach {option value} $args { + if {[array names options -exact "$option"] != ""} { + set options($option) $value + } else { + error "ERROR: Unknown get_tccs option $option (with value $value; args are $args)" + } + } + + if {$mem_if_memtype == "ddr2"} { + set options(-write_deskew) "none" + } + + set speedgrade [ get_speedgrade_string ] + if { ($mem_if_memtype == "ddr3") && ($speedgrade != "2") && ($options(-write_deskew) == "dynamic") } { + set options(-write_deskew) "static" + } + + if { ($mem_if_memtype == "ddr3") && ($options(-write_deskew) == "none") } { + set options(-write_deskew) "static" + } + + if { ($mem_if_memtype == "ddr3") && ($speedgrade == "4") && ($options(-ddr3_discrete) == 0)} { + set options(-ddr3_discrete) 1 + } + + set interface_type [ddr3_p0_get_io_interface_type $dqs_list] + # The tCCS for a VHPAD interface is the same as a HPAD interface + if {$interface_type == "VHPAD"} { + set interface_type "HPAD" + } + set io_std [ddr3_p0_get_io_standard [lindex $dqs_list 0]] + set result [list 0 0] + if {$interface_type != "" && $interface_type != "UNKNOWN" && $io_std != "" && $io_std != "UNKNOWN"} { + package require ::quartus::ddr_timing_model + + set tccs_params [list IO $interface_type] + if {($mem_if_memtype == "ddr3") && ($options(-ddr3_discrete) == 1)} { + lappend tccs_params NONLEVELED + } elseif {($mem_if_memtype == "ddr3") && ($options(-write_deskew) == "static")} { + if {$options(-dll_length) == 12} { + set options(-dll_length) 10 + } + if {$options(-dll_length) != 0} { + lappend tccs_params STATIC_DESKEW_$options(-dll_length) + } else { + # No DLL length dependency + lappend tccs_params STATIC_DESKEW + } + } elseif {($mem_if_memtype == "ddr3") && ($options(-write_deskew) == "dynamic")} { + lappend tccs_params DYNAMIC_DESKEW + } + if {$options(-ddr3_discrete) == 0 && $options(-write_deskew) != "none"} { + set mode [ddr3_p0_get_deskew_freq_range $tccs_params $period] + if {$mode == [list]} { + post_message -type critical_warning "Memory interface with period $period and write $options(-write_deskew) deskew does not fall in a supported frequency range" + } elseif {[lindex $mode 0] != [list]} { + lappend tccs_params [lindex $mode 0] + puts $tccs_params + } + } + if {[catch {get_io_standard_node_delay -dst TCCS_LEAD -io_standard $io_std -parameters $tccs_params} tccs_lead] != 0 || $tccs_lead == "" || $tccs_lead == 0 || \ + [catch {get_io_standard_node_delay -dst TCCS_LAG -io_standard $io_std -parameters $tccs_params} tccs_lag] != 0 || $tccs_lag == "" || $tccs_lag == 0 } { + set family $TimeQuestInfo(family) + error "Missing $family timing model for tCCS of $io_std $tccs_params" + } else { + return [list $tccs_lead $tccs_lag] + } + } +} + +# For static deskew, get the frequency range of the given configuration +# Return triplet {mode min_freq max_freq} +proc ddr3_p0_get_deskew_freq_range {timing_params period} { + set mode [list] + # freq_range list should be sorted from low to high + if {[lindex $timing_params 2] == "STATIC_DESKEW_8" || [lindex $timing_params 2] == "STATIC_DESKEW_10"} { + # These modes have more than 2 freq ranges + set range_list [list LOW HIGH] + } else { + # Just 1 freq range + set range_list [list [list]] + } + set freq_mode [list] + foreach freq_range $range_list { + if {[catch {get_micro_node_delay -micro MIN -parameters [concat $timing_params $freq_range]} min_freq] != 0 || $min_freq == "" || + [catch {get_micro_node_delay -micro MAX -parameters [concat $timing_params $freq_range]} max_freq] != 0 || $max_freq == ""} { + # Invalid mode + } else { + set max_freq_period [expr 1000.0 / $min_freq] + set min_freq_period [expr 1000.0 / $max_freq] + lappend freq_mode [list $freq_range $min_freq $max_freq] + if {$period >= $min_freq_period && $period <= $max_freq_period} { + set mode [lindex $freq_mode end] + break + } + } + } + if {$mode == [list] && $freq_mode != [list]} { + if {$period < $min_freq_period} { + # Fastest mode + set mode [lindex $freq_mode end] + } else { + # Slowest mode + set mode [lindex $freq_mode 0] + } + } + return $mode +} + + + + +# Return a tuple of setup,hold time for read capture +proc ddr3_p0_get_tsw { mem_if_memtype dqs_list period args} { + global TimeQuestInfo + array set options [list "-read_deskew" "none" "-dll_length" 0 "-config_period" 0 "-ddr3_discrete" 0] + foreach {option value} $args { + if {[array names options -exact "$option"] != ""} { + set options($option) $value + } else { + error "ERROR: Unknown get_tsw option $option (with value $value; args are $args)" + } + } + + set interface_type [ddr3_p0_get_io_interface_type $dqs_list] + if {$interface_type == "VHPAD"} { + set interface_type "HPAD" + } + set io_std [ddr3_p0_get_io_standard [lindex $dqs_list 0]] + + if {$interface_type != "" && $interface_type != "UNKNOWN" && $io_std != "" && $io_std != "UNKNOWN"} { + package require ::quartus::ddr_timing_model + set family $TimeQuestInfo(family) + set tsw_params [list IO $interface_type] + if {$options(-ddr3_discrete) == 1} { + lappend tsw_params NONLEVELED + } elseif {$options(-read_deskew) == "static"} { + if {$options(-dll_length) != 0} { + lappend tsw_params STATIC_DESKEW_$options(-dll_length) + } else { + # No DLL length dependency + lappend tsw_params STATIC_DESKEW + } + } elseif {$options(-read_deskew) == "dynamic"} { + lappend tsw_params DYNAMIC_DESKEW + } + + if {[catch {get_io_standard_node_delay -dst TSU -io_standard $io_std -parameters $tsw_params} tsw_setup] != 0 || $tsw_setup == "" || $tsw_setup == 0 || \ + [catch {get_io_standard_node_delay -dst TH -io_standard $io_std -parameters $tsw_params} tsw_hold] != 0 || $tsw_hold == "" || $tsw_hold == 0 } { + error "Missing $family timing model for tSW of $io_std $tsw_params" + } else { + # Derate tSW for DDR2 on VPAD in CIII Q240 parts + # The tSW for HPADs and for other interface types on C8 devices + # have a large guardband, so derating for them is not required + if {[get_part_info -package -pin_count $TimeQuestInfo(part)] == "PQFP 240"} { + if {[catch {get_io_standard_node_delay -dst TSU -io_standard $io_std -parameters [list IO $interface_type Q240_DERATING]} tsw_setup_derating] != 0 || $tsw_setup_derating == 0 || \ + [catch {get_io_standard_node_delay -dst TH -io_standard $io_std -parameters [list IO $interface_type Q240_DERATING]} tsw_hold_derating] != 0 || $tsw_hold_derating == 0} { + set f "$io_std/$interface_type/$family" + switch -glob $f { + "SSTL_18*/VPAD/Cyclone III" { + set tsw_setup_derating 50 + set tsw_hold_derating 135 + } + "SSTL_18*/VPAD/Cyclone IV E" { + set tsw_setup_derating 50 + set tsw_hold_derating 135 + } + default { + set tsw_setup_derating 0 + set tsw_hold_derating 0 + } + } + } + incr tsw_setup $tsw_setup_derating + incr tsw_hold $tsw_hold_derating + } + return [list $tsw_setup $tsw_hold] + } + } +} + +# ---------------------------------------------------------------- +# +proc ddr3_p0_get_fitter_report_pin_info_from_report {target_pin info_type pin_report_id} { +# +# Description: Gets the report field for the given pin in the given report +# +# ---------------------------------------------------------------- + set pin_name_column [ddr3_p0_get_report_column $pin_report_id "Name"] + set info_column [ddr3_p0_get_report_column $pin_report_id $info_type] + set result "" + + if {$pin_name_column == 0 && 0} { + set row_index [get_report_panel_row_index -id $pin_report_id $target_pin] + if {$row_index != -1} { + set row [get_report_panel_row -id $pin_report_id -row $row_index] + set result [lindex $row $info_column] + } + } else { + set report_rows [get_number_of_rows -id $pin_report_id] + for {set row_index 1} {$row_index < $report_rows && $result == ""} {incr row_index} { + set row [get_report_panel_row -id $pin_report_id -row $row_index] + set pin [lindex $row $pin_name_column] + if {$pin == $target_pin} { + set result [lindex $row $info_column] + } + } + } + return $result +} + +# ---------------------------------------------------------------- +# +proc ddr3_p0_get_fitter_report_pin_info {target_pin info_type preferred_report_id {found_report_id_name ""}} { +# +# Description: Gets the report field for the given pin by searching through the +# input, output and bidir pin reports +# +# ---------------------------------------------------------------- + if {$found_report_id_name != ""} { + upvar 1 $found_report_id_name found_report_id + } + set found_report_id -1 + set result "" + if {$preferred_report_id == -1} { + set pin_report_list [list "Fitter||Resource Section||Bidir Pins" "Fitter||Resource Section||Input Pins" "Fitter||Resource Section||Output Pins"] + for {set pin_report_index 0} {$pin_report_index != [llength $pin_report_list] && $result == ""} {incr pin_report_index} { + set pin_report_id [get_report_panel_id [lindex $pin_report_list $pin_report_index]] + if {$pin_report_id != -1} { + set result [ddr3_p0_get_fitter_report_pin_info_from_report $target_pin $info_type $pin_report_id] + if {$result != ""} { + set found_report_id $pin_report_id + } + } else { + post_message -type error "ddr3_p0_pin_map.tcl: Failed to find fitter report. If report timing is run after an ECO, the user must set_global_assignment -name ECO_REGENERATE_REPORT ON in ddr3_p0.qsf and in ddr3_p0_pin_assignment.tcl files and rerun ECO and STA" + } + } + } else { + set result [ddr3_p0_get_fitter_report_pin_info_from_report $target_pin $info_type $preferred_report_id] + if {$result != ""} { + set found_report_id $preferred_report_id + } + } + return $result +} +# ---------------------------------------------------------------- +# +proc ddr3_p0_get_fitter_report_pin_io_type_info {target_pin} { +# +# Description: Gets the type of IO, either column or row for +# a given pin. If none found then "" is returned. +# +# ---------------------------------------------------------------- + set result "" + set pin_report_id [get_report_panel_id "Fitter||Resource Section||All Package Pins"] + if {$pin_report_id != -1} { + set pin_name_column [ddr3_p0_get_report_column $pin_report_id "Pin Name/Usage"] + set info_column [ddr3_p0_get_report_column $pin_report_id "I/O Type"] + if {$pin_name_column == 0 && 0} { + set row_index [get_report_panel_row_index -id $pin_report_id $target_pin] + if {$row_index != -1} { + set row [get_report_panel_row -id $pin_report_id -row $row_index] + set result [lindex $row $info_column] + } + } else { + set report_rows [get_number_of_rows -id $pin_report_id] + for {set row_index 1} {$row_index < $report_rows && $result == ""} {incr row_index} { + set row [get_report_panel_row -id $pin_report_id -row $row_index] + set pin [lindex $row $pin_name_column] + if {$pin == $target_pin} { + set result [lindex $row $info_column] + } + } + } + } else { + set pin_report_id [get_report_panel_id "Fitter||Resource Section||DQS Summary"] + if {$pin_report_id != -1} { + + set report_rows [get_number_of_rows -id $pin_report_id] + set pin_name_column [ddr3_p0_get_report_column $pin_report_id "Name"] + set info_column [ddr3_p0_get_report_column $pin_report_id "I/O Edge"] + + for {set row_index 1} {$row_index < $report_rows && $result == ""} {incr row_index} { + set row [get_report_panel_row -id $pin_report_id -row $row_index] + set pin [lindex $row $pin_name_column] + regsub -all {[ \r\t\n]+} $pin "" pin_no_whitespace + if {$pin_no_whitespace == $target_pin} { + set result [lindex $row $info_column] + } + } + + if {($result == "Bottom") || ($result == "Top")} { + set result "Column I/O" + } elseif {($result == "Left") || ($result == "Right")} { + set result "Row I/O" + } + } + } + + return $result +} +# ---------------------------------------------------------------- +# +proc ddr3_p0_get_io_interface_type {pin_list} { +# +# Description: Gets the type of pin that the given pins are placed on +# either (HPAD, VPAD, HYBRID, "", or UNKNOWN). +# "" is returned if pin_list is empty +# UNKNOWN is returned if an error was encountered +# This function assumes the fitter has already completed and the +# compiler report has been loaded. +# +# ---------------------------------------------------------------- + set preferred_report_id -1 + set interface_type "" + foreach target_pin $pin_list { + set io_bank [ddr3_p0_get_fitter_report_pin_info $target_pin "I/O Bank" $preferred_report_id preferred_report_id] + if {[regexp -- {^([0-9]+)[A-Z]*} $io_bank -> io_bank_number]} { + if {$io_bank_number == 1 || $io_bank_number == 2 || $io_bank_number == 5 || $io_bank_number == 6} { + # Row I/O + if {$interface_type == ""} { + set interface_type "HPAD" + } elseif {$interface_type == "VIO"} { + set interface_type "HYBRID" + } + } elseif {$io_bank_number == 3 || $io_bank_number == 4 || $io_bank_number == 7 || $io_bank_number == 8} { + if {$interface_type == ""} { + set interface_type "VPAD" + } elseif {$interface_type == "HIO"} { + set interface_type "HYBRID" + } + } else { + post_message -type critical_warning "Unknown I/O bank $io_bank for pin $target_pin" + # Assume worst case performance (mixed HIO/VIO interface) + set interface_type "HYBRID" + } + } + } + return $interface_type +} + + +# ---------------------------------------------------------------- +# +proc ddr3_p0_get_report_column { report_id str} { +# +# Description: Gets the report column index with the given header string +# +# ---------------------------------------------------------------- + set target_col [get_report_panel_column_index -id $report_id $str] + if {$target_col == -1} { + error "Cannot find $str column" + } + return $target_col +} + +proc ddr3_p0_traverse_to_dll_id {dqs_pin msg_list_name} { + upvar 1 $msg_list_name msg_list + set dqs_pin_id [get_atom_node_by_name -name $dqs_pin] + set dqs_to_dll_path [list {IO_PAD fanout PADOUT} {IO_IBUF fanout O} {DQS_DELAY_CHAIN fanin DELAYCTRLIN} {DLL end DELAYCTRLOUT}] + set dll_id_list [ddr3_p0_traverse_atom_path $dqs_pin_id -1 $dqs_to_dll_path] + set dll_id -1 + if {[llength $dll_id_list] == 1} { + set dll_atom_oterm_pair [lindex $dll_id_list 0] + set dll_id [lindex $dll_atom_oterm_pair 0] + } elseif {[llength $dll_id_list] > 1} { + lappend msg_list "Error: Found more than 1 DLL" + } else { + lappend msg_list "Error: DLL not found" + } + return $dll_id +} + +proc ddr3_p0_traverse_to_dqs_delaychain_id {dqs_pin msg_list_name} { + upvar 1 $msg_list_name msg_list + set dqs_pin_id [get_atom_node_by_name -name $dqs_pin] + set dqs_to_delaychain_path [list {IO_PAD fanout PADOUT} {IO_IBUF fanout O} {DQS_DELAY_CHAIN atom}] + set delaychain_id_list [ddr3_p0_traverse_atom_path $dqs_pin_id -1 $dqs_to_delaychain_path] + set delaychain_id -1 + if {[llength $delaychain_id_list] == 1} { + set delaychain_atom_oterm_pair [lindex $delaychain_id_list 0] + set delaychain_id [lindex $delaychain_atom_oterm_pair 0] + } elseif {[llength $delaychain_id_list] > 1} { + lappend msg_list "Error: Found more than 1 DQS delaychain" + } else { + lappend msg_list "Error: DQS delaychain not found" + } + return $delaychain_id +} + +proc ddr3_p0_get_dqs_phase { dqs_pins } { + set dqs_phase -100 + set dqs0 [lindex $dqs_pins 0] + if {$dqs0 != ""} { + set dqs_delay_chain_id [ddr3_p0_traverse_to_dqs_delaychain_id $dqs0 msg_list] + if {$dqs_delay_chain_id != -1} { + set dqs_phase [get_atom_node_info -key INT_DQS_PHASE_SHIFT -node $dqs_delay_chain_id] + } + } + + set dqs_phase [expr {$dqs_phase / 100}] + + if {$dqs_phase < 0} { + set dqs_phase 90 + post_message -type critical_warning "Unable to determine DQS delay chain phase shift. Assuming default setting of $dqs_phase" + } + + return $dqs_phase +} + +proc ddr3_p0_get_dqs_period { dqs_pins } { + set dqs_period -100 + set dqs0 [lindex $dqs_pins 0] + if {$dqs0 != ""} { + set dll_id [ddr3_p0_traverse_to_dll_id $dqs0 msg_list] + if {$dll_id != -1} { + set dqs_period_str [get_atom_node_info -key TIME_INPUT_FREQUENCY -node $dll_id] + if {[regexp {(.*) ps} $dqs_period_str matched dqs_period_ps] == 1} { + set dqs_period [expr $dqs_period_ps/1000.0] + } elseif {[regexp {(.*) ps} $dqs_period_str matched dqs_period_ns] == 1} { + set dqs_period $dqs_period_ns + } + + } + } + + if {$dqs_period < 0} { + set dqs_period 0 + post_message -type critical_warning "Unable to determine DQS delay chain period. Assuming default setting of $dqs_period" + } + + return $dqs_period +} + +proc ddr3_p0_get_operating_conditions_number {} { + set cur_operating_condition [get_operating_conditions] + set counter 0 + foreach_in_collection op [get_available_operating_conditions] { + if {[string compare $cur_operating_condition $op] == 0} { + return $counter + } + incr counter + } + return $counter +} + +proc ddr3_p0_get_rzq_pins { instname all_rzq_pins } { + upvar $all_rzq_pins rzqpins + load_package atoms + read_atom_netlist + set rzq_pins [ list ] + set entity_names_on [ ddr3_p0_are_entity_names_on ] + + # Get all termination atoms, to which rzqpin should be attached + set_project_mode -always_show_entity_name off + set instance ${instname}* + set atoms [get_atom_nodes -type TERMINATION -matching [escape_brackets $instance] ] + post_message -type info "Number of Termination Atoms: [get_collection_size $atoms]" + foreach_in_collection term_atom $atoms { + set rzq_pin "" + set atom $term_atom + set term_atom_name [get_atom_node_info -key name -node $term_atom] + post_message -type info "Found Termination Atom $term_atom_name" + set type [get_atom_node_info -key type -node $term_atom] + + # Check until you traverse to an IO_PAD for the RZQ Pin + while { ![regexp IO_PAD $type ] } { + set name [get_atom_node_info -key name -node $atom] + set iterms [get_atom_iports -node $atom] + set iterm_size [llength $iterms] + # Check for Multiple Inputs + if { $iterm_size > 1 } { + post_message -type error " Multiple inputs to a node:$name attached to a Termination_Atom:$term_atom_name " + break + + } + + foreach iterm $iterms { + set fanin [get_atom_port_info -node $atom -type iport -port_id $iterm -key fanin] + set atom [lindex $fanin 0] + set type [get_atom_node_info -key type -node $atom] + set rzq_pin [get_atom_node_info -key name -node $atom] + } + } + + lappend rzq_pins [ join $rzq_pin ] + } + + set_project_mode -always_show_entity_name qsf + set rzqpins $rzq_pins +} + +proc ddr3_p0_get_ddr_pins { instname allpins } { + # We need to make a local copy of the allpins associative array + upvar allpins pins + global ::GLOBAL_ddr3_p0_dqs_group_size + global ::GLOBAL_ddr3_p0_number_of_dqs_groups + + set synthesis_flow 0 + set sta_flow 0 + if { $::TimeQuestInfo(nameofexecutable) == "quartus_map" } { + set synthesis_flow 1 + } elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_sta" } { + set sta_flow 1 + } + + set dqs_inst "altdq_dqs2_inst|" + set dqs_pins [ list ] + set dqsn_pins [ list ] + set q_groups [ list ] + set dqs_in_clocks [ list ] + set dqs_out_clocks [ list ] + set dqsn_out_clocks [ list ] + + for { set i 0 } { $i < $::GLOBAL_ddr3_p0_number_of_dqs_groups } { incr i } { + + set dqs_string ${instname}|p0|umemphy|uio_pads|dq_ddio\[$i\].ubidir_dq_dqs|${dqs_inst}obuf_os_0|o + set dqs_local_pins [ ddr3_p0_get_names_in_collection [ get_fanouts $dqs_string ] ] + set dqsn_string ${instname}|p0|umemphy|uio_pads|dq_ddio\[$i\].ubidir_dq_dqs|${dqs_inst}obuf_os_bar_0|o + set dqsn_local_pins [ ddr3_p0_get_names_in_collection [ get_fanouts $dqsn_string ] ] + + set dm_string ${instname}|p0|umemphy|uio_pads|dq_ddio\[$i\].ubidir_dq_dqs|${dqs_inst}extra_output_pad_gen\[0\].obuf_1|o + set dm_local_pins [ ddr3_p0_get_names_in_collection [ get_fanouts $dm_string ] ] + + set dqs_in_clock(dqs_pin) [ lindex $dqs_local_pins 0 ] + set dqs_in_clock(dqs_shifted_pin) "${instname}|p0|umemphy|uio_pads|dq_ddio[$i].ubidir_dq_dqs|${dqs_inst}dqs_delay_chain|dqsbusout" + set dqs_in_clock(div_name) "${instname}|div_clock_$i" + set dqs_in_clock(div_pin) "${instname}|p0|umemphy|uread_datapath|read_capture_clk_div2[$i]" + + lappend dqs_in_clocks [ array get dqs_in_clock ] + + set dqs_out_clock(dst) [ lindex $dqs_local_pins 0 ] + set dqs_out_clock(src) $dqs_string + set dqs_out_clock(dm_pin) [ lindex $dm_local_pins 0 ] + set dqsn_out_clock(dst) [ lindex $dqsn_local_pins 0 ] + set dqsn_out_clock(src) $dqsn_string + set dqsn_out_clock(dm_pin) [ lindex $dm_local_pins 0 ] + lappend dqs_out_clocks [ array get dqs_out_clock ] + lappend dqsn_out_clocks [ array get dqsn_out_clock ] + + set q_group [ list ] + for { set j 0 } { $j < $::GLOBAL_ddr3_p0_dqs_group_size } { incr j } { + set index [ expr $i * $::GLOBAL_ddr3_p0_dqs_group_size + $j ] + set q_string ${instname}|p0|umemphy|uio_pads|dq_ddio\[$i\].ubidir_dq_dqs|${dqs_inst}pad_gen\[${j}\].data_out|o + set tmp_q_pins [ ddr3_p0_get_names_in_collection [ get_fanouts $q_string ] ] + + lappend q_group $tmp_q_pins + } + + if { [llength $dqs_local_pins] != 1} { post_sdc_message critical_warning "Could not find DQS pin number $i" } + if { [llength $dqsn_local_pins] != 1} { post_sdc_message critical_warning "Could not find DQSn pin number $i" } + if { [llength $q_group] != $::GLOBAL_ddr3_p0_dqs_group_size} { + post_sdc_message critical_warning "Could not find correct number of D pins for K pin $i. \ + Found [llength $q_group] pins. Expecting ${::GLOBAL_ddr3_p0_dqs_group_size}." + } + + lappend dqs_pins [ join $dqs_local_pins ] + lappend dqsn_pins [ join $dqsn_local_pins ] + lappend dm_pins [ join $dm_local_pins ] + lappend q_groups [ join $q_group ] + } + + set pins(dqs_pins) $dqs_pins + set pins(dqsn_pins) $dqsn_pins + set pins(dm_pins) $dm_pins + set pins(q_groups) $q_groups + set pins(all_dq_pins) [ join [ join $q_groups ] ] + set pins(dqs_in_clocks) $dqs_in_clocks + set pins(dqs_out_clocks) $dqs_out_clocks + set pins(dqsn_out_clocks) $dqsn_out_clocks + + set pins(all_dq_dm_pins) [ concat $pins(all_dq_pins) $pins(dm_pins) ] + + # Other Outputs + + set pins(ck_pins) [ list ] + set pins(ckn_pins) [ list ] + set pins(add_pins) [ list ] + set pins(ba_pins) [ list ] + set pins(cmd_pins) [ list ] + set pins(reset_pins) [ list ] + + set patterns [ list ] + lappend patterns ck_pins ${instname}|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[*].uclk_generator|pseudo_diffa_0|o + lappend patterns ckn_pins ${instname}|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[*].uclk_generator|pseudo_diffa_0|obar + + set addr_cmd_postfix "acblock[*].ddio_out|dataout" + lappend patterns reset_pins ${instname}|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad|${addr_cmd_postfix} + + lappend patterns add_pins ${instname}|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad|${addr_cmd_postfix} + lappend patterns ba_pins ${instname}|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad|${addr_cmd_postfix} + lappend patterns cmd_pins ${instname}|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad|${addr_cmd_postfix} + + foreach {pin_type pattern} $patterns { + set local_pins [ ddr3_p0_get_names_in_collection [ get_fanouts $pattern ] ] + if {[llength $local_pins] == 0} { + post_message -type critical_warning "Could not find pin of type $pin_type from pattern $pattern" + } else { + foreach pin [lsort -unique $local_pins] { + lappend pins($pin_type) $pin + } + } + } + + + set pins(ac_pins) [ concat $pins(add_pins) $pins(ba_pins) $pins(cmd_pins) $pins(reset_pins)] + set pins(ac_wo_reset_pins) [ concat $pins(add_pins) $pins(ba_pins) $pins(cmd_pins)] + + set pins(afi_ck_pins) ${instname}|p0|umemphy|afi_clk_reg + set pins(avl_ck_pins) ${instname}|p0|umemphy|avl_clk_reg + set pins(avl_phy_ck_pins) ${instname}|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|input_path_gen[0].read_fifo~READ_ADDRESS_DFF + set pins(config_ck_pins) ${instname}|p0|umemphy|config_clk_reg + set pins(dqs_enable_regs_pins) ${instname}|p0|umemphy|uio_pads|dq_ddio[*].ubidir_dq_dqs|altdq_dqs2_inst|dqs_enable_ctrl~DQSENABLEOUT_DFF + set inst_driver "" + set pins(driver_core_ck_pins) "" + if {[regexp -nocase {if[0-9]$} $instname] == 1} { + set inst_driver [regsub {if[0-9]$} $instname "d0"] + } + if {[string compare -nocase $inst_driver ""] != 0} { + set pins(driver_core_ck_pins) ${inst_driver}|traffic_generator_0|pnf_per_bit_persist[0] + } + + ############# + # PLL STUFF # + ############# + + set pll_afi_clock "_UNDEFINED_PIN_" + set pll_ck_clock "_UNDEFINED_PIN_" + set pll_dq_write_clock "_UNDEFINED_PIN_" + set pll_write_clock "_UNDEFINED_PIN_" + set pll_avl_clock "_UNDEFINED_PIN_" + set pll_avl_phy_clock "_UNDEFINED_PIN_" + set pll_config_clock "_UNDEFINED_PIN_" + set pll_ref_clock "_UNDEFINED_PIN_" + set pll_ref_clock_input_buffer "_UNDEFINED_PIN_" + set pll_driver_core_clock "_UNDEFINED_PIN_" + + set msg_list [ list ] + + # CLOCK OUTPUT PLL + set pll_ck_clock_id [ddr3_p0_get_output_clock_id $pins(ck_pins) "CK Output" msg_list] + if {$pll_ck_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins [join $pins(ck_pins)]" + } else { + set pll_ck_clock [ddr3_p0_get_pll_clock_name $pll_ck_clock_id] + } + set pins(pll_ck_clock) $pll_ck_clock + + + # DRIVER CORE CLOCK PLL + if {[string compare -nocase $pins(driver_core_ck_pins) ""] != 0 && [get_collection_size [get_registers -nowarn $pins(driver_core_ck_pins)]] > 0} { + set pll_driver_core_clock_id [ddr3_p0_get_output_clock_id $pins(driver_core_ck_pins) "DRIVER CORE CK" msg_list] + if {$pll_driver_core_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins [join $pins(driver_core_ck_pins)]" + } else { + set pll_driver_core_clock [ddr3_p0_get_pll_clock_name $pll_driver_core_clock_id] + } + } + set pins(pll_driver_core_clock) $pll_driver_core_clock + + # AFI CLOCK PLL + set pll_afi_clock_id [ddr3_p0_get_output_clock_id $pins(afi_ck_pins) "AFI CK" msg_list] + if {$pll_afi_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins [join $pins(afi_ck_pins)]" + } else { + set pll_afi_clock [ddr3_p0_get_pll_clock_name $pll_afi_clock_id] + } + set pins(pll_afi_clock) $pll_afi_clock + + + # DQ PLL + set pll_dq_write_clock_id [ddr3_p0_get_output_clock_id [ join [ join $pins(q_groups) ]] "Write DQ CK" msg_list 20] + if {$pll_dq_write_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins [ join [ join $pins(q_groups) ]]" + } else { + set pll_dq_write_clock [ddr3_p0_get_pll_clock_name $pll_dq_write_clock_id] + } + set pins(pll_dq_write_clock) $pll_dq_write_clock + + # DQS PLL + set pll_write_clock_id [ddr3_p0_get_output_clock_id $pins(dqs_pins) "Write CK" msg_list 20] + if {$pll_write_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins $pins(dqs_pins)" + } else { + set pll_write_clock [ddr3_p0_get_pll_clock_name $pll_write_clock_id] + } + set pins(pll_write_clock) $pll_write_clock + + + + set pll_avl_clock_id [ddr3_p0_get_output_clock_id $pins(avl_ck_pins) "Avalon Bus CK" msg_list] + if {$pll_avl_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins [join $pins(avl_ck_pins)]" + } else { + set pll_avl_clock [ddr3_p0_get_pll_clock_name $pll_avl_clock_id] + } + set pins(pll_avl_clock) $pll_avl_clock + + if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} { + set pll_avl_phy_clock_id [ddr3_p0_get_output_clock_id $pins(avl_phy_ck_pins) "Avalon PHY Bus CK" msg_list] + if {$pll_avl_phy_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins [join $pins(avl_phy_ck_pins)]" + } else { + set pll_avl_phy_clock [ddr3_p0_get_pll_clock_name $pll_avl_phy_clock_id] + } + } + set pins(pll_avl_phy_clock) $pll_avl_phy_clock + + set pll_config_clock_id [ddr3_p0_get_output_clock_id $pins(config_ck_pins) "Config CK" msg_list] + if {$pll_config_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ddr3_p0_pin_map.tcl: $msg" + } + post_message -type critical_warning "ddr3_p0_pin_map.tcl: Failed to find PLL clock for pins [join $pins(config_ck_pins)]" + } else { + set pll_config_clock [ddr3_p0_get_pll_clock_name $pll_config_clock_id] + } + set pins(pll_config_clock) $pll_config_clock + + + # REF CLOCK + set pll_ref_clock_id [ddr3_p0_get_input_clk_id $pll_ck_clock_id] + if {$pll_ref_clock_id == -1} { + post_message -type error "ddr3_p0_pin_map.tcl: Failed to find PLL reference clock" + } else { + set pll_ref_clock [get_node_info -name $pll_ref_clock_id] + } + set pins(pll_ref_clock) $pll_ref_clock + + if {$synthesis_flow == 0} { + if {$pll_ref_clock_id != -1} { + set pll_ref_clock_id_fanout_edges [get_node_info -fanout_edges $pll_ref_clock_id] + if {[llength $pll_ref_clock_id_fanout_edges] > 0} { + for {set i 0} {$i < 1} {incr i} { + set pll_ref_clock_input_buffer [get_node_info -name [get_edge_info -dst [get_node_info -fanout_edges [get_edge_info -dst [lindex $pll_ref_clock_id_fanout_edges $i]]]]] + } + } + } + } + set pins(pll_ref_clock_input_buffer) $pll_ref_clock_input_buffer + + + set entity_names_on [ ddr3_p0_are_entity_names_on ] + + # Instance name prefix + + set prefix [ string map "| |*:" $instname ] + set prefix "*:$prefix" + + ##################### + # READ CAPTURE DDIO # + ##################### + + # Pending ALTDQ_DQS fix + # Half rate: separate read and write ALTDQ_DQS + # Full rate: bidirectional ALTDQ_DQS + + set read_capture_ddio_prefix [expr { $entity_names_on ? \ + "$prefix|*:p0|*:umemphy|*:uio_pads|*:dq_ddio\[*\].ubidir_dq_dqs|*:" : \ + "$instname|p0|umemphy|uio_pads|dq_ddio\[*\].ubidir_dq_dqs|" }] + + set read_capture_ddio [list "${read_capture_ddio_prefix}${dqs_inst}*input_path_gen\[*\].capture_reg~DFFLO" \ + "${read_capture_ddio_prefix}${dqs_inst}*input_path_gen\[*\].aligned_input\[*\]"] + set pins(read_capture_ddio) $read_capture_ddio + + ################### + # RESET REGISTERS # + ################### + + # the output of this flop feeds the asynchronous clear pin of the reset registers and should be false pathed + # since the deassertion of the reset is synchronous with the use of a reset pipeline + # normal timing analysis will take care that + set afi_reset_reg $prefix|*:p0|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3] + if { ! $entity_names_on } { + set afi_reset_reg $instname|p0|umemphy|ureset|ureset_afi_clk|reset_reg[3] + } + set pins(afi_reset_reg) $afi_reset_reg + + set seq_reset_reg ${prefix}|*:s0|* + if { ! $entity_names_on } { + set seq_reset_reg ${instname}|s0|* + } + set pins(seq_reset_reg) $seq_reset_reg + + # first flop of a synchronzier + # sequencer issues multiple resets during calibration, reset is synced over from AFI to read capture clock domain + set sync_reg $prefix|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync + if { ! $entity_names_on } { + set sync_reg $instname|p0|umemphy|uread_datapath|read_buffering[*].seq_read_fifo_reset_sync + } + set pins(sync_reg) $sync_reg + + + ############################### + # DATA RESYNCHRONIZATION FIFO # + ############################### + + set fifo_wraddress_reg $prefix|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*] + if { ! $entity_names_on } { + set fifo_wraddress_reg $instname|p0|umemphy|uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*] + } + set pins(fifo_wraddress_reg) $fifo_wraddress_reg + + set fifo_rdaddress_reg $prefix|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].rdaddress[*] + if { ! $entity_names_on } { + set fifo_rdaddress_reg $instname|p0|umemphy|uread_datapath|read_buffering[*].read_subgroup[*].rdaddress[*] + } + set pins(fifo_rdaddress_reg) $fifo_rdaddress_reg + + set fifo_wrdata_reg $prefix|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF* + if { ! $entity_names_on } { + set fifo_wrdata_reg $instname|p0|umemphy|uio_pads|dq_ddio[*].ubidir_dq_dqs|altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF* + } + set pins(fifo_wrdata_reg) $fifo_wrdata_reg + + set fifo_rddata_reg $prefix|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*] + if { ! $entity_names_on } { + set fifo_rddata_reg $instname|p0|umemphy|uio_pads|dq_ddio[*].ubidir_dq_dqs|altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*] + } + set pins(fifo_rddata_reg) $fifo_rddata_reg + +} + +proc ddr3_p0_initialize_ddr_db { ddr_db_par } { + upvar $ddr_db_par local_ddr_db + + global ::GLOBAL_ddr3_p0_corename + + post_sdc_message info "Initializing DDR database for CORE $::GLOBAL_ddr3_p0_corename" + set instance_list [ddr3_p0_get_core_instance_list $::GLOBAL_ddr3_p0_corename] + # set local_ddr_db(instance_list) $instance_list + + foreach instname $instance_list { + post_sdc_message info "Finding port-to-pin mapping for CORE: $::GLOBAL_ddr3_p0_corename INSTANCE: $instname" + + ddr3_p0_get_ddr_pins $instname allpins + + ddr3_p0_verify_ddr_pins allpins + + set local_ddr_db($instname) [ array get allpins ] + } +} + +proc ddr3_p0_verify_ddr_pins { pins_par } { + upvar $pins_par pins + + # Verify Q groups + set current_q_group_size -1 + foreach q_group $pins(q_groups) { + set group_size [ llength $q_group ] + if { $group_size == 0 } { + post_message -type critical_warning "Q group of size 0" + } + if { $current_q_group_size == -1 } { + set current_q_group_size $group_size + } else { + if { $current_q_group_size != $group_size } { + post_message -type critical_warning "Inconsistent Q group size across groups" + } + } + } + + # Verify DM pins + set counted_dm_pins [ llength $pins(dm_pins) ] + if { $::GLOBAL_ddr3_p0_number_of_dm_pins != $counted_dm_pins } { + post_message -type critical_warning "Unexpected number of detected DM pins: $counted_dm_pins" + post_message -type critical_warning " expected: $::GLOBAL_ddr3_p0_number_of_dm_pins" + } + # Verify Address/Command/BA pins + if { [ llength $pins(add_pins) ] == 0 } { + post_message -type critical_warning "Address pins of size 0" + } + if { [ llength $pins(cmd_pins) ] == 0 } { + post_message -type critical_warning "Command pins of size 0" + } + if { [ llength $pins(ba_pins) ] == 0 } { + post_message -type critical_warning "BA pins of size 0" + } + if { [ llength $pins(reset_pins) ] == 0 } { + post_message -type critical_warning "Reset pins of size 0" + } +} + +proc ddr3_p0_get_all_instances_div_names { ddr_db_par } { + upvar $ddr_db_par local_ddr_db + + set div_names [ list ] + set instnames [ array names local_ddr_db ] + foreach instance $instnames { + array set pins $local_ddr_db($instance) + + foreach { dqs_in_clock_struct } $pins(dqs_in_clocks) { + array set dqs_in_clock $dqs_in_clock_struct + lappend div_names $dqs_in_clock(div_name) + } + } + + return $div_names +} + +proc ddr3_p0_get_all_instances_dqs_pins { ddr_db_par } { + upvar $ddr_db_par local_ddr_db + + set dqs_pins [ list ] + set instnames [ array names local_ddr_db ] + foreach instance $instnames { + array set pins $local_ddr_db($instance) + + foreach { dqs_pin } $pins(dqs_pins) { + lappend dqs_pins ${dqs_pin}_IN + lappend dqs_pins ${dqs_pin}_OUT + } + foreach { dqsn_pin } $pins(dqsn_pins) { + lappend dqs_pins ${dqsn_pin}_OUT + } + foreach { ck_pin } $pins(ck_pins) { + lappend dqs_pins $ck_pin + } + foreach { ckn_pin } $pins(ckn_pins) { + lappend dqs_pins $ckn_pin + } + } + + return $dqs_pins +} + +proc ddr3_p0_dump_all_pins { ddr_db_par } { + upvar $ddr_db_par local_ddr_db + + set instnames [ array names local_ddr_db ] + + set filename "${::GLOBAL_ddr3_p0_corename}_all_pins.txt" + if [ catch { open $filename w 0777 } FH ] { + post_message -type error "Can't open file < $filename > for writing" + } + + post_message -type info "Dumping reference pin-map file: $filename" + + set script_name [ info script ] + puts $FH "# PIN MAP for core < $::GLOBAL_ddr3_p0_corename >" + puts $FH "#" + puts $FH "# Generated by ${::GLOBAL_ddr3_p0_corename}_pin_assignments.tcl" + puts $FH "#" + puts $FH "# This file is for reference only and is not used by Quartus Prime" + puts $FH "#" + puts $FH "" + + foreach instance $instnames { + array set pins $local_ddr_db($instance) + + puts $FH "INSTANCE: $instance" + puts $FH "DQS: $pins(dqs_pins)" + puts $FH "DQSn: $pins(dqsn_pins)" + puts $FH "DQ: $pins(q_groups)" + + puts $FH "DM $pins(dm_pins)" + + puts $FH "CK: $pins(ck_pins)" + puts $FH "CKn: $pins(ckn_pins)" + + puts $FH "ADD: $pins(add_pins)" + puts $FH "CMD: $pins(cmd_pins)" + puts $FH "RESET: $pins(reset_pins)" + puts $FH "BA: $pins(ba_pins)" + + puts $FH "REF CLK: $pins(pll_ref_clock)" + puts $FH "PLL AFI: $pins(pll_afi_clock)" + puts $FH "PLL CK: $pins(pll_ck_clock)" + puts $FH "PLL DQ WRITE: $pins(pll_dq_write_clock)" + puts $FH "PLL WRITE: $pins(pll_write_clock)" + puts $FH "PLL AVL: $pins(pll_avl_clock)" + puts $FH "PLL AVL PHY: $pins(pll_avl_phy_clock)" + puts $FH "PLL CONFIG: $pins(pll_config_clock)" + puts $FH "PLL DRIVER CORE: $pins(pll_driver_core_clock)" + + set i 0 + foreach dqs_in_clock_struct $pins(dqs_in_clocks) { + array set dqs_in_clock $dqs_in_clock_struct + puts $FH "DQS_IN_CLOCK DQS_PIN ($i): $dqs_in_clock(dqs_pin)" + puts $FH "DQS_IN_CLOCK DQS_SHIFTED_PIN ($i): $dqs_in_clock(dqs_shifted_pin)" + puts $FH "DQS_IN_CLOCK DIV_NAME ($i): $dqs_in_clock(div_name)" + puts $FH "DQS_IN_CLOCK DIV_PIN ($i): $dqs_in_clock(div_pin)" + + incr i + } + + set i 0 + foreach dqs_out_clock_struct $pins(dqs_out_clocks) { + array set dqs_out_clock $dqs_out_clock_struct + puts $FH "DQS_OUT_CLOCK SRC ($i): $dqs_out_clock(src)" + puts $FH "DQS_OUT_CLOCK DST ($i): $dqs_out_clock(dst)" + puts $FH "DQS_OUT_CLOCK DM ($i): $dqs_out_clock(dm_pin)" + + incr i + } + + set i 0 + foreach dqsn_out_clock_struct $pins(dqsn_out_clocks) { + array set dqsn_out_clock $dqsn_out_clock_struct + puts $FH "DQSN_OUT_CLOCK SRC ($i): $dqsn_out_clock(src)" + puts $FH "DQSN_OUT_CLOCK DST ($i): $dqsn_out_clock(dst)" + puts $FH "DQSN_OUT_CLOCK DM ($i): $dqsn_out_clock(dm_pin)" + + incr i + } + + puts $FH "READ CAPTURE DDIO: $pins(read_capture_ddio)" + puts $FH "AFI RESET REGISTERS: $pins(afi_reset_reg)" + puts $FH "SEQ RESET REGISTERS: $pins(seq_reset_reg)" + puts $FH "SYNCHRONIZERS: $pins(sync_reg)" + puts $FH "SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: $pins(fifo_wraddress_reg)" + puts $FH "SYNCHRONIZATION FIFO WRITE REGISTERS: $pins(fifo_wrdata_reg)" + puts $FH "SYNCHRONIZATION FIFO READ REGISTERS: $pins(fifo_rddata_reg)" + + puts $FH "" + puts $FH "#" + puts $FH "# END OF INSTANCE: $instance" + puts $FH "" + } + + close $FH +} +proc ddr3_p0_dump_static_pin_map { ddr_db_par filename } { + upvar $ddr_db_par local_ddr_db + + set instnames [ array names local_ddr_db ] + + if [ catch { open $filename w 0777 } FH ] { + post_message -type error "Can't open file < $filename > for writing" + } + + post_message -type info "Dumping static pin-map file: $filename" + + puts $FH "# AUTO-GENERATED static pin map for core < $::GLOBAL_ddr3_p0_corename >" + puts $FH "" + puts $FH "proc ${::GLOBAL_ddr3_p0_corename}_initialize_static_ddr_db { ddr_db_par } {" + puts $FH " upvar \$ddr_db_par local_ddr_db" + puts $FH "" + + foreach instname $instnames { + array set pins $local_ddr_db($instname) + + puts $FH " # Pin Mapping for instance: $instname" + + ddr3_p0_static_map_expand_list $FH pins dqs_pins + ddr3_p0_static_map_expand_list $FH pins dqsn_pins + + ddr3_p0_static_map_expand_list_of_list $FH pins q_groups + + puts $FH "" + puts $FH " set pins(all_dq_pins) \[ join \[ join \$pins(q_groups) \] \]" + + ddr3_p0_static_map_expand_list $FH pins dm_pins + + ddr3_p0_static_map_expand_list $FH pins ck_pins + ddr3_p0_static_map_expand_list $FH pins ckn_pins + + ddr3_p0_static_map_expand_list $FH pins add_pins + ddr3_p0_static_map_expand_list $FH pins cmd_pins + ddr3_p0_static_map_expand_list $FH pins reset_pins + ddr3_p0_static_map_expand_list $FH pins ba_pins + + puts $FH "" + puts $FH " set pins(ac_pins) \[ concat \$pins(add_pins) \$pins(ba_pins) \$pins(cmd_pins) \$pins(reset_pins)\]" + + ddr3_p0_static_map_expand_string $FH pins pll_ref_clock + ddr3_p0_static_map_expand_string $FH pins pll_afi_clock + ddr3_p0_static_map_expand_string $FH pins pll_ck_clock + ddr3_p0_static_map_expand_string $FH pins pll_dq_write_clock + ddr3_p0_static_map_expand_string $FH pins pll_write_clock + ddr3_p0_static_map_expand_string $FH pins pll_avl_clock + ddr3_p0_static_map_expand_string $FH pins pll_avl_phy_clock + ddr3_p0_static_map_expand_string $FH pins pll_config_clock + ddr3_p0_static_map_expand_string $FH pins pll_driver_core_clock + + puts $FH "" + puts $FH " set dqs_in_clocks \[ list \]" + set i 0 + foreach dqs_in_clock_struct $pins(dqs_in_clocks) { + array set dqs_in_clock $dqs_in_clock_struct + puts $FH " # DIV Clock ($i)" + puts $FH " set dqs_in_clock(dqs_pin) $dqs_in_clock(dqs_pin)" + puts $FH " set dqs_in_clock(dqs_shifted_pin) $dqs_in_clock(dqs_shifted_pin)" + puts $FH " set dqs_in_clock(div_name) $dqs_in_clock(div_name)" + puts $FH " set dqs_in_clock(div_pin) $dqs_in_clock(div_pin)" + + puts $FH " lappend dqs_in_clocks \[ array get dqs_in_clock \]" + + incr i + } + puts $FH " set pins(dqs_in_clocks) \$dqs_in_clocks" + + + puts $FH "" + puts $FH " set dqs_out_clocks \[ list \]" + set i 0 + foreach dqs_out_clock_struct $pins(dqs_out_clocks) { + array set dqs_out_clock $dqs_out_clock_struct + puts $FH " # DQS OUT Clock ($i)" + puts $FH " set dqs_out_clock(src) $dqs_out_clock(src)" + puts $FH " set dqs_out_clock(dst) $dqs_out_clock(dst)" + puts $FH " set dqs_out_clock(dm_pin) $dqs_out_clock(dm_pin)" + puts $FH " lappend dqs_out_clocks \[ array get dqs_out_clock \]" + + incr i + } + puts $FH " set pins(dqs_out_clocks) \$dqs_out_clocks" + + puts $FH "" + puts $FH " set dqsn_out_clocks \[ list \]" + set i 0 + foreach dqsn_out_clock_struct $pins(dqsn_out_clocks) { + array set dqsn_out_clock $dqsn_out_clock_struct + puts $FH " # DQSN OUT Clock ($i)" + puts $FH " set dqsn_out_clock(src) $dqsn_out_clock(src)" + puts $FH " set dqsn_out_clock(dst) $dqsn_out_clock(dst)" + puts $FH " set dqsn_out_clock(dm_pin) $dqsn_out_clock(dm_pin)" + puts $FH " lappend dqsn_out_clocks \[ array get dqsn_out_clock \]" + + incr i + } + puts $FH " set pins(dqsn_out_clocks) \$dqsn_out_clocks" + + ddr3_p0_static_map_expand_string $FH pins read_capture_ddio + ddr3_p0_static_map_expand_string $FH pins afi_reset_reg + ddr3_p0_static_map_expand_string $FH pins seq_reset_reg + ddr3_p0_static_map_expand_string $FH pins sync_reg + ddr3_p0_static_map_expand_string $FH pins fifo_wraddress_reg + ddr3_p0_static_map_expand_string $FH pins fifo_wrdata_reg + ddr3_p0_static_map_expand_string $FH pins fifo_rddata_reg + + puts $FH "" + puts $FH " set local_ddr_db($instname) \[ array get pins \]" + } + + puts $FH "}" + + close $FH +} diff --git a/ip/altera/ddr3/ddr3_p0_report_timing.tcl b/ip/altera/ddr3/ddr3_p0_report_timing.tcl new file mode 100644 index 0000000..81da1b2 --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_report_timing.tcl @@ -0,0 +1,473 @@ +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +#################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains the routines to generate the UniPHY memory +# interface timing report at the end of the compile flow. +# +# These routines are only meant to be used in this specific context. +# Trying to using them in a different context can have unexpected +# results. +############################################################# +# This report_timing script performs the timing analysis for +# all memory interfaces in the design. In particular, this +# script will loop over all memory interface cores and +# instances and will timing analyze a range of paths that +# are applicable for each instance. These include the +# timing analysis for the read capture, write, PHY +# address/command, and resynchronization paths among others. +# +# In performing the above timing analysis, the script +# calls procedures that are found in a separate file (report_timing_core.tcl) +# that has all the details of the timing analysis, and this +# file only serves as the top-level timing analysis flow. +# +# To reduce data lookups in all the procuedures that perform +# the individual timing analysis, data that is needed for +# multiple procedures is lookup up in this file and passed +# to the various parameters. These data include both values +# that are applicable over all operating conditions, and those +# that are applicable to only one operating condition. +# +# In addition to the data that is looked up, the script +# and the underlying procedures use various other data +# that are stored in TCL sets and include the following: +# +# t(.) : Holds the memory timing parameters +# board(.) : Holds the board skews and propagation delays +# SSN(.) : Holds the SSN pushout and pullin delays +# IP(.) : Holds the configuration of the memory interface +# that was generated +# ISI(.) : Holds any intersymbol interference when the +# memory interface is generated in a multirank +# topology +# MP(.) : Holds some process variation data for the memory +# See below for more information +# pins(.) : Holds the pin names for the memory interface +# +############################################################# + +set script_dir [file dirname [info script]] + +############################################################# +# Memory Specification Process Variation Information +############################################################# + +# The percentage of the JEDEC specification that is due +# to process variation + +set MP(DQSQ) 0.65 +set MP(QH_time) 0.55 +set MP(IS) 0.70 +set MP(IH) 0.6 +set MP(DS) 0.60 +set MP(DH) 0.50 +set MP(DSS) 0.60 +set MP(DSH) 0.60 +set MP(DQSS) 0.5 +set MP(WLH) 0.60 +set MP(WLS) 0.70 +set MP(DQSCK) 0.5 +set MP(DQSCK_T) 0.15 + +############################################################# +# Initialize the environment +############################################################# + +global quartus +if { ![info exists quartus(nameofexecutable)] || $quartus(nameofexecutable) != "quartus_sta" } { + post_message -type error "This script must be run from quartus_sta" + return 1 +} + +if { ! [ is_project_open ] } { + if { [ llength $quartus(args) ] > 0 } { + set project_name [lindex $quartus(args) 0] + project_open -revision [ get_current_revision $project_name ] $project_name + } else { + post_message -type error "Missing project_name argument" + return 1 + } +} + +############################################################# +# Some useful functions +############################################################# +source "$script_dir/ddr3_p0_timing.tcl" +source "$script_dir/ddr3_p0_pin_map.tcl" +source "$script_dir/ddr3_p0_report_timing_core.tcl" + +set family [get_family_string] +set family [string tolower $family] +if {$family == "arria ii gx"} { + set family "arria ii" +} +if {$family == "stratix iv gx"} { + set family "stratix iv" +} +if {$family == "stratix v gx"} { + set family "stratix v" +} +if {$family == "stratix v gt"} { + set family "stratix v" +} +if {$family == "hardcopy iv gx"} { + set family "hardcopy iv" +} + + +############################################################# +# Load the timing netlist +############################################################# + +if { ! [ timing_netlist_exist ] } { + create_timing_netlist +} + +set opcs [ list "" ] + +set signoff_mode $::quartus(ipc_mode) +if { [string match "*Analyzer GUI" [get_current_timequest_report_folder]]} { + read_sdc + update_timing_netlist + set script_dir [file dirname [info script]] + source "$script_dir/ddr3_p0_timing.tcl" + source "$script_dir/ddr3_p0_pin_map.tcl" + source "$script_dir/ddr3_p0_report_timing_core.tcl" +} + +load_package atoms +read_atom_netlist + +load_package report +load_report +if { ! [timing_netlist_exist] } { + post_message -type error "Timing Netlist has not been created. Run the 'Update Timing Netlist' task first." + return +} + +package require ::quartus::ioo +package require ::quartus::sin +initialize_ioo + +############################################################# +# This is the main timing analysis function +# It performs the timing analysis over all of the +# various Memory Interface instances and timing corners +############################################################# + +set mem_if_memtype "ddr3" + +if [ info exists ddr_db ] { + unset ddr_db +} + +############################################### +# This is the main call to the netlist traversal routines +# that will automatically find all pins and registers required +# to timing analyze the Core. +ddr3_p0_initialize_ddr_db ddr_db + +set old_active_clocks [get_active_clocks] +set_active_clocks [all_clocks] + +# If multiple instances of this core are present in the +# design they will all be analyzed through the +# following loop +set instances [ array names ddr_db ] +set inst_id 0 +foreach inst $instances { + if { [ info exists pins ] } { + # Clean-up stale content + unset pins + } + array set pins $ddr_db($inst) + + set inst_controller [regsub {p0$} $inst "c0"] + + #################################################### + # # + # Transfer the pin names to a more readable scheme # + # # + #################################################### + set dqs_pins $pins(dqs_pins) + set dqsn_pins $pins(dqsn_pins) + set q_groups [ list ] + foreach dq_group $pins(q_groups) { + set dq_group $dq_group + lappend q_groups $dq_group + } + set all_dq_pins [ join [ join $q_groups ] ] + + set ck_pins $pins(ck_pins) + set ckn_pins $pins(ckn_pins) + set add_pins $pins(add_pins) + set ba_pins $pins(ba_pins) + set cmd_pins $pins(cmd_pins) + set ac_pins [ concat $add_pins $ba_pins $cmd_pins ] + set dm_pins $pins(dm_pins) + set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ] + + + ################################################################################# + # Find some design values and parameters that will used during the timing analysis + # that do not change accross the operating conditions + set period $t(CK) + + # Get the number of PLL steps + set pll_steps "UNDEFINED" + + # Package skew + [catch {get_max_package_skew} max_package_skew] + if { ($max_package_skew == "") } { + set max_package_skew 0 + } else { + set max_package_skew [expr $max_package_skew / 1000.0] + } + + # DLL length + # Arria V DLL Length is always 8 + set dll_length 8 + + # DQS_phase offset + set dqs_phase [ ddr3_p0_get_dqs_phase $dqs_pins ] + + set fitter_run [ddr3_p0_get_io_interface_type [lindex [lindex $pins(q_groups) 0] 0]] + if {$fitter_run == ""} { + post_message -type critical_warning "Fitter (quartus_fit) failed or was not run. Run the Fitter (quartus_fit) successfully before running ReportDDR" + continue + } + + # Get the interface type (HPAD or VPAD) + set interface_type [ddr3_p0_get_io_interface_type $all_dq_pins] + + # Treat the VHPAD interface as the same as a HPAD interface + if {($interface_type == "VHPAD") || ($interface_type == "HYBRID")} { + set interface_type "HPAD" + } + + # Get the IO standard which helps us determine the Memory type + set io_std [ddr3_p0_get_io_standard [lindex $dqs_pins 0]] + + if {$interface_type == "" || $interface_type == "UNKNOWN" || $io_std == "" || $io_std == "UNKNOWN"} { + set result 0 + } + + # Get some of the FPGA jitter and DCD specs + # When not specified all jitter values are peak-to-peak jitters in ns + set tJITper [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -period $period]/1000.0] + set tJITdty [expr [get_micro_node_delay -micro MEM_CK_DC_JITTER -parameters [list IO PHY_SHORT]]/1000.0] + # DCD value that is looked up is in %, and thus needs to be divided by 100 + set tDCD [expr [get_micro_node_delay -micro MEM_CK_DCD -parameters [list IO PHY_SHORT]]/100.0] + # This is the peak-to-peak jitter on the whole DQ-DQS read capture path + set DQSpathjitter [expr [get_micro_node_delay -micro DQDQS_JITTER -parameters [list IO] -in_fitter]/1000.0] + # This is the proportion of the DQ-DQS read capture path jitter that applies to setup (looed up value is in %, and thus needs to be divided by 100) + set DQSpathjitter_setup_prop [expr [get_micro_node_delay -micro DQDQS_JITTER_DIVISION -parameters [list IO] -in_fitter]/100.0] + + set fname "" + set fbasename "" + if {[llength $instances] <= 1} { + set fbasename "${::GLOBAL_ddr3_p0_corename}" + } else { + set fbasename "${::GLOBAL_ddr3_p0_corename}_${inst_id}" + } + + set fname "${fbasename}_summary.csv" + + ################################################################################# + # Now loop the timing analysis over the various operating conditions + set summary [list] + foreach opc $opcs { + if {$opc != "" } { + set_operating_conditions $opc + update_timing_netlist + } + set opcname [get_operating_conditions_info [get_operating_conditions] -display_name] + set opcname [string trim $opcname] + + set model_corner [ddr3_p0_get_model_corner] + initialize_sin -model [lindex $model_corner 0] -corner [lindex $model_corner 1] + + global assumptions_cache + set in_gui [regexp "TimeQuest Timing Analyzer GUI" [get_current_timequest_report_folder]] + if {!$in_gui && [array exists assumptions_cache] && [info exists assumptions_cache(${::GLOBAL_ddr3_p0_corename}-$inst)] } { + set assumptions_valid $assumptions_cache(${::GLOBAL_ddr3_p0_corename}-$inst) + if {!$assumptions_valid} { + post_message -type critical_warning "Read Capture and Write timing analyses may not be valid due to violated timing model assumptions" + post_message -type critical_warning "See violated timing model assumptions in previous timing analysis above" + } + } else { + set assumptions_valid [ddr3_p0_verify_flexible_timing_assumptions $inst pins $mem_if_memtype] + set assumptions_cache(${::GLOBAL_ddr3_p0_corename}-$inst) $assumptions_valid + } + + ####################################### + # Determine parameters and values that are valid only for this operating condition + + set total_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {TOTAL_SCALE_FACTOR} -parameters {IO}] + set total_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {TOTAL_SCALE_FACTOR} -parameters {IO MIN}] + set scale_factors(total) [expr $total_max_scale_factor - $total_min_scale_factor] + + set odv_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {ODV_SCALE_FACTOR} -parameters {IO}] + set odv_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {ODV_SCALE_FACTOR} -parameters {IO MIN}] + set scale_factors(odv) [expr $odv_max_scale_factor - $odv_min_scale_factor] + + set eol_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {EOL_SCALE_FACTOR} -parameters {IO}] + set eol_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {EOL_SCALE_FACTOR} -parameters {IO MIN}] + set scale_factors(eol) [expr $eol_max_scale_factor - $eol_min_scale_factor] + + set emif_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {MEM_INTERFACE_SCALE_FACTOR} -parameters {IO}] + set emif_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {MEM_INTERFACE_SCALE_FACTOR} -parameters {IO MIN}] + set scale_factors(emif) [expr $emif_max_scale_factor - $emif_min_scale_factor] + + ####################################### + # Write Analysis + + ddr3_p0_perform_flexible_write_launch_timing_analysis $opcs $opcname $inst $family scale_factors $interface_type $max_package_skew $dll_length $period pins t summary MP IP board + + ####################################### + # Read Analysis + + ddr3_p0_perform_flexible_read_capture_timing_analysis $opcs $opcname $inst $family scale_factors $io_std $interface_type $max_package_skew $dqs_phase $period $all_dq_pins pins t summary MP IP board fpga + + ####################################### + # PHY and Address/command Analyses + + ddr3_p0_perform_ac_analyses $opcs $opcname $inst scale_factors pins t summary IP + ddr3_p0_perform_phy_analyses $opcs $opcname $inst $inst_controller pins t summary IP + + + ####################################### + # Bus Turnaround Time Analysis + ddr3_p0_perform_flexible_bus_turnaround_time_analysis $opcs $opcname $inst $family $period $dll_length $interface_type $tJITper $tJITdty $tDCD $pll_steps pins t summary MP IP SSN board ISI + + + ####################################### + # Postamble analysis + ddr3_p0_perform_flexible_postamble_timing_analysis $opcs $opcname $inst scale_factors $family $period $dll_length $interface_type $tJITper $tJITdty $tDCD $DQSpathjitter pins t summary MP IP SSN board ISI + + } + + ################################################# + # Now perform analysis of some of the calibrated paths that consider + # Worst-case conditions + + set opcname "All Conditions" + + ####################################### + # Print out the Summary Panel for this instance + + set summary [lsort -command ddr3_p0_sort_proc $summary] + + set f -1 + if { [ddr3_p0_get_operating_conditions_number] == 0 } { + set f [open $fname w] + + puts $f "Core: ${::GLOBAL_ddr3_p0_corename} - Instance: $inst" + puts $f "Path, Setup Margin, Hold Margin" + } else { + set f [open $fname a] + } + + + + + post_message -type info "Core: ${::GLOBAL_ddr3_p0_corename} - Instance: $inst" + post_message -type info " setup hold" + set panel_name "$inst" + set root_folder_name [get_current_timequest_report_folder] + if { ! [string match "${root_folder_name}*" $panel_name] } { + set panel_name "${root_folder_name}||$panel_name" + } + # Create the root if it doesn't yet exist + if {[get_report_panel_id $root_folder_name] == -1} { + set panel_id [create_report_panel -folder $root_folder_name] + } + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + # Create summary panel + set total_failures 0 + set rows [list] + lappend rows "add_row_to_table -id \$panel_id \[list \"Path\" \"Operating Condition\" \"Setup Slack\" \"Hold Slack\"\]" + foreach summary_line $summary { + foreach {corner order path su hold num_su num_hold} $summary_line { } + if {($num_su == 0) || ([string trim $su] == "")} { + set su "--" + } + if {($num_hold == 0) || ([string trim $hold] == "")} { + set hold "--" + } + + + if { ($su != "--" && $su < 0) || ($hold != "--" && $hold < 0) } { + incr total_failures + set type warning + set offset 50 + } else { + set type info + set offset 53 + } + if {$su != "--"} { + set su [ ddr3_p0_round_3dp $su] + } + if {$hold != "--"} { + set hold [ ddr3_p0_round_3dp $hold] + } + post_message -type $type [format "%-${offset}s | %6s %6s" $path $su $hold] + puts $f [format "\"%s\",%s,%s" $path $su $hold] + set fg_colours [list black black] + if { $su != "--" && $su < 0 } { + lappend fg_colours red + } else { + lappend fg_colours black + } + + if { $hold != "" && $hold < 0 } { + lappend fg_colours red + } else { + lappend fg_colours black + } + lappend rows "add_row_to_table -id \$panel_id -fcolors \"$fg_colours\" \[list \"$path\" \"$corner\" \"$su\" \"$hold\"\]" + } + close $f + if {$total_failures > 0} { + post_message -type critical_warning "DDR Timing requirements not met" + set panel_id [create_report_panel -table $panel_name -color red] + } else { + set panel_id [create_report_panel -table $panel_name] + } + foreach row $rows { + eval $row + } + + write_timing_report + + + incr inst_id +} + +set_active_clocks $old_active_clocks +uninitialize_sin +uninitialize_ioo diff --git a/ip/altera/ddr3/ddr3_p0_report_timing_core.tcl b/ip/altera/ddr3/ddr3_p0_report_timing_core.tcl new file mode 100644 index 0000000..80e9e3c --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_report_timing_core.tcl @@ -0,0 +1,1937 @@ +# (C) 2001-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +############################################################# +# Write Timing Analysis +############################################################# +proc ddr3_p0_perform_flexible_write_launch_timing_analysis {opcs opcname inst family scale_factors_name interface_type max_package_skew dll_length period pin_array_name timing_parameters_array_name summary_name MP_name IP_name board_name} { + + ############################################################################### + # This timing analysis covers the write timing constraints. It includes support + # for uncalibrated and calibrated write paths. The analysis starts by running a + # conventional timing analysis for the write paths and then adds support for + # topologies and IP options which are unique to source-synchronous data transfers. + # The support for further topologies includes common clock paths in DDR3 as well as + # correlation between D and K. The support for further IP includes support for + # write-deskew calibration. + # + # During write deskew calibration, the IP will adjust delay chain settings along + # each signal path to reduce the skew between D pins and to centre align the K + # clock within the DVW. This operation has the benefit of increasing margin on the + # setup and hold, as well as removing some of the unknown process variation on each + # signal path. This timing analysis emulates the IP process by deskewing each pin as + # well as accounting for the elimination of the unknown process variation. Once the + # deskew emulation is complete, the analysis further considers the effect of changing + # the delay chain settings to the operation of the device after calibration: these + # effects include changes in voltage and temperature which may affect the optimality + # of the deskew process. + # + # The timing analysis creates a write summary report indicating how the timing analysis + # was performed starting with a typical timing analysis before calibration. + ############################################################################### + + ####################################### + # Need access to global variables + upvar 1 $summary_name summary + upvar 1 $timing_parameters_array_name t + upvar 1 $pin_array_name pins + upvar 1 $MP_name MP + upvar 1 $IP_name IP + upvar 1 $board_name board + upvar 1 $scale_factors_name scale_factors + + set eol_reduction_factor $IP(eol_reduction_factor_write) + set num_failing_path $IP(num_report_paths) + + set debug 0 + set result 1 + + ################################# + # Find the clock output of the PLL + set ref_clock_input $pins(pll_ref_clock) + set msg_list [ list ] + set dqs_pll_clock_id [ddr3_p0_get_output_clock_id $pins(dqs_pins) "DQS output" msg_list] + if {$dqs_pll_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "$msg" + } + post_message -type warning "Failed to find PLL clock for pins [join $pins(dqs_pins)]" + set result 0 + } else { + set dqsclksource [get_node_info -name $dqs_pll_clock_id] + } + + set msg_list [ list ] + set dq_pll_clock_id [ddr3_p0_get_output_clock_id [ join [ join $pins(q_groups) ]] "DQ output" msg_list] + if {$dq_pll_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "$msg" + } + post_message -type warning "Failed to find PLL clock for pins [ join [ join $pins(q_groups) ]]" + set result 0 + } else { + set dqclksource [get_node_info -name $dq_pll_clock_id] + } + + foreach q_group $pins(q_groups) { + set q_group $q_group + lappend q_groups $q_group + } + set all_dq_pins [ join [ join $q_groups ] ] + set dm_pins $pins(dm_pins) + set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ] + + if {$IP(write_deskew_mode) == "dynamic"} { + set panel_name_setup "Before Calibration \u0028Negative slacks are OK\u0029||$inst Write \u0028Before Calibration\u0029 (setup)" + set panel_name_hold "Before Calibration \u0028Negative slacks are OK\u0029||$inst Write \u0028Before Calibration\u0029 (hold)" + } else { + set panel_name_setup "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Write (setup)" + set panel_name_hold "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Write (hold)" + } + + ##################################################################### + # Default Write Analysis + set before_calibration_reporting [get_ini_var -name "qsta_enable_before_calibration_ddr_reporting"] + if {![string equal -nocase $before_calibration_reporting off]} { + set res_0 [report_timing -detail full_path -to [get_ports $all_dq_dm_pins] \ + -npaths $num_failing_path -panel_name $panel_name_setup -setup -disable_panel_color -quiet] + set res_1 [report_timing -detail full_path -to [get_ports $all_dq_dm_pins] \ + -npaths $num_failing_path -panel_name $panel_name_hold -hold -disable_panel_color -quiet] + } + + # Perform the default timing analysis to get required and arrival times + set paths_setup [get_timing_paths -to [get_ports $all_dq_dm_pins] -npaths 400 -setup -nworst 1] + set paths_hold [get_timing_paths -to [get_ports $all_dq_dm_pins] -npaths 400 -hold -nworst 1] + + ##################################### + # Find Memory Calibration Improvement + ##################################### + + set mp_setup_slack 0 + set mp_hold_slack 0 + if {($IP(write_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} { + # Reduce the effect of tDS on the setup slack + set mp_setup_slack [expr $MP(DS)*$t(DS)] + + # Reduce the effect of tDH on the hold slack + set mp_hold_slack [expr $MP(DH)*$t(DH)] + } + set pll_clock $pins(pll_write_clock) + regsub {\|divclk$} $pll_clock "" pll_clock + set pll_max [ddr3_p0_min_in_collection [get_path -rise_from ${pll_clock}|vco*ph[0] -rise_to ${pll_clock}|divclk] "arrival_time"] + set pll_min [ddr3_p0_min_in_collection [get_path -rise_from ${pll_clock}|vco*ph[0] -rise_to ${pll_clock}|divclk -min_path] "arrival_time"] + set pll_ccpp [expr $pll_max - $pll_min] + + ######################################## + # Go over each pin and compute its slack + # Then include any effects that are unique + # to source synchronous designs including + # common clocks, signal correlation, and + # IP calibration options to compute the + # total slack of the instance + + set setup_slack 1000000000 + set hold_slack 1000000000 + set default_setup_slack 1000000000 + set default_hold_slack 1000000000 + + set max_write_deskew_setup [expr $IP(write_deskew_range_setup)*$IP(quantization_T9)] + set max_write_deskew_hold [expr $IP(write_deskew_range_hold)*$IP(quantization_T9)] + + if {($result == 1)} { + + # Go over each DQS pin + set group_number -1 + foreach dqpins $pins(q_groups) { + + set group_number [expr $group_number + 1] + + set dqspin [lindex $pins(dqs_pins) $group_number] + set dqsnpin [lindex $pins(dqsn_pins) $group_number] + set dmpins [lindex $pins(dm_pins) $group_number] + set dqdmpins $dqpins + if {[llength $dmpins] > 0} { + lappend dqdmpins $dmpins + } + + # Find DQS clock node before the periphery + set msg_list [list] + set leveling_delay_chain_name [ddr3_p0_traverse_to_leveling_delay_chain $dqspin msg_list] + + set dqs_periphery_node ${leveling_delay_chain_name}|clkin + + set cps_name [ddr3_p0_traverse_to_clock_phase_select $dqspin msg_list] + set dqs_clk_phase_select_node ${cps_name}|clkout + # Find paths from PLL to DQS clock periphery node + set DQSpaths_max [get_path -rise_from $dqsclksource -rise_to $dqs_clk_phase_select_node -nworst 1] + set DQSpaths_min [get_path -rise_from $dqsclksource -rise_to $dqs_clk_phase_select_node -nworst 1 -min_path] + set DQSmin_of_max [ddr3_p0_min_in_collection $DQSpaths_max "arrival_time"] + set DQSmax_of_min [ddr3_p0_max_in_collection $DQSpaths_min "arrival_time"] + set DQSmax_of_max [ddr3_p0_max_in_collection $DQSpaths_max "arrival_time"] + set DQSmin_of_min [ddr3_p0_min_in_collection $DQSpaths_min "arrival_time"] + + ############################################# + # Find extra DQS pessimism due to correlation (both spatial correlation and aging correlation) + ############################################# + + # Find paths from DQS clock periphery node to beginning of output buffer + set output_buffer_node ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*obuf*_0|i + set DQSperiphery_min [get_path -rise_from $dqs_clk_phase_select_node -rise_to $dqspin -min_path -nworst 1] + set DQSperiphery_max [get_path -rise_from $dqs_clk_phase_select_node -rise_to $dqspin -nworst 1] + set DQSperiphery_min_delay [ddr3_p0_min_in_collection $DQSperiphery_min "arrival_time"] + set DQSperiphery_max_delay [ddr3_p0_max_in_collection $DQSperiphery_max "arrival_time"] + set aiot_delay [ddr3_p0_round_3dp [expr [ddr3_p0_get_rise_aiot_delay $dqspin] * 1e9]] + set DQSperiphery_min_delay [expr $DQSperiphery_min_delay - $aiot_delay] + set DQSperiphery_max_delay [expr $DQSperiphery_max_delay - $aiot_delay] + set DQSpath_pessimism [expr $DQSperiphery_min_delay*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)] + + # Go over each DQ pin in group + set dq_index 0 + set dm_index 0 + + foreach dqpin $dqdmpins { + + if {[lsearch -exact $dmpins $dqpin] >= 0} { + set isdmpin 1 + regexp {\d+} $dqpin dm_pin_index + } else { + set isdmpin 0 + regexp {\d+} $dqpin dq_pin_index + } + + # Perform the default timing analysis to get required and arrival times + set pin_setup_slack [ddr3_p0_min_in_collection_to_name $paths_setup "slack" $dqpin] + set pin_hold_slack [ddr3_p0_min_in_collection_to_name $paths_hold "slack" $dqpin] + + set default_setup_slack [min $default_setup_slack $pin_setup_slack] + set default_hold_slack [min $default_hold_slack $pin_hold_slack] + + if { $debug } { + puts "$group_number $dqspin $dqpin $pin_setup_slack $pin_hold_slack" + } + + ############################### + # Extra common clock pessimism removal (from PLL) that is not caught by STA + ############################### + + # Find the DQ clock node before the periphery + set msg_list [list] + set leveling_delay_chain_name [ddr3_p0_traverse_to_leveling_delay_chain $dqpin msg_list] + + set dq_periphery_node ${leveling_delay_chain_name}|clkin + + set cps_name [ddr3_p0_traverse_to_clock_phase_select $dqpin msg_list] + set dq_clk_phase_select_node ${cps_name}|clkout + + # Find paths from PLL to DQ clock periphery node + set DQpaths_max [get_path -rise_from $dqclksource -rise_to $dq_clk_phase_select_node -nworst 1] + set DQpaths_min [get_path -rise_from $dqclksource -rise_to $dq_clk_phase_select_node -nworst 1 -min_path] + set DQmin_of_max [ddr3_p0_min_in_collection $DQpaths_max "arrival_time"] + set DQmax_of_min [ddr3_p0_max_in_collection $DQpaths_min "arrival_time"] + set DQmax_of_max [ddr3_p0_max_in_collection $DQpaths_max "arrival_time"] + set DQmin_of_min [ddr3_p0_min_in_collection $DQpaths_min "arrival_time"] + if {[expr abs(($DQSmax_of_min - $DQSmin_of_max) - ($DQmax_of_min - $DQmin_of_max))] < 0.05} { + set extra_ccpp_DQS [expr $DQSmin_of_max - $DQSmax_of_min] + set extra_ccpp_DQ [expr $DQmin_of_max - $DQmax_of_min] + set extra_ccpp [expr [min $extra_ccpp_DQS $extra_ccpp_DQ] + $pll_ccpp] + } else { + set extra_ccpp $pll_ccpp + } + + # Add the extra ccpp to both setup and hold slacks + set pin_setup_slack [expr $pin_setup_slack + $extra_ccpp] + set pin_hold_slack [expr $pin_hold_slack + $extra_ccpp] + + + ######################################## + # Add the memory calibration improvement + ######################################## + + set pin_setup_slack [expr $pin_setup_slack + $mp_setup_slack] + set pin_hold_slack [expr $pin_hold_slack + $mp_hold_slack] + + ############################################ + # Find extra DQ pessimism due to correlation + # (both spatial correlation and aging correlation) + ############################################ + + # Find the DQ clock node before the periphery + if {$isdmpin == 1} { + set output_buffer_node_dq ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*extra_output_pad_gen[0].obuf_1|i + } else { + set output_buffer_node_dq ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|pad_gen[${dq_index}].data_out|i + } + + set DQperiphery_min [get_path -rise_from $dq_clk_phase_select_node -rise_to $dqpin -min_path -nworst 1] + set DQperiphery_max [get_path -rise_from $dq_clk_phase_select_node -rise_to $dqpin -nworst 1] + + set DQperiphery_min_delay [ddr3_p0_min_in_collection $DQperiphery_min "arrival_time"] + set DQperiphery_max_delay [ddr3_p0_max_in_collection $DQperiphery_max "arrival_time"] + set aiot_delay [ddr3_p0_round_3dp [expr [ddr3_p0_get_rise_aiot_delay $dqpin] * 1e9]] + set DQperiphery_min_delay [expr $DQperiphery_min_delay - $aiot_delay] + set DQperiphery_max_delay [expr $DQperiphery_max_delay - $aiot_delay] + set DQpath_pessimism [expr $DQperiphery_min_delay*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)] + + ######################################## + # Merge current slacks with other slacks + ######################################## + + # If write deskew is available, the setup and hold slacks for this pin will be equal + # and can also remove the extra DQS and DQ pessimism removal + if {$IP(write_deskew_mode) == "dynamic"} { + + set extra_pessimism $IP(epw)*$DQperiphery_min_delay + + # Consider the maximum range of the deskew when deskewing + set shift_setup_slack [expr ($pin_setup_slack + $pin_hold_slack)/2 - $pin_setup_slack] + if {$shift_setup_slack >= $max_write_deskew_setup} { + if { $debug } { + puts "limited setup" + } + set pin_setup_slack [expr $pin_setup_slack + $max_write_deskew_setup + $extra_pessimism/2] + set pin_hold_slack [expr $pin_hold_slack - $max_write_deskew_setup + $extra_pessimism/2] + + # Remember the largest shifts in either direction + if {[info exist max_shift]} { + if {$max_write_deskew_setup > $max_shift} { + set max_shift $max_write_deskew_setup + } + if {$max_write_deskew_setup < $min_shift} { + set min_shift $max_write_deskew_setup + } + } else { + set max_shift $max_write_deskew_setup + set min_shift $max_shift + } + + } elseif {$shift_setup_slack <= -$max_write_deskew_hold} { + if { $debug } { + puts "limited hold" + } + set pin_setup_slack [expr $pin_setup_slack - $max_write_deskew_hold + $extra_pessimism/2] + set pin_hold_slack [expr $pin_hold_slack + $max_write_deskew_hold + $extra_pessimism/2] + + # Remember the largest shifts in either direction + if {[info exist max_shift]} { + if {[expr 0 -$max_write_deskew_hold] > $max_shift} { + set max_shift [expr 0 - $max_write_deskew_hold] + } + if {[expr 0 -$max_write_deskew_hold] < $min_shift} { + set min_shift [expr 0 - $max_write_deskew_hold] + } + } else { + set max_shift [expr 0 - $max_write_deskew_hold] + set min_shift $max_shift + } + } else { + # In this case we can also consider the DQS/DQpath pessimism since we can guarantee we have enough delay chain settings to align it + set pin_setup_slack [expr $pin_setup_slack + $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2] + set pin_hold_slack [expr $pin_hold_slack - $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2] + + # Remember the largest shifts in either direction + if {[info exist max_shift]} { + if {[expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] > $max_shift} { + set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] + } + if {[expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] < $min_shift} { + set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] + } + } else { + set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] + set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] + } + } + } else { + # For uncalibrated calls, there is some spatial correlation between DQ and DQS signals, so remove + # some of the pessimism + set total_DQ_DQS_pessimism [expr $DQSpath_pessimism + $DQpath_pessimism] + set dqs_width [llength $dqpins] + if {$dqs_width <= 9} { + set pin_setup_slack [expr $pin_setup_slack + 0.35*$total_DQ_DQS_pessimism] + set pin_hold_slack [expr $pin_hold_slack + 0.35*$total_DQ_DQS_pessimism] + } + } + + + set setup_slack [min $setup_slack $pin_setup_slack] + set hold_slack [min $hold_slack $pin_hold_slack] + + if { $debug } { + puts " $extra_ccpp $DQSpath_pessimism $DQpath_pessimism ($pin_setup_slack $pin_hold_slack $setup_slack $hold_slack)" + } + + if {$isdmpin == 0} { + set dq_index [expr $dq_index + 1] + } else { + set dm_index [expr $dm_index + 1] + } + } + } + } + + ############################### + # Consider some post calibration effects on calibration + # and output the write summary report + ############################### + set positive_fcolour [list "black" "blue" "blue"] + set negative_fcolour [list "black" "red" "red"] + + set wr_summary [list] + + if {$IP(write_deskew_mode) == "dynamic"} { + lappend wr_summary [list " Before Calibration Write" [ddr3_p0_format_3dp $default_setup_slack] [ddr3_p0_format_3dp $default_hold_slack]] + } else { + lappend wr_summary [list " Standard Write" [ddr3_p0_format_3dp $default_setup_slack] [ddr3_p0_format_3dp $default_hold_slack]] + } + + if {($IP(write_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} { + lappend wr_summary [list " Memory Calibration" [ddr3_p0_format_3dp $mp_setup_slack] [ddr3_p0_format_3dp $mp_hold_slack]] + } + + if {$IP(write_deskew_mode) == "dynamic"} { + if { $debug } { + puts " $setup_slack $hold_slack" + } + + ####################################### + # Find values for uncertainty table + set t(wru_fpga_deskew_s) [expr $setup_slack - $default_setup_slack - $extra_ccpp - $mp_setup_slack] + set t(wru_fpga_deskew_h) [expr $hold_slack - $default_hold_slack - $extra_ccpp - $mp_setup_slack] + ####################################### + + # Remove external delays (add slack) that are fixed by the dynamic deskew + if { $IP(discrete_device) == 1 } { + set t(WL_PSE) 0 + } + [catch {get_float_table_node_delay -src {DELAYCHAIN_T9} -dst {VTVARIATION} -parameters [list IO $interface_type]} t9_vt_variation_percent] + set extra_shift [expr $board(intra_DQS_group_skew) + [ddr3_p0_round_3dp [expr (1.0-$t9_vt_variation_percent)*$t(WL_PSE)]]] + + if {$extra_shift > [expr $max_write_deskew_setup - $max_shift]} { + set setup_slack [expr $setup_slack + $max_write_deskew_setup - $max_shift] + } else { + set setup_slack [expr $setup_slack + $extra_shift] + } + if {$extra_shift > [expr $max_write_deskew_hold + $min_shift]} { + set hold_slack [expr $hold_slack + $max_write_deskew_hold + $min_shift] + } else { + set hold_slack [expr $hold_slack + $extra_shift] + } + + if { $debug } { + puts " $setup_slack $hold_slack" + } + set deskew_setup [expr $setup_slack - $default_setup_slack -$mp_setup_slack] + set deskew_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack] + lappend wr_summary [list " Deskew Write and/or more clock pessimism removal" [ddr3_p0_format_3dp $deskew_setup] [ddr3_p0_format_3dp $deskew_hold]] + + ####################################### + # Find values for uncertainty table + set t(wru_external_deskew_s) [expr $deskew_setup - $t(wru_fpga_deskew_s) + $mp_setup_slack - $extra_ccpp] + set t(wru_external_deskew_h) [expr $deskew_hold - $t(wru_fpga_deskew_h) + $mp_hold_slack - $extra_ccpp] + ####################################### + + # Consider errors in the dynamic deskew + set t9_quantization $IP(quantization_T9) + set setup_slack [expr $setup_slack - $t9_quantization] + set hold_slack [expr $hold_slack - $t9_quantization] + if { $debug } { + puts " $setup_slack $hold_slack" + } + lappend wr_summary [list " Quantization error" [ddr3_p0_format_3dp [expr 0-$t9_quantization]] [ddr3_p0_format_3dp [expr 0-$t9_quantization]]] + + # Consider variation in the delay chains used during dynamic deksew + #This works out to 0 since the DLL length is 8 for AV/CV + set offset_from_90 0 + if {$IP(num_ranks) == 1} { + set t9_variation [expr [min [expr $offset_from_90 + [max [expr $MP(DS)*$t(DS)] [expr $MP(DH)*$t(DH)]] + (2*$board(intra_DQS_group_skew) + $max_package_skew + $t(WL_PSE))] [max $max_write_deskew_setup $max_write_deskew_hold]]*2*$t9_vt_variation_percent] + } else { + set t9_variation [expr [min [expr $offset_from_90 + (2*$board(intra_DQS_group_skew) + $max_package_skew + $t(WL_PSE))] [max $max_write_deskew_setup $max_write_deskew_hold]]*2*$t9_vt_variation_percent] + } + set setup_slack [expr $setup_slack - $t9_variation] + set hold_slack [expr $hold_slack - $t9_variation] + if { $debug } { + puts " $setup_slack $hold_slack" + } + lappend wr_summary [list " Calibration uncertainty" [ddr3_p0_format_3dp [expr 0-$t9_variation]] [ddr3_p0_format_3dp [expr 0-$t9_variation]]] + + ####################################### + # Find values for uncertainty table + set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"] + if {[string equal -nocase $uncertainty_reporting on]} { + set t(wru_calibration_uncertaintyerror_s) [expr 0 - $t9_variation - $t9_quantization] + set t(wru_calibration_uncertaintyerror_h) [expr 0 - $t9_variation - $t9_quantization] + set t(wru_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(wru_output_max_delay_external) - $extra_ccpp] + set t(wru_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(wru_output_min_delay_external) - $extra_ccpp] + set t(wru_extl_uncertainty_s) [expr $t(wru_output_max_delay_external)] + set t(wru_extl_uncertainty_h) [expr $t(wru_output_min_delay_external)] + } + ####################################### + + } else { + set pessimism_setup [expr $setup_slack - $default_setup_slack - $mp_setup_slack] + set pessimism_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack] + lappend wr_summary [list " Spatial correlation pessimism removal" [ddr3_p0_format_3dp $pessimism_setup] [ddr3_p0_format_3dp $pessimism_hold]] + + ####################################### + # Find values for uncertainty table + set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"] + if {[string equal -nocase $uncertainty_reporting on]} { + set t(wru_fpga_deskew_s) 0 + set t(wru_fpga_deskew_h) 0 + set t(wru_external_deskew_s) 0 + set t(wru_external_deskew_h) 0 + set t(wru_calibration_uncertaintyerror_s) 0 + set t(wru_calibration_uncertaintyerror_h) 0 + set t(wru_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(wru_output_max_delay_external) - $pessimism_setup] + set t(wru_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(wru_output_min_delay_external) - $pessimism_hold] + set t(wru_extl_uncertainty_s) [expr $t(wru_output_max_delay_external)] + set t(wru_extl_uncertainty_h) [expr $t(wru_output_min_delay_external)] + } + ####################################### + } + + ############################### + # Consider Duty Cycle Calibration if enabled + ############################### + + if {($IP(write_dcc) == "dynamic")} { + #First remove the Systematic DCD + set setup_slack [expr $setup_slack + $t(WL_DCD)] + set hold_slack [expr $hold_slack + $t(WL_DCD)] + if { $debug } { + puts " $setup_slack $hold_slack" + } + lappend wr_summary [list " Duty cycle correction" $t(WL_DCD) $t(WL_DCD)] + + #Add errors in the DCC + set DCC_quantization $IP(quantization_DCC) + set setup_slack [expr $setup_slack - $DCC_quantization] + set hold_slack [expr $hold_slack - $DCC_quantization] + if { $debug } { + puts " $setup_slack $hold_slack" + } + lappend wr_summary [list " Duty cycle correction quantization error" [ddr3_p0_format_3dp [expr 0-$DCC_quantization]] [ddr3_p0_format_3dp [expr 0-$DCC_quantization]]] + + # Consider variation in the DCC + [catch {get_float_table_node_delay -src {DELAYCHAIN_DUTY_CYCLE} -dst {VTVARIATION} -parameters [list IO $interface_type]} dcc_vt_variation_percent] + set dcc_variation [expr $t(WL_DCD)*2*$dcc_vt_variation_percent] + set setup_slack [expr $setup_slack - $dcc_variation] + set hold_slack [expr $hold_slack - $dcc_variation] + if { $debug } { + puts " $setup_slack $hold_slack" + } + lappend wr_summary [list " Duty cycle correction calibration uncertainity" [ddr3_p0_format_3dp [expr 0-$dcc_variation]] [ddr3_p0_format_3dp [expr 0-$dcc_variation]]] + } + + ####################################### + ####################################### + # Create the write analysis panel + set panel_name "$inst Write" + set root_folder_name [get_current_timequest_report_folder] + + if { ! [string match "${root_folder_name}*" $panel_name] } { + set panel_name "${root_folder_name}||$panel_name" + } + # Create the root if it doesn't yet exist + if {[get_report_panel_id $root_folder_name] == -1} { + set panel_id [create_report_panel -folder $root_folder_name] + } + + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + if {($setup_slack < 0) || ($hold_slack <0)} { + set panel_id [create_report_panel -table $panel_name -color red] + } else { + set panel_id [create_report_panel -table $panel_name] + } + add_row_to_table -id $panel_id [list "Operation" "Setup Slack" "Hold Slack"] + + if {($IP(write_deskew_mode) == "dynamic")} { + set fcolour [ddr3_p0_get_colours $setup_slack $hold_slack] + add_row_to_table -id $panel_id [list "After Calibration Write" [ddr3_p0_format_3dp $setup_slack] [ddr3_p0_format_3dp $hold_slack]] -fcolor $fcolour + lappend summary [list $opcname 0 "Write ($opcname)" $setup_slack $hold_slack] + } else { + set fcolour [ddr3_p0_get_colours $setup_slack $hold_slack] + add_row_to_table -id $panel_id [list "Write" [ddr3_p0_format_3dp $setup_slack] [ddr3_p0_format_3dp $hold_slack]] -fcolor $fcolour + lappend summary [list $opcname 0 "Write ($opcname)" [ddr3_p0_format_3dp $setup_slack] [ddr3_p0_format_3dp $hold_slack]] + } + + foreach summary_line $wr_summary { + add_row_to_table -id $panel_id $summary_line -fcolors $positive_fcolour + } + + ####################################### + # Create the Write uncertainty panel + set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"] + if {[string equal -nocase $uncertainty_reporting on]} { + set panel_name "$inst Write Uncertainty" + set root_folder_name [get_current_timequest_report_folder] + + if { ! [string match "${root_folder_name}*" $panel_name] } { + set panel_name "${root_folder_name}||$panel_name" + } + + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + set panel_id [create_report_panel -table $panel_name] + add_row_to_table -id $panel_id [list "Value" "Setup Side" "Hold Side"] + add_row_to_table -id $panel_id [list "Uncertainty" "" ""] + add_row_to_table -id $panel_id [list " FPGA uncertainty" [ddr3_p0_format_3dp $t(wru_fpga_uncertainty_s)] [ddr3_p0_format_3dp $t(wru_fpga_uncertainty_h)]] + add_row_to_table -id $panel_id [list " External uncertainty" [ddr3_p0_format_3dp $t(wru_extl_uncertainty_s)] [ddr3_p0_format_3dp $t(wru_extl_uncertainty_h)]] + add_row_to_table -id $panel_id [list "Deskew" "" ""] + add_row_to_table -id $panel_id [list " FPGA deskew" [ddr3_p0_format_3dp $t(wru_fpga_deskew_s)] [ddr3_p0_format_3dp $t(wru_fpga_deskew_h)]] + add_row_to_table -id $panel_id [list " External deskew" [ddr3_p0_format_3dp $t(wru_external_deskew_s)] [ddr3_p0_format_3dp $t(wru_external_deskew_h)]] + add_row_to_table -id $panel_id [list " Calibration uncertainty/error" [ddr3_p0_format_3dp $t(wru_calibration_uncertaintyerror_s)] [ddr3_p0_format_3dp $t(wru_calibration_uncertaintyerror_h)]] + } +} + + +############################################################# +# Read Timing Analysis +############################################################# +proc ddr3_p0_perform_flexible_read_capture_timing_analysis {opcs opcname inst family scale_factors_name io_std interface_type max_package_skew dqs_phase period all_dq_pins pin_array_name timing_parameters_array_name summary_name MP_name IP_name board_name fpga_name} { + + ################################################################################ + # This timing analysis covers the read timing constraints. It includes support + # for uncalibrated and calibrated read paths. The analysis starts by running a + # conventional timing analysis for the read paths and then adds support for + # topologies and IP options which are unique to source-synchronous data transfers. + # The support for further topologies includes correlation between DQ and DQS signals + # The support for further IP includes support for read-deskew calibration. + # + # During read deskew calibration, the IP will adjust delay chain settings along + # each signal path to reduce the skew between DQ pins and to centre align the DQ + # strobe within the DVW. This operation has the benefit of increasing margin on the + # setup and hold, as well as removing some of the unknown process variation on each + # signal path. This timing analysis emulates the IP process by deskewing each pin as + # well as accounting for the elimination of the unknown process variation. Once the + # deskew emulation is complete, the analysis further considers the effect of changing + # the delay chain settings to the operation of the device after calibration: these + # effects include changes in voltage and temperature which may affect the optimality + # of the deskew process. + # + # The timing analysis creates a read summary report indicating how the timing analysis + # was performed starting with a typical timing analysis before calibration. + ############################################################################### + + ####################################### + # Need access to global variables + upvar 1 $summary_name summary + upvar 1 $timing_parameters_array_name t + upvar 1 $pin_array_name pins + upvar 1 $MP_name MP + upvar 1 $IP_name IP + upvar 1 $board_name board + upvar 1 $fpga_name fpga + upvar 1 $scale_factors_name scale_factors + + set eol_reduction_factor $IP(eol_reduction_factor_read) + set num_failing_path $IP(num_report_paths) + + # Debug switch. Change to 1 to get more run-time debug information + set debug 0 + set result 1 + + foreach dqsclock $pins(dqs_pins) { + lappend dqs_pins_in ${dqsclock}_IN + } + + if {$IP(read_deskew_mode) == "dynamic"} { + set panel_name_setup "Before Calibration \u0028Negative slacks are OK\u0029||$inst Read Capture \u0028Before Calibration\u0029 (setup)" + set panel_name_hold "Before Calibration \u0028Negative slacks are OK\u0029||$inst Read Capture \u0028Before Calibration\u0029 (hold)" + } else { + set panel_name_setup "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Read Capture (setup)" + set panel_name_hold "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Read Capture (hold)" + } + + ##################################################################### + # Default Read Analysis + set before_calibration_reporting [get_ini_var -name "qsta_enable_before_calibration_ddr_reporting"] + if {![string equal -nocase $before_calibration_reporting off]} { + set res_0 [report_timing -detail full_path -from [get_ports $all_dq_pins] \ + -to_clock [get_clocks $dqs_pins_in] -npaths $num_failing_path -panel_name $panel_name_setup -setup -disable_panel_color -quiet] + set res_1 [report_timing -detail full_path -from [get_ports $all_dq_pins] \ + -to_clock [get_clocks $dqs_pins_in] -npaths $num_failing_path -panel_name $panel_name_hold -hold -disable_panel_color -quiet] + } + + set paths_setup [get_timing_paths -from [get_ports $all_dq_pins] -to_clock [get_clocks $dqs_pins_in] -npaths 400 -setup -nworst 1] + set paths_hold [get_timing_paths -from [get_ports $all_dq_pins] -to_clock [get_clocks $dqs_pins_in] -npaths 400 -hold -nworst 1] + + ##################################### + # Find Memory Calibration Improvement + ##################################### + + set mp_setup_slack 0 + set mp_hold_slack 0 + if {($IP(read_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} { + # Reduce the effect of tDQSQ on the setup slack + set mp_setup_slack [expr $MP(DQSQ)*$t(DQSQ)] + + # Reduce the effect of tQH_time on the hold slack + set mp_hold_slack [expr $MP(QH_time)*(0.5*$period-$t(QH_time))] + } + + ######################################## + # Go over each pin and compute its slack + # Then include any effects that are unique + # to source synchronous designs including + # common clocks, signal correlation, and + # IP calibration options to compute the + # total slack of the instance + + set prefix [ string map "| |*:" $inst ] + set prefix "*:$prefix" + # Get some of the FPGA jitter and DCD specs + # When not specified all jitter values are peak-to-peak jitters in ns + set tJITper [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -period $period]/1000.0] + set tJITdty [expr [get_micro_node_delay -micro MEM_CK_DC_JITTER -parameters [list IO PHY_SHORT]]/1000.0] + # DCD value that is looked up is in %, and thus needs to be divided by 100 + set tDCD [expr [get_micro_node_delay -micro MEM_CK_DCD -parameters [list IO PHY_SHORT]]/100.0] + + # This is the peak-to-peak jitter on the whole DQ-DQS read capture path + set DQSpathjitter [expr [get_micro_node_delay -micro DQDQS_JITTER -parameters [list IO] -in_fitter]/1000.0] + # This is the proportion of the DQ-DQS read capture path jitter that applies to setup (looed up value is in %, and thus needs to be divided by 100) + set DQSpathjitter_setup_prop [expr [get_micro_node_delay -micro DQDQS_JITTER_DIVISION -parameters [list IO] -in_fitter]/100.0] + # Phase Error on DQS paths. This parameter is queried at run time + set fpga(tDQS_PSERR) [ expr [ get_integer_node_delay -integer $::GLOBAL_ddr3_p0_dqs_delay_chain_length -parameters {IO MAX HIGH} -src DQS_PSERR -in_fitter ] / 1000.0 ] + + set setup_slack 1000000000 + set hold_slack 1000000000 + set default_setup_slack 1000000000 + set default_hold_slack 1000000000 + + # Find quiet jitter values during calibration + if {$family == "arria v"} { + set quiet_clk_jitter_proportion 0.25 + } else { + set quiet_clk_jitter_proportion 0.5 + } + set quiet_setup_jitter [expr 0.8*$DQSpathjitter*$DQSpathjitter_setup_prop] + set quiet_hold_jitter [expr 0.8*$DQSpathjitter*(1-$DQSpathjitter_setup_prop) + $quiet_clk_jitter_proportion*$tJITper/2] + set max_read_deskew_setup [expr $IP(read_deskew_range_setup)*$IP(quantization_T1)] + set max_read_deskew_hold [expr $IP(read_deskew_range_hold)*$IP(quantization_T1)] + + if {($result == 1)} { + + # Go over each DQS pin + set group_number -1 + foreach qpins $pins(q_groups) { + + set group_number [expr $group_number + 1] + + set dqspin [lindex $pins(dqs_pins) $group_number] + set dqsnpin [lindex $pins(dqsn_pins) $group_number] + + ############################################# + # Find extra DQS pessimism due to correlation + # (both spatial correlation and aging correlation) + ############################################# + + # Find paths from output of the input buffer to the end of the DQS periphery + set input_buffer_node "${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*strobe_in|o" + set DQScapture_node [list "${prefix}*dq_ddio[${group_number}].ubidir_dq_dqs|*altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO" ] + + set DQSperiphery_min [get_path -rise_from $input_buffer_node -rise_to $DQScapture_node -min_path -nworst 1] + set DQSperiphery_max [get_path -rise_from $input_buffer_node -rise_to $DQScapture_node -nworst 1] + set DQSperiphery_min_delay [ddr3_p0_min_in_collection $DQSperiphery_min "arrival_time"] + set DQSperiphery_max_delay [ddr3_p0_max_in_collection $DQSperiphery_max "arrival_time"] + set DQSpath_pessimism [expr ($DQSperiphery_min_delay - 90.0/360*$t(CK))*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)] + + # Go over each DQ pin in group + set q_index 0 + foreach qpin $qpins { + regexp {\d+} $qpin q_pin_index + + # Perform the default timing analysis to get required and arrival times + set pin_setup_slack [ddr3_p0_min_in_collection_from_name $paths_setup "slack" $qpin] + set pin_hold_slack [ddr3_p0_min_in_collection_from_name $paths_hold "slack" $qpin] + + set default_setup_slack [min $default_setup_slack $pin_setup_slack] + set default_hold_slack [min $default_hold_slack $pin_hold_slack] + + if { $debug } { + puts "READ: $group_number $dqspin $qpin $pin_setup_slack $pin_hold_slack (MP: $mp_setup_slack $mp_hold_slack)" + } + + ############################### + # Add the memory calibration improvement + ############################### + + set pin_setup_slack [expr $pin_setup_slack + $mp_setup_slack] + set pin_hold_slack [expr $pin_hold_slack + $mp_hold_slack] + + ############################################ + # Find extra DQ pessimism due to correlation + ############################################ + + # Find paths from output of the input buffer to the end of the DQ periphery + set input_buffer_node_dq ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*pad_gen[${q_index}].data_in|o + set DQcapture_node [list "${prefix}*dq_ddio[${group_number}].ubidir_dq_dqs|*altdq_dqs2_inst|*input_path_gen[${q_index}].capture_reg~DFFLO" ] + + set DQperiphery_min [get_path -rise_from $input_buffer_node_dq -rise_to $DQScapture_node -min_path -nworst 1] + set DQperiphery_max [get_path -rise_from $input_buffer_node_dq -rise_to $DQScapture_node -nworst 1] + set DQperiphery_min_delay [ddr3_p0_min_in_collection $DQperiphery_min "arrival_time"] + set DQperiphery_max_delay [ddr3_p0_max_in_collection $DQperiphery_max "arrival_time"] + set DQpath_pessimism [expr $DQperiphery_min_delay*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)] + + ######################################## + # Merge current slacks with other slacks + ######################################## + + # If read deskew is available, the setup and hold slacks for this pin will be equal + # and can also remove the extra DQS pessimism removal + if {$IP(read_deskew_mode) == "dynamic"} { + + set extra_pessimism $IP(epr)*$DQperiphery_min_delay + + # Consider the maximum range of the deskew when deskewing + set shift_setup_slack [expr (($pin_setup_slack + $quiet_setup_jitter) + ($pin_hold_slack + $quiet_hold_jitter))/2 - $pin_setup_slack - $quiet_setup_jitter] + if {$shift_setup_slack >= $max_read_deskew_setup} { + if { $debug } { + puts "limited setup" + } + set pin_setup_slack [expr $pin_setup_slack + $max_read_deskew_setup + $extra_pessimism/2] + set pin_hold_slack [expr $pin_hold_slack - $max_read_deskew_setup + $extra_pessimism/2] + + # Remember the largest shifts in either direction + if {[info exist max_shift]} { + if {$max_read_deskew_setup > $max_shift} { + set max_shift $max_read_deskew_setup + } + if {$max_read_deskew_setup < $min_shift} { + set min_shift $max_read_deskew_setup + } + } else { + set max_shift $max_read_deskew_setup + set min_shift $max_shift + } + + } elseif {$shift_setup_slack <= -$max_read_deskew_hold} { + if { $debug } { + puts "limited hold" + } + set pin_setup_slack [expr $pin_setup_slack - $max_read_deskew_hold + $extra_pessimism/2] + set pin_hold_slack [expr $pin_hold_slack + $max_read_deskew_hold + $extra_pessimism/2] + + # Remember the largest shifts in either direction + if {[info exist max_shift]} { + if {[expr 0 -$max_read_deskew_hold] > $max_shift} { + set max_shift [expr 0 - $max_read_deskew_hold] + } + if {[expr 0 -$max_read_deskew_hold] < $min_shift} { + set min_shift [expr 0 - $max_read_deskew_hold] + } + } else { + set max_shift [expr 0 - $max_read_deskew_hold] + set min_shift $max_shift + } + } else { + # In this case we can also consider the DQS path pessimism since we can guarantee we have enough delay chain settings to align it + set pin_setup_slack [expr $pin_setup_slack + $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2] + set pin_hold_slack [expr $pin_hold_slack - $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2] + + # Remember the largest shifts in either direction + if {[info exist max_shift]} { + if {[expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] > $max_shift} { + set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] + } + if {[expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] < $min_shift} { + set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] + } + } else { + set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] + set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] + } + } + } else { + # For uncalibrated calls, there is some spatial correlation between DQ and DQS signals, so remove + # some of the pessimism + set total_DQ_DQS_pessimism [expr $DQSpath_pessimism + $DQpath_pessimism] + set dqs_width [llength $qpins] + if {$dqs_width <= 9} { + set pin_setup_slack [expr $pin_setup_slack + 0.35*$total_DQ_DQS_pessimism] + set pin_hold_slack [expr $pin_hold_slack + 0.35*$total_DQ_DQS_pessimism] + } + } + + set setup_slack [min $setup_slack $pin_setup_slack] + set hold_slack [min $hold_slack $pin_hold_slack] + + if { $debug } { + puts "READ: $DQSpath_pessimism $DQpath_pessimism ($pin_setup_slack $pin_hold_slack $setup_slack $hold_slack)" + } + set q_index [expr $q_index + 1] + } + } + } + + ######################################################## + # Consider some post calibration effects on calibration + # and output the read summary report + ######################################################## + + set positive_fcolour [list "black" "blue" "blue"] + set negative_fcolour [list "black" "red" "red"] + + set rc_summary [list] + + set fcolour [ddr3_p0_get_colours $default_setup_slack $default_hold_slack] + if {$IP(read_deskew_mode) == "dynamic"} { + lappend rc_summary [list " Before Calibration Read Capture" [ddr3_p0_format_3dp $default_setup_slack] [ddr3_p0_format_3dp $default_hold_slack]] + } else { + lappend rc_summary [list " Standard Read Capture" [ddr3_p0_format_3dp $default_setup_slack] [ddr3_p0_format_3dp $default_hold_slack]] + } + + if {($IP(read_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} { + lappend rc_summary [list " Memory Calibration" [ddr3_p0_format_3dp $mp_setup_slack] [ddr3_p0_format_3dp $mp_hold_slack]] + } + + if {$IP(read_deskew_mode) == "dynamic"} { + if { $debug } { + puts " $setup_slack $hold_slack" + } + + ####################################### + # Find values for uncertainty table + set t(rdu_fpga_deskew_s) [expr $setup_slack - $default_setup_slack - $mp_setup_slack] + set t(rdu_fpga_deskew_h) [expr $hold_slack - $default_hold_slack - $mp_hold_slack] + ####################################### + + # Remove external delays (add slack) that are fixed by the dynamic deskew + [catch {get_float_table_node_delay -src {DELAYCHAIN_T1} -dst {VTVARIATION} -parameters [list IO $interface_type]} t1_vt_variation_percent] + set extra_shift [expr $board(intra_DQS_group_skew) + [ddr3_p0_round_3dp [expr (1.0-$t1_vt_variation_percent)*$fpga(tDQS_PSERR)]]] + + if {$extra_shift > [expr $max_read_deskew_setup - $max_shift]} { + set setup_slack [expr $setup_slack + $max_read_deskew_setup - $max_shift] + } else { + set setup_slack [expr $setup_slack + $extra_shift] + } + if {$extra_shift > [expr $max_read_deskew_hold + $min_shift]} { + set hold_slack [expr $hold_slack + $max_read_deskew_hold + $min_shift] + } else { + set hold_slack [expr $hold_slack + $extra_shift] + } + + if { $debug } { + puts " $setup_slack $hold_slack" + } + set deskew_setup [expr $setup_slack - $default_setup_slack - $mp_setup_slack] + set deskew_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack] + lappend rc_summary [list " Deskew Read" [ddr3_p0_format_3dp $deskew_setup] [ddr3_p0_format_3dp $deskew_hold]] + + ####################################### + # Find values for uncertainty table + set t(rdu_external_deskew_s) [expr $deskew_setup - $t(rdu_fpga_deskew_s) + $mp_setup_slack] + set t(rdu_external_deskew_h) [expr $deskew_hold - $t(rdu_fpga_deskew_h) + $mp_hold_slack] + ####################################### + + # Consider errors in the dynamic deskew + set t1_quantization $IP(quantization_T1) + set setup_slack [expr $setup_slack - $t1_quantization] + set hold_slack [expr $hold_slack - $t1_quantization] + if { $debug } { + puts " $setup_slack $hold_slack" + } + lappend rc_summary [list " Quantization error" [ddr3_p0_format_3dp [expr 0-$t1_quantization]] [ddr3_p0_format_3dp [expr 0-$t1_quantization]]] + + # Consider variation in the delay chains used during dynamic deksew + set dqs_period [ ddr3_p0_get_dqs_period $pins(dqs_pins) ] + set offset_from_90 [ddr3_p0_get_acv_read_offset $period $dqs_phase $dqs_period] + if {$IP(num_ranks) == 1} { + set t1_variation [expr [min [expr $offset_from_90 + [max [expr $MP(DQSQ)*$t(DQSQ)] [expr $MP(QH_time)*(0.5*$period - $t(QH_time))]] + 2*$board(intra_DQS_group_skew) + $max_package_skew + $fpga(tDQS_PSERR)] [max $max_read_deskew_setup $max_read_deskew_hold]]*2*$t1_vt_variation_percent*0.75] + } else { + set t1_variation [expr [min [expr $offset_from_90 + 2*$board(intra_DQS_group_skew) + $max_package_skew + $fpga(tDQS_PSERR)] [max $max_read_deskew_setup $max_read_deskew_hold]]*2*$t1_vt_variation_percent*0.75] + } + if {($dqs_period < 1.250) && ($family == "arria v")} { + set speedgrade [string trim [string range [get_speedgrade_string] 0 0]] + if {$speedgrade == 6} { + set further_dqs_pserr 0.025 + set t1_variation [expr $t1_variation + $further_dqs_pserr] + } + } + set setup_slack [expr $setup_slack - $t1_variation] + set hold_slack [expr $hold_slack - $t1_variation] + if { $debug } { + puts " $setup_slack $hold_slack" + } + lappend rc_summary [list " Calibration uncertainty" [ddr3_p0_format_3dp [expr 0-$t1_variation]] [ddr3_p0_format_3dp [expr 0-$t1_variation]]] + + ####################################### + # Find values for uncertainty table + set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"] + if {[string equal -nocase $uncertainty_reporting on]} { + set t(rdu_calibration_uncertaintyerror_s) [expr 0 - $t1_variation - $t1_quantization] + set t(rdu_calibration_uncertaintyerror_h) [expr 0 - $t1_variation - $t1_quantization] + set t(rdu_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(rdu_input_max_delay_external)] + set t(rdu_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(rdu_input_min_delay_external)] + set t(rdu_extl_uncertainty_s) [expr $t(rdu_input_max_delay_external)] + set t(rdu_extl_uncertainty_h) [expr $t(rdu_input_min_delay_external)] + } + ####################################### + + } else { + set pessimism_setup [expr $setup_slack - $default_setup_slack - $mp_setup_slack] + set pessimism_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack] + lappend rc_summary [list " Spatial correlation pessimism removal" [ddr3_p0_format_3dp $pessimism_setup] [ddr3_p0_format_3dp $pessimism_hold]] + + ####################################### + # Find values for uncertainty table + set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"] + if {[string equal -nocase $uncertainty_reporting on]} { + set t(rdu_fpga_deskew_s) 0 + set t(rdu_fpga_deskew_h) 0 + set t(rdu_external_deskew_s) 0 + set t(rdu_external_deskew_h) 0 + set t(rdu_calibration_uncertaintyerror_s) 0 + set t(rdu_calibration_uncertaintyerror_h) 0 + set t(rdu_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(rdu_input_max_delay_external) - $pessimism_setup] + set t(rdu_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(rdu_input_min_delay_external) - $pessimism_hold] + set t(rdu_extl_uncertainty_s) [expr $t(rdu_input_max_delay_external)] + set t(rdu_extl_uncertainty_h) [expr $t(rdu_input_min_delay_external)] + } + ####################################### + } + + ####################################### + # Create the read analysis panel + set panel_name "$inst Read Capture" + set root_folder_name [get_current_timequest_report_folder] + + if { ! [string match "${root_folder_name}*" $panel_name] } { + set panel_name "${root_folder_name}||$panel_name" + } + # Create the root if it doesn't yet exist + if {[get_report_panel_id $root_folder_name] == -1} { + set panel_id [create_report_panel -folder $root_folder_name] + } + + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + if {($setup_slack < 0) || ($hold_slack <0)} { + set panel_id [create_report_panel -table $panel_name -color red] + } else { + set panel_id [create_report_panel -table $panel_name] + } + add_row_to_table -id $panel_id [list "Operation" "Setup Slack" "Hold Slack"] + + if {$IP(read_deskew_mode) == "dynamic"} { + set fcolour [ddr3_p0_get_colours $setup_slack $hold_slack] + add_row_to_table -id $panel_id [list "After Calibration Read Capture" [ddr3_p0_format_3dp $setup_slack] [ddr3_p0_format_3dp $hold_slack]] -fcolor $fcolour + lappend summary [list $opcname 0 "Read Capture ($opcname)" $setup_slack $hold_slack] + } else { + set fcolour [ddr3_p0_get_colours $setup_slack $hold_slack] + add_row_to_table -id $panel_id [list "Read Capture" [ddr3_p0_format_3dp $setup_slack] [ddr3_p0_format_3dp $hold_slack]] -fcolor $fcolour + lappend summary [list $opcname 0 "Read Capture ($opcname)" $setup_slack $hold_slack] + } + + foreach summary_line $rc_summary { + add_row_to_table -id $panel_id $summary_line -fcolors $positive_fcolour + } + + ####################################### + # Create the Read uncertainty panel + set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"] + if {[string equal -nocase $uncertainty_reporting on]} { + set panel_name "$inst Read Capture Uncertainty" + set root_folder_name [get_current_timequest_report_folder] + + if { ! [string match "${root_folder_name}*" $panel_name] } { + set panel_name "${root_folder_name}||$panel_name" + } + + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + set panel_id [create_report_panel -table $panel_name] + add_row_to_table -id $panel_id [list "Value" "Setup Side" "Hold Side"] + add_row_to_table -id $panel_id [list "Uncertainty" "" ""] + add_row_to_table -id $panel_id [list " FPGA uncertainty" [ddr3_p0_format_3dp $t(rdu_fpga_uncertainty_s)] [ddr3_p0_format_3dp $t(rdu_fpga_uncertainty_h)]] + add_row_to_table -id $panel_id [list " External uncertainty" [ddr3_p0_format_3dp $t(rdu_extl_uncertainty_s)] [ddr3_p0_format_3dp $t(rdu_extl_uncertainty_h)]] + add_row_to_table -id $panel_id [list "Deskew" "" ""] + add_row_to_table -id $panel_id [list " FPGA deskew" [ddr3_p0_format_3dp $t(rdu_fpga_deskew_s)] [ddr3_p0_format_3dp $t(rdu_fpga_deskew_h)]] + add_row_to_table -id $panel_id [list " External deskew" [ddr3_p0_format_3dp $t(rdu_external_deskew_s)] [ddr3_p0_format_3dp $t(rdu_external_deskew_h)]] + add_row_to_table -id $panel_id [list " Calibration uncertainty/error" [ddr3_p0_format_3dp $t(rdu_calibration_uncertaintyerror_s)] [ddr3_p0_format_3dp $t(rdu_calibration_uncertaintyerror_h)]] + } +} + +############################################################# +# Other Timing Analysis +############################################################# + +proc ddr3_p0_perform_phy_analyses {opcs opcname inst inst_controller pin_array_name timing_parameters_array_name summary_name IP_name} { + + ############################################################################### + # The PHY analysis concerns the timing requirements of the PHY which includes + # soft registers in the FPGA core as well as some registers in the hard periphery + # The read capture and write registers are not analyzed here, even though they + # are part of the PHY since they are timing analyzed separately. + ############################################################################### + + ####################################### + # Need access to global variables + upvar 1 $summary_name summary + upvar 1 $timing_parameters_array_name t + upvar 1 $pin_array_name pins + upvar 1 $IP_name IP + + set num_failing_path $IP(num_report_paths) + + set entity_names_on [ ddr3_p0_are_entity_names_on ] + + set prefix [ string map "| |*:" $inst ] + set prefix "*:$prefix" + set prefix_controller [ string map "| |*:" $inst_controller ] + set prefix_controller "*:$prefix_controller" + + if { ! $entity_names_on } { + set core_regs [remove_from_collection [get_registers $inst|*] [get_registers $pins(read_capture_ddio)]] + } else { + set core_regs [remove_from_collection [get_registers $prefix|*] [get_registers $pins(read_capture_ddio)]] + } + + # Core + set res_0 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core (setup)" -setup] + set res_1 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core (hold)" -hold] + lappend summary [list $opcname 0 "Core ($opcname)" [lindex $res_0 1] [lindex $res_1 1] [lindex $res_0 0] [lindex $res_1 0]] + + # Core Recovery/Removal + set res_0 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core Recovery/Removal (recovery)" -recovery] + set res_1 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core Recovery/Removal (removal)" -removal] + lappend summary [list $opcname 0 "Core Recovery/Removal ($opcname)" [lindex $res_0 1] [lindex $res_1 1] [lindex $res_0 0] [lindex $res_1 0]] + + +} + +proc ddr3_p0_perform_ac_analyses {opcs opcname inst scale_factors_name pin_array_name timing_parameters_array_name summary_name IP_name} { + + ############################################################################### + # The adress/command analysis concerns the timing requirements of the pins (other + # than the D/Q pins) which go to the memory device/DIMM. These include address/command + # pins, some of which are runing at Single-Data-Rate (SDR) and some which are + # running at Half-Data-Rate (HDR). + ############################################################################### + + ####################################### + # Need access to global variables + upvar 1 $summary_name summary + upvar 1 $timing_parameters_array_name t + upvar 1 $pin_array_name pins + upvar 1 $IP_name IP + upvar 1 $scale_factors_name scale_factors + set eol_reduction_factor $IP(eol_reduction_factor_addr) + + set num_failing_path $IP(num_report_paths) + + set add_pins $pins(add_pins) + set ba_pins $pins(ba_pins) + set cmd_pins $pins(cmd_pins) + set reset_pins $pins(reset_pins) + set ac_pins [ concat $add_pins $ba_pins $cmd_pins ] + + set entity_names_on [ ddr3_p0_are_entity_names_on ] + + set prefix [ string map "| |*:" $inst ] + set prefix "*:$prefix" + + set panel_name_setup "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Address Command (setup)" + set panel_name_hold "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Address Command (hold)" + + set panel_name_dqs_setup "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst DQS vs CK (setup)" + set panel_name_dqs_hold "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst DQS vs CK (hold)" + + ###################################################################### + ##Default Address Command Analysis + set res_0 [report_timing -detail full_path -to $ac_pins \ + -npaths $num_failing_path -panel_name $panel_name_setup -setup -disable_panel_color -quiet] + set res_1 [report_timing -detail full_path -to $ac_pins \ + -npaths $num_failing_path -panel_name $panel_name_hold -hold -disable_panel_color -quiet] + set default_setup_slack [lindex $res_0 1] + set default_hold_slack [lindex $res_1 1] + + # Perform the default A/C timing analysis to get required and arrival times + set paths_setup [get_timing_paths -to [get_ports $ac_pins] -npaths 400 -setup -nworst 1] + set paths_hold [get_timing_paths -to [get_ports $ac_pins] -npaths 400 -hold -nworst 1] + + ###################################################################### + ##Default DQS vs CK Analysis + set dqs_res_0 [report_timing -detail full_path -to [get_ports $pins(dqs_pins)] -npaths $num_failing_path -panel_name $panel_name_dqs_setup -setup -disable_panel_color -quiet] + set dqs_res_1 [report_timing -detail full_path -to [get_ports $pins(dqs_pins)] -npaths $num_failing_path -panel_name $panel_name_dqs_hold -hold -disable_panel_color -quiet] + set default_dqs_setup_slack [lindex $dqs_res_0 1] + set default_dqs_hold_slack [lindex $dqs_res_1 1] + + # Perform the default DQS vs CK timing analysis to get required and arrival times + set dqs_paths_setup [get_timing_paths -to [get_ports $pins(dqs_pins)] -npaths 400 -setup -nworst 1] + set dqs_paths_hold [get_timing_paths -to [get_ports $pins(dqs_pins)] -npaths 400 -hold -nworst 1] + + ###################################################################### + ##Find portions of common clock pessimism removal + + # Some regular expression matching to create the right strings + set pll_clock $pins(pll_write_clock) + + set ck_periphery_nodes [list] + foreach ck_pin $pins(ck_pins) { + set clk_clk_phase_select_node [ddr3_p0_traverse_to_clock_phase_select $ck_pin msg_list] + set clk_periphery_node ${clk_clk_phase_select_node}|clkout + lappend clk_periphery_nodes $clk_periphery_node + } + set clk_periphery_nodes [lsort -unique $clk_periphery_nodes] + set clk_max [ddr3_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $clk_periphery_nodes] "arrival_time"] + if {$clk_max <= 0} {set clk_max -9999} + set clk_min [ddr3_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $clk_periphery_nodes -min_path] "arrival_time"] + if {$clk_min <= 0} {set clk_min 9999} + + set CKperiphery_min [get_path -rise_from $clk_periphery_nodes -rise_to $pins(ck_pins) -min_path -nworst 1] + set CKperiphery_max [get_path -rise_from $clk_periphery_nodes -rise_to $pins(ck_pins) -nworst 1] + set CKperiphery_min_delay [ddr3_p0_min_in_collection $CKperiphery_min "arrival_time"] + set CKperiphery_max_delay [ddr3_p0_max_in_collection $CKperiphery_max "arrival_time"] + set aiot_delay [ddr3_p0_round_3dp [expr [ddr3_p0_get_rise_aiot_delay [lindex $pins(ck_pins) 0]] * 1e9]] + set CKperiphery_min_delay [expr $CKperiphery_min_delay - $aiot_delay] + set CKperiphery_max_delay [expr $CKperiphery_max_delay - $aiot_delay] + set CKpath_pessimism [expr $CKperiphery_min_delay*($scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor) + + ($CKperiphery_max_delay - $CKperiphery_min_delay)/2] + + ###################################################################### + ##Loop over AC pins, and perform analysis + + set pll_clock $pins(pll_write_clock) + # The A/C CPS is set to inversion mode, so we require a RF path + set rise_or_fall_to "fall_to" + + set setup_slack 1000000000 + set hold_slack 1000000000 + foreach ac_pin $ac_pins { + + set pin_setup_slack [ddr3_p0_min_in_collection_to_name $paths_setup "slack" $ac_pin] + set pin_hold_slack [ddr3_p0_min_in_collection_to_name $paths_hold "slack" $ac_pin] + set current_ccpr [ddr3_p0_min_in_collection_to_name $paths_hold "ccpp" $ac_pin] + + set ac_clk_phase_select_node [ddr3_p0_traverse_to_clock_phase_select $ac_pin msg_list] + set ac_periphery_node ${ac_clk_phase_select_node}|clkout + + set ac_max [ddr3_p0_max_in_collection [get_path -rise_from $pll_clock -${rise_or_fall_to} $ac_periphery_node] "arrival_time"] + if {$ac_max <= 0} {set ac_max -9999} + set ac_min [ddr3_p0_max_in_collection [get_path -rise_from $pll_clock -${rise_or_fall_to} $ac_periphery_node -min_path] "arrival_time"] + if {$ac_min <= 0} {set ac_min 9999} + set extra_ccpr [ddr3_p0_round_3dp [expr ($clk_max - $clk_min + $ac_max - $ac_min)/2.0]] + + set pin_setup_slack [expr $pin_setup_slack + $extra_ccpr] + set pin_hold_slack [expr $pin_hold_slack + $extra_ccpr] + + set ACperiphery_min [get_path -rise_from $ac_periphery_node -rise_to $ac_pin -min_path -nworst 1 ] + set ACperiphery_max [get_path -rise_from $ac_periphery_node -rise_to $ac_pin -nworst 1] + set ACperiphery_min_delay [ddr3_p0_min_in_collection $ACperiphery_min "arrival_time"] + set ACperiphery_max_delay [ddr3_p0_max_in_collection $ACperiphery_max "arrival_time"] + set aiot_delay [ddr3_p0_round_3dp [expr [ddr3_p0_get_rise_aiot_delay [lindex $ac_pin 0]] * 1e9]] + set ACperiphery_min_delay [expr $ACperiphery_min_delay - $aiot_delay] + set ACperiphery_max_delay [expr $ACperiphery_max_delay - $aiot_delay] + set ACpath_pessimism [expr $ACperiphery_min_delay*($scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor) + ($ACperiphery_max_delay - $ACperiphery_min_delay)/2] + + set pin_setup_slack [expr $pin_setup_slack + $ACpath_pessimism] + set pin_hold_slack [expr $pin_hold_slack + $CKpath_pessimism] + + set setup_slack [min $setup_slack $pin_setup_slack] + set hold_slack [min $hold_slack $pin_hold_slack] + + } + + ######################################## + ######################################## + ##Create the a/c analysis panel + set ac_summary [list] + lappend ac_summary [list " Standard Address Command" [ddr3_p0_format_3dp $default_setup_slack] [ddr3_p0_format_3dp $default_hold_slack]] + lappend ac_summary [list " Extra common clock and spatial correlation pessimism removal" [ddr3_p0_format_3dp [expr $setup_slack - $default_setup_slack]] [ddr3_p0_format_3dp [expr $hold_slack - $default_hold_slack]]] + + set positive_fcolour [list "black" "blue" "blue"] + set negative_fcolour [list "black" "red" "red"] + set panel_name "$inst Address Command" + set root_folder_name [get_current_timequest_report_folder] + + if { ! [string match "${root_folder_name}*" $panel_name] } { + set panel_name "${root_folder_name}||$panel_name" + } + # Create the root if it doesn't yet exist + if {[get_report_panel_id $root_folder_name] == -1} { + set panel_id [create_report_panel -folder $root_folder_name] + } + + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + if {($setup_slack < 0) || ($hold_slack <0)} { + set panel_id [create_report_panel -table $panel_name -color red] + } else { + set panel_id [create_report_panel -table $panel_name] + } + add_row_to_table -id $panel_id [list "Operation" "Setup Slack" "Hold Slack"] + + set fcolour [ddr3_p0_get_colours $setup_slack $hold_slack] + add_row_to_table -id $panel_id [list "Address Command" [ddr3_p0_format_3dp $setup_slack] [ddr3_p0_format_3dp $hold_slack]] -fcolor $fcolour + lappend summary [list $opcname 0 "Address Command ($opcname)" [ddr3_p0_format_3dp $setup_slack] [ddr3_p0_format_3dp $hold_slack]] + + foreach summary_line $ac_summary { + add_row_to_table -id $panel_id $summary_line -fcolors $positive_fcolour + } + + ###################################################################### + ##Loop over DQS pins, and perform analysis + + set pll_clock $pins(pll_write_clock) + + set dqs_setup_slack 1000000000 + set dqs_hold_slack 1000000000 + foreach dqs_pin $pins(dqs_pins) { + + set dqs_pin_setup_slack [ddr3_p0_min_in_collection_to_name $dqs_paths_setup "slack" $dqs_pin] + set dqs_pin_hold_slack [ddr3_p0_min_in_collection_to_name $dqs_paths_hold "slack" $dqs_pin] + + set dqs_clk_phase_select_node [ddr3_p0_traverse_to_clock_phase_select $dqs_pin msg_list] + set dqs_periphery_node ${dqs_clk_phase_select_node}|clkout + + set dqs_max [ddr3_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $dqs_periphery_node] "arrival_time"] + if {$dqs_max <= 0} {set dqs_max -9999} + set dqs_min [ddr3_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $dqs_periphery_node -min_path] "arrival_time"] + if {$dqs_min <= 0} {set dqs_min 9999} + + set extra_ccpr [ddr3_p0_round_3dp [expr ($clk_max - $clk_min + $dqs_max - $dqs_min)/2.0]] + + set dqs_pin_setup_slack [expr $dqs_pin_setup_slack + $extra_ccpr] + set dqs_pin_hold_slack [expr $dqs_pin_hold_slack + $extra_ccpr] + + set dqs_setup_slack [min $dqs_setup_slack $dqs_pin_setup_slack] + set dqs_hold_slack [min $dqs_hold_slack $dqs_pin_hold_slack] + } + + ######################################## + ######################################## + ##Create the DQS vs CK analysis panel + + set dqs_summary [list] + + lappend dqs_summary [list " Standard DQS vs CK" [ddr3_p0_format_3dp $default_dqs_setup_slack] [ddr3_p0_format_3dp $default_dqs_hold_slack]] + lappend dqs_summary [list " Extra common clock pessimism removal" [ddr3_p0_format_3dp [expr $dqs_setup_slack - $default_dqs_setup_slack]] [ddr3_p0_format_3dp [expr $dqs_hold_slack - $default_dqs_hold_slack]]] + + set dqs_panel_name "$inst DQS vs CK" + + if { ! [string match "${root_folder_name}*" $dqs_panel_name] } { + set dqs_panel_name "${root_folder_name}||$dqs_panel_name" + } + + # Delete any pre-existing summary panel + set dqs_panel_id [get_report_panel_id $dqs_panel_name] + if {$dqs_panel_id != -1} { + delete_report_panel -id $dqs_panel_id + } + + if {($dqs_setup_slack < 0) || ($dqs_hold_slack <0)} { + set dqs_panel_id [create_report_panel -table $dqs_panel_name -color red] + } else { + set dqs_panel_id [create_report_panel -table $dqs_panel_name] + } + add_row_to_table -id $dqs_panel_id [list "Operation" "Setup Slack" "Hold Slack"] + + set fcolour [ddr3_p0_get_colours $dqs_setup_slack $dqs_hold_slack] + add_row_to_table -id $dqs_panel_id [list "DQS vs CK" [ddr3_p0_format_3dp $dqs_setup_slack] [ddr3_p0_format_3dp $dqs_hold_slack]] -fcolor $fcolour + lappend summary [list $opcname 0 "DQS vs CK ($opcname)" [ddr3_p0_format_3dp $dqs_setup_slack] [ddr3_p0_format_3dp $dqs_hold_slack]] + + foreach summary_line $dqs_summary { + add_row_to_table -id $dqs_panel_id $summary_line -fcolors $positive_fcolour + } +} + + +############################################################# +# Bus Turnaround Time Analysis +############################################################# + +proc ddr3_p0_perform_flexible_bus_turnaround_time_analysis {opcs opcname instname family period dll_length interface_type tJITper tJITdty tDCD pll_steps pin_array_name timing_parameters_array_name summary_name MP_name IP_name SSN_name board_name ISI_parameters_name} { + + ############################################################################### + # The bus-turnaround time analysis concerns making sure there is no contention on + # on the DQ bus when a read command is followed by a write command. When a read + # command is issued, some cycles later the memory takes control of the DQS bus and + # starts sending back data to the controller. If the controller issues a write + # command too early then the read command data may not have fully read and there + # may be contention on the bus. This analysis determines how much margin there + # is on the switchover time and if the slack is negative, either the controller's + # bus turnaround time must be increased (which reduces effeciency), or the + # absolute delays on the board traces must be reduced. + ############################################################################### + + ####################################### + # Need access to global variables + upvar 1 $summary_name summary + upvar 1 $timing_parameters_array_name t + upvar 1 $IP_name IP + upvar 1 $pin_array_name pins + upvar 1 $board_name board + upvar 1 $MP_name MP + upvar 1 $SSN_name SSN + upvar 1 $ISI_parameters_name ISI + + # Derived parameters + if {$t(DWIDTH_RATIO) == 2} { + set burst_length 4 + } elseif {$t(DWIDTH_RATIO) == 4} { + set burst_length 8 + } else { + set burst_length 16 + } + + ###################################################################### + # Find the maximum delay of the CK issuing a read command followed by + # read data coming back + + # Maximum clock delay + set ac_hold [get_timing_paths -to $pins(add_pins) -hold -npaths 100] + set max_dly [expr [ddr3_p0_max_in_collection $ac_hold "clock_skew"]] + + # SSO and Jitter pushout on clock + set max_dly [expr $max_dly + $SSN(pushout_o) + $tJITper/2] + + # CK Board delay + set max_dly [expr $max_dly + $board(abs_max_CK_delay)] + + # Read Latency and Burst Lenght + set max_dly [expr $max_dly + ($t(RL) + $burst_length/2)*$t(CK)] + + # DQS Board delay + set max_dly [expr $max_dly + $board(abs_max_DQS_delay)] + + # Time for DQS to go high impedance relative to the CK + set max_dly [expr $max_dly + $t(DQSCK)] + + # SSI pushout on DQS + set max_dly [expr $max_dly + $SSN(pushout_i)] + + ###################################################################### + # Find the minimum delay of the issuing a write command after read + # command has been issued and the FPGA taking hold of the DQS trace + + # Because of the levelling operation we assume that the output delay of + # the clock is the same as the output delay of the write (other than + # board delays and transient delays + set ac_setup [get_timing_paths -to $pins(add_pins) -setup -npaths 100] + set min_dly [expr [ddr3_p0_min_in_collection $ac_setup "clock_skew"]] + + # SSO pullin on write data + set min_dly [expr $min_dly - $SSN(pullin_o)] + + # Jitter and other effects on write data + set min_dly [expr $min_dly - $t(WL_DCD) - $t(WL_JITTER) - $t(WL_PSE)] + + # Quantization error on levelling + set min_dly [expr $min_dly - $IP(quantization_WL)] + + # Difference in board delay + set min_dly [expr $min_dly - $board(minCK_DQS_skew)] + + # Delay between the read command and write command + set num_clocks_read_to_write [expr $t(RL) - $t(WL) + $burst_length/2 + 2 + $t(rd_to_wr_turnaround_oct)] + set min_dly [expr $min_dly + $num_clocks_read_to_write*$t(CK)] + + # Delay between write command and write data on the bus + set min_dly [expr $min_dly + $t(WL)*$t(CK)] + + # Adjustment for when the DQS preamble is driven + set min_dly [expr $min_dly - $t(CK)] + + # Adjustment for when the OCT is enabled (one cycle berfore DQS preamble) + set min_dly [expr $min_dly - $t(CK)] + + set setup_slack [expr $min_dly - $max_dly] + set hold_slack "--" + + lappend summary [list $opcname 0 "Bus Turnaround Time ($opcname)" $setup_slack $hold_slack] + +} + + +proc ddr3_p0_perform_resync_timing_analysis {opcs opcname inst fbasename family scale_factors_name io_std interface_type period pin_array_name timing_parameters_array_name summary_name MP_name IP_name board_name fpga_name SSN_name} { + + ############################################################################### + # The resynchronization timing analysis concerns transferring read data that + # has been captured with a DQS strobe to a clock domain under the control of + # the UniPHY. A special FIFO is used to resynchronize the data which has a wide + # tolerance to any changes in the arrival time of data from DQS groups + ############################################################################### + + ####################################### + # Need access to global variables + upvar 1 $summary_name summary + upvar 1 $timing_parameters_array_name t + upvar 1 $pin_array_name pins + upvar 1 $MP_name MP + upvar 1 $IP_name IP + upvar 1 $board_name board + upvar 1 $fpga_name fpga + upvar 1 $SSN_name SSN + upvar 1 $scale_factors_name scale_factors + + set num_paths 5000 + + set prefix [ string map "| |*:" $inst ] + set prefix "*:$prefix" + + lappend summary [list $opcname 0 "Read Resync ($opcname)" 1.000 1.000] + + return + ####################################### + # Node names + set dqs_pins $pins(dqs_pins) + set fifo ${prefix}*${fbasename}_flop_mem:read_buffering[*].read_subgroup[*].uread_fifo|data_stored[*][*] + set reg_in_rd_clk_domain ${prefix}*${fbasename}_flop_mem:read_buffering[*].read_subgroup[*].uread_fifo|rd_data[*] + set reg_wr_address ${prefix}*${fbasename}_read_datapath:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*] + set reg_rd_address ${prefix}*${fbasename}_read_datapath:uread_datapath|read_buffering[*].read_subgroup[*].rdaddress[*] + + ####################################### + # Paths + set max_DQS_to_fifo_paths [get_path -from $dqs_pins -to $fifo -npaths $num_paths -nworst 1] + set min_DQS_to_fifo_paths [get_path -from $dqs_pins -to $fifo -npaths $num_paths -min_path -nworst 1] + + set max_fifo_to_rd_clk_domain_paths [get_path -from $fifo -to $reg_in_rd_clk_domain -npaths $num_paths -nworst 1] + set min_fifo_to_rd_clk_domain_paths [get_path -from $fifo -to $reg_in_rd_clk_domain -npaths $num_paths -min_path -nworst 1] + + set max_DQS_to_wr_address_paths [get_path -from $dqs_pins -to $reg_wr_address -npaths $num_paths -nworst 1] + set min_DQS_to_wr_address_paths [get_path -from $dqs_pins -to $reg_wr_address -npaths $num_paths -min_path -nworst 1] + + set max_rd_address_to_rd_data_paths [get_path -from $reg_rd_address -to $reg_in_rd_clk_domain -npaths $num_paths -nworst 1] + set min_rd_address_to_rd_data_paths [get_path -from $reg_rd_address -to $reg_in_rd_clk_domain -npaths $num_paths -min_path -nworst 1] + + set max_dqs_common_to_fifo [ddr3_p0_max_in_collection [get_path -from $dqs_pins -to $fifo -nworst 1] "arrival_time"] + + ######################################### + # Limit to one endpoint/startpoint + + foreach_in_collection path $max_DQS_to_fifo_paths { + set arrival_time [get_path_info $path -arrival_time] + set startpoint [get_node_info -name [get_path_info $path -from]] + if {[info exist max_DQS_to_fifo_paths_max($startpoint)]} { + if {$arrival_time > $max_DQS_to_fifo_paths_max($startpoint)} { + set max_DQS_to_fifo_paths_max($startpoint) $arrival_time + } + } else { + set max_DQS_to_fifo_paths_max($startpoint) $arrival_time + } + } + + foreach_in_collection path $min_DQS_to_fifo_paths { + set arrival_time [get_path_info $path -arrival_time] + set startpoint [get_node_info -name [get_path_info $path -from]] + if {[info exist min_DQS_to_fifo_paths_min($startpoint)]} { + if {$arrival_time < $min_DQS_to_fifo_paths_min($startpoint)} { + set min_DQS_to_fifo_paths_min($startpoint) $arrival_time + } + } else { + set min_DQS_to_fifo_paths_min($startpoint) $arrival_time + } + } + + + foreach_in_collection path $max_fifo_to_rd_clk_domain_paths { + set arrival_time [get_path_info $path -arrival_time] + set endpoint [get_node_info -name [get_path_info $path -to]] + if {[info exist max_fifo_to_rd_clk_domain_paths_max($endpoint)]} { + if {$arrival_time > $max_fifo_to_rd_clk_domain_paths_max($endpoint)} { + set max_fifo_to_rd_clk_domain_paths_max($endpoint) $arrival_time + } + } else { + set max_fifo_to_rd_clk_domain_paths_max($endpoint) $arrival_time + } + } + + foreach_in_collection path $min_fifo_to_rd_clk_domain_paths { + set arrival_time [get_path_info $path -arrival_time] + set endpoint [get_node_info -name [get_path_info $path -to]] + if {[info exist min_fifo_to_rd_clk_domain_paths_min($endpoint)]} { + if {$arrival_time < $min_fifo_to_rd_clk_domain_paths_min($endpoint)} { + set min_fifo_to_rd_clk_domain_paths_min($endpoint) $arrival_time + } + } else { + set min_fifo_to_rd_clk_domain_paths_min($endpoint) $arrival_time + } + } + + foreach_in_collection path $max_rd_address_to_rd_data_paths { + set arrival_time [get_path_info $path -arrival_time] + set endpoint [get_node_info -name [get_path_info $path -to]] + if {[info exist max_rd_address_to_rd_data_paths_max($endpoint)]} { + if {$arrival_time > $max_rd_address_to_rd_data_paths_max($endpoint)} { + set max_rd_address_to_rd_data_paths_max($endpoint) $arrival_time + } + } else { + set max_rd_address_to_rd_data_paths_max($endpoint) $arrival_time + } + } + + foreach_in_collection path $min_rd_address_to_rd_data_paths { + set arrival_time [get_path_info $path -arrival_time] + set endpoint [get_node_info -name [get_path_info $path -to]] + if {[info exist min_rd_address_to_rd_data_paths_min($endpoint)]} { + if {$arrival_time < $min_rd_address_to_rd_data_paths_min($endpoint)} { + set min_rd_address_to_rd_data_paths_min($endpoint) $arrival_time + } + } else { + set min_rd_address_to_rd_data_paths_min($endpoint) $arrival_time + } + } + + ####################################### + # TCO times + set i 0 + set tco_fifo_min 0 + set tco_fifo_max 0 + foreach_in_collection register [get_keepers $fifo] { + set tcotemp [get_register_info $register -tco] + if {$i == 0} { + set tco_fifo_min $tcotemp + set tco_fifo_max $tcotemp + } else { + if {$tcotemp < $tco_fifo_min} { + set tco_fifo_min $tcotemp + } elseif {$tcotemp > $tco_fifo_max} { + set tco_fifo_max $tcotemp + } + } + incr i + } + set i 0 + set tco_wr_address_min 0 + set tco_wr_address_max 0 + foreach_in_collection register [get_keepers $reg_wr_address] { + set tcotemp [get_register_info $register -tco] + if {$i == 0} { + set tco_wr_address_min $tcotemp + set tco_wr_address_max $tcotemp + } else { + if {$tcotemp < $tco_wr_address_min} { + set tco_wr_address_min $tcotemp + } elseif {$tcotemp > $tco_wr_address_max} { + set tco_wr_addressmax $tcotemp + } + } + incr i + } + + ####################################### + # Other parameters + set entity_names_on [ ddr3_p0_are_entity_names_on ] + set fly_by_wire 1.6 + set min_latency 1 + set max_latency 2 + if { ! $entity_names_on } { + set fifo_depth [get_collection_size [get_keepers $inst*read_buffering[0].read_subgroup[0].uread_fifo|data_stored[*][0]]] + } else { + set fifo_depth [get_collection_size [get_keepers $prefix*read_buffering[0].read_subgroup[0].uread_fifo|data_stored[*][0]]] + } + if {($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} { + # Reduce the effect of tDQSCK + set mp_DQSCK [expr $MP(DQSCK)*$t(DQSCK)] + } else { + set mp_DQSCK 0 + } + set hf_DQS_variation [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -in_fitter -period $period]/1000.0*2/2] + set hf_DQS_variation [expr $hf_DQS_variation + $SSN(pushout_o) + $SSN(pullin_o) + 2*$t(DQSCK) - 2*$mp_DQSCK + $SSN(pullin_i)] + set hf_DQS_variation [expr $hf_DQS_variation + [get_float_table_node_delay -src {DELAYCHAIN_T9} -dst {VTVARIATION} -parameters [list IO $interface_type]]*$max_dqs_common_to_fifo/2] + + ####################################### + # Board parameters + set board_skew [expr $board(inter_DQS_group_skew)/2.0] + if {$IP(num_ranks) > 1} { + set board_skew [expr $board_skew + $board(tpd_inter_DIMM)] + } + + ####################################### + # Body of Resync analysis + # Go over each DQ pin + + set total_setup_slack 10000000 + set total_hold_slack 10000000 + + set regs [get_keepers $reg_in_rd_clk_domain] + + foreach_in_collection reg $regs { + + set reg_name [get_register_info -name $reg] + + if {[info exists max_rd_address_to_rd_data_paths_max($reg_name)]==0} { + # not all registers have arcs for the hard read fifo, depending upon full/half rate + continue + } + + regexp {read_buffering\[(\d+)\]\.read_subgroup} $reg_name match dqs_group_number + + set dqs_pin [lindex $pins(dqs_pins) $dqs_group_number] + if {!([info exists max_DQS_to_fifo_paths_max($dqs_pin)] && + [info exists min_DQS_to_fifo_paths_min($dqs_pin)] && + [info exists max_fifo_to_rd_clk_domain_paths_max($reg_name_fifo_data_rd_clk_domain)] && + [info exists min_fifo_to_rd_clk_domain_paths_min($reg_name_fifo_data_rd_clk_domain)] && + [info exists max_rd_address_to_rd_data_paths_max($reg_name)] && + [info exists min_rd_address_to_rd_data_paths_min($reg_name)])} { + post_message -type error "Paths not found for resync analysis." + return 1 + } + set max_DQS_to_fifo $max_DQS_to_fifo_paths_max($dqs_pin) + set min_DQS_to_fifo $min_DQS_to_fifo_paths_min($dqs_pin) + set max_fifo_to_rd_clk_domain $max_fifo_to_rd_clk_domain_paths_max($reg_name) + set min_fifo_to_rd_clk_domain $min_fifo_to_rd_clk_domain_paths_min($reg_name) + set max_rd_address_to_rd_data $max_rd_address_to_rd_data_paths_max($reg_name) + set min_rd_address_to_rd_data $min_rd_address_to_rd_data_paths_min($reg_name) + + + ############### + # Setup analysis + set setup_arrival_time [expr ($max_DQS_to_fifo - $min_DQS_to_fifo) + $tco_fifo_max + $max_fifo_to_rd_clk_domain] + set setup_required_time [expr $min_latency*$period + $tco_wr_address_min + $min_rd_address_to_rd_data] + set setup_slack [expr $setup_required_time - $setup_arrival_time - $board_skew] + + ############### + # Hold analysis + set hold_arrival_time [expr ($min_DQS_to_fifo - $max_DQS_to_fifo) + $tco_fifo_min + $min_fifo_to_rd_clk_domain + $fifo_depth*$period] + set hold_required_time [expr $hf_DQS_variation + $max_rd_address_to_rd_data + $tco_wr_address_max + $max_latency*$period + $fly_by_wire] + set hold_slack [expr -$hold_required_time + $hold_arrival_time - $board_skew] + + if {$setup_slack < $total_setup_slack} { + set total_setup_slack $setup_slack + } + + if {$hold_slack < $total_hold_slack} { + set total_hold_slack $hold_slack + } + } + + lappend summary [list $opcname 0 "Read Resync ($opcname)" $total_setup_slack $total_hold_slack] + +} + +############################################################# +# Postamble Timing Analysis +############################################################# + +proc ddr3_p0_perform_flexible_postamble_timing_analysis {opcs opcname instname scale_factors_name family period dll_length interface_type tJITper tJITdty tDCD DQSpathjitter pin_array_name timing_parameters_array_name summary_name MP_name IP_name SSN_name board_name ISI_parameters_name} { + + ############################################################################### + # The postamble analysis concerns gating the DQS signal within the device + # in the allotated time before DQS goes tri-state, such that spurious data is not + # registered if there is noise on DQS. Altera devices have dedicated register that + # can be used to ground the DQS signal, and the timing analysis below considers + # the timing margins for the clock that is used to reset that register. + ############################################################################### + + + ####################################### + # Need access to global variables + upvar 1 $summary_name summary + upvar 1 $timing_parameters_array_name t + upvar 1 $IP_name IP + upvar 1 $pin_array_name pins + upvar 1 $board_name board + upvar 1 $MP_name MP + upvar 1 $SSN_name SSN + upvar 1 $ISI_parameters_name ISI + upvar 1 $scale_factors_name scale_factors + + # Ideal setup and hold slacks is half the postamble time (full clock cycle) + set setup_slack [expr 0.5*$t(CK)] + set hold_slack [expr 0.5*$t(CK)] + + ############################### + # Memory Parameters + ############################### + + # Remove the variation in the clock coming back from the memory + set tDQSCK $t(DQSCK) + if {($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} { + if {$IP(tracking_enabled) == 1} { + set tDQSCK [expr (1.0-($MP(DQSCK)+$MP(DQSCK_T)))*$tDQSCK] + } else { + set tDQSCK [expr (1.0-$MP(DQSCK))*$tDQSCK] + } + } elseif {$IP(mp_calibration) == 1} { + set tDQSCK [expr (1.0-$MP(DQSCK)/2.5)*$tDQSCK] + } + + set setup_slack [expr $setup_slack - $tDQSCK] + set hold_slack [expr $hold_slack - $tDQSCK] + + ############################## + # Jitter/SSN Effects + ############################## + + # Remove the jitter on the clock out to the memory, and the DQS enable clock + set setup_slack [expr $setup_slack - $tJITper/2 - $tJITper/2] + set hold_slack [expr $hold_slack - $tJITper/2 - $tJITper/2] + + # Remove the jitter on the DQS path + set setup_slack [expr $setup_slack - $DQSpathjitter/2] + set hold_slack [expr $hold_slack - $DQSpathjitter/2] + + # Remove SSN effects + if {$IP(tracking_enabled) == 1} { + set total_ssn [expr $SSN(pushout_o) + $SSN(pushout_i) + $SSN(pullin_o) + $SSN(pullin_i)] + set setup_slack [expr $setup_slack - $total_ssn/2] + set hold_slack [expr $hold_slack - $total_ssn/2] + } else { + set setup_slack [expr $setup_slack - $SSN(pushout_o) - $SSN(pushout_i)] + set hold_slack [expr $hold_slack - $SSN(pullin_o) - $SSN(pullin_i)] + } + + ############################## + # VT/Aging effects + ############################## + + set coarse_delay [expr $t(CK)/$dll_length] + set dqsenableextend_regs [list *dq_ddio[*].ubidir_dq_dqs|*|dqs_enable_ctrl~DFFEXTENDDQSENABLE *dq_ddio[*].ubidir_dq_dqs|*|dqs_enable_ctrl~DQSENABLEOUT_DFF] + # Clock out to DQS path coming back into the FPGA + set mem_clock_delay_max [ddr3_p0_max_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $pins(ck_pins)] "arrival_time"] + set mem_clock_delay_min [ddr3_p0_min_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $pins(ck_pins) -min_path] "arrival_time"] + + + set dqs_delay_max [ddr3_p0_max_in_collection [get_path -rise_from $pins(dqs_pins) -fall_to *POSTAMBLE_DFF] "arrival_time"] + set dqs_delay_min [ddr3_p0_min_in_collection [get_path -rise_from $pins(dqs_pins) -fall_to *POSTAMBLE_DFF -min_path] "arrival_time"] + set ck_pin_buffer_delay [ddr3_p0_round_3dp [expr [ddr3_p0_get_min_aiot_delay [lindex $pins(ck_pins) 0]] * 1e9]] + + set return_path_delay_max [expr $mem_clock_delay_max + $dqs_delay_max - ($ck_pin_buffer_delay*1.55)] + set return_path_delay_min [expr $mem_clock_delay_min + $dqs_delay_min - ($ck_pin_buffer_delay*1.55)] + + # DQS Enable clk to DQS Enable register + set clock_delay_max [ddr3_p0_max_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $dqsenableextend_regs] "arrival_time"] + set clock_delay_min [ddr3_p0_min_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $dqsenableextend_regs -min_path] "arrival_time"] + set t11_delay_max [ddr3_p0_max_in_collection [get_path -rise_from $dqsenableextend_regs -fall_to *POSTAMBLE_DFF] "arrival_time"] + set t11_delay_min [ddr3_p0_min_in_collection [get_path -rise_from $dqsenableextend_regs -fall_to *POSTAMBLE_DFF -min_path] "arrival_time"] + + set t11_setting_delay_max_base [expr [get_integer_node_delay -integer 0 -parameters {DQS_ENABLE RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0] + set t11_setting_delay_max [expr [get_integer_node_delay -integer 15 -parameters {DQS_ENABLE RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0] + set t11_setting_delay_max [expr {$t11_setting_delay_max - $t11_setting_delay_max_base}] + set t11_setting_delay_min_base [expr [get_integer_node_delay -integer 0 -parameters {DQS_ENABLE MIN RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0] + set t11_setting_delay_min [expr [get_integer_node_delay -integer 15 -parameters {DQS_ENABLE MIN RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0] + set t11_setting_delay_min [expr {$t11_setting_delay_min - $t11_setting_delay_min_base}] + + set dqs_enable_signal_delay_max [expr $clock_delay_max + $t11_delay_max + $t11_setting_delay_max] + set dqs_enable_signal_delay_min [expr $clock_delay_min + $t11_delay_min + $t11_setting_delay_min] + + if {($mem_clock_delay_max == 0) || ($clock_delay_max == 0) || ($dqs_delay_max == 0)} { + lappend summary [list $opcname 0 "Postamble ($opcname)" -1.999 -1.999] + return + } + + # Determine the worst-case difference between the two paths + set t11_delay_difference 0 + set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_min - $dqs_enable_signal_delay_min)}]] + set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_min - $dqs_enable_signal_delay_max)}]] + set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_max - $dqs_enable_signal_delay_min)}]] + set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_max - $dqs_enable_signal_delay_max)}]] + if {$t11_delay_difference < 0} { + # If the DQS Enable path is longer, then any T11 setting picked for centering will make the delay mismatch worse + set t11_delay_difference [expr {abs($t11_delay_difference) + $coarse_delay}] + } + + # Determine worst-case V or VT variation as a % of delay + set lf_vt_drift_derating 0.75 + if {$IP(tracking_enabled) == 1} { + # Just V variation + set vt_variation_percent [expr 2*[get_float_table_node_delay -src {DELAYCHAIN_DUTY_CYCLE} -dst {VTVARIATION} -parameters [list IO $interface_type]]] + } else { + # Both V and T variation + #TODO, get T variation + set vt_variation_percent [expr 0.10 + 2*[get_float_table_node_delay -src {DELAYCHAIN_DUTY_CYCLE} -dst {VTVARIATION} -parameters [list IO $interface_type]]] + } + + # Determine aging variation as a % of delay + set age_variation_derating 0.7 + set age_variation_percent [expr $scale_factors(eol)/$IP(eol_reduction_factor_write)] + + # Determine total on-chip variation + set delay_variation_percent [expr 2*$vt_variation_percent*$lf_vt_drift_derating + $age_variation_derating*$age_variation_percent] + set delay_variation [expr $t11_delay_difference*$delay_variation_percent] + + set setup_slack [expr $setup_slack - $delay_variation/2] + set hold_slack [expr $hold_slack - $delay_variation/2] + + # Voltage variation across matched clocks (this is not included above because the matched clock paths are subtracted out) + #Below values for delay miscorrelation matched paths are obtained from the FLS + set delay_miscorrelation_matched_paths_just_v 0.014 + set delay_miscorrelation_matched_paths 0.02 + set matched_path_voltage_variation [expr $clock_delay_max*$delay_miscorrelation_matched_paths_just_v*2] + set setup_slack [expr $setup_slack - $matched_path_voltage_variation/2] + set hold_slack [expr $hold_slack - $matched_path_voltage_variation/2] + + # DCD effects + #1.25 is the period @ 800MHz + set dcd_effect [expr 1.25*$tDCD*2] + set setup_slack [expr $setup_slack - $dcd_effect/2] + set hold_slack [expr $hold_slack - $dcd_effect/2] + + ############################## + # PVT compensated tracking uncertainties + ############################## + + set dll_update_latency 9000.0 + set hf_rate_of_change 0.00001029 + set ldc_tracking_error_percent [min $vt_variation_percent [expr $dll_update_latency*$hf_rate_of_change]] + set ldc_tracking_error [expr 2*$t(CK)*3/$dll_length*$ldc_tracking_error_percent] + set ldc_absolute_error [expr 2*$IP(quantization_WL)*3+2*$t(CK)*0.375*$delay_miscorrelation_matched_paths] + + set setup_slack [expr $setup_slack - $ldc_tracking_error/2 - $ldc_absolute_error/2] + set hold_slack [expr $hold_slack - $ldc_tracking_error/2 - $ldc_absolute_error/2] + + + ############################## + # Quantization error + ############################## + + set quantization_step [expr 2*$IP(quantization_T11)*1.5] + set setup_slack [expr $setup_slack - $quantization_step/2] + set hold_slack [expr $hold_slack - $quantization_step/2] + + ############################## + # Tracking algorithm uncertainties + ############################## + + if {$IP(tracking_enabled) == 1} { + set mistake_tracking_jitter [expr 0.025*(2*$tDQSCK + 2*$tJITper + $total_ssn + $delay_variation + $quantization_step + $ldc_tracking_error + $matched_path_voltage_variation)] + set setup_slack [expr $setup_slack - $mistake_tracking_jitter/2] + set hold_slack [expr $hold_slack - $mistake_tracking_jitter/2] + } + + ############################## + # Multirank effects + ############################## + + + # Remove Multirank board skew effects - Calibration will calibrate to the average of multiple ranks + if {$IP(num_ranks) > 1} { + set setup_slack [expr $setup_slack - $board(tpd_inter_DIMM)] + set hold_slack [expr $hold_slack - $board(tpd_inter_DIMM)] + } + + lappend summary [list $opcname 0 "Postamble ($opcname)" $setup_slack $hold_slack] +} + diff --git a/ip/altera/ddr3/ddr3_p0_reset.v b/ip/altera/ddr3/ddr3_p0_reset.v new file mode 100644 index 0000000..6668cbb --- /dev/null +++ b/ip/altera/ddr3/ddr3_p0_reset.v @@ -0,0 +1,157 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *) +module ddr3_p0_reset( + seq_reset_mem_stable, + pll_afi_clk, + pll_addr_cmd_clk, + pll_dqs_ena_clk, + seq_clk, + scc_clk, + pll_avl_clk, + reset_n_scc_clk, + reset_n_avl_clk, + read_capture_clk, + pll_locked, + global_reset_n, + soft_reset_n, + ctl_reset_n, + ctl_reset_export_n, + reset_n_afi_clk, + reset_n_addr_cmd_clk, + reset_n_resync_clk, + reset_n_seq_clk, + reset_n_read_capture_clk +); + + +parameter MEM_READ_DQS_WIDTH = ""; + +parameter NUM_AFI_RESET = 1; + + +input seq_reset_mem_stable; + +input pll_afi_clk; +input pll_addr_cmd_clk; +input pll_dqs_ena_clk; +input seq_clk; +input scc_clk; +input pll_avl_clk; +output reset_n_scc_clk; +output reset_n_avl_clk; +input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk; +input pll_locked; +input global_reset_n; +input soft_reset_n; +output ctl_reset_n; +output ctl_reset_export_n; +output [NUM_AFI_RESET-1:0] reset_n_afi_clk; +output reset_n_addr_cmd_clk; +output reset_n_resync_clk; +output reset_n_seq_clk; +output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk; + +// Apply the synthesis keep attribute on the synchronized reset wires +// so that these names can be constrained using QSF settings to keep +// the resets on local routing. +wire phy_reset_n /* synthesis keep = 1 */; +wire phy_reset_mem_stable_n /* synthesis keep = 1*/; + +wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture; + + + assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable; + assign reset_n_read_capture_clk = reset_n_read_capture; + + assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n; + + ddr3_p0_reset_sync ureset_afi_clk( + .reset_n (phy_reset_n), + .clk (pll_afi_clk), + .reset_n_sync (reset_n_afi_clk) + ); + defparam ureset_afi_clk.RESET_SYNC_STAGES = 15; + defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET; + + ddr3_p0_reset_sync ureset_ctl_reset_clk( + .reset_n (phy_reset_n), + .clk (pll_afi_clk), + .reset_n_sync ({ctl_reset_n, ctl_reset_export_n}) + ); + defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15; + defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2; + + ddr3_p0_reset_sync ureset_addr_cmd_clk( + .reset_n (phy_reset_n), + .clk (pll_addr_cmd_clk), + .reset_n_sync (reset_n_addr_cmd_clk) + ); + defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15; + defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1; + + + + ddr3_p0_reset_sync ureset_resync_clk( + .reset_n (phy_reset_n), + .clk (pll_dqs_ena_clk), + .reset_n_sync (reset_n_resync_clk) + ); + defparam ureset_resync_clk.RESET_SYNC_STAGES = 15; + defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1; + + ddr3_p0_reset_sync ureset_seq_clk( + .reset_n (phy_reset_n), + .clk (seq_clk), + .reset_n_sync (reset_n_seq_clk) + ); + defparam ureset_seq_clk.RESET_SYNC_STAGES = 15; + defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1; + + ddr3_p0_reset_sync ureset_scc_clk( + .reset_n (phy_reset_n), + .clk (scc_clk), + .reset_n_sync (reset_n_scc_clk) + ); + defparam ureset_scc_clk.RESET_SYNC_STAGES = 15; + defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1; + + ddr3_p0_reset_sync ureset_avl_clk( + .reset_n (phy_reset_n), + .clk (pll_avl_clk), + .reset_n_sync (reset_n_avl_clk) + ); + defparam ureset_avl_clk.RESET_SYNC_STAGES = 2; + defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1; + +generate +genvar i; + for (i=0; i [cpu_inst:reset_n, hphy_bridge:reset_n, irq_mapper:reset, mm_interconnect_0:cpu_inst_reset_n_reset_bridge_in_reset_reset, seq_bridge:reset, sequencer_mem:reset1, sequencer_reg_file_inst:avl_reset_n, sequencer_scc_mgr_inst:avl_reset_n] + wire sequencer_rst_clken_out_clken; // sequencer_rst:clken_out -> sequencer_mem:clken1 + wire [31:0] cpu_inst_data_master_readdata; // mm_interconnect_0:cpu_inst_data_master_readdata -> cpu_inst:d_readdata + wire cpu_inst_data_master_waitrequest; // mm_interconnect_0:cpu_inst_data_master_waitrequest -> cpu_inst:d_waitrequest + wire [19:0] cpu_inst_data_master_address; // cpu_inst:d_address -> mm_interconnect_0:cpu_inst_data_master_address + wire [3:0] cpu_inst_data_master_byteenable; // cpu_inst:d_byteenable -> mm_interconnect_0:cpu_inst_data_master_byteenable + wire cpu_inst_data_master_read; // cpu_inst:d_read -> mm_interconnect_0:cpu_inst_data_master_read + wire cpu_inst_data_master_write; // cpu_inst:d_write -> mm_interconnect_0:cpu_inst_data_master_write + wire [31:0] cpu_inst_data_master_writedata; // cpu_inst:d_writedata -> mm_interconnect_0:cpu_inst_data_master_writedata + wire seq_bridge_m0_waitrequest; // mm_interconnect_0:seq_bridge_m0_waitrequest -> seq_bridge:m0_waitrequest + wire [31:0] seq_bridge_m0_readdata; // mm_interconnect_0:seq_bridge_m0_readdata -> seq_bridge:m0_readdata + wire seq_bridge_m0_debugaccess; // seq_bridge:m0_debugaccess -> mm_interconnect_0:seq_bridge_m0_debugaccess + wire [31:0] seq_bridge_m0_address; // seq_bridge:m0_address -> mm_interconnect_0:seq_bridge_m0_address + wire seq_bridge_m0_read; // seq_bridge:m0_read -> mm_interconnect_0:seq_bridge_m0_read + wire [3:0] seq_bridge_m0_byteenable; // seq_bridge:m0_byteenable -> mm_interconnect_0:seq_bridge_m0_byteenable + wire seq_bridge_m0_readdatavalid; // mm_interconnect_0:seq_bridge_m0_readdatavalid -> seq_bridge:m0_readdatavalid + wire [31:0] seq_bridge_m0_writedata; // seq_bridge:m0_writedata -> mm_interconnect_0:seq_bridge_m0_writedata + wire seq_bridge_m0_write; // seq_bridge:m0_write -> mm_interconnect_0:seq_bridge_m0_write + wire [0:0] seq_bridge_m0_burstcount; // seq_bridge:m0_burstcount -> mm_interconnect_0:seq_bridge_m0_burstcount + wire [31:0] cpu_inst_instruction_master_readdata; // mm_interconnect_0:cpu_inst_instruction_master_readdata -> cpu_inst:i_readdata + wire cpu_inst_instruction_master_waitrequest; // mm_interconnect_0:cpu_inst_instruction_master_waitrequest -> cpu_inst:i_waitrequest + wire [16:0] cpu_inst_instruction_master_address; // cpu_inst:i_address -> mm_interconnect_0:cpu_inst_instruction_master_address + wire cpu_inst_instruction_master_read; // cpu_inst:i_read -> mm_interconnect_0:cpu_inst_instruction_master_read + wire [31:0] mm_interconnect_0_hphy_bridge_s0_readdata; // hphy_bridge:s0_readdata -> mm_interconnect_0:hphy_bridge_s0_readdata + wire mm_interconnect_0_hphy_bridge_s0_waitrequest; // hphy_bridge:s0_waitrequest -> mm_interconnect_0:hphy_bridge_s0_waitrequest + wire [15:0] mm_interconnect_0_hphy_bridge_s0_address; // mm_interconnect_0:hphy_bridge_s0_address -> hphy_bridge:s0_address + wire mm_interconnect_0_hphy_bridge_s0_read; // mm_interconnect_0:hphy_bridge_s0_read -> hphy_bridge:s0_read + wire mm_interconnect_0_hphy_bridge_s0_write; // mm_interconnect_0:hphy_bridge_s0_write -> hphy_bridge:s0_write + wire [31:0] mm_interconnect_0_hphy_bridge_s0_writedata; // mm_interconnect_0:hphy_bridge_s0_writedata -> hphy_bridge:s0_writedata + wire mm_interconnect_0_sequencer_mem_s1_chipselect; // mm_interconnect_0:sequencer_mem_s1_chipselect -> sequencer_mem:s1_chipselect + wire [31:0] mm_interconnect_0_sequencer_mem_s1_readdata; // sequencer_mem:s1_readdata -> mm_interconnect_0:sequencer_mem_s1_readdata + wire [12:0] mm_interconnect_0_sequencer_mem_s1_address; // mm_interconnect_0:sequencer_mem_s1_address -> sequencer_mem:s1_address + wire [3:0] mm_interconnect_0_sequencer_mem_s1_byteenable; // mm_interconnect_0:sequencer_mem_s1_byteenable -> sequencer_mem:s1_be + wire mm_interconnect_0_sequencer_mem_s1_write; // mm_interconnect_0:sequencer_mem_s1_write -> sequencer_mem:s1_write + wire [31:0] mm_interconnect_0_sequencer_mem_s1_writedata; // mm_interconnect_0:sequencer_mem_s1_writedata -> sequencer_mem:s1_writedata + wire [31:0] mm_interconnect_0_sequencer_scc_mgr_inst_avl_readdata; // sequencer_scc_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_scc_mgr_inst_avl_readdata + wire mm_interconnect_0_sequencer_scc_mgr_inst_avl_waitrequest; // sequencer_scc_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_scc_mgr_inst_avl_waitrequest + wire [12:0] mm_interconnect_0_sequencer_scc_mgr_inst_avl_address; // mm_interconnect_0:sequencer_scc_mgr_inst_avl_address -> sequencer_scc_mgr_inst:avl_address + wire mm_interconnect_0_sequencer_scc_mgr_inst_avl_read; // mm_interconnect_0:sequencer_scc_mgr_inst_avl_read -> sequencer_scc_mgr_inst:avl_read + wire mm_interconnect_0_sequencer_scc_mgr_inst_avl_write; // mm_interconnect_0:sequencer_scc_mgr_inst_avl_write -> sequencer_scc_mgr_inst:avl_write + wire [31:0] mm_interconnect_0_sequencer_scc_mgr_inst_avl_writedata; // mm_interconnect_0:sequencer_scc_mgr_inst_avl_writedata -> sequencer_scc_mgr_inst:avl_writedata + wire [31:0] mm_interconnect_0_sequencer_reg_file_inst_avl_readdata; // sequencer_reg_file_inst:avl_readdata -> mm_interconnect_0:sequencer_reg_file_inst_avl_readdata + wire mm_interconnect_0_sequencer_reg_file_inst_avl_waitrequest; // sequencer_reg_file_inst:avl_waitrequest -> mm_interconnect_0:sequencer_reg_file_inst_avl_waitrequest + wire [3:0] mm_interconnect_0_sequencer_reg_file_inst_avl_address; // mm_interconnect_0:sequencer_reg_file_inst_avl_address -> sequencer_reg_file_inst:avl_address + wire mm_interconnect_0_sequencer_reg_file_inst_avl_read; // mm_interconnect_0:sequencer_reg_file_inst_avl_read -> sequencer_reg_file_inst:avl_read + wire [3:0] mm_interconnect_0_sequencer_reg_file_inst_avl_byteenable; // mm_interconnect_0:sequencer_reg_file_inst_avl_byteenable -> sequencer_reg_file_inst:avl_be + wire mm_interconnect_0_sequencer_reg_file_inst_avl_write; // mm_interconnect_0:sequencer_reg_file_inst_avl_write -> sequencer_reg_file_inst:avl_write + wire [31:0] mm_interconnect_0_sequencer_reg_file_inst_avl_writedata; // mm_interconnect_0:sequencer_reg_file_inst_avl_writedata -> sequencer_reg_file_inst:avl_writedata + wire [31:0] cpu_inst_d_irq_irq; // irq_mapper:sender_irq -> cpu_inst:d_irq + + altera_mem_if_sequencer_rst #( + .DEPTH (10), + .CLKEN_LAGS_RESET (0) + ) sequencer_rst ( + .clk (avl_clk), // clk.clk + .rst (avl_reset_n), // rst.reset + .reset_out (sequencer_rst_reset_out_reset), // reset_out.reset + .clken_out (sequencer_rst_clken_out_clken) // clken_out.clken + ); + + altera_mem_if_sequencer_cpu_cv_synth_cpu_inst #( + .DEVICE_FAMILY ("CYCLONEV") + ) cpu_inst ( + .clk (avl_clk), // clk.clk + .reset_n (~sequencer_rst_reset_out_reset), // reset_n.reset_n + .d_address (cpu_inst_data_master_address), // data_master.address + .d_byteenable (cpu_inst_data_master_byteenable), // .byteenable + .d_read (cpu_inst_data_master_read), // .read + .d_readdata (cpu_inst_data_master_readdata), // .readdata + .d_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest + .d_write (cpu_inst_data_master_write), // .write + .d_writedata (cpu_inst_data_master_writedata), // .writedata + .i_address (cpu_inst_instruction_master_address), // instruction_master.address + .i_read (cpu_inst_instruction_master_read), // .read + .i_readdata (cpu_inst_instruction_master_readdata), // .readdata + .i_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest + .d_irq (cpu_inst_d_irq_irq), // d_irq.irq + .no_ci_readra () // custom_instruction_master.readra + ); + + sequencer_scc_mgr #( + .AVL_DATA_WIDTH (32), + .AVL_ADDR_WIDTH (13), + .MEM_IF_READ_DQS_WIDTH (2), + .MEM_IF_WRITE_DQS_WIDTH (2), + .MEM_IF_DQ_WIDTH (16), + .MEM_IF_DM_WIDTH (2), + .MEM_NUMBER_OF_RANKS (1), + .DLL_DELAY_CHAIN_LENGTH (8), + .FAMILY ("CYCLONEV"), + .USE_2X_DLL ("false"), + .USE_SHADOW_REGS (0), + .USE_DQS_TRACKING (0), + .DUAL_WRITE_CLOCK (0), + .SCC_DATA_WIDTH (1), + .TRK_PARALLEL_SCC_LOAD (0) + ) sequencer_scc_mgr_inst ( + .avl_clk (avl_clk), // avl_clk.clk + .avl_reset_n (~sequencer_rst_reset_out_reset), // avl_reset.reset_n + .avl_address (mm_interconnect_0_sequencer_scc_mgr_inst_avl_address), // avl.address + .avl_write (mm_interconnect_0_sequencer_scc_mgr_inst_avl_write), // .write + .avl_writedata (mm_interconnect_0_sequencer_scc_mgr_inst_avl_writedata), // .writedata + .avl_read (mm_interconnect_0_sequencer_scc_mgr_inst_avl_read), // .read + .avl_readdata (mm_interconnect_0_sequencer_scc_mgr_inst_avl_readdata), // .readdata + .avl_waitrequest (mm_interconnect_0_sequencer_scc_mgr_inst_avl_waitrequest), // .waitrequest + .scc_clk (scc_clk), // scc_clk.clk + .scc_reset_n (reset_n_scc_clk), // scc_reset.reset_n + .scc_data (scc_data), // scc.scc_data + .scc_dqs_ena (scc_dqs_ena), // .scc_dqs_ena + .scc_dqs_io_ena (scc_dqs_io_ena), // .scc_dqs_io_ena + .scc_dq_ena (scc_dq_ena), // .scc_dq_ena + .scc_dm_ena (scc_dm_ena), // .scc_dm_ena + .capture_strobe_tracking (capture_strobe_tracking), // .capture_strobe_tracking + .scc_upd (scc_upd), // .scc_upd + .afi_init_req (afi_init_req), // afi_init_cal_req.afi_init_req + .afi_cal_req (afi_cal_req), // .afi_cal_req + .scc_sr_dqsenable_delayctrl (), // (terminated) + .scc_sr_dqsdisablen_delayctrl (), // (terminated) + .scc_sr_multirank_delayctrl () // (terminated) + ); + + sequencer_reg_file #( + .AVL_DATA_WIDTH (32), + .AVL_ADDR_WIDTH (4), + .AVL_NUM_SYMBOLS (4), + .AVL_SYMBOL_WIDTH (8), + .REGISTER_RDATA (0), + .NUM_REGFILE_WORDS (16) + ) sequencer_reg_file_inst ( + .avl_clk (avl_clk), // avl_clk.clk + .avl_reset_n (~sequencer_rst_reset_out_reset), // avl_reset.reset_n + .avl_address (mm_interconnect_0_sequencer_reg_file_inst_avl_address), // avl.address + .avl_write (mm_interconnect_0_sequencer_reg_file_inst_avl_write), // .write + .avl_writedata (mm_interconnect_0_sequencer_reg_file_inst_avl_writedata), // .writedata + .avl_read (mm_interconnect_0_sequencer_reg_file_inst_avl_read), // .read + .avl_readdata (mm_interconnect_0_sequencer_reg_file_inst_avl_readdata), // .readdata + .avl_waitrequest (mm_interconnect_0_sequencer_reg_file_inst_avl_waitrequest), // .waitrequest + .avl_be (mm_interconnect_0_sequencer_reg_file_inst_avl_byteenable) // .byteenable + ); + + altera_mem_if_simple_avalon_mm_bridge #( + .DATA_WIDTH (32), + .SLAVE_DATA_WIDTH (32), + .MASTER_DATA_WIDTH (32), + .SYMBOL_WIDTH (8), + .ADDRESS_WIDTH (16), + .MASTER_ADDRESS_WIDTH (10), + .SLAVE_ADDRESS_WIDTH (10), + .BURSTCOUNT_WIDTH (3), + .WORKAROUND_HARD_PHY_ISSUE (1) + ) hphy_bridge ( + .clk (avl_clk), // clk.clk + .reset_n (~sequencer_rst_reset_out_reset), // reset.reset_n + .s0_address (mm_interconnect_0_hphy_bridge_s0_address), // s0.address + .s0_read (mm_interconnect_0_hphy_bridge_s0_read), // .read + .s0_readdata (mm_interconnect_0_hphy_bridge_s0_readdata), // .readdata + .s0_write (mm_interconnect_0_hphy_bridge_s0_write), // .write + .s0_writedata (mm_interconnect_0_hphy_bridge_s0_writedata), // .writedata + .s0_waitrequest (mm_interconnect_0_hphy_bridge_s0_waitrequest), // .waitrequest + .m0_address (avl_address), // m0.address + .m0_read (avl_read), // .read + .m0_readdata (avl_readdata), // .readdata + .m0_write (avl_write), // .write + .m0_writedata (avl_writedata), // .writedata + .m0_waitrequest (avl_waitrequest), // .waitrequest + .s0_waitrequest_n (), // (terminated) + .s0_beginbursttransfer (1'b0), // (terminated) + .s0_burstcount (3'b000), // (terminated) + .s0_byteenable (4'b1111), // (terminated) + .s0_readdatavalid (), // (terminated) + .m0_beginbursttransfer (), // (terminated) + .m0_burstcount (), // (terminated) + .m0_byteenable (), // (terminated) + .m0_readdatavalid (1'b0) // (terminated) + ); + + altera_mem_if_sequencer_mem_no_ifdef_params #( + .AVL_DATA_WIDTH (32), + .AVL_ADDR_WIDTH (13), + .AVL_NUM_SYMBOLS (4), + .AVL_SYMBOL_WIDTH (8), + .MEM_SIZE (23552), + .INIT_FILE ("ddr3_s0_sequencer_mem.hex"), + .RAM_BLOCK_TYPE ("AUTO") + ) sequencer_mem ( + .clk1 (avl_clk), // clk1.clk + .reset1 (sequencer_rst_reset_out_reset), // reset1.reset + .clken1 (sequencer_rst_clken_out_clken), // clken1.clken + .s1_address (mm_interconnect_0_sequencer_mem_s1_address), // s1.address + .s1_write (mm_interconnect_0_sequencer_mem_s1_write), // .write + .s1_writedata (mm_interconnect_0_sequencer_mem_s1_writedata), // .writedata + .s1_readdata (mm_interconnect_0_sequencer_mem_s1_readdata), // .readdata + .s1_be (mm_interconnect_0_sequencer_mem_s1_byteenable), // .byteenable + .s1_chipselect (mm_interconnect_0_sequencer_mem_s1_chipselect) // .chipselect + ); + + altera_avalon_mm_bridge #( + .DATA_WIDTH (32), + .SYMBOL_WIDTH (8), + .HDL_ADDR_WIDTH (32), + .BURSTCOUNT_WIDTH (1), + .PIPELINE_COMMAND (1), + .PIPELINE_RESPONSE (1) + ) seq_bridge ( + .clk (avl_clk), // clk.clk + .reset (sequencer_rst_reset_out_reset), // reset.reset + .s0_waitrequest (seq_waitrequest), // s0.waitrequest + .s0_readdata (seq_readdata), // .readdata + .s0_readdatavalid (seq_readdatavalid), // .readdatavalid + .s0_burstcount (seq_burstcount), // .burstcount + .s0_writedata (seq_writedata), // .writedata + .s0_address (seq_address), // .address + .s0_write (seq_write), // .write + .s0_read (seq_read), // .read + .s0_byteenable (seq_byteenable), // .byteenable + .s0_debugaccess (seq_debugaccess), // .debugaccess + .m0_waitrequest (seq_bridge_m0_waitrequest), // m0.waitrequest + .m0_readdata (seq_bridge_m0_readdata), // .readdata + .m0_readdatavalid (seq_bridge_m0_readdatavalid), // .readdatavalid + .m0_burstcount (seq_bridge_m0_burstcount), // .burstcount + .m0_writedata (seq_bridge_m0_writedata), // .writedata + .m0_address (seq_bridge_m0_address), // .address + .m0_write (seq_bridge_m0_write), // .write + .m0_read (seq_bridge_m0_read), // .read + .m0_byteenable (seq_bridge_m0_byteenable), // .byteenable + .m0_debugaccess (seq_bridge_m0_debugaccess), // .debugaccess + .s0_response (), // (terminated) + .m0_response (2'b00) // (terminated) + ); + + ddr3_s0_mm_interconnect_0 mm_interconnect_0 ( + .avl_clk_out_clk_clk (avl_clk), // avl_clk_out_clk.clk + .cpu_inst_reset_n_reset_bridge_in_reset_reset (sequencer_rst_reset_out_reset), // cpu_inst_reset_n_reset_bridge_in_reset.reset + .cpu_inst_data_master_address (cpu_inst_data_master_address), // cpu_inst_data_master.address + .cpu_inst_data_master_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest + .cpu_inst_data_master_byteenable (cpu_inst_data_master_byteenable), // .byteenable + .cpu_inst_data_master_read (cpu_inst_data_master_read), // .read + .cpu_inst_data_master_readdata (cpu_inst_data_master_readdata), // .readdata + .cpu_inst_data_master_write (cpu_inst_data_master_write), // .write + .cpu_inst_data_master_writedata (cpu_inst_data_master_writedata), // .writedata + .cpu_inst_instruction_master_address (cpu_inst_instruction_master_address), // cpu_inst_instruction_master.address + .cpu_inst_instruction_master_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest + .cpu_inst_instruction_master_read (cpu_inst_instruction_master_read), // .read + .cpu_inst_instruction_master_readdata (cpu_inst_instruction_master_readdata), // .readdata + .seq_bridge_m0_address (seq_bridge_m0_address), // seq_bridge_m0.address + .seq_bridge_m0_waitrequest (seq_bridge_m0_waitrequest), // .waitrequest + .seq_bridge_m0_burstcount (seq_bridge_m0_burstcount), // .burstcount + .seq_bridge_m0_byteenable (seq_bridge_m0_byteenable), // .byteenable + .seq_bridge_m0_read (seq_bridge_m0_read), // .read + .seq_bridge_m0_readdata (seq_bridge_m0_readdata), // .readdata + .seq_bridge_m0_readdatavalid (seq_bridge_m0_readdatavalid), // .readdatavalid + .seq_bridge_m0_write (seq_bridge_m0_write), // .write + .seq_bridge_m0_writedata (seq_bridge_m0_writedata), // .writedata + .seq_bridge_m0_debugaccess (seq_bridge_m0_debugaccess), // .debugaccess + .hphy_bridge_s0_address (mm_interconnect_0_hphy_bridge_s0_address), // hphy_bridge_s0.address + .hphy_bridge_s0_write (mm_interconnect_0_hphy_bridge_s0_write), // .write + .hphy_bridge_s0_read (mm_interconnect_0_hphy_bridge_s0_read), // .read + .hphy_bridge_s0_readdata (mm_interconnect_0_hphy_bridge_s0_readdata), // .readdata + .hphy_bridge_s0_writedata (mm_interconnect_0_hphy_bridge_s0_writedata), // .writedata + .hphy_bridge_s0_waitrequest (mm_interconnect_0_hphy_bridge_s0_waitrequest), // .waitrequest + .sequencer_mem_s1_address (mm_interconnect_0_sequencer_mem_s1_address), // sequencer_mem_s1.address + .sequencer_mem_s1_write (mm_interconnect_0_sequencer_mem_s1_write), // .write + .sequencer_mem_s1_readdata (mm_interconnect_0_sequencer_mem_s1_readdata), // .readdata + .sequencer_mem_s1_writedata (mm_interconnect_0_sequencer_mem_s1_writedata), // .writedata + .sequencer_mem_s1_byteenable (mm_interconnect_0_sequencer_mem_s1_byteenable), // .byteenable + .sequencer_mem_s1_chipselect (mm_interconnect_0_sequencer_mem_s1_chipselect), // .chipselect + .sequencer_reg_file_inst_avl_address (mm_interconnect_0_sequencer_reg_file_inst_avl_address), // sequencer_reg_file_inst_avl.address + .sequencer_reg_file_inst_avl_write (mm_interconnect_0_sequencer_reg_file_inst_avl_write), // .write + .sequencer_reg_file_inst_avl_read (mm_interconnect_0_sequencer_reg_file_inst_avl_read), // .read + .sequencer_reg_file_inst_avl_readdata (mm_interconnect_0_sequencer_reg_file_inst_avl_readdata), // .readdata + .sequencer_reg_file_inst_avl_writedata (mm_interconnect_0_sequencer_reg_file_inst_avl_writedata), // .writedata + .sequencer_reg_file_inst_avl_byteenable (mm_interconnect_0_sequencer_reg_file_inst_avl_byteenable), // .byteenable + .sequencer_reg_file_inst_avl_waitrequest (mm_interconnect_0_sequencer_reg_file_inst_avl_waitrequest), // .waitrequest + .sequencer_scc_mgr_inst_avl_address (mm_interconnect_0_sequencer_scc_mgr_inst_avl_address), // sequencer_scc_mgr_inst_avl.address + .sequencer_scc_mgr_inst_avl_write (mm_interconnect_0_sequencer_scc_mgr_inst_avl_write), // .write + .sequencer_scc_mgr_inst_avl_read (mm_interconnect_0_sequencer_scc_mgr_inst_avl_read), // .read + .sequencer_scc_mgr_inst_avl_readdata (mm_interconnect_0_sequencer_scc_mgr_inst_avl_readdata), // .readdata + .sequencer_scc_mgr_inst_avl_writedata (mm_interconnect_0_sequencer_scc_mgr_inst_avl_writedata), // .writedata + .sequencer_scc_mgr_inst_avl_waitrequest (mm_interconnect_0_sequencer_scc_mgr_inst_avl_waitrequest) // .waitrequest + ); + + ddr3_s0_irq_mapper irq_mapper ( + .clk (avl_clk), // clk.clk + .reset (sequencer_rst_reset_out_reset), // clk_reset.reset + .sender_irq (cpu_inst_d_irq_irq) // sender.irq + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_s0_AC_ROM.hex b/ip/altera/ddr3/ddr3_s0_AC_ROM.hex new file mode 100644 index 0000000..14e9b5d --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_AC_ROM.hex @@ -0,0 +1,41 @@ +:04000000207000006C +:040001002078000063 +:0400020010080231AF +:0400030010080330AE +:04000400100900409F +:04000500100A0008D5 +:04000600100B0000DB +:0400070010380400A9 +:040008001008024991 +:04000900100802C811 +:04000A00100A0020B8 +:04000B0010090010C8 +:04000C00100B0000D5 +:04000D003078000047 +:04000E00387800003E +:04000F003078000045 +:040010001068000074 +:04001100106B000070 +:0400120010280400AE +:040013001048000091 +:040014001C98000034 +:040015001C9B000030 +:040016001C9800082A +:040017001C9B000826 +:0400180038F80000B4 +:040019003CF80000AF +:04001A003878000032 +:04001B0018180000B1 +:04001C001898000030 +:04001D001358000074 +:04001E00135B000070 +:04001F00135800086A +:04002000135B000866 +:040021003378000030 +:04002200105800086A +:040023001078000051 +:0400240000000000D8 +:0400250000000000D7 +:0400260000000000D6 +:0400270000000000D5 +:00000001FF diff --git a/ip/altera/ddr3/ddr3_s0_inst_ROM.hex b/ip/altera/ddr3/ddr3_s0_inst_ROM.hex new file mode 100644 index 0000000..2824689 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_inst_ROM.hex @@ -0,0 +1,129 @@ +:03000000080000F5 +:030001000806806E +:03000200008180FA +:0300030000820078 +:03000400008280F7 +:0300050000830075 +:03000600008380F4 +:0300070000810075 +:03000800008480F1 +:030009000085006F +:03000A00008580EE +:03000B000086006C +:03000C000084006D +:03000D00000800E8 +:03000E00008680E9 +:03000F0000088066 +:0300100000A680C7 +:030011000806805E +:03001200000900E2 +:030013000806805C +:0300140000098060 +:0300150000A680C2 +:03001600008680E1 +:0300170008068058 +:03001800000B6872 +:0300190000CCE830 +:03001A00000AE8F1 +:03001B00008CE86E +:03001C00000B884E +:03001D0000EC886C +:03001E00000A08CD +:03001F0000AC88AA +:030020000806804F +:0300210000CE000E +:0300220000CD808E +:0300230000E700F3 +:03002400000C00CD +:03002500020CE0EA +:03002600020CE0E9 +:03002700020CE0E8 +:03002800020CE0E7 +:03002900000D00C7 +:03002A000006804D +:03002B000006804C +:03002C000006804B +:03002D000006804A +:03002E00060E803B +:03002F0006108038 +:0300300006108037 +:0300310006108036 +:0300320000A680A5 +:03003300008680C4 +:030034000806803B +:0300350000CE00FA +:0300360000CD807A +:0300370000E700DF +:03003800000C00B9 +:03003900030CE0D5 +:03003A00030CE0D4 +:03003B00030CE0D3 +:03003C00030CE0D2 +:03003D00000D00B3 +:03003E0000068039 +:03003F0000068038 +:0300400000068037 +:0300410000068036 +:03004200070E8026 +:0300430007108023 +:0300440007108022 +:0300450007108021 +:0300460000A68091 +:03004700008680B0 +:0300480008068027 +:030049000011584B +:03004A000006D8D5 +:03004B0008068024 +:03004C0000116838 +:03004D000007E8C1 +:03004E000007E8C0 +:03004F000087E83F +:03005000040FE8B2 +:030051000410E8B0 +:030052000410E8AF +:030053000410E8AE +:0300540000116830 +:030055000007E8B9 +:030056000007E8B8 +:0300570000A7E817 +:0300580008068017 +:03005900040E880A +:03005A0004108807 +:03005B0004108806 +:03005C0004108805 +:03005D00040F6825 +:03005E000410E8A3 +:03005F000410E8A2 +:030060000410E8A1 +:0300610000A68076 +:03006200040FE8A0 +:030063000410E89E +:030064000410E89D +:030065000410E89C +:030066000410087B +:03006700041088FA +:03006800041088F9 +:03006900041088F8 +:03006A0000110082 +:03006B0000C6804C +:03006C000086808B +:03006D0000E6802A +:03006E0008068001 +:03006F000000008E +:030070000080000D +:0300710000A000EC +:0300720000C000CB +:0300730008000082 +:0300740000008009 +:0300750000808088 +:0300760000A08067 +:0300770000C08046 +:03007800080080FD +:0300790000918073 +:03007A000086807D +:03007B0000A6805C +:03007C00080680F3 +:03007D00040F0865 +:03007E00080680F1 +:03007F000000007E +:00000001FF diff --git a/ip/altera/ddr3/ddr3_s0_irq_mapper.sv b/ip/altera/ddr3/ddr3_s0_irq_mapper.sv new file mode 100644 index 0000000..f0cd75e --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_irq_mapper.sv @@ -0,0 +1,58 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 0 +// SENDER_IRW_WIDTH : 32 +// IRQ_MAP : +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_s0_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [31 : 0] sender_irq +); + + initial sender_irq = 0; + + always @* begin + sender_irq = 0; + + end + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_make_qsys_seq.tcl b/ip/altera/ddr3/ddr3_s0_make_qsys_seq.tcl new file mode 100644 index 0000000..0b41c5c --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_make_qsys_seq.tcl @@ -0,0 +1,106 @@ +set arg_list [list] +lappend arg_list "--component-param=HPS_PROTOCOL=DDR3" +lappend arg_list "--component-param=RATE=Full" +lappend arg_list "--component-param=DLL_USE_DR_CLK=false" +lappend arg_list "--component-param=MEM_IF_READ_DQS_WIDTH=2" +lappend arg_list "--component-param=DUAL_WRITE_CLOCK=false" +lappend arg_list "--component-param=MEM_IF_DQ_WIDTH=16" +lappend arg_list "--component-param=MEM_IF_DM_WIDTH=2" +lappend arg_list "--component-param=MEM_BURST_LENGTH=8" +lappend arg_list "--component-param=DLL_DELAY_CHAIN_LENGTH=8" +lappend arg_list "--component-param=DELAY_PER_OPA_TAP=416" +lappend arg_list "--component-param=DELAY_PER_DCHAIN_TAP=25" +lappend arg_list "--component-param=MAX_LATENCY_COUNT_WIDTH=5" +lappend arg_list "--component-param=CALIB_VFIFO_OFFSET=6" +lappend arg_list "--component-param=CALIB_LFIFO_OFFSET=8" +lappend arg_list "--component-param=CALIB_REG_WIDTH=8" +lappend arg_list "--component-param=READ_VALID_FIFO_SIZE=16" +lappend arg_list "--component-param=MEM_T_WL=6" +lappend arg_list "--component-param=MEM_T_RL=7" +lappend arg_list "--component-param=AFI_ADDRESS_WIDTH=13" +lappend arg_list "--component-param=AFI_CONTROL_WIDTH=1" +lappend arg_list "--component-param=AFI_DATA_WIDTH=32" +lappend arg_list "--component-param=AFI_DATA_MASK_WIDTH=4" +lappend arg_list "--component-param=AFI_DQS_WIDTH=2" +lappend arg_list "--component-param=MEM_IF_WRITE_DQS_WIDTH=2" +lappend arg_list "--component-param=AFI_BANK_WIDTH=3" +lappend arg_list "--component-param=AFI_CHIP_SELECT_WIDTH=1" +lappend arg_list "--component-param=AFI_MAX_WRITE_LATENCY_COUNT_WIDTH=6" +lappend arg_list "--component-param=AFI_MAX_READ_LATENCY_COUNT_WIDTH=6" +lappend arg_list "--component-param=IO_DQS_EN_DELAY_OFFSET=0" +lappend arg_list "--component-param=MEM_TINIT_CK=150000" +lappend arg_list "--component-param=MEM_TMRD_CK=4" +lappend arg_list "--component-param=AFI_DEBUG_INFO_WIDTH=32" +lappend arg_list "--component-param=AFI_CLK_EN_WIDTH=1" +lappend arg_list "--component-param=AFI_ODT_WIDTH=1" +lappend arg_list "--component-param=MR0_BL=1" +lappend arg_list "--component-param=MR0_BT=0" +lappend arg_list "--component-param=MR0_CAS_LATENCY=3" +lappend arg_list "--component-param=MR0_WR=1" +lappend arg_list "--component-param=MR0_PD=0" +lappend arg_list "--component-param=MR1_DLL=0" +lappend arg_list "--component-param=MR1_ODS=0" +lappend arg_list "--component-param=MR1_RTT=2" +lappend arg_list "--component-param=MR1_AL=0" +lappend arg_list "--component-param=MR1_QOFF=0" +lappend arg_list "--component-param=RDIMM=0" +lappend arg_list "--component-param=LRDIMM=0" +lappend arg_list "--component-param=MR0_DLL=1" +lappend arg_list "--component-param=MR1_WL=0" +lappend arg_list "--component-param=MR1_TDQS=0" +lappend arg_list "--component-param=MR2_CWL=1" +lappend arg_list "--component-param=MR2_ASR=0" +lappend arg_list "--component-param=MR2_SRT=0" +lappend arg_list "--component-param=MR2_RTT_WR=0" +lappend arg_list "--component-param=MR3_MPR_RF=0" +lappend arg_list "--component-param=MR3_MPR=0" +lappend arg_list "--component-param=RDIMM_CONFIG=0" +lappend arg_list "--component-param=LRDIMM_EXTENDED_CONFIG=0x0" +lappend arg_list "--component-param=MEM_NUMBER_OF_RANKS=1" +lappend arg_list "--component-param=MEM_CLK_EN_WIDTH=1" +lappend arg_list "--component-param=MEM_ODT_WIDTH=1" +lappend arg_list "--component-param=MEM_BANK_WIDTH=3" +lappend arg_list "--component-param=MEM_ADDRESS_WIDTH=13" +lappend arg_list "--component-param=MEM_CONTROL_WIDTH=1" +lappend arg_list "--component-param=MEM_CHIP_SELECT_WIDTH=1" +lappend arg_list "--component-param=USE_DQS_TRACKING=false" +lappend arg_list "--component-param=USE_SHADOW_REGS=false" +lappend arg_list "--component-param=HCX_COMPAT_MODE=false" +lappend arg_list "--component-param=NUM_WRITE_FR_CYCLE_SHIFTS=0" +lappend arg_list "--component-param=SEQUENCER_VERSION=15.1" +lappend arg_list "--component-param=ENABLE_NON_DESTRUCTIVE_CALIB=false" +lappend arg_list "--component-param=ENABLE_NON_DES_CAL=false" +lappend arg_list "--component-param=ENABLE_NON_DES_CAL_TEST=false" +lappend arg_list "--component-param=AP_MODE_EN=0" +lappend arg_list "--component-param=USE_USER_RDIMM_VALUE==false" +lappend arg_list "--component-param=MRS_MIRROR_PING_PONG_ATSO=false" +lappend arg_list "--component-param=ENABLE_NIOS_OCI=false" +lappend arg_list "--component-param=ENABLE_DEBUG_BRIDGE=true" +lappend arg_list "--component-param=MAKE_INTERNAL_NIOS_VISIBLE=false" +lappend arg_list "--component-param=ENABLE_NIOS_JTAG_UART=false" +lappend arg_list "--component-param=ENABLE_LARGE_RW_MGR_DI_BUFFER=false" +lappend arg_list "--component-param=SEQ_ROM=ddr3_s0_sequencer_mem.hex" +lappend arg_list "--component-param=RAM_BLOCK_TYPE=AUTO" +lappend arg_list "--component-param=AC_ROM_INIT_FILE_NAME=ddr3_s0_AC_ROM.hex" +lappend arg_list "--component-param=INST_ROM_INIT_FILE_NAME=ddr3_s0_inst_ROM.hex" +lappend arg_list "--component-param=HARD_PHY=true" +lappend arg_list "--component-param=USE_SEQUENCER_BFM=false" +lappend arg_list "--component-param=HHP_HPS=false" +lappend arg_list "--component-param=MAX10_RTL_SEQ=false" +lappend arg_list "--component-param=HARD_VFIFO=1" +lappend arg_list "--component-param=SEQUENCER_MEM_SIZE=23552" +lappend arg_list "--component-param=SEQUENCER_MEM_ADDRESS_WIDTH=13" +lappend arg_list "--component-param=TRK_PARALLEL_SCC_LOAD=false" +lappend arg_list "--component-param=SCC_DATA_WIDTH=1" +lappend arg_list "--component-param=AVL_CLK_PS=16667" +lappend arg_list "--component-param=AFI_CLK_PS=3333" +lappend arg_list "--component-param=TREFI=35100" +lappend arg_list "--component-param=TRFC=350" +lappend arg_list "--component-param=REFRESH_INTERVAL=15000" +lappend arg_list "--output-name=ddr3_s0" +lappend arg_list "--system-info=DEVICE_FAMILY=CYCLONEV" +lappend arg_list "--report-file=sopcinfo:ddr3_s0.sopcinfo" +lappend arg_list "--report-file=txt:ddr3_s0_seq_ipd_report.txt" +lappend arg_list "--file-set=QUARTUS_SYNTH" +catch { eval [concat [list exec "/opt/altera/15.1/quartus//sopc_builder/bin/ip-generate" --component-name=qsys_sequencer_110] $arg_list] } temp +puts $temp diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0.v b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0.v new file mode 100644 index 0000000..d3c62ea --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0.v @@ -0,0 +1,2200 @@ +// ddr3_s0_mm_interconnect_0.v + +// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_s0_mm_interconnect_0 ( + input wire avl_clk_out_clk_clk, // avl_clk_out_clk.clk + input wire cpu_inst_reset_n_reset_bridge_in_reset_reset, // cpu_inst_reset_n_reset_bridge_in_reset.reset + input wire [19:0] cpu_inst_data_master_address, // cpu_inst_data_master.address + output wire cpu_inst_data_master_waitrequest, // .waitrequest + input wire [3:0] cpu_inst_data_master_byteenable, // .byteenable + input wire cpu_inst_data_master_read, // .read + output wire [31:0] cpu_inst_data_master_readdata, // .readdata + input wire cpu_inst_data_master_write, // .write + input wire [31:0] cpu_inst_data_master_writedata, // .writedata + input wire [16:0] cpu_inst_instruction_master_address, // cpu_inst_instruction_master.address + output wire cpu_inst_instruction_master_waitrequest, // .waitrequest + input wire cpu_inst_instruction_master_read, // .read + output wire [31:0] cpu_inst_instruction_master_readdata, // .readdata + input wire [31:0] seq_bridge_m0_address, // seq_bridge_m0.address + output wire seq_bridge_m0_waitrequest, // .waitrequest + input wire [0:0] seq_bridge_m0_burstcount, // .burstcount + input wire [3:0] seq_bridge_m0_byteenable, // .byteenable + input wire seq_bridge_m0_read, // .read + output wire [31:0] seq_bridge_m0_readdata, // .readdata + output wire seq_bridge_m0_readdatavalid, // .readdatavalid + input wire seq_bridge_m0_write, // .write + input wire [31:0] seq_bridge_m0_writedata, // .writedata + input wire seq_bridge_m0_debugaccess, // .debugaccess + output wire [15:0] hphy_bridge_s0_address, // hphy_bridge_s0.address + output wire hphy_bridge_s0_write, // .write + output wire hphy_bridge_s0_read, // .read + input wire [31:0] hphy_bridge_s0_readdata, // .readdata + output wire [31:0] hphy_bridge_s0_writedata, // .writedata + input wire hphy_bridge_s0_waitrequest, // .waitrequest + output wire [12:0] sequencer_mem_s1_address, // sequencer_mem_s1.address + output wire sequencer_mem_s1_write, // .write + input wire [31:0] sequencer_mem_s1_readdata, // .readdata + output wire [31:0] sequencer_mem_s1_writedata, // .writedata + output wire [3:0] sequencer_mem_s1_byteenable, // .byteenable + output wire sequencer_mem_s1_chipselect, // .chipselect + output wire [3:0] sequencer_reg_file_inst_avl_address, // sequencer_reg_file_inst_avl.address + output wire sequencer_reg_file_inst_avl_write, // .write + output wire sequencer_reg_file_inst_avl_read, // .read + input wire [31:0] sequencer_reg_file_inst_avl_readdata, // .readdata + output wire [31:0] sequencer_reg_file_inst_avl_writedata, // .writedata + output wire [3:0] sequencer_reg_file_inst_avl_byteenable, // .byteenable + input wire sequencer_reg_file_inst_avl_waitrequest, // .waitrequest + output wire [12:0] sequencer_scc_mgr_inst_avl_address, // sequencer_scc_mgr_inst_avl.address + output wire sequencer_scc_mgr_inst_avl_write, // .write + output wire sequencer_scc_mgr_inst_avl_read, // .read + input wire [31:0] sequencer_scc_mgr_inst_avl_readdata, // .readdata + output wire [31:0] sequencer_scc_mgr_inst_avl_writedata, // .writedata + input wire sequencer_scc_mgr_inst_avl_waitrequest // .waitrequest + ); + + wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest + wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata + wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess + wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address + wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read + wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable + wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid + wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock + wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write + wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata + wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount + wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid + wire [105:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data + wire rsp_mux_src_ready; // cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready + wire [3:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel + wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket + wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket + wire seq_bridge_m0_translator_avalon_universal_master_0_waitrequest; // seq_bridge_m0_agent:av_waitrequest -> seq_bridge_m0_translator:uav_waitrequest + wire [31:0] seq_bridge_m0_translator_avalon_universal_master_0_readdata; // seq_bridge_m0_agent:av_readdata -> seq_bridge_m0_translator:uav_readdata + wire seq_bridge_m0_translator_avalon_universal_master_0_debugaccess; // seq_bridge_m0_translator:uav_debugaccess -> seq_bridge_m0_agent:av_debugaccess + wire [31:0] seq_bridge_m0_translator_avalon_universal_master_0_address; // seq_bridge_m0_translator:uav_address -> seq_bridge_m0_agent:av_address + wire seq_bridge_m0_translator_avalon_universal_master_0_read; // seq_bridge_m0_translator:uav_read -> seq_bridge_m0_agent:av_read + wire [3:0] seq_bridge_m0_translator_avalon_universal_master_0_byteenable; // seq_bridge_m0_translator:uav_byteenable -> seq_bridge_m0_agent:av_byteenable + wire seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // seq_bridge_m0_agent:av_readdatavalid -> seq_bridge_m0_translator:uav_readdatavalid + wire seq_bridge_m0_translator_avalon_universal_master_0_lock; // seq_bridge_m0_translator:uav_lock -> seq_bridge_m0_agent:av_lock + wire seq_bridge_m0_translator_avalon_universal_master_0_write; // seq_bridge_m0_translator:uav_write -> seq_bridge_m0_agent:av_write + wire [31:0] seq_bridge_m0_translator_avalon_universal_master_0_writedata; // seq_bridge_m0_translator:uav_writedata -> seq_bridge_m0_agent:av_writedata + wire [2:0] seq_bridge_m0_translator_avalon_universal_master_0_burstcount; // seq_bridge_m0_translator:uav_burstcount -> seq_bridge_m0_agent:av_burstcount + wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest + wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata + wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_agent:av_debugaccess + wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_agent:av_address + wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_agent:av_read + wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_agent:av_byteenable + wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid + wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_agent:av_lock + wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_agent:av_write + wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_agent:av_writedata + wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_agent:av_burstcount + wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> cpu_inst_instruction_master_agent:rp_valid + wire [105:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> cpu_inst_instruction_master_agent:rp_data + wire rsp_mux_002_src_ready; // cpu_inst_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready + wire [3:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> cpu_inst_instruction_master_agent:rp_channel + wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> cpu_inst_instruction_master_agent:rp_startofpacket + wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> cpu_inst_instruction_master_agent:rp_endofpacket + wire [31:0] hphy_bridge_s0_agent_m0_readdata; // hphy_bridge_s0_translator:uav_readdata -> hphy_bridge_s0_agent:m0_readdata + wire hphy_bridge_s0_agent_m0_waitrequest; // hphy_bridge_s0_translator:uav_waitrequest -> hphy_bridge_s0_agent:m0_waitrequest + wire hphy_bridge_s0_agent_m0_debugaccess; // hphy_bridge_s0_agent:m0_debugaccess -> hphy_bridge_s0_translator:uav_debugaccess + wire [31:0] hphy_bridge_s0_agent_m0_address; // hphy_bridge_s0_agent:m0_address -> hphy_bridge_s0_translator:uav_address + wire [3:0] hphy_bridge_s0_agent_m0_byteenable; // hphy_bridge_s0_agent:m0_byteenable -> hphy_bridge_s0_translator:uav_byteenable + wire hphy_bridge_s0_agent_m0_read; // hphy_bridge_s0_agent:m0_read -> hphy_bridge_s0_translator:uav_read + wire hphy_bridge_s0_agent_m0_readdatavalid; // hphy_bridge_s0_translator:uav_readdatavalid -> hphy_bridge_s0_agent:m0_readdatavalid + wire hphy_bridge_s0_agent_m0_lock; // hphy_bridge_s0_agent:m0_lock -> hphy_bridge_s0_translator:uav_lock + wire [31:0] hphy_bridge_s0_agent_m0_writedata; // hphy_bridge_s0_agent:m0_writedata -> hphy_bridge_s0_translator:uav_writedata + wire hphy_bridge_s0_agent_m0_write; // hphy_bridge_s0_agent:m0_write -> hphy_bridge_s0_translator:uav_write + wire [2:0] hphy_bridge_s0_agent_m0_burstcount; // hphy_bridge_s0_agent:m0_burstcount -> hphy_bridge_s0_translator:uav_burstcount + wire hphy_bridge_s0_agent_rf_source_valid; // hphy_bridge_s0_agent:rf_source_valid -> hphy_bridge_s0_agent_rsp_fifo:in_valid + wire [106:0] hphy_bridge_s0_agent_rf_source_data; // hphy_bridge_s0_agent:rf_source_data -> hphy_bridge_s0_agent_rsp_fifo:in_data + wire hphy_bridge_s0_agent_rf_source_ready; // hphy_bridge_s0_agent_rsp_fifo:in_ready -> hphy_bridge_s0_agent:rf_source_ready + wire hphy_bridge_s0_agent_rf_source_startofpacket; // hphy_bridge_s0_agent:rf_source_startofpacket -> hphy_bridge_s0_agent_rsp_fifo:in_startofpacket + wire hphy_bridge_s0_agent_rf_source_endofpacket; // hphy_bridge_s0_agent:rf_source_endofpacket -> hphy_bridge_s0_agent_rsp_fifo:in_endofpacket + wire hphy_bridge_s0_agent_rsp_fifo_out_valid; // hphy_bridge_s0_agent_rsp_fifo:out_valid -> hphy_bridge_s0_agent:rf_sink_valid + wire [106:0] hphy_bridge_s0_agent_rsp_fifo_out_data; // hphy_bridge_s0_agent_rsp_fifo:out_data -> hphy_bridge_s0_agent:rf_sink_data + wire hphy_bridge_s0_agent_rsp_fifo_out_ready; // hphy_bridge_s0_agent:rf_sink_ready -> hphy_bridge_s0_agent_rsp_fifo:out_ready + wire hphy_bridge_s0_agent_rsp_fifo_out_startofpacket; // hphy_bridge_s0_agent_rsp_fifo:out_startofpacket -> hphy_bridge_s0_agent:rf_sink_startofpacket + wire hphy_bridge_s0_agent_rsp_fifo_out_endofpacket; // hphy_bridge_s0_agent_rsp_fifo:out_endofpacket -> hphy_bridge_s0_agent:rf_sink_endofpacket + wire cmd_mux_src_valid; // cmd_mux:src_valid -> hphy_bridge_s0_agent:cp_valid + wire [105:0] cmd_mux_src_data; // cmd_mux:src_data -> hphy_bridge_s0_agent:cp_data + wire cmd_mux_src_ready; // hphy_bridge_s0_agent:cp_ready -> cmd_mux:src_ready + wire [3:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hphy_bridge_s0_agent:cp_channel + wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hphy_bridge_s0_agent:cp_startofpacket + wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hphy_bridge_s0_agent:cp_endofpacket + wire [31:0] sequencer_mem_s1_agent_m0_readdata; // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_agent:m0_readdata + wire sequencer_mem_s1_agent_m0_waitrequest; // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_agent:m0_waitrequest + wire sequencer_mem_s1_agent_m0_debugaccess; // sequencer_mem_s1_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess + wire [31:0] sequencer_mem_s1_agent_m0_address; // sequencer_mem_s1_agent:m0_address -> sequencer_mem_s1_translator:uav_address + wire [3:0] sequencer_mem_s1_agent_m0_byteenable; // sequencer_mem_s1_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable + wire sequencer_mem_s1_agent_m0_read; // sequencer_mem_s1_agent:m0_read -> sequencer_mem_s1_translator:uav_read + wire sequencer_mem_s1_agent_m0_readdatavalid; // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_agent:m0_readdatavalid + wire sequencer_mem_s1_agent_m0_lock; // sequencer_mem_s1_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock + wire [31:0] sequencer_mem_s1_agent_m0_writedata; // sequencer_mem_s1_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata + wire sequencer_mem_s1_agent_m0_write; // sequencer_mem_s1_agent:m0_write -> sequencer_mem_s1_translator:uav_write + wire [2:0] sequencer_mem_s1_agent_m0_burstcount; // sequencer_mem_s1_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount + wire sequencer_mem_s1_agent_rf_source_valid; // sequencer_mem_s1_agent:rf_source_valid -> sequencer_mem_s1_agent_rsp_fifo:in_valid + wire [106:0] sequencer_mem_s1_agent_rf_source_data; // sequencer_mem_s1_agent:rf_source_data -> sequencer_mem_s1_agent_rsp_fifo:in_data + wire sequencer_mem_s1_agent_rf_source_ready; // sequencer_mem_s1_agent_rsp_fifo:in_ready -> sequencer_mem_s1_agent:rf_source_ready + wire sequencer_mem_s1_agent_rf_source_startofpacket; // sequencer_mem_s1_agent:rf_source_startofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_startofpacket + wire sequencer_mem_s1_agent_rf_source_endofpacket; // sequencer_mem_s1_agent:rf_source_endofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_endofpacket + wire sequencer_mem_s1_agent_rsp_fifo_out_valid; // sequencer_mem_s1_agent_rsp_fifo:out_valid -> sequencer_mem_s1_agent:rf_sink_valid + wire [106:0] sequencer_mem_s1_agent_rsp_fifo_out_data; // sequencer_mem_s1_agent_rsp_fifo:out_data -> sequencer_mem_s1_agent:rf_sink_data + wire sequencer_mem_s1_agent_rsp_fifo_out_ready; // sequencer_mem_s1_agent:rf_sink_ready -> sequencer_mem_s1_agent_rsp_fifo:out_ready + wire sequencer_mem_s1_agent_rsp_fifo_out_startofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_agent:rf_sink_startofpacket + wire sequencer_mem_s1_agent_rsp_fifo_out_endofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_agent:rf_sink_endofpacket + wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sequencer_mem_s1_agent:cp_valid + wire [105:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sequencer_mem_s1_agent:cp_data + wire cmd_mux_001_src_ready; // sequencer_mem_s1_agent:cp_ready -> cmd_mux_001:src_ready + wire [3:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sequencer_mem_s1_agent:cp_channel + wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sequencer_mem_s1_agent:cp_startofpacket + wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sequencer_mem_s1_agent:cp_endofpacket + wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_agent:m0_readdata + wire sequencer_scc_mgr_inst_avl_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_agent:m0_waitrequest + wire sequencer_scc_mgr_inst_avl_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess + wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_address; // sequencer_scc_mgr_inst_avl_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address + wire [3:0] sequencer_scc_mgr_inst_avl_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable + wire sequencer_scc_mgr_inst_avl_agent_m0_read; // sequencer_scc_mgr_inst_avl_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read + wire sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_agent:m0_readdatavalid + wire sequencer_scc_mgr_inst_avl_agent_m0_lock; // sequencer_scc_mgr_inst_avl_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock + wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata + wire sequencer_scc_mgr_inst_avl_agent_m0_write; // sequencer_scc_mgr_inst_avl_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write + wire [2:0] sequencer_scc_mgr_inst_avl_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount + wire sequencer_scc_mgr_inst_avl_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_valid + wire [106:0] sequencer_scc_mgr_inst_avl_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_data + wire sequencer_scc_mgr_inst_avl_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_agent:rf_source_ready + wire sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_startofpacket + wire sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_endofpacket + wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_agent:rf_sink_valid + wire [106:0] sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_agent:rf_sink_data + wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_ready + wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_startofpacket + wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_endofpacket + wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sequencer_scc_mgr_inst_avl_agent:cp_valid + wire [105:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sequencer_scc_mgr_inst_avl_agent:cp_data + wire cmd_mux_002_src_ready; // sequencer_scc_mgr_inst_avl_agent:cp_ready -> cmd_mux_002:src_ready + wire [3:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sequencer_scc_mgr_inst_avl_agent:cp_channel + wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_startofpacket + wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_endofpacket + wire [31:0] sequencer_reg_file_inst_avl_agent_m0_readdata; // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_agent:m0_readdata + wire sequencer_reg_file_inst_avl_agent_m0_waitrequest; // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_agent:m0_waitrequest + wire sequencer_reg_file_inst_avl_agent_m0_debugaccess; // sequencer_reg_file_inst_avl_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess + wire [31:0] sequencer_reg_file_inst_avl_agent_m0_address; // sequencer_reg_file_inst_avl_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address + wire [3:0] sequencer_reg_file_inst_avl_agent_m0_byteenable; // sequencer_reg_file_inst_avl_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable + wire sequencer_reg_file_inst_avl_agent_m0_read; // sequencer_reg_file_inst_avl_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read + wire sequencer_reg_file_inst_avl_agent_m0_readdatavalid; // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_agent:m0_readdatavalid + wire sequencer_reg_file_inst_avl_agent_m0_lock; // sequencer_reg_file_inst_avl_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock + wire [31:0] sequencer_reg_file_inst_avl_agent_m0_writedata; // sequencer_reg_file_inst_avl_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata + wire sequencer_reg_file_inst_avl_agent_m0_write; // sequencer_reg_file_inst_avl_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write + wire [2:0] sequencer_reg_file_inst_avl_agent_m0_burstcount; // sequencer_reg_file_inst_avl_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount + wire sequencer_reg_file_inst_avl_agent_rf_source_valid; // sequencer_reg_file_inst_avl_agent:rf_source_valid -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_valid + wire [106:0] sequencer_reg_file_inst_avl_agent_rf_source_data; // sequencer_reg_file_inst_avl_agent:rf_source_data -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_data + wire sequencer_reg_file_inst_avl_agent_rf_source_ready; // sequencer_reg_file_inst_avl_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_agent:rf_source_ready + wire sequencer_reg_file_inst_avl_agent_rf_source_startofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_startofpacket + wire sequencer_reg_file_inst_avl_agent_rf_source_endofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_endofpacket + wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_agent:rf_sink_valid + wire [106:0] sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_agent:rf_sink_data + wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready; // sequencer_reg_file_inst_avl_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_agent_rsp_fifo:out_ready + wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_startofpacket + wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_endofpacket + wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sequencer_reg_file_inst_avl_agent:cp_valid + wire [105:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sequencer_reg_file_inst_avl_agent:cp_data + wire cmd_mux_003_src_ready; // sequencer_reg_file_inst_avl_agent:cp_ready -> cmd_mux_003:src_ready + wire [3:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sequencer_reg_file_inst_avl_agent:cp_channel + wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sequencer_reg_file_inst_avl_agent:cp_startofpacket + wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sequencer_reg_file_inst_avl_agent:cp_endofpacket + wire cpu_inst_data_master_agent_cp_valid; // cpu_inst_data_master_agent:cp_valid -> router:sink_valid + wire [105:0] cpu_inst_data_master_agent_cp_data; // cpu_inst_data_master_agent:cp_data -> router:sink_data + wire cpu_inst_data_master_agent_cp_ready; // router:sink_ready -> cpu_inst_data_master_agent:cp_ready + wire cpu_inst_data_master_agent_cp_startofpacket; // cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket + wire cpu_inst_data_master_agent_cp_endofpacket; // cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket + wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid + wire [105:0] router_src_data; // router:src_data -> cmd_demux:sink_data + wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready + wire [3:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel + wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket + wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket + wire seq_bridge_m0_agent_cp_valid; // seq_bridge_m0_agent:cp_valid -> router_001:sink_valid + wire [105:0] seq_bridge_m0_agent_cp_data; // seq_bridge_m0_agent:cp_data -> router_001:sink_data + wire seq_bridge_m0_agent_cp_ready; // router_001:sink_ready -> seq_bridge_m0_agent:cp_ready + wire seq_bridge_m0_agent_cp_startofpacket; // seq_bridge_m0_agent:cp_startofpacket -> router_001:sink_startofpacket + wire seq_bridge_m0_agent_cp_endofpacket; // seq_bridge_m0_agent:cp_endofpacket -> router_001:sink_endofpacket + wire cpu_inst_instruction_master_agent_cp_valid; // cpu_inst_instruction_master_agent:cp_valid -> router_002:sink_valid + wire [105:0] cpu_inst_instruction_master_agent_cp_data; // cpu_inst_instruction_master_agent:cp_data -> router_002:sink_data + wire cpu_inst_instruction_master_agent_cp_ready; // router_002:sink_ready -> cpu_inst_instruction_master_agent:cp_ready + wire cpu_inst_instruction_master_agent_cp_startofpacket; // cpu_inst_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket + wire cpu_inst_instruction_master_agent_cp_endofpacket; // cpu_inst_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket + wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid + wire [105:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data + wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready + wire [3:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel + wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket + wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket + wire hphy_bridge_s0_agent_rp_valid; // hphy_bridge_s0_agent:rp_valid -> router_003:sink_valid + wire [105:0] hphy_bridge_s0_agent_rp_data; // hphy_bridge_s0_agent:rp_data -> router_003:sink_data + wire hphy_bridge_s0_agent_rp_ready; // router_003:sink_ready -> hphy_bridge_s0_agent:rp_ready + wire hphy_bridge_s0_agent_rp_startofpacket; // hphy_bridge_s0_agent:rp_startofpacket -> router_003:sink_startofpacket + wire hphy_bridge_s0_agent_rp_endofpacket; // hphy_bridge_s0_agent:rp_endofpacket -> router_003:sink_endofpacket + wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid + wire [105:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data + wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready + wire [3:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel + wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket + wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket + wire sequencer_mem_s1_agent_rp_valid; // sequencer_mem_s1_agent:rp_valid -> router_004:sink_valid + wire [105:0] sequencer_mem_s1_agent_rp_data; // sequencer_mem_s1_agent:rp_data -> router_004:sink_data + wire sequencer_mem_s1_agent_rp_ready; // router_004:sink_ready -> sequencer_mem_s1_agent:rp_ready + wire sequencer_mem_s1_agent_rp_startofpacket; // sequencer_mem_s1_agent:rp_startofpacket -> router_004:sink_startofpacket + wire sequencer_mem_s1_agent_rp_endofpacket; // sequencer_mem_s1_agent:rp_endofpacket -> router_004:sink_endofpacket + wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid + wire [105:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data + wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready + wire [3:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel + wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket + wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket + wire sequencer_scc_mgr_inst_avl_agent_rp_valid; // sequencer_scc_mgr_inst_avl_agent:rp_valid -> router_005:sink_valid + wire [105:0] sequencer_scc_mgr_inst_avl_agent_rp_data; // sequencer_scc_mgr_inst_avl_agent:rp_data -> router_005:sink_data + wire sequencer_scc_mgr_inst_avl_agent_rp_ready; // router_005:sink_ready -> sequencer_scc_mgr_inst_avl_agent:rp_ready + wire sequencer_scc_mgr_inst_avl_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_startofpacket -> router_005:sink_startofpacket + wire sequencer_scc_mgr_inst_avl_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_endofpacket -> router_005:sink_endofpacket + wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid + wire [105:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data + wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready + wire [3:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel + wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket + wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket + wire sequencer_reg_file_inst_avl_agent_rp_valid; // sequencer_reg_file_inst_avl_agent:rp_valid -> router_006:sink_valid + wire [105:0] sequencer_reg_file_inst_avl_agent_rp_data; // sequencer_reg_file_inst_avl_agent:rp_data -> router_006:sink_data + wire sequencer_reg_file_inst_avl_agent_rp_ready; // router_006:sink_ready -> sequencer_reg_file_inst_avl_agent:rp_ready + wire sequencer_reg_file_inst_avl_agent_rp_startofpacket; // sequencer_reg_file_inst_avl_agent:rp_startofpacket -> router_006:sink_startofpacket + wire sequencer_reg_file_inst_avl_agent_rp_endofpacket; // sequencer_reg_file_inst_avl_agent:rp_endofpacket -> router_006:sink_endofpacket + wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid + wire [105:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data + wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready + wire [3:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel + wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket + wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket + wire router_001_src_valid; // router_001:src_valid -> seq_bridge_m0_limiter:cmd_sink_valid + wire [105:0] router_001_src_data; // router_001:src_data -> seq_bridge_m0_limiter:cmd_sink_data + wire router_001_src_ready; // seq_bridge_m0_limiter:cmd_sink_ready -> router_001:src_ready + wire [3:0] router_001_src_channel; // router_001:src_channel -> seq_bridge_m0_limiter:cmd_sink_channel + wire router_001_src_startofpacket; // router_001:src_startofpacket -> seq_bridge_m0_limiter:cmd_sink_startofpacket + wire router_001_src_endofpacket; // router_001:src_endofpacket -> seq_bridge_m0_limiter:cmd_sink_endofpacket + wire [105:0] seq_bridge_m0_limiter_cmd_src_data; // seq_bridge_m0_limiter:cmd_src_data -> cmd_demux_001:sink_data + wire seq_bridge_m0_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> seq_bridge_m0_limiter:cmd_src_ready + wire [3:0] seq_bridge_m0_limiter_cmd_src_channel; // seq_bridge_m0_limiter:cmd_src_channel -> cmd_demux_001:sink_channel + wire seq_bridge_m0_limiter_cmd_src_startofpacket; // seq_bridge_m0_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket + wire seq_bridge_m0_limiter_cmd_src_endofpacket; // seq_bridge_m0_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket + wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> seq_bridge_m0_limiter:rsp_sink_valid + wire [105:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> seq_bridge_m0_limiter:rsp_sink_data + wire rsp_mux_001_src_ready; // seq_bridge_m0_limiter:rsp_sink_ready -> rsp_mux_001:src_ready + wire [3:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> seq_bridge_m0_limiter:rsp_sink_channel + wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> seq_bridge_m0_limiter:rsp_sink_startofpacket + wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> seq_bridge_m0_limiter:rsp_sink_endofpacket + wire seq_bridge_m0_limiter_rsp_src_valid; // seq_bridge_m0_limiter:rsp_src_valid -> seq_bridge_m0_agent:rp_valid + wire [105:0] seq_bridge_m0_limiter_rsp_src_data; // seq_bridge_m0_limiter:rsp_src_data -> seq_bridge_m0_agent:rp_data + wire seq_bridge_m0_limiter_rsp_src_ready; // seq_bridge_m0_agent:rp_ready -> seq_bridge_m0_limiter:rsp_src_ready + wire [3:0] seq_bridge_m0_limiter_rsp_src_channel; // seq_bridge_m0_limiter:rsp_src_channel -> seq_bridge_m0_agent:rp_channel + wire seq_bridge_m0_limiter_rsp_src_startofpacket; // seq_bridge_m0_limiter:rsp_src_startofpacket -> seq_bridge_m0_agent:rp_startofpacket + wire seq_bridge_m0_limiter_rsp_src_endofpacket; // seq_bridge_m0_limiter:rsp_src_endofpacket -> seq_bridge_m0_agent:rp_endofpacket + wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid + wire [105:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data + wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready + wire [3:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel + wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket + wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket + wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid + wire [105:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data + wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready + wire [3:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel + wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket + wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket + wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid + wire [105:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data + wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready + wire [3:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel + wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket + wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket + wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid + wire [105:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data + wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready + wire [3:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel + wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket + wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket + wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid + wire [105:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data + wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready + wire [3:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel + wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket + wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket + wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_003:sink1_valid + wire [105:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_003:sink1_data + wire cmd_demux_001_src1_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src1_ready + wire [3:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_003:sink1_channel + wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_003:sink1_startofpacket + wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_003:sink1_endofpacket + wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux_001:sink2_valid + wire [105:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux_001:sink2_data + wire cmd_demux_002_src0_ready; // cmd_mux_001:sink2_ready -> cmd_demux_002:src0_ready + wire [3:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux_001:sink2_channel + wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux_001:sink2_startofpacket + wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux_001:sink2_endofpacket + wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid + wire [105:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data + wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready + wire [3:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel + wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket + wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket + wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid + wire [105:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data + wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready + wire [3:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel + wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket + wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket + wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid + wire [105:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data + wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready + wire [3:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel + wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket + wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket + wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> rsp_mux_002:sink0_valid + wire [105:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> rsp_mux_002:sink0_data + wire rsp_demux_001_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux_001:src2_ready + wire [3:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> rsp_mux_002:sink0_channel + wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> rsp_mux_002:sink0_startofpacket + wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> rsp_mux_002:sink0_endofpacket + wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid + wire [105:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data + wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready + wire [3:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel + wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket + wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket + wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid + wire [105:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data + wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready + wire [3:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel + wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket + wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket + wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink1_valid + wire [105:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink1_data + wire rsp_demux_003_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_003:src1_ready + wire [3:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink1_channel + wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink1_startofpacket + wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink1_endofpacket + wire [3:0] seq_bridge_m0_limiter_cmd_valid_data; // seq_bridge_m0_limiter:cmd_src_valid -> cmd_demux_001:sink_valid + wire hphy_bridge_s0_agent_rdata_fifo_src_valid; // hphy_bridge_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid + wire [33:0] hphy_bridge_s0_agent_rdata_fifo_src_data; // hphy_bridge_s0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data + wire hphy_bridge_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> hphy_bridge_s0_agent:rdata_fifo_src_ready + wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> hphy_bridge_s0_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> hphy_bridge_s0_agent:rdata_fifo_sink_data + wire avalon_st_adapter_out_0_ready; // hphy_bridge_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready + wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> hphy_bridge_s0_agent:rdata_fifo_sink_error + wire sequencer_mem_s1_agent_rdata_fifo_src_valid; // sequencer_mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid + wire [33:0] sequencer_mem_s1_agent_rdata_fifo_src_data; // sequencer_mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data + wire sequencer_mem_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> sequencer_mem_s1_agent:rdata_fifo_src_ready + wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> sequencer_mem_s1_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> sequencer_mem_s1_agent:rdata_fifo_sink_data + wire avalon_st_adapter_001_out_0_ready; // sequencer_mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready + wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> sequencer_mem_s1_agent:rdata_fifo_sink_error + wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid + wire [33:0] sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data + wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_ready + wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_data + wire avalon_st_adapter_002_out_0_ready; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready + wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_error + wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid + wire [33:0] sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data + wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sequencer_reg_file_inst_avl_agent:rdata_fifo_src_ready + wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_data + wire avalon_st_adapter_003_out_0_ready; // sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready + wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_error + + altera_merlin_master_translator #( + .AV_ADDRESS_W (20), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (1) + ) cpu_inst_data_master_translator ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read + .uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address + .av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest + .av_byteenable (cpu_inst_data_master_byteenable), // .byteenable + .av_read (cpu_inst_data_master_read), // .read + .av_readdata (cpu_inst_data_master_readdata), // .readdata + .av_write (cpu_inst_data_master_write), // .write + .av_writedata (cpu_inst_data_master_writedata), // .writedata + .av_burstcount (1'b1), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_readdatavalid (), // (terminated) + .av_lock (1'b0), // (terminated) + .av_debugaccess (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (32), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (1), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (0) + ) seq_bridge_m0_translator ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (seq_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (seq_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (seq_bridge_m0_translator_avalon_universal_master_0_read), // .read + .uav_write (seq_bridge_m0_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (seq_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (seq_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (seq_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (seq_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (seq_bridge_m0_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (seq_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (seq_bridge_m0_address), // avalon_anti_master_0.address + .av_waitrequest (seq_bridge_m0_waitrequest), // .waitrequest + .av_burstcount (seq_bridge_m0_burstcount), // .burstcount + .av_byteenable (seq_bridge_m0_byteenable), // .byteenable + .av_read (seq_bridge_m0_read), // .read + .av_readdata (seq_bridge_m0_readdata), // .readdata + .av_readdatavalid (seq_bridge_m0_readdatavalid), // .readdatavalid + .av_write (seq_bridge_m0_write), // .write + .av_writedata (seq_bridge_m0_writedata), // .writedata + .av_debugaccess (seq_bridge_m0_debugaccess), // .debugaccess + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_lock (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (17), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (0), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (1), + .AV_REGISTERINCOMINGSIGNALS (0) + ) cpu_inst_instruction_master_translator ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read + .uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address + .av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest + .av_read (cpu_inst_instruction_master_read), // .read + .av_readdata (cpu_inst_instruction_master_readdata), // .readdata + .av_burstcount (1'b1), // (terminated) + .av_byteenable (4'b1111), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_readdatavalid (), // (terminated) + .av_write (1'b0), // (terminated) + .av_writedata (32'b00000000000000000000000000000000), // (terminated) + .av_lock (1'b0), // (terminated) + .av_debugaccess (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (16), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hphy_bridge_s0_translator ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (hphy_bridge_s0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hphy_bridge_s0_agent_m0_burstcount), // .burstcount + .uav_read (hphy_bridge_s0_agent_m0_read), // .read + .uav_write (hphy_bridge_s0_agent_m0_write), // .write + .uav_waitrequest (hphy_bridge_s0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hphy_bridge_s0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hphy_bridge_s0_agent_m0_byteenable), // .byteenable + .uav_readdata (hphy_bridge_s0_agent_m0_readdata), // .readdata + .uav_writedata (hphy_bridge_s0_agent_m0_writedata), // .writedata + .uav_lock (hphy_bridge_s0_agent_m0_lock), // .lock + .uav_debugaccess (hphy_bridge_s0_agent_m0_debugaccess), // .debugaccess + .av_address (hphy_bridge_s0_address), // avalon_anti_slave_0.address + .av_write (hphy_bridge_s0_write), // .write + .av_read (hphy_bridge_s0_read), // .read + .av_readdata (hphy_bridge_s0_readdata), // .readdata + .av_writedata (hphy_bridge_s0_writedata), // .writedata + .av_waitrequest (hphy_bridge_s0_waitrequest), // .waitrequest + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (13), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) sequencer_mem_s1_translator ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (sequencer_mem_s1_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount + .uav_read (sequencer_mem_s1_agent_m0_read), // .read + .uav_write (sequencer_mem_s1_agent_m0_write), // .write + .uav_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable + .uav_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata + .uav_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata + .uav_lock (sequencer_mem_s1_agent_m0_lock), // .lock + .uav_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess + .av_address (sequencer_mem_s1_address), // avalon_anti_slave_0.address + .av_write (sequencer_mem_s1_write), // .write + .av_readdata (sequencer_mem_s1_readdata), // .readdata + .av_writedata (sequencer_mem_s1_writedata), // .writedata + .av_byteenable (sequencer_mem_s1_byteenable), // .byteenable + .av_chipselect (sequencer_mem_s1_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (13), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) sequencer_scc_mgr_inst_avl_translator ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount + .uav_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read + .uav_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write + .uav_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable + .uav_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata + .uav_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata + .uav_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock + .uav_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess + .av_address (sequencer_scc_mgr_inst_avl_address), // avalon_anti_slave_0.address + .av_write (sequencer_scc_mgr_inst_avl_write), // .write + .av_read (sequencer_scc_mgr_inst_avl_read), // .read + .av_readdata (sequencer_scc_mgr_inst_avl_readdata), // .readdata + .av_writedata (sequencer_scc_mgr_inst_avl_writedata), // .writedata + .av_waitrequest (sequencer_scc_mgr_inst_avl_waitrequest), // .waitrequest + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (4), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (32), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) sequencer_reg_file_inst_avl_translator ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset + .uav_address (sequencer_reg_file_inst_avl_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount + .uav_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read + .uav_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write + .uav_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable + .uav_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata + .uav_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata + .uav_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock + .uav_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess + .av_address (sequencer_reg_file_inst_avl_address), // avalon_anti_slave_0.address + .av_write (sequencer_reg_file_inst_avl_write), // .write + .av_read (sequencer_reg_file_inst_avl_read), // .read + .av_readdata (sequencer_reg_file_inst_avl_readdata), // .readdata + .av_writedata (sequencer_reg_file_inst_avl_writedata), // .writedata + .av_byteenable (sequencer_reg_file_inst_avl_byteenable), // .byteenable + .av_waitrequest (sequencer_reg_file_inst_avl_waitrequest), // .waitrequest + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_ORI_BURST_SIZE_H (105), + .PKT_ORI_BURST_SIZE_L (103), + .PKT_RESPONSE_STATUS_H (102), + .PKT_RESPONSE_STATUS_L (101), + .PKT_QOS_H (88), + .PKT_QOS_L (88), + .PKT_DATA_SIDEBAND_H (86), + .PKT_DATA_SIDEBAND_L (86), + .PKT_ADDR_SIDEBAND_H (85), + .PKT_ADDR_SIDEBAND_L (85), + .PKT_BURST_TYPE_H (84), + .PKT_BURST_TYPE_L (83), + .PKT_CACHE_H (100), + .PKT_CACHE_L (97), + .PKT_THREAD_ID_H (93), + .PKT_THREAD_ID_L (93), + .PKT_BURST_SIZE_H (82), + .PKT_BURST_SIZE_L (80), + .PKT_TRANS_EXCLUSIVE (73), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (87), + .PKT_PROTECTION_H (96), + .PKT_PROTECTION_L (94), + .PKT_BURSTWRAP_H (79), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .ST_DATA_W (106), + .ST_CHANNEL_W (4), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (0), + .BURSTWRAP_VALUE (7), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) cpu_inst_data_master_agent ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address + .av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write + .av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (cpu_inst_data_master_agent_cp_valid), // cp.valid + .cp_data (cpu_inst_data_master_agent_cp_data), // .data + .cp_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket + .cp_ready (cpu_inst_data_master_agent_cp_ready), // .ready + .rp_valid (rsp_mux_src_valid), // rp.valid + .rp_data (rsp_mux_src_data), // .data + .rp_channel (rsp_mux_src_channel), // .channel + .rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket + .rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket + .rp_ready (rsp_mux_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_ORI_BURST_SIZE_H (105), + .PKT_ORI_BURST_SIZE_L (103), + .PKT_RESPONSE_STATUS_H (102), + .PKT_RESPONSE_STATUS_L (101), + .PKT_QOS_H (88), + .PKT_QOS_L (88), + .PKT_DATA_SIDEBAND_H (86), + .PKT_DATA_SIDEBAND_L (86), + .PKT_ADDR_SIDEBAND_H (85), + .PKT_ADDR_SIDEBAND_L (85), + .PKT_BURST_TYPE_H (84), + .PKT_BURST_TYPE_L (83), + .PKT_CACHE_H (100), + .PKT_CACHE_L (97), + .PKT_THREAD_ID_H (93), + .PKT_THREAD_ID_L (93), + .PKT_BURST_SIZE_H (82), + .PKT_BURST_SIZE_L (80), + .PKT_TRANS_EXCLUSIVE (73), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (87), + .PKT_PROTECTION_H (96), + .PKT_PROTECTION_L (94), + .PKT_BURSTWRAP_H (79), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .ST_DATA_W (106), + .ST_CHANNEL_W (4), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (2), + .BURSTWRAP_VALUE (7), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) seq_bridge_m0_agent ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .av_address (seq_bridge_m0_translator_avalon_universal_master_0_address), // av.address + .av_write (seq_bridge_m0_translator_avalon_universal_master_0_write), // .write + .av_read (seq_bridge_m0_translator_avalon_universal_master_0_read), // .read + .av_writedata (seq_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (seq_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (seq_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (seq_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (seq_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (seq_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (seq_bridge_m0_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (seq_bridge_m0_agent_cp_valid), // cp.valid + .cp_data (seq_bridge_m0_agent_cp_data), // .data + .cp_startofpacket (seq_bridge_m0_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (seq_bridge_m0_agent_cp_endofpacket), // .endofpacket + .cp_ready (seq_bridge_m0_agent_cp_ready), // .ready + .rp_valid (seq_bridge_m0_limiter_rsp_src_valid), // rp.valid + .rp_data (seq_bridge_m0_limiter_rsp_src_data), // .data + .rp_channel (seq_bridge_m0_limiter_rsp_src_channel), // .channel + .rp_startofpacket (seq_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket + .rp_endofpacket (seq_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket + .rp_ready (seq_bridge_m0_limiter_rsp_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_ORI_BURST_SIZE_H (105), + .PKT_ORI_BURST_SIZE_L (103), + .PKT_RESPONSE_STATUS_H (102), + .PKT_RESPONSE_STATUS_L (101), + .PKT_QOS_H (88), + .PKT_QOS_L (88), + .PKT_DATA_SIDEBAND_H (86), + .PKT_DATA_SIDEBAND_L (86), + .PKT_ADDR_SIDEBAND_H (85), + .PKT_ADDR_SIDEBAND_L (85), + .PKT_BURST_TYPE_H (84), + .PKT_BURST_TYPE_L (83), + .PKT_CACHE_H (100), + .PKT_CACHE_L (97), + .PKT_THREAD_ID_H (93), + .PKT_THREAD_ID_L (93), + .PKT_BURST_SIZE_H (82), + .PKT_BURST_SIZE_L (80), + .PKT_TRANS_EXCLUSIVE (73), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (87), + .PKT_PROTECTION_H (96), + .PKT_PROTECTION_L (94), + .PKT_BURSTWRAP_H (79), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .ST_DATA_W (106), + .ST_CHANNEL_W (4), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (1), + .BURSTWRAP_VALUE (3), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) cpu_inst_instruction_master_agent ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address + .av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write + .av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (cpu_inst_instruction_master_agent_cp_valid), // cp.valid + .cp_data (cpu_inst_instruction_master_agent_cp_data), // .data + .cp_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket + .cp_ready (cpu_inst_instruction_master_agent_cp_ready), // .ready + .rp_valid (rsp_mux_002_src_valid), // rp.valid + .rp_data (rsp_mux_002_src_data), // .data + .rp_channel (rsp_mux_002_src_channel), // .channel + .rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket + .rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket + .rp_ready (rsp_mux_002_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_ORI_BURST_SIZE_H (105), + .PKT_ORI_BURST_SIZE_L (103), + .PKT_RESPONSE_STATUS_H (102), + .PKT_RESPONSE_STATUS_L (101), + .PKT_BURST_SIZE_H (82), + .PKT_BURST_SIZE_L (80), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (87), + .PKT_PROTECTION_H (96), + .PKT_PROTECTION_L (94), + .PKT_BURSTWRAP_H (79), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .PKT_SYMBOL_W (8), + .ST_CHANNEL_W (4), + .ST_DATA_W (106), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .ECC_ENABLE (0) + ) hphy_bridge_s0_agent ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .m0_address (hphy_bridge_s0_agent_m0_address), // m0.address + .m0_burstcount (hphy_bridge_s0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hphy_bridge_s0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hphy_bridge_s0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hphy_bridge_s0_agent_m0_lock), // .lock + .m0_readdata (hphy_bridge_s0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hphy_bridge_s0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hphy_bridge_s0_agent_m0_read), // .read + .m0_waitrequest (hphy_bridge_s0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hphy_bridge_s0_agent_m0_writedata), // .writedata + .m0_write (hphy_bridge_s0_agent_m0_write), // .write + .rp_endofpacket (hphy_bridge_s0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hphy_bridge_s0_agent_rp_ready), // .ready + .rp_valid (hphy_bridge_s0_agent_rp_valid), // .valid + .rp_data (hphy_bridge_s0_agent_rp_data), // .data + .rp_startofpacket (hphy_bridge_s0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_mux_src_ready), // cp.ready + .cp_valid (cmd_mux_src_valid), // .valid + .cp_data (cmd_mux_src_data), // .data + .cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_src_channel), // .channel + .rf_sink_ready (hphy_bridge_s0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hphy_bridge_s0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hphy_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hphy_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hphy_bridge_s0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hphy_bridge_s0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hphy_bridge_s0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hphy_bridge_s0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hphy_bridge_s0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hphy_bridge_s0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error + .rdata_fifo_src_ready (hphy_bridge_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hphy_bridge_s0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hphy_bridge_s0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (107), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hphy_bridge_s0_agent_rsp_fifo ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (hphy_bridge_s0_agent_rf_source_data), // in.data + .in_valid (hphy_bridge_s0_agent_rf_source_valid), // .valid + .in_ready (hphy_bridge_s0_agent_rf_source_ready), // .ready + .in_startofpacket (hphy_bridge_s0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hphy_bridge_s0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hphy_bridge_s0_agent_rsp_fifo_out_data), // out.data + .out_valid (hphy_bridge_s0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hphy_bridge_s0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hphy_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hphy_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_ORI_BURST_SIZE_H (105), + .PKT_ORI_BURST_SIZE_L (103), + .PKT_RESPONSE_STATUS_H (102), + .PKT_RESPONSE_STATUS_L (101), + .PKT_BURST_SIZE_H (82), + .PKT_BURST_SIZE_L (80), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (87), + .PKT_PROTECTION_H (96), + .PKT_PROTECTION_L (94), + .PKT_BURSTWRAP_H (79), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .PKT_SYMBOL_W (8), + .ST_CHANNEL_W (4), + .ST_DATA_W (106), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .ECC_ENABLE (0) + ) sequencer_mem_s1_agent ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .m0_address (sequencer_mem_s1_agent_m0_address), // m0.address + .m0_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount + .m0_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable + .m0_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess + .m0_lock (sequencer_mem_s1_agent_m0_lock), // .lock + .m0_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata + .m0_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid + .m0_read (sequencer_mem_s1_agent_m0_read), // .read + .m0_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest + .m0_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata + .m0_write (sequencer_mem_s1_agent_m0_write), // .write + .rp_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (sequencer_mem_s1_agent_rp_ready), // .ready + .rp_valid (sequencer_mem_s1_agent_rp_valid), // .valid + .rp_data (sequencer_mem_s1_agent_rp_data), // .data + .rp_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_mux_001_src_ready), // cp.ready + .cp_valid (cmd_mux_001_src_valid), // .valid + .cp_data (cmd_mux_001_src_data), // .data + .cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_001_src_channel), // .channel + .rf_sink_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // .data + .rf_source_ready (sequencer_mem_s1_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid + .rf_source_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (sequencer_mem_s1_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error + .rdata_fifo_src_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (107), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) sequencer_mem_s1_agent_rsp_fifo ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (sequencer_mem_s1_agent_rf_source_data), // in.data + .in_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid + .in_ready (sequencer_mem_s1_agent_rf_source_ready), // .ready + .in_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket + .out_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // out.data + .out_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid + .out_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_ORI_BURST_SIZE_H (105), + .PKT_ORI_BURST_SIZE_L (103), + .PKT_RESPONSE_STATUS_H (102), + .PKT_RESPONSE_STATUS_L (101), + .PKT_BURST_SIZE_H (82), + .PKT_BURST_SIZE_L (80), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (87), + .PKT_PROTECTION_H (96), + .PKT_PROTECTION_L (94), + .PKT_BURSTWRAP_H (79), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .PKT_SYMBOL_W (8), + .ST_CHANNEL_W (4), + .ST_DATA_W (106), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .ECC_ENABLE (0) + ) sequencer_scc_mgr_inst_avl_agent ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .m0_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // m0.address + .m0_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount + .m0_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable + .m0_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess + .m0_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock + .m0_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata + .m0_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid + .m0_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read + .m0_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest + .m0_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata + .m0_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write + .rp_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // .ready + .rp_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid + .rp_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data + .rp_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_mux_002_src_ready), // cp.ready + .cp_valid (cmd_mux_002_src_valid), // .valid + .cp_data (cmd_mux_002_src_data), // .data + .cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_002_src_channel), // .channel + .rf_sink_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // .data + .rf_source_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid + .rf_source_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error + .rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (107), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) sequencer_scc_mgr_inst_avl_agent_rsp_fifo ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // in.data + .in_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid + .in_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // .ready + .in_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket + .out_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // out.data + .out_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid + .out_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_ORI_BURST_SIZE_H (105), + .PKT_ORI_BURST_SIZE_L (103), + .PKT_RESPONSE_STATUS_H (102), + .PKT_RESPONSE_STATUS_L (101), + .PKT_BURST_SIZE_H (82), + .PKT_BURST_SIZE_L (80), + .PKT_TRANS_LOCK (72), + .PKT_BEGIN_BURST (87), + .PKT_PROTECTION_H (96), + .PKT_PROTECTION_L (94), + .PKT_BURSTWRAP_H (79), + .PKT_BURSTWRAP_L (77), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_ADDR_H (67), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (68), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .PKT_TRANS_READ (71), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .PKT_SYMBOL_W (8), + .ST_CHANNEL_W (4), + .ST_DATA_W (106), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .ECC_ENABLE (0) + ) sequencer_reg_file_inst_avl_agent ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .m0_address (sequencer_reg_file_inst_avl_agent_m0_address), // m0.address + .m0_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount + .m0_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable + .m0_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess + .m0_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock + .m0_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata + .m0_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid + .m0_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read + .m0_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest + .m0_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata + .m0_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write + .rp_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // .ready + .rp_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid + .rp_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data + .rp_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_mux_003_src_ready), // cp.ready + .cp_valid (cmd_mux_003_src_valid), // .valid + .cp_data (cmd_mux_003_src_data), // .data + .cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_003_src_channel), // .channel + .rf_sink_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // .data + .rf_source_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid + .rf_source_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error + .rdata_fifo_src_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (107), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) sequencer_reg_file_inst_avl_agent_rsp_fifo ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // in.data + .in_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid + .in_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // .ready + .in_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket + .out_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // out.data + .out_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid + .out_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + ddr3_s0_mm_interconnect_0_router router ( + .sink_ready (cpu_inst_data_master_agent_cp_ready), // sink.ready + .sink_valid (cpu_inst_data_master_agent_cp_valid), // .valid + .sink_data (cpu_inst_data_master_agent_cp_data), // .data + .sink_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_src_ready), // src.ready + .src_valid (router_src_valid), // .valid + .src_data (router_src_data), // .data + .src_channel (router_src_channel), // .channel + .src_startofpacket (router_src_startofpacket), // .startofpacket + .src_endofpacket (router_src_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_router_001 router_001 ( + .sink_ready (seq_bridge_m0_agent_cp_ready), // sink.ready + .sink_valid (seq_bridge_m0_agent_cp_valid), // .valid + .sink_data (seq_bridge_m0_agent_cp_data), // .data + .sink_startofpacket (seq_bridge_m0_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (seq_bridge_m0_agent_cp_endofpacket), // .endofpacket + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_001_src_ready), // src.ready + .src_valid (router_001_src_valid), // .valid + .src_data (router_001_src_data), // .data + .src_channel (router_001_src_channel), // .channel + .src_startofpacket (router_001_src_startofpacket), // .startofpacket + .src_endofpacket (router_001_src_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_router_002 router_002 ( + .sink_ready (cpu_inst_instruction_master_agent_cp_ready), // sink.ready + .sink_valid (cpu_inst_instruction_master_agent_cp_valid), // .valid + .sink_data (cpu_inst_instruction_master_agent_cp_data), // .data + .sink_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_002_src_ready), // src.ready + .src_valid (router_002_src_valid), // .valid + .src_data (router_002_src_data), // .data + .src_channel (router_002_src_channel), // .channel + .src_startofpacket (router_002_src_startofpacket), // .startofpacket + .src_endofpacket (router_002_src_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_router_003 router_003 ( + .sink_ready (hphy_bridge_s0_agent_rp_ready), // sink.ready + .sink_valid (hphy_bridge_s0_agent_rp_valid), // .valid + .sink_data (hphy_bridge_s0_agent_rp_data), // .data + .sink_startofpacket (hphy_bridge_s0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hphy_bridge_s0_agent_rp_endofpacket), // .endofpacket + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_003_src_ready), // src.ready + .src_valid (router_003_src_valid), // .valid + .src_data (router_003_src_data), // .data + .src_channel (router_003_src_channel), // .channel + .src_startofpacket (router_003_src_startofpacket), // .startofpacket + .src_endofpacket (router_003_src_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_router_004 router_004 ( + .sink_ready (sequencer_mem_s1_agent_rp_ready), // sink.ready + .sink_valid (sequencer_mem_s1_agent_rp_valid), // .valid + .sink_data (sequencer_mem_s1_agent_rp_data), // .data + .sink_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // .endofpacket + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_004_src_ready), // src.ready + .src_valid (router_004_src_valid), // .valid + .src_data (router_004_src_data), // .data + .src_channel (router_004_src_channel), // .channel + .src_startofpacket (router_004_src_startofpacket), // .startofpacket + .src_endofpacket (router_004_src_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_router_003 router_005 ( + .sink_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // sink.ready + .sink_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid + .sink_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data + .sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // .endofpacket + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_005_src_ready), // src.ready + .src_valid (router_005_src_valid), // .valid + .src_data (router_005_src_data), // .data + .src_channel (router_005_src_channel), // .channel + .src_startofpacket (router_005_src_startofpacket), // .startofpacket + .src_endofpacket (router_005_src_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_router_006 router_006 ( + .sink_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // sink.ready + .sink_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid + .sink_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data + .sink_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // .endofpacket + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_006_src_ready), // src.ready + .src_valid (router_006_src_valid), // .valid + .src_data (router_006_src_data), // .data + .src_channel (router_006_src_channel), // .channel + .src_startofpacket (router_006_src_startofpacket), // .startofpacket + .src_endofpacket (router_006_src_endofpacket) // .endofpacket + ); + + altera_merlin_traffic_limiter #( + .PKT_DEST_ID_H (92), + .PKT_DEST_ID_L (91), + .PKT_SRC_ID_H (90), + .PKT_SRC_ID_L (89), + .PKT_BYTE_CNT_H (76), + .PKT_BYTE_CNT_L (74), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_TRANS_POSTED (69), + .PKT_TRANS_WRITE (70), + .MAX_OUTSTANDING_RESPONSES (1), + .PIPELINED (0), + .ST_DATA_W (106), + .ST_CHANNEL_W (4), + .VALID_WIDTH (4), + .ENFORCE_ORDER (1), + .PREVENT_HAZARDS (0), + .SUPPORTS_POSTED_WRITES (1), + .SUPPORTS_NONPOSTED_WRITES (0), + .REORDER (0) + ) seq_bridge_m0_limiter ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .cmd_sink_ready (router_001_src_ready), // cmd_sink.ready + .cmd_sink_valid (router_001_src_valid), // .valid + .cmd_sink_data (router_001_src_data), // .data + .cmd_sink_channel (router_001_src_channel), // .channel + .cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket + .cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket + .cmd_src_ready (seq_bridge_m0_limiter_cmd_src_ready), // cmd_src.ready + .cmd_src_data (seq_bridge_m0_limiter_cmd_src_data), // .data + .cmd_src_channel (seq_bridge_m0_limiter_cmd_src_channel), // .channel + .cmd_src_startofpacket (seq_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket + .cmd_src_endofpacket (seq_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket + .rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready + .rsp_sink_valid (rsp_mux_001_src_valid), // .valid + .rsp_sink_channel (rsp_mux_001_src_channel), // .channel + .rsp_sink_data (rsp_mux_001_src_data), // .data + .rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket + .rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket + .rsp_src_ready (seq_bridge_m0_limiter_rsp_src_ready), // rsp_src.ready + .rsp_src_valid (seq_bridge_m0_limiter_rsp_src_valid), // .valid + .rsp_src_data (seq_bridge_m0_limiter_rsp_src_data), // .data + .rsp_src_channel (seq_bridge_m0_limiter_rsp_src_channel), // .channel + .rsp_src_startofpacket (seq_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket + .rsp_src_endofpacket (seq_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket + .cmd_src_valid (seq_bridge_m0_limiter_cmd_valid_data) // cmd_valid.data + ); + + ddr3_s0_mm_interconnect_0_cmd_demux cmd_demux ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_src_ready), // sink.ready + .sink_channel (router_src_channel), // .channel + .sink_data (router_src_data), // .data + .sink_startofpacket (router_src_startofpacket), // .startofpacket + .sink_endofpacket (router_src_endofpacket), // .endofpacket + .sink_valid (router_src_valid), // .valid + .src0_ready (cmd_demux_src0_ready), // src0.ready + .src0_valid (cmd_demux_src0_valid), // .valid + .src0_data (cmd_demux_src0_data), // .data + .src0_channel (cmd_demux_src0_channel), // .channel + .src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket + .src1_ready (cmd_demux_src1_ready), // src1.ready + .src1_valid (cmd_demux_src1_valid), // .valid + .src1_data (cmd_demux_src1_data), // .data + .src1_channel (cmd_demux_src1_channel), // .channel + .src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket + .src2_ready (cmd_demux_src2_ready), // src2.ready + .src2_valid (cmd_demux_src2_valid), // .valid + .src2_data (cmd_demux_src2_data), // .data + .src2_channel (cmd_demux_src2_channel), // .channel + .src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket + .src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket + .src3_ready (cmd_demux_src3_ready), // src3.ready + .src3_valid (cmd_demux_src3_valid), // .valid + .src3_data (cmd_demux_src3_data), // .data + .src3_channel (cmd_demux_src3_channel), // .channel + .src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket + .src3_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_demux_001 cmd_demux_001 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (seq_bridge_m0_limiter_cmd_src_ready), // sink.ready + .sink_channel (seq_bridge_m0_limiter_cmd_src_channel), // .channel + .sink_data (seq_bridge_m0_limiter_cmd_src_data), // .data + .sink_startofpacket (seq_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket + .sink_endofpacket (seq_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket + .sink_valid (seq_bridge_m0_limiter_cmd_valid_data), // sink_valid.data + .src0_ready (cmd_demux_001_src0_ready), // src0.ready + .src0_valid (cmd_demux_001_src0_valid), // .valid + .src0_data (cmd_demux_001_src0_data), // .data + .src0_channel (cmd_demux_001_src0_channel), // .channel + .src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (cmd_demux_001_src1_ready), // src1.ready + .src1_valid (cmd_demux_001_src1_valid), // .valid + .src1_data (cmd_demux_001_src1_data), // .data + .src1_channel (cmd_demux_001_src1_channel), // .channel + .src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_demux_002 cmd_demux_002 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_002_src_ready), // sink.ready + .sink_channel (router_002_src_channel), // .channel + .sink_data (router_002_src_data), // .data + .sink_startofpacket (router_002_src_startofpacket), // .startofpacket + .sink_endofpacket (router_002_src_endofpacket), // .endofpacket + .sink_valid (router_002_src_valid), // .valid + .src0_ready (cmd_demux_002_src0_ready), // src0.ready + .src0_valid (cmd_demux_002_src0_valid), // .valid + .src0_data (cmd_demux_002_src0_data), // .data + .src0_channel (cmd_demux_002_src0_channel), // .channel + .src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_mux cmd_mux ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (cmd_mux_src_ready), // src.ready + .src_valid (cmd_mux_src_valid), // .valid + .src_data (cmd_mux_src_data), // .data + .src_channel (cmd_mux_src_channel), // .channel + .src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket + .sink0_ready (cmd_demux_src0_ready), // sink0.ready + .sink0_valid (cmd_demux_src0_valid), // .valid + .sink0_channel (cmd_demux_src0_channel), // .channel + .sink0_data (cmd_demux_src0_data), // .data + .sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_mux_001 cmd_mux_001 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (cmd_mux_001_src_ready), // src.ready + .src_valid (cmd_mux_001_src_valid), // .valid + .src_data (cmd_mux_001_src_data), // .data + .src_channel (cmd_mux_001_src_channel), // .channel + .src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (cmd_demux_src1_ready), // sink0.ready + .sink0_valid (cmd_demux_src1_valid), // .valid + .sink0_channel (cmd_demux_src1_channel), // .channel + .sink0_data (cmd_demux_src1_data), // .data + .sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket + .sink1_ready (cmd_demux_001_src0_ready), // sink1.ready + .sink1_valid (cmd_demux_001_src0_valid), // .valid + .sink1_channel (cmd_demux_001_src0_channel), // .channel + .sink1_data (cmd_demux_001_src0_data), // .data + .sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket + .sink2_ready (cmd_demux_002_src0_ready), // sink2.ready + .sink2_valid (cmd_demux_002_src0_valid), // .valid + .sink2_channel (cmd_demux_002_src0_channel), // .channel + .sink2_data (cmd_demux_002_src0_data), // .data + .sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket + .sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_mux cmd_mux_002 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (cmd_mux_002_src_ready), // src.ready + .src_valid (cmd_mux_002_src_valid), // .valid + .src_data (cmd_mux_002_src_data), // .data + .src_channel (cmd_mux_002_src_channel), // .channel + .src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket + .sink0_ready (cmd_demux_src2_ready), // sink0.ready + .sink0_valid (cmd_demux_src2_valid), // .valid + .sink0_channel (cmd_demux_src2_channel), // .channel + .sink0_data (cmd_demux_src2_data), // .data + .sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_mux_003 cmd_mux_003 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (cmd_mux_003_src_ready), // src.ready + .src_valid (cmd_mux_003_src_valid), // .valid + .src_data (cmd_mux_003_src_data), // .data + .src_channel (cmd_mux_003_src_channel), // .channel + .src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket + .sink0_ready (cmd_demux_src3_ready), // sink0.ready + .sink0_valid (cmd_demux_src3_valid), // .valid + .sink0_channel (cmd_demux_src3_channel), // .channel + .sink0_data (cmd_demux_src3_data), // .data + .sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket + .sink1_ready (cmd_demux_001_src1_ready), // sink1.ready + .sink1_valid (cmd_demux_001_src1_valid), // .valid + .sink1_channel (cmd_demux_001_src1_channel), // .channel + .sink1_data (cmd_demux_001_src1_data), // .data + .sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_demux_002 rsp_demux ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_003_src_ready), // sink.ready + .sink_channel (router_003_src_channel), // .channel + .sink_data (router_003_src_data), // .data + .sink_startofpacket (router_003_src_startofpacket), // .startofpacket + .sink_endofpacket (router_003_src_endofpacket), // .endofpacket + .sink_valid (router_003_src_valid), // .valid + .src0_ready (rsp_demux_src0_ready), // src0.ready + .src0_valid (rsp_demux_src0_valid), // .valid + .src0_data (rsp_demux_src0_data), // .data + .src0_channel (rsp_demux_src0_channel), // .channel + .src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_rsp_demux_001 rsp_demux_001 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_004_src_ready), // sink.ready + .sink_channel (router_004_src_channel), // .channel + .sink_data (router_004_src_data), // .data + .sink_startofpacket (router_004_src_startofpacket), // .startofpacket + .sink_endofpacket (router_004_src_endofpacket), // .endofpacket + .sink_valid (router_004_src_valid), // .valid + .src0_ready (rsp_demux_001_src0_ready), // src0.ready + .src0_valid (rsp_demux_001_src0_valid), // .valid + .src0_data (rsp_demux_001_src0_data), // .data + .src0_channel (rsp_demux_001_src0_channel), // .channel + .src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (rsp_demux_001_src1_ready), // src1.ready + .src1_valid (rsp_demux_001_src1_valid), // .valid + .src1_data (rsp_demux_001_src1_data), // .data + .src1_channel (rsp_demux_001_src1_channel), // .channel + .src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket + .src2_ready (rsp_demux_001_src2_ready), // src2.ready + .src2_valid (rsp_demux_001_src2_valid), // .valid + .src2_data (rsp_demux_001_src2_data), // .data + .src2_channel (rsp_demux_001_src2_channel), // .channel + .src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket + .src2_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_cmd_demux_002 rsp_demux_002 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_005_src_ready), // sink.ready + .sink_channel (router_005_src_channel), // .channel + .sink_data (router_005_src_data), // .data + .sink_startofpacket (router_005_src_startofpacket), // .startofpacket + .sink_endofpacket (router_005_src_endofpacket), // .endofpacket + .sink_valid (router_005_src_valid), // .valid + .src0_ready (rsp_demux_002_src0_ready), // src0.ready + .src0_valid (rsp_demux_002_src0_valid), // .valid + .src0_data (rsp_demux_002_src0_data), // .data + .src0_channel (rsp_demux_002_src0_channel), // .channel + .src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_rsp_demux_003 rsp_demux_003 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_006_src_ready), // sink.ready + .sink_channel (router_006_src_channel), // .channel + .sink_data (router_006_src_data), // .data + .sink_startofpacket (router_006_src_startofpacket), // .startofpacket + .sink_endofpacket (router_006_src_endofpacket), // .endofpacket + .sink_valid (router_006_src_valid), // .valid + .src0_ready (rsp_demux_003_src0_ready), // src0.ready + .src0_valid (rsp_demux_003_src0_valid), // .valid + .src0_data (rsp_demux_003_src0_data), // .data + .src0_channel (rsp_demux_003_src0_channel), // .channel + .src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket + .src1_ready (rsp_demux_003_src1_ready), // src1.ready + .src1_valid (rsp_demux_003_src1_valid), // .valid + .src1_data (rsp_demux_003_src1_data), // .data + .src1_channel (rsp_demux_003_src1_channel), // .channel + .src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_rsp_mux rsp_mux ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (rsp_mux_src_ready), // src.ready + .src_valid (rsp_mux_src_valid), // .valid + .src_data (rsp_mux_src_data), // .data + .src_channel (rsp_mux_src_channel), // .channel + .src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket + .sink0_ready (rsp_demux_src0_ready), // sink0.ready + .sink0_valid (rsp_demux_src0_valid), // .valid + .sink0_channel (rsp_demux_src0_channel), // .channel + .sink0_data (rsp_demux_src0_data), // .data + .sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket + .sink1_ready (rsp_demux_001_src0_ready), // sink1.ready + .sink1_valid (rsp_demux_001_src0_valid), // .valid + .sink1_channel (rsp_demux_001_src0_channel), // .channel + .sink1_data (rsp_demux_001_src0_data), // .data + .sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket + .sink2_ready (rsp_demux_002_src0_ready), // sink2.ready + .sink2_valid (rsp_demux_002_src0_valid), // .valid + .sink2_channel (rsp_demux_002_src0_channel), // .channel + .sink2_data (rsp_demux_002_src0_data), // .data + .sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket + .sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket + .sink3_ready (rsp_demux_003_src0_ready), // sink3.ready + .sink3_valid (rsp_demux_003_src0_valid), // .valid + .sink3_channel (rsp_demux_003_src0_channel), // .channel + .sink3_data (rsp_demux_003_src0_data), // .data + .sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket + .sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_rsp_mux_001 rsp_mux_001 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (rsp_mux_001_src_ready), // src.ready + .src_valid (rsp_mux_001_src_valid), // .valid + .src_data (rsp_mux_001_src_data), // .data + .src_channel (rsp_mux_001_src_channel), // .channel + .src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (rsp_demux_001_src1_ready), // sink0.ready + .sink0_valid (rsp_demux_001_src1_valid), // .valid + .sink0_channel (rsp_demux_001_src1_channel), // .channel + .sink0_data (rsp_demux_001_src1_data), // .data + .sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket + .sink1_ready (rsp_demux_003_src1_ready), // sink1.ready + .sink1_valid (rsp_demux_003_src1_valid), // .valid + .sink1_channel (rsp_demux_003_src1_channel), // .channel + .sink1_data (rsp_demux_003_src1_data), // .data + .sink1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_rsp_mux_002 rsp_mux_002 ( + .clk (avl_clk_out_clk_clk), // clk.clk + .reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (rsp_mux_002_src_ready), // src.ready + .src_valid (rsp_mux_002_src_valid), // .valid + .src_data (rsp_mux_002_src_data), // .data + .src_channel (rsp_mux_002_src_channel), // .channel + .src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket + .sink0_ready (rsp_demux_001_src2_ready), // sink0.ready + .sink0_valid (rsp_demux_001_src2_valid), // .valid + .sink0_channel (rsp_demux_001_src2_channel), // .channel + .sink0_data (rsp_demux_001_src2_data), // .data + .sink0_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket + ); + + ddr3_s0_mm_interconnect_0_avalon_st_adapter #( + .inBitsPerSymbol (34), + .inUsePackets (0), + .inDataWidth (34), + .inChannelWidth (0), + .inErrorWidth (0), + .inUseEmptyPort (0), + .inUseValid (1), + .inUseReady (1), + .inReadyLatency (0), + .outDataWidth (34), + .outChannelWidth (0), + .outErrorWidth (1), + .outUseEmptyPort (0), + .outUseValid (1), + .outUseReady (1), + .outReadyLatency (0) + ) avalon_st_adapter ( + .in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (hphy_bridge_s0_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (hphy_bridge_s0_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (hphy_bridge_s0_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_out_0_error) // .error + ); + + ddr3_s0_mm_interconnect_0_avalon_st_adapter #( + .inBitsPerSymbol (34), + .inUsePackets (0), + .inDataWidth (34), + .inChannelWidth (0), + .inErrorWidth (0), + .inUseEmptyPort (0), + .inUseValid (1), + .inUseReady (1), + .inReadyLatency (0), + .outDataWidth (34), + .outChannelWidth (0), + .outErrorWidth (1), + .outUseEmptyPort (0), + .outUseValid (1), + .outUseReady (1), + .outReadyLatency (0) + ) avalon_st_adapter_001 ( + .in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_001_out_0_error) // .error + ); + + ddr3_s0_mm_interconnect_0_avalon_st_adapter #( + .inBitsPerSymbol (34), + .inUsePackets (0), + .inDataWidth (34), + .inChannelWidth (0), + .inErrorWidth (0), + .inUseEmptyPort (0), + .inUseValid (1), + .inUseReady (1), + .inReadyLatency (0), + .outDataWidth (34), + .outChannelWidth (0), + .outErrorWidth (1), + .outUseEmptyPort (0), + .outUseValid (1), + .outUseReady (1), + .outReadyLatency (0) + ) avalon_st_adapter_002 ( + .in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_002_out_0_error) // .error + ); + + ddr3_s0_mm_interconnect_0_avalon_st_adapter #( + .inBitsPerSymbol (34), + .inUsePackets (0), + .inDataWidth (34), + .inChannelWidth (0), + .inErrorWidth (0), + .inUseEmptyPort (0), + .inUseValid (1), + .inUseReady (1), + .inReadyLatency (0), + .outDataWidth (34), + .outChannelWidth (0), + .outErrorWidth (1), + .outUseEmptyPort (0), + .outUseValid (1), + .outUseReady (1), + .outReadyLatency (0) + ) avalon_st_adapter_003 ( + .in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_003_out_0_error) // .error + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter.v b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter.v new file mode 100644 index 0000000..7a2e27b --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter.v @@ -0,0 +1,202 @@ +// ddr3_s0_mm_interconnect_0_avalon_st_adapter.v + +// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 15.1 185 + +`timescale 1 ps / 1 ps +module ddr3_s0_mm_interconnect_0_avalon_st_adapter #( + parameter inBitsPerSymbol = 34, + parameter inUsePackets = 0, + parameter inDataWidth = 34, + parameter inChannelWidth = 0, + parameter inErrorWidth = 0, + parameter inUseEmptyPort = 0, + parameter inUseValid = 1, + parameter inUseReady = 1, + parameter inReadyLatency = 0, + parameter outDataWidth = 34, + parameter outChannelWidth = 0, + parameter outErrorWidth = 1, + parameter outUseEmptyPort = 0, + parameter outUseValid = 1, + parameter outUseReady = 1, + parameter outReadyLatency = 0 + ) ( + input wire in_clk_0_clk, // in_clk_0.clk + input wire in_rst_0_reset, // in_rst_0.reset + input wire [33:0] in_0_data, // in_0.data + input wire in_0_valid, // .valid + output wire in_0_ready, // .ready + output wire [33:0] out_0_data, // out_0.data + output wire out_0_valid, // .valid + input wire out_0_ready, // .ready + output wire [0:0] out_0_error // .error + ); + + generate + // If any of the display statements (or deliberately broken + // instantiations) within this generate block triggers then this module + // has been instantiated this module with a set of parameters different + // from those it was generated for. This will usually result in a + // non-functioning system. + if (inBitsPerSymbol != 34) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inbitspersymbol_check ( .error(1'b1) ); + end + if (inUsePackets != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inusepackets_check ( .error(1'b1) ); + end + if (inDataWidth != 34) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + indatawidth_check ( .error(1'b1) ); + end + if (inChannelWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inchannelwidth_check ( .error(1'b1) ); + end + if (inErrorWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inerrorwidth_check ( .error(1'b1) ); + end + if (inUseEmptyPort != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inuseemptyport_check ( .error(1'b1) ); + end + if (inUseValid != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inusevalid_check ( .error(1'b1) ); + end + if (inUseReady != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inuseready_check ( .error(1'b1) ); + end + if (inReadyLatency != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + inreadylatency_check ( .error(1'b1) ); + end + if (outDataWidth != 34) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outdatawidth_check ( .error(1'b1) ); + end + if (outChannelWidth != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outchannelwidth_check ( .error(1'b1) ); + end + if (outErrorWidth != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outerrorwidth_check ( .error(1'b1) ); + end + if (outUseEmptyPort != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outuseemptyport_check ( .error(1'b1) ); + end + if (outUseValid != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outusevalid_check ( .error(1'b1) ); + end + if (outUseReady != 1) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outuseready_check ( .error(1'b1) ); + end + if (outReadyLatency != 0) + begin + initial begin + $display("Generated module instantiated with wrong parameters"); + $stop; + end + instantiated_with_wrong_parameters_error_see_comment_above + outreadylatency_check ( .error(1'b1) ); + end + endgenerate + + ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 ( + .clk (in_clk_0_clk), // clk.clk + .reset_n (~in_rst_0_reset), // reset.reset_n + .in_data (in_0_data), // in.data + .in_valid (in_0_valid), // .valid + .in_ready (in_0_ready), // .ready + .out_data (out_0_data), // out.data + .out_valid (out_0_valid), // .valid + .out_ready (out_0_ready), // .ready + .out_error (out_0_error) // .error + ); + +endmodule diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv new file mode 100644 index 0000000..c5645e1 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv @@ -0,0 +1,107 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/09/09 $ +// $Author: dmunday $ + + +// -------------------------------------------------------------------------------- +//| Avalon Streaming Error Adapter +// -------------------------------------------------------------------------------- + +`timescale 1ns / 100ps + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 +// use_ready: true +// use_packets: false +// use_empty: 0 +// empty_width: 0 +// data_width: 34 +// channel_width: 0 +// in_error_width: 0 +// out_error_width: 1 +// in_errors_list +// in_errors_indices 0 +// out_errors_list +// has_in_error_desc: FALSE +// has_out_error_desc: FALSE +// out_has_other: FALSE +// out_other_index: -1 +// dumpVar: +// inString: in_error[ +// closeString: ] | + +// ------------------------------------------ + + + + +module ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 +( + // Interface: in + output reg in_ready, + input in_valid, + input [34-1: 0] in_data, + // Interface: out + input out_ready, + output reg out_valid, + output reg [34-1: 0] out_data, + output reg [0:0] out_error, + // Interface: clk + input clk, + // Interface: reset + input reset_n + + /*AUTOARG*/); + + reg in_error = 0; + initial in_error = 0; + + // --------------------------------------------------------------------- + //| Pass-through Mapping + // --------------------------------------------------------------------- + always_comb begin + in_ready = out_ready; + out_valid = in_valid; + out_data = in_data; + + end + + // --------------------------------------------------------------------- + //| Error Mapping + // --------------------------------------------------------------------- + always_comb begin + out_error = 0; + + out_error = in_error; + + end //always @* +endmodule + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux.sv new file mode 100644 index 0000000..143a80d --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux.sv @@ -0,0 +1,146 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_cmd_demux +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// NUM_OUTPUTS: 4 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module ddr3_s0_mm_interconnect_0_cmd_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [106-1 : 0] sink_data, // ST_DATA_W=106 + input [4-1 : 0] sink_channel, // ST_CHANNEL_W=4 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [106-1 : 0] src0_data, // ST_DATA_W=106 + output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [106-1 : 0] src1_data, // ST_DATA_W=106 + output reg [4-1 : 0] src1_channel, // ST_CHANNEL_W=4 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + output reg src2_valid, + output reg [106-1 : 0] src2_data, // ST_DATA_W=106 + output reg [4-1 : 0] src2_channel, // ST_CHANNEL_W=4 + output reg src2_startofpacket, + output reg src2_endofpacket, + input src2_ready, + + output reg src3_valid, + output reg [106-1 : 0] src3_data, // ST_DATA_W=106 + output reg [4-1 : 0] src3_channel, // ST_CHANNEL_W=4 + output reg src3_startofpacket, + output reg src3_endofpacket, + input src3_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 4; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + src2_data = sink_data; + src2_startofpacket = sink_startofpacket; + src2_endofpacket = sink_endofpacket; + src2_channel = sink_channel >> NUM_OUTPUTS; + + src2_valid = sink_channel[2] && sink_valid; + + src3_data = sink_data; + src3_startofpacket = sink_startofpacket; + src3_endofpacket = sink_endofpacket; + src3_channel = sink_channel >> NUM_OUTPUTS; + + src3_valid = sink_channel[3] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + assign ready_vector[2] = src2_ready; + assign ready_vector[3] = src3_ready; + + assign sink_ready = |(sink_channel & ready_vector); + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_001.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_001.sv new file mode 100644 index 0000000..ae3f5fe --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_001.sv @@ -0,0 +1,116 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_cmd_demux_001 +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 4 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module ddr3_s0_mm_interconnect_0_cmd_demux_001 +( + // ------------------- + // Sink + // ------------------- + input [4-1 : 0] sink_valid, + input [106-1 : 0] sink_data, // ST_DATA_W=106 + input [4-1 : 0] sink_channel, // ST_CHANNEL_W=4 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [106-1 : 0] src0_data, // ST_DATA_W=106 + output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [106-1 : 0] src1_data, // ST_DATA_W=106 + output reg [4-1 : 0] src1_channel, // ST_CHANNEL_W=4 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid[0]; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid[1]; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{2{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_002.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_002.sv new file mode 100644 index 0000000..b66af72 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux_002.sv @@ -0,0 +1,101 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_cmd_demux_002 +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module ddr3_s0_mm_interconnect_0_cmd_demux_002 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [106-1 : 0] sink_data, // ST_DATA_W=106 + input [4-1 : 0] sink_channel, // ST_CHANNEL_W=4 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [106-1 : 0] src0_data, // ST_DATA_W=106 + output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{3{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux.sv new file mode 100644 index 0000000..ab5ac7c --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux.sv @@ -0,0 +1,97 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_cmd_mux +// NUM_INPUTS: 1 +// ARBITRATION_SHARES: 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// ------------------------------------------ + +module ddr3_s0_mm_interconnect_0_cmd_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [106-1 : 0] sink0_data, + input [4-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [106-1 : 0] src_data, + output [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 106 + 4 + 2; + localparam NUM_INPUTS = 1; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam PKT_TRANS_LOCK = 72; + + assign src_valid = sink0_valid; + assign src_data = sink0_data; + assign src_channel = sink0_channel; + assign src_startofpacket = sink0_startofpacket; + assign src_endofpacket = sink0_endofpacket; + assign sink0_ready = src_ready; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_001.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_001.sv new file mode 100644 index 0000000..8aff719 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_001.sv @@ -0,0 +1,388 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_cmd_mux_001 +// NUM_INPUTS: 3 +// ARBITRATION_SHARES: 1 1 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// ------------------------------------------ + +module ddr3_s0_mm_interconnect_0_cmd_mux_001 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [106-1 : 0] sink0_data, + input [4-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [106-1 : 0] sink1_data, + input [4-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + input sink2_valid, + input [106-1 : 0] sink2_data, + input [4-1: 0] sink2_channel, + input sink2_startofpacket, + input sink2_endofpacket, + output sink2_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [106-1 : 0] src_data, + output [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 106 + 4 + 2; + localparam NUM_INPUTS = 3; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam PKT_TRANS_LOCK = 72; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + wire [PAYLOAD_W - 1 : 0] sink2_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + assign valid[2] = sink2_valid; + + wire [NUM_INPUTS - 1 : 0] eop; + assign eop[0] = sink0_endofpacket; + assign eop[1] = sink1_endofpacket; + assign eop[2] = sink2_endofpacket; + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[72]; + lock[1] = sink1_data[72]; + lock[2] = sink2_data[72]; + end + reg [NUM_INPUTS - 1 : 0] locked = '0; + always @(posedge clk or posedge reset) begin + if (reset) begin + locked <= '0; + end + else begin + locked <= grant & lock; + end + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (last_cycle) + packet_in_progress <= 1'b0; + else if (src_valid) + packet_in_progress <= 1'b1; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + // 2 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} } | + share_2 & { SHARE_COUNTER_W {next_grant[2]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid)); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + wire final_packet_2 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_2, + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid)); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] prev_request; + always @(posedge clk, posedge reset) begin + if (reset) + prev_request <= '0; + else + prev_request <= request & ~(valid & eop); + end + + assign request = (PIPELINE_ARB == 1) ? valid | locked : + prev_request | valid | locked; + + wire [NUM_INPUTS - 1 : 0] next_grant_from_arb; + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("round-robin"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant_from_arb), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + assign next_grant = next_grant_from_arb; + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + assign sink2_ready = src_ready && grant[2]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} } | + sink2_payload & {PAYLOAD_W {grant[2]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + assign sink2_payload = {sink2_channel,sink2_data, + sink2_startofpacket,sink2_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_003.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_003.sv new file mode 100644 index 0000000..6611094 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux_003.sv @@ -0,0 +1,367 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_cmd_mux_003 +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// ------------------------------------------ + +module ddr3_s0_mm_interconnect_0_cmd_mux_003 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [106-1 : 0] sink0_data, + input [4-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [106-1 : 0] sink1_data, + input [4-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [106-1 : 0] src_data, + output [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 106 + 4 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam PKT_TRANS_LOCK = 72; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + wire [NUM_INPUTS - 1 : 0] eop; + assign eop[0] = sink0_endofpacket; + assign eop[1] = sink1_endofpacket; + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[72]; + lock[1] = sink1_data[72]; + end + reg [NUM_INPUTS - 1 : 0] locked = '0; + always @(posedge clk or posedge reset) begin + if (reset) begin + locked <= '0; + end + else begin + locked <= grant & lock; + end + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (last_cycle) + packet_in_progress <= 1'b0; + else if (src_valid) + packet_in_progress <= 1'b1; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid)); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid)); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] prev_request; + always @(posedge clk, posedge reset) begin + if (reset) + prev_request <= '0; + else + prev_request <= request & ~(valid & eop); + end + + assign request = (PIPELINE_ARB == 1) ? valid | locked : + prev_request | valid | locked; + + wire [NUM_INPUTS - 1 : 0] next_grant_from_arb; + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("round-robin"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant_from_arb), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + assign next_grant = next_grant_from_arb; + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router.sv new file mode 100644 index 0000000..7242557 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router.sv @@ -0,0 +1,241 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_s0_mm_interconnect_0_router_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [92 - 91 : 0] default_destination_id, + output [4-1 : 0] default_wr_channel, + output [4-1 : 0] default_rd_channel, + output [4-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[92 - 91 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 4'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_s0_mm_interconnect_0_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [106-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [106-1 : 0] src_data, + output reg [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 92; + localparam PKT_DEST_ID_L = 91; + localparam PKT_PROTECTION_H = 96; + localparam PKT_PROTECTION_L = 94; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h18000 - 64'h10000); + localparam PAD1 = log2ceil(64'h60000 - 64'h58000); + localparam PAD2 = log2ceil(64'h70040 - 64'h70000); + localparam PAD3 = log2ceil(64'hc0000 - 64'h80000); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'hc0000; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_ADDR_W-1 : 0] address; + always @* begin + address = {PKT_ADDR_W{1'b0}}; + address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + end + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [4-1 : 0] default_src_channel; + + + + + + + ddr3_s0_mm_interconnect_0_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x10000 .. 0x18000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h10000 ) begin + src_channel = 4'b0010; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x58000 .. 0x60000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h58000 ) begin + src_channel = 4'b0100; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; + end + + // ( 0x70000 .. 0x70040 ) + if ( {address[RG:PAD2],{PAD2{1'b0}}} == 20'h70000 ) begin + src_channel = 4'b1000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; + end + + // ( 0x80000 .. 0xc0000 ) + if ( {address[RG:PAD3],{PAD3{1'b0}}} == 20'h80000 ) begin + src_channel = 4'b0001; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_001.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_001.sv new file mode 100644 index 0000000..64a9aa7 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_001.sv @@ -0,0 +1,227 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_s0_mm_interconnect_0_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 1 + ) + (output [92 - 91 : 0] default_destination_id, + output [4-1 : 0] default_wr_channel, + output [4-1 : 0] default_rd_channel, + output [4-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[92 - 91 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 4'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_s0_mm_interconnect_0_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [106-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [106-1 : 0] src_data, + output reg [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 92; + localparam PKT_DEST_ID_L = 91; + localparam PKT_PROTECTION_H = 96; + localparam PKT_PROTECTION_L = 94; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h18000 - 64'h10000); + localparam PAD1 = log2ceil(64'h70040 - 64'h70000); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h70040; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_ADDR_W-1 : 0] address; + always @* begin + address = {PKT_ADDR_W{1'b0}}; + address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + end + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [4-1 : 0] default_src_channel; + + + + + + + ddr3_s0_mm_interconnect_0_router_001_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x10000 .. 0x18000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h10000 ) begin + src_channel = 4'b01; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x70000 .. 0x70040 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h70000 ) begin + src_channel = 4'b10; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_002.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_002.sv new file mode 100644 index 0000000..84e7107 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_002.sv @@ -0,0 +1,216 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_s0_mm_interconnect_0_router_002_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 1 + ) + (output [92 - 91 : 0] default_destination_id, + output [4-1 : 0] default_wr_channel, + output [4-1 : 0] default_rd_channel, + output [4-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[92 - 91 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 4'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_s0_mm_interconnect_0_router_002 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [106-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [106-1 : 0] src_data, + output reg [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 92; + localparam PKT_DEST_ID_L = 91; + localparam PKT_PROTECTION_H = 96; + localparam PKT_PROTECTION_L = 94; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h18000 - 64'h10000); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h18000; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [4-1 : 0] default_src_channel; + + + + + + + ddr3_s0_mm_interconnect_0_router_002_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + + // ( 10000 .. 18000 ) + src_channel = 4'b1; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_003.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_003.sv new file mode 100644 index 0000000..32e3ad5 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_003.sv @@ -0,0 +1,215 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_s0_mm_interconnect_0_router_003_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [92 - 91 : 0] default_destination_id, + output [4-1 : 0] default_wr_channel, + output [4-1 : 0] default_rd_channel, + output [4-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[92 - 91 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 4'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_s0_mm_interconnect_0_router_003 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [106-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [106-1 : 0] src_data, + output reg [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 92; + localparam PKT_DEST_ID_L = 91; + localparam PKT_PROTECTION_H = 96; + localparam PKT_PROTECTION_L = 94; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [4-1 : 0] default_src_channel; + + + + + + + ddr3_s0_mm_interconnect_0_router_003_default_decode the_default_decode( + .default_destination_id (), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 4'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_004.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_004.sv new file mode 100644 index 0000000..32819d0 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_004.sv @@ -0,0 +1,228 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_s0_mm_interconnect_0_router_004_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [92 - 91 : 0] default_destination_id, + output [4-1 : 0] default_wr_channel, + output [4-1 : 0] default_rd_channel, + output [4-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[92 - 91 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 4'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_s0_mm_interconnect_0_router_004 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [106-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [106-1 : 0] src_data, + output reg [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 92; + localparam PKT_DEST_ID_L = 91; + localparam PKT_PROTECTION_H = 96; + localparam PKT_PROTECTION_L = 94; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [4-1 : 0] default_src_channel; + + + + + // ------------------------------------------------------- + // Write and read transaction signals + // ------------------------------------------------------- + wire read_transaction; + assign read_transaction = sink_data[PKT_TRANS_READ]; + + + ddr3_s0_mm_interconnect_0_router_004_default_decode the_default_decode( + .default_destination_id (), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 4'b001; + end + + if (destid == 2 ) begin + src_channel = 4'b010; + end + + if (destid == 1 && read_transaction) begin + src_channel = 4'b100; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_006.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_006.sv new file mode 100644 index 0000000..554744b --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_router_006.sv @@ -0,0 +1,219 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module ddr3_s0_mm_interconnect_0_router_006_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [92 - 91 : 0] default_destination_id, + output [4-1 : 0] default_wr_channel, + output [4-1 : 0] default_rd_channel, + output [4-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[92 - 91 : 0]; + + generate + if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment + assign default_src_channel = '0; + end + else begin : default_channel_assignment + assign default_src_channel = 4'b1 << DEFAULT_CHANNEL; + end + endgenerate + + generate + if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin : default_rw_channel_assignment + assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL; + end + endgenerate + +endmodule + + +module ddr3_s0_mm_interconnect_0_router_006 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [106-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [106-1 : 0] src_data, + output reg [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 67; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 92; + localparam PKT_DEST_ID_L = 91; + localparam PKT_PROTECTION_H = 96; + localparam PKT_PROTECTION_L = 94; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 70; + localparam PKT_TRANS_READ = 71; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + wire [4-1 : 0] default_src_channel; + + + + + + + ddr3_s0_mm_interconnect_0_router_006_default_decode the_default_decode( + .default_destination_id (), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 4'b01; + end + + if (destid == 2 ) begin + src_channel = 4'b10; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_001.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_001.sv new file mode 100644 index 0000000..f6bd55b --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_001.sv @@ -0,0 +1,131 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_rsp_demux_001 +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// NUM_OUTPUTS: 3 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module ddr3_s0_mm_interconnect_0_rsp_demux_001 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [106-1 : 0] sink_data, // ST_DATA_W=106 + input [4-1 : 0] sink_channel, // ST_CHANNEL_W=4 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [106-1 : 0] src0_data, // ST_DATA_W=106 + output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [106-1 : 0] src1_data, // ST_DATA_W=106 + output reg [4-1 : 0] src1_channel, // ST_CHANNEL_W=4 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + output reg src2_valid, + output reg [106-1 : 0] src2_data, // ST_DATA_W=106 + output reg [4-1 : 0] src2_channel, // ST_CHANNEL_W=4 + output reg src2_startofpacket, + output reg src2_endofpacket, + input src2_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 3; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + src2_data = sink_data; + src2_startofpacket = sink_startofpacket; + src2_endofpacket = sink_endofpacket; + src2_channel = sink_channel >> NUM_OUTPUTS; + + src2_valid = sink_channel[2] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + assign ready_vector[2] = src2_ready; + + assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_003.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_003.sv new file mode 100644 index 0000000..eb8752a --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_demux_003.sv @@ -0,0 +1,116 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_rsp_demux_003 +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module ddr3_s0_mm_interconnect_0_rsp_demux_003 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [106-1 : 0] sink_data, // ST_DATA_W=106 + input [4-1 : 0] sink_channel, // ST_CHANNEL_W=4 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [106-1 : 0] src0_data, // ST_DATA_W=106 + output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [106-1 : 0] src1_data, // ST_DATA_W=106 + output reg [4-1 : 0] src1_channel, // ST_CHANNEL_W=4 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{2{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux.sv new file mode 100644 index 0000000..a7d75c5 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux.sv @@ -0,0 +1,386 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_rsp_mux +// NUM_INPUTS: 4 +// ARBITRATION_SHARES: 1 1 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// ------------------------------------------ + +module ddr3_s0_mm_interconnect_0_rsp_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [106-1 : 0] sink0_data, + input [4-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [106-1 : 0] sink1_data, + input [4-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + input sink2_valid, + input [106-1 : 0] sink2_data, + input [4-1: 0] sink2_channel, + input sink2_startofpacket, + input sink2_endofpacket, + output sink2_ready, + + input sink3_valid, + input [106-1 : 0] sink3_data, + input [4-1: 0] sink3_channel, + input sink3_startofpacket, + input sink3_endofpacket, + output sink3_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [106-1 : 0] src_data, + output [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 106 + 4 + 2; + localparam NUM_INPUTS = 4; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam PKT_TRANS_LOCK = 72; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + wire [PAYLOAD_W - 1 : 0] sink2_payload; + wire [PAYLOAD_W - 1 : 0] sink3_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + assign valid[2] = sink2_valid; + assign valid[3] = sink3_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[72]; + lock[1] = sink1_data[72]; + lock[2] = sink2_data[72]; + lock[3] = sink3_data[72]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (last_cycle) + packet_in_progress <= 1'b0; + else if (src_valid) + packet_in_progress <= 1'b1; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + // 2 | 1 | 0 + // 3 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} } | + share_2 & { SHARE_COUNTER_W {next_grant[2]} } | + share_3 & { SHARE_COUNTER_W {next_grant[3]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid)); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + wire final_packet_2 = 1'b1; + + wire final_packet_3 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_3, + final_packet_2, + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid)); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + wire [NUM_INPUTS - 1 : 0] next_grant_from_arb; + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant_from_arb), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + assign next_grant = next_grant_from_arb; + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + assign sink2_ready = src_ready && grant[2]; + assign sink3_ready = src_ready && grant[3]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} } | + sink2_payload & {PAYLOAD_W {grant[2]} } | + sink3_payload & {PAYLOAD_W {grant[3]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + assign sink2_payload = {sink2_channel,sink2_data, + sink2_startofpacket,sink2_endofpacket}; + assign sink3_payload = {sink3_channel,sink3_data, + sink3_startofpacket,sink3_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_001.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_001.sv new file mode 100644 index 0000000..70980c9 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_001.sv @@ -0,0 +1,346 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_rsp_mux_001 +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// ------------------------------------------ + +module ddr3_s0_mm_interconnect_0_rsp_mux_001 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [106-1 : 0] sink0_data, + input [4-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [106-1 : 0] sink1_data, + input [4-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [106-1 : 0] src_data, + output [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 106 + 4 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam PKT_TRANS_LOCK = 72; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[72]; + lock[1] = sink1_data[72]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (last_cycle) + packet_in_progress <= 1'b0; + else if (src_valid) + packet_in_progress <= 1'b1; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid)); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid)); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + wire [NUM_INPUTS - 1 : 0] next_grant_from_arb; + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant_from_arb), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + assign next_grant = next_grant_from_arb; + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_002.sv b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_002.sv new file mode 100644 index 0000000..3963129 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux_002.sv @@ -0,0 +1,97 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2014 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2015/08/09 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: ddr3_s0_mm_interconnect_0_rsp_mux_002 +// NUM_INPUTS: 1 +// ARBITRATION_SHARES: 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 72 (arbitration locking enabled) +// ST_DATA_W: 106 +// ST_CHANNEL_W: 4 +// ------------------------------------------ + +module ddr3_s0_mm_interconnect_0_rsp_mux_002 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [106-1 : 0] sink0_data, + input [4-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [106-1 : 0] src_data, + output [4-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 106 + 4 + 2; + localparam NUM_INPUTS = 1; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 106; + localparam ST_CHANNEL_W = 4; + localparam PKT_TRANS_LOCK = 72; + + assign src_valid = sink0_valid; + assign src_data = sink0_data; + assign src_channel = sink0_channel; + assign src_startofpacket = sink0_startofpacket; + assign src_endofpacket = sink0_endofpacket; + assign sink0_ready = src_ready; +endmodule + + + diff --git a/ip/altera/ddr3/ddr3_s0_sequencer_mem.hex b/ip/altera/ddr3/ddr3_s0_sequencer_mem.hex new file mode 100644 index 0000000..ec89e6f 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+:0416EF0000000000F7 +:0416F00000000000F6 +:0416F10000000000F5 +:0416F20000000000F4 +:0416F30000000000F3 +:0416F40000000000F2 +:0416F50000000000F1 +:0416F60000000000F0 +:0416F70000000000EF +:0416F80000000000EE +:0416F90000000000ED +:0416FA0000000000EC +:0416FB0000000000EB +:0416FC0000000000EA +:0416FD0000000000E9 +:0416FE0000000000E8 +:0416FF0000000000E7 +:00000001FF diff --git a/ip/altera/ddr3/ddr3_s0_software/sequencer.c b/ip/altera/ddr3/ddr3_s0_software/sequencer.c new file mode 100644 index 0000000..62cce5d --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_software/sequencer.c @@ -0,0 +1,10850 @@ +/* +* Copyright Altera Corporation (C) 2012-2014. All rights reserved +* +* SPDX-License-Identifier: BSD-3-Clause +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Altera Corporation nor the +* names of its contributors may be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#include "sequencer_defines.h" + +#include "alt_types.h" +#include "system.h" +#if HPS_HW +#include "sdram_io.h" +#else +#include "io.h" +#endif +#include "sequencer.h" +#include "tclrpt.h" +#include "sequencer_auto.h" + +#if HHP_HPS_SIMULATION +#include "hps_controller.h" +#endif + + +/****************************************************************************** + ****************************************************************************** + ** NOTE: Special Rules for Globale Variables ** + ** ** + ** All global variables that are explicitly initialized (including ** + ** explicitly initialized to zero), are only initialized once, during ** + ** configuration time, and not again on reset. This means that they ** + ** preserve their current contents across resets, which is needed for some ** + ** special cases involving communication with external modules. In ** + ** addition, this avoids paying the price to have the memory initialized, ** + ** even for zeroed data, provided it is explicitly set to zero in the code, ** + ** and doesn't rely on implicit initialization. ** + ****************************************************************************** + ******************************************************************************/ + +#ifndef ARMCOMPILER +#if ARRIAV +// Temporary workaround to place the initial stack pointer at a safe offset from end +#define STRINGIFY(s) STRINGIFY_STR(s) +#define STRINGIFY_STR(s) #s +asm(".global __alt_stack_pointer"); +asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER)); +#endif + +#if CYCLONEV +// Temporary workaround to place the initial stack pointer at a safe offset from end +#define STRINGIFY(s) STRINGIFY_STR(s) +#define STRINGIFY_STR(s) #s +asm(".global __alt_stack_pointer"); +asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER)); +#endif +#endif + +#if ENABLE_PRINTF_LOG +#include +#include + +typedef struct { + alt_u32 v; + alt_u32 p; + alt_u32 d; + alt_u32 ps; +} dqs_pos_t; + +/* +The parameters that were previously here are now supplied by generation, until the new data manager is working. +*/ + +struct { + const char *stage; + + alt_u32 vfifo_idx; + + dqs_pos_t gwrite_pos[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + + dqs_pos_t dqs_enable_left_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH]; + dqs_pos_t dqs_enable_right_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH]; + dqs_pos_t dqs_enable_mid[RW_MGR_MEM_IF_READ_DQS_WIDTH]; + + dqs_pos_t dqs_wlevel_left_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + dqs_pos_t dqs_wlevel_right_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + dqs_pos_t dqs_wlevel_mid[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + + alt_32 dq_read_left_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH][RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 dq_read_right_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH][RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 dq_write_left_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 dq_write_right_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 dm_left_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_NUM_DM_PER_WRITE_GROUP]; + alt_32 dm_right_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_NUM_DM_PER_WRITE_GROUP]; +} bfm_gbl; + +#endif + +#if HPS_HW +#include +#endif // HPS_HW + +#if BFM_MODE +#include + +// DPI access function via library +extern long long get_sim_time(void); + +typedef struct { + alt_u32 v; + alt_u32 p; + alt_u32 d; + alt_u32 ps; +} dqs_pos_t; + +/* +The parameters that were previously here are now supplied by generation, until the new data manager is working. +*/ + +struct { + FILE *outfp; + int bfm_skip_guaranteed_write; + int trk_sample_count; + int trk_long_idle_updates; + int lfifo_margin; + const char *stage; + + alt_u32 vfifo_idx; + + dqs_pos_t gwrite_pos[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + + dqs_pos_t dqs_enable_left_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH]; + dqs_pos_t dqs_enable_right_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH]; + dqs_pos_t dqs_enable_mid[RW_MGR_MEM_IF_READ_DQS_WIDTH]; + + dqs_pos_t dqs_wlevel_left_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + dqs_pos_t dqs_wlevel_right_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + dqs_pos_t dqs_wlevel_mid[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + + alt_32 dq_read_left_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH][RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 dq_read_right_edge[RW_MGR_MEM_IF_READ_DQS_WIDTH][RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 dq_write_left_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_MEM_DQ_PER_WRITE_DQS]; + alt_32 dq_write_right_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_MEM_DQ_PER_WRITE_DQS]; + alt_32 dm_left_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_NUM_DM_PER_WRITE_GROUP]; + alt_32 dm_right_edge[RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_NUM_DM_PER_WRITE_GROUP]; +} bfm_gbl; + + +#endif + +#if ENABLE_TCL_DEBUG +debug_data_t my_debug_data; +#endif + +#define NEWVERSION_RDDESKEW 1 +#define NEWVERSION_WRDESKEW 1 +#define NEWVERSION_GW 1 +#define NEWVERSION_WL 1 +#define NEWVERSION_DQSEN 1 + +// Just to make the debugging code more uniform +#ifndef RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 0 +#endif + +#if HALF_RATE +#define HALF_RATE_MODE 1 +#else +#define HALF_RATE_MODE 0 +#endif + +#if QUARTER_RATE +#define QUARTER_RATE_MODE 1 +#else +#define QUARTER_RATE_MODE 0 +#endif +#define DELTA_D 1 + +// case:56390 +// VFIFO_CONTROL_WIDTH_PER_DQS is the number of VFIFOs actually instantiated per DQS. This is always one except: +// AV QDRII where it is 2 for x18 and x18w2, and 4 for x36 and x36w2 +// RLDRAMII x36 and x36w2 where it is 2. +// In 12.0sp1 we set this to 4 for all of the special cases above to keep it simple. +// In 12.0sp2 or 12.1 this should get moved to generation and unified with the same constant used in the phy mgr + +#define VFIFO_CONTROL_WIDTH_PER_DQS 1 + +#if ARRIAV + +#if QDRII + #if RW_MGR_MEM_DQ_PER_READ_DQS > 9 + #undef VFIFO_CONTROL_WIDTH_PER_DQS + #define VFIFO_CONTROL_WIDTH_PER_DQS 4 + #endif +#endif // protocol check + +#if RLDRAMII + #if RW_MGR_MEM_DQ_PER_READ_DQS > 9 + #undef VFIFO_CONTROL_WIDTH_PER_DQS + #define VFIFO_CONTROL_WIDTH_PER_DQS 2 + #endif +#endif // protocol check + +#endif // family check + +// In order to reduce ROM size, most of the selectable calibration steps are +// decided at compile time based on the user's calibration mode selection, +// as captured by the STATIC_CALIB_STEPS selection below. +// +// However, to support simulation-time selection of fast simulation mode, where +// we skip everything except the bare minimum, we need a few of the steps to +// be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the +// check, which is based on the rtl-supplied value, or we dynamically compute the +// value to use based on the dynamically-chosen calibration mode + +#if QDRII +#define BTFLD_FMT "%llx" +#else +#define BTFLD_FMT "%lx" +#endif + +#if BFM_MODE // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + +// TODO: should make this configurable; could even have it read from config file or env at startup +#define DLEVEL 2 +// space around comma is required for varargs macro to remove comma if args is empty +#define DPRINT(level, fmt, args...) if (DLEVEL >= (level)) printf("[%lld] SEQ.C: " fmt "\n" , get_sim_time(), ## args) +#define IPRINT(fmt, args...) printf("[%lld] SEQ.C: " fmt "\n" , get_sim_time(), ## args) +#define BFM_GBL_SET(field,value) bfm_gbl.field = value +#define BFM_GBL_GET(field) bfm_gbl.field +#define BFM_STAGE(label) BFM_GBL_SET(stage,label) +#define BFM_INC_VFIFO bfm_gbl.vfifo_idx = (bfm_gbl.vfifo_idx + 1) % VFIFO_SIZE +#define COV(label) getpid() /* no-op marker for coverage */ + +#elif ENABLE_PRINTF_LOG // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#define DLEVEL 2 + +void wait_printf_queue() +{ + alt_u32 next_entry; + + while (debug_printf_output->count == PRINTF_READ_BUFFER_FIFO_WORDS || debug_printf_output->slave_lock != 0) + {} + + debug_printf_output->master_lock = 1; + next_entry = (debug_printf_output->head + debug_printf_output->count) % PRINTF_READ_BUFFER_FIFO_WORDS; + strcpy((char*)(&(debug_printf_output->read_buffer[next_entry])), (char*)(debug_printf_output->active_word)); + debug_printf_output->count++; + debug_printf_output->master_lock = 0; +} +#define DPRINT(level, fmt, args...) \ + if (DLEVEL >= (level)) { \ + snprintf((char*)(debug_printf_output->active_word), PRINTF_READ_BUFFER_SIZE*4, "DEBUG:" fmt, ## args); \ + wait_printf_queue(); \ + } +#define IPRINT(fmt, args...) \ + snprintf((char*)(debug_printf_output->active_word), PRINTF_READ_BUFFER_SIZE*4, "INFO:" fmt, ## args); \ + wait_printf_queue(); + +#define BFM_GBL_SET(field,value) bfm_gbl.field = value +#define BFM_GBL_GET(field) bfm_gbl.field +#define BFM_STAGE(label) BFM_GBL_SET(stage,label) +#define BFM_INC_VFIFO bfm_gbl.vfifo_idx = (bfm_gbl.vfifo_idx + 1) % VFIFO_SIZE +#define COV(label) + +#elif HPS_HW // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +// For HPS running on actual hardware + +#define DLEVEL 0 +#ifdef HPS_HW_SERIAL_SUPPORT +// space around comma is required for varargs macro to remove comma if args is empty +#define DPRINT(level, fmt, args...) if (DLEVEL >= (level)) printf("SEQ.C: " fmt "\n" , ## args) +#define IPRINT(fmt, args...) printf("SEQ.C: " fmt "\n" , ## args) +#if RUNTIME_CAL_REPORT +#define RPRINT(fmt, args...) printf("SEQ.C: " fmt "\n" , ## args) +#endif +#else +#define DPRINT(level, fmt, args...) +#define IPRINT(fmt, args...) +#endif +#define BFM_GBL_SET(field,value) +#define BFM_GBL_GET(field) ((long unsigned int)0) +#define BFM_STAGE(stage) +#define BFM_INC_VFIFO +#define COV(label) + +#else // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~----------------------------------- + +// Default mode +#define DPRINT(level, fmt, args...) +#define IPRINT(fmt, args...) +#define BFM_GBL_SET(field,value) +#define BFM_GBL_GET(field) 0 +#define BFM_STAGE(stage) +#define BFM_INC_VFIFO +#define COV(label) + +#endif // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~---------------------------------- + +#if BFM_MODE +#define TRACE_FUNC(fmt, args...) DPRINT(1, "%s[%ld]: " fmt, __func__, __LINE__ , ## args) +#else +#define TRACE_FUNC(fmt, args...) DPRINT(1, "%s[%d]: " fmt, __func__, __LINE__ , ## args) +#endif + +#if BFM_MODE +// In BFM mode, we do full calibration as for real-rtl +#define DYNAMIC_CALIB_STEPS STATIC_CALIB_STEPS +#else +#define DYNAMIC_CALIB_STEPS (dyn_calib_steps) +#endif + +#if STATIC_SIM_FILESET +#define STATIC_IN_RTL_SIM CALIB_IN_RTL_SIM +#else +#define STATIC_IN_RTL_SIM 0 +#endif + +#if STATIC_SKIP_MEM_INIT +#define STATIC_SKIP_DELAY_LOOPS CALIB_SKIP_DELAY_LOOPS +#else +#define STATIC_SKIP_DELAY_LOOPS 0 +#endif + +#if STATIC_FULL_CALIBRATION +#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | STATIC_SKIP_DELAY_LOOPS) +#elif STATIC_QUICK_CALIBRATION +#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | CALIB_SKIP_WRITES | CALIB_SKIP_DELAY_SWEEPS | CALIB_SKIP_ALL_BITS_CHK | STATIC_SKIP_DELAY_LOOPS) +#elif STATIC_SKIP_CALIBRATION +#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | CALIB_SKIP_WRITES | CALIB_SKIP_WLEVEL | CALIB_SKIP_LFIFO | CALIB_SKIP_VFIFO | CALIB_SKIP_DELAY_SWEEPS | CALIB_SKIP_ALL_BITS_CHK | STATIC_SKIP_DELAY_LOOPS) +#else +#undef STATIC_CALIB_STEPS +// This should force an error +#endif + +// calibration steps requested by the rtl +alt_u16 dyn_calib_steps = 0; + +// To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option +// instead of static, we use boolean logic to select between +// non-skip and skip values +// +// The mask is set to include all bits when not-skipping, but is +// zero when skipping + +alt_u16 skip_delay_mask = 0; // mask off bits when skipping/not-skipping + +#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \ + ((non_skip_value) & skip_delay_mask) + + +// TODO: The skip group strategy is completely missing + +gbl_t *gbl = 0; +param_t *param = 0; + +alt_u32 curr_shadow_reg = 0; + +#if ENABLE_DELAY_CHAIN_WRITE +alt_u32 vfifo_settings[RW_MGR_MEM_IF_READ_DQS_WIDTH]; +#endif // ENABLE_DELAY_CHAIN_WRITE + +#if ENABLE_NON_DESTRUCTIVE_CALIB +// Technically, the use of these variables could be separated from ENABLE_NON_DESTRUCTIVE_CALIB +// but currently they are part of a single feature which is not fully validated, so we're keeping +// them together + +// These variables can be modified by external rtl modules, and hence are "volatile" +volatile alt_u32 no_init = 0; +volatile alt_u32 abort_cal = 0; +#endif + +alt_u32 rw_mgr_mem_calibrate_write_test (alt_u32 rank_bgn, alt_u32 write_group, alt_u32 use_dm, alt_u32 all_correct, t_btfld *bit_chk, alt_u32 all_ranks); + +#if ENABLE_BRINGUP_DEBUGGING + +#define DI_BUFFER_DEBUG_SIZE 64 + +alt_u8 di_buf_gbl[DI_BUFFER_DEBUG_SIZE*4] = {0}; + +void load_di_buf_gbl(void) +{ + int i; + int j; + + for (i = 0; i < DI_BUFFER_DEBUG_SIZE; i++) { + alt_u32 val = IORD_32DIRECT(RW_MGR_DI_BASE + i*4, 0); + for (j = 0; j < 4; j++) { + alt_u8 byte = (val >> (8*j)) & 0xff; + di_buf_gbl[i*4 + j] = byte; + } + } +} + +#endif /* ENABLE_BRINGUP_DEBUGGING */ + + +#if ENABLE_DQSEN_SWEEP +void init_di_buffer(void) +{ + alt_u32 i; + + debug_data->di_report.flags = 0; + debug_data->di_report.cur_samples = 0; + + for (i = 0; i < NUM_DI_SAMPLE; i++) + { + debug_data->di_report.di_buffer[i].bit_chk = 0; + debug_data->di_report.di_buffer[i].delay = 0; + debug_data->di_report.di_buffer[i].d = 0; + debug_data->di_report.di_buffer[i].v = 0; + debug_data->di_report.di_buffer[i].p = 0; + debug_data->di_report.di_buffer[i].di_buffer_0a = 0; + debug_data->di_report.di_buffer[i].di_buffer_0b = 0; + debug_data->di_report.di_buffer[i].di_buffer_1a = 0; + debug_data->di_report.di_buffer[i].di_buffer_1b = 0; + debug_data->di_report.di_buffer[i].di_buffer_2a = 0; + debug_data->di_report.di_buffer[i].di_buffer_2b = 0; + debug_data->di_report.di_buffer[i].di_buffer_3a = 0; + debug_data->di_report.di_buffer[i].di_buffer_3b = 0; + debug_data->di_report.di_buffer[i].di_buffer_4a = 0; + debug_data->di_report.di_buffer[i].di_buffer_4b = 0; + } +} + +inline void flag_di_buffer_ready() +{ + debug_data->di_report.flags |= DI_REPORT_FLAGS_READY; +} + +inline void flag_di_buffer_done() +{ + debug_data->di_report.flags |= DI_REPORT_FLAGS_READY; + debug_data->di_report.flags |= DI_REPORT_FLAGS_DONE; +} + +void wait_di_buffer(void) +{ + if (debug_data->di_report.cur_samples == NUM_DI_SAMPLE) + { + flag_di_buffer_ready(); + while (debug_data->di_report.cur_samples != 0) + { + } + debug_data->di_report.flags = 0; + } +} + +void sample_di_data(alt_u32 bit_chk, alt_u32 delay, alt_u32 d, alt_u32 v, alt_u32 p) +{ + alt_u32 k; + alt_u32 di_status_word; + alt_u32 di_word_avail; + alt_u32 di_write_to_read_ratio; + alt_u32 di_write_to_read_ratio_2_exp; + + wait_di_buffer(); + + k = debug_data->di_report.cur_samples; + + debug_data->di_report.di_buffer[k].bit_chk = bit_chk; + debug_data->di_report.di_buffer[k].delay = delay; + debug_data->di_report.di_buffer[k].d = d; + debug_data->di_report.di_buffer[k].v = v; + debug_data->di_report.di_buffer[k].p = p; + + di_status_word = IORD_32DIRECT(BASE_RW_MGR + 8, 0); + di_word_avail = di_status_word & 0x0000FFFF; + di_write_to_read_ratio = (di_status_word & 0x00FF0000) >> 16; + di_write_to_read_ratio_2_exp = (di_status_word & 0xFF000000) >> 24; + + debug_data->di_report.di_buffer[k].di_buffer_0a = IORD_32DIRECT(BASE_RW_MGR + 16 + 0*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_0b = IORD_32DIRECT(BASE_RW_MGR + 16 + 1*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_1a = IORD_32DIRECT(BASE_RW_MGR + 16 + 2*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_1b = IORD_32DIRECT(BASE_RW_MGR + 16 + 3*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_2a = IORD_32DIRECT(BASE_RW_MGR + 16 + 4*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_2b = IORD_32DIRECT(BASE_RW_MGR + 16 + 5*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_3a = IORD_32DIRECT(BASE_RW_MGR + 16 + 6*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_3b = IORD_32DIRECT(BASE_RW_MGR + 16 + 7*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_4a = IORD_32DIRECT(BASE_RW_MGR + 16 + 8*4, 0); + debug_data->di_report.di_buffer[k].di_buffer_4b = IORD_32DIRECT(BASE_RW_MGR + 16 + 9*4, 0); + + debug_data->di_report.cur_samples = debug_data->di_report.cur_samples + 1; +} +#endif + +// This (TEST_SIZE) is used to test handling of large roms, to make +// sure we are sizing things correctly +// Note, the initialized data takes up twice the space in rom, since +// there needs to be a copy with the initial value and a copy that is +// written too, since on soft-reset, it needs to have the initial values +// without reloading the memory from external sources + +// #define TEST_SIZE (6*1024) + +#ifdef TEST_SIZE + +#define PRE_POST_TEST_SIZE 3 + +unsigned int pre_test_size_mem[PRE_POST_TEST_SIZE] = { 1, 2, 3}; + +unsigned int test_size_mem[TEST_SIZE/sizeof(unsigned int)] = { 100, 200, 300 }; + +unsigned int post_test_size_mem[PRE_POST_TEST_SIZE] = {10, 20, 30}; + +void write_test_mem(void) +{ + int i; + + for (i = 0; i < PRE_POST_TEST_SIZE; i++) { + pre_test_size_mem[i] = (i+1)*10; + post_test_size_mem[i] = (i+1); + } + + for (i = 0; i < sizeof(test_size_mem)/sizeof(unsigned int); i++) { + test_size_mem[i] = i; + } + +} + +int check_test_mem(int start) +{ + int i; + + for (i = 0; i < PRE_POST_TEST_SIZE; i++) { + if (start) { + if (pre_test_size_mem[i] != (i+1)) { + return 0; + } + if (post_test_size_mem[i] != (i+1)*10) { + return 0; + } + } else { + if (pre_test_size_mem[i] != (i+1)*10) { + return 0; + } + if (post_test_size_mem[i] != (i+1)) { + return 0; + } + } + } + + for (i = 0; i < sizeof(test_size_mem)/sizeof(unsigned int); i++) { + if (start) { + if (i < 3) { + if (test_size_mem[i] != (i+1)*100) { + return 0; + } + } else { + if (test_size_mem[i] != 0) { + return 0; + } + } + } else { + if (test_size_mem[i] != i) { + return 0; + } + } + } + + return 1; +} + +#endif // TEST_SIZE + +static void set_failing_group_stage(alt_u32 group, alt_u32 stage, alt_u32 substage) +{ + ALTERA_ASSERT(group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + // Only set the global stage if there was not been any other failing group + if (gbl->error_stage == CAL_STAGE_NIL) + { + gbl->error_substage = substage; + gbl->error_stage = stage; + gbl->error_group = group; + TCLRPT_SET(debug_summary_report->error_sub_stage, substage); + TCLRPT_SET(debug_summary_report->error_stage, stage); + TCLRPT_SET(debug_summary_report->error_group, group); + + } + + // Always set the group specific errors + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][group].error_stage, stage); + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][group].error_sub_stage, substage); + +} + +static inline void reg_file_set_group(alt_u32 set_group) +{ + // Read the current group and stage + alt_u32 cur_stage_group = IORD_32DIRECT (REG_FILE_CUR_STAGE, 0); + + // Clear the group + cur_stage_group &= 0x0000FFFF; + + // Set the group + cur_stage_group |= (set_group << 16); + + // Write the data back + IOWR_32DIRECT (REG_FILE_CUR_STAGE, 0, cur_stage_group); +} + +static inline void reg_file_set_stage(alt_u32 set_stage) +{ + // Read the current group and stage + alt_u32 cur_stage_group = IORD_32DIRECT (REG_FILE_CUR_STAGE, 0); + + // Clear the stage and substage + cur_stage_group &= 0xFFFF0000; + + // Set the stage + cur_stage_group |= (set_stage & 0x000000FF); + + // Write the data back + IOWR_32DIRECT (REG_FILE_CUR_STAGE, 0, cur_stage_group); +} + +static inline void reg_file_set_sub_stage(alt_u32 set_sub_stage) +{ + // Read the current group and stage + alt_u32 cur_stage_group = IORD_32DIRECT (REG_FILE_CUR_STAGE, 0); + + // Clear the substage + cur_stage_group &= 0xFFFF00FF; + + // Set the sub stage + cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00); + + // Write the data back + IOWR_32DIRECT (REG_FILE_CUR_STAGE, 0, cur_stage_group); +} + +static inline alt_u32 is_write_group_enabled_for_dm(alt_u32 write_group) +{ +#if DM_PINS_ENABLED + #if RLDRAMII + alt_32 decrement_counter = write_group + 1; + + while (decrement_counter > 0) + { + decrement_counter -= RW_MGR_MEM_IF_WRITE_DQS_WIDTH/RW_MGR_MEM_DATA_MASK_WIDTH; + } + + if (decrement_counter == 0) + { + return 1; + } + else + { + return 0; + } + #else + return 1; + #endif +#else + return 0; +#endif +} + +static inline void select_curr_shadow_reg_using_rank(alt_u32 rank) +{ +#if USE_SHADOW_REGS + //USER Map the rank to its shadow reg and set the global variable + curr_shadow_reg = (rank >> (NUM_RANKS_PER_SHADOW_REG - 1)); +#endif +} + +void initialize(void) +{ + TRACE_FUNC(); + + //USER calibration has control over path to memory + +#if HARD_PHY + // In Hard PHY this is a 2-bit control: + // 0: AFI Mux Select + // 1: DDIO Mux Select + IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0x3); +#else + IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 1); +#endif + + //USER memory clock is not stable we begin initialization + + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 0); + + //USER calibration status all set to zero + + IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, 0); + IOWR_32DIRECT (PHY_MGR_CAL_DEBUG_INFO, 0, 0); + + if (((DYNAMIC_CALIB_STEPS) & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) { + param->read_correct_mask_vg = ((t_btfld)1 << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1; + param->write_correct_mask_vg = ((t_btfld)1 << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1; + param->read_correct_mask = ((t_btfld)1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1; + param->write_correct_mask = ((t_btfld)1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1; + param->dm_correct_mask = ((t_btfld)1 << (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH)) - 1; + } +} + + +#if MRS_MIRROR_PING_PONG_ATSO +// This code is specific to the ATSO setup. There are two ways to set +// the cs/odt mask: +// 1. the normal way (set_rank_and_odt_mask) +// This method will be used in general. The behavior will be to unmask +// BOTH CS (i.e. broadcast to both sides as if calibrating one large interface). +// 2. this function +// This method will be used for MRS settings only. This allows us to do settings +// on a per-side basis. This is needed because Slot 1 Rank 1 needs a mirrored MRS. +// This function is specific to our setup ONLY. +void set_rank_and_odt_mask_for_ping_pong_atso(alt_u32 side, alt_u32 odt_mode) +{ + alt_u32 odt_mask_0 = 0; + alt_u32 odt_mask_1 = 0; + alt_u32 cs_and_odt_mask; + + if(odt_mode == RW_MGR_ODT_MODE_READ_WRITE) + { + //USER 1 Rank + //USER Read: ODT = 0 + //USER Write: ODT = 1 + odt_mask_0 = 0x0; + odt_mask_1 = 0x1; + } + else + { + odt_mask_0 = 0x0; + odt_mask_1 = 0x0; + } + + cs_and_odt_mask = + (0xFF & ~(1 << side)) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); + + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, cs_and_odt_mask); +} +#endif + +#if DDR3 +void set_rank_and_odt_mask(alt_u32 rank, alt_u32 odt_mode) +{ + alt_u32 odt_mask_0 = 0; + alt_u32 odt_mask_1 = 0; + alt_u32 cs_and_odt_mask; + + if(odt_mode == RW_MGR_ODT_MODE_READ_WRITE) + { +#if USE_SHADOW_REGS + alt_u32 rank_one_hot = (0xFF & (1 << rank)); + select_curr_shadow_reg_using_rank(rank); + + //USER Assert afi_rrank and afi_wrank. These signals ultimately drive + //USER the read/write rank select signals which select the shadow register. + IOWR_32DIRECT (RW_MGR_SET_ACTIVE_RANK, 0, rank_one_hot); +#endif + + if ( LRDIMM ) { + // USER LRDIMMs have two cases to consider: single-slot and dual-slot. + // USER In single-slot, assert ODT for write only. + // USER In dual-slot, assert ODT for both slots for write, + // USER and on the opposite slot only for reads. + // USER + // USER Further complicating this is that both DIMMs have either 1 or 2 ODT + // USER inputs, which do the same thing (only one is actually required). + if ((RW_MGR_MEM_CHIP_SELECT_WIDTH/RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM) == 1) { + // USER Single-slot case + if (RW_MGR_MEM_ODT_WIDTH == 1) { + // USER Read = 0, Write = 1 + odt_mask_0 = 0x0; + odt_mask_1 = 0x1; + } else if (RW_MGR_MEM_ODT_WIDTH == 2) { + // USER Read = 00, Write = 11 + odt_mask_0 = 0x0; + odt_mask_1 = 0x3; + } + } else if ((RW_MGR_MEM_CHIP_SELECT_WIDTH/RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM) == 2) { + // USER Dual-slot case + if (RW_MGR_MEM_ODT_WIDTH == 2) { + // USER Read: asserted for opposite slot, Write: asserted for both + odt_mask_0 = (rank < 2) ? 0x2 : 0x1; + odt_mask_1 = 0x3; + } else if (RW_MGR_MEM_ODT_WIDTH == 4) { + // USER Read: asserted for opposite slot, Write: asserted for both + odt_mask_0 = (rank < 2) ? 0xC : 0x3; + odt_mask_1 = 0xF; + } + } + } else if(RW_MGR_MEM_NUMBER_OF_RANKS == 1) { + //USER 1 Rank + //USER Read: ODT = 0 + //USER Write: ODT = 1 + odt_mask_0 = 0x0; + odt_mask_1 = 0x1; + } else if(RW_MGR_MEM_NUMBER_OF_RANKS == 2) { + //USER 2 Ranks + if(RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1 || + (RDIMM && RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 2 + && RW_MGR_MEM_CHIP_SELECT_WIDTH == 4)) { + //USER - Dual-Slot , Single-Rank (1 chip-select per DIMM) + //USER OR + //USER - RDIMM, 4 total CS (2 CS per DIMM) means 2 DIMM + //USER Since MEM_NUMBER_OF_RANKS is 2 they are both single rank + //USER with 2 CS each (special for RDIMM) + //USER Read: Turn on ODT on the opposite rank + //USER Write: Turn on ODT on all ranks + odt_mask_0 = 0x3 & ~(1 << rank); + odt_mask_1 = 0x3; + } else { + //USER - Single-Slot , Dual-rank DIMMs (2 chip-selects per DIMM) + //USER Read: Turn on ODT off on all ranks + //USER Write: Turn on ODT on active rank + odt_mask_0 = 0x0; + odt_mask_1 = 0x3 & (1 << rank); + } + } else { + //USER 4 Ranks + //USER Read: + //USER ----------+-----------------------+ + //USER | | + //USER | ODT | + //USER Read From +-----------------------+ + //USER Rank | 3 | 2 | 1 | 0 | + //USER ----------+-----+-----+-----+-----+ + //USER 0 | 0 | 1 | 0 | 0 | + //USER 1 | 1 | 0 | 0 | 0 | + //USER 2 | 0 | 0 | 0 | 1 | + //USER 3 | 0 | 0 | 1 | 0 | + //USER ----------+-----+-----+-----+-----+ + //USER + //USER Write: + //USER ----------+-----------------------+ + //USER | | + //USER | ODT | + //USER Write To +-----------------------+ + //USER Rank | 3 | 2 | 1 | 0 | + //USER ----------+-----+-----+-----+-----+ + //USER 0 | 0 | 1 | 0 | 1 | + //USER 1 | 1 | 0 | 1 | 0 | + //USER 2 | 0 | 1 | 0 | 1 | + //USER 3 | 1 | 0 | 1 | 0 | + //USER ----------+-----+-----+-----+-----+ + switch(rank) + { + case 0: + odt_mask_0 = 0x4; + odt_mask_1 = 0x5; + break; + case 1: + odt_mask_0 = 0x8; + odt_mask_1 = 0xA; + break; + case 2: + odt_mask_0 = 0x1; + odt_mask_1 = 0x5; + break; + case 3: + odt_mask_0 = 0x2; + odt_mask_1 = 0xA; + break; + } + } + } + else + { + odt_mask_0 = 0x0; + odt_mask_1 = 0x0; + } + +#if ADVANCED_ODT_CONTROL + // odt_mask_0 = read + // odt_mask_1 = write + odt_mask_0 = (CFG_READ_ODT_CHIP >> (RW_MGR_MEM_ODT_WIDTH * rank)); + odt_mask_1 = (CFG_WRITE_ODT_CHIP >> (RW_MGR_MEM_ODT_WIDTH * rank)); + odt_mask_0 &= ((1 << RW_MGR_MEM_ODT_WIDTH) - 1); + odt_mask_1 &= ((1 << RW_MGR_MEM_ODT_WIDTH) - 1); +#endif + +#if MRS_MIRROR_PING_PONG_ATSO + // See set_cs_and_odt_mask_for_ping_pong_atso + cs_and_odt_mask = + (0xFC) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); +#else + if(RDIMM && RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 2 + && RW_MGR_MEM_CHIP_SELECT_WIDTH == 4 && RW_MGR_MEM_NUMBER_OF_RANKS == 2) { + //USER See RDIMM special case above + cs_and_odt_mask = + (0xFF & ~(1 << (2*rank))) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); + } else if (LRDIMM) { +#if LRDIMM + // USER LRDIMM special cases - When RM=2, CS[2] is remapped to A[16] so skip it, + // USER and when RM=4, CS[3:2] are remapped to A[17:16] so skip them both. + alt_u32 lrdimm_rank = 0; + alt_u32 lrdimm_rank_mask = 0; + + //USER When rank multiplication is active, the remapped CS pins must be forced low + //USER instead of high for proper targetted RTT_NOM programming. + if (LRDIMM_RANK_MULTIPLICATION_FACTOR == 2) { + // USER Mask = CS[5:0] = 011011 + lrdimm_rank_mask = (0x3 | (0x3 << 3)); + } else if (LRDIMM_RANK_MULTIPLICATION_FACTOR == 4) { + // USER Mask = CS[7:0] = 00110011 + lrdimm_rank_mask = (0x3 | (0x3 << 4)); + } + + // USER Handle LRDIMM cases where Rank multiplication may be active + if (((RW_MGR_MEM_CHIP_SELECT_WIDTH/RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM) == 1)) { + // USER Single-DIMM case + lrdimm_rank = ~(1 << rank); + } else if ((RW_MGR_MEM_CHIP_SELECT_WIDTH/RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM) == 2) { + if (rank < (RW_MGR_MEM_NUMBER_OF_RANKS >> 1)) { + // USER Dual-DIMM case, accessing first slot + lrdimm_rank = ~(1 << rank); + } else { + // USER Dual-DIMM case, accessing second slot + lrdimm_rank = ~(1 << (rank + RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM - (RW_MGR_MEM_NUMBER_OF_RANKS>>1))); + } + } + cs_and_odt_mask = + (lrdimm_rank_mask & lrdimm_rank) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); +#endif // LRDIMM + } else { + cs_and_odt_mask = + (0xFF & ~(1 << rank)) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); + } +#endif + + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, cs_and_odt_mask); +} +#else +#if DDR2 +void set_rank_and_odt_mask(alt_u32 rank, alt_u32 odt_mode) +{ + alt_u32 odt_mask_0 = 0; + alt_u32 odt_mask_1 = 0; + alt_u32 cs_and_odt_mask; + + if(odt_mode == RW_MGR_ODT_MODE_READ_WRITE) + { + if(RW_MGR_MEM_NUMBER_OF_RANKS == 1) { + //USER 1 Rank + //USER Read: ODT = 0 + //USER Write: ODT = 1 + odt_mask_0 = 0x0; + odt_mask_1 = 0x1; + } else if(RW_MGR_MEM_NUMBER_OF_RANKS == 2) { + //USER 2 Ranks + if(RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1 || + (RDIMM && RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 2 + && RW_MGR_MEM_CHIP_SELECT_WIDTH == 4)) { + //USER - Dual-Slot , Single-Rank (1 chip-select per DIMM) + //USER OR + //USER - RDIMM, 4 total CS (2 CS per DIMM) means 2 DIMM + //USER Since MEM_NUMBER_OF_RANKS is 2 they are both single rank + //USER with 2 CS each (special for RDIMM) + //USER Read/Write: Turn on ODT on the opposite rank + odt_mask_0 = 0x3 & ~(1 << rank); + odt_mask_1 = 0x3 & ~(1 << rank); + } else { + //USER - Single-Slot , Dual-rank DIMMs (2 chip-selects per DIMM) + //USER Read: Turn on ODT off on all ranks + //USER Write: Turn on ODT on active rank + odt_mask_0 = 0x0; + odt_mask_1 = 0x3 & (1 << rank); + } + } else { + //USER 4 Ranks + //USER Read/Write: + //USER -----------+-----------------------+ + //USER | | + //USER | ODT | + //USER Read/Write | | + //USER From +-----------------------+ + //USER Rank | 3 | 2 | 1 | 0 | + //USER -----------+-----+-----+-----+-----+ + //USER 0 | 0 | 1 | 0 | 0 | + //USER 1 | 1 | 0 | 0 | 0 | + //USER 2 | 0 | 0 | 0 | 1 | + //USER 3 | 0 | 0 | 1 | 0 | + //USER -----------+-----+-----+-----+-----+ + switch(rank) + { + case 0: + odt_mask_0 = 0x4; + odt_mask_1 = 0x4; + break; + case 1: + odt_mask_0 = 0x8; + odt_mask_1 = 0x8; + break; + case 2: + odt_mask_0 = 0x1; + odt_mask_1 = 0x1; + break; + case 3: + odt_mask_0 = 0x2; + odt_mask_1 = 0x2; + break; + } + } + } + else + { + odt_mask_0 = 0x0; + odt_mask_1 = 0x0; + } + + if(RDIMM && RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 2 + && RW_MGR_MEM_CHIP_SELECT_WIDTH == 4 && RW_MGR_MEM_NUMBER_OF_RANKS == 2) { + //USER See RDIMM/LRDIMM special case above + cs_and_odt_mask = + (0xFF & ~(1 << (2*rank))) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); + } else { + cs_and_odt_mask = + (0xFF & ~(1 << rank)) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); + } + + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, cs_and_odt_mask); +} +#else // QDRII and RLDRAMx +void set_rank_and_odt_mask(alt_u32 rank, alt_u32 odt_mode) +{ + alt_u32 cs_and_odt_mask = + (0xFF & ~(1 << rank)); + + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, cs_and_odt_mask); +} +#endif +#endif + +//USER Given a rank, select the set of shadow registers that is responsible for the +//USER delays of such rank, so that subsequent SCC updates will go to those shadow +//USER registers. +void select_shadow_regs_for_update (alt_u32 rank, alt_u32 group, alt_u32 update_scan_chains) +{ +#if USE_SHADOW_REGS + alt_u32 rank_one_hot = (0xFF & (1 << rank)); + + //USER Assert afi_rrank and afi_wrank. These signals ultimately drive + //USER the read/write rank select signals which select the shadow register. + IOWR_32DIRECT (RW_MGR_SET_ACTIVE_RANK, 0, rank_one_hot); + + //USER Cause the SCC manager to switch its register file, which is used as + //USER local cache of the various dtap/ptap settings. There's one register file + //USER per shadow register set. + IOWR_32DIRECT (SCC_MGR_ACTIVE_RANK, 0, rank_one_hot); + + if (update_scan_chains) { + alt_u32 i; + + //USER On the read side, a memory read is required because the read rank + //USER select signal (as well as the postamble delay chain settings) is clocked + //USER into the periphery by the postamble signal. Simply asserting afi_rrank + //USER is not enough. If update_scc_regfile is not set, we assume there'll be a + //USER subsequent read that'll handle this. + for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; ++i) { + + //USER The dummy read can go to any non-skipped rank. + //USER Skipped ranks are uninitialized and their banks are un-activated. + //USER Accessing skipped ranks can lead to bad behavior. + if (! param->skip_ranks[i]) { + + set_rank_and_odt_mask(i, RW_MGR_ODT_MODE_READ_WRITE); + + // must re-assert afi_wrank/afi_rrank prior to issuing read + // because set_rank_and_odt_mask may have changed the signals. + IOWR_32DIRECT (RW_MGR_SET_ACTIVE_RANK, 0, rank_one_hot); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x10); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x10); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B); + + IOWR_32DIRECT (RW_MGR_RUN_ALL_GROUPS, 0, __RW_MGR_READ_B2B); + + //USER The dummy read above may cause the DQS enable signal to be stuck high. + //USER The following corrects this. + IOWR_32DIRECT (RW_MGR_RUN_ALL_GROUPS, 0, __RW_MGR_CLEAR_DQS_ENABLE); + + set_rank_and_odt_mask(i, RW_MGR_ODT_MODE_OFF); + + break; + } + } + + //USER Reset the fifos to get pointers to known state + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + + //USER On the write side the afi_wrank signal eventually propagates to the I/O + //USER through the write datapath. We need to make sure we wait long enough for + //USER this to happen. The operations above should be enough, hence no extra delay + //USER inserted here. + + //USER Make sure the data in the I/O scan chains are in-sync with the register + //USER file inside the SCC manager. If we don't do this, a subsequent SCC_UPDATE + //USER may cause stale data for the other shadow register to be loaded. This must + //USER be done for every scan chain of the current group. Note that in shadow + //USER register mode, the SCC_UPDATE signal is per-group. + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group); + + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, group); + IOWR_32DIRECT (SCC_MGR_DQS_IO_ENA, 0, 0); + + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + IOWR_32DIRECT (SCC_MGR_DQ_ENA, 0, i); + } + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { + IOWR_32DIRECT (SCC_MGR_DM_ENA, 0, i); + } + } + + //USER Map the rank to its shadow reg + select_curr_shadow_reg_using_rank(rank); +#endif +} + +#if HHP_HPS +void scc_mgr_initialize(void) +{ + // Clear register file for HPS + // 16 (2^4) is the size of the full register file in the scc mgr: + // RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS + MEM_IF_READ_DQS_WIDTH - 1) + 1; + alt_u32 i; + for (i = 0; i < 16; i++) { + DPRINT(1, "Clearing SCC RFILE index %lu", i); + IOWR_32DIRECT(SCC_MGR_HHP_RFILE, i << 2, 0); + } +} +#endif + +inline void scc_mgr_set_dqs_bus_in_delay(alt_u32 read_group, alt_u32 delay) +{ + ALTERA_ASSERT(read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQS_IN_DELAY(read_group, delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][read_group].dqs_bus_in_delay, delay); + +} + +static inline void scc_mgr_set_dqs_io_in_delay(alt_u32 write_group, alt_u32 delay) +{ + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQS_IO_IN_DELAY(delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].dqs_io_in_delay, delay); + +} + +static inline void scc_mgr_set_dqs_en_phase(alt_u32 read_group, alt_u32 phase) +{ + ALTERA_ASSERT(read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQS_EN_PHASE(read_group, phase); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][read_group].dqs_en_phase, phase); + +} + +void scc_mgr_set_dqs_en_phase_all_ranks (alt_u32 read_group, alt_u32 phase) +{ + alt_u32 r; + alt_u32 update_scan_chains; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + //USER although the h/w doesn't support different phases per shadow register, + //USER for simplicity our scc manager modeling keeps different phase settings per + //USER shadow reg, and it's important for us to keep them in sync to match h/w. + //USER for efficiency, the scan chain update should occur only once to sr0. + update_scan_chains = (r == 0) ? 1 : 0; + + select_shadow_regs_for_update(r, read_group, update_scan_chains); + scc_mgr_set_dqs_en_phase(read_group, phase); + + if (update_scan_chains) { + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + } +} + + +static inline void scc_mgr_set_dqdqs_output_phase(alt_u32 write_group, alt_u32 phase) +{ + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + #if CALIBRATE_BIT_SLIPS + alt_u32 num_fr_slips = 0; + while (phase > IO_DQDQS_OUT_PHASE_MAX) { + phase -= IO_DLL_CHAIN_LENGTH; + num_fr_slips++; + } + IOWR_32DIRECT (PHY_MGR_FR_SHIFT, write_group*4, num_fr_slips); +#endif + + // Load the setting in the SCC manager + WRITE_SCC_DQDQS_OUT_PHASE(write_group, phase); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].dqdqs_out_phase, phase); + +} + +void scc_mgr_set_dqdqs_output_phase_all_ranks (alt_u32 write_group, alt_u32 phase) +{ + alt_u32 r; + alt_u32 update_scan_chains; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + //USER although the h/w doesn't support different phases per shadow register, + //USER for simplicity our scc manager modeling keeps different phase settings per + //USER shadow reg, and it's important for us to keep them in sync to match h/w. + //USER for efficiency, the scan chain update should occur only once to sr0. + update_scan_chains = (r == 0) ? 1 : 0; + + select_shadow_regs_for_update(r, write_group, update_scan_chains); + scc_mgr_set_dqdqs_output_phase(write_group, phase); + + if (update_scan_chains) { + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, write_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + } +} + + +static inline void scc_mgr_set_dqs_en_delay(alt_u32 read_group, alt_u32 delay) +{ + ALTERA_ASSERT(read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQS_EN_DELAY(read_group, delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][read_group].dqs_en_delay, delay); + +} + +void scc_mgr_set_dqs_en_delay_all_ranks (alt_u32 read_group, alt_u32 delay) +{ + alt_u32 r; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + + select_shadow_regs_for_update(r, read_group, 0); + + scc_mgr_set_dqs_en_delay(read_group, delay); + + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, read_group); + +#if !USE_SHADOW_REGS + // In shadow register mode, the T11 settings are stored in registers + // in the core, which are updated by the DQS_ENA signals. Not issuing + // the SCC_MGR_UPD command allows us to save lots of rank switching + // overhead, by calling select_shadow_regs_for_update with update_scan_chains + // set to 0. + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); +#endif + } +} + +static void scc_mgr_set_oct_out1_delay(alt_u32 write_group, alt_u32 delay) +{ + alt_u32 read_group; + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + // Load the setting in the SCC manager + // Although OCT affects only write data, the OCT delay is controlled by the DQS logic block + // which is instantiated once per read group. For protocols where a write group consists + // of multiple read groups, the setting must be set multiple times. + for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; + read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; + ++read_group) { + + WRITE_SCC_OCT_OUT1_DELAY(read_group, delay); + } + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].oct_out_delay1, delay); + +} + +static void scc_mgr_set_oct_out2_delay(alt_u32 write_group, alt_u32 delay) +{ + alt_u32 read_group; + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + // Load the setting in the SCC manager + // Although OCT affects only write data, the OCT delay is controlled by the DQS logic block + // which is instantiated once per read group. For protocols where a write group consists + // of multiple read groups, the setting must be set multiple times. + for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; + read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; + ++read_group) { + + WRITE_SCC_OCT_OUT2_DELAY(read_group, delay); + } + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].oct_out_delay2, delay); + +} + +static inline void scc_mgr_set_dqs_bypass(alt_u32 write_group, alt_u32 bypass) +{ + // Load the setting in the SCC manager + WRITE_SCC_DQS_BYPASS(write_group, bypass); +} + +inline void scc_mgr_set_dq_out1_delay(alt_u32 write_group, alt_u32 dq_in_group, alt_u32 delay) +{ +#if ENABLE_TCL_DEBUG || ENABLE_ASSERT + alt_u32 dq = write_group*RW_MGR_MEM_DQ_PER_WRITE_DQS + dq_in_group; +#endif + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + ALTERA_ASSERT(dq < RW_MGR_MEM_DATA_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQ_OUT1_DELAY(dq_in_group, delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dq_settings[curr_shadow_reg][dq].dq_out_delay1, delay); + +} + +inline void scc_mgr_set_dq_out2_delay(alt_u32 write_group, alt_u32 dq_in_group, alt_u32 delay) +{ +#if ENABLE_TCL_DEBUG || ENABLE_ASSERT + alt_u32 dq = write_group*RW_MGR_MEM_DQ_PER_WRITE_DQS + dq_in_group; +#endif + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + ALTERA_ASSERT(dq < RW_MGR_MEM_DATA_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQ_OUT2_DELAY(dq_in_group, delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dq_settings[curr_shadow_reg][dq].dq_out_delay2, delay); + +} + +inline void scc_mgr_set_dq_in_delay(alt_u32 write_group, alt_u32 dq_in_group, alt_u32 delay) +{ +#if ENABLE_TCL_DEBUG || ENABLE_ASSERT + alt_u32 dq = write_group*RW_MGR_MEM_DQ_PER_WRITE_DQS + dq_in_group; +#endif + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + ALTERA_ASSERT(dq < RW_MGR_MEM_DATA_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQ_IN_DELAY(dq_in_group, delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dq_settings[curr_shadow_reg][dq].dq_in_delay, delay); + +} + +static inline void scc_mgr_set_dq_bypass(alt_u32 write_group, alt_u32 dq_in_group, alt_u32 bypass) +{ + // Load the setting in the SCC manager + WRITE_SCC_DQ_BYPASS(dq_in_group, bypass); +} + +static inline void scc_mgr_set_rfifo_mode(alt_u32 write_group, alt_u32 dq_in_group, alt_u32 mode) +{ + // Load the setting in the SCC manager + WRITE_SCC_RFIFO_MODE(dq_in_group, mode); +} + +static inline void scc_mgr_set_hhp_extras(void) +{ + // Load the fixed setting in the SCC manager + // bits: 0:0 = 1'b1 - dqs bypass + // bits: 1:1 = 1'b1 - dq bypass + // bits: 4:2 = 3'b001 - rfifo_mode + // bits: 6:5 = 2'b01 - rfifo clock_select + // bits: 7:7 = 1'b0 - separate gating from ungating setting + // bits: 8:8 = 1'b0 - separate OE from Output delay setting + alt_u32 value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0); + WRITE_SCC_HHP_EXTRAS(value); +} + +static inline void scc_mgr_set_hhp_dqse_map(void) +{ + // Load the fixed setting in the SCC manager + WRITE_SCC_HHP_DQSE_MAP(0); +} + +static inline void scc_mgr_set_dqs_out1_delay(alt_u32 write_group, alt_u32 delay) +{ + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQS_IO_OUT1_DELAY(delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].dqs_out_delay1, delay); + +} + +static inline void scc_mgr_set_dqs_out2_delay(alt_u32 write_group, alt_u32 delay) +{ + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + // Load the setting in the SCC manager + WRITE_SCC_DQS_IO_OUT2_DELAY(delay); + + // Make the setting in the TCL report + TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].dqs_out_delay2, delay); + +} + +inline void scc_mgr_set_dm_out1_delay(alt_u32 write_group, alt_u32 dm, alt_u32 delay) +{ + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + ALTERA_ASSERT(dm < RW_MGR_NUM_DM_PER_WRITE_GROUP); + + // Load the setting in the SCC manager + WRITE_SCC_DM_IO_OUT1_DELAY(dm, delay); + + // Make the setting in the TCL report + + if (RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP > 0) + { + TCLRPT_SET(debug_cal_report->cal_dm_settings[curr_shadow_reg][write_group][dm].dm_out_delay1, delay); + } +} + +inline void scc_mgr_set_dm_out2_delay(alt_u32 write_group, alt_u32 dm, alt_u32 delay) +{ + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + ALTERA_ASSERT(dm < RW_MGR_NUM_DM_PER_WRITE_GROUP); + + // Load the setting in the SCC manager + WRITE_SCC_DM_IO_OUT2_DELAY(dm, delay); + + // Make the setting in the TCL report + + if (RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP > 0) + { + TCLRPT_SET(debug_cal_report->cal_dm_settings[curr_shadow_reg][write_group][dm].dm_out_delay2, delay); + } +} + +static inline void scc_mgr_set_dm_in_delay(alt_u32 write_group, alt_u32 dm, alt_u32 delay) +{ + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + ALTERA_ASSERT(dm < RW_MGR_NUM_DM_PER_WRITE_GROUP); + + // Load the setting in the SCC manager + WRITE_SCC_DM_IO_IN_DELAY(dm, delay); + + // Make the setting in the TCL report + + if (RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP > 0) + { + TCLRPT_SET(debug_cal_report->cal_dm_settings[curr_shadow_reg][write_group][dm].dm_in_delay, delay); + } +} + +static inline void scc_mgr_set_dm_bypass(alt_u32 write_group, alt_u32 dm, alt_u32 bypass) +{ + // Load the setting in the SCC manager + WRITE_SCC_DM_BYPASS(dm, bypass); +} + +//USER Zero all DQS config +// TODO: maybe rename to scc_mgr_zero_dqs_config (or something) +void scc_mgr_zero_all (void) +{ + alt_u32 i, r; + + //USER Zero all DQS config settings, across all groups and all shadow registers + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + + // Strictly speaking this should be called once per group to make + // sure each group's delay chain is refreshed from the SCC register file, + // but since we're resetting all delay chains anyway, we can save some + // runtime by calling select_shadow_regs_for_update just once to switch + // rank. + select_shadow_regs_for_update(r, 0, 1); + + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + // The phases actually don't exist on a per-rank basis, but there's + // no harm updating them several times, so let's keep the code simple. + scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE); + scc_mgr_set_dqs_en_phase(i, 0); + scc_mgr_set_dqs_en_delay(i, 0); + } + + for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + scc_mgr_set_dqdqs_output_phase(i, 0); +#if ARRIAV || CYCLONEV + // av/cv don't have out2 + scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE); +#else + scc_mgr_set_oct_out1_delay(i, 0); + scc_mgr_set_oct_out2_delay(i, IO_DQS_OUT_RESERVE); +#endif + } + + //USER multicast to all DQS group enables + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, 0xff); + +#if USE_SHADOW_REGS + //USER in shadow-register mode, SCC_UPDATE is done on a per-group basis + //USER unless we explicitly ask for a multicast via the group counter + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, 0xFF); +#endif + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } +} + +void scc_set_bypass_mode(alt_u32 write_group, alt_u32 mode) +{ + // mode = 0 : Do NOT bypass - Half Rate Mode + // mode = 1 : Bypass - Full Rate Mode + +#if !HHP_HPS + alt_u32 i; +#endif + +#if HHP_HPS + // only need to set once for all groups, pins, dq, dqs, dm + if (write_group == 0) { + DPRINT(1, "Setting HHP Extras"); + scc_mgr_set_hhp_extras(); + DPRINT(1, "Done Setting HHP Extras"); + } +#endif + +#if !HHP_HPS + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) + { + scc_mgr_set_dq_bypass(write_group, i, mode); + scc_mgr_set_rfifo_mode(write_group, i, mode); + } +#endif + + //USER multicast to all DQ enables + IOWR_32DIRECT (SCC_MGR_DQ_ENA, 0, 0xff); + +#if !HHP_HPS + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) + { + scc_mgr_set_dm_bypass(write_group, i, mode); + } +#endif + + IOWR_32DIRECT (SCC_MGR_DM_ENA, 0, 0xff); + +#if !HHP_HPS + scc_mgr_set_dqs_bypass(write_group, mode); +#endif + + //USER update current DQS IO enable + IOWR_32DIRECT (SCC_MGR_DQS_IO_ENA, 0, 0); + + //USER update the DQS logic + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, write_group); + + //USER hit update + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); +} + +// Moving up to avoid warnings +void scc_mgr_load_dqs_for_write_group (alt_u32 write_group) +{ + alt_u32 read_group; + + // Although OCT affects only write data, the OCT delay is controlled by the DQS logic block + // which is instantiated once per read group. For protocols where a write group consists + // of multiple read groups, the setting must be scanned multiple times. + for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; + read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; + ++read_group) { + + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, read_group); + } +} + +void scc_mgr_zero_group (alt_u32 write_group, alt_u32 test_begin, alt_32 out_only) +{ + alt_u32 i, r; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + + select_shadow_regs_for_update(r, write_group, 1); + + //USER Zero all DQ config settings + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) + { + scc_mgr_set_dq_out1_delay(write_group, i, 0); + scc_mgr_set_dq_out2_delay(write_group, i, IO_DQ_OUT_RESERVE); + if (!out_only) { + scc_mgr_set_dq_in_delay(write_group, i, 0); + } + } + + //USER multicast to all DQ enables + IOWR_32DIRECT (SCC_MGR_DQ_ENA, 0, 0xff); + + //USER Zero all DM config settings + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) + { + if (!out_only) { + // Do we really need this? + scc_mgr_set_dm_in_delay(write_group, i, 0); + } + scc_mgr_set_dm_out1_delay(write_group, i, 0); + scc_mgr_set_dm_out2_delay(write_group, i, IO_DM_OUT_RESERVE); + } + + //USER multicast to all DM enables + IOWR_32DIRECT (SCC_MGR_DM_ENA, 0, 0xff); + + //USER zero all DQS io settings + if (!out_only) { + scc_mgr_set_dqs_io_in_delay(write_group, 0); + } +#if ARRIAV || CYCLONEV + // av/cv don't have out2 + scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE); + scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE); + scc_mgr_load_dqs_for_write_group (write_group); +#else + scc_mgr_set_dqs_out1_delay(write_group, 0); + scc_mgr_set_dqs_out2_delay(write_group, IO_DQS_OUT_RESERVE); + scc_mgr_set_oct_out1_delay(write_group, 0); + scc_mgr_set_oct_out2_delay(write_group, IO_DQS_OUT_RESERVE); + scc_mgr_load_dqs_for_write_group (write_group); +#endif + + //USER multicast to all DQS IO enables (only 1) + IOWR_32DIRECT (SCC_MGR_DQS_IO_ENA, 0, 0); + +#if USE_SHADOW_REGS + //USER in shadow-register mode, SCC_UPDATE is done on a per-group basis + //USER unless we explicitly ask for a multicast via the group counter + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, 0xFF); +#endif + //USER hit update to zero everything + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } +} + +//USER load up dqs config settings + +void scc_mgr_load_dqs (alt_u32 dqs) +{ + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, dqs); +} + + +//USER load up dqs io config settings + +void scc_mgr_load_dqs_io (void) +{ + IOWR_32DIRECT (SCC_MGR_DQS_IO_ENA, 0, 0); +} + +//USER load up dq config settings + +void scc_mgr_load_dq (alt_u32 dq_in_group) +{ + IOWR_32DIRECT (SCC_MGR_DQ_ENA, 0, dq_in_group); +} + +//USER load up dm config settings + +void scc_mgr_load_dm (alt_u32 dm) +{ + IOWR_32DIRECT (SCC_MGR_DM_ENA, 0, dm); +} + +//USER apply and load a particular input delay for the DQ pins in a group +//USER group_bgn is the index of the first dq pin (in the write group) + +void scc_mgr_apply_group_dq_in_delay (alt_u32 write_group, alt_u32 group_bgn, alt_u32 delay) +{ + alt_u32 i, p; + + for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { + scc_mgr_set_dq_in_delay(write_group, p, delay); + scc_mgr_load_dq (p); + } +} + +//USER apply and load a particular output delay for the DQ pins in a group + +void scc_mgr_apply_group_dq_out1_delay (alt_u32 write_group, alt_u32 group_bgn, alt_u32 delay1) +{ + alt_u32 i, p; + + for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { + scc_mgr_set_dq_out1_delay(write_group, i, delay1); + scc_mgr_load_dq (i); + } +} + +void scc_mgr_apply_group_dq_out2_delay (alt_u32 write_group, alt_u32 group_bgn, alt_u32 delay2) +{ + alt_u32 i, p; + + for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { + scc_mgr_set_dq_out2_delay(write_group, i, delay2); + scc_mgr_load_dq (i); + } +} + +//USER apply and load a particular output delay for the DM pins in a group + +void scc_mgr_apply_group_dm_out1_delay (alt_u32 write_group, alt_u32 delay1) +{ + alt_u32 i; + + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { + scc_mgr_set_dm_out1_delay(write_group, i, delay1); + scc_mgr_load_dm (i); + } +} + + +//USER apply and load delay on both DQS and OCT out1 +void scc_mgr_apply_group_dqs_io_and_oct_out1 (alt_u32 write_group, alt_u32 delay) +{ + scc_mgr_set_dqs_out1_delay(write_group, delay); + scc_mgr_load_dqs_io (); + + scc_mgr_set_oct_out1_delay(write_group, delay); + scc_mgr_load_dqs_for_write_group (write_group); +} + +//USER apply and load delay on both DQS and OCT out2 +void scc_mgr_apply_group_dqs_io_and_oct_out2 (alt_u32 write_group, alt_u32 delay) +{ + scc_mgr_set_dqs_out2_delay(write_group, delay); + scc_mgr_load_dqs_io (); + + scc_mgr_set_oct_out2_delay(write_group, delay); + scc_mgr_load_dqs_for_write_group (write_group); +} + +//USER set delay on both DQS and OCT out1 by incrementally changing +//USER the settings one dtap at a time towards the target value, to avoid +//USER breaking the lock of the DLL/PLL on the memory device. +void scc_mgr_set_group_dqs_io_and_oct_out1_gradual (alt_u32 write_group, alt_u32 delay) +{ + alt_u32 d = READ_SCC_DQS_IO_OUT1_DELAY(); + + while (d > delay) { + --d; + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + } + while (d < delay) { + ++d; + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + } +} + +//USER set delay on both DQS and OCT out2 by incrementally changing +//USER the settings one dtap at a time towards the target value, to avoid +//USER breaking the lock of the DLL/PLL on the memory device. +void scc_mgr_set_group_dqs_io_and_oct_out2_gradual (alt_u32 write_group, alt_u32 delay) +{ + alt_u32 d = READ_SCC_DQS_IO_OUT2_DELAY(); + + while (d > delay) { + --d; + scc_mgr_apply_group_dqs_io_and_oct_out2 (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + } + while (d < delay) { + ++d; + scc_mgr_apply_group_dqs_io_and_oct_out2 (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + } +} + +//USER apply a delay to the entire output side: DQ, DM, DQS, OCT + +void scc_mgr_apply_group_all_out_delay (alt_u32 write_group, alt_u32 group_bgn, alt_u32 delay) +{ + //USER dq shift + + scc_mgr_apply_group_dq_out1_delay (write_group, group_bgn, delay); + + //USER dm shift + + scc_mgr_apply_group_dm_out1_delay (write_group, delay); + + //USER dqs and oct shift + + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, delay); +} + +//USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks +void scc_mgr_apply_group_all_out_delay_all_ranks (alt_u32 write_group, alt_u32 group_bgn, alt_u32 delay) +{ + alt_u32 r; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + + select_shadow_regs_for_update(r, write_group, 1); + + scc_mgr_apply_group_all_out_delay (write_group, group_bgn, delay); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } +} + +//USER apply a delay to the entire output side: DQ, DM, DQS, OCT + +void scc_mgr_apply_group_all_out_delay_add (alt_u32 write_group, alt_u32 group_bgn, alt_u32 delay) +{ + alt_u32 i, p, new_delay; + + //USER dq shift + + for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { + + new_delay = READ_SCC_DQ_OUT2_DELAY(i); + new_delay += delay; + + if (new_delay > IO_IO_OUT2_DELAY_MAX) { + DPRINT(1, "%s(%lu, %lu, %lu) DQ[%lu,%lu]: %lu > %lu => %lu", + __func__, write_group, group_bgn, delay, i, p, + new_delay, (long unsigned int)IO_IO_OUT2_DELAY_MAX, (long unsigned int)IO_IO_OUT2_DELAY_MAX); + new_delay = IO_IO_OUT2_DELAY_MAX; + } + + scc_mgr_set_dq_out2_delay(write_group, i, new_delay); + scc_mgr_load_dq (i); + } + + //USER dm shift + + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { + new_delay = READ_SCC_DM_IO_OUT2_DELAY(i); + new_delay += delay; + + if (new_delay > IO_IO_OUT2_DELAY_MAX) { + DPRINT(1, "%s(%lu, %lu, %lu) DM[%lu]: %lu > %lu => %lu", + __func__, write_group, group_bgn, delay, i, + new_delay, (long unsigned int)IO_IO_OUT2_DELAY_MAX, (long unsigned int)IO_IO_OUT2_DELAY_MAX); + new_delay = IO_IO_OUT2_DELAY_MAX; + } + + scc_mgr_set_dm_out2_delay(write_group, i, new_delay); + scc_mgr_load_dm (i); + } + + //USER dqs shift + + new_delay = READ_SCC_DQS_IO_OUT2_DELAY(); + new_delay += delay; + + if (new_delay > IO_IO_OUT2_DELAY_MAX) { + DPRINT(1, "%s(%lu, %lu, %lu) DQS: %lu > %d => %d; adding %lu to OUT1", + __func__, write_group, group_bgn, delay, + new_delay, IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX, + new_delay - IO_IO_OUT2_DELAY_MAX); + scc_mgr_set_dqs_out1_delay(write_group, new_delay - IO_IO_OUT2_DELAY_MAX); + new_delay = IO_IO_OUT2_DELAY_MAX; + } + + scc_mgr_set_dqs_out2_delay(write_group, new_delay); + scc_mgr_load_dqs_io (); + + //USER oct shift + + new_delay = READ_SCC_OCT_OUT2_DELAY(write_group); + new_delay += delay; + + if (new_delay > IO_IO_OUT2_DELAY_MAX) { + DPRINT(1, "%s(%lu, %lu, %lu) DQS: %lu > %d => %d; adding %lu to OUT1", + __func__, write_group, group_bgn, delay, + new_delay, IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX, + new_delay - IO_IO_OUT2_DELAY_MAX); + scc_mgr_set_oct_out1_delay(write_group, new_delay - IO_IO_OUT2_DELAY_MAX); + new_delay = IO_IO_OUT2_DELAY_MAX; + } + + scc_mgr_set_oct_out2_delay(write_group, new_delay); + scc_mgr_load_dqs_for_write_group (write_group); +} + +//USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks +void scc_mgr_apply_group_all_out_delay_add_all_ranks (alt_u32 write_group, alt_u32 group_bgn, alt_u32 delay) +{ + alt_u32 r; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + + select_shadow_regs_for_update(r, write_group, 1); + + scc_mgr_apply_group_all_out_delay_add (write_group, group_bgn, delay); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } +} + +static inline void scc_mgr_spread_out2_delay_all_ranks (alt_u32 write_group, alt_u32 test_bgn) +{ +#if STRATIXV || ARRIAVGZ + alt_u32 found; + alt_u32 i; + alt_u32 p; + alt_u32 d; + alt_u32 r; + + const alt_u32 delay_step = IO_IO_OUT2_DELAY_MAX/(RW_MGR_MEM_DQ_PER_WRITE_DQS-1); /* we start at zero, so have one less dq to devide among */ + + TRACE_FUNC("(%lu,%lu)", write_group, test_bgn); + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + select_shadow_regs_for_update(r, write_group, 1); + for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++, d += delay_step) { + DPRINT(1, "rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay: g=%lu r=%lu, i=%lu p=%lu d=%lu", + write_group, r, i, p, d); + scc_mgr_set_dq_out2_delay(write_group, i, d); + scc_mgr_load_dq (i); + } + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } +#endif +} + +#if DDR3 +// optimization used to recover some slots in ddr3 inst_rom +// could be applied to other protocols if we wanted to +void set_jump_as_return(void) +{ + // to save space, we replace return with jump to special shared RETURN instruction + // so we set the counter to large value so that we always jump + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0xFF); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_RETURN); + +} +#endif + +// should always use constants as argument to ensure all computations are performed at compile time +static inline void delay_for_n_mem_clocks(const alt_u32 clocks) +{ + alt_u32 afi_clocks; + alt_u8 inner; + alt_u8 outer; + alt_u16 c_loop; + + TRACE_FUNC("clocks=%lu ... start", clocks); + + afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO; /* scale (rounding up) to get afi clocks */ + + // Note, we don't bother accounting for being off a little bit because of a few extra instructions in outer loops + // Note, the loops have a test at the end, and do the test before the decrement, and so always perform the loop + // 1 time more than the counter value + if (afi_clocks == 0) { + inner = outer = c_loop = 0; + } else if (afi_clocks <= 0x100) { + inner = afi_clocks-1; + outer = 0; + c_loop = 0; + } else if (afi_clocks <= 0x10000) { + inner = 0xff; + outer = (afi_clocks-1) >> 8; + c_loop = 0; + } else { + inner = 0xff; + outer = 0xff; + c_loop = (afi_clocks-1) >> 16; + } + + // rom instructions are structured as follows: + // + // IDLE_LOOP2: jnz cntr0, TARGET_A + // IDLE_LOOP1: jnz cntr1, TARGET_B + // return + // + // so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and TARGET_B is + // set to IDLE_LOOP2 as well + // + // if we have no outer loop, though, then we can use IDLE_LOOP1 only, and set + // TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely + // + // a little confusing, but it helps save precious space in the inst_rom and sequencer rom + // and keeps the delays more accurate and reduces overhead + if (afi_clocks <= 0x100) { + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner)); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP1); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP1); + + } else { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer)); + + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_IDLE_LOOP2); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP2); + + // hack to get around compiler not being smart enough + if (afi_clocks <= 0x10000) { + // only need to run once + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2); + } else { + do { + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2); + } while (c_loop-- != 0); + } + } + + TRACE_FUNC("clocks=%lu ... end", clocks); +} + +// should always use constants as argument to ensure all computations are performed at compile time +static inline void delay_for_n_ns(const alt_u32 nanoseconds) +{ + TRACE_FUNC("nanoseconds=%lu ... end", nanoseconds); + delay_for_n_mem_clocks((1000*nanoseconds) / (1000000/AFI_CLK_FREQ) * AFI_RATE_RATIO); +} + +#if RLDRAM3 +// Special routine to recover memory device from illegal state after +// ck/dk relationship is potentially violated. +static inline void recover_mem_device_after_ck_dqs_violation(void) +{ + //USER Issue MRS0 command. For some reason this is required once we + //USER violate tCKDK. Without this all subsequent write tests will fail + //USER even with known good delays. + + //USER Load MR0 + if ( RW_MGR_MEM_NUMBER_OF_RANKS == 1 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 2 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFC); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 4 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFC); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + //USER Wait MRSC + delay_for_n_mem_clocks(12); + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xF3); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_QUAD_RANK); + } + else { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + } + + //USER Wait MRSC + delay_for_n_mem_clocks(12); +} +#else +// Special routine to recover memory device from illegal state after +// ck/dqs relationship is violated. +static inline void recover_mem_device_after_ck_dqs_violation(void) +{ + // Current protocol doesn't require any special recovery +} +#endif + +#if (LRDIMM && DDR3) +// Routine to program specific LRDIMM control words. +static void rw_mgr_lrdimm_rc_program(alt_u32 fscw, alt_u32 rc_addr, alt_u32 rc_val) +{ + alt_u32 i; + const alt_u32 AC_BASE_CONTENT = __RW_MGR_CONTENT_ac_rdimm; + //USER These values should be dynamically loaded instead of hard-coded + const alt_u32 AC_ADDRESS_POSITION = 0x0; + const alt_u32 AC_BANK_ADDRESS_POSITION = 0xD; + alt_u32 ac_content; + alt_u32 lrdimm_cs_msk = RW_MGR_RANK_NONE; + + TRACE_FUNC(); + + //USER Turn on only CS0 and CS1 for each DIMM. + for (i = 0; i < RW_MGR_MEM_CHIP_SELECT_WIDTH; i+= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM) + { + lrdimm_cs_msk &= (~(3 << i)); + } + + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, lrdimm_cs_msk); + + // Program the fscw first (RC7), followed by the actual value + for (i = 0; i < 2; i++) + { + alt_u32 addr; + alt_u32 val; + + addr = (i == 0) ? 7 : rc_addr; + val = (i == 0) ? fscw : rc_val; + + ac_content = + AC_BASE_CONTENT | + //USER Word address + ((addr & 0x7) << AC_ADDRESS_POSITION) | + (((addr >> 3) & 0x1) << (AC_BANK_ADDRESS_POSITION + 2)) | + //USER Configuration Word + (((val >> 2) & 0x3) << (AC_BANK_ADDRESS_POSITION)) | + ((val & 0x3) << (AC_ADDRESS_POSITION + 3)); + + //USER Override the AC row with the RDIMM command + IOWR_32DIRECT(BASE_RW_MGR, 0x1C00 + (__RW_MGR_ac_rdimm << 2), ac_content); + + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_RDIMM_CMD); + } + + // USER The following registers require a delay of tSTAB (6us) for proper functionality. + // USER F0RC2, F0RC10, F0RC11, F1RC8, F1RC11-F1RC15 + // USER Note that it is only necessary to wait tSTAB after all of these + // USER control words have been written, not after each one. Only F0RC0-F0RC15 + // USER are guaranteed to be written (and in order), but F1* are not so + // USER wait after each. + if ( ((fscw == 0) && ((rc_addr==2) || (rc_addr==10) || (rc_addr==11))) + || ((fscw == 1) && (rc_addr >= 8))) + { + delay_for_n_ns(6000); + } +} +#endif +#if (RDIMM || LRDIMM) && DDR3 +void rw_mgr_rdimm_initialize(void) +{ + alt_u32 i; + alt_u32 conf_word; +#if RDIMM + const alt_u32 AC_BASE_CONTENT = __RW_MGR_CONTENT_ac_rdimm; + //USER These values should be dynamically loaded instead of hard-coded + const alt_u32 AC_ADDRESS_POSITION = 0x0; + const alt_u32 AC_BANK_ADDRESS_POSITION = 0xD; + alt_u32 ac_content; +#endif + + TRACE_FUNC(); + + //USER RDIMM registers are programmed by writing 16 configuration words + //USER 1. An RDIMM command is a NOP with all CS asserted + //USER 2. The 4-bit address of the configuration words is + //USER * { mem_ba[2] , mem_a[2] , mem_a[1] , mem_a[0] } + //USER 3. The 4-bit configuration word is + //USER * { mem_ba[1] , mem_ba[0] , mem_a[4] , mem_a[3] } + +#if RDIMM + //USER Turn on all ranks + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, RW_MGR_RANK_ALL); +#endif + + for(i = 0; i < 16; i++) + { + + + if(i < 8) + { +#if ENABLE_TCL_DEBUG && USE_USER_RDIMM_VALUE + conf_word = (my_debug_data.command_parameters[0] >> (i * 4)) & 0xF; +#else + conf_word = (RDIMM_CONFIG_WORD_LOW >> (i * 4)) & 0xF; +#endif + } + else + { +#if ENABLE_TCL_DEBUG && USE_USER_RDIMM_VALUE + conf_word = (my_debug_data.command_parameters[1] >> ((i - 8) * 4)) & 0xF; +#else + conf_word = (RDIMM_CONFIG_WORD_HIGH >> ((i - 8) * 4)) & 0xF; +#endif + } + +#if RDIMM + ac_content = + AC_BASE_CONTENT | + //USER Word address + ((i & 0x7) << AC_ADDRESS_POSITION) | + (((i >> 3) & 0x1) << (AC_BANK_ADDRESS_POSITION + 2)) | + //USER Configuration Word + (((conf_word >> 2) & 0x3) << (AC_BANK_ADDRESS_POSITION)) | + ((conf_word & 0x3) << (AC_ADDRESS_POSITION + 3)); + + //USER Override the AC row with the RDIMM command + IOWR_32DIRECT(BASE_RW_MGR, 0x1C00 + (__RW_MGR_ac_rdimm << 2), ac_content); + + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_RDIMM_CMD); + //USER When sending the RC2 or RC10 word, tSTAB time must elapse before the next command + //USER is sent out. tSTAB is currently hard-coded to 6us. + if((i == 2) || (i == 10)) + { + //USER tSTAB = 6 us + delay_for_n_ns(6000); + } + +#endif +#if LRDIMM + // USER Program configuration word with FSCW set to zero. + rw_mgr_lrdimm_rc_program(0, i, conf_word); +#endif + } +} +#else +void rw_mgr_rdimm_initialize(void) { } +#endif + +#if DDR3 + +#if (ADVANCED_ODT_CONTROL || LRDIMM) +alt_u32 ddr3_mirror_mrs_cmd(alt_u32 bit_vector) { + // This function performs address mirroring of an AC ROM command, which + // requires swapping the following DDR3 bits: + // A[3] <=> A[4] + // A[5] <=> A[6] + // A[7] <=> A[8] + // BA[0] <=>BA[1] + // We assume AC_ROM_ENTRY = {BA[2:0], A[15:0]}. + alt_u32 unchanged_bits; + alt_u32 mask_a; + alt_u32 mask_b; + alt_u32 retval; + + unchanged_bits = (~(DDR3_AC_MIRR_MASK | (DDR3_AC_MIRR_MASK << 1))) & bit_vector; + mask_a = DDR3_AC_MIRR_MASK & bit_vector; + mask_b = (DDR3_AC_MIRR_MASK << 1) & bit_vector; + + retval = unchanged_bits | (mask_a << 1) | (mask_b >> 1); + + return retval; +} + +void rtt_change_MRS1_MRS2_NOM_WR (alt_u32 prev_ac_mr , alt_u32 odt_ac_mr, alt_u32 mirr_on, alt_u32 mr_cmd ) { + // This function updates the ODT-specific Mode Register bits (MRS1 or MRS2) in the AC ROM. + // Parameters: prev_ac_mr - Original, *un-mirrored* AC ROM Entry + // odt_ac_mr - ODT bits to update (un-mirrored) + // mirr_on - boolean flag indicating if the regular or mirrored entry is updated + // mr_cmd - Mode register command (only MR1 and MR2 are supported for DDR3) + alt_u32 new_ac_mr; + alt_u32 ac_rom_entry = 0; + alt_u32 ac_rom_mask; + + switch (mr_cmd) { + case 1: { + // USER MRS1 = RTT_NOM, RTT_DRV + ac_rom_mask = DDR3_MR1_ODT_MASK; + ac_rom_entry = mirr_on ? (0x1C00 | (__RW_MGR_ac_mrs1_mirr << 2)) + : (0x1C00 | (__RW_MGR_ac_mrs1 << 2)); + } break; + case 2: { + // USER MRS2 = RTT_WR + ac_rom_mask = DDR3_MR2_ODT_MASK; + ac_rom_entry = mirr_on ? (0x1C00 | (__RW_MGR_ac_mrs2_mirr << 2)) + : (0x1C00 | (__RW_MGR_ac_mrs2 << 2)); + } break; + } + + // USER calculate new AC values and update ROM + new_ac_mr = odt_ac_mr; + new_ac_mr |= (prev_ac_mr & ac_rom_mask); + if (mirr_on) { + new_ac_mr = ddr3_mirror_mrs_cmd(new_ac_mr); + } + IOWR_32DIRECT(BASE_RW_MGR, ac_rom_entry, new_ac_mr); +} +#endif //(ADVANCED_ODT_CONTROL || LRDIMM) + +void rw_mgr_mem_initialize (void) +{ + alt_u32 r; + +#if LRDIMM + alt_u32 rtt_nom; + alt_u32 rtt_drv; + alt_u32 rtt_wr; +#endif // LRDIMM + + TRACE_FUNC(); + + //USER The reset / cke part of initialization is broadcasted to all ranks + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, RW_MGR_RANK_ALL); + + // Here's how you load register for a loop + //USER Counters are located @ 0x800 + //USER Jump address are located @ 0xC00 + //USER For both, registers 0 to 3 are selected using bits 3 and 2, like in + //USER 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C + // I know this ain't pretty, but Avalon bus throws away the 2 least significant bits + + //USER start with memory RESET activated + + //USER tINIT is typically 200us (but can be adjusted in the GUI) + //USER The total number of cycles required for this nested counter structure to + //USER complete is defined by: + //USER num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1 + + //USER Load counters + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL)); + + //USER Load jump address + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_0_CKE_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_0_CKE_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_RESET_0_CKE_0); + + //USER Execute count instruction + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_0_CKE_0); + + //USER indicate that memory is stable + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); + + //USER transition the RESET to high + //USER Wait for 500us + //USER num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1 + //USER Load counters + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL)); + + //USER Load jump address + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_1_CKE_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_1_CKE_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_RESET_1_CKE_0); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_1_CKE_0); + + //USER bring up clock enable + + //USER tXRP < 250 ck cycles + delay_for_n_mem_clocks(250); + +#ifdef RDIMM + // USER initialize RDIMM buffer so MRS and RZQ Calibrate commands will be + // USER propagated to discrete memory devices + rw_mgr_rdimm_initialize(); +#endif + +#if LRDIMM + // USER initialize LRDIMM MB so MRS and RZQ Calibrate commands will be + // USER propagated to all sub-ranks. Per LRDIMM spec, all LRDIMM ranks must have + // USER RTT_WR set, but only physical ranks 0 and 1 should have RTT_NOM set. + // USER Therefore RTT_NOM=0 is broadcast to all ranks, and the non-zero value is + // USER programmed directly into Ranks 0 and 1 using physical MRS targetting. + rw_mgr_rdimm_initialize(); + + rtt_nom = LRDIMM_SPD_MR_RTT_NOM(LRDIMM_SPD_MR); + rtt_drv = LRDIMM_SPD_MR_RTT_DRV(LRDIMM_SPD_MR); + rtt_wr = LRDIMM_SPD_MR_RTT_WR(LRDIMM_SPD_MR); + + // USER Configure LRDIMM to broadcast LRDIMM MRS commands to all ranks + rw_mgr_lrdimm_rc_program(0, 14, (((RDIMM_CONFIG_WORD_HIGH >> 24) & 0xF) & (~0x4))); + + // USER Update contents of AC ROM with new RTT WR, DRV values only (NOM = Off) + rtt_change_MRS1_MRS2_NOM_WR(__RW_MGR_CONTENT_ac_mrs1, rtt_drv, 0, 1); + rtt_change_MRS1_MRS2_NOM_WR(__RW_MGR_CONTENT_ac_mrs1, rtt_drv, 1, 1); + rtt_change_MRS1_MRS2_NOM_WR(__RW_MGR_CONTENT_ac_mrs2, rtt_wr, 0, 2); + rtt_change_MRS1_MRS2_NOM_WR(__RW_MGR_CONTENT_ac_mrs2, rtt_wr, 1, 2); +#endif +#if RDIMM + // USER initialize RDIMM buffer so MRS and RZQ Calibrate commands will be + // USER propagated to discrete memory devices + rw_mgr_rdimm_initialize(); +#endif + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + +#if ADVANCED_ODT_CONTROL + alt_u32 rtt_nom = 0; + alt_u32 rtt_wr = 0; + alt_u32 rtt_drv = 0; + + switch (r) { + case 0: { + rtt_nom = MR1_RTT_RANK0; + rtt_wr = MR2_RTT_WR_RANK0; + rtt_drv = MR1_RTT_DRV_RANK0; + } break; + case 1: { + rtt_nom = MR1_RTT_RANK1; + rtt_wr = MR2_RTT_WR_RANK1; + rtt_drv = MR1_RTT_DRV_RANK1; + } break; + case 2: { + rtt_nom = MR1_RTT_RANK2; + rtt_wr = MR2_RTT_WR_RANK2; + rtt_drv = MR1_RTT_DRV_RANK2; + } break; + case 3: { + rtt_nom = MR1_RTT_RANK3; + rtt_wr = MR2_RTT_WR_RANK3; + rtt_drv = MR1_RTT_DRV_RANK3; + } break; + } + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs1, (rtt_nom|rtt_drv), + ((RW_MGR_MEM_ADDRESS_MIRRORING>>r)&0x1), 1); + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs2, rtt_wr, + ((RW_MGR_MEM_ADDRESS_MIRRORING>>r)&0x1), 2); +#endif //ADVANCED_ODT_CONTROL + + //USER set rank +#if MRS_MIRROR_PING_PONG_ATSO + // Special case + // SIDE 0 + set_rank_and_odt_mask_for_ping_pong_atso(0, RW_MGR_ODT_MODE_OFF); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET); + + // SIDE 1 + set_rank_and_odt_mask_for_ping_pong_atso(1, RW_MGR_ODT_MODE_OFF); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET_MIRR); + + // Unmask all CS + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); +#else + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER Use Mirror-ed commands for odd ranks if address mirrorring is on + if((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) { + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET_MIRR); + } else { + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET); + } +#endif + + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ZQCL); + + //USER tZQinit = tDLLK = 512 ck cycles + delay_for_n_mem_clocks(512); + } +#if LRDIMM + // USER Configure LRDIMM to target physical ranks decoded by RM bits only (ranks 0,1 only) + // USER Set bit F0RC14.DBA0 to '1' so MRS commands target physical ranks only + rw_mgr_lrdimm_rc_program(0, 14, (((RDIMM_CONFIG_WORD_HIGH >> 24) & 0xF) | 0x4)); + // USER update AC ROM MR1 entry to include RTT_NOM + rtt_change_MRS1_MRS2_NOM_WR(__RW_MGR_CONTENT_ac_mrs1, (rtt_drv|rtt_nom), 0, 1); + rtt_change_MRS1_MRS2_NOM_WR(__RW_MGR_CONTENT_ac_mrs1, (rtt_drv|rtt_nom), 1, 1); + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER Use Mirror-ed commands for odd ranks if address mirrorring is on + if((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) { + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR); + delay_for_n_mem_clocks(4); + } else { + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + delay_for_n_mem_clocks(4); + } + } + + // USER Initiate LRDIMM MB->Physical Rank training here + // USER -> Set minimum skew mode for levelling - F3RC6 = 0001 + rw_mgr_lrdimm_rc_program(3, 6, 0x1); + // USER -> Set error status output in register F2RC3 for debugging purposes + rw_mgr_lrdimm_rc_program(2, 3, 0x8); + +#ifdef LRDIMM_EXT_CONFIG_ARRAY + // USER Configure LRDIMM ODT/Drive parameters using SPD information + { + static const alt_u8 lrdimm_cfg_array[][3] = LRDIMM_EXT_CONFIG_ARRAY; + alt_u32 cfg_reg_ctr; + + for (cfg_reg_ctr = 0; cfg_reg_ctr < (sizeof(lrdimm_cfg_array)/sizeof(lrdimm_cfg_array[0])); cfg_reg_ctr++) + { + alt_u32 lrdimm_fp = (alt_u32)lrdimm_cfg_array[cfg_reg_ctr][0]; + alt_u32 lrdimm_rc = (alt_u32)lrdimm_cfg_array[cfg_reg_ctr][1]; + alt_u32 lrdimm_val = (alt_u32)lrdimm_cfg_array[cfg_reg_ctr][2]; + + rw_mgr_lrdimm_rc_program(lrdimm_fp, lrdimm_rc, lrdimm_val); + } + } +#endif // LRDIMM_EXT_CONFIG_ARRAY + + // USER -> Initiate MB->DIMM training on the LRDIMM + rw_mgr_lrdimm_rc_program(0, 12, 0x2); +#if (!STATIC_SKIP_DELAY_LOOPS) + // USER Wait for max(tcal) * number of physical ranks. Tcal is approx. 10ms. + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS * RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM; r++) + { + delay_for_n_ns(80000000UL); + } +#endif // !STATIC_SKIP_DELAY_LOOPS + // USER Place MB back in normal operating mode + rw_mgr_lrdimm_rc_program(0, 12, 0x0); +#endif // LRDIMM +} + + +#if (ENABLE_NON_DESTRUCTIVE_CALIB || ENABLE_NON_DES_CAL) +void rw_mgr_mem_initialize_no_init (void) +{ + alt_u32 r; + alt_u32 mem_refresh_all_ranks(alt_u32 no_validate); + TRACE_FUNC(); + rw_mgr_rdimm_initialize(); + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, RW_MGR_RANK_ALL); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_RETURN); + delay_for_n_mem_clocks(512); + mem_refresh_all_ranks(1); + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + continue; + } + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + set_jump_as_return(); + if((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) { + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET_MIRR); + } else { + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET); + } + +// Reprogramming these is not really required but.... + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + + + + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ZQCL); + delay_for_n_mem_clocks(512); + } + + IOWR_32DIRECT (RW_MGR_ENABLE_REFRESH, 0, 1); // Enable refresh engine + +} +#endif +#endif // DDR3 + +#if DDR2 +void rw_mgr_mem_initialize (void) +{ + alt_u32 r; + + TRACE_FUNC(); + + //USER *** NOTE *** + //USER The following STAGE (n) notation refers to the corresponding stage in the Micron datasheet + + // Here's how you load register for a loop + //USER Counters are located @ 0x800 + //USER Jump address are located @ 0xC00 + //USER For both, registers 0 to 3 are selected using bits 3 and 2, like in + //USER 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C + // I know this ain't pretty, but Avalon bus throws away the 2 least significant bits + + //USER *** STAGE (1, 2, 3) *** + + //USER start with CKE low + + //USER tINIT is typically 200us (but can be adjusted in the GUI) + //USER The total number of cycles required for this nested counter structure to + //USER complete is defined by: + //USER num_cycles = (CTR0 + 1) * [(CTR1 + 1) * (2 * (CTR2 + 1) + 1) + 1] + 1 + + //TODO: Need to manage multi-rank + + //USER Load counters + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL)); + + //USER Load jump address + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_CKE_0); + + //USER Execute count instruction + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0); + + //USER indicate that memory is stable + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); + + //USER Bring up CKE + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_NOP); + + //USER *** STAGE (4) + + //USER Wait for 400ns + delay_for_n_ns(400); + + //USER Multi-rank section begins here + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER * **** * + //USER * NOTE * + //USER * **** * + //USER The following commands must be spaced by tMRD or tRPA which are in the order + //USER of 2 to 4 full rate cycles. This is peanuts in the NIOS domain, so for now + //USER we can avoid redundant wait loops + + // Possible FIXME BEN: for HHP, we need to add delay loops to be sure + // although, the sequencer write interface by itself likely has enough delay + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + //USER *** STAGE (5) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR2); + + //USER *** STAGE (6) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR3); + + //USER *** STAGE (7) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR); + + //USER *** STAGE (8) + //USER DLL reset + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_DLL_RESET); + + //USER *** STAGE (9) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + //USER *** STAGE (10) + + //USER Issue 2 refresh commands spaced by tREF + + //USER First REFRESH + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH); + + //USER tREF = 200ns + delay_for_n_ns(200); + + //USER Second REFRESH + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH); + + //USER Second idle loop + delay_for_n_ns(200); + + //USER *** STAGE (11) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_CALIB); + + //USER *** STAGE (12) + //USER OCD defaults + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR_OCD_ENABLE); + + //USER *** STAGE (13) + //USER OCD exit + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR); + + //USER *** STAGE (14) + + //USER The memory is now initialized. Before being able to use it, we must still + //USER wait for the DLL to lock, 200 clock cycles after it was reset @ STAGE (8). + //USER Since we cannot keep track of time in any other way, let's start counting from now + delay_for_n_mem_clocks(200); + } +} +#endif // DDR2 + +#if LPDDR2 +void rw_mgr_mem_initialize (void) +{ + alt_u32 r; + + //USER *** NOTE *** + //USER The following STAGE (n) notation refers to the corresponding stage in the Micron datasheet + + // Here's how you load register for a loop + //USER Counters are located @ 0x800 + //USER Jump address are located @ 0xC00 + //USER For both, registers 0 to 3 are selected using bits 3 and 2, like in + //USER 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C + // I know this ain't pretty, but Avalon bus throws away the 2 least significant bits + + //USER *** STAGE (1, 2, 3) *** + + //USER start with CKE low + + //USER tINIT1 = 100ns + + //USER 100ns @ 300MHz (3.333 ns) ~ 30 cycles + //USER If a is the number of iteration in a loop + //USER it takes the following number of cycles to complete the operation: + //USER number_of_cycles = (2 + n) * a + //USER where n is the number of instruction in the inner loop + //USER One possible solution is n = 0 , a = 15 => a = 0x10 + + //USER Load counter + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x10)); + + //USER Load jump address + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0); + + //USER Execute count instruction + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0); + + //USER tINIT3 = 200us + delay_for_n_ns(200000); + + //USER indicate that memory is stable + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); + + //USER Multi-rank section begins here + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER MRW RESET + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR63_RESET); + } + + //USER tINIT5 = 10us + delay_for_n_ns(10000); + + //USER Multi-rank section begins here + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER MRW ZQC + // Note: We cannot calibrate other ranks when the current rank is calibrating for tZQINIT + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR10_ZQC); + + //USER tZQINIT = 1us + delay_for_n_ns(1000); + + //USER * **** * + //USER * NOTE * + //USER * **** * + //USER The following commands must be spaced by tMRW which is in the order + //USER of 3 to 5 full rate cycles. This is peanuts in the NIOS domain, so for now + //USER we can avoid redundant wait loops + + //USER MRW MR1 + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR1_CALIB); + + //USER MRW MR2 + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR2); + + //USER MRW MR3 + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR3); + } +} +#endif // LPDDR2 + +#if LPDDR1 +void rw_mgr_mem_initialize (void) +{ + alt_u32 r; + + TRACE_FUNC(); + + //USER *** NOTE *** + //USER The following STAGE (n) notation refers to the corresponding stage in the Micron datasheet + + // Here's how you load register for a loop + //USER Counters are located @ 0x800 + //USER Jump address are located @ 0xC00 + //USER For both, registers 0 to 3 are selected using bits 3 and 2, like in + //USER 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C + // I know this ain't pretty, but Avalon bus throws away the 2 least significant bits + + //USER *** STAGE (1, 2, 3) *** + + //USER start with CKE high + + //USER tINIT = 200us + + //USER 200us @ 300MHz (3.33 ns) ~ 60000 clock cycles + //USER If a and b are the number of iteration in 2 nested loops + //USER it takes the following number of cycles to complete the operation: + //USER number_of_cycles = ((2 + n) * b + 2) * a + //USER where n is the number of instruction in the inner loop + //USER One possible solution is n = 0 , a = 256 , b = 118 => a = FF, b = 76 + + //TODO: Need to manage multi-rank + + //USER Load counters + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x76)); + + //USER Load jump address + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_1); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_1_inloop); + + //USER Execute count instruction and bring up CKE + //USER IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_1); + + //USER indicate that memory is stable + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); + + //USER Multi-rank section begins here + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER * **** * + //USER * NOTE * + //USER * **** * + //USER The following commands must be spaced by tMRD or tRPA which are in the order + //USER of 2 to 4 full rate cycles. This is peanuts in the NIOS domain, so for now + //USER we can avoid redundant wait loops + + // Possible FIXME BEN: for HHP, we need to add delay loops to be sure + // although, the sequencer write interface by itself likely has enough delay + + //USER *** STAGE (9) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + //USER *** STAGE (10) + + //USER Issue 2 refresh commands spaced by tREF + + //USER First REFRESH + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH); + + //USER tREF = 200ns + delay_for_n_ns(200); + + //USER Second REFRESH + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH); + + //USER Second idle loop + delay_for_n_ns(200); + + //USER *** STAGE (11) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_CALIB); + + //USER *** STAGE (13) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR); + + } +} +#endif // LPDDR1 + +#if QDRII +void rw_mgr_mem_initialize (void) +{ + TRACE_FUNC(); + + //USER Turn off QDRII DLL to reset it + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE); + + //USER Turn on QDRII DLL and wait 25us for it to lock + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_NOP); + delay_for_n_ns(25000); + + //USER indicate that memory is stable + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); +} +#endif + +#if QDRII +void rw_mgr_mem_dll_lock_wait (void) +{ + //USER The DLL in QDR requires 25us to lock + delay_for_n_ns(25000); +} +#else +void rw_mgr_mem_dll_lock_wait (void) { } +#endif + +#if RLDRAMII +void rw_mgr_mem_initialize (void) +{ + TRACE_FUNC(); + + //USER start with memory RESET activated + + //USER tINIT = 200us + delay_for_n_ns(200000); + + //USER indicate that memory is stable + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); + + //USER Dummy MRS, followed by valid MRS commands to reset the DLL on memory device + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS_INIT); + + //USER 8192 memory cycles for DLL to lock. + // 8192 cycles are required by Renesas LLDRAM-II, though we don't officially support it + delay_for_n_mem_clocks(8192); + + //USER Refresh all banks + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REF_X8); + + //USER 1024 memory cycles + delay_for_n_mem_clocks(1024); +} +#endif + +#if RLDRAM3 +void rw_mgr_mem_initialize (void) +{ + TRACE_FUNC(); + alt_u32 r; + + // Here's how you load register for a loop + //USER Counters are located @ 0x800 + //USER Jump address are located @ 0xC00 + //USER For both, registers 0 to 3 are selected using bits 3 and 2, like in + //USER 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C + // I know this ain't pretty, but Avalon bus throws away the 2 least significant bits + + //USER start with memory RESET activated + + //USER tINIT = 200us + + //USER 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles + //USER If a and b are the number of iteration in 2 nested loops + //USER it takes the following number of cycles to complete the operation: + //USER number_of_cycles = ((2 + n) * a + 2) * b + //USER where n is the number of instruction in the inner loop + //USER One possible solution is n = 0 , a = 256 , b = 106 => a = FF, b = 6A + + //USER Load counters + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF)); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x6A)); + + //USER Load jump address + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_0_inloop); + + //USER Execute count instruction + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_0); + + //USER indicate that memory is stable + IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1); + + //USER transition the RESET to high + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_NOP); + + //USER Wait for 10000 cycles + delay_for_n_mem_clocks(10000); + + //USER Load MR0 + if ( RW_MGR_MEM_NUMBER_OF_RANKS == 1 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 2 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFC); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 4 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFC); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + //USER Wait MRSC + delay_for_n_mem_clocks(12); + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xF3); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_QUAD_RANK); + } + else { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0); + } + + + //USER Wait MRSC + delay_for_n_mem_clocks(12); + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + continue; + } + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + //USER Load MR1 (reset DLL reset and kick off long ZQ calibration) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_CALIB); + + //USER Wait 512 cycles for DLL to reset and for ZQ calibration to complete + delay_for_n_mem_clocks(512); + } + + //USER Load MR2 (set write protocol to Single Bank) + if ( RW_MGR_MEM_NUMBER_OF_RANKS == 1 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 2 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFC); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 4 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xF0); + } + else { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + } + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2_CALIB); + + //USER Wait MRSC and a bit more + delay_for_n_mem_clocks(64); +} +#endif + +//USER At the end of calibration we have to program the user settings in, and +//USER hand off the memory to the user. + +#if DDR3 +void rw_mgr_mem_handoff (void) +{ + alt_u32 r; +#if LRDIMM + alt_u32 rtt_nom; + alt_u32 rtt_drv; + alt_u32 rtt_wr; +#endif // LRDIMM + + TRACE_FUNC(); + +#if LRDIMM + rtt_nom = LRDIMM_SPD_MR_RTT_NOM(LRDIMM_SPD_MR); + rtt_drv = LRDIMM_SPD_MR_RTT_DRV(LRDIMM_SPD_MR); + rtt_wr = LRDIMM_SPD_MR_RTT_WR(LRDIMM_SPD_MR); + + // USER Configure LRDIMM to broadcast LRDIMM MRS commands to all ranks + // USER Set bit F0RC14.DBA0 to '0' so MRS commands target all physical ranks in a logical rank + rw_mgr_lrdimm_rc_program(0, 14, (((RDIMM_CONFIG_WORD_HIGH >> 24) & 0xF) & (~0x4))); + + // USER Update contents of AC ROM with new RTT WR, DRV values + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs1, rtt_drv, 0, 1); + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs1, rtt_drv, 1, 1); + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs2, rtt_wr, 0, 2); + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs2, rtt_wr, 1, 2); +#endif // LRDIMM + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + +#if MRS_MIRROR_PING_PONG_ATSO + // Side 0 + set_rank_and_odt_mask_for_ping_pong_atso(0, RW_MGR_ODT_MODE_OFF); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER); + + // Side 1 + set_rank_and_odt_mask_for_ping_pong_atso(1, RW_MGR_ODT_MODE_OFF); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER_MIRR); + + // Unmask all CS + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); +#else + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER precharge all banks ... + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + //USER load up MR settings specified by user + + //USER Use Mirror-ed commands for odd ranks if address mirrorring is on + if((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) { + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER_MIRR); + } else { + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER); + } +#endif + //USER need to wait tMOD (12CK or 15ns) time before issuing other commands, + //USER but we will have plenty of NIOS cycles before actual handoff so its okay. + } + + +#if LRDIMM + delay_for_n_mem_clocks(12); + // USER Set up targetted MRS commands + rw_mgr_lrdimm_rc_program(0, 14, (((RDIMM_CONFIG_WORD_HIGH >> 24) & 0xF) | 0x4)); + // USER update AC ROM MR1 entry to include RTT_NOM for physical ranks 0,1 only + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs1, (rtt_drv|rtt_nom), 0, 1); + rtt_change_MRS1_MRS2_NOM_WR (__RW_MGR_CONTENT_ac_mrs1, (rtt_drv|rtt_nom), 1, 1); + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER Use Mirror-ed commands for odd ranks if address mirrorring is on + if((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) { + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR); + delay_for_n_mem_clocks(4); + } else { + delay_for_n_mem_clocks(4); + set_jump_as_return(); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + delay_for_n_mem_clocks(4); + } + } +#endif // LRDIMM +} +#endif // DDR3 + +#if DDR2 +void rw_mgr_mem_handoff (void) +{ + alt_u32 r; + + TRACE_FUNC(); + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER precharge all banks ... + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + //USER load up MR settings specified by user + + // FIXME BEN: for HHP, we need to add delay loops to be sure + // We can check this with BFM perhaps + // Likely enough delay in RW_MGR though + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR2); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR3); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_USER); + + //USER need to wait tMOD (12CK or 15ns) time before issuing other commands, + //USER but we will have plenty of NIOS cycles before actual handoff so its okay. + } +} +#endif //USER DDR2 + +#if LPDDR2 +void rw_mgr_mem_handoff (void) +{ + alt_u32 r; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER precharge all banks... + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + //USER load up MR settings specified by user + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR1_USER); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR2); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR3); + } +} +#endif //USER LPDDR2 + +#if LPDDR1 +void rw_mgr_mem_handoff (void) +{ + alt_u32 r; + + TRACE_FUNC(); + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER precharge all banks ... + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + //USER load up MR settings specified by user + + // FIXME BEN: for HHP, we need to add delay loops to be sure + // We can check this with BFM perhaps + // Likely enough delay in RW_MGR though + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_USER); + + //USER need to wait tMOD (12CK or 15ns) time before issuing other commands, + //USER but we will have plenty of NIOS cycles before actual handoff so its okay. + } +} +#endif //USER LPDDR1 + +#if RLDRAMII +void rw_mgr_mem_handoff (void) +{ + TRACE_FUNC(); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS); +} +#endif + +#if RLDRAM3 +void rw_mgr_mem_handoff (void) +{ + TRACE_FUNC(); + alt_u32 r; + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + continue; + } + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER Load user requested MR1 + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1); + } + + if ( RW_MGR_MEM_NUMBER_OF_RANKS == 1 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 2 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFC); + } else if ( RW_MGR_MEM_NUMBER_OF_RANKS == 4 ) { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xF0); + } + else { + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, 0xFE); + } + //USER Load user requested MR2 + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2); + + //USER Wait MRSC and a bit more + delay_for_n_mem_clocks(64); +} +#endif + +#if QDRII +void rw_mgr_mem_handoff (void) +{ + TRACE_FUNC(); +} +#endif + +#if DDRX +//USER performs a guaranteed read on the patterns we are going to use during a read test to ensure memory works +alt_u32 rw_mgr_mem_calibrate_read_test_patterns (alt_u32 rank_bgn, alt_u32 group, alt_u32 num_tries, t_btfld *bit_chk, alt_u32 all_ranks) +{ + alt_u32 r, vg; + t_btfld correct_mask_vg; + t_btfld tmp_bit_chk; + alt_u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); + + *bit_chk = param->read_correct_mask; + correct_mask_vg = param->read_correct_mask_vg; + + for (r = rank_bgn; r < rank_end; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + + //USER Load up a constant bursts of read commands + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_READ); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_READ_CONT); + + tmp_bit_chk = 0; + for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) + { + //USER reset the fifos to get pointers to known state + + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + + tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, ((group*RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS+vg) << 2), __RW_MGR_GUARANTEED_READ); + tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0))); + + if (vg == 0) { + break; + } + } + *bit_chk &= tmp_bit_chk; + } + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group << 2), __RW_MGR_CLEAR_DQS_ENABLE); + + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + DPRINT(2, "test_load_patterns(%lu,ALL) => (%lu == %lu) => %lu", group, *bit_chk, param->read_correct_mask, (long unsigned int)(*bit_chk == param->read_correct_mask)); + return (*bit_chk == param->read_correct_mask); +} + +alt_u32 rw_mgr_mem_calibrate_read_test_patterns_all_ranks (alt_u32 group, alt_u32 num_tries, t_btfld *bit_chk) +{ + if (rw_mgr_mem_calibrate_read_test_patterns (0, group, num_tries, bit_chk, 1)) + { + return 1; + } + else + { + // case:139851 - if guaranteed read fails, we can retry using different dqs enable phases. + // It is possible that with the initial phase, dqs enable is asserted/deasserted too close + // to an dqs edge, truncating the read burst. + alt_u32 p; + for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++) { + scc_mgr_set_dqs_en_phase_all_ranks (group, p); + if (rw_mgr_mem_calibrate_read_test_patterns (0, group, num_tries, bit_chk, 1)) + { + return 1; + } + } + return 0; + } +} +#endif + +//USER load up the patterns we are going to use during a read test +#if DDRX +void rw_mgr_mem_calibrate_read_load_patterns (alt_u32 rank_bgn, alt_u32 all_ranks) +{ + alt_u32 r; + alt_u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); + + TRACE_FUNC(); + + for (r = rank_bgn; r < rank_end; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + + //USER Load up a constant bursts + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_WRITE_WAIT0); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_WRITE_WAIT1); + +#if QUARTER_RATE + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x01); +#endif +#if HALF_RATE + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x02); +#endif +#if FULL_RATE + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x04); +#endif + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_GUARANTEED_WRITE_WAIT2); + +#if QUARTER_RATE + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x01); +#endif +#if HALF_RATE + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x02); +#endif +#if FULL_RATE + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x04); +#endif + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_GUARANTEED_WRITE_WAIT3); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_GUARANTEED_WRITE); + } + + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); +} +#endif + +#if QDRII +void rw_mgr_mem_calibrate_read_load_patterns (alt_u32 rank_bgn, alt_u32 all_ranks) +{ + TRACE_FUNC(); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_WRITE_WAIT0); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_WRITE_WAIT1); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_GUARANTEED_WRITE); +} +#endif + +#if RLDRAMX +void rw_mgr_mem_calibrate_read_load_patterns (alt_u32 rank_bgn, alt_u32 all_ranks) +{ + TRACE_FUNC(); + alt_u32 r; + alt_u32 rank_end = RW_MGR_MEM_NUMBER_OF_RANKS;//all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); +#if QUARTER_RATE + alt_u32 write_data_cycles = 0x10; +#else + alt_u32 write_data_cycles = 0x20; +#endif + + for (r = rank_bgn; r < rank_end; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, write_data_cycles); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_WRITE_WAIT0); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, write_data_cycles); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_WRITE_WAIT1); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, write_data_cycles); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_GUARANTEED_WRITE_WAIT2); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, write_data_cycles); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_GUARANTEED_WRITE_WAIT3); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_GUARANTEED_WRITE); + } + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); +} +#endif + +static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks (void) +{ + rw_mgr_mem_calibrate_read_load_patterns (0, 1); +} + + +// pe checkout pattern for harden managers +//void pe_checkout_pattern (void) +//{ +// // test RW manager +// +// // do some reads to check load buffer +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1); +// +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2); +// +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B); +// +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B); +// +// // clear error word +// IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); +// +// IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_READ_B2B); +// +// alt_u32 readdata; +// +// // read error word +// readdata = IORD_32DIRECT(BASE_RW_MGR, 0); +// +// // read DI buffer +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0); +// +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1); +// +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2); +// +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B); +// +// IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0); +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B); +// +// // clear error word +// IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); +// +// // do read +// IOWR_32DIRECT (RW_MGR_LOOPBACK_MODE, 0, __RW_MGR_READ_B2B); +// +// // read error word +// readdata = IORD_32DIRECT(BASE_RW_MGR, 0); +// +// // error word should be 0x00 +// +// // read DI buffer +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0); +// +// // clear error word +// IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); +// +// // do dm read +// IOWR_32DIRECT (RW_MGR_LOOPBACK_MODE, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1); +// +// // read error word +// readdata = IORD_32DIRECT(BASE_RW_MGR, 0); +// +// // error word should be ff +// +// // read DI buffer +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0); +// readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0); +// +// // exit loopback mode +// IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_IDLE_LOOP2); +// +// // start of phy manager access +// +// readdata = IORD_32DIRECT (PHY_MGR_MAX_RLAT_WIDTH, 0); +// readdata = IORD_32DIRECT (PHY_MGR_MAX_AFI_WLAT_WIDTH, 0); +// readdata = IORD_32DIRECT (PHY_MGR_MAX_AFI_RLAT_WIDTH, 0); +// readdata = IORD_32DIRECT (PHY_MGR_CALIB_SKIP_STEPS, 0); +// readdata = IORD_32DIRECT (PHY_MGR_CALIB_VFIFO_OFFSET, 0); +// readdata = IORD_32DIRECT (PHY_MGR_CALIB_LFIFO_OFFSET, 0); +// +// // start of data manager test +// +// readdata = IORD_32DIRECT (DATA_MGR_DRAM_CFG , 0); +// readdata = IORD_32DIRECT (DATA_MGR_MEM_T_WL , 0); +// readdata = IORD_32DIRECT (DATA_MGR_MEM_T_ADD , 0); +// readdata = IORD_32DIRECT (DATA_MGR_MEM_T_RL , 0); +// readdata = IORD_32DIRECT (DATA_MGR_MEM_T_RFC , 0); +// readdata = IORD_32DIRECT (DATA_MGR_MEM_T_REFI , 0); +// readdata = IORD_32DIRECT (DATA_MGR_MEM_T_WR , 0); +// readdata = IORD_32DIRECT (DATA_MGR_MEM_T_MRD , 0); +// readdata = IORD_32DIRECT (DATA_MGR_COL_WIDTH , 0); +// readdata = IORD_32DIRECT (DATA_MGR_ROW_WIDTH , 0); +// readdata = IORD_32DIRECT (DATA_MGR_BANK_WIDTH , 0); +// readdata = IORD_32DIRECT (DATA_MGR_CS_WIDTH , 0); +// readdata = IORD_32DIRECT (DATA_MGR_ITF_WIDTH , 0); +// readdata = IORD_32DIRECT (DATA_MGR_DVC_WIDTH , 0); +// +//} + +//USER try a read and see if it returns correct data back. has dummy reads inserted into the mix +//USER used to align dqs enable. has more thorough checks than the regular read test. + +alt_u32 rw_mgr_mem_calibrate_read_test (alt_u32 rank_bgn, alt_u32 group, alt_u32 num_tries, alt_u32 all_correct, t_btfld *bit_chk, alt_u32 all_groups, alt_u32 all_ranks) +{ + alt_u32 r, vg; + t_btfld correct_mask_vg; + t_btfld tmp_bit_chk; + alt_u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); + +#if LRDIMM + // USER Disable MB Write-levelling mode and enter normal operation + rw_mgr_lrdimm_rc_program(0,12,0x0); +#endif + + *bit_chk = param->read_correct_mask; + correct_mask_vg = param->read_correct_mask_vg; + + alt_u32 quick_read_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION) || BFM_MODE; + + for (r = rank_bgn; r < rank_end; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x10); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x10); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2); + + if(quick_read_mode) { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x1); /* need at least two (1+1) reads to capture failures */ + } else if (all_groups) { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x06); + } else { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x32); + } + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B); + if(all_groups) { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, RW_MGR_MEM_IF_READ_DQS_WIDTH * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1); + } else { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0); + } + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B); + + tmp_bit_chk = 0; + for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) + { + //USER reset the fifos to get pointers to known state + + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + + tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS); + + IOWR_32DIRECT (all_groups ? RW_MGR_RUN_ALL_GROUPS : RW_MGR_RUN_SINGLE_GROUP, ((group*RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS+vg) << 2), __RW_MGR_READ_B2B); + tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0))); + + if (vg == 0) { + break; + } + } + *bit_chk &= tmp_bit_chk; + } + +#if ENABLE_BRINGUP_DEBUGGING + load_di_buf_gbl(); +#endif + + #if DDRX + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group << 2), __RW_MGR_CLEAR_DQS_ENABLE); + #endif + + if (all_correct) + { + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + DPRINT(2, "read_test(%lu,ALL,%lu) => (%lu == %lu) => %lu", group, all_groups, *bit_chk, param->read_correct_mask, (long unsigned int)(*bit_chk == param->read_correct_mask)); + return (*bit_chk == param->read_correct_mask); + } + else + { + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + DPRINT(2, "read_test(%lu,ONE,%lu) => (%lu != %lu) => %lu", group, all_groups, *bit_chk, (long unsigned int)0, (long unsigned int)(*bit_chk != 0x00)); + return (*bit_chk != 0x00); + } +} + +static inline alt_u32 rw_mgr_mem_calibrate_read_test_all_ranks (alt_u32 group, alt_u32 num_tries, alt_u32 all_correct, t_btfld *bit_chk, alt_u32 all_groups) +{ + return rw_mgr_mem_calibrate_read_test (0, group, num_tries, all_correct, bit_chk, all_groups, 1); +} + +#if ENABLE_DELAY_CHAIN_WRITE +void rw_mgr_incr_vfifo_auto(alt_u32 grp) { + alt_u32 v; + v = vfifo_settings[grp]%VFIFO_SIZE; + rw_mgr_incr_vfifo(grp, &v); + vfifo_settings[grp] = v; +} + +void rw_mgr_decr_vfifo_auto(alt_u32 grp) { + alt_u32 v; + v = vfifo_settings[grp]%VFIFO_SIZE; + rw_mgr_decr_vfifo(grp, &v); + vfifo_settings[grp] = v; +} +#endif // ENABLE_DELAY_CHAIN_WRITE + +void rw_mgr_incr_vfifo(alt_u32 grp, alt_u32 *v) { + //USER fiddle with FIFO + if(HARD_PHY) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HARD_PHY, 0, grp); + } else if (QUARTER_RATE_MODE && !HARD_VFIFO) { + if ((*v & 3) == 3) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_QR, 0, grp); + } else if ((*v & 2) == 2) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR_HR, 0, grp); + } else if ((*v & 1) == 1) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HR, 0, grp); + } else { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR, 0, grp); + } + } else if (HARD_VFIFO) { + // Arria V & Cyclone V have a hard full-rate VFIFO that only has a single incr signal + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR, 0, grp); + } + else { + if (!HALF_RATE_MODE || (*v & 1) == 1) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HR, 0, grp); + } else { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR, 0, grp); + } + } + + (*v)++; +#if USE_DQS_TRACKING && !HHP_HPS + IOWR_32DIRECT (TRK_V_POINTER, (grp << 2), *v); +#endif + BFM_INC_VFIFO; +} + +//Used in quick cal to properly loop through the duplicated VFIFOs in AV QDRII/RLDRAM +static inline void rw_mgr_incr_vfifo_all(alt_u32 grp, alt_u32 *v) { +#if VFIFO_CONTROL_WIDTH_PER_DQS == 1 + rw_mgr_incr_vfifo(grp, v); +#else + alt_u32 i; + for(i = 0; i < VFIFO_CONTROL_WIDTH_PER_DQS; i++) { + rw_mgr_incr_vfifo(grp*VFIFO_CONTROL_WIDTH_PER_DQS+i, v); + if(i != 0) { + (*v)--; + } + } +#endif +} + +void rw_mgr_decr_vfifo(alt_u32 grp, alt_u32 *v) { + + alt_u32 i; + + for (i = 0; i < VFIFO_SIZE-1; i++) { + rw_mgr_incr_vfifo(grp, v); + } +} + +//USER find a good dqs enable to use + +#if QDRII || RLDRAMX +alt_u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (alt_u32 grp) +{ + alt_u32 v; + alt_u32 found; + alt_u32 dtaps_per_ptap, tmp_delay; + t_btfld bit_chk; + + TRACE_FUNC("%lu", grp); + + reg_file_set_sub_stage(CAL_SUBSTAGE_DQS_EN_PHASE); + + found = 0; + + //USER first push vfifo until we get a passing read + for (v = 0; v < VFIFO_SIZE && found == 0;) { + DPRINT(2, "find_dqs_en_phase: vfifo %lu", BFM_GBL_GET(vfifo_idx)); + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found = 1; + } + + if (!found) { + //USER fiddle with FIFO +#if (VFIFO_CONTROL_WIDTH_PER_DQS != 1) + alt_u32 i; + for (i = 0; i < VFIFO_CONTROL_WIDTH_PER_DQS; i++) { + rw_mgr_incr_vfifo(grp*VFIFO_CONTROL_WIDTH_PER_DQS+i, &v); + v--; // undo increment of v in rw_mgr_incr_vfifo + } + v++; // add back single increment +#else + rw_mgr_incr_vfifo(grp, &v); +#endif + } + } + +#if (VFIFO_CONTROL_WIDTH_PER_DQS != 1) + if (found) { + // we found a vfifo setting that works for at least one vfifo "group" + // Some groups may need next vfifo setting, so check each one to + // see if we get new bits passing by increment the vfifo + alt_u32 i; + t_btfld best_bit_chk_inv; + alt_u8 found_on_first_check = (v == 1); + + best_bit_chk_inv = ~bit_chk; + + for (i = 0; i < VFIFO_CONTROL_WIDTH_PER_DQS; i++) { + rw_mgr_incr_vfifo(grp*VFIFO_CONTROL_WIDTH_PER_DQS+i, &v); + v--; // undo increment of v in rw_mgr_incr_vfifo, just in case it matters for next check + rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0); + if ((bit_chk & best_bit_chk_inv) != 0) { + // found some new bits + best_bit_chk_inv = ~bit_chk; + } else { + // no improvement, so put back + rw_mgr_decr_vfifo(grp*VFIFO_CONTROL_WIDTH_PER_DQS+i, &v); + v++; + if (found_on_first_check) { + // found on first vfifo check, so we also need to check earlier vfifo values + rw_mgr_decr_vfifo(grp*VFIFO_CONTROL_WIDTH_PER_DQS+i, &v); + v++; // undo decrement of v in rw_mgr_incr_vfifo, just in case it matters for next check + rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0); + if ((bit_chk & best_bit_chk_inv) != 0) { + // found some new bits + best_bit_chk_inv = ~bit_chk; + } else { + // no improvement, so put back + rw_mgr_incr_vfifo(grp*VFIFO_CONTROL_WIDTH_PER_DQS+i, &v); + v--; + } + } // found_on_first_check + } // check for new bits + } // loop over all vfifo control bits + } +#endif + + if (found) { + DPRINT(2, "find_dqs_en_phase: found vfifo=%lu", BFM_GBL_GET(vfifo_idx)); + // Not really dqs_enable left/right edge, but close enough for testing purposes + BFM_GBL_SET(dqs_enable_left_edge[grp].v,BFM_GBL_GET(vfifo_idx)); + BFM_GBL_SET(dqs_enable_right_edge[grp].v,BFM_GBL_GET(vfifo_idx)); + BFM_GBL_SET(dqs_enable_mid[grp].v,BFM_GBL_GET(vfifo_idx)); + } else { + DPRINT(2, "find_dqs_en_phase: no valid vfifo found"); + } + +#if ENABLE_TCL_DEBUG + // FIXME: Not a dynamically calculated value for dtaps_per_ptap + dtaps_per_ptap = 0; + tmp_delay = 0; + while (tmp_delay < IO_DELAY_PER_OPA_TAP) { + dtaps_per_ptap++; + tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP; + } + dtaps_per_ptap--; + ALTERA_ASSERT(dtaps_per_ptap <= IO_DQS_EN_DELAY_MAX); + + TCLRPT_SET(debug_summary_report->computed_dtap_per_ptap, dtaps_per_ptap); +#endif + + return found; +} +#endif + +#if DDRX +#if NEWVERSION_DQSEN + +// Navid's version + +alt_u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (alt_u32 grp) +{ + alt_u32 i, d, v, p, sr; + alt_u32 max_working_cnt; + alt_u32 fail_cnt; + t_btfld bit_chk; + alt_u32 dtaps_per_ptap; + alt_u32 found_begin, found_end; + alt_u32 work_bgn, work_mid, work_end, tmp_delay; + alt_u32 test_status; + alt_u32 found_passing_read, found_failing_read, initial_failing_dtap; +#if RUNTIME_CAL_REPORT + alt_u32 start_v[NUM_SHADOW_REGS], start_p[NUM_SHADOW_REGS], start_d[NUM_SHADOW_REGS]; + alt_u32 end_v[NUM_SHADOW_REGS], end_p[NUM_SHADOW_REGS], end_d[NUM_SHADOW_REGS]; + for(sr = 0; sr < NUM_SHADOW_REGS; sr++) { + start_v[sr] = 0; + start_p[sr] = 0; + start_d[sr] = 0; + } +#endif + + TRACE_FUNC("%lu", grp); + BFM_STAGE("find_dqs_en_phase"); + ALTERA_ASSERT(grp < RW_MGR_MEM_IF_READ_DQS_WIDTH); + + reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); + + scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); +#if SKIP_PTAP_0_DQS_EN_CAL + scc_mgr_set_dqs_en_phase_all_ranks(grp, 1); +#else + scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); +#endif + + fail_cnt = 0; + + //USER ************************************************************** + //USER * Step 0 : Determine number of delay taps for each phase tap * + + dtaps_per_ptap = 0; + tmp_delay = 0; + while (tmp_delay < IO_DELAY_PER_OPA_TAP) { + dtaps_per_ptap++; + tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP; + } + dtaps_per_ptap--; + ALTERA_ASSERT(dtaps_per_ptap <= IO_DQS_EN_DELAY_MAX); + tmp_delay = 0; + TCLRPT_SET(debug_summary_report->computed_dtap_per_ptap, dtaps_per_ptap); + + // VFIFO sweep +#if ENABLE_DQSEN_SWEEP + init_di_buffer(); + work_bgn = 0; + for (d = 0; d <= dtaps_per_ptap; d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) { + work_bgn = tmp_delay; + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + for (i = 0; i < VFIFO_SIZE; i++) { + for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++, work_bgn += IO_DELAY_PER_OPA_TAP) { + DPRINT(2, "find_dqs_en_phase: begin: vfifo=%lu ptap=%lu dtap=%lu", BFM_GBL_GET(vfifo_idx), p, d); + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + test_status = rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0); + + //if (p ==0 && d == 0) + sample_di_data(bit_chk, work_bgn, d, i, p); + } + //Increment FIFO + rw_mgr_incr_vfifo(grp, &v); + } + + work_bgn++; + } + flag_di_buffer_done(); +#endif + + //USER ********************************************************* + //USER * Step 1 : First push vfifo until we get a failing read * + for (v = 0; v < VFIFO_SIZE; ) { + DPRINT(2, "find_dqs_en_phase: vfifo %lu", BFM_GBL_GET(vfifo_idx)); + test_status = rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0); + if (!test_status) { + fail_cnt++; + + if (fail_cnt == 2) { + break; + } + } + + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } + + if (v >= VFIFO_SIZE) { + //USER no failing read found!! Something must have gone wrong + DPRINT(2, "find_dqs_en_phase: vfifo failed"); + return 0; + } + + max_working_cnt = 0; + + //USER ******************************************************** + //USER * step 2: find first working phase, increment in ptaps * + found_begin = 0; + work_bgn = 0; + for (d = 0; d <= dtaps_per_ptap; d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) { + work_bgn = tmp_delay; + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + for (i = 0; i < VFIFO_SIZE; i++) { + for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++, work_bgn += IO_DELAY_PER_OPA_TAP) { +#if SKIP_PTAP_0_DQS_EN_CAL + // Skip p == 0 setting for HARD PHY + if (p == 0) { + continue; + } +#endif + DPRINT(2, "find_dqs_en_phase: begin: vfifo=%lu ptap=%lu dtap=%lu", BFM_GBL_GET(vfifo_idx), p, d); + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + test_status = rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0); + + if (test_status) { + max_working_cnt = 1; + found_begin = 1; + break; + } + } + + if (found_begin) { + break; + } + + if (p > IO_DQS_EN_PHASE_MAX) { + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } + } + + if (found_begin) { + break; + } + } + + if (i >= VFIFO_SIZE) { + //USER cannot find working solution + DPRINT(2, "find_dqs_en_phase: no vfifo/ptap/dtap"); + return 0; + } + + work_end = work_bgn; + + //USER If d is 0 then the working window covers a phase tap and we can follow the old procedure + //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end + if (d == 0) { + //USER ******************************************************************** + //USER * step 3a: if we have room, back off by one and increment in dtaps * + COV(EN_PHASE_PTAP_OVERLAP); + + //USER Special case code for backing up a phase + if (p == 0) { + p = IO_DQS_EN_PHASE_MAX ; + rw_mgr_decr_vfifo(grp, &v); + } else { + p = p - 1; + } + tmp_delay = work_bgn - IO_DELAY_PER_OPA_TAP; + + // For HARD EMIF we increase the phase if p == 0 as we can't set that value +#if SKIP_PTAP_0_DQS_EN_CAL + if (p == 0) { + p = 1; + tmp_delay = work_bgn; + } +#endif + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + found_begin = 0; + for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < work_bgn; d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) { + + DPRINT(2, "find_dqs_en_phase: begin-2: vfifo=%lu ptap=%lu dtap=%lu", BFM_GBL_GET(vfifo_idx), p, d); + + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found_begin = 1; + work_bgn = tmp_delay; + break; + } + } + +#if BFM_MODE + { + alt_32 p2, v2, d2; + + // print out where the actual beginning is + if (found_begin) { + v2 = BFM_GBL_GET(vfifo_idx); + p2 = p; + d2 = d; + } else if (p == IO_DQS_EN_PHASE_MAX) { + v2 = (BFM_GBL_GET(vfifo_idx) + 1) % VFIFO_SIZE; +#if SKIP_PTAP_0_DQS_EN_CAL + p2 = 1; +#else + p2 = 0; +#endif + d2 = 0; + } else { + v2 = BFM_GBL_GET(vfifo_idx); + p2 = p + 1; + d2 = 0; + } + + DPRINT(2, "find_dqs_en_phase: begin found: vfifo=%lu ptap=%lu dtap=%lu begin=%lu", + v2, p2, d2, work_bgn); + BFM_GBL_SET(dqs_enable_left_edge[grp].v,v2); + BFM_GBL_SET(dqs_enable_left_edge[grp].p,p2); + BFM_GBL_SET(dqs_enable_left_edge[grp].d,d2); + BFM_GBL_SET(dqs_enable_left_edge[grp].ps,work_bgn); + } +#endif + // Record the debug data + // Currently dqsen is the same for all ranks + for (sr = 0; sr < NUM_SHADOW_REGS; sr++) + { + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].work_begin, work_bgn); + if (found_begin) + { + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].phase_begin, p); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].delay_begin, d); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].vfifo_begin, v % VFIFO_SIZE); +#if RUNTIME_CAL_REPORT + start_v[sr] = v % VFIFO_SIZE; + start_p[sr] = p; + start_d[sr] = d; +#endif + } + else if (p == IO_DQS_EN_PHASE_MAX) + { + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].phase_begin, 0); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].delay_begin, 0); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].vfifo_begin, (v+1) % VFIFO_SIZE); +#if RUNTIME_CAL_REPORT + start_v[sr] = (v+1) % VFIFO_SIZE; + start_p[sr] = p; + start_d[sr] = d; +#endif + } + else + { + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].phase_begin, p+1); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].delay_begin, 0); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].vfifo_begin, v % VFIFO_SIZE); +#if RUNTIME_CAL_REPORT + start_v[sr] = v % VFIFO_SIZE; + start_p[sr] = p+1; + start_d[sr] = d; +#endif + } + } + + //USER We have found a working dtap before the ptap found above + if (found_begin == 1) { + max_working_cnt++; + } + + //USER Restore VFIFO to old state before we decremented it (if needed) + p = p + 1; + if (p > IO_DQS_EN_PHASE_MAX) { + p = 0; + rw_mgr_incr_vfifo(grp, &v); + } + + scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); + + //USER *********************************************************************************** + //USER * step 4a: go forward from working phase to non working phase, increment in ptaps * + p = p + 1; + work_end += IO_DELAY_PER_OPA_TAP; + if (p > IO_DQS_EN_PHASE_MAX) { + //USER fiddle with FIFO + p = 0; + rw_mgr_incr_vfifo(grp, &v); + } + + found_end = 0; + for (; i < VFIFO_SIZE + 1; i++) { + for (; p <= IO_DQS_EN_PHASE_MAX; p++, work_end += IO_DELAY_PER_OPA_TAP) { + DPRINT(2, "find_dqs_en_phase: end: vfifo=%lu ptap=%lu dtap=%lu", BFM_GBL_GET(vfifo_idx), p, (long unsigned int)0); +#if SKIP_PTAP_0_DQS_EN_CAL + if ( p == 0 ) { + max_working_cnt++; + continue; + } +#endif + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found_end = 1; + break; + } else { + max_working_cnt++; + } + } + + if (found_end) { + break; + } + + if (p > IO_DQS_EN_PHASE_MAX) { + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + p = 0; + } + } + + if (i >= VFIFO_SIZE + 1) { + //USER cannot see edge of failing read + DPRINT(2, "find_dqs_en_phase: end: failed"); + return 0; + } + + //USER ********************************************************* + //USER * step 5a: back off one from last, increment in dtaps * + + //USER Special case code for backing up a phase +#if SKIP_PTAP_0_DQS_EN_CAL + if (p == 1) { + p = 0; + work_end -= IO_DELAY_PER_OPA_TAP; + max_working_cnt--; + } +#endif + if (p == 0) { + p = IO_DQS_EN_PHASE_MAX; + rw_mgr_decr_vfifo(grp, &v); + } else { + p = p - 1; + } + + work_end -= IO_DELAY_PER_OPA_TAP; + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + //USER * The actual increment of dtaps is done outside of the if/else loop to share code + d = 0; + + DPRINT(2, "find_dqs_en_phase: found end v/p: vfifo=%lu ptap=%lu", BFM_GBL_GET(vfifo_idx), p); + } else { + + // We should not be hitting this case as the window should be around one clock cycle wide + + //USER ******************************************************************** + //USER * step 3-5b: Find the right edge of the window using delay taps * + COV(EN_PHASE_PTAP_NO_OVERLAP); + + DPRINT(2, "find_dqs_en_phase: begin found: vfifo=%lu ptap=%lu dtap=%lu begin=%lu", BFM_GBL_GET(vfifo_idx), p, d, work_bgn); + BFM_GBL_SET(dqs_enable_left_edge[grp].v,BFM_GBL_GET(vfifo_idx)); + BFM_GBL_SET(dqs_enable_left_edge[grp].p,p); + BFM_GBL_SET(dqs_enable_left_edge[grp].d,d); + BFM_GBL_SET(dqs_enable_left_edge[grp].ps,work_bgn); + + work_end = work_bgn; + + //USER * The actual increment of dtaps is done outside of the if/else loop to share code + + //USER Only here to counterbalance a subtract later on which is not needed if this branch + //USER of the algorithm is taken + max_working_cnt++; + } + + //USER The dtap increment to find the failing edge is done here + for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) { + + DPRINT(2, "find_dqs_en_phase: end-2: dtap=%lu", d); + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } + } + + //USER Go back to working dtap + if (d != 0) { + work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP; + } + + DPRINT(2, "find_dqs_en_phase: found end v/p/d: vfifo=%lu ptap=%lu dtap=%lu end=%lu", BFM_GBL_GET(vfifo_idx), p, d-1, work_end); + BFM_GBL_SET(dqs_enable_right_edge[grp].v,BFM_GBL_GET(vfifo_idx)); + BFM_GBL_SET(dqs_enable_right_edge[grp].p,p); + BFM_GBL_SET(dqs_enable_right_edge[grp].d,d-1); + BFM_GBL_SET(dqs_enable_right_edge[grp].ps,work_end); + + // Record the debug data + for (sr = 0; sr < NUM_SHADOW_REGS; sr++) + { + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].work_end, work_end); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].phase_end, p); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].delay_end, d-1); + TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][grp].vfifo_end, v % VFIFO_SIZE); +#if RUNTIME_CAL_REPORT + end_v[sr] = v % VFIFO_SIZE; + end_p[sr] = p; + end_d[sr] = d-1; +#endif + } + + if (work_end >= work_bgn) { + //USER we have a working range + } else { + //USER nil range + DPRINT(2, "find_dqs_en_phase: end-2: failed"); + return 0; + } + + DPRINT(2, "find_dqs_en_phase: found range [%lu,%lu]", work_bgn, work_end); + +#if USE_DQS_TRACKING + // *************************************************************** + //USER * We need to calculate the number of dtaps that equal a ptap + //USER * To do that we'll back up a ptap and re-find the edge of the + //USER * window using dtaps + + DPRINT(2, "find_dqs_en_phase: calculate dtaps_per_ptap for tracking"); + + //USER Special case code for backing up a phase + +#if SKIP_PTAP_0_DQS_EN_CAL + if (p == 0 || p == 1) { +#else + if (p == 0) { +#endif + p = IO_DQS_EN_PHASE_MAX; + rw_mgr_decr_vfifo(grp, &v); + DPRINT(2, "find_dqs_en_phase: backed up cycle/phase: v=%lu p=%lu", BFM_GBL_GET(vfifo_idx), p); + } else { + p = p - 1; + DPRINT(2, "find_dqs_en_phase: backed up phase only: v=%lu p=%lu", BFM_GBL_GET(vfifo_idx), p); + } + + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + //USER Increase dtap until we first see a passing read (in case the window is smaller than a ptap), + //USER and then a failing read to mark the edge of the window again + + //USER Find a passing read + DPRINT(2, "find_dqs_en_phase: find passing read"); + found_passing_read = 0; + found_failing_read = 0; + initial_failing_dtap = d; + for (; d <= IO_DQS_EN_DELAY_MAX; d++) { + DPRINT(2, "find_dqs_en_phase: testing read d=%lu", d); + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found_passing_read = 1; + break; + } + } + + if (found_passing_read) { + //USER Find a failing read + DPRINT(2, "find_dqs_en_phase: find failing read"); + for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) { + DPRINT(2, "find_dqs_en_phase: testing read d=%lu", d); + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found_failing_read = 1; + break; + } + } + } else { + DPRINT(1, "find_dqs_en_phase: failed to calculate dtaps per ptap. Fall back on static value"); + } + + //USER The dynamically calculated dtaps_per_ptap is only valid if we found a passing/failing read + //USER If we didn't, it means d hit the max (IO_DQS_EN_DELAY_MAX). + //USER Otherwise, dtaps_per_ptap retains its statically calculated value. + if(found_passing_read && found_failing_read) { + dtaps_per_ptap = d - initial_failing_dtap; + } + + ALTERA_ASSERT(dtaps_per_ptap <= IO_DQS_EN_DELAY_MAX); +#if HHP_HPS + IOWR_32DIRECT (REG_FILE_DTAPS_PER_PTAP, 0, dtaps_per_ptap); +#else + IOWR_32DIRECT (TRK_DTAPS_PER_PTAP, 0, dtaps_per_ptap); +#endif + + DPRINT(2, "find_dqs_en_phase: dtaps_per_ptap=%lu - %lu = %lu", d, initial_failing_dtap, dtaps_per_ptap); +#endif + + //USER ******************************************** + //USER * step 6: Find the centre of the window * + + work_mid = (work_bgn + work_end) / 2; + tmp_delay = 0; + + DPRINT(2, "work_bgn=%ld work_end=%ld work_mid=%ld", work_bgn, work_end, work_mid); + //USER Get the middle delay to be less than a VFIFO delay + for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++, tmp_delay += IO_DELAY_PER_OPA_TAP); + DPRINT(2, "vfifo ptap delay %ld", tmp_delay); + while(work_mid > tmp_delay) work_mid -= tmp_delay; + DPRINT(2, "new work_mid %ld", work_mid); + tmp_delay = 0; + for (p = 0; p <= IO_DQS_EN_PHASE_MAX && tmp_delay < work_mid; p++, tmp_delay += IO_DELAY_PER_OPA_TAP); + tmp_delay -= IO_DELAY_PER_OPA_TAP; + DPRINT(2, "new p %ld, tmp_delay=%ld", p-1, tmp_delay); + for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < work_mid; d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP); + DPRINT(2, "new d %ld, tmp_delay=%ld", d, tmp_delay); + + // DQSEN same for all shadow reg + for(sr = 0; sr < NUM_SHADOW_REGS; sr++) { + TCLRPT_SET(debug_cal_report->cal_dqs_in_margins[sr][grp].dqsen_margin, max_working_cnt -1); + } +#if SKIP_PTAP_0_DQS_EN_CAL + if (p == 1) { + // If center lies at p=0 and d=d, then the safest choice is to set the center at p=1 and d=0 + p = 2; + d = 0; + } +#endif + scc_mgr_set_dqs_en_phase_all_ranks(grp, p-1); + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + //USER push vfifo until we can successfully calibrate. We can do this because + //USER the largest possible margin in 1 VFIFO cycle + + for (i = 0; i < VFIFO_SIZE; i++) { + DPRINT(2, "find_dqs_en_phase: center: vfifo=%lu", BFM_GBL_GET(vfifo_idx)); + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } + + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } + + if (i >= VFIFO_SIZE) { + DPRINT(2, "find_dqs_en_phase: center: failed"); + return 0; + } +#if RUNTIME_CAL_REPORT + for(sr = 0; sr < NUM_SHADOW_REGS; sr++) { + RPRINT("DQS Enable ; Group %lu ; Rank %lu ; Start VFIFO %2li ; Phase %li ; Delay %2li", grp, sr, start_v[sr], start_p[sr], start_d[sr]); + RPRINT("DQS Enable ; Group %lu ; Rank %lu ; End VFIFO %2li ; Phase %li ; Delay %2li", grp, sr, end_v[sr], end_p[sr], end_d[sr]); + // Case 174276: Normalizing VFIFO center + RPRINT("DQS Enable ; Group %lu ; Rank %lu ; Center VFIFO %2li ; Phase %li ; Delay %2li", grp, sr, (v % VFIFO_SIZE), p-1, d); + } +#endif + DPRINT(2, "find_dqs_en_phase: center found: vfifo=%li ptap=%lu dtap=%lu", BFM_GBL_GET(vfifo_idx), p-1, d); + #if ENABLE_DELAY_CHAIN_WRITE + vfifo_settings[grp] = v; + #endif // ENABLE_DELAY_CHAIN_WRITE + BFM_GBL_SET(dqs_enable_mid[grp].v,BFM_GBL_GET(vfifo_idx)); + BFM_GBL_SET(dqs_enable_mid[grp].p,p-1); + BFM_GBL_SET(dqs_enable_mid[grp].d,d); + BFM_GBL_SET(dqs_enable_mid[grp].ps,work_mid); + return 1; +} + +#if 0 +// Ryan's algorithm + +alt_u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (alt_u32 grp) +{ + alt_u32 i, d, v, p; + alt_u32 min_working_p, max_working_p, min_working_d, max_working_d, max_working_cnt; + alt_u32 fail_cnt; + t_btfld bit_chk; + alt_u32 dtaps_per_ptap; + alt_u32 found_begin, found_end; + alt_u32 tmp_delay; + + TRACE_FUNC("%lu", grp); + + reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); + + scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); + scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); + + fail_cnt = 0; + + //USER ************************************************************** + //USER * Step 0 : Determine number of delay taps for each phase tap * + + dtaps_per_ptap = 0; + tmp_delay = 0; + while (tmp_delay < IO_DELAY_PER_OPA_TAP) { + dtaps_per_ptap++; + tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP; + } + dtaps_per_ptap--; + + //USER ********************************************************* + //USER * Step 1 : First push vfifo until we get a failing read * + for (v = 0; v < VFIFO_SIZE; ) { + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + fail_cnt++; + + if (fail_cnt == 2) { + break; + } + } + + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } + + if (i >= VFIFO_SIZE) { + //USER no failing read found!! Something must have gone wrong + return 0; + } + + max_working_cnt = 0; + min_working_p = 0; + + //USER ******************************************************** + //USER * step 2: find first working phase, increment in ptaps * + found_begin = 0; + for (d = 0; d <= dtaps_per_ptap; d++) { + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + for (i = 0; i < VFIFO_SIZE; i++) { + for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++) { + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + max_working_cnt = 1; + found_begin = 1; + break; + } + } + + if (found_begin) { + break; + } + + if (p > IO_DQS_EN_PHASE_MAX) { + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } + } + + if (found_begin) { + break; + } + } + + if (i >= VFIFO_SIZE) { + //USER cannot find working solution + return 0; + } + + min_working_p = p; + + //USER If d is 0 then the working window covers a phase tap and we can follow the old procedure + //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end + if (d == 0) { + //USER ******************************************************************** + //USER * step 3a: if we have room, back off by one and increment in dtaps * + min_working_d = 0; + + //USER Special case code for backing up a phase + if (p == 0) { + p = IO_DQS_EN_PHASE_MAX ; + rw_mgr_decr_vfifo(grp, &v); + } else { + p = p - 1; + } + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + found_begin = 0; + for (d = 0; d <= dtaps_per_ptap; d++) { + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found_begin = 1; + min_working_d = d; + break; + } + } + + //USER We have found a working dtap before the ptap found above + if (found_begin == 1) { + min_working_p = p; + max_working_cnt++; + } + + //USER Restore VFIFO to old state before we decremented it + p = p + 1; + if (p > IO_DQS_EN_PHASE_MAX) { + p = 0; + rw_mgr_incr_vfifo(grp, &v); + } + + scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); + + + //USER *********************************************************************************** + //USER * step 4a: go forward from working phase to non working phase, increment in ptaps * + p = p + 1; + if (p > IO_DQS_EN_PHASE_MAX) { + //USER fiddle with FIFO + p = 0; + rw_mgr_incr_vfifo(grp, &v); + } + + found_end = 0; + for (; i < VFIFO_SIZE+1; i++) { + for (; p <= IO_DQS_EN_PHASE_MAX; p++) { + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found_end = 1; + break; + } else { + max_working_cnt++; + } + } + + if (found_end) { + break; + } + + if (p > IO_DQS_EN_PHASE_MAX) { + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + p = 0; + } + } + + if (i >= VFIFO_SIZE+1) { + //USER cannot see edge of failing read + return 0; + } + + //USER ********************************************************* + //USER * step 5a: back off one from last, increment in dtaps * + max_working_d = 0; + + //USER Special case code for backing up a phase + if (p == 0) { + p = IO_DQS_EN_PHASE_MAX; + rw_mgr_decr_vfifo(grp, &v); + } else { + p = p - 1; + } + + max_working_p = p; + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + + for (d = 0; d <= IO_DQS_EN_DELAY_MAX; d++) { + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } + } + + //USER Go back to working dtap + if (d != 0) { + max_working_d = d - 1; + } + + } else { + + //USER ******************************************************************** + //USER * step 3-5b: Find the right edge of the window using delay taps * + + max_working_p = min_working_p; + min_working_d = d; + + for (; d <= IO_DQS_EN_DELAY_MAX; d++) { + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } + } + + //USER Go back to working dtap + if (d != 0) { + max_working_d = d - 1; + } + + //USER Only here to counterbalance a subtract later on which is not needed if this branch + //USER of the algorithm is taken + max_working_cnt++; + } + + //USER ******************************************** + //USER * step 6: Find the centre of the window * + + //USER If the number of working phases is even we will step back a phase and find the + //USER edge with a larger delay chain tap + if ((max_working_cnt & 1) == 0) { + p = min_working_p + (max_working_cnt-1)/2; + + //USER Special case code for backing up a phase + if (max_working_p == 0) { + max_working_p = IO_DQS_EN_PHASE_MAX; + rw_mgr_decr_vfifo(grp, &v); + } else { + max_working_p = max_working_p - 1; + } + + scc_mgr_set_dqs_en_phase_all_ranks(grp, max_working_p); + + //USER Code to determine at which dtap we should start searching again for a failure + //USER If we've moved back such that the max and min p are the same, we should start searching + //USER from where the window actually exists + if (max_working_p == min_working_p) { + d = min_working_d; + } else { + d = max_working_d; + } + + for (; d <= IO_DQS_EN_DELAY_MAX; d++) { + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } + } + + //USER Go back to working dtap + if (d != 0) { + max_working_d = d - 1; + } + } else { + p = min_working_p + (max_working_cnt)/2; + } + + while (p > IO_DQS_EN_PHASE_MAX) { + p -= (IO_DQS_EN_PHASE_MAX + 1); + } + + d = (min_working_d + max_working_d)/2; + + scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + + //USER push vfifo until we can successfully calibrate + + for (i = 0; i < VFIFO_SIZE; i++) { + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } + + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } + + if (i >= VFIFO_SIZE) { + return 0; + } + + return 1; +} + +#endif + +#else +// Val's original version + +alt_u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (alt_u32 grp) +{ + alt_u32 i, j, v, d; + alt_u32 min_working_d, max_working_cnt; + alt_u32 fail_cnt; + t_btfld bit_chk; + alt_u32 delay_per_ptap_mid; + + TRACE_FUNC("%lu", grp); + + reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); + + scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); + scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); + + fail_cnt = 0; + + //USER first push vfifo until we get a failing read + v = 0; + for (i = 0; i < VFIFO_SIZE; i++) { + if (!rw_mgr_mem_calibrate_read_test_all_ranks (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { + fail_cnt++; + + if (fail_cnt == 2) { + break; + } + } + + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } + + if (v >= VFIFO_SIZE) { + //USER no failing read found!! Something must have gone wrong + + return 0; + } + + max_working_cnt = 0; + min_working_d = 0; + + for (i = 0; i < VFIFO_SIZE+1; i++) { + for (d = 0; d <= IO_DQS_EN_PHASE_MAX; d++) { + scc_mgr_set_dqs_en_phase_all_ranks(grp, d); + + rw_mgr_mem_calibrate_read_test_all_ranks (grp, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0); + if (bit_chk) { + //USER passing read + + if (max_working_cnt == 0) { + min_working_d = d; + } + + max_working_cnt++; + } else { + if (max_working_cnt > 0) { + //USER already have one working value + break; + } + } + } + + if (d > IO_DQS_EN_PHASE_MAX) { + //USER fiddle with FIFO + rw_mgr_incr_vfifo(grp, &v); + } else { + //USER found working solution! + + d = min_working_d + (max_working_cnt - 1) / 2; + + while (d > IO_DQS_EN_PHASE_MAX) { + d -= (IO_DQS_EN_PHASE_MAX + 1); + } + + break; + } + } + + if (i >= VFIFO_SIZE+1) { + //USER cannot find working solution or cannot see edge of failing read + + return 0; + } + + //USER in the case the number of working steps is even, use 50ps taps to further center the window + + if ((max_working_cnt & 1) == 0) { + delay_per_ptap_mid = IO_DELAY_PER_OPA_TAP / 2; + + //USER increment in 50ps taps until we reach the required amount + + for (i = 0, j = 0; i <= IO_DQS_EN_DELAY_MAX && j < delay_per_ptap_mid; i++, j += IO_DELAY_PER_DQS_EN_DCHAIN_TAP); + + scc_mgr_set_dqs_en_delay_all_ranks(grp, i - 1); + } + + scc_mgr_set_dqs_en_phase_all_ranks(grp, d); + + //USER push vfifo until we can successfully calibrate + + for (i = 0; i < VFIFO_SIZE; i++) { + if (rw_mgr_mem_calibrate_read_test_all_ranks (grp, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } + + //USER fiddle with FIFO + rw_mgr_incr_vfifo (grp, &v); + } + + if (i >= VFIFO_SIZE) { + return 0; + } + + return 1; +} + +#endif +#endif + + +// Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different dq_in_delay values +static inline alt_u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay (alt_u32 write_group, alt_u32 read_group, alt_u32 test_bgn) +{ +#if STRATIXV || ARRIAV || CYCLONEV || ARRIAVGZ + alt_u32 found; + alt_u32 i; + alt_u32 p; + alt_u32 d; + alt_u32 r; + + const alt_u32 delay_step = IO_IO_IN_DELAY_MAX/(RW_MGR_MEM_DQ_PER_READ_DQS-1); /* we start at zero, so have one less dq to devide among */ + + TRACE_FUNC("(%lu,%lu,%lu)", write_group, read_group, test_bgn); + + // try different dq_in_delays since the dq path is shorter than dqs + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + select_shadow_regs_for_update(r, write_group, 1); + for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) { + DPRINT(1, "rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay: g=%lu/%lu r=%lu, i=%lu p=%lu d=%lu", + write_group, read_group, r, i, p, d); + scc_mgr_set_dq_in_delay(write_group, p, d); + scc_mgr_load_dq (p); + } + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + + found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group); + + DPRINT(1, "rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay: g=%lu/%lu found=%lu; Reseting delay chain to zero", + write_group, read_group, found); + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + select_shadow_regs_for_update(r, write_group, 1); + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { + scc_mgr_set_dq_in_delay(write_group, p, 0); + scc_mgr_load_dq (p); + } + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + + return found; +#else + return rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group); +#endif +} + +//USER per-bit deskew DQ and center + +#if NEWVERSION_RDDESKEW + +alt_u32 rw_mgr_mem_calibrate_vfifo_center (alt_u32 rank_bgn, alt_u32 write_group, alt_u32 read_group, alt_u32 test_bgn, alt_u32 use_read_test, alt_u32 update_fom) +{ + alt_u32 i, p, d, min_index; + //USER Store these as signed since there are comparisons with signed numbers + t_btfld bit_chk; + t_btfld sticky_bit_chk; + alt_32 left_edge[RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 right_edge[RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 final_dq[RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_32 mid; + alt_32 orig_mid_min, mid_min; + alt_32 new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs, final_dqs_en; + alt_32 dq_margin, dqs_margin; + alt_u32 stop; + + TRACE_FUNC("%lu %lu", read_group, test_bgn); +#if BFM_MODE + if (use_read_test) { + BFM_STAGE("vfifo_center"); + } else { + BFM_STAGE("vfifo_center_after_writes"); + } +#endif + + ALTERA_ASSERT(read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH); + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + start_dqs = READ_SCC_DQS_IN_DELAY(read_group); + if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { + start_dqs_en = READ_SCC_DQS_EN_DELAY(read_group); + } + + select_curr_shadow_reg_using_rank(rank_bgn); + + //USER per-bit deskew + + //USER set the left and right edge of each bit to an illegal value + //USER use (IO_IO_IN_DELAY_MAX + 1) as an illegal value + sticky_bit_chk = 0; + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + left_edge[i] = IO_IO_IN_DELAY_MAX + 1; + right_edge[i] = IO_IO_IN_DELAY_MAX + 1; + } + + //USER Search for the left edge of the window for each bit + for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) { + scc_mgr_apply_group_dq_in_delay (write_group, test_bgn, d); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit + if (use_read_test) { + stop = !rw_mgr_mem_calibrate_read_test (rank_bgn, read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0, 0); + } else { + rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0); + bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS * (read_group - (write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH))); + stop = (bit_chk == 0); + } + sticky_bit_chk = sticky_bit_chk | bit_chk; + stop = stop && (sticky_bit_chk == param->read_correct_mask); + DPRINT(2, "vfifo_center(left): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT " && %lu", d, sticky_bit_chk, param->read_correct_mask, stop); + + if (stop == 1) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + if (bit_chk & 1) { + //USER Remember a passing test as the left_edge + left_edge[i] = d; + } else { + //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge + if (left_edge[i] == IO_IO_IN_DELAY_MAX + 1) { + right_edge[i] = -(d + 1); + } + } + DPRINT(2, "vfifo_center[l,d=%lu]: bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld", + d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]); + bit_chk = bit_chk >> 1; + } + } + } + + //USER Reset DQ delay chains to 0 + scc_mgr_apply_group_dq_in_delay (write_group, test_bgn, 0); + sticky_bit_chk = 0; + for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) { + + DPRINT(2, "vfifo_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i], i, right_edge[i]); + + //USER Check for cases where we haven't found the left edge, which makes our assignment of the the + //USER right edge invalid. Reset it to the illegal value. + if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) { + right_edge[i] = IO_IO_IN_DELAY_MAX + 1; + DPRINT(2, "vfifo_center: reset right_edge[%lu]: %ld", i, right_edge[i]); + } + + //USER Reset sticky bit (except for bits where we have seen both the left and right edge) + sticky_bit_chk = sticky_bit_chk << 1; + if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) && (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) { + sticky_bit_chk = sticky_bit_chk | 1; + } + + if (i == 0) + { + break; + } + } + + //USER Search for the right edge of the window for each bit + for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) { + scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs); + if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { + alt_u32 delay = d + start_dqs_en; + if (delay > IO_DQS_EN_DELAY_MAX) { + delay = IO_DQS_EN_DELAY_MAX; + } + scc_mgr_set_dqs_en_delay(read_group, delay); + } + scc_mgr_load_dqs (read_group); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit + if (use_read_test) { + stop = !rw_mgr_mem_calibrate_read_test (rank_bgn, read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0, 0); + } else { + rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0); + bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS * (read_group - (write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH))); + stop = (bit_chk == 0); + } + sticky_bit_chk = sticky_bit_chk | bit_chk; + stop = stop && (sticky_bit_chk == param->read_correct_mask); + + DPRINT(2, "vfifo_center(right): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT " && %lu", d, sticky_bit_chk, param->read_correct_mask, stop); + + if (stop == 1) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + if (bit_chk & 1) { + //USER Remember a passing test as the right_edge + right_edge[i] = d; + } else { + if (d != 0) { + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1) { + left_edge[i] = -(d + 1); + } + } else { + //USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1 + if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1 && left_edge[i] != IO_IO_IN_DELAY_MAX + 1) { + right_edge[i] = -1; + } + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + else if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1) { + left_edge[i] = -(d + 1); + } + + } + } + + DPRINT(2, "vfifo_center[r,d=%lu]: bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld", + d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]); + bit_chk = bit_chk >> 1; + } + } + } + + // Store all observed margins +#if ENABLE_TCL_DEBUG + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + alt_u32 dq = read_group*RW_MGR_MEM_DQ_PER_READ_DQS + i; + + ALTERA_ASSERT(dq < RW_MGR_MEM_DATA_WIDTH); + + TCLRPT_SET(debug_cal_report->cal_dq_in_margins[curr_shadow_reg][dq].left_edge, left_edge[i]); + TCLRPT_SET(debug_cal_report->cal_dq_in_margins[curr_shadow_reg][dq].right_edge, right_edge[i]); + } +#endif + + //USER Check that all bits have a window + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + DPRINT(2, "vfifo_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i], i, right_edge[i]); + BFM_GBL_SET(dq_read_left_edge[read_group][i],left_edge[i]); + BFM_GBL_SET(dq_read_right_edge[read_group][i],right_edge[i]); + if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i] == IO_IO_IN_DELAY_MAX + 1)) { + + //USER Restore delay chain settings before letting the loop in + //USER rw_mgr_mem_calibrate_vfifo to retry different dqs/ck relationships + scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs); + if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { + scc_mgr_set_dqs_en_delay(read_group, start_dqs_en); + } + scc_mgr_load_dqs (read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + DPRINT(1, "vfifo_center: failed to find edge [%lu]: %ld %ld", i, left_edge[i], right_edge[i]); + if (use_read_test) { + set_failing_group_stage(read_group*RW_MGR_MEM_DQ_PER_READ_DQS + i, CAL_STAGE_VFIFO, CAL_SUBSTAGE_VFIFO_CENTER); + } else { + set_failing_group_stage(read_group*RW_MGR_MEM_DQ_PER_READ_DQS + i, CAL_STAGE_VFIFO_AFTER_WRITES, CAL_SUBSTAGE_VFIFO_CENTER); + } + return 0; + } + } + + //USER Find middle of window for each DQ bit + mid_min = left_edge[0] - right_edge[0]; + min_index = 0; + for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + mid = left_edge[i] - right_edge[i]; + if (mid < mid_min) { + mid_min = mid; + min_index = i; + } + } + + //USER -mid_min/2 represents the amount that we need to move DQS. If mid_min is odd and positive we'll need to add one to + //USER make sure the rounding in further calculations is correct (always bias to the right), so just add 1 for all positive values + if (mid_min > 0) { + mid_min++; + } + mid_min = mid_min / 2; + + DPRINT(1, "vfifo_center: mid_min=%ld (index=%lu)", mid_min, min_index); + + //USER Determine the amount we can change DQS (which is -mid_min) + orig_mid_min = mid_min; +#if ENABLE_DQS_IN_CENTERING + new_dqs = start_dqs - mid_min; + if (new_dqs > IO_DQS_IN_DELAY_MAX) { + new_dqs = IO_DQS_IN_DELAY_MAX; + } else if (new_dqs < 0) { + new_dqs = 0; + } + mid_min = start_dqs - new_dqs; + DPRINT(1, "vfifo_center: new mid_min=%ld new_dqs=%ld", mid_min, new_dqs); + + if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { + if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX) { + mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX; + } else if (start_dqs_en - mid_min < 0) { + mid_min += start_dqs_en - mid_min; + } + } + new_dqs = start_dqs - mid_min; +#else + new_dqs = start_dqs; + mid_min = 0; +#endif + + DPRINT(1, "vfifo_center: start_dqs=%ld start_dqs_en=%ld new_dqs=%ld mid_min=%ld", + start_dqs, IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1, new_dqs, mid_min); + + //USER Initialize data for export structures + dqs_margin = IO_IO_IN_DELAY_MAX + 1; + dq_margin = IO_IO_IN_DELAY_MAX + 1; + + //USER add delay to bring centre of all DQ windows to the same "level" + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { + //USER Use values before divide by 2 to reduce round off error + shift_dq = (left_edge[i] - right_edge[i] - (left_edge[min_index] - right_edge[min_index]))/2 + (orig_mid_min - mid_min); + + DPRINT(2, "vfifo_center: before: shift_dq[%lu]=%ld", i, shift_dq); + + if (shift_dq + (alt_32)READ_SCC_DQ_IN_DELAY(p) > (alt_32)IO_IO_IN_DELAY_MAX) { + shift_dq = (alt_32)IO_IO_IN_DELAY_MAX - READ_SCC_DQ_IN_DELAY(i); + } else if (shift_dq + (alt_32)READ_SCC_DQ_IN_DELAY(p) < 0) { + shift_dq = -(alt_32)READ_SCC_DQ_IN_DELAY(p); + } + DPRINT(2, "vfifo_center: after: shift_dq[%lu]=%ld", i, shift_dq); + final_dq[i] = READ_SCC_DQ_IN_DELAY(p) + shift_dq; + scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]); + scc_mgr_load_dq (p); + + DPRINT(2, "vfifo_center: margin[%lu]=[%ld,%ld]", i, + left_edge[i] - shift_dq + (-mid_min), + right_edge[i] + shift_dq - (-mid_min)); + //USER To determine values for export structures + if (left_edge[i] - shift_dq + (-mid_min) < dq_margin) { + dq_margin = left_edge[i] - shift_dq + (-mid_min); + } + if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin) { + dqs_margin = right_edge[i] + shift_dq - (-mid_min); + } + } + +#if ENABLE_DQS_IN_CENTERING + final_dqs = new_dqs; + if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { + final_dqs_en = start_dqs_en - mid_min; + } +#else + final_dqs = start_dqs; + if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { + final_dqs_en = start_dqs_en; + } +#endif + + //USER Move DQS-en + if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { + scc_mgr_set_dqs_en_delay(read_group, final_dqs_en); + scc_mgr_load_dqs (read_group); + } + +#if QDRII || RLDRAMX + //USER Move DQS. Do it gradually to minimize the chance of causing a timing + //USER failure in core FPGA logic driven by an input-strobe-derived clock + d = READ_SCC_DQS_IN_DELAY(read_group); + while (d != final_dqs) { + if (d > final_dqs) { + --d; + } else { + ++d; + } + scc_mgr_set_dqs_bus_in_delay(read_group, d); + scc_mgr_load_dqs (read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } +#else + //USER Move DQS + scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs); + scc_mgr_load_dqs (read_group); +#endif + + if(update_fom) { + //USER Export values + gbl->fom_in += (dq_margin + dqs_margin)/(RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + TCLRPT_SET(debug_summary_report->fom_in, debug_summary_report->fom_in + (dq_margin + dqs_margin)/(RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)); + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][write_group].fom_in, debug_cal_report->cal_status_per_group[curr_shadow_reg][write_group].fom_in + (dq_margin + dqs_margin)/(RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)); + } + + TCLRPT_SET(debug_cal_report->cal_dqs_in_margins[curr_shadow_reg][read_group].dqs_margin, dqs_margin); + TCLRPT_SET(debug_cal_report->cal_dqs_in_margins[curr_shadow_reg][read_group].dq_margin, dq_margin); + + DPRINT(2, "vfifo_center: dq_margin=%ld dqs_margin=%ld", dq_margin, dqs_margin); + +#if RUNTIME_CAL_REPORT + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + if (use_read_test) { + RPRINT("Read Deskew ; DQ %2lu ; Rank %lu ; Left edge %3li ; Right edge %3li ; DQ delay %2li ; DQS delay %2li", read_group*RW_MGR_MEM_DQ_PER_READ_DQS + i, curr_shadow_reg, left_edge[i], right_edge[i], final_dq[i], final_dqs); + } else { + RPRINT("Read after Write ; DQ %2lu ; Rank %lu ; Left edge %3li ; Right edge %3li ; DQ delay %2li ; DQS delay %2li", read_group*RW_MGR_MEM_DQ_PER_READ_DQS + i, curr_shadow_reg, left_edge[i], right_edge[i], final_dq[i], final_dqs); + } + } +#endif + + //USER Do not remove this line as it makes sure all of our decisions have been applied + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + return (dq_margin >= 0) && (dqs_margin >= 0); +} + +#else + +alt_u32 rw_mgr_mem_calibrate_vfifo_center (alt_u32 rank_bgn, alt_u32 grp, alt_u32 test_bgn, alt_u32 use_read_test) +{ + alt_u32 i, p, d; + alt_u32 mid; + t_btfld bit_chk; + alt_u32 max_working_dq[RW_MGR_MEM_DQ_PER_READ_DQS]; + alt_u32 dq_margin, dqs_margin; + alt_u32 start_dqs; + + TRACE_FUNC("%lu %lu", grp, test_bgn); + + //USER per-bit deskew. + //USER start of the per-bit sweep with the minimum working delay setting for + //USER all bits. + + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + max_working_dq[i] = 0; + } + + for (d = 1; d <= IO_IO_IN_DELAY_MAX; d++) { + scc_mgr_apply_group_dq_in_delay (write_group, test_bgn, d); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + if (!rw_mgr_mem_calibrate_read_test (rank_bgn, grp, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0, 0)) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + if (bit_chk & 1) { + max_working_dq[i] = d; + } + bit_chk = bit_chk >> 1; + } + } + } + + //USER determine minimum working value for DQ + + dq_margin = IO_IO_IN_DELAY_MAX; + + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + if (max_working_dq[i] < dq_margin) { + dq_margin = max_working_dq[i]; + } + } + + //USER add delay to bring all DQ windows to the same "level" + + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { + if (max_working_dq[i] > dq_margin) { + scc_mgr_set_dq_in_delay(write_group, i, max_working_dq[i] - dq_margin); + } else { + scc_mgr_set_dq_in_delay(write_group, i, 0); + } + + scc_mgr_load_dq (p, p); + } + + //USER sweep DQS window, may potentially have more window due to per-bit-deskew that was done + //USER in the previous step. + + start_dqs = READ_SCC_DQS_IN_DELAY(grp); + + for (d = start_dqs + 1; d <= IO_DQS_IN_DELAY_MAX; d++) { + scc_mgr_set_dqs_bus_in_delay(grp, d); + scc_mgr_load_dqs (grp); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + if (!rw_mgr_mem_calibrate_read_test (rank_bgn, grp, NUM_READ_TESTS, PASS_ALL_BITS, &bit_chk, 0, 0)) { + break; + } + } + + scc_mgr_set_dqs_bus_in_delay(grp, start_dqs); + + //USER margin on the DQS pin + + dqs_margin = d - start_dqs - 1; + + //USER find mid point, +1 so that we don't go crazy pushing DQ + + mid = (dq_margin + dqs_margin + 1) / 2; + + gbl->fom_in += dq_margin + dqs_margin; +// TCLRPT_SET(debug_summary_report->fom_in, debug_summary_report->fom_in + (dq_margin + dqs_margin)); +// TCLRPT_SET(debug_cal_report->cal_status_per_group[grp].fom_in, (dq_margin + dqs_margin)); + + + + +#if ENABLE_DQS_IN_CENTERING + //USER center DQS ... if the headroom is setup properly we shouldn't need to + + if (dqs_margin > mid) { + scc_mgr_set_dqs_bus_in_delay(grp, READ_SCC_DQS_IN_DELAY(grp) + dqs_margin - mid); + + if (DDRX) { + alt_u32 delay = READ_SCC_DQS_EN_DELAY(grp) + dqs_margin - mid; + + if (delay > IO_DQS_EN_DELAY_MAX) { + delay = IO_DQS_EN_DELAY_MAX; + } + + scc_mgr_set_dqs_en_delay(grp, delay); + } + } +#endif + + scc_mgr_load_dqs (grp); + + //USER center DQ + + if (dq_margin > mid) { + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { + scc_mgr_set_dq_in_delay(write_group, i, READ_SCC_DQ_IN_DELAY(i) + dq_margin - mid); + scc_mgr_load_dq (p, p); + } + + dqs_margin += dq_margin - mid; + dq_margin -= dq_margin - mid; + } + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + return (dq_margin + dqs_margin) > 0; +} + +#endif + +//USER calibrate the read valid prediction FIFO. +//USER +//USER - read valid prediction will consist of finding a good DQS enable phase, DQS enable delay, DQS input phase, and DQS input delay. +//USER - we also do a per-bit deskew on the DQ lines. + +#if DYNAMIC_CALIBRATION_MODE || STATIC_QUICK_CALIBRATION + +#if !ENABLE_SUPER_QUICK_CALIBRATION + +//USER VFIFO Calibration -- Quick Calibration +alt_u32 rw_mgr_mem_calibrate_vfifo (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 v, d, i; + alt_u32 found; + t_btfld bit_chk; + + TRACE_FUNC("%lu %lu", grp, test_bgn); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_VFIFO); + + //USER Load up the patterns used by read calibration + + rw_mgr_mem_calibrate_read_load_patterns_all_ranks (); + + //USER maximum phase values for the sweep + + + //USER update info for sims + + reg_file_set_group(g); + + found = 0; + v = 0; + for (i = 0; i < VFIFO_SIZE && found == 0; i++) { + for (d = 0; d <= IO_DQS_EN_PHASE_MAX && found == 0; d++) { + if (DDRX) + { + scc_mgr_set_dqs_en_phase_all_ranks(g, d); + } + + //USER calibrate the vfifo with the current dqs enable phase setting + + if (rw_mgr_mem_calibrate_read_test_all_ranks (g, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found = 1; + } + } + + if (found) { + break; + } else { + rw_mgr_incr_vfifo_all (g, &v); + } + } + + return found; +} + +#else + +//USER VFIFO Calibration -- Super Quick Calibration +alt_u32 rw_mgr_mem_calibrate_vfifo (alt_u32 grp, alt_u32 test_bgn2) +{ + alt_u32 g, v, d, i; + alt_u32 test_bgn; + alt_u32 found; + t_btfld bit_chk; + alt_u32 phase_increment; + alt_u32 final_v_setting = 0; + alt_u32 final_d_setting = 0; + + TRACE_FUNC("%lu %lu", grp, test_bgn2); + + #if ARRIAV || CYCLONEV + // Compensate for simulation model behaviour + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + scc_mgr_set_dqs_bus_in_delay(i, 10); + scc_mgr_load_dqs (i); + } + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + #endif + + //USER The first call to this function will calibrate all groups + if (grp !=0) { + return 1; + } + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_VFIFO); + + //USER Load up the patterns used by read calibration + + rw_mgr_mem_calibrate_read_load_patterns_all_ranks (); + + //USER maximum phase values for the sweep + + //USER Calibrate group 0 + g = 0; + test_bgn = 0; + + //USER update info for sims + + reg_file_set_group(g); + + found = 0; + + //USER In behavioral simulation only phases 0 and IO_DQS_EN_PHASE_MAX/2 are relevant + //USER All other values produces the same results as those 2, so there's really no + //USER point in sweeping them all + phase_increment = (IO_DQS_EN_PHASE_MAX + 1) / 2; + //USER Make sure phase_increment is > 0 to prevent infinite loop + if (phase_increment == 0) phase_increment++; + + v = 0; + for (i = 0; i < VFIFO_SIZE && found == 0; i++) { + for (d = 0; d <= IO_DQS_EN_PHASE_MAX && found == 0; d += phase_increment) { + + scc_mgr_set_dqs_en_phase_all_ranks(g, d); + + //USER calibrate the vfifo with the current dqs enable phase setting + + if (rw_mgr_mem_calibrate_read_test_all_ranks (g, 1, PASS_ONE_BIT, &bit_chk, 0)) { + found = 1; + final_v_setting = v; + final_d_setting = d; + } + } + + if (!found) { + rw_mgr_incr_vfifo_all (g, &v); + } else { + break; + } + } + + if (!found) return 0; + + //USER Now copy the calibration settings to all other groups + for (g = 1, test_bgn = RW_MGR_MEM_DQ_PER_READ_DQS; (g < RW_MGR_MEM_IF_READ_DQS_WIDTH) && found; g++, test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) { + //USER Set the VFIFO + v = 0; + for (i = 0; i < final_v_setting; i++) { + rw_mgr_incr_vfifo_all (g, &v); + } + + //USER Set the proper phase + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, g); + scc_mgr_set_dqs_en_phase_all_ranks(g, final_d_setting); + + //USER Verify that things worked as expected + if(!rw_mgr_mem_calibrate_read_test_all_ranks (g, 1, PASS_ONE_BIT, &bit_chk, 0)) { + //USER Fail + found = 0; + } + } + + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, 0); + return found; +} + +#endif +#endif + +#if DYNAMIC_CALIBRATION_MODE || STATIC_FULL_CALIBRATION + +#if NEWVERSION_GW + +//USER VFIFO Calibration -- Full Calibration +alt_u32 rw_mgr_mem_calibrate_vfifo (alt_u32 read_group, alt_u32 test_bgn) +{ + alt_u32 p, d, rank_bgn, sr; + alt_u32 dtaps_per_ptap; + alt_u32 tmp_delay; + t_btfld bit_chk; + alt_u32 grp_calibrated; + alt_u32 write_group, write_test_bgn; + alt_u32 failed_substage; + alt_u32 dqs_in_dtaps, orig_start_dqs; + + TRACE_FUNC("%lu %lu", read_group, test_bgn); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_VFIFO); + + if (DDRX) { + write_group = read_group; + write_test_bgn = test_bgn; + } else { + write_group = read_group / (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + write_test_bgn = read_group * RW_MGR_MEM_DQ_PER_READ_DQS; + } + + // USER Determine number of delay taps for each phase tap + dtaps_per_ptap = 0; + tmp_delay = 0; + if (!QDRII) { + while (tmp_delay < IO_DELAY_PER_OPA_TAP) { + dtaps_per_ptap++; + tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP; + } + dtaps_per_ptap--; + tmp_delay = 0; + } + + //USER update info for sims + + reg_file_set_group(read_group); + + grp_calibrated = 0; + + reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ); + failed_substage = CAL_SUBSTAGE_GUARANTEED_READ; + + for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d+=2) { + + if (DDRX || RLDRAMX) { + // In RLDRAMX we may be messing the delay of pins in the same write group but outside of + // the current read group, but that's ok because we haven't calibrated the output side yet. + if (d > 0) { + scc_mgr_apply_group_all_out_delay_add_all_ranks (write_group, write_test_bgn, d); + } + } + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) { + //USER set a particular dqdqs phase + if (DDRX) { + scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p); + } + + //USER Previous iteration may have failed as a result of ck/dqs or ck/dk violation, + //USER in which case the device may require special recovery. + if (DDRX || RLDRAMX) { + if (d != 0 || p != 0) { + recover_mem_device_after_ck_dqs_violation(); + } + } + + DPRINT(1, "calibrate_vfifo: g=%lu p=%lu d=%lu", read_group, p, d); + BFM_GBL_SET(gwrite_pos[read_group].p, p); + BFM_GBL_SET(gwrite_pos[read_group].d, d); + + //USER Load up the patterns used by read calibration using current DQDQS phase + +#if BFM_MODE + // handled by pre-initializing memory if skipping + if (bfm_gbl.bfm_skip_guaranteed_write == 0) { + rw_mgr_mem_calibrate_read_load_patterns_all_ranks (); + } +#else + rw_mgr_mem_calibrate_read_load_patterns_all_ranks (); + +#if DDRX +#if !AP_MODE + if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) { + if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks (read_group, 1, &bit_chk)) { + DPRINT(1, "Guaranteed read test failed: g=%lu p=%lu d=%lu", read_group, p, d); + break; + } + } +#endif +#endif +#endif + +#if ARRIAV || CYCLONEV + /////// + // To make DQS bypass able to calibrate more often + /////// + // Loop over different DQS in delay chains for the purpose of DQS Enable calibration finding one bit working + orig_start_dqs = READ_SCC_DQS_IN_DELAY(read_group); + for (dqs_in_dtaps = orig_start_dqs; dqs_in_dtaps <= IO_DQS_IN_DELAY_MAX && grp_calibrated == 0; dqs_in_dtaps++) { + + for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) { + + if (! param->skip_shadow_regs[sr]) { + + //USER Select shadow register set + select_shadow_regs_for_update(rank_bgn, read_group, 1); + + WRITE_SCC_DQS_IN_DELAY(read_group, dqs_in_dtaps); + scc_mgr_load_dqs (read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + } +#endif + +// case:56390 +#if 0 && ARRIAV && QDRII + // Note, much of this counts on the fact that we don't need to keep track + // of what vfifo offset we are at because incr_vfifo doesn't use it + // We also assume only a single group, and that the vfifo incrementers start at offset zero + +#define BIT(w,b) (((w) >> (b)) & 1) + { + alt_u32 prev; + alt_u32 vbase; + alt_u32 i; + + grp_calibrated = 0; + + // check every combination of vfifo relative settings + for (prev = vbase = 0; vbase < (1 << VFIFO_CONTROL_WIDTH_PER_DQS); prev=vbase, vbase++ ) { + // check each bit to see if we need to increment, decrement, or leave the corresponding vfifo alone + for (i = 0; i < VFIFO_CONTROL_WIDTH_PER_DQS; i++) { + if (BIT(vbase,i) > BIT(prev,i)) { + rw_mgr_incr_vfifo(read_group*VFIFO_CONTROL_WIDTH_PER_DQS + i,0); + } else if (BIT(vbase,i) < BIT(prev,i)) { + rw_mgr_decr_vfifo(read_group*VFIFO_CONTROL_WIDTH_PER_DQS + i,0); + } + } + if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay (write_group, read_group, test_bgn)) { + +#if ARRIAV || CYCLONEV + /////// + // To make DQS bypass able to calibrate more often + /////// + // Before doing read deskew, set DQS in back to the reserve value + WRITE_SCC_DQS_IN_DELAY(read_group, orig_start_dqs); + scc_mgr_load_dqs (read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); +#endif + + if (! rw_mgr_mem_calibrate_vfifo_center (0, write_group, read_group, test_bgn, 1)) { + // remember last failed stage + failed_substage = CAL_SUBSTAGE_VFIFO_CENTER; + } else { + grp_calibrated = 1; + } + } else { + failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; + } + if (grp_calibrated) { + break; + } + + break; // comment out for fix + + } + } +#else + grp_calibrated = 1; + if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay (write_group, read_group, test_bgn)) { + // USER Read per-bit deskew can be done on a per shadow register basis + for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) { +#if RUNTIME_CAL_REPORT + //Report print can cause a delay at each instance of rw_mgr_mem_calibrate_vfifo_center, need to re-issue guaranteed write to ensure no refresh violation + rw_mgr_mem_calibrate_read_load_patterns_all_ranks (); +#endif + //USER Determine if this set of ranks should be skipped entirely + if (! param->skip_shadow_regs[sr]) { + + //USER Select shadow register set + select_shadow_regs_for_update(rank_bgn, read_group, 1); + +#if ARRIAV || CYCLONEV + /////// + // To make DQS bypass able to calibrate more often + /////// + // Before doing read deskew, set DQS in back to the reserve value + WRITE_SCC_DQS_IN_DELAY(read_group, orig_start_dqs); + scc_mgr_load_dqs (read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); +#endif + + // If doing read after write calibration, do not update FOM now - do it then +#if READ_AFTER_WRITE_CALIBRATION + if (! rw_mgr_mem_calibrate_vfifo_center (rank_bgn, write_group, read_group, test_bgn, 1, 0)) { +#else + if (! rw_mgr_mem_calibrate_vfifo_center (rank_bgn, write_group, read_group, test_bgn, 1, 1)) { +#endif + grp_calibrated = 0; + failed_substage = CAL_SUBSTAGE_VFIFO_CENTER; + } + } + } + } else { + grp_calibrated = 0; + failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; + } +#endif +#if BFM_MODE + if (bfm_gbl.bfm_skip_guaranteed_write > 0 && !grp_calibrated) { + // This should never happen with pre-initialized guaranteed write load pattern + // unless calibration was always going to fail + DPRINT(0, "calibrate_vfifo: skip guaranteed write calibration failed"); + break; + } else if (bfm_gbl.bfm_skip_guaranteed_write == -1) { + // if skip value is -1, then we expect to fail, but we want to use + // the regular guaranteed write next time + if (grp_calibrated) { + // We shouldn't be succeeding for this test, so this is an error + DPRINT(0, "calibrate_vfifo: ERROR: skip guaranteed write == -1, but calibration passed"); + grp_calibrated = 0; + break; + } else { + DPRINT(0, "calibrate_vfifo: skip guaranteed write == -1, expected failure, trying again with no skip"); + bfm_gbl.bfm_skip_guaranteed_write = 0; + } + } + +#endif +#if ARRIAV || CYCLONEV + /////// + // To make DQS bypass able to calibrate more often + /////// + } +#endif + + } +#if BFM_MODE + if (bfm_gbl.bfm_skip_guaranteed_write && !grp_calibrated) break; +#endif + } + + if (grp_calibrated == 0) { + set_failing_group_stage(write_group, CAL_STAGE_VFIFO, failed_substage); + + return 0; + } + + //USER Reset the delay chains back to zero if they have moved > 1 (check for > 1 because loop will increase d even when pass in first case) + if (DDRX || RLDRAMII) { + if (d > 2) { + scc_mgr_zero_group(write_group, write_test_bgn, 1); + } + } + + + return 1; +} + +#else + +//USER VFIFO Calibration -- Full Calibration +alt_u32 rw_mgr_mem_calibrate_vfifo (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 p, rank_bgn, sr; + alt_u32 grp_calibrated; + alt_u32 failed_substage; + + TRACE_FUNC("%lu %lu", g, test_bgn); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_VFIFO); + + reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ); + + failed_substage = CAL_SUBSTAGE_GUARANTEED_READ; + + //USER update info for sims + + reg_file_set_group(g); + + grp_calibrated = 0; + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) { + //USER set a particular dqdqs phase + if (DDRX) { + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + } + + //USER Load up the patterns used by read calibration using current DQDQS phase + + rw_mgr_mem_calibrate_read_load_patterns_all_ranks (); +#if DDRX + if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) { + if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks (read_group, 1, &bit_chk)) { + break; + } + } +#endif + + grp_calibrated = 1; + if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay (g, g, test_bgn)) { + // USER Read per-bit deskew can be done on a per shadow register basis + for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) { + + //USER Determine if this set of ranks should be skipped entirely + if (! param->skip_shadow_regs[sr]) { + + //USER Select shadow register set + select_shadow_regs_for_update(rank_bgn, read_group, 1); + + if (! rw_mgr_mem_calibrate_vfifo_center (rank_bgn, g, test_bgn, 1)) { + grp_calibrated = 0; + failed_substage = CAL_SUBSTAGE_VFIFO_CENTER; + } + } + } + } else { + grp_calibrated = 0; + failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; + } + } + + if (grp_calibrated == 0) { + set_failing_group_stage(g, CAL_STAGE_VFIFO, failed_substage); + return 0; + } + + + return 1; +} + +#endif + +#endif + +#if READ_AFTER_WRITE_CALIBRATION +//USER VFIFO Calibration -- Read Deskew Calibration after write deskew +alt_u32 rw_mgr_mem_calibrate_vfifo_end (alt_u32 read_group, alt_u32 test_bgn) +{ + alt_u32 rank_bgn, sr; + alt_u32 grp_calibrated; + alt_u32 write_group; + + TRACE_FUNC("%lu %lu", read_group, test_bgn); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES); + reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); + + if (DDRX) { + write_group = read_group; + } else { + write_group = read_group / (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + } + + //USER update info for sims + reg_file_set_group(read_group); + + grp_calibrated = 1; + // USER Read per-bit deskew can be done on a per shadow register basis + for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) { + + //USER Determine if this set of ranks should be skipped entirely + if (! param->skip_shadow_regs[sr]) { + + //USER Select shadow register set + select_shadow_regs_for_update(rank_bgn, read_group, 1); + + // This is the last calibration round, update FOM here + if (! rw_mgr_mem_calibrate_vfifo_center (rank_bgn, write_group, read_group, test_bgn, 0, 1)) { + grp_calibrated = 0; + } + } + } + + + if (grp_calibrated == 0) { + set_failing_group_stage(write_group, CAL_STAGE_VFIFO_AFTER_WRITES, CAL_SUBSTAGE_VFIFO_CENTER); + return 0; + } + + return 1; +} +#endif + + +//USER Calibrate LFIFO to find smallest read latency + +alt_u32 rw_mgr_mem_calibrate_lfifo (void) +{ + alt_u32 found_one; + t_btfld bit_chk; + alt_u32 g; + + TRACE_FUNC(); + BFM_STAGE("lfifo"); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_LFIFO); + reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY); + + //USER Load up the patterns used by read calibration for all ranks + + rw_mgr_mem_calibrate_read_load_patterns_all_ranks (); + + found_one = 0; + + do { + IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat); + DPRINT(2, "lfifo: read_lat=%lu", gbl->curr_read_lat); + + if (!rw_mgr_mem_calibrate_read_test_all_ranks (0, NUM_READ_TESTS, PASS_ALL_BITS, &bit_chk, 1)) { + break; + } + + found_one = 1; + + //USER reduce read latency and see if things are working + //USER correctly + + gbl->curr_read_lat--; + } while (gbl->curr_read_lat > 0); + + //USER reset the fifos to get pointers to known state + + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + + if (found_one) { + //USER add a fudge factor to the read latency that was determined + gbl->curr_read_lat += 2; +#if BFM_MODE + gbl->curr_read_lat += BFM_GBL_GET(lfifo_margin); +#endif + IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat); +#if RUNTIME_CAL_REPORT + RPRINT("LFIFO Calibration ; PHY Read Latency %li", gbl->curr_read_lat); +#endif + + DPRINT(2, "lfifo: success: using read_lat=%lu", gbl->curr_read_lat); + + return 1; + } else { + set_failing_group_stage(0xff, CAL_STAGE_LFIFO, CAL_SUBSTAGE_READ_LATENCY); + + for (g = 0; g < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; g++) + { + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][g].error_stage, CAL_STAGE_LFIFO); + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][g].error_sub_stage, CAL_SUBSTAGE_READ_LATENCY); + } + + DPRINT(2, "lfifo: failed at initial read_lat=%lu", gbl->curr_read_lat); + + return 0; + } +} + +//USER issue write test command. +//USER two variants are provided. one that just tests a write pattern and another that +//USER tests datamask functionality. + +#if QDRII +void rw_mgr_mem_calibrate_write_test_issue (alt_u32 group, alt_u32 test_dm) +{ + alt_u32 quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) && ENABLE_SUPER_QUICK_CALIBRATION) || BFM_MODE; + + //USER CNTR 1 - This is used to ensure enough time elapses for read data to come back. + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x30); + + if (test_dm) { + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + if(quick_write_mode) { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x08); + } else { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x40); + } + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group) << 2, __RW_MGR_LFSR_WR_RD_DM_BANK_0); + } else { + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + if(quick_write_mode) { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x08); + } else { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x40); + } + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_LFSR_WR_RD_BANK_0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_LFSR_WR_RD_BANK_0_WAIT); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group) << 2, __RW_MGR_LFSR_WR_RD_BANK_0); + } +} +#else +void rw_mgr_mem_calibrate_write_test_issue (alt_u32 group, alt_u32 test_dm) +{ + alt_u32 mcc_instruction; + alt_u32 quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) && ENABLE_SUPER_QUICK_CALIBRATION) || BFM_MODE; + alt_u32 rw_wl_nop_cycles; + + //USER Set counter and jump addresses for the right + //USER number of NOP cycles. + //USER The number of supported NOP cycles can range from -1 to infinity + //USER Three different cases are handled: + //USER + //USER 1. For a number of NOP cycles greater than 0, the RW Mgr looping + //USER mechanism will be used to insert the right number of NOPs + //USER + //USER 2. For a number of NOP cycles equals to 0, the micro-instruction + //USER issuing the write command will jump straight to the micro-instruction + //USER that turns on DQS (for DDRx), or outputs write data (for RLD), skipping + //USER the NOP micro-instruction all together + //USER + //USER 3. A number of NOP cycles equal to -1 indicates that DQS must be turned + //USER on in the same micro-instruction that issues the write command. Then we need + //USER to directly jump to the micro-instruction that sends out the data + //USER + //USER NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters (2 and 3). One + //USER jump-counter (0) is used to perform multiple write-read operations. + //USER one counter left to issue this command in "multiple-group" mode. + +#if MULTIPLE_AFI_WLAT + rw_wl_nop_cycles = gbl->rw_wl_nop_cycles_per_group[group]; +#else + rw_wl_nop_cycles = gbl->rw_wl_nop_cycles; +#endif + + if(rw_wl_nop_cycles == -1) + { + #if DDRX + //USER CNTR 2 - We want to execute the special write operation that + //USER turns on DQS right away and then skip directly to the instruction that + //USER sends out the data. We set the counter to a large number so that the + //USER jump is always taken + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0xFF); + + //USER CNTR 3 - Not used + if(test_dm) + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP); + } + else + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_BANK_0_WL_1; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_BANK_0_DATA); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_BANK_0_NOP); + } + + #endif + } + else if(rw_wl_nop_cycles == 0) + { + #if DDRX + //USER CNTR 2 - We want to skip the NOP operation and go straight to + //USER the DQS enable instruction. We set the counter to a large number so that the + //USER jump is always taken + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0xFF); + + //USER CNTR 3 - Not used + if(test_dm) + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_DM_BANK_0; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS); + } + else + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_BANK_0; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_BANK_0_DQS); + } + #endif + + #if RLDRAMX + //USER CNTR 2 - We want to skip the NOP operation and go straight to + //USER the write data instruction. We set the counter to a large number so that the + //USER jump is always taken + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0xFF); + + //USER CNTR 3 - Not used + if(test_dm) + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_DM_BANK_0; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA); + } + else + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_BANK_0; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_BANK_0_DATA); + } + #endif + } + else + { + //USER CNTR 2 - In this case we want to execute the next instruction and NOT + //USER take the jump. So we set the counter to 0. The jump address doesn't count + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x0); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, 0x0); + + //USER CNTR 3 - Set the nop counter to the number of cycles we need to loop for, minus 1 + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, rw_wl_nop_cycles - 1); + if(test_dm) + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_DM_BANK_0; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP); + } + else + { + mcc_instruction = __RW_MGR_LFSR_WR_RD_BANK_0; + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_BANK_0_NOP); + } + } + + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + + if(quick_write_mode) { + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x08); + } else { +#if ENABLE_NON_DES_CAL + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x08); // Break this up for refresh purposes +#else + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x40); +#endif + } + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, mcc_instruction); + + //USER CNTR 1 - This is used to ensure enough time elapses for read data to come back. + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x30); + + if(test_dm) + { + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT); + } else { + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_LFSR_WR_RD_BANK_0_WAIT); + } + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group << 2), mcc_instruction); + +#if ENABLE_NON_DES_CAL + alt_u32 i = 0; + for (i=0; i < 8; i++) + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group << 2), mcc_instruction); +#endif + + + + + + + +} +#endif + +//USER Test writes, can check for a single bit pass or multiple bit pass + +alt_u32 rw_mgr_mem_calibrate_write_test (alt_u32 rank_bgn, alt_u32 write_group, alt_u32 use_dm, alt_u32 all_correct, t_btfld *bit_chk, alt_u32 all_ranks) +{ + alt_u32 r; + t_btfld correct_mask_vg; + t_btfld tmp_bit_chk; + alt_u32 vg; + alt_u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); + + *bit_chk = param->write_correct_mask; + correct_mask_vg = param->write_correct_mask_vg; + + for (r = rank_bgn; r < rank_end; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + + tmp_bit_chk = 0; + for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) { + + //USER reset the fifos to get pointers to known state + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + + tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_WRITE_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS); + rw_mgr_mem_calibrate_write_test_issue (write_group*RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg, use_dm); + + tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0))); + DPRINT(2, "write_test(%lu,%lu,%lu) :[%lu,%lu] " BTFLD_FMT " & ~%x => " BTFLD_FMT " => " BTFLD_FMT, + write_group, use_dm, all_correct, r, vg, + correct_mask_vg, IORD_32DIRECT(BASE_RW_MGR, 0), correct_mask_vg & ~IORD_32DIRECT(BASE_RW_MGR, 0), + tmp_bit_chk); + + if (vg == 0) { + break; + } + } + *bit_chk &= tmp_bit_chk; + } + + if (all_correct) + { + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + DPRINT(2, "write_test(%lu,%lu,ALL) : " BTFLD_FMT " == " BTFLD_FMT " => %lu", write_group, use_dm, + *bit_chk, param->write_correct_mask, (long unsigned int)(*bit_chk == param->write_correct_mask)); + return (*bit_chk == param->write_correct_mask); + } + else + { + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + DPRINT(2, "write_test(%lu,%lu,ONE) : " BTFLD_FMT " != " BTFLD_FMT " => %lu", write_group, use_dm, + *bit_chk, (long unsigned int)0, (long unsigned int)(*bit_chk != 0)); + return (*bit_chk != 0x00); + } +} + +static inline alt_u32 rw_mgr_mem_calibrate_write_test_all_ranks (alt_u32 write_group, alt_u32 use_dm, alt_u32 all_correct, t_btfld *bit_chk) +{ + return rw_mgr_mem_calibrate_write_test (0, write_group, use_dm, all_correct, bit_chk, 1); +} + + +//USER level the write operations + +#if DYNAMIC_CALIBRATION_MODE || STATIC_QUICK_CALIBRATION + +#if QDRII + +//USER Write Levelling -- Quick Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + TRACE_FUNC("%lu %lu", g, test_bgn); + + return 0; +} + +#endif + +#if RLDRAMX +#if !ENABLE_SUPER_QUICK_CALIBRATION + +//USER Write Levelling -- Quick Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 d; + t_btfld bit_chk; + + TRACE_FUNC("%lu %lu", g, test_bgn); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_WLEVEL); + reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); + reg_file_set_group(g); + + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + if (d > IO_IO_OUT1_DELAY_MAX) { + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); + + return 0; + } + + return 1; +} + +#else + +//USER Write Levelling -- Super Quick Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 d; + t_btfld bit_chk; + + TRACE_FUNC("%lu %lu", g, test_bgn); + + //USER The first call to this function will calibrate all groups + if (g != 0) { + return 1; + } + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_WLEVEL); + reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); + reg_file_set_group(g); + + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + if (d > IO_IO_OUT1_DELAY_MAX) { + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); + + return 0; + } + + reg_file_set_sub_stage(CAL_SUBSTAGE_WLEVEL_COPY); + + //USER Now copy the calibration settings to all other groups + for (g = 1, test_bgn = RW_MGR_MEM_DQ_PER_WRITE_DQS; g < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; g++, test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) { + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + //USER Verify that things worked as expected + if (!rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WLEVEL_COPY); + + return 0; + } + } + + return 1; +} + +#endif +#endif + +#if DDRX +#if !ENABLE_SUPER_QUICK_CALIBRATION + +//USER Write Levelling -- Quick Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 p; + t_btfld bit_chk; + + TRACE_FUNC("%lu %lu", g, test_bgn); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_WLEVEL); + reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); + + //USER maximum phases for the sweep + + //USER starting phases + + //USER update info for sims + + reg_file_set_group(g); + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) { + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + if (p > IO_DQDQS_OUT_PHASE_MAX) { + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); + + return 0; + } + + return 1; +} + +#else + +//USER Write Levelling -- Super Quick Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 p; + t_btfld bit_chk; + + TRACE_FUNC("%lu %lu", g, test_bgn); + + //USER The first call to this function will calibrate all groups + if (g != 0) { + return 1; + } + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_WLEVEL); + reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); + + //USER maximum phases for the sweep + + //USER starting phases + + //USER update info for sims + + reg_file_set_group(g); + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) { + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + if (p > IO_DQDQS_OUT_PHASE_MAX) { + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); + + return 0; + } + + reg_file_set_sub_stage(CAL_SUBSTAGE_WLEVEL_COPY); + + //USER Now copy the calibration settings to all other groups + for (g = 1, test_bgn = RW_MGR_MEM_DQ_PER_READ_DQS; (g < RW_MGR_MEM_IF_READ_DQS_WIDTH); g++, test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) { + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, g); + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + //USER Verify that things worked as expected + if (!rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WLEVEL_COPY); + + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, 0); + return 0; + } + } + + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, 0); + return 1; +} + +#endif +#endif + +#endif + +#if DYNAMIC_CALIBRATION_MODE || STATIC_FULL_CALIBRATION + +#if QDRII +//USER Write Levelling -- Full Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + TRACE_FUNC("%lu %lu", g, test_bgn); + + return 0; +} +#endif + +#if RLDRAMX +//USER Write Levelling -- Full Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 d; + t_btfld bit_chk; + alt_u32 work_bgn, work_end; + alt_u32 d_bgn, d_end; + alt_u32 found_begin; + + TRACE_FUNC("%lu %lu", g, test_bgn); + BFM_STAGE("wlevel"); + + ALTERA_ASSERT(g < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_WLEVEL); + reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); + + //USER maximum delays for the sweep + + //USER update info for sims + + reg_file_set_group(g); + + //USER starting and end range where writes work + + scc_mgr_spread_out2_delay_all_ranks (g,test_bgn); + + work_bgn = 0; + work_end = 0; + + //USER step 1: find first working dtap, increment in dtaps + found_begin = 0; + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++, work_bgn += IO_DELAY_PER_DCHAIN_TAP) { + DPRINT(2, "wlevel: begin: d=%lu", d); + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + found_begin = 1; + d_bgn = d; + break; + } else { + recover_mem_device_after_ck_dqs_violation(); + } + } + + if (!found_begin) { + //USER fail, cannot find first working delay + + DPRINT(2, "wlevel: failed to find first working delay", d); + + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); + + return 0; + } + + DPRINT(2, "wlevel: found begin d=%lu work_bgn=%lu", d_bgn, work_bgn); + BFM_GBL_SET(dqs_wlevel_left_edge[g].d,d_bgn); + BFM_GBL_SET(dqs_wlevel_left_edge[g].ps,work_bgn); + + reg_file_set_sub_stage(CAL_SUBSTAGE_LAST_WORKING_DELAY); + + //USER step 2 : find first non-working dtap, increment in dtaps + work_end = work_bgn; + d = d + 1; + for (; d <= IO_IO_OUT1_DELAY_MAX; d++, work_end += IO_DELAY_PER_DCHAIN_TAP) { + DPRINT(2, "wlevel: end: d=%lu", d); + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (!rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + recover_mem_device_after_ck_dqs_violation(); + break; + } + } + d_end = d - 1; + + if (d_end >= d_bgn) { + //USER we have a working range + } else { + //USER nil range + //Note: don't think this is possible + + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_LAST_WORKING_DELAY); + + return 0; + } + + DPRINT(2, "wlevel: found end: d=%lu work_end=%lu", d_end, work_end); + BFM_GBL_SET(dqs_wlevel_right_edge[g].d,d_end); + BFM_GBL_SET(dqs_wlevel_right_edge[g].ps,work_end); + + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[curr_shadow_reg][g].dqdqs_start, work_bgn); + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[curr_shadow_reg][g].dqdqs_end, work_end); + + + //USER center + + d = (d_end + d_bgn) / 2; + + DPRINT(2, "wlevel: found middle: d=%lu work_mid=%lu", d, (work_end + work_bgn)/2); + BFM_GBL_SET(dqs_wlevel_mid[g].d,d); + BFM_GBL_SET(dqs_wlevel_mid[g].ps,(work_end + work_bgn)/2); + + scc_mgr_zero_group (g, test_bgn, 1); + scc_mgr_apply_group_all_out_delay_add_all_ranks (g, test_bgn, d); + + return 1; +} +#endif + + +#if DDRX +#if NEWVERSION_WL + +//USER Write Levelling -- Full Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 p, d, sr; + +#if CALIBRATE_BIT_SLIPS +#if QUARTER_RATE_MODE + alt_32 num_additional_fr_cycles = 3; +#elif HALF_RATE_MODE + alt_32 num_additional_fr_cycles = 1; +#else + alt_32 num_additional_fr_cycles = 0; +#endif +#if MULTIPLE_AFI_WLAT + num_additional_fr_cycles++; +#endif +#else + alt_u32 num_additional_fr_cycles = 0; +#endif + + t_btfld bit_chk; + alt_u32 work_bgn, work_end, work_mid; + alt_u32 tmp_delay; + alt_u32 found_begin; + alt_u32 dtaps_per_ptap; + + TRACE_FUNC("%lu %lu", g, test_bgn); + BFM_STAGE("wlevel"); + + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_WLEVEL); + reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); + + //USER maximum phases for the sweep + +#if USE_DQS_TRACKING +#if HHP_HPS + dtaps_per_ptap = IORD_32DIRECT(REG_FILE_DTAPS_PER_PTAP, 0); +#else + dtaps_per_ptap = IORD_32DIRECT(TRK_DTAPS_PER_PTAP, 0); +#endif +#else + dtaps_per_ptap = 0; + tmp_delay = 0; + while (tmp_delay < IO_DELAY_PER_OPA_TAP) { + dtaps_per_ptap++; + tmp_delay += IO_DELAY_PER_DCHAIN_TAP; + } + dtaps_per_ptap--; + tmp_delay = 0; +#endif + + //USER starting phases + + //USER update info for sims + + reg_file_set_group(g); + + //USER starting and end range where writes work + + scc_mgr_spread_out2_delay_all_ranks (g,test_bgn); + + work_bgn = 0; + work_end = 0; + + //USER step 1: find first working phase, increment in ptaps, and then in dtaps if ptaps doesn't find a working phase + found_begin = 0; + tmp_delay = 0; + for (d = 0; d <= dtaps_per_ptap; d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) { + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + work_bgn = tmp_delay; + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles*IO_DLL_CHAIN_LENGTH; p++, work_bgn += IO_DELAY_PER_OPA_TAP) { + DPRINT(2, "wlevel: begin-1: p=%lu d=%lu", p, d); + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + found_begin = 1; + break; + } + } + + if (found_begin) { + break; + } + } + + if (p > IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles*IO_DLL_CHAIN_LENGTH) { + //USER fail, cannot find first working phase + + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); + + return 0; + } + + DPRINT(2, "wlevel: first valid p=%lu d=%lu", p, d); + + reg_file_set_sub_stage(CAL_SUBSTAGE_LAST_WORKING_DELAY); + + //USER If d is 0 then the working window covers a phase tap and we can follow the old procedure + //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end + if (d == 0) { + COV(WLEVEL_PHASE_PTAP_OVERLAP); + work_end = work_bgn + IO_DELAY_PER_OPA_TAP; + + //USER step 2: if we have room, back off by one and increment in dtaps + + if (p > 0) { +#ifdef BFM_MODE + int found = 0; +#endif + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1); + + tmp_delay = work_bgn - IO_DELAY_PER_OPA_TAP; + + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_bgn; d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) { + DPRINT(2, "wlevel: begin-2: p=%lu d=%lu", (p-1), d); + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { +#ifdef BFM_MODE + found = 1; +#endif + work_bgn = tmp_delay; + break; + } + } + +#ifdef BFM_MODE + { + alt_u32 d2; + alt_u32 p2; + if (found) { + d2 = d; + p2 = p - 1; + } else { + d2 = 0; + p2 = p; + } + + DPRINT(2, "wlevel: found begin-A: p=%lu d=%lu ps=%lu", p2, d2, work_bgn); + + BFM_GBL_SET(dqs_wlevel_left_edge[g].p,p2); + BFM_GBL_SET(dqs_wlevel_left_edge[g].d,d2); + BFM_GBL_SET(dqs_wlevel_left_edge[g].ps,work_bgn); + } +#endif + + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, 0); + } else { + DPRINT(2, "wlevel: found begin-B: p=%lu d=%lu ps=%lu", p, d, work_bgn); + + BFM_GBL_SET(dqs_wlevel_left_edge[g].p,p); + BFM_GBL_SET(dqs_wlevel_left_edge[g].d,d); + BFM_GBL_SET(dqs_wlevel_left_edge[g].ps,work_bgn); + } + + //USER step 3: go forward from working phase to non working phase, increment in ptaps + + for (p = p + 1; p <= IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles*IO_DLL_CHAIN_LENGTH; p++, work_end += IO_DELAY_PER_OPA_TAP) { + DPRINT(2, "wlevel: end-0: p=%lu d=%lu", p, (long unsigned int)0); + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + if (!rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + //USER step 4: back off one from last, increment in dtaps + //USER The actual increment is done outside the if/else statement since it is shared with other code + + p = p - 1; + + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + work_end -= IO_DELAY_PER_OPA_TAP; + d = 0; + + } else { + //USER step 5: Window doesn't cover phase tap, just increment dtaps until failure + //USER The actual increment is done outside the if/else statement since it is shared with other code + COV(WLEVEL_PHASE_PTAP_NO_OVERLAP); + work_end = work_bgn; + DPRINT(2, "wlevel: found begin-C: p=%lu d=%lu ps=%lu", p, d, work_bgn); + BFM_GBL_SET(dqs_wlevel_left_edge[g].p,p); + BFM_GBL_SET(dqs_wlevel_left_edge[g].d,d); + BFM_GBL_SET(dqs_wlevel_left_edge[g].ps,work_bgn); + + } + + //USER The actual increment until failure + for (; d <= IO_IO_OUT1_DELAY_MAX; d++, work_end += IO_DELAY_PER_DCHAIN_TAP) { + DPRINT(2, "wlevel: end: p=%lu d=%lu", p, d); + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (!rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + scc_mgr_zero_group (g, test_bgn, 1); + + work_end -= IO_DELAY_PER_DCHAIN_TAP; + + if (work_end >= work_bgn) { + //USER we have a working range + } else { + //USER nil range + + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_LAST_WORKING_DELAY); + + return 0; + } + + DPRINT(2, "wlevel: found end: p=%lu d=%lu; range: [%lu,%lu]", p, d-1, work_bgn, work_end); + BFM_GBL_SET(dqs_wlevel_right_edge[g].p,p); + BFM_GBL_SET(dqs_wlevel_right_edge[g].d,d-1); + BFM_GBL_SET(dqs_wlevel_right_edge[g].ps,work_end); + + for(sr = 0; sr < NUM_SHADOW_REGS; sr++) { + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[sr][g].dqdqs_start, work_bgn); + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[sr][g].dqdqs_end, work_end); + } + + //USER center + + work_mid = (work_bgn + work_end) / 2; + + DPRINT(2, "wlevel: work_mid=%ld", work_mid); + + tmp_delay = 0; + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles*IO_DLL_CHAIN_LENGTH && tmp_delay < work_mid; p++, tmp_delay += IO_DELAY_PER_OPA_TAP); + + if (tmp_delay > work_mid) { + tmp_delay -= IO_DELAY_PER_OPA_TAP; + p--; + } + + while (p > IO_DQDQS_OUT_PHASE_MAX) { + tmp_delay -= IO_DELAY_PER_OPA_TAP; + p--; + } + + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + DPRINT(2, "wlevel: p=%lu tmp_delay=%lu left=%lu", p, tmp_delay, work_mid - tmp_delay); + + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_mid; d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP); + + if (tmp_delay > work_mid) { + tmp_delay -= IO_DELAY_PER_DCHAIN_TAP; + d--; + } + + DPRINT(2, "wlevel: p=%lu d=%lu tmp_delay=%lu left=%lu", p, d, tmp_delay, work_mid - tmp_delay); + + scc_mgr_apply_group_all_out_delay_add_all_ranks (g, test_bgn, d); + + DPRINT(2, "wlevel: found middle: p=%lu d=%lu", p, d); + BFM_GBL_SET(dqs_wlevel_mid[g].p,p); + BFM_GBL_SET(dqs_wlevel_mid[g].d,d); + BFM_GBL_SET(dqs_wlevel_mid[g].ps,work_mid); + + return 1; +} + + +#else + +//USER Write Levelling -- Full Calibration +alt_u32 rw_mgr_mem_calibrate_wlevel (alt_u32 g, alt_u32 test_bgn) +{ + alt_u32 p, d; + t_btfld bit_chk; + alt_u32 work_bgn, work_end, work_mid; + alt_u32 tmp_delay; + + TRACE_FUNC("%lu %lu", g, test_bgn); + + //USER update info for sims + + reg_file_set_stage(CAL_STAGE_WLEVEL); + reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); + + //USER maximum phases for the sweep + + //USER starting phases + + //USER update info for sims + + reg_file_set_group(g); + + //USER starting and end range where writes work + + work_bgn = 0; + work_end = 0; + + //USER step 1: find first working phase, increment in ptaps + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++, work_bgn += IO_DELAY_PER_OPA_TAP) { + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + if (p > IO_DQDQS_OUT_PHASE_MAX) { + //USER fail, cannot find first working phase + + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); + + return 0; + } + + work_end = work_bgn + IO_DELAY_PER_OPA_TAP; + + reg_file_set_sub_stage(CAL_SUBSTAGE_LAST_WORKING_DELAY); + + //USER step 2: if we have room, back off by one and increment in dtaps + + if (p > 0) { + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1); + + tmp_delay = work_bgn - IO_DELAY_PER_OPA_TAP; + + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_bgn; d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) { + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + work_bgn = tmp_delay; + break; + } + } + + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, 0); + } + + //USER step 3: go forward from working phase to non working phase, increment in ptaps + + for (p = p + 1; p <= IO_DQDQS_OUT_PHASE_MAX; p++, work_end += IO_DELAY_PER_OPA_TAP) { + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); + + if (!rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + //USER step 4: back off one from last, increment in dtaps + + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1); + + work_end -= IO_DELAY_PER_OPA_TAP; + + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++, work_end += IO_DELAY_PER_DCHAIN_TAP) { + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, d); + + if (!rw_mgr_mem_calibrate_write_test_all_ranks (g, 0, PASS_ONE_BIT, &bit_chk)) { + break; + } + } + + scc_mgr_apply_group_all_out_delay_all_ranks (g, test_bgn, 0); + + if (work_end > work_bgn) { + //USER we have a working range + } else { + //USER nil range + + set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_LAST_WORKING_DELAY); + + return 0; + } + + //USER center + + work_mid = (work_bgn + work_end) / 2; + + tmp_delay = 0; + + for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && tmp_delay < work_mid; p++, tmp_delay += IO_DELAY_PER_OPA_TAP); + + tmp_delay -= IO_DELAY_PER_OPA_TAP; + + scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1); + + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_mid; d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP); + + scc_mgr_apply_group_all_out_delay_add_all_ranks (g, test_bgn, d - 1); + + + return 1; +} + +#endif +#endif +#endif + +//USER center all windows. do per-bit-deskew to possibly increase size of certain windows + +#if NEWVERSION_WRDESKEW + +alt_u32 rw_mgr_mem_calibrate_writes_center (alt_u32 rank_bgn, alt_u32 write_group, alt_u32 test_bgn) +{ + alt_u32 i, p, min_index; + alt_32 d; + //USER Store these as signed since there are comparisons with signed numbers + t_btfld bit_chk; +#if QDRII + t_btfld tmp_bit_chk; + t_btfld tmp_mask; + t_btfld mask; +#endif + t_btfld sticky_bit_chk; + alt_32 left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS]; + alt_32 right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS]; + alt_32 mid; + alt_32 mid_min, orig_mid_min; + alt_32 new_dqs, start_dqs, shift_dq; +#if RUNTIME_CAL_REPORT + alt_32 new_dq[RW_MGR_MEM_DQ_PER_WRITE_DQS]; +#endif + alt_32 dq_margin, dqs_margin, dm_margin; + alt_u32 stop; + + TRACE_FUNC("%lu %lu", write_group, test_bgn); + BFM_STAGE("writes_center"); + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + dm_margin = 0; + + start_dqs = READ_SCC_DQS_IO_OUT1_DELAY(); + + select_curr_shadow_reg_using_rank(rank_bgn); + + //USER per-bit deskew + + //USER set the left and right edge of each bit to an illegal value + //USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value + sticky_bit_chk = 0; + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1; + right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1; + } + + //USER Search for the left edge of the window for each bit + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn, d); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit + stop = !rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0); + sticky_bit_chk = sticky_bit_chk | bit_chk; + stop = stop && (sticky_bit_chk == param->write_correct_mask); + DPRINT(2, "write_center(left): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT " && %lu [bit_chk=" BTFLD_FMT "]", + d, sticky_bit_chk, param->write_correct_mask, stop, bit_chk); + + if (stop == 1) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + if (bit_chk & 1) { + //USER Remember a passing test as the left_edge + left_edge[i] = d; + } else { + //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge + if (left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { + right_edge[i] = -(d + 1); + } + } + DPRINT(2, "write_center[l,d=%lu): bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld", + d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]); + bit_chk = bit_chk >> 1; + } + } + } + + //USER Reset DQ delay chains to 0 + scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn, 0); + sticky_bit_chk = 0; + for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) { + + DPRINT(2, "write_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i], i, right_edge[i]); + + //USER Check for cases where we haven't found the left edge, which makes our assignment of the the + //USER right edge invalid. Reset it to the illegal value. + if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) && (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) { + right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1; + DPRINT(2, "write_center: reset right_edge[%lu]: %ld", i, right_edge[i]); + } + + //USER Reset sticky bit (except for bits where we have seen the left edge) + sticky_bit_chk = sticky_bit_chk << 1; + if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) { + sticky_bit_chk = sticky_bit_chk | 1; + } + + if (i == 0) + { + break; + } + } + + //USER Search for the right edge of the window for each bit + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) { + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d + start_dqs); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + + //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit + stop = !rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0); + if (stop) { + recover_mem_device_after_ck_dqs_violation(); + } + sticky_bit_chk = sticky_bit_chk | bit_chk; + stop = stop && (sticky_bit_chk == param->write_correct_mask); + + DPRINT(2, "write_center (right): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT " && %lu", d, sticky_bit_chk, param->write_correct_mask, stop); + + if (stop == 1) { + if (d == 0) { + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + //USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1 + if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1 && left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1) { + right_edge[i] = -1; + } + } + } + break; + } else { + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + if (bit_chk & 1) { + //USER Remember a passing test as the right_edge + right_edge[i] = d; + } else { + if (d != 0) { + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { + left_edge[i] = -(d + 1); + } + } else { + //USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1 + if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1 && left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1) { + right_edge[i] = -1; + } + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + else if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { + left_edge[i] = -(d + 1); + } + } + } + DPRINT(2, "write_center[r,d=%lu): bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld", + d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]); + bit_chk = bit_chk >> 1; + } + } + } + +#if ENABLE_TCL_DEBUG + // Store all observed margins + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + alt_u32 dq = write_group*RW_MGR_MEM_DQ_PER_WRITE_DQS + i; + + ALTERA_ASSERT(dq < RW_MGR_MEM_DATA_WIDTH); + + TCLRPT_SET(debug_cal_report->cal_dq_out_margins[curr_shadow_reg][dq].left_edge, left_edge[i]); + TCLRPT_SET(debug_cal_report->cal_dq_out_margins[curr_shadow_reg][dq].right_edge, right_edge[i]); + } +#endif + + //USER Check that all bits have a window + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + DPRINT(2, "write_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i], i, right_edge[i]); + BFM_GBL_SET(dq_write_left_edge[write_group][i],left_edge[i]); + BFM_GBL_SET(dq_write_right_edge[write_group][i],right_edge[i]); + if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) || (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) { + set_failing_group_stage(test_bgn + i, CAL_STAGE_WRITES, CAL_SUBSTAGE_WRITES_CENTER); + return 0; + } + } + + //USER Find middle of window for each DQ bit + mid_min = left_edge[0] - right_edge[0]; + min_index = 0; + for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + mid = left_edge[i] - right_edge[i]; + if (mid < mid_min) { + mid_min = mid; + min_index = i; + } + } + + //USER -mid_min/2 represents the amount that we need to move DQS. If mid_min is odd and positive we'll need to add one to + //USER make sure the rounding in further calculations is correct (always bias to the right), so just add 1 for all positive values + if (mid_min > 0) { + mid_min++; + } + mid_min = mid_min / 2; + + DPRINT(1, "write_center: mid_min=%ld", mid_min); + + //USER Determine the amount we can change DQS (which is -mid_min) + orig_mid_min = mid_min; +#if ENABLE_DQS_OUT_CENTERING + if (DDRX || RLDRAMX) { + new_dqs = start_dqs - mid_min; + DPRINT(2, "write_center: new_dqs(1)=%ld", new_dqs); + if (new_dqs > IO_IO_OUT1_DELAY_MAX) { + new_dqs = IO_IO_OUT1_DELAY_MAX; + } else if (new_dqs < 0) { + new_dqs = 0; + } + mid_min = start_dqs - new_dqs; + + new_dqs = start_dqs - mid_min; + } else { + new_dqs = start_dqs; + mid_min = 0; + } +#else + new_dqs = start_dqs; + mid_min = 0; +#endif + + DPRINT(1, "write_center: start_dqs=%ld new_dqs=%ld mid_min=%ld", start_dqs, new_dqs, mid_min); + + //USER Initialize data for export structures + dqs_margin = IO_IO_OUT1_DELAY_MAX + 1; + dq_margin = IO_IO_OUT1_DELAY_MAX + 1; + + //USER add delay to bring centre of all DQ windows to the same "level" + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { + //USER Use values before divide by 2 to reduce round off error + shift_dq = (left_edge[i] - right_edge[i] - (left_edge[min_index] - right_edge[min_index]))/2 + (orig_mid_min - mid_min); + + DPRINT(2, "write_center: before: shift_dq[%lu]=%ld", i, shift_dq); + + if (shift_dq + (alt_32)READ_SCC_DQ_OUT1_DELAY(i) > (alt_32)IO_IO_OUT1_DELAY_MAX) { + shift_dq = (alt_32)IO_IO_OUT1_DELAY_MAX - READ_SCC_DQ_OUT1_DELAY(i); + } else if (shift_dq + (alt_32)READ_SCC_DQ_OUT1_DELAY(i) < 0) { + shift_dq = -(alt_32)READ_SCC_DQ_OUT1_DELAY(i); + } +#if RUNTIME_CAL_REPORT + new_dq[i] = shift_dq; +#endif + DPRINT(2, "write_center: after: shift_dq[%lu]=%ld", i, shift_dq); + scc_mgr_set_dq_out1_delay(write_group, i, READ_SCC_DQ_OUT1_DELAY(i) + shift_dq); + scc_mgr_load_dq (i); + + DPRINT(2, "write_center: margin[%lu]=[%ld,%ld]", i, + left_edge[i] - shift_dq + (-mid_min), + right_edge[i] + shift_dq - (-mid_min)); + //USER To determine values for export structures + if (left_edge[i] - shift_dq + (-mid_min) < dq_margin) { + dq_margin = left_edge[i] - shift_dq + (-mid_min); + } + if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin) { + dqs_margin = right_edge[i] + shift_dq - (-mid_min); + } + } + + //USER Move DQS + if (QDRII) { + scc_mgr_set_group_dqs_io_and_oct_out1_gradual (write_group, new_dqs); + } else { + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, new_dqs); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + +#if RUNTIME_CAL_REPORT + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { + RPRINT("Write Deskew ; DQ %2lu ; Rank %lu ; Left edge %3li ; Right edge %3li ; DQ delay %2li ; DQS delay %2li", write_group*RW_MGR_MEM_DQ_PER_WRITE_DQS + i, rank_bgn, left_edge[i], right_edge[i], new_dq[i], new_dqs); + } +#endif + + + ////////////////////// + ////////////////////// + //USER Centre DM + ////////////////////// + ////////////////////// + + BFM_STAGE("dm_center"); + + DPRINT(2, "write_center: DM"); + +#if RLDRAMX + + //Note: this is essentially the same as DDR with the exception of the dm_ global accounting + + //USER Determine if first group in device to initialize left and right edges + if (!is_write_group_enabled_for_dm(write_group)) + { + DPRINT(2, "dm_calib: skipping since not last in group"); + } + else + { + + // last in the group, so we need to do DM + DPRINT(2, "dm_calib: calibrating DM since last in group"); + + //USER set the left and right edge of each bit to an illegal value + //USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value + left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1; + right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1; + + sticky_bit_chk = 0; + //USER Search for the left edge of the window for the DM bit + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_dm_out1_delay (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + //USER Stop searching when the write test doesn't pass AND when we've seen a passing write before + if (rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) { + DPRINT(2, "dm_calib: left=%lu passed", d); + left_edge[0] = d; + } else { + DPRINT(2, "dm_calib: left=%lu failed", d); + //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge + if (left_edge[0] == IO_IO_OUT1_DELAY_MAX + 1) { + right_edge[0] = -(d + 1); + } else { + //USER left edge has been seen, so this failure marks the left edge, and we are done + break; + } + } + DPRINT(2, "dm_calib[l,d=%lu]: left_edge: %ld right_edge: %ld", + d, left_edge[0], right_edge[0]); + } + + DPRINT(2, "dm_calib left done: left_edge: %ld right_edge: %ld", + left_edge[0], right_edge[0]); + + //USER Reset DM delay chains to 0 + scc_mgr_apply_group_dm_out1_delay (write_group, 0); + + //USER Check for cases where we haven't found the left edge, which makes our assignment of the the + //USER right edge invalid. Reset it to the illegal value. + if ((left_edge[0] == IO_IO_OUT1_DELAY_MAX + 1) && (right_edge[0] != IO_IO_OUT1_DELAY_MAX + 1)) { + right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1; + DPRINT(2, "dm_calib: reset right_edge: %ld", right_edge[0]); + } + + //USER Search for the right edge of the window for the DM bit + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d++) { + // Note: This only shifts DQS, so are we limiting ourselve to + // width of DQ unnecessarily + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d + new_dqs); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + //USER Stop searching when the test fails and we've seen passing test already + if (rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) { + DPRINT(2, "dm_calib: right=%lu passed", d); + right_edge[0] = d; + } else { + recover_mem_device_after_ck_dqs_violation(); + + DPRINT(2, "dm_calib: right=%lu failed", d); + if (d != 0) { + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + if (right_edge[0] == IO_IO_OUT1_DELAY_MAX + 1) { + left_edge[0] = -(d + 1); + } else { + break; + } + } else { + //USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1 + if (right_edge[0] == IO_IO_OUT1_DELAY_MAX + 1 && left_edge[0] != IO_IO_OUT1_DELAY_MAX + 1) { + right_edge[0] = -1; + // we're done + break; + } + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + else if (right_edge[0] == IO_IO_OUT1_DELAY_MAX + 1) { + left_edge[0] = -(d + 1); + } + } + } + DPRINT(2, "dm_calib[l,d=%lu]: left_edge: %ld right_edge: %ld", + d, left_edge[0], right_edge[0]); + } + + DPRINT(2, "dm_calib: left=%ld right=%ld", left_edge[0], right_edge[0]); +#if BFM_MODE + // need to update for all groups covered by this dm + for (i = write_group+1-(RW_MGR_MEM_IF_WRITE_DQS_WIDTH/RW_MGR_MEM_DATA_MASK_WIDTH); i <= write_group; i++) + { + DPRINT(3, "dm_calib: left[%d]=%ld right[%d]=%ld", i, left_edge[0], i, right_edge[0]); + BFM_GBL_SET(dm_left_edge[i][0],left_edge[0]); + BFM_GBL_SET(dm_right_edge[i][0],right_edge[0]); + } +#endif + + //USER Move DQS (back to orig) + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, new_dqs); + + //USER move DM + //USER Find middle of window for the DM bit + mid = (left_edge[0] - right_edge[0]) / 2; + if (mid < 0) { + mid = 0; + } + scc_mgr_apply_group_dm_out1_delay (write_group, mid); + + dm_margin = left_edge[0]; + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + DPRINT(2, "dm_calib: left=%ld right=%ld mid=%ld dm_margin=%ld", + left_edge[0], right_edge[0], mid, dm_margin); + } // end of DM calibration +#endif + + +#if DDRX + //USER set the left and right edge of each bit to an illegal value + //USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value + left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1; + right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1; + alt_32 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1; + alt_32 end_curr = IO_IO_OUT1_DELAY_MAX + 1; + alt_32 bgn_best = IO_IO_OUT1_DELAY_MAX + 1; + alt_32 end_best = IO_IO_OUT1_DELAY_MAX + 1; + alt_32 win_best = 0; + + //USER Search for the/part of the window with DM shift + for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d-=DELTA_D) { + scc_mgr_apply_group_dm_out1_delay (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + if (rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) { + + //USE Set current end of the window + end_curr = -d; + //USER If a starting edge of our window has not been seen this is our current start of the DM window + if(bgn_curr == IO_IO_OUT1_DELAY_MAX + 1){ + bgn_curr = -d; + } + + //USER If current window is bigger than best seen. Set best seen to be current window + if((end_curr-bgn_curr+1) > win_best ){ + win_best = end_curr-bgn_curr+1; + bgn_best = bgn_curr; + end_best = end_curr; + } + } else { + //USER We just saw a failing test. Reset temp edge + bgn_curr=IO_IO_OUT1_DELAY_MAX + 1; + end_curr=IO_IO_OUT1_DELAY_MAX + 1; + } + + + } + + + //USER Reset DM delay chains to 0 + scc_mgr_apply_group_dm_out1_delay (write_group, 0); + + //USER Check to see if the current window nudges up aganist 0 delay. If so we need to continue the search by shifting DQS otherwise DQS search begins as a new search + if(end_curr!=0) { + bgn_curr=IO_IO_OUT1_DELAY_MAX + 1; + end_curr=IO_IO_OUT1_DELAY_MAX + 1; + } + + //USER Search for the/part of the window with DQS shifts + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d+=DELTA_D) { + // Note: This only shifts DQS, so are we limiting ourselve to + // width of DQ unnecessarily + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d + new_dqs); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + if (rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) { + + //USE Set current end of the window + end_curr = d; + //USER If a beginning edge of our window has not been seen this is our current begin of the DM window + if(bgn_curr == IO_IO_OUT1_DELAY_MAX + 1){ + bgn_curr = d; + } + + //USER If current window is bigger than best seen. Set best seen to be current window + if((end_curr-bgn_curr+1) > win_best){ + win_best = end_curr-bgn_curr+1; + bgn_best = bgn_curr; + end_best = end_curr; + } + } else { + //USER We just saw a failing test. Reset temp edge + recover_mem_device_after_ck_dqs_violation(); + bgn_curr = IO_IO_OUT1_DELAY_MAX + 1; + end_curr = IO_IO_OUT1_DELAY_MAX + 1; + + //USER Early exit optimization: if ther remaining delay chain space is less than already seen largest window we can exit + if((win_best-1) > (IO_IO_OUT1_DELAY_MAX - new_dqs - d)){ + break; + } + + } + } + + //USER assign left and right edge for cal and reporting; + left_edge[0] = -1*bgn_best; + right_edge[0] = end_best; + + DPRINT(2, "dm_calib: left=%ld right=%ld", left_edge[0], right_edge[0]); + BFM_GBL_SET(dm_left_edge[write_group][0],left_edge[0]); + BFM_GBL_SET(dm_right_edge[write_group][0],right_edge[0]); + + //USER Move DQS (back to orig) + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, new_dqs); + + //USER Move DM + + //USER Find middle of window for the DM bit + mid = (left_edge[0] - right_edge[0]) / 2; + + //USER only move right, since we are not moving DQS/DQ + if (mid < 0) { + mid = 0; + } + + //dm_marign should fail if we never find a window + if(win_best==0){ + dm_margin = -1; + }else{ + dm_margin = left_edge[0] - mid; + } + + + + scc_mgr_apply_group_dm_out1_delay(write_group, mid); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + DPRINT(2, "dm_calib: left=%ld right=%ld mid=%ld dm_margin=%ld", + left_edge[0], right_edge[0], mid, dm_margin); +#endif + +#if QDRII + sticky_bit_chk = 0; + + //USER set the left and right edge of each bit to an illegal value + //USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + left_edge[i] = right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1; + } + + mask = param->dm_correct_mask; + + //USER Search for the left edge of the window for the DM bit + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_dm_out1_delay (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + //USER Stop searching when the read test doesn't pass for all bits (as they've already been calibrated) + stop = !rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ONE_BIT, &bit_chk, 0); + DPRINT(2, "dm_calib[l,d=%lu] stop=%ld bit_chk=%llx sticky_bit_chk=%llx mask=%llx", + d, stop, bit_chk, sticky_bit_chk, param->write_correct_mask); + tmp_bit_chk = bit_chk; + tmp_mask = mask; + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + if ( (tmp_bit_chk & mask) == mask ) { + sticky_bit_chk = sticky_bit_chk | tmp_mask; + } + tmp_bit_chk = tmp_bit_chk >> (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH); + tmp_mask = tmp_mask << (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH); + } + stop = stop && (sticky_bit_chk == param->write_correct_mask); + + if (stop == 1) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + DPRINT(2, "dm_calib[l,i=%lu] d=%lu bit_chk&dm_mask=" BTFLD_FMT " == " BTFLD_FMT, i, d, + bit_chk & mask, mask); + if ((bit_chk & mask) == mask) { + DPRINT(2, "dm_calib: left[%lu]=%lu", i, d); + left_edge[i] = d; + } else { + //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge + if (left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { + right_edge[i] = -(d + 1); + } + } + bit_chk = bit_chk >> (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH); + } + } + } + + //USER Reset DM delay chains to 0 + scc_mgr_apply_group_dm_out1_delay (write_group, 0); + + //USER Check for cases where we haven't found the left edge, which makes our assignment of the the + //USER right edge invalid. Reset it to the illegal value. + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) && (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) { + right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1; + DPRINT(2, "dm_calib: reset right_edge: %d", right_edge[i]); + } + } + + //USER Search for the right edge of the window for the DM bit + for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d++) { + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d + new_dqs); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + rw_mgr_mem_dll_lock_wait(); + + //USER Stop searching when the read test doesn't pass for all bits (as they've already been calibrated) + stop = !rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ONE_BIT, &bit_chk, 0); + DPRINT(2, "dm_calib[l,d=%lu] stop=%ld bit_chk=%llx sticky_bit_chk=%llx mask=%llx", + d, stop, bit_chk, sticky_bit_chk, param->write_correct_mask); + tmp_bit_chk = bit_chk; + tmp_mask = mask; + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + if ( (tmp_bit_chk & mask) == mask ) { + sticky_bit_chk = sticky_bit_chk | tmp_mask; + } + tmp_bit_chk = tmp_bit_chk >> (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH); + tmp_mask = tmp_mask << (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH); + } + stop = stop && (sticky_bit_chk == param->write_correct_mask); + + if (stop == 1) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + DPRINT(2, "dm_calib[r,i=%lu] d=%lu bit_chk&dm_mask=" BTFLD_FMT " == " BTFLD_FMT, i, d, + bit_chk & mask, mask); + if ((bit_chk & mask) == mask) { + right_edge[i] = d; + } else { + //USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1 + if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1 && left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1) { + right_edge[i] = -1; + // we're done + break; + } + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + else if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { + left_edge[i] = -(d + 1); + } + } + bit_chk = bit_chk >> (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH); + } + } + } + + //USER Move DQS (back to orig) + scc_mgr_set_group_dqs_io_and_oct_out1_gradual (write_group, new_dqs); + + //USER Move DM + dm_margin = IO_IO_OUT1_DELAY_MAX; + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + //USER Find middle of window for the DM bit + mid = (left_edge[i] - right_edge[i]) / 2; + DPRINT(2, "dm_calib[mid,i=%lu] left=%ld right=%ld mid=%ld", i, left_edge[i], right_edge[i], mid); + BFM_GBL_SET(dm_left_edge[write_group][i],left_edge[i]); + BFM_GBL_SET(dm_right_edge[write_group][i],right_edge[i]); + if (mid < 0) { + mid = 0; + } + scc_mgr_set_dm_out1_delay(write_group, i, mid); + scc_mgr_load_dm (i); + if ((left_edge[i] - mid) < dm_margin) { + dm_margin = left_edge[i] - mid; + } + } +#endif + + // Store observed DM margins +#if RLDRAMX + if (is_write_group_enabled_for_dm(write_group)) + { + TCLRPT_SET(debug_cal_report->cal_dm_margins[curr_shadow_reg][write_group][0].left_edge, left_edge[0]); + TCLRPT_SET(debug_cal_report->cal_dm_margins[curr_shadow_reg][write_group][0].right_edge, right_edge[0]); + } +#else + for (i = 0; i < RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP; i++) { + TCLRPT_SET(debug_cal_report->cal_dm_margins[curr_shadow_reg][write_group][i].left_edge, left_edge[i]); + TCLRPT_SET(debug_cal_report->cal_dm_margins[curr_shadow_reg][write_group][i].right_edge, right_edge[i]); + } +#endif + +#if RUNTIME_CAL_REPORT + for (i = 0; i < RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP; i++) { + RPRINT("DM Deskew ; Group %lu ; Left edge %3li; Right edge %3li; DM delay %2li", write_group, left_edge[i], right_edge[i], mid); + } +#endif + + //USER Export values + gbl->fom_out += dq_margin + dqs_margin; + + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[curr_shadow_reg][write_group].dqs_margin, dqs_margin); + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[curr_shadow_reg][write_group].dq_margin, dq_margin); + +#if RLDRAMX + if (is_write_group_enabled_for_dm(write_group)) + { + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[curr_shadow_reg][write_group].dm_margin, dm_margin); + } +#else + TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[curr_shadow_reg][write_group].dm_margin, dm_margin); +#endif + TCLRPT_SET(debug_summary_report->fom_out, debug_summary_report->fom_out + (dq_margin + dqs_margin)); + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][write_group].fom_out, (dq_margin + dqs_margin)); + + DPRINT(2, "write_center: dq_margin=%ld dqs_margin=%ld dm_margin=%ld", dq_margin, dqs_margin, dm_margin); + + //USER Do not remove this line as it makes sure all of our decisions have been applied + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0); +} + +#else // !NEWVERSION_WRDESKEW + +alt_u32 rw_mgr_mem_calibrate_writes_center (alt_u32 rank_bgn, alt_u32 write_group, alt_u32 test_bgn) +{ + alt_u32 i, p, d; + alt_u32 mid; + t_btfld bit_chk, sticky_bit_chk; + alt_u32 max_working_dq[RW_MGR_MEM_DQ_PER_WRITE_DQS]; + alt_u32 max_working_dm[RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; + alt_u32 dq_margin, dqs_margin, dm_margin; + alt_u32 start_dqs; + alt_u32 stop; + + TRACE_FUNC("%lu %lu", write_group, test_bgn); + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + //USER per-bit deskew + + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + max_working_dq[i] = 0; + } + + for (d = 1; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn, d); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + if (!rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0)) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + if (bit_chk & 1) { + max_working_dq[i] = d; + } + bit_chk = bit_chk >> 1; + } + } + } + + scc_mgr_apply_group_dq_out1_delay (write_group, test_bgn, 0); + + //USER determine minimum of maximums + + dq_margin = IO_IO_OUT1_DELAY_MAX; + + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + if (max_working_dq[i] < dq_margin) { + dq_margin = max_working_dq[i]; + } + } + + //USER add delay to center DQ windows + + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { + if (max_working_dq[i] > dq_margin) { + scc_mgr_set_dq_out1_delay(write_group, i, max_working_dq[i] - dq_margin); + } else { + scc_mgr_set_dq_out1_delay(write_group, i, 0); + } + + scc_mgr_load_dq (p, i); + } + + //USER sweep DQS window, may potentially have more window due to per-bit-deskew + + start_dqs = READ_SCC_DQS_IO_OUT1_DELAY(); + + for (d = start_dqs + 1; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, d); + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + + if (!rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ALL_BITS, &bit_chk, 0)) { + break; + } + } + + scc_mgr_set_dqs_out1_delay(write_group, start_dqs); + scc_mgr_set_oct_out1_delay(write_group, start_dqs); + + dqs_margin = d - start_dqs - 1; + + //USER time to center, +1 so that we don't go crazy centering DQ + + mid = (dq_margin + dqs_margin + 1) / 2; + + gbl->fom_out += dq_margin + dqs_margin; + TCLRPT_SET(debug_summary_report->fom_out, debug_summary_report->fom_out + (dq_margin + dqs_margin)); + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][grp].fom_out, (dq_margin + dqs_margin)); + +#if ENABLE_DQS_OUT_CENTERING + //USER center DQS ... if the headroom is setup properly we shouldn't need to + if (DDRX) { + if (dqs_margin > mid) { + scc_mgr_set_dqs_out1_delay(write_group, READ_SCC_DQS_IO_OUT1_DELAY() + dqs_margin - mid); + scc_mgr_set_oct_out1_delay(write_group, READ_SCC_OCT_OUT1_DELAY(write_group) + dqs_margin - mid); + } + } +#endif + + scc_mgr_load_dqs_io (); + scc_mgr_load_dqs_for_write_group (write_group); + + //USER center dq + + if (dq_margin > mid) { + for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { + scc_mgr_set_dq_out1_delay(write_group, i, READ_SCC_DQ_OUT1_DELAY(i) + dq_margin - mid); + scc_mgr_load_dq (p, i); + } + dqs_margin += dq_margin - mid; + dq_margin -= dq_margin - mid; + } + + //USER do dm centering + + if (!RLDRAMX) { + dm_margin = IO_IO_OUT1_DELAY_MAX; + + if (QDRII) { + sticky_bit_chk = 0; + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + max_working_dm[i] = 0; + } + } + + for (d = 1; d <= IO_IO_OUT1_DELAY_MAX; d++) { + scc_mgr_apply_group_dm_out1_delay (write_group, d); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + if (DDRX) { + if (rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) { + max_working_dm[0] = d; + } else { + break; + } + } else { + stop = !rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0); + sticky_bit_chk = sticky_bit_chk | bit_chk; + stop = stop && (sticky_bit_chk == param->read_correct_mask); + + if (stop == 1) { + break; + } else { + for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + if ((bit_chk & param->dm_correct_mask) == param->dm_correct_mask) { + max_working_dm[i] = d; + } + bit_chk = bit_chk >> (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH); + } + } + } + } + + i = 0; + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { + if (max_working_dm[i] > mid) { + scc_mgr_set_dm_out1_delay(write_group, i, max_working_dm[i] - mid); + } else { + scc_mgr_set_dm_out1_delay(write_group, i, 0); + } + + scc_mgr_load_dm (i); + + if (max_working_dm[i] < dm_margin) { + dm_margin = max_working_dm[i]; + } + } + } else { + dm_margin = 0; + } + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + return (dq_margin + dqs_margin) > 0; +} + +#endif + +//USER calibrate the write operations + +alt_u32 rw_mgr_mem_calibrate_writes (alt_u32 rank_bgn, alt_u32 g, alt_u32 test_bgn) +{ + //USER update info for sims + + TRACE_FUNC("%lu %lu", g, test_bgn); + + reg_file_set_stage(CAL_STAGE_WRITES); + reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER); + + //USER starting phases + + //USER update info for sims + + reg_file_set_group(g); + + if (!rw_mgr_mem_calibrate_writes_center (rank_bgn, g, test_bgn)) { + set_failing_group_stage(g, CAL_STAGE_WRITES, CAL_SUBSTAGE_WRITES_CENTER); + return 0; + } + + + return 1; +} + +// helpful for creating eye diagrams +// TODO: This is for the TCL DBG... but obviously it serves no purpose... +// Decide what to do with it! + +void rw_mgr_mem_calibrate_eye_diag_aid (void) +{ + // no longer exists +} + +// TODO: This needs to be update to properly handle the number of failures +// Right now it only checks if the write test was successful or not +alt_u32 rw_mgr_mem_calibrate_full_test (alt_u32 min_correct, t_btfld *bit_chk, alt_u32 test_dm) +{ + alt_u32 g; + alt_u32 success = 0; + alt_u32 run_groups = ~param->skip_groups; + + TRACE_FUNC("%lu %lu", min_correct, test_dm); + + for (g = 0; g < RW_MGR_MEM_IF_READ_DQS_WIDTH; g++) { + if (run_groups & ((1 << RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1)) + { + success = rw_mgr_mem_calibrate_write_test_all_ranks (g, test_dm, PASS_ALL_BITS, bit_chk); + } + run_groups = run_groups >> RW_MGR_NUM_DQS_PER_WRITE_GROUP; + } + + return success; +} + +#if ENABLE_TCL_DEBUG +// see how far we can push a particular DQ pin before complete failure on input and output sides +// NOTE: if ever executing a run_*_margining function outside of calibration context you must first issue IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 1); +void run_dq_margining (alt_u32 rank_bgn, alt_u32 write_group) +{ + alt_u32 test_num; + alt_u32 read_group; + alt_u32 read_test_bgn; + alt_u32 subdq; + alt_u32 dq; + alt_u32 delay; + alt_u32 calibrated_delay; + alt_u32 working_cnt; + t_btfld bit_chk; + t_btfld bit_chk_test = 0; + t_btfld bit_chk_mask; + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + select_curr_shadow_reg_using_rank(rank_bgn); + + // Load the read patterns + rw_mgr_mem_calibrate_read_load_patterns (rank_bgn, 0); + + // sweep input delays + for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH, read_test_bgn = 0; + read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH; + read_group++, read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) + { + + ALTERA_ASSERT(read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH); + + for (subdq = 0; subdq < RW_MGR_MEM_DQ_PER_READ_DQS; subdq++) + { + dq = read_group*RW_MGR_MEM_DQ_PER_READ_DQS + subdq; + + ALTERA_ASSERT(dq < RW_MGR_MEM_DATA_WIDTH); + + calibrated_delay = debug_cal_report->cal_dq_settings[curr_shadow_reg][dq].dq_in_delay; + + working_cnt = 0; + + bit_chk_test = 0; + + // Find the left edge + for (delay = calibrated_delay; delay <= IO_IO_IN_DELAY_MAX; delay++) + { + WRITE_SCC_DQ_IN_DELAY((subdq + read_test_bgn), delay); + scc_mgr_load_dq (subdq + read_test_bgn); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + for (test_num = 0; test_num < NUM_READ_TESTS; test_num++) + { + rw_mgr_mem_calibrate_read_test (rank_bgn, read_group, 1, PASS_ONE_BIT, &bit_chk, 0, 0); + if (test_num == 0) + { + bit_chk_test = bit_chk; + } + else + { + bit_chk_test &= bit_chk; + } + } + + // Check only the bit we are testing + bit_chk_mask = (bit_chk_test & (((t_btfld) 1) << ((t_btfld) subdq))); + if (bit_chk_mask == 0) + { + break; + } + + working_cnt++; + } + + // Restore the settings + WRITE_SCC_DQ_IN_DELAY((subdq + read_test_bgn), calibrated_delay); + scc_mgr_load_dq (subdq + read_test_bgn); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + // Store the setting + TCLRPT_SET(debug_margin_report->margin_dq_in_margins[curr_shadow_reg][dq].min_working_setting, working_cnt); + + // Find the right edge + calibrated_delay = debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][read_group].dqs_bus_in_delay; + + working_cnt = 0; + for (delay = calibrated_delay; delay <= IO_DQS_IN_DELAY_MAX; delay++) + { + WRITE_SCC_DQS_IN_DELAY(read_group, delay); + scc_mgr_load_dqs(read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + for (test_num = 0; test_num < NUM_READ_TESTS; test_num++) + { + rw_mgr_mem_calibrate_read_test (rank_bgn, read_group, 1, PASS_ONE_BIT, &bit_chk, 0, 0); + if (test_num == 0) + { + bit_chk_test = bit_chk; + } + else + { + bit_chk_test &= bit_chk; + } + } + + // Check only the bit we are testing + bit_chk_mask = (bit_chk_test & (((t_btfld)1) << ((t_btfld)(subdq)))); + if (bit_chk_mask == 0) + { + break; + } + + working_cnt++; + } + + // Restore the settings + WRITE_SCC_DQS_IN_DELAY(read_group, calibrated_delay); + scc_mgr_load_dqs(read_group); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + // Store the setting + TCLRPT_SET(debug_margin_report->margin_dq_in_margins[curr_shadow_reg][dq].max_working_setting, working_cnt); + + } + } + + // sweep output delays + for (subdq = 0; subdq < RW_MGR_MEM_DQ_PER_WRITE_DQS; subdq++) + { + dq = write_group*RW_MGR_MEM_DQ_PER_WRITE_DQS + subdq; + + calibrated_delay = debug_cal_report->cal_dq_settings[curr_shadow_reg][dq].dq_out_delay1; + working_cnt = 0; + + // Find the left edge + for (delay = calibrated_delay; delay <= IO_IO_OUT1_DELAY_MAX; delay++) + { + WRITE_SCC_DQ_OUT1_DELAY(subdq, delay); + scc_mgr_load_dq (subdq); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + for (test_num = 0; test_num < NUM_WRITE_TESTS; test_num++) + { + rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ALL_BITS, &bit_chk, 0); + if (test_num == 0) + { + bit_chk_test = bit_chk; + } + else + { + bit_chk_test &= bit_chk; + } + } + + // Check only the bit we are testing + bit_chk_mask = (bit_chk_test & (((t_btfld)1) << ((t_btfld)subdq))); + if (bit_chk_mask == 0) + { + break; + } + + working_cnt++; + } + + // Restore the settings + WRITE_SCC_DQ_OUT1_DELAY(subdq, calibrated_delay); + scc_mgr_load_dq (subdq); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + // Store the setting + TCLRPT_SET(debug_margin_report->margin_dq_out_margins[curr_shadow_reg][dq].min_working_setting, working_cnt); + + // Find the right edge + calibrated_delay = debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].dqs_out_delay1; + + working_cnt = 0; + for (delay = calibrated_delay; delay <= IO_IO_OUT1_DELAY_MAX; delay++) + { + WRITE_SCC_DQS_IO_OUT1_DELAY(delay); + scc_mgr_load_dqs_io(); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + + for (test_num = 0; test_num < NUM_WRITE_TESTS; test_num++) + { + rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0); + if (test_num == 0) + { + bit_chk_test = bit_chk; + } + else + { + bit_chk_test &= bit_chk; + } + } + + // Check only the bit we are testing + bit_chk_mask = (bit_chk_test & (((t_btfld)1) << ((t_btfld)subdq))); + if (bit_chk_mask == 0) + { + break; + } + + working_cnt++; + } + + //USER Restore the settings + if (QDRII) { + scc_mgr_set_group_dqs_io_and_oct_out1_gradual (write_group, calibrated_delay); + } else { + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, calibrated_delay); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + + // Store the setting + TCLRPT_SET(debug_margin_report->margin_dq_out_margins[curr_shadow_reg][dq].max_working_setting, working_cnt); + } +} +#endif + +#if ENABLE_TCL_DEBUG +// NOTE: if ever executing a run_*_margining function outside of calibration context you must first issue IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 1); +void run_dm_margining (alt_u32 rank_bgn, alt_u32 write_group) +{ + alt_u32 test_status; + alt_u32 test_num; + alt_u32 dm; + alt_u32 delay; + alt_u32 calibrated_delay; + alt_u32 working_cnt; + t_btfld bit_chk; + + ALTERA_ASSERT(write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH); + + select_curr_shadow_reg_using_rank(rank_bgn); + + // sweep output delays + for (dm = 0; dm < RW_MGR_NUM_DM_PER_WRITE_GROUP; dm++) + { + + calibrated_delay = debug_cal_report->cal_dm_settings[curr_shadow_reg][write_group][dm].dm_out_delay1; + working_cnt = 0; + + // Find the left edge + for (delay = calibrated_delay; delay <= IO_IO_OUT1_DELAY_MAX; delay++) + { + WRITE_SCC_DM_IO_OUT1_DELAY(dm, delay); + scc_mgr_load_dm (dm); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + test_status = 1; + for (test_num = 0; test_num < NUM_WRITE_TESTS; test_num++) + { + if (!rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) + { + test_status = 0; + break; + } + } + + if (test_status == 0) + { + break; + } + + working_cnt++; + } + + // Restore the settings + WRITE_SCC_DM_IO_OUT1_DELAY(dm, calibrated_delay); + scc_mgr_load_dm (dm); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + // Store the setting + TCLRPT_SET(debug_margin_report->margin_dm_margins[curr_shadow_reg][write_group][dm].min_working_setting, working_cnt); + + // Find the right edge + calibrated_delay = debug_cal_report->cal_dqs_out_settings[curr_shadow_reg][write_group].dqs_out_delay1; + + working_cnt = 0; + for (delay = calibrated_delay; delay <= IO_IO_OUT1_DELAY_MAX; delay++) + { + WRITE_SCC_DQS_IO_OUT1_DELAY(delay); + scc_mgr_load_dqs_io(); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + if (QDRII) + { + rw_mgr_mem_dll_lock_wait(); + } + + test_status = 1; + for (test_num = 0; test_num < NUM_WRITE_TESTS; test_num++) + { + if (!rw_mgr_mem_calibrate_write_test (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) + { + test_status = 0; + break; + } + } + + if (test_status == 0) + { + break; + } + + working_cnt++; + } + + //USER Restore the settings + if (QDRII) { + scc_mgr_set_group_dqs_io_and_oct_out1_gradual (write_group, calibrated_delay); + } else { + scc_mgr_apply_group_dqs_io_and_oct_out1 (write_group, calibrated_delay); + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + + // Store the setting + TCLRPT_SET(debug_margin_report->margin_dm_margins[curr_shadow_reg][write_group][dm].max_working_setting, working_cnt); + + } +} +#endif + + +//USER precharge all banks and activate row 0 in bank "000..." and bank "111..." +#if DDRX +void mem_precharge_and_activate (void) +{ + alt_u32 r; + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + + //USER precharge all banks ... + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0F); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT1); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0F); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT2); + + //USER activate rows + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ACTIVATE_0_AND_1); + } +} +#endif + +#if QDRII || RLDRAMX +void mem_precharge_and_activate (void) {} +#endif + +//USER perform all refreshes necessary over all ranks +#if (ENABLE_NON_DESTRUCTIVE_CALIB || ENABLE_NON_DES_CAL) +// Only have DDR3 version for now +#if DDR3 +alt_u32 mem_refresh_all_ranks (alt_u32 no_validate) +{ + const alt_u32 T_REFI_NS = 3900; // JEDEC spec refresh interval in ns (industrial temp) +// const alt_u32 T_RFC_NS = 350; // Worst case REFRESH-REFRESH or REFRESH-ACTIVATE wait time in ns + // Alternatively, we could extract T_RFC from uniphy_gen.tcl + const alt_u32 T_RFC_AFI = 350 * AFI_CLK_FREQ / 1000; // T_RFC expressed in mem clk cycles (will be less than 256) +#if (ENABLE_NON_DESTRUCTIVE_CALIB) + const alt_u32 NUM_REFRESH_POSTING = 8192; // Number of consecutive refresh commands supported by Micron DDR3 devices +#else + const alt_u32 NUM_REFRESH_POSTING = 8; +#endif + alt_u32 i; + alt_u32 elapsed_time; // In AVL clock cycles + +#if (ENABLE_NON_DESTRUCTIVE_CALIB) + //USER Reset the refresh interval timer + elapsed_time = IORD_32DIRECT (BASE_TIMER, 0); + IOWR_32DIRECT (BASE_TIMER, 0, 0x00); + + //USER Validate that maximum refresh interval is not exceeded + if ( !no_validate ) { + if (!(~elapsed_time) || elapsed_time > (NUM_REFRESH_POSTING * T_REFI_NS * AVL_CLK_FREQ / 1000) ) { + // Non-destructive calibration failure + return 0; + } + } + +#endif + //USER set CS and ODT mask + if ( RDIMM || LRDIMM ) { + if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) { + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + } + else { + // Only single-rank DIMM supported for non-destructive cal + return 0; + } + } + else { // UDIMM + // Issue refreshes to all ranks simultaneously + IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, RW_MGR_RANK_ALL); + } + + //USER Precharge all banks + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); + // Wait for tRP = 15ns before issuing REFRESH commands + // No need to insert explicit delay; simulation shows more than 1000 ns between PRECHARGE and first REFRESH + + //USER Issue refreshes + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_REFRESH_ALL); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_REFRESH_DELAY); + for (i = 0; i < NUM_REFRESH_POSTING; i += 256) { + // Issue 256 REFRESH commands, waiting t_RFC between consecutive refreshes + +#if (ENABLE_NON_DESTRUCTIVE_CALIB) + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0xFF); +#else + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x07); +#endif + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, T_RFC_AFI); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH_ALL); + } + + //USER Re-activate all banks + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x00); // No need to wait between commands to activate different banks (since ACTIVATE is preceded by tRFC wait) + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0F); // Wait for ACTIVATE to complete + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT1); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT2); + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ACTIVATE_0_AND_1); + + return 1; +} +#else +alt_u32 mem_refresh_all_ranks (alt_u32 no_validate) +{ + return 1; +} +#endif +#endif + +//USER Configure various memory related parameters. + +#if DDRX +void mem_config (void) +{ + alt_u32 rlat, wlat; + alt_u32 rw_wl_nop_cycles; + alt_u32 max_latency; +#if CALIBRATE_BIT_SLIPS + alt_u32 i; +#endif + + TRACE_FUNC(); + + //USER read in write and read latency + + wlat = IORD_32DIRECT (MEM_T_WL_ADD, 0); +#if HARD_PHY + wlat += IORD_32DIRECT (DATA_MGR_MEM_T_ADD, 0); /* WL for hard phy does not include additive latency */ + + #if DDR3 || DDR2 + // YYONG: add addtional write latency to offset the address/command extra clock cycle + // YYONG: We change the AC mux setting causing AC to be delayed by one mem clock cycle + // YYONG: only do this for DDR3 + wlat = wlat + 1; + #endif +#endif + + rlat = IORD_32DIRECT (MEM_T_RL_ADD, 0); + + if (QUARTER_RATE_MODE) { + //USER In Quarter-Rate the WL-to-nop-cycles works like this + //USER 0,1 -> 0 + //USER 2,3,4,5 -> 1 + //USER 6,7,8,9 -> 2 + //USER etc... + rw_wl_nop_cycles = (wlat + 6) / 4 - 1; + } + else if(HALF_RATE_MODE) { + //USER In Half-Rate the WL-to-nop-cycles works like this + //USER 0,1 -> -1 + //USER 2,3 -> 0 + //USER 4,5 -> 1 + //USER etc... + if(wlat % 2) + { + rw_wl_nop_cycles = ((wlat - 1) / 2) - 1; + } + else + { + rw_wl_nop_cycles = (wlat / 2) - 1; + } + } + else { + rw_wl_nop_cycles = wlat - 2; +#if LPDDR2 + rw_wl_nop_cycles = rw_wl_nop_cycles + 1; +#endif + } +#if MULTIPLE_AFI_WLAT + for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + gbl->rw_wl_nop_cycles_per_group[i] = rw_wl_nop_cycles; + } +#endif + gbl->rw_wl_nop_cycles = rw_wl_nop_cycles; + +#if ARRIAV || CYCLONEV + //USER For AV/CV, lfifo is hardened and always runs at full rate + //USER so max latency in AFI clocks, used here, is correspondingly smaller + if (QUARTER_RATE_MODE) { + max_latency = (1<curr_read_lat = (rlat + 1) / 4 + 8; + } else if (HALF_RATE_MODE) { + //USER write latency + wlat = (wlat - 1) / 2 + 1; + + //USER set a pretty high read latency initially + gbl->curr_read_lat = (rlat + 1) / 2 + 8; + } else { + //USER write latency +#if HARD_PHY + // Adjust Write Latency for Hard PHY + wlat = wlat + 1; +#if LPDDR2 + // Add another one in hard for LPDDR2 since this value is raw from controller + // assume tdqss is one + wlat = wlat + 1; +#endif +#endif + + //USER set a pretty high read latency initially + gbl->curr_read_lat = rlat + 16; + } + + if (gbl->curr_read_lat > max_latency) { + gbl->curr_read_lat = max_latency; + } + IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat); + + //USER advertise write latency + gbl->curr_write_lat = wlat; +#if MULTIPLE_AFI_WLAT + for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { +#if HARD_PHY + IOWR_32DIRECT (PHY_MGR_AFI_WLAT, i*4, wlat - 2); +#else + IOWR_32DIRECT (PHY_MGR_AFI_WLAT, i*4, wlat - 1); +#endif + } +#else +#if HARD_PHY + IOWR_32DIRECT (PHY_MGR_AFI_WLAT, 0, wlat - 2); +#else + IOWR_32DIRECT (PHY_MGR_AFI_WLAT, 0, wlat - 1); +#endif +#endif + + //USER initialize bit slips +#if CALIBRATE_BIT_SLIPS + for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + IOWR_32DIRECT (PHY_MGR_FR_SHIFT, i*4, 0); + } +#endif + + + mem_precharge_and_activate (); +} +#endif + +#if QDRII || RLDRAMX +void mem_config (void) +{ + alt_u32 wlat, nop_cycles, max_latency; + + TRACE_FUNC(); + + max_latency = (1<curr_read_lat = (IORD_32DIRECT (MEM_T_RL_ADD, 0) + 1) / 4 + 8; + } else if (HALF_RATE_MODE) { + gbl->curr_read_lat = (IORD_32DIRECT (MEM_T_RL_ADD, 0) + 1) / 2 + 8; + } else { + gbl->curr_read_lat = IORD_32DIRECT (MEM_T_RL_ADD, 0) + 16; + } + if (gbl->curr_read_lat > max_latency) { + gbl->curr_read_lat = max_latency; + } + IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat); + + if (RLDRAMX) + { + //USER read in write and read latency + wlat = IORD_32DIRECT (MEM_T_WL_ADD, 0); + + if (QUARTER_RATE_MODE) + { + // TODO_JCHOI Verify + nop_cycles = ((wlat - 1) / 4) - 1; + } + else if (HALF_RATE_MODE) + { +#if HR_DDIO_OUT_HAS_THREE_REGS + nop_cycles = (wlat / 2) - 2; +#else + #if RLDRAM3 + // RLDRAM3 uses all AFI phases to issue commands + nop_cycles = (wlat / 2) - 2; + #else + nop_cycles = ((wlat + 1) / 2) - 2; + #endif +#endif + } + else + { + nop_cycles = wlat - 1; + } + gbl->rw_wl_nop_cycles = nop_cycles; + } +} +#endif + +//USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode + +void mem_skip_calibrate (void) +{ + alt_u32 vfifo_offset; + alt_u32 i, j, r; +#if HCX_COMPAT_MODE && DDR3 + alt_u32 v; +#if (RDIMM || LRDIMM) + alt_u32 increment = 2; +#else + alt_u32 wlat = IORD_32DIRECT (PHY_MGR_MEM_T_WL, 0); + alt_u32 rlat = IORD_32DIRECT (PHY_MGR_MEM_T_RL, 0); + alt_u32 increment = rlat - wlat*2 + 1; +#endif +#endif + + TRACE_FUNC(); + + // Need to update every shadow register set used by the interface + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + + // Strictly speaking this should be called once per group to make + // sure each group's delay chains are refreshed from the SCC register file, + // but since we're resetting all delay chains anyway, we can save some + // runtime by calling select_shadow_regs_for_update just once to switch rank. + select_shadow_regs_for_update(r, 0, 1); + + //USER Set output phase alignment settings appropriate for skip calibration + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + +#if STRATIXV || ARRIAV || CYCLONEV || ARRIAVGZ + scc_mgr_set_dqs_en_phase(i, 0); +#else +#if IO_DLL_CHAIN_LENGTH == 6 + scc_mgr_set_dqs_en_phase(i, (IO_DLL_CHAIN_LENGTH >> 1) - 1); +#else + scc_mgr_set_dqs_en_phase(i, (IO_DLL_CHAIN_LENGTH >> 1)); +#endif +#endif +#if HCX_COMPAT_MODE && DDR3 + v = 0; + for (j = 0; j < increment; j++) { + rw_mgr_incr_vfifo(i, &v); + } + +#if IO_DLL_CHAIN_LENGTH == 6 + scc_mgr_set_dqdqs_output_phase(i, 6); +#else + scc_mgr_set_dqdqs_output_phase(i, 7); +#endif +#else + #if HCX_COMPAT_MODE + // in this mode, write_clk doesn't always lead mem_ck by 90 deg, and so + // the enhancement in case:33398 can't be applied. + scc_mgr_set_dqdqs_output_phase(i, (IO_DLL_CHAIN_LENGTH - IO_DLL_CHAIN_LENGTH / 3)); + #else + // Case:33398 + // + // Write data arrives to the I/O two cycles before write latency is reached (720 deg). + // -> due to bit-slip in a/c bus + // -> to allow board skew where dqs is longer than ck + // -> how often can this happen!? + // -> can claim back some ptaps for high freq support if we can relax this, but i digress... + // + // The write_clk leads mem_ck by 90 deg + // The minimum ptap of the OPA is 180 deg + // Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay + // The write_clk is always delayed by 2 ptaps + // + // Hence, to make DQS aligned to CK, we need to delay DQS by: + // (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH)) + // + // Dividing the above by (360 / IO_DLL_CHAIN_LENGTH) gives us the number of ptaps, which simplies to: + // + // (1.25 * IO_DLL_CHAIN_LENGTH - 2) + scc_mgr_set_dqdqs_output_phase(i, (1.25 * IO_DLL_CHAIN_LENGTH - 2)); + #endif +#endif + } + + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, 0xff); + IOWR_32DIRECT (SCC_MGR_DQS_IO_ENA, 0, 0xff); + + for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) { + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, i); + IOWR_32DIRECT (SCC_MGR_DQ_ENA, 0, 0xff); + IOWR_32DIRECT (SCC_MGR_DM_ENA, 0, 0xff); + } + +#if USE_SHADOW_REGS + //USER in shadow-register mode, SCC_UPDATE is done on a per-group basis + //USER unless we explicitly ask for a multicast via the group counter + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, 0xFF); +#endif + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + } + +#if ARRIAV || CYCLONEV + // Compensate for simulation model behaviour + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + scc_mgr_set_dqs_bus_in_delay(i, 10); + scc_mgr_load_dqs (i); + } + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); +#endif + +#if ARRIAV || CYCLONEV + //ArriaV has hard FIFOs that can only be initialized by incrementing in sequencer + vfifo_offset = CALIB_VFIFO_OFFSET; + for (j = 0; j < vfifo_offset; j++) { + if(HARD_PHY) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HARD_PHY, 0, 0xff); + } else { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR, 0, 0xff); + } + } +#else +// Note, this is not currently supported; changing this might significantly +// increase the size of the ROM +#if SUPPORT_DYNAMIC_SKIP_CALIBRATE_ACTIONS + if ((DYNAMIC_CALIB_STEPS) & CALIB_IN_RTL_SIM) { + //USER VFIFO is reset to the correct settings in RTL simulation + } else { + vfifo_offset = IORD_32DIRECT (PHY_MGR_CALIB_VFIFO_OFFSET, 0); + + if (QUARTER_RATE_MODE) { + while (vfifo_offset > 3) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_QR, 0, 0xff); + vfifo_offset -= 4; + } + + if (vfifo_offset == 3) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR_HR, 0, 0xff); + } else if (vfifo_offset == 2) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HR, 0, 0xff); + } else if (vfifo_offset == 1) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR, 0, 0xff); + } + } else { + while (vfifo_offset > 1) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HR, 0, 0xff); + vfifo_offset -= 2; + } + + if (vfifo_offset == 1) { + IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_FR, 0, 0xff); + } + } + } +#endif +#endif + + + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + +#if ARRIAV || CYCLONEV + // For ACV with hard lfifo, we get the skip-cal setting from generation-time constant + gbl->curr_read_lat = CALIB_LFIFO_OFFSET; +#else + gbl->curr_read_lat = IORD_32DIRECT (PHY_MGR_CALIB_LFIFO_OFFSET, 0); +#endif + IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat); +} + + +#if BFM_MODE +void print_group_settings(alt_u32 group, alt_u32 dq_begin) +{ + int i; + + fprintf(bfm_gbl.outfp, "Group %lu (offset %lu)\n", group, dq_begin); + + fprintf(bfm_gbl.outfp, "Output:\n"); + fprintf(bfm_gbl.outfp, "dqdqs_out_phase: %2u\n", READ_SCC_DQDQS_OUT_PHASE(group)); + fprintf(bfm_gbl.outfp, "dqs_out1_delay: %2u\n", READ_SCC_DQS_IO_OUT1_DELAY()); + fprintf(bfm_gbl.outfp, "dqs_out2_delay: %2u\n", READ_SCC_DQS_IO_OUT2_DELAY()); + fprintf(bfm_gbl.outfp, "oct_out1_delay: %2u\n", READ_SCC_OCT_OUT1_DELAY(group)); + fprintf(bfm_gbl.outfp, "oct_out2_delay: %2u\n", READ_SCC_OCT_OUT2_DELAY(group)); + fprintf(bfm_gbl.outfp, "dm_out1: "); + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { + fprintf(bfm_gbl.outfp, "%2u ", READ_SCC_DM_IO_OUT1_DELAY(i)); + } + fprintf(bfm_gbl.outfp, "\n"); + fprintf(bfm_gbl.outfp, "dm_out2: "); + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { + fprintf(bfm_gbl.outfp, "%2u ", READ_SCC_DM_IO_OUT2_DELAY(i)); + } + fprintf(bfm_gbl.outfp, "\n"); + fprintf(bfm_gbl.outfp, "dq_out1: "); + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + fprintf(bfm_gbl.outfp, "%2u ", READ_SCC_DQ_OUT1_DELAY(i)); + } + fprintf(bfm_gbl.outfp, "\n"); + fprintf(bfm_gbl.outfp, "dq_out2: "); + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { + fprintf(bfm_gbl.outfp, "%2u ", READ_SCC_DQ_OUT2_DELAY(i)); + } + fprintf(bfm_gbl.outfp, "\n"); + + fprintf(bfm_gbl.outfp, "Input:\n"); + fprintf(bfm_gbl.outfp, "dqs_en_phase: %2u\n", READ_SCC_DQS_EN_PHASE(group)); + fprintf(bfm_gbl.outfp, "dqs_en_delay: %2u\n", READ_SCC_DQS_EN_DELAY(group)); + fprintf(bfm_gbl.outfp, "dqs_in_delay: %2u\n", READ_SCC_DQS_IN_DELAY(group)); + fprintf(bfm_gbl.outfp, "dq_in: "); + for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { + fprintf(bfm_gbl.outfp, "%2u ", READ_SCC_DQ_IN_DELAY(i)); + } + fprintf(bfm_gbl.outfp, "\n"); + + fprintf(bfm_gbl.outfp, "\n"); + + fflush(bfm_gbl.outfp); +} + +#endif + +#if RUNTIME_CAL_REPORT +void print_report(alt_u32 pass) +{ + RPRINT("Calibration Summary"); + char *stage_name, *substage_name; + + if(pass) { + RPRINT("Calibration Passed"); + RPRINT("FOM IN = %lu", gbl->fom_in); + RPRINT("FOM OUT = %lu", gbl->fom_out); + } else { + RPRINT("Calibration Failed"); + switch (gbl->error_stage) { + case CAL_STAGE_NIL: + stage_name = "NIL"; + substage_name = "NIL"; + case CAL_STAGE_VFIFO: + stage_name = "VFIFO"; + switch (gbl->error_substage) { + case CAL_SUBSTAGE_GUARANTEED_READ: + substage_name = "GUARANTEED READ"; + break; + case CAL_SUBSTAGE_DQS_EN_PHASE: + substage_name = "DQS ENABLE PHASE"; + break; + case CAL_SUBSTAGE_VFIFO_CENTER: + substage_name = "Read Per-Bit Deskew"; + break; + default: + substage_name = "NIL"; + } + break; + case CAL_STAGE_WLEVEL: + stage_name = "WRITE LEVELING"; + switch (gbl->error_substage) { + case CAL_SUBSTAGE_WORKING_DELAY: + substage_name = "DQS Window Left Edge"; //need a more descriptive name + break; + case CAL_SUBSTAGE_LAST_WORKING_DELAY: + substage_name = "DQS Window Right Edge"; + break; + case CAL_SUBSTAGE_WLEVEL_COPY: + substage_name = "WRITE LEVEL COPY"; + break; + default: + substage_name = "NIL"; + } + break; + case CAL_STAGE_LFIFO: + stage_name = "LFIFO"; + substage_name = "READ LATENCY"; + break; + case CAL_STAGE_WRITES: + stage_name = "WRITES"; + substage_name = "Write Per-Bit Deskew"; + break; + case CAL_STAGE_FULLTEST: + stage_name = "FULL TEST"; + substage_name = "FULL TEST"; + break; + case CAL_STAGE_REFRESH: + stage_name = "REFRESH"; + substage_name = "REFRESH"; + break; + case CAL_STAGE_CAL_SKIPPED: + stage_name = "SKIP CALIBRATION"; //hw: is this needed + substage_name = "SKIP CALIBRATION"; + break; + case CAL_STAGE_CAL_ABORTED: + stage_name = "ABORTED CALIBRATION"; //hw: hum??? + substage_name = "ABORTED CALIBRATION"; + break; + case CAL_STAGE_VFIFO_AFTER_WRITES: + stage_name = "READ Fine-tuning"; + switch (gbl->error_substage) { + case CAL_SUBSTAGE_GUARANTEED_READ: + substage_name = "GUARANTEED READ"; + break; + case CAL_SUBSTAGE_DQS_EN_PHASE: + substage_name = "DQS ENABLE PHASE"; + break; + case CAL_SUBSTAGE_VFIFO_CENTER: + substage_name = "VFIFO CENTER"; + break; + default: + substage_name = "NIL"; + } + break; + default: + stage_name = "NIL"; + substage_name = "NIL"; + } + RPRINT("Error Stage : %lu - %s", gbl->error_stage, stage_name); + RPRINT("Error Substage: %lu - %s", gbl->error_substage, substage_name); + RPRINT("Error Group : %lu", gbl->error_group); + } +} +#endif //RUNTIME_CAL_REPORT + +//USER Memory calibration entry point + +alt_u32 mem_calibrate (void) +{ + alt_u32 i; + alt_u32 rank_bgn, sr; + alt_u32 write_group, write_test_bgn; + alt_u32 read_group, read_test_bgn; + alt_u32 run_groups, current_run; + alt_u32 failing_groups = 0; + alt_u32 group_failed = 0; + alt_u32 sr_failed = 0; + + TRACE_FUNC(); + + // Initialize the data settings + DPRINT(1, "Preparing to init data"); +#if ENABLE_TCL_DEBUG + tclrpt_initialize_data(); +#endif + DPRINT(1, "Init complete"); + + gbl->error_substage = CAL_SUBSTAGE_NIL; + gbl->error_stage = CAL_STAGE_NIL; + gbl->error_group = 0xff; + gbl->fom_in = 0; + gbl->fom_out = 0; + + TCLRPT_SET(debug_summary_report->cal_read_latency, 0); + TCLRPT_SET(debug_summary_report->cal_write_latency, 0); + + mem_config (); + + if(ARRIAV || CYCLONEV) { + alt_u32 bypass_mode = (HARD_PHY) ? 0x1 : 0x0; + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, i); + scc_set_bypass_mode (i, bypass_mode); + } + } + + if (((DYNAMIC_CALIB_STEPS) & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) { + //USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode + + mem_skip_calibrate (); + } else { + for (i = 0; i < NUM_CALIB_REPEAT; i++) { + + //USER Zero all delay chain/phase settings for all groups and all shadow register sets + scc_mgr_zero_all (); + +#if ENABLE_SUPER_QUICK_CALIBRATION + for (write_group = 0, write_test_bgn = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++, write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) + { + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, write_group); + scc_mgr_zero_group (write_group, write_test_bgn, 0); + } +#endif + + run_groups = ~param->skip_groups; + + for (write_group = 0, write_test_bgn = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++, write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) + { + // Initialized the group failure + group_failed = 0; + + // Mark the group as being attempted for calibration +#if ENABLE_TCL_DEBUG + tclrpt_set_group_as_calibration_attempted(write_group); +#endif + +#if RLDRAMX || QDRII + //Note: + // It seems that with rldram and qdr vfifo starts at max (not sure for ddr) + // also not sure if max is really vfifo_size-1 or vfifo_size + BFM_GBL_SET(vfifo_idx,VFIFO_SIZE-1); +#else + BFM_GBL_SET(vfifo_idx,0); +#endif + current_run = run_groups & ((1 << RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1); + run_groups = run_groups >> RW_MGR_NUM_DQS_PER_WRITE_GROUP; + + if (current_run == 0) + { + continue; + } + + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, write_group); +#if !ENABLE_SUPER_QUICK_CALIBRATION + scc_mgr_zero_group (write_group, write_test_bgn, 0); +#endif + + for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH, read_test_bgn = 0; + read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH && group_failed == 0; + read_group++, read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) { + + //USER Calibrate the VFIFO + if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_VFIFO)) { + if (!rw_mgr_mem_calibrate_vfifo (read_group, read_test_bgn)) { + group_failed = 1; + + if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) { + return 0; + } + } + } + } + + //USER level writes (or align DK with CK for RLDRAMX) + if (group_failed == 0) + { + if ((DDRX || RLDRAMII) && !(ARRIAV || CYCLONEV)) + { + if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_WLEVEL)) { + if (!rw_mgr_mem_calibrate_wlevel (write_group, write_test_bgn)) { + group_failed = 1; + + if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) { + return 0; + } + } + } + } + } + + //USER Calibrate the output side + if (group_failed == 0) + { + for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) { + sr_failed = 0; + if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES)) { + if ((STATIC_CALIB_STEPS) & CALIB_SKIP_DELAY_SWEEPS) { + //USER not needed in quick mode! + } else { + //USER Determine if this set of ranks should be skipped entirely + if (! param->skip_shadow_regs[sr]) { + + //USER Select shadow register set + select_shadow_regs_for_update(rank_bgn, write_group, 1); + + if (!rw_mgr_mem_calibrate_writes (rank_bgn, write_group, write_test_bgn)) { + sr_failed = 1; + if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) { + return 0; + } + } + } + } + } + if(sr_failed == 0) { + TCLRPT_SET(debug_cal_report->cal_status_per_group[sr][write_group].error_stage, CAL_STAGE_NIL); + } else { + group_failed = 1; + } + } + } + +#if READ_AFTER_WRITE_CALIBRATION + if (group_failed == 0) + { + for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH, read_test_bgn = 0; + read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH && group_failed == 0; + read_group++, read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) { + + if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES)) { + if (!rw_mgr_mem_calibrate_vfifo_end (read_group, read_test_bgn)) { + group_failed = 1; + + if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) { + return 0; + } + } + } + } + } +#endif + + if (group_failed == 0) + { + +#if BFM_MODE + + // TODO: should just update global BFM structure with all data + // and print all out at the end + print_group_settings(write_group, write_test_bgn); +#endif + +#if STATIC_IN_RTL_SIM +#if ENABLE_TCL_DEBUG && BFM_MODE + tclrpt_populate_fake_margin_data(); +#endif +#else +#if ENABLE_TCL_DEBUG + if (gbl->phy_debug_mode_flags & PHY_DEBUG_ENABLE_MARGIN_RPT) + { + // Run margining + for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) { + + //USER Determine if this set of ranks should be skipped entirely + if (! param->skip_shadow_regs[sr]) { + + //USER Select shadow register set + select_shadow_regs_for_update(rank_bgn, write_group, 1); + + run_dq_margining(rank_bgn, write_group); +#if DDRX + if (RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP > 0) + { + run_dm_margining(rank_bgn, write_group); + } +#endif +#if QDRII + run_dm_margining(rank_bgn, write_group); +#endif +#if RLDRAMX + if (is_write_group_enabled_for_dm(write_group)) + { + run_dm_margining(rank_bgn, write_group); + } +#endif + } + } + } +#endif +#endif + } + + if (group_failed != 0) + { + failing_groups++; + } + +#if ENABLE_NON_DESTRUCTIVE_CALIB + if (gbl->phy_debug_mode_flags & PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION) { + // USER Refresh the memory + if (!mem_refresh_all_ranks(0)) { + set_failing_group_stage(write_group, CAL_STAGE_REFRESH, CAL_SUBSTAGE_REFRESH); + TCLRPT_SET(debug_cal_report->cal_status_per_group[curr_shadow_reg][write_group].error_stage, CAL_STAGE_REFRESH); + return 0; + } + } +#endif + +#if ENABLE_NON_DESTRUCTIVE_CALIB + // USER Check if synchronous abort has been asserted + if (abort_cal) { + set_failing_group_stage(write_group, CAL_STAGE_CAL_ABORTED, CAL_SUBSTAGE_NIL); + return 0; + } +#endif + } + + // USER If there are any failing groups then report the failure + if (failing_groups != 0) + { + return 0; + } + + //USER Calibrate the LFIFO + if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) { + //USER If we're skipping groups as part of debug, don't calibrate LFIFO + if (param->skip_groups == 0) + { + if (!rw_mgr_mem_calibrate_lfifo ()) { + return 0; + } + } + } + } + } + + TCLRPT_SET(debug_summary_report->cal_write_latency, IORD_32DIRECT (MEM_T_WL_ADD, 0)); + if (QUARTER_RATE == 1) { + // The read latency is in terms of AFI cycles so we multiply by 4 in quarter + // rate to get the memory cycles. + TCLRPT_SET(debug_summary_report->cal_read_latency, gbl->curr_read_lat * 4); + } + else if (HALF_RATE == 1) { + // The read latency is in terms of AFI cycles so we multiply by 2 in half + // rate to get the memory cycles. + TCLRPT_SET(debug_summary_report->cal_read_latency, gbl->curr_read_lat * 2); + } + else { + TCLRPT_SET(debug_summary_report->cal_read_latency, gbl->curr_read_lat); + } + + + //USER Do not remove this line as it makes sure all of our decisions have been applied + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + return 1; +} +#if ENABLE_NON_DES_CAL +alt_u32 run_mem_calibrate(alt_u32 non_des_mode) { + +#else +alt_u32 run_mem_calibrate(void) { +#endif + + alt_u32 pass; + alt_u32 debug_info; + + // Initialize the debug status to show that calibration has started. + // This should occur before anything else +#if ENABLE_TCL_DEBUG + tclrpt_initialize_debug_status(); + + // Set that calibration has started + debug_data->status |= 1 << DEBUG_STATUS_CALIBRATION_STARTED; +#endif + // Reset pass/fail status shown on afi_cal_success/fail + IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_RESET); + + TRACE_FUNC(); + + BFM_STAGE("calibrate"); +#if USE_DQS_TRACKING +#if HHP_HPS + //stop tracking manger + alt_u32 ctrlcfg = IORD_32DIRECT(CTRL_CONFIG_REG,0); + + IOWR_32DIRECT(CTRL_CONFIG_REG, 0, ctrlcfg & 0xFFBFFFFF); +#else + // we need to stall tracking + IOWR_32DIRECT (TRK_STALL, 0, TRK_STALL_REQ_VAL); + // busy wait for tracking manager to ack stall request + while (IORD_32DIRECT (TRK_STALL, 0) != TRK_STALL_ACKED_VAL) { + } +#endif +#endif + + initialize(); + +#if ENABLE_NON_DESTRUCTIVE_CALIB + if (gbl->phy_debug_mode_flags & PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION) { + if (no_init) { + rw_mgr_mem_initialize_no_init(); + // refresh is done as part of rw_mgr_mem_initialize_no_init() + } else { + rw_mgr_mem_initialize (); + mem_refresh_all_ranks(1); + } + } else { + rw_mgr_mem_initialize (); + } +#else +#if ENABLE_NON_DES_CAL + if (non_des_mode) + rw_mgr_mem_initialize_no_init(); + else + rw_mgr_mem_initialize (); + +#else + rw_mgr_mem_initialize (); +#endif +#endif + + +#if ENABLE_BRINGUP_DEBUGGING + do_bringup_test(); +#endif + + pass = mem_calibrate (); + +#if ENABLE_NON_DESTRUCTIVE_CALIB + if( (gbl->phy_debug_mode_flags & PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION) ) { + if (!mem_refresh_all_ranks(0)) { + set_failing_group_stage(RW_MGR_MEM_IF_WRITE_DQS_WIDTH, CAL_STAGE_REFRESH, CAL_SUBSTAGE_REFRESH); + pass = 0; + } + } else { + mem_precharge_and_activate (); + } +#else + mem_precharge_and_activate (); +#endif + + //pe_checkout_pattern(); + + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + + if (pass) { + TCLRPT_SET(debug_summary_report->error_stage, CAL_STAGE_NIL); + + + BFM_STAGE("handoff"); + +#ifdef TEST_SIZE + if (!check_test_mem(0)) { + gbl->error_stage = 0x92; + gbl->error_group = 0x92; + } +#endif + } + +#if TRACKING_ERROR_TEST + if (IORD_32DIRECT(REG_FILE_TRK_SAMPLE_CHECK, 0) == 0xFE) { + poll_for_sample_check(); + } +#endif + + //USER Handoff +#if ENABLE_NON_DES_CAL + + if (non_des_mode) + { + alt_u32 took_too_long = 0; + IOWR_32DIRECT (RW_MGR_ENABLE_REFRESH, 0, 0); // Disable refresh engine + took_too_long = IORD_32DIRECT (RW_MGR_ENABLE_REFRESH, 0); + + if (took_too_long != 0) + { + pass = 0; // force a failure + set_failing_group_stage(RW_MGR_MEM_IF_WRITE_DQS_WIDTH, CAL_STAGE_REFRESH, CAL_SUBSTAGE_REFRESH); + } + } +#endif + + + //USER Don't return control of the PHY back to AFI when in debug mode + if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) { + rw_mgr_mem_handoff (); + +#if HARD_PHY + // In Hard PHY this is a 2-bit control: + // 0: AFI Mux Select + // 1: DDIO Mux Select + IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0x2); +#else + IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0); +#endif + } +#if USE_DQS_TRACKING +#if HHP_HPS + IOWR_32DIRECT(CTRL_CONFIG_REG, 0, ctrlcfg); +#else + // clear tracking stall flags + IOWR_32DIRECT (TRK_STALL, 0, 0); +#endif +#endif + +#if FAKE_CAL_FAIL + if (0) { +#else + if (pass) { +#endif + IPRINT("CALIBRATION PASSED"); + + gbl->fom_in /= 2; + gbl->fom_out /= 2; + + if (gbl->fom_in > 0xff) { + gbl->fom_in = 0xff; + } + + if (gbl->fom_out > 0xff) { + gbl->fom_out = 0xff; + } + +#if BFM_MODE + // duplicated because we want it after updating gbl, but before phy + // is informed that calibration has completed + print_gbl(); + fini_outfile(); +#endif + + // Update the FOM in the register file + debug_info = gbl->fom_in; + debug_info |= gbl->fom_out << 8; + IOWR_32DIRECT (REG_FILE_FOM, 0, debug_info); + + IOWR_32DIRECT (PHY_MGR_CAL_DEBUG_INFO, 0, debug_info); + IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_SUCCESS); + + } else { + + IPRINT("CALIBRATION FAILED"); + + debug_info = gbl->error_stage; + debug_info |= gbl->error_substage << 8; + debug_info |= gbl->error_group << 16; + +#if BFM_MODE + // duplicated because we want it after updating gbl, but before phy + // is informed that calibration has completed + print_gbl(); + fini_outfile(); +#endif + + IOWR_32DIRECT (REG_FILE_FAILING_STAGE, 0, debug_info); + IOWR_32DIRECT (PHY_MGR_CAL_DEBUG_INFO, 0, debug_info); + IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL); + + // Update the failing group/stage in the register file + debug_info = gbl->error_stage; + debug_info |= gbl->error_substage << 8; + debug_info |= gbl->error_group << 16; + IOWR_32DIRECT (REG_FILE_FAILING_STAGE, 0, debug_info); + + } + +#if RUNTIME_CAL_REPORT + print_report(pass); +#endif + + + // Mark the reports as being ready to read + TCLRPT_SET(debug_summary_report->report_flags, debug_summary_report->report_flags |= DEBUG_REPORT_STATUS_REPORT_READY); + TCLRPT_SET(debug_cal_report->report_flags, debug_cal_report->report_flags |= DEBUG_REPORT_STATUS_REPORT_READY); + TCLRPT_SET(debug_margin_report->report_flags, debug_margin_report->report_flags |= DEBUG_REPORT_STATUS_REPORT_READY); + + // Set the debug status to show that calibration has ended. + // This should occur after everything else +#if ENABLE_TCL_DEBUG + debug_data->status |= 1 << DEBUG_STATUS_CALIBRATION_ENDED; +#endif + return pass; + +} + +#if HCX_COMPAT_MODE || ENABLE_INST_ROM_WRITE +void hc_initialize_rom_data(void) +{ + alt_u32 i; + + for(i = 0; i < inst_rom_init_size; i++) + { + alt_u32 data = inst_rom_init[i]; + IOWR_32DIRECT (RW_MGR_INST_ROM_WRITE, (i << 2), data); + } + + for(i = 0; i < ac_rom_init_size; i++) + { + alt_u32 data = ac_rom_init[i]; + IOWR_32DIRECT (RW_MGR_AC_ROM_WRITE, (i << 2), data); + } +} +#endif + +#if BFM_MODE +void init_outfile(void) +{ + const char *filename = getenv("SEQ_OUT_FILE"); + + if (filename == NULL) { + filename = "sequencer.out"; + } + + if ((bfm_gbl.outfp = fopen(filename, "w")) == NULL) { + printf("ERROR: Failed to open %s for writing; using stdout\n", filename); + bfm_gbl.outfp = stdout; + } + + fprintf(bfm_gbl.outfp, "%s%s %s ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu dqs=%lu,%lu dq=%lu dm=%lu " + "ptap_delay=%lu dtap_delay=%lu dtap_dqsen_delay=%lu dll=%lu\n", + RDIMM ? "r" : (LRDIMM ? "l" : ""), + DDR2 ? "DDR2" : (DDR3 ? "DDR3" : (QDRII ? "QDRII" : (RLDRAMII ? "RLDRAMII" : (RLDRAM3 ? "RLDRAM3" : "??PROTO??")))), + FULL_RATE ? "FR" : (HALF_RATE ? "HR" : (QUARTER_RATE ? "QR" : "??RATE??")), + RW_MGR_MEM_NUMBER_OF_RANKS, + RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM, + RW_MGR_MEM_DQ_PER_READ_DQS, + RW_MGR_MEM_DQ_PER_WRITE_DQS, + RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS, + RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS, + RW_MGR_MEM_IF_READ_DQS_WIDTH, + RW_MGR_MEM_IF_WRITE_DQS_WIDTH, + RW_MGR_MEM_DATA_WIDTH, + RW_MGR_MEM_DATA_MASK_WIDTH, + IO_DELAY_PER_OPA_TAP, + IO_DELAY_PER_DCHAIN_TAP, + IO_DELAY_PER_DQS_EN_DCHAIN_TAP, + IO_DLL_CHAIN_LENGTH); + fprintf(bfm_gbl.outfp, "max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu io_in_d=%lu io_out1_d=%lu io_out2_d=%lu " + "dqs_in_reserve=%lu dqs_out_reserve=%lu\n", + IO_DQS_EN_PHASE_MAX, + IO_DQDQS_OUT_PHASE_MAX, + IO_DQS_EN_DELAY_MAX, + IO_DQS_IN_DELAY_MAX, + IO_IO_IN_DELAY_MAX, + IO_IO_OUT1_DELAY_MAX, + IO_IO_OUT2_DELAY_MAX, + IO_DQS_IN_RESERVE, + IO_DQS_OUT_RESERVE); + fprintf(bfm_gbl.outfp, "\n"); + // repeat these in a format that can be easily parsed + fprintf(bfm_gbl.outfp, "ptap_delay: %lu\n", IO_DELAY_PER_OPA_TAP); + fprintf(bfm_gbl.outfp, "dtap_delay: %lu\n", IO_DELAY_PER_DCHAIN_TAP); + fprintf(bfm_gbl.outfp, "ptap_per_cycle: %lu\n", IO_DLL_CHAIN_LENGTH); + fprintf(bfm_gbl.outfp, "ptap_max: %lu\n", IO_DQDQS_OUT_PHASE_MAX); + fprintf(bfm_gbl.outfp, "dtap_max: %lu\n", IO_IO_OUT1_DELAY_MAX); + fprintf(bfm_gbl.outfp, "vfifo_size: %lu\n", VFIFO_SIZE); +} + +void fini_outfile(void) +{ + if (bfm_gbl.outfp != stdout && bfm_gbl.outfp != NULL) { + // just flush, in case we calibrate again + fflush(bfm_gbl.outfp); + } +} + +void print_u32_array(const char *label, alt_u32 *val, alt_u32 size) +{ + int i; + + fprintf(bfm_gbl.outfp, "%s", label); + for (i = 0; i < size; i++) { + fprintf(bfm_gbl.outfp, "%lu ", val[i]); + } + fprintf(bfm_gbl.outfp, "\n"); +} + +void print_s32_array(const char *label, alt_32 *val, alt_u32 size) +{ + int i; + + fprintf(bfm_gbl.outfp, "%s", label); + for (i = 0; i < size; i++) { + fprintf(bfm_gbl.outfp, "%ld ", val[i]); + } + fprintf(bfm_gbl.outfp, "\n"); +} + +void print_dqs_array(const char *label, alt_u32 *dqs) +{ + print_u32_array(label, dqs, MAX_DQS); +} + +void print_read_dq_array(const char *label, alt_32 *dq) +{ + print_s32_array(label, dq, RW_MGR_MEM_IF_READ_DQS_WIDTH*RW_MGR_MEM_DQ_PER_READ_DQS); +} + +void print_write_dq_array(const char *label, alt_32 *dq) +{ + print_s32_array(label, dq, RW_MGR_MEM_IF_WRITE_DQS_WIDTH*RW_MGR_MEM_DQ_PER_WRITE_DQS); +} + +void print_dm_array(const char *label, alt_32 *dq) +{ + print_s32_array(label, dq, RW_MGR_MEM_IF_WRITE_DQS_WIDTH*RW_MGR_NUM_DM_PER_WRITE_GROUP); +} + +void print_dqs_pos_array(const char *fmt, dqs_pos_t *dqs, int has_v, int has_ps) +{ + int i; + + if (has_v) { + fprintf(bfm_gbl.outfp, fmt, "_v: "); + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + fprintf(bfm_gbl.outfp, "%lu ", dqs[i].v); + } + fprintf(bfm_gbl.outfp, "\n"); + } + fprintf(bfm_gbl.outfp, fmt, "_p: "); + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + fprintf(bfm_gbl.outfp, "%lu ", dqs[i].p); + } + fprintf(bfm_gbl.outfp, "\n"); + fprintf(bfm_gbl.outfp, fmt, "_d: "); + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + fprintf(bfm_gbl.outfp, "%lu ", dqs[i].d); + } + fprintf(bfm_gbl.outfp, "\n"); + if (has_ps) { + fprintf(bfm_gbl.outfp, fmt, "_ps: "); + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + fprintf(bfm_gbl.outfp, "%lu ", dqs[i].ps); + } + fprintf(bfm_gbl.outfp, "\n"); + } +} + +void print_gbl(void) +{ + int i; + + fprintf(bfm_gbl.outfp, "Globals\n"); + fprintf(bfm_gbl.outfp, "bfm_stage: %s\n", BFM_GBL_GET(stage)); + // TODO: may want to do this per group, like other values + print_dqs_pos_array( "dqse_left%s ", BFM_GBL_GET(dqs_enable_left_edge), 1, 1); + print_dqs_pos_array( "dqse_right%s ", BFM_GBL_GET(dqs_enable_right_edge), 1, 1); + print_dqs_pos_array( "dqse_mid%s ", BFM_GBL_GET(dqs_enable_mid), 1, 1); + print_dqs_pos_array( "gwrite_pos%s ", BFM_GBL_GET(gwrite_pos), 0, 0); + print_dqs_pos_array( "dqswl_left%s ", BFM_GBL_GET(dqs_wlevel_left_edge), 0, 1); + print_dqs_pos_array( "dqswl_right%s", BFM_GBL_GET(dqs_wlevel_right_edge), 0, 1); + print_dqs_pos_array( "dqswl_mid%s ", BFM_GBL_GET(dqs_wlevel_mid), 0, 1); + print_read_dq_array( "dq_read_l: ", BFM_GBL_GET(dq_read_left_edge)); + print_read_dq_array( "dq_read_r: ", BFM_GBL_GET(dq_read_right_edge)); + print_write_dq_array( "dq_write_l: ", BFM_GBL_GET(dq_write_left_edge)); + print_write_dq_array( "dq_write_r: ", BFM_GBL_GET(dq_write_right_edge)); + print_dm_array( "dm_l: ", BFM_GBL_GET(dm_left_edge)); + print_dm_array( "dm_r: ", BFM_GBL_GET(dm_right_edge)); + + fprintf(bfm_gbl.outfp, "curr_read_lat: %lu\n", gbl->curr_read_lat); + fprintf(bfm_gbl.outfp, "error_stage: %lu\n", gbl->error_stage); + fprintf(bfm_gbl.outfp, "error_group: %lu\n", gbl->error_group); + fprintf(bfm_gbl.outfp, "fom_in: %lu\n", gbl->fom_in); + fprintf(bfm_gbl.outfp, "fom_out: %lu\n", gbl->fom_out); + fflush(bfm_gbl.outfp); +}; + +void bfm_set_globals_from_config() +{ + const char *filename = "board_delay_config.txt"; + const char *seq_c_prefix = "seq_c_"; + FILE *fp; + char line[1024]; + char name[64]; + int value; + + if ((fp = fopen(filename, "r")) == NULL) { + DPRINT(0, "Failed to open %s for reading; skipping config\n", filename); + return; + } + + while (fgets(line, sizeof(line), fp) != NULL) { + if (sscanf(line, "%s %ld", name, &value) != 2) { + continue; + } + // for some unknown reason, sscanf of 'name' doesn't seem to work when linked into modelsim, + // so we take a different approach for the name part, by just looking at the original line + if (strncmp(line, seq_c_prefix, strlen(seq_c_prefix)) != 0) { + // not a line targetted for us + continue; + } + + if (strncmp(line, "seq_c_skip_guaranteed_write", strlen("seq_c_skip_guaranteed_write")) == 0) { + BFM_GBL_SET(bfm_skip_guaranteed_write,value); + DPRINT(0, "bfm_skip_guaranteed_write => %ld", value); + } else if (strncmp(line, "seq_c_trk_sample_count", strlen("seq_c_trk_sample_count")) == 0) { + BFM_GBL_SET(trk_sample_count,value); + DPRINT(0, "trk_sample_count => %ld", value); + } else if (strncmp(line, "seq_c_trk_long_idle_updates", strlen("seq_c_trk_long_idle_updates")) == 0) { + BFM_GBL_SET(trk_long_idle_updates,value); + DPRINT(0, "trk_long_idle_updates => %ld", value); + } else if (strncmp(line, "seq_c_lfifo_margin", strlen("seq_c_lfifo_margin")) == 0) { + BFM_GBL_SET(lfifo_margin,value/AFI_RATE_RATIO); + DPRINT(0, "lfifo_margin => %ld", value); + } else { + DPRINT(0, "Unknown Sequencer setting in line: %s\n", line); + } + } + + fclose(fp); +} +#endif + +void initialize_reg_file(void) +{ + // Initialize the register file with the correct data + IOWR_32DIRECT (REG_FILE_SIGNATURE, 0, REG_FILE_INIT_SEQ_SIGNATURE); + IOWR_32DIRECT (REG_FILE_DEBUG_DATA_ADDR, 0, 0); + IOWR_32DIRECT (REG_FILE_CUR_STAGE, 0, 0); + IOWR_32DIRECT (REG_FILE_FOM, 0, 0); + IOWR_32DIRECT (REG_FILE_FAILING_STAGE, 0, 0); + IOWR_32DIRECT (REG_FILE_DEBUG1, 0, 0); + IOWR_32DIRECT (REG_FILE_DEBUG2, 0, 0); +} + +#if HPS_HW +void initialize_hps_phy(void) +{ + // These may need to be included also: + // wrap_back_en (false) + // atpg_en (false) + // pipelineglobalenable (true) + + alt_u32 reg; + // Tracking also gets configured here because it's in the same register + alt_u32 trk_sample_count = 7500; + alt_u32 trk_long_idle_sample_count = (10 << 16) | 100; // Format is number of outer loops in the 16 MSB, sample count in 16 LSB. + + reg = 0; +#if DDR3 || DDR2 + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2); +#else + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(1); +#endif + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1); + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1); + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1); + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0); +#if LPDDR2 + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(0); +#else + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1); +#endif + // Fix for long latency VFIFO + // This field selects the intrinsic latency to RDATA_EN/FULL path. 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles. + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0); + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(trk_sample_count); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(trk_sample_count >> SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH); + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(trk_long_idle_sample_count); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(trk_long_idle_sample_count >> SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET, reg); +} +#endif + +#if USE_DQS_TRACKING + +#if HHP_HPS +void initialize_tracking(void) +{ + alt_u32 concatenated_longidle = 0x0; + alt_u32 concatenated_delays = 0x0; + alt_u32 concatenated_rw_addr = 0x0; + alt_u32 concatenated_refresh = 0x0; + alt_u32 dtaps_per_ptap; + alt_u32 tmp_delay; + + // compute usable version of value in case we skip full computation later + dtaps_per_ptap = 0; + tmp_delay = 0; + while (tmp_delay < IO_DELAY_PER_OPA_TAP) { + dtaps_per_ptap++; + tmp_delay += IO_DELAY_PER_DCHAIN_TAP; + } + dtaps_per_ptap--; + +#if BFM_MODE + concatenated_longidle = concatenated_longidle ^ (bfm_gbl.trk_long_idle_updates > 0 ? bfm_gbl.trk_long_idle_updates : 10); //longidle outer loop + concatenated_longidle = concatenated_longidle << 16; + concatenated_longidle = concatenated_longidle ^ (bfm_gbl.trk_sample_count > 0 ? bfm_gbl.trk_sample_count : 100); //longidle sample count +#else + concatenated_longidle = concatenated_longidle ^ 10; //longidle outer loop + concatenated_longidle = concatenated_longidle << 16; + concatenated_longidle = concatenated_longidle ^ 100; //longidle sample count +#endif + + concatenated_delays = concatenated_delays ^ 243; // trfc, worst case of 933Mhz 4Gb + concatenated_delays = concatenated_delays << 8; + concatenated_delays = concatenated_delays ^ 14; // trcd, worst case + concatenated_delays = concatenated_delays << 8; + concatenated_delays = concatenated_delays ^ 10; // vfifo wait + concatenated_delays = concatenated_delays << 8; + concatenated_delays = concatenated_delays ^ 4; // mux delay + +#if DDR3 || LPDDR2 + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_IDLE; + concatenated_rw_addr = concatenated_rw_addr << 8; + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_ACTIVATE_1; + concatenated_rw_addr = concatenated_rw_addr << 8; + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_SGLE_READ; + concatenated_rw_addr = concatenated_rw_addr << 8; + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_PRECHARGE_ALL; +#endif + +#if DDR3 || LPDDR2 + concatenated_refresh = concatenated_refresh ^ __RW_MGR_REFRESH_ALL; +#else + concatenated_refresh = concatenated_refresh ^ 0; +#endif + concatenated_refresh = concatenated_refresh << 24; + concatenated_refresh = concatenated_refresh ^ 1000; // trefi + + // Initialize the register file with the correct data + IOWR_32DIRECT (REG_FILE_DTAPS_PER_PTAP, 0, dtaps_per_ptap); +#if BFM_MODE + IOWR_32DIRECT (REG_FILE_TRK_SAMPLE_COUNT, 0, bfm_gbl.trk_sample_count > 0 ? bfm_gbl.trk_sample_count : 7500); +#else + IOWR_32DIRECT (REG_FILE_TRK_SAMPLE_COUNT, 0, 7500); +#endif + IOWR_32DIRECT (REG_FILE_TRK_LONGIDLE, 0, concatenated_longidle); + IOWR_32DIRECT (REG_FILE_DELAYS, 0, concatenated_delays); + IOWR_32DIRECT (REG_FILE_TRK_RW_MGR_ADDR, 0, concatenated_rw_addr); + IOWR_32DIRECT (REG_FILE_TRK_READ_DQS_WIDTH, 0, RW_MGR_MEM_IF_READ_DQS_WIDTH); + IOWR_32DIRECT (REG_FILE_TRK_RFSH, 0, concatenated_refresh); +} + +#else + +void initialize_tracking(void) +{ + alt_u32 concatenated_longidle = 0x0; + alt_u32 concatenated_delays = 0x0; + alt_u32 concatenated_rw_addr = 0x0; + alt_u32 concatenated_refresh = 0x0; + alt_u32 dtaps_per_ptap; + alt_u32 tmp_delay; + + // compute usable version of value in case we skip full computation later + dtaps_per_ptap = 0; + tmp_delay = 0; + while (tmp_delay < IO_DELAY_PER_OPA_TAP) { + dtaps_per_ptap++; + tmp_delay += IO_DELAY_PER_DCHAIN_TAP; + } + dtaps_per_ptap--; + +#if BFM_MODE + concatenated_longidle = concatenated_longidle ^ (bfm_gbl.trk_long_idle_updates > 0 ? bfm_gbl.trk_long_idle_updates : 10); //longidle outer loop + concatenated_longidle = concatenated_longidle << 16; + concatenated_longidle = concatenated_longidle ^ (bfm_gbl.trk_sample_count > 0 ? bfm_gbl.trk_sample_count : 100); //longidle sample count +#else + concatenated_longidle = concatenated_longidle ^ 10; //longidle outer loop + concatenated_longidle = concatenated_longidle << 16; + concatenated_longidle = concatenated_longidle ^ 100; //longidle sample count +#endif + +#if FULL_RATE + concatenated_delays = concatenated_delays ^ 60; // trfc +#endif +#if HALF_RATE + concatenated_delays = concatenated_delays ^ 30; // trfc +#endif +#if QUARTER_RATE + concatenated_delays = concatenated_delays ^ 15; // trfc +#endif + concatenated_delays = concatenated_delays << 8; +#if FULL_RATE + concatenated_delays = concatenated_delays ^ 4; // trcd +#endif +#if HALF_RATE + concatenated_delays = concatenated_delays ^ 2; // trcd +#endif +#if QUARTER_RATE + concatenated_delays = concatenated_delays ^ 0; // trcd +#endif + concatenated_delays = concatenated_delays << 8; +#if FULL_RATE + concatenated_delays = concatenated_delays ^ 5; // vfifo wait +#endif +#if HALF_RATE + concatenated_delays = concatenated_delays ^ 3; // vfifo wait +#endif +#if QUARTER_RATE + concatenated_delays = concatenated_delays ^ 1; // vfifo wait +#endif + concatenated_delays = concatenated_delays << 8; +#if FULL_RATE + concatenated_delays = concatenated_delays ^ 4; // mux delay +#endif +#if HALF_RATE + concatenated_delays = concatenated_delays ^ 2; // mux delay +#endif +#if QUARTER_RATE + concatenated_delays = concatenated_delays ^ 0; // mux delay +#endif + +#if DDR3 || LPDDR2 + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_IDLE; + concatenated_rw_addr = concatenated_rw_addr << 8; + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_ACTIVATE_1; + concatenated_rw_addr = concatenated_rw_addr << 8; + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_SGLE_READ; + concatenated_rw_addr = concatenated_rw_addr << 8; + concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_PRECHARGE_ALL; +#endif + +#if DDR3 || LPDDR2 + concatenated_refresh = concatenated_refresh ^ __RW_MGR_REFRESH_ALL; +#else + concatenated_refresh = concatenated_refresh ^ 0; +#endif + concatenated_refresh = concatenated_refresh << 24; + concatenated_refresh = concatenated_refresh ^ 546; // trefi + + IOWR_32DIRECT (TRK_DTAPS_PER_PTAP, 0, dtaps_per_ptap); +#if BFM_MODE + IOWR_32DIRECT (TRK_SAMPLE_COUNT, 0, bfm_gbl.trk_sample_count > 0 ? bfm_gbl.trk_sample_count : 7500); +#else + IOWR_32DIRECT (TRK_SAMPLE_COUNT, 0, 7500); +#endif + IOWR_32DIRECT (TRK_LONGIDLE, 0, concatenated_longidle); + IOWR_32DIRECT (TRK_DELAYS, 0, concatenated_delays); + IOWR_32DIRECT (TRK_RW_MGR_ADDR, 0, concatenated_rw_addr); + IOWR_32DIRECT (TRK_READ_DQS_WIDTH, 0, RW_MGR_MEM_IF_READ_DQS_WIDTH); + IOWR_32DIRECT (TRK_RFSH, 0, concatenated_refresh); +} +#endif /* HHP_HPS */ +#endif /* USE_DQS_TRACKING */ + +#if HHP_HPS_SIMULATION +void initialize_hps_controller(void) +{ + alt_u32 reg; + alt_u32 memtype; + alt_u32 ecc; + alt_u32 ctrl_width; + alt_u32 mem_bl; + + if (DDR2) { + memtype = 1; + } else if (DDR3) { + memtype = 2; + } else if (LPDDR1) { + memtype = 3; + } else if (LPDDR2) { + memtype = 4; + } else { + // should never happen + memtype = 0; + } + + if (RW_MGR_MEM_DATA_WIDTH == 24 || RW_MGR_MEM_DATA_WIDTH == 40) { + // we have ecc + ecc = 1; + } else { + ecc = 0; + } + + reg = 0; + reg |= SDR_CTRLGRP_CTRLCFG_MEMTYPE_SET(memtype); + reg |= SDR_CTRLGRP_CTRLCFG_MEMBL_SET(MEM_BURST_LENGTH); + reg |= SDR_CTRLGRP_CTRLCFG_ADDRORDER_SET(ADDR_ORDER); + reg |= SDR_CTRLGRP_CTRLCFG_ECCEN_SET(ecc); + reg |= SDR_CTRLGRP_CTRLCFG_ECCCORREN_SET(0); + reg |= SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_SET(0); + reg |= SDR_CTRLGRP_CTRLCFG_GENSBE_SET(0); + reg |= SDR_CTRLGRP_CTRLCFG_GENDBE_SET(0); + reg |= SDR_CTRLGRP_CTRLCFG_REORDEREN_SET(1); + reg |= SDR_CTRLGRP_CTRLCFG_STARVELIMIT_SET(0x8); + reg |= SDR_CTRLGRP_CTRLCFG_DQSTRKEN_SET(USE_DQS_TRACKING); // Do we want this? +#if DM_PINS_ENABLED + reg |= SDR_CTRLGRP_CTRLCFG_NODMPINS_SET(0); +#else + reg |= SDR_CTRLGRP_CTRLCFG_NODMPINS_SET(1); +#endif + reg |= SDR_CTRLGRP_CTRLCFG_BURSTINTREN_SET(0); + reg |= SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_SET(0); + reg |= SDR_CTRLGRP_CTRLCFG_OUTPUTREG_SET(0); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_CTRLCFG_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_DRAMTIMING1_TCWL_SET(MEM_WTCL_INT); + reg |= SDR_CTRLGRP_DRAMTIMING1_TAL_SET(MEM_ATCL_INT); + reg |= SDR_CTRLGRP_DRAMTIMING1_TCL_SET(MEM_TCL); + reg |= SDR_CTRLGRP_DRAMTIMING1_TRRD_SET(MEM_TRRD); + reg |= SDR_CTRLGRP_DRAMTIMING1_TFAW_SET(MEM_TFAW); + reg |= SDR_CTRLGRP_DRAMTIMING1_TRFC_SET(MEM_TRFC); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMTIMING1_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_DRAMTIMING2_TREFI_SET(MEM_TREFI); + reg |= SDR_CTRLGRP_DRAMTIMING2_TRCD_SET(MEM_TRCD); + reg |= SDR_CTRLGRP_DRAMTIMING2_TRP_SET(MEM_TRP); + reg |= SDR_CTRLGRP_DRAMTIMING2_TWTR_SET(MEM_TWTR); + reg |= SDR_CTRLGRP_DRAMTIMING2_TWR_SET(MEM_TWR); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMTIMING2_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_DRAMTIMING3_TRTP_SET(MEM_TRTP); + reg |= SDR_CTRLGRP_DRAMTIMING3_TRAS_SET(MEM_TRAS); + reg |= SDR_CTRLGRP_DRAMTIMING3_TRC_SET(MEM_TRC); + reg |= SDR_CTRLGRP_DRAMTIMING3_TMRD_SET(MEM_TMRD_CK); + reg |= SDR_CTRLGRP_DRAMTIMING3_TCCD_SET(CFG_TCCD); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMTIMING3_OFFSET, reg); + + + // These values don't really matter for the HPS simulation + reg = 0; + reg |= SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_SET(512); + reg |= SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_SET(10); + reg |= SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_SET(0); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMTIMING4_OFFSET, reg); + + // These values don't really matter for the HPS simulation + reg = 0; + reg |= SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_SET(0); + reg |= SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_SET(0); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_LOWPWRTIMING_OFFSET, reg); + + + // These values don't really matter for the HPS simulation + reg = 0; + reg |= SDR_CTRLGRP_DRAMODT_CFG_WRITE_ODT_CHIP_SET(0); + reg |= SDR_CTRLGRP_DRAMODT_CFG_READ_ODT_CHIP_SET(0); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMODT_OFFSET, reg); + + + reg = 0; + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_ACT_TO_RDWR_SET(INTG_EXTRA_CTL_CLK_ACT_TO_RDWR); + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_ACT_TO_PCH_SET(INTG_EXTRA_CTL_CLK_RD_TO_PCH); + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_ACT_TO_ACT_SET(INTG_EXTRA_CTL_CLK_ACT_TO_ACT); + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_RD_SET(INTG_EXTRA_CTL_CLK_RD_TO_RD); + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP_SET(INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP); + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_SET(INTG_EXTRA_CTL_CLK_RD_TO_WR); + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC_SET(INTG_EXTRA_CTL_CLK_RD_TO_WR_BC); + reg |= SDR_CTRLGRP_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP_SET(INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_EXTRATIME1_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_EXTRATIME2_CFG_EXTRA_CTL_CLK_RD_TO_PCH_SET(INTG_EXTRA_CTL_CLK_RD_TO_PCH); + reg |= SDR_CTRLGRP_EXTRATIME2_CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID_SET(INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID); + reg |= SDR_CTRLGRP_EXTRATIME2_CFG_EXTRA_CTL_CLK_WR_TO_WR_SET(INTG_EXTRA_CTL_CLK_WR_TO_WR); + reg |= SDR_CTRLGRP_EXTRATIME2_CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP_SET(INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP); + reg |= SDR_CTRLGRP_EXTRATIME2_CFG_EXTRA_CTL_CLK_WR_TO_RD_SET(INTG_EXTRA_CTL_CLK_WR_TO_RD); + reg |= SDR_CTRLGRP_EXTRATIME2_CFG_EXTRA_CTL_CLK_WR_TO_RD_BC_SET(INTG_EXTRA_CTL_CLK_WR_TO_RD_BC); + reg |= SDR_CTRLGRP_EXTRATIME2_CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP_SET(INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_EXTRATIME2_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_EXTRATIME3_CFG_EXTRA_CTL_CLK_WR_TO_PCH_SET(INTG_EXTRA_CTL_CLK_WR_TO_PCH); + reg |= SDR_CTRLGRP_EXTRATIME3_CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID_SET(INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID); + reg |= SDR_CTRLGRP_EXTRATIME3_CFG_EXTRA_CTL_CLK_PCH_TO_VALID_SET(INTG_EXTRA_CTL_CLK_PCH_TO_VALID); + reg |= SDR_CTRLGRP_EXTRATIME3_CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID_SET(INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID); + reg |= SDR_CTRLGRP_EXTRATIME3_CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK_SET(INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK); + reg |= SDR_CTRLGRP_EXTRATIME3_CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT_SET(INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT); + reg |= SDR_CTRLGRP_EXTRATIME3_CFG_EXTRA_CTL_CLK_ARF_TO_VALID_SET(INTG_EXTRA_CTL_CLK_ARF_TO_VALID); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_EXTRATIME3_OFFSET, reg); + + + reg = 0; + reg |= SDR_CTRLGRP_EXTRATIME4_CFG_EXTRA_CTL_CLK_PDN_TO_VALID_SET(INTG_EXTRA_CTL_CLK_PDN_TO_VALID); + reg |= SDR_CTRLGRP_EXTRATIME4_CFG_EXTRA_CTL_CLK_SRF_TO_VALID_SET(INTG_EXTRA_CTL_CLK_SRF_TO_VALID); + reg |= SDR_CTRLGRP_EXTRATIME4_CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL_SET(INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL); + reg |= SDR_CTRLGRP_EXTRATIME4_CFG_EXTRA_CTL_CLK_ARF_PERIOD_SET(INTG_EXTRA_CTL_CLK_ARF_PERIOD); + reg |= SDR_CTRLGRP_EXTRATIME4_CFG_EXTRA_CTL_CLK_PDN_PERIOD_SET(INTG_EXTRA_CTL_CLK_PDN_PERIOD); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_EXTRATIME4_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_DRAMADDRW_COLBITS_SET(MEM_IF_COL_ADDR_WIDTH); + reg |= SDR_CTRLGRP_DRAMADDRW_ROWBITS_SET(MEM_IF_ROW_ADDR_WIDTH); + reg |= SDR_CTRLGRP_DRAMADDRW_BANKBITS_SET(MEM_IF_BANKADDR_WIDTH); + reg |= SDR_CTRLGRP_DRAMADDRW_CSBITS_SET(MEM_IF_CS_WIDTH > 1 ? MEM_IF_CHIP_BITS : 0); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMADDRW_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_SET(RW_MGR_MEM_DATA_WIDTH); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMIFWIDTH_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_SET(RW_MGR_MEM_DQ_PER_READ_DQS); // should always be 8 + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_DRAMDEVWIDTH_OFFSET, reg); + + switch (RW_MGR_MEM_DATA_WIDTH) { + case 8: ctrl_width = 0; break; + case 16: // FALLTHROUGH + case 24: ctrl_width = 1; break; + case 32: // FALLTHROUGH + case 40: ctrl_width = 2; break; + default: ctrl_width = 0; break; /* shouldn't happen */ + } + + reg = 0; + reg |= SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_SET(ctrl_width); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_CTRLWIDTH_OFFSET, reg); + + // hard-coded values taken from test bench + reg = 0; + // 30'b111111111111010001000010001000 + reg |= SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_SET(0x3FFD1088); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_MPPRIORITY_OFFSET, reg); + + // hard-coded values taken from test bench + reg = 0; + // first 32 bits of 50'b01111011111000010000100001000010000100001000010000 + reg |= SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_SET(0x21084210); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_OFFSET, reg); + + // hard-coded values taken from test bench + reg = 0; + // first next 18 bits of 50'b01111011111000010000100001000010000100001000010000 + reg |= SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_SET(0x1EF84); + // first 14 of 64'b0011111000000000000000000000000000000000001000000010000000100000 + reg |= SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_SET(0x2002); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_OFFSET, reg); + + // hard-coded values taken from test bench + reg = 0; + // next 32 bits of 64'b0011111000000000000000000000000000000000001000000010000000100000 + reg |= SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_SET(0x80); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_OFFSET, reg); + + // hard-coded values taken from test bench + reg = 0; + // next 18 bits of 64'b0011111000000000000000000000000000000000001000000010000000100000 + reg |= SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_SET(0xF800); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_OFFSET, reg); + + switch (MEM_BURST_LENGTH) { + case 2: mem_bl = 0; break; + case 4: mem_bl = 1; break; + case 8: mem_bl = 2; break; + default: mem_bl = 2; break; // should never happen + } + reg = 0; + reg |= SDR_CTRLGRP_STATICCFG_MEMBL_SET(mem_bl); + reg |= SDR_CTRLGRP_STATICCFG_USEECCASDATA_SET(0); /* allow fpga to access ecc bits; not supported */ + reg |= SDR_CTRLGRP_STATICCFG_APPLYCFG_SET(1); /* apply all of the configs here and above */ + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_STATICCFG_OFFSET, reg); + + reg = 0; + reg |= SDR_CTRLGRP_FPGAPORTRST_PORTRSTN_SET(~0); + IOWR_32DIRECT (BASE_MMR, SDR_CTRLGRP_FPGAPORTRST_OFFSET, reg); +} +#endif + +void user_init_cal_req(void) +{ + alt_u32 scc_afi_reg; + + scc_afi_reg = IORD_32DIRECT (SCC_MGR_AFI_CAL_INIT, 0); + + if (scc_afi_reg == 1 || scc_afi_reg == 16) {// 1 is initialization request + initialize(); + rw_mgr_mem_initialize (); + rw_mgr_mem_handoff (); + IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0); + IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_SUCCESS); + } else if (scc_afi_reg == 2 || scc_afi_reg == 32) { +#if ENABLE_NON_DES_CAL + run_mem_calibrate (0); +#else + run_mem_calibrate(); +#endif + } +#if ENABLE_NON_DES_CAL + else if (scc_afi_reg == 4) { + //non destructive mem init + IOWR_32DIRECT (SCC_MGR_AFI_CAL_INIT, 0, scc_afi_reg & ~(1 << 2)); + + rw_mgr_mem_initialize_no_init(); + + + } else if (scc_afi_reg == 8) { + //non destructive mem calibrate + IOWR_32DIRECT (SCC_MGR_AFI_CAL_INIT, 0, scc_afi_reg & ~(1 << 3)); + + run_mem_calibrate (1); + IOWR_32DIRECT (RW_MGR_ENABLE_REFRESH, 0, 0); // Disable refresh engine + } +#endif + +} + +#if TRACKING_WATCH_TEST || TRACKING_ERROR_TEST +void decrement_dqs_en_phase (alt_u32 group) { + alt_u32 phase = 0; + alt_u32 v; + phase = READ_SCC_DQS_EN_PHASE(group); + + if (phase == 0) { + rw_mgr_decr_vfifo(group, &v); + scc_mgr_set_dqs_en_phase(group, IO_DQS_EN_PHASE_MAX); + scc_mgr_set_dqs_en_delay(group, IO_DQS_EN_DELAY_MAX); + return; + } + + scc_mgr_set_dqs_en_phase(group, phase - 1); + scc_mgr_set_dqs_en_delay(group, IO_DQS_EN_DELAY_MAX); +} + +void read_samples (void) +{ + alt_u32 group = 0; + alt_32 sample_count = 0; + alt_u32 delay = 0; + alt_u32 phase = 0; + + alt_u32 dtaps_per_ptap = 0; + + dtaps_per_ptap = IORD_32DIRECT(0xD0000, 0); + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][group].dtaps_per_ptap, dtaps_per_ptap); + +#if TRACKING_WATCH_TEST + for (;;) { + // Stall tracking to ensure accurate reading + IOWR_32DIRECT (TRK_STALL, 0, TRK_STALL_REQ_VAL); + // Wait for tracking manager to ack stall request + while (IORD_32DIRECT (TRK_STALL, 0) != TRK_STALL_ACKED_VAL) { + } + + for (group = 0; group < RW_MGR_MEM_IF_READ_DQS_WIDTH; group++) { + // Read sample counter + sample_count = IORD_32DIRECT(0x58F00, group << 2); + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][group].sample_count, sample_count); + delay = READ_SCC_DQS_EN_DELAY(group); + phase = READ_SCC_DQS_EN_PHASE(group); + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][group].dqs_en_phase, (delay | (phase << 16))); + } + + // Release stall + IOWR_32DIRECT(TRK_STALL, 0, 0); + } +#endif + +#if TRACKING_ERROR_TEST + for (group = 0; group < RW_MGR_MEM_IF_READ_DQS_WIDTH; group++) { + // Read sample counter + sample_count = IORD_32DIRECT(0x58F00, group << 2); + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][group].sample_count, sample_count); + delay = READ_SCC_DQS_EN_DELAY(group); + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][group].dqs_en_delay, delay); + phase = READ_SCC_DQS_EN_PHASE(group); + TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[curr_shadow_reg][group].dqs_en_phase, phase); + } +#endif +} + +void tracking_sample_check (void) +{ + alt_u32 group = 0; + alt_u32 t11_d = 0; + alt_u32 read_val = 0; + + alt_u32 num_samples = 0; + alt_u32 num_samples_max = 7500; + + alt_u32 bit_chk = 0; + alt_u32 test_status = 0; + + for (group = 0; group < RW_MGR_MEM_IF_READ_DQS_WIDTH; group++) + { + // TODO: Figure out whether the sample counter and sample run + // values should be defined somewhere, or just leave them + // hardcoded. + IOWR_32DIRECT(0x58F00, group << 2, 0x00); + } + + for (num_samples = 0; num_samples < num_samples_max; num_samples++) { + //do a read + //test_status = rw_mgr_mem_calibrate_read_test_all_ranks (group, 1, PASS_ONE_BIT, &bit_chk, 0); + //do a write + test_status = rw_mgr_mem_calibrate_write_test_all_ranks (group, 0, PASS_ONE_BIT, &bit_chk); + + // do a sample + IOWR_32DIRECT(0x58FFC, 0, 0xFF); + } + + read_samples(); +} + +void poll_for_sample_check (void) +{ + alt_u32 check_status = 2; + alt_u32 delay = 0; + alt_u32 group = 0; + + alt_u32 READY_FOR_READ = 0xFE; + alt_u32 READ_FINISHED = 0xFD; + alt_u32 EXIT_LOOP = 0x00; + alt_u32 FINISHED_SIGNAL = 0xFF; + + for (;;) { + check_status = IORD_32DIRECT(REG_FILE_TRK_SAMPLE_CHECK, 0); + + if (check_status == READY_FOR_READ) { + for (group = 0; group < RW_MGR_MEM_IF_READ_DQS_WIDTH; group++) { + + delay = READ_SCC_DQS_EN_DELAY(group); + + if (delay == 0) { + decrement_dqs_en_phase(group); + } else { + delay--; + scc_mgr_set_dqs_en_delay(group, delay); + } + + IOWR_32DIRECT (SCC_MGR_DQS_ENA, 0, group); + } + + IOWR_32DIRECT (SCC_MGR_UPD, 0, 0); + + tracking_sample_check(); + check_status = IORD_32DIRECT(REG_FILE_TRK_SAMPLE_CHECK, 0); + if (check_status != EXIT_LOOP) { + IOWR_32DIRECT(REG_FILE_TRK_SAMPLE_CHECK, 0, READ_FINISHED); + } + } + if (check_status == EXIT_LOOP) { + IOWR_32DIRECT(REG_FILE_TRK_SAMPLE_CHECK, 0, FINISHED_SIGNAL); + break; + } + } +} +#endif // TRACKING_WATCH_TEST || TRACKING_ERROR_TEST + +#if BFM_MODE +int seq_main(void) +#elif HPS_HW +int sdram_calibration(void) +#else +int main(void) +#endif +{ + param_t my_param; + gbl_t my_gbl; + alt_u32 pass; + alt_u32 i; + + param = &my_param; + gbl = &my_gbl; + + // Initialize the debug mode flags + gbl->phy_debug_mode_flags = 0; + // Set the calibration enabled by default + gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; + // Only enable margining by default if requested +#if ENABLE_MARGIN_REPORT_GEN + gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_MARGIN_RPT; +#endif + // Only sweep all groups (regardless of fail state) by default if requested +#if ENABLE_SWEEP_ALL_GROUPS + gbl->phy_debug_mode_flags |= PHY_DEBUG_SWEEP_ALL_GROUPS; +#endif + //Set enabled read test by default +#if DISABLE_GUARANTEED_READ + gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ; +#endif +#if ENABLE_NON_DESTRUCTIVE_CALIB + gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION; +#endif + +#if BFM_MODE + init_outfile(); + bfm_set_globals_from_config(); +#endif + + // Initialize the register file + initialize_reg_file(); + +#if HPS_HW + // Initialize any PHY CSR + initialize_hps_phy(); +#endif + +#if HHP_HPS + scc_mgr_initialize(); +#endif + +#if USE_DQS_TRACKING + initialize_tracking(); +#endif + + // Initialize the TCL report. This must occur before any printf + // but after the debug mode flags and register file +#if ENABLE_TCL_DEBUG + tclrpt_initialize(&my_debug_data); +#endif + + // USER Enable all ranks, groups + for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++) { + param->skip_ranks[i] = 0; + } + for (i = 0; i < NUM_SHADOW_REGS; ++i) { + param->skip_shadow_regs[i] = 0; + } + param->skip_groups = 0; + + IPRINT("Preparing to start memory calibration"); + + TRACE_FUNC(); + DPRINT(1, "%s%s %s ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu dqs=%lu,%lu dq=%lu dm=%lu " + "ptap_delay=%lu dtap_delay=%lu dtap_dqsen_delay=%lu, dll=%lu", + RDIMM ? "r" : (LRDIMM ? "l" : ""), + DDR2 ? "DDR2" : (DDR3 ? "DDR3" : (QDRII ? "QDRII" : (RLDRAMII ? "RLDRAMII" : (RLDRAM3 ? "RLDRAM3" : "??PROTO??")))), + FULL_RATE ? "FR" : (HALF_RATE ? "HR" : (QUARTER_RATE ? "QR" : "??RATE??")), + (long unsigned int)RW_MGR_MEM_NUMBER_OF_RANKS, + (long unsigned int)RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM, + (long unsigned int)RW_MGR_MEM_DQ_PER_READ_DQS, + (long unsigned int)RW_MGR_MEM_DQ_PER_WRITE_DQS, + (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS, + (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS, + (long unsigned int)RW_MGR_MEM_IF_READ_DQS_WIDTH, + (long unsigned int)RW_MGR_MEM_IF_WRITE_DQS_WIDTH, + (long unsigned int)RW_MGR_MEM_DATA_WIDTH, + (long unsigned int)RW_MGR_MEM_DATA_MASK_WIDTH, + (long unsigned int)IO_DELAY_PER_OPA_TAP, + (long unsigned int)IO_DELAY_PER_DCHAIN_TAP, + (long unsigned int)IO_DELAY_PER_DQS_EN_DCHAIN_TAP, + (long unsigned int)IO_DLL_CHAIN_LENGTH); + DPRINT(1, "max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu io_in_d=%lu io_out1_d=%lu io_out2_d=%lu" + "dqs_in_reserve=%lu dqs_out_reserve=%lu", + (long unsigned int)IO_DQS_EN_PHASE_MAX, + (long unsigned int)IO_DQDQS_OUT_PHASE_MAX, + (long unsigned int)IO_DQS_EN_DELAY_MAX, + (long unsigned int)IO_DQS_IN_DELAY_MAX, + (long unsigned int)IO_IO_IN_DELAY_MAX, + (long unsigned int)IO_IO_OUT1_DELAY_MAX, + (long unsigned int)IO_IO_OUT2_DELAY_MAX, + (long unsigned int)IO_DQS_IN_RESERVE, + (long unsigned int)IO_DQS_OUT_RESERVE); + +#if HCX_COMPAT_MODE || ENABLE_INST_ROM_WRITE + hc_initialize_rom_data(); +#endif + +#if !HARD_PHY + // Hard PHY does not support soft reset + IOWR_32DIRECT (RW_MGR_SOFT_RESET, 0, 0); +#endif + + //USER update info for sims + reg_file_set_stage(CAL_STAGE_NIL); + reg_file_set_group(0); + + // Load global needed for those actions that require + // some dynamic calibration support +#if HARD_PHY + dyn_calib_steps = STATIC_CALIB_STEPS; +#else + dyn_calib_steps = IORD_32DIRECT(PHY_MGR_CALIB_SKIP_STEPS, 0); +#endif + + // Load global to allow dynamic selection of delay loop settings + // based on calibration mode + if (!((DYNAMIC_CALIB_STEPS) & CALIB_SKIP_DELAY_LOOPS)) { + skip_delay_mask = 0xff; + } else { + skip_delay_mask = 0x0; + } + + +#ifdef TEST_SIZE + if (!check_test_mem(1)) { + IOWR_32DIRECT (PHY_MGR_CAL_DEBUG_INFO, 0, 0x9090); + IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL); + } + write_test_mem(); + if (!check_test_mem(0)) { + IOWR_32DIRECT (PHY_MGR_CAL_DEBUG_INFO, 0, 0x9191); + IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL); + } +#endif + + +#if HHP_HPS_SIMULATION + // configure controller + initialize_hps_controller(); +#endif + +#if ENABLE_TCL_DEBUG && USE_USER_RDIMM_VALUE + tclrpt_loop(); +#endif + + +#if ENABLE_NON_DES_CAL_TEST + rw_mgr_mem_initialize (); + +// IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_IDLE); +// IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_SELF_REFRESH); + + pass = run_mem_calibrate (1); + +#else + +#if ENABLE_NON_DES_CAL +#if ENABLE_TCL_DEBUG + tclrpt_loop(); +#else + pass = run_mem_calibrate (1); +#endif +#else + pass = run_mem_calibrate (); +#endif + +#endif + +#if TRACKING_WATCH_TEST + if (IORD_32DIRECT(REG_FILE_TRK_SAMPLE_CHECK, 0) == 0xEE) { + read_samples(); + } +#endif + +#if ENABLE_PRINTF_LOG + IPRINT("Calibration complete"); + // Send the end of transmission character + IPRINT("%c", 0x4); +#endif + + + + +#if BFM_MODE +#if ENABLE_TCL_DEBUG + tclrpt_dump_internal_data(); +#endif + bfm_sequencer_is_done(); +#elif HHP_HPS_SIMULATION + // nothing to do for HPS simulation following calibration + while (1) { + } +#elif ENABLE_TCL_DEBUG + #if HPS_HW + // EMPTY + #else + tclrpt_loop(); + #endif +#else + #if HPS_HW + // EMPTY + #else + while (1) { + user_init_cal_req(); + } + + #endif +#endif + + +return pass; +} + + +#if ENABLE_BRINGUP_DEBUGGING + +/////////////////////////////////////////////////////////////////////////////////////// +// Bring-Up test Support +/////////////////////////////////////////////////////////////////////////////////////// + + +void do_bringup_test_guaranteed_write (void) +{ + alt_u32 r; + + TRACE_FUNC(); + + for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { + if (param->skip_ranks[r]) { + //USER request to skip the rank + + continue; + } + + //USER set rank + set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + + //USER Load up a constant bursts + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_WRITE_0_1_A_5_WAIT0); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_WRITE_0_1_A_5_WAIT1); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_GUARANTEED_WRITE_0_1_A_5_WAIT2); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x20); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_GUARANTEED_WRITE_0_1_A_5_WAIT3); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_GUARANTEED_WRITE_0_1_A_5); + } + + set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); +} + +void do_bringup_test_clear_di_buf (alt_u32 group) +{ + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 128); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_DO_CLEAR_DI_BUF); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, group << 2, __RW_MGR_DO_CLEAR_DI_BUF); +} + +void do_bringup_test_guaranteed_read (alt_u32 group) +{ + IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0); + IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); + + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 16); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_DO_TEST_READ); + IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 16); + IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_DO_TEST_READ_POST_WAIT); + + IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, group << 2, __RW_MGR_DO_TEST_READ); +} + +void do_bringup_test () +{ + int i; + alt_u32 group; + alt_u32 v = 0; + + group = 0; + + mem_config (); + + // 15 is the maximum latency (should make dependent on actual design + IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, 15); /* lfifo setting */ + +#if ARRIAV || CYCLONEV + for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { + IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, i); + scc_set_bypass_mode(i, 0); + } +#endif + + // initialize global buffer to something known + for (i = 0; i < sizeof(di_buf_gbl); i++) { + di_buf_gbl[i] = 0xee; + } + + // pre-increment vfifo to ensure not at max value + rw_mgr_incr_vfifo(group, &v); + rw_mgr_incr_vfifo(group, &v); + + do_bringup_test_clear_di_buf(group); + + while (1) { + do_bringup_test_guaranteed_write(); + do_bringup_test_guaranteed_read(group); + load_di_buf_gbl(); + rw_mgr_incr_vfifo(group, &v); + } +} + + +#endif // ENABLE_BRINGUP_DEBUGGING + +#if ENABLE_ASSERT +void err_report_internal_error +( + const char* description, + const char* module, + const char* file, + int line +) +{ + void *array[10]; + size_t size; + char **strings; + size_t i; + + fprintf(stderr, ERR_IE_TEXT, module, file, line, description, "\n"); + + size = backtrace (array, 10); + strings = backtrace_symbols (array, size); + + fprintf (stderr, "Obtained %zd stack frames.\n", size); + + for (i = 0; i < size; i++) + { + fprintf (stderr, "%s\n", strings[i]); + } + + free (strings); +} +#endif diff --git a/ip/altera/ddr3/ddr3_s0_software/sequencer.h b/ip/altera/ddr3/ddr3_s0_software/sequencer.h new file mode 100644 index 0000000..8c65969 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_software/sequencer.h @@ -0,0 +1,648 @@ +#ifndef _SEQUENCER_H_ +#define _SEQUENCER_H_ + +/* +* Copyright Altera Corporation (C) 2012-2014. All rights reserved +* +* SPDX-License-Identifier: BSD-3-Clause +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Altera Corporation nor the +* names of its contributors may be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#if ENABLE_ASSERT +#define ERR_IE_TEXT "Internal Error: Sub-system: %s, File: %s, Line: %d\n%s%s" + +extern void err_report_internal_error (const char* description, const char* module, const char* file, int line); + +#define ALTERA_INTERNAL_ERROR(string) {err_report_internal_error(string, "SEQ", __FILE__, __LINE__); exit(-1);} + +#define ALTERA_ASSERT(condition) \ + if (!(condition)) { ALTERA_INTERNAL_ERROR(#condition); } +#define ALTERA_INFO_ASSERT(condition,text) \ + if (!(condition)) { ALTERA_INTERNAL_ERROR(text); } + +#else + +#define ALTERA_ASSERT(condition) +#define ALTERA_INFO_ASSERT(condition,text) + +#endif + + +#if RLDRAMII +#define RW_MGR_NUM_DM_PER_WRITE_GROUP (1) +#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (1) +#else +#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) +#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) +#endif + +#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) +#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS) + +#define RW_MGR_RUN_SINGLE_GROUP BASE_RW_MGR +#define RW_MGR_RUN_ALL_GROUPS BASE_RW_MGR + 0x0400 + +#if HARD_PHY +#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020) +#else +#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0010) +#endif + +#if DDR3 +#define DDR3_MR1_ODT_MASK 0xFFFFFD99 +#define DDR3_MR2_ODT_MASK 0xFFFFF9FF +#define DDR3_AC_MIRR_MASK 0x020A8 + +#if LRDIMM +// USER RTT_NOM: bits {4,3,2} of the SPD = bits {9,6,2} of the MR +#define LRDIMM_SPD_MR_RTT_NOM(spd_byte) \ + ( (((spd_byte) & (1 << 4)) << (9-4)) \ + | (((spd_byte) & (1 << 3)) << (6-3)) \ + | (((spd_byte) & (1 << 2)) << (2-2))) + +// USER RTT_DRV: bits {1,0} of the SPD = bits {5,1} of the MR +#define LRDIMM_SPD_MR_RTT_DRV(spd_byte) \ + ( (((spd_byte) & (1 << 1)) << (5-1)) \ + | (((spd_byte) & (1 << 0)) << (1-0))) + +// USER RTT_WR: bits {7,6} of the SPD = bits {10,9} of the MR +#define LRDIMM_SPD_MR_RTT_WR(spd_byte) \ + (((spd_byte) & (3 << 6)) << (9-6)) + +#endif // LRDIMM +#endif // DDR3 + +#define RW_MGR_LOAD_CNTR_0 BASE_RW_MGR + 0x0800 +#define RW_MGR_LOAD_CNTR_1 BASE_RW_MGR + 0x0804 +#define RW_MGR_LOAD_CNTR_2 BASE_RW_MGR + 0x0808 +#define RW_MGR_LOAD_CNTR_3 BASE_RW_MGR + 0x080C + +#define RW_MGR_LOAD_JUMP_ADD_0 BASE_RW_MGR + 0x0C00 +#define RW_MGR_LOAD_JUMP_ADD_1 BASE_RW_MGR + 0x0C04 +#define RW_MGR_LOAD_JUMP_ADD_2 BASE_RW_MGR + 0x0C08 +#define RW_MGR_LOAD_JUMP_ADD_3 BASE_RW_MGR + 0x0C0C + +#define RW_MGR_RESET_READ_DATAPATH BASE_RW_MGR + 0x1000 +#define RW_MGR_SOFT_RESET BASE_RW_MGR + 0x2000 + +#define RW_MGR_SET_CS_AND_ODT_MASK BASE_RW_MGR + 0x1400 +#define RW_MGR_SET_ACTIVE_RANK BASE_RW_MGR + 0x2400 + +#define RW_MGR_LOOPBACK_MODE BASE_RW_MGR + 0x0200 + +#define RW_MGR_ENABLE_REFRESH BASE_RW_MGR + 0x3000 + +#define RW_MGR_RANK_NONE 0xFF +#define RW_MGR_RANK_ALL 0x00 + +#define RW_MGR_ODT_MODE_OFF 0 +#define RW_MGR_ODT_MODE_READ_WRITE 1 + +#define NUM_CALIB_REPEAT 1 + +#define NUM_READ_TESTS 7 +#define NUM_READ_PB_TESTS 7 +#define NUM_WRITE_TESTS 15 +#define NUM_WRITE_PB_TESTS 31 + +#define PASS_ALL_BITS 1 +#define PASS_ONE_BIT 0 + +/* calibration stages */ + +#define CAL_STAGE_NIL 0 +#define CAL_STAGE_VFIFO 1 +#define CAL_STAGE_WLEVEL 2 +#define CAL_STAGE_LFIFO 3 +#define CAL_STAGE_WRITES 4 +#define CAL_STAGE_FULLTEST 5 +#define CAL_STAGE_REFRESH 6 +#define CAL_STAGE_CAL_SKIPPED 7 +#define CAL_STAGE_CAL_ABORTED 8 +#define CAL_STAGE_VFIFO_AFTER_WRITES 9 + +/* calibration substages */ + +#define CAL_SUBSTAGE_NIL 0 +#define CAL_SUBSTAGE_GUARANTEED_READ 1 +#define CAL_SUBSTAGE_DQS_EN_PHASE 2 +#define CAL_SUBSTAGE_VFIFO_CENTER 3 +#define CAL_SUBSTAGE_WORKING_DELAY 1 +#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2 +#define CAL_SUBSTAGE_WLEVEL_COPY 3 +#define CAL_SUBSTAGE_WRITES_CENTER 1 +#define CAL_SUBSTAGE_READ_LATENCY 1 +#define CAL_SUBSTAGE_REFRESH 1 + +#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS) +#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > RW_MGR_MEM_IF_READ_DQS_WIDTH ? RW_MGR_MEM_IF_WRITE_DQS_WIDTH : RW_MGR_MEM_IF_READ_DQS_WIDTH) +#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH) +#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH) + +/* length of VFIFO, from SW_MACROS */ +#define VFIFO_SIZE (READ_VALID_FIFO_SIZE) + +/* Memory for data transfer between TCL scripts and NIOS. + * + * - First word is a command request. + * - The remaining words are part of the transfer. + */ + +/* Define the base address of each manager. */ + +/* MarkW: how should these base addresses be done for A-V? */ +#define BASE_PTR_MGR SEQUENCER_PTR_MGR_INST_BASE +#if HARD_PHY +#define BASE_PHY_MGR (0x00088000) +#define BASE_RW_MGR (0x00090000) +#define BASE_DATA_MGR (0x00098000) +#else +#define BASE_PHY_MGR SEQUENCER_PHY_MGR_INST_BASE +#define BASE_RW_MGR SEQUENCER_RW_MGR_INST_BASE +#define BASE_DATA_MGR SEQUENCER_DATA_MGR_INST_BASE +#endif +#define BASE_SCC_MGR SEQUENCER_SCC_MGR_INST_BASE +#define BASE_REG_FILE SEQUENCER_REG_FILE_INST_BASE +#define BASE_TIMER SEQUENCER_TIMER_INST_BASE +#define BASE_MMR (0x000C0000) +#define BASE_TRK_MGR (0x000D0000) + +/* Register file addresses. */ +#define REG_FILE_SIGNATURE (BASE_REG_FILE + 0x0000) +#define REG_FILE_DEBUG_DATA_ADDR (BASE_REG_FILE + 0x0004) +#define REG_FILE_CUR_STAGE (BASE_REG_FILE + 0x0008) +#define REG_FILE_FOM (BASE_REG_FILE + 0x000C) +#define REG_FILE_FAILING_STAGE (BASE_REG_FILE + 0x0010) +#define REG_FILE_DEBUG1 (BASE_REG_FILE + 0x0014) +#define REG_FILE_DEBUG2 (BASE_REG_FILE + 0x0018) + +#if TRACKING_WATCH_TEST || TRACKING_ERROR_TEST +#define REG_FILE_TRK_SAMPLE_CHECK (BASE_REG_FILE + 0x003C) +#elif MARGIN_VARIATION_TEST +#define IO_DQS_EN_DELAY_OFFSET (IORD_32DIRECT(BASE_REG_FILE + 0x003C, 0)) +#endif + +#if HHP_HPS +#define REG_FILE_DTAPS_PER_PTAP (BASE_REG_FILE + 0x001C) +#define REG_FILE_TRK_SAMPLE_COUNT (BASE_REG_FILE + 0x0020) +#define REG_FILE_TRK_LONGIDLE (BASE_REG_FILE + 0x0024) +#define REG_FILE_DELAYS (BASE_REG_FILE + 0x0028) +#define REG_FILE_TRK_RW_MGR_ADDR (BASE_REG_FILE + 0x002C) +#define REG_FILE_TRK_READ_DQS_WIDTH (BASE_REG_FILE + 0x0030) +#define REG_FILE_TRK_RFSH (BASE_REG_FILE + 0x0034) +#define CTRL_CONFIG_REG (BASE_MMR + 0x0000) +#else +/* Tracking slave addresses. */ +#define TRK_DTAPS_PER_PTAP (BASE_TRK_MGR + 0x0000) +#define TRK_SAMPLE_COUNT (BASE_TRK_MGR + 0x0004) +#define TRK_LONGIDLE (BASE_TRK_MGR + 0x0008) +#define TRK_DELAYS (BASE_TRK_MGR + 0x000C) +#define TRK_RW_MGR_ADDR (BASE_TRK_MGR + 0x0010) +#define TRK_READ_DQS_WIDTH (BASE_TRK_MGR + 0x0014) +#define TRK_RFSH (BASE_TRK_MGR + 0x0018) +#define TRK_STALL (BASE_TRK_MGR + 0x001C) +#define TRK_V_POINTER (BASE_TRK_MGR + 0x0020) + +#define TRK_STALL_REQ_VAL (0x1) +#define TRK_STALL_ACKED_VAL (0x80000000 | TRK_STALL_REQ_VAL) +#endif // HHP_HPS + +/* PHY manager configuration registers. */ + +#define PHY_MGR_PHY_RLAT (BASE_PHY_MGR + 0x4000) +#define PHY_MGR_RESET_MEM_STBL (BASE_PHY_MGR + 0x4004) +#define PHY_MGR_MUX_SEL (BASE_PHY_MGR + 0x4008) +#define PHY_MGR_CAL_STATUS (BASE_PHY_MGR + 0x400c) +#define PHY_MGR_CAL_DEBUG_INFO (BASE_PHY_MGR + 0x4010) +#define PHY_MGR_VFIFO_RD_EN_OVRD (BASE_PHY_MGR + 0x4014) +#if CALIBRATE_BIT_SLIPS +#define PHY_MGR_FR_SHIFT (BASE_PHY_MGR + 0x4020) +#if MULTIPLE_AFI_WLAT +#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x4020 + 4*RW_MGR_MEM_IF_WRITE_DQS_WIDTH) +#else +#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x4018) +#endif +#else +#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x4018) +#endif +#define PHY_MGR_AFI_RLAT (BASE_PHY_MGR + 0x401c) + +#define PHY_MGR_CAL_RESET (0) +#define PHY_MGR_CAL_SUCCESS (1) +#define PHY_MGR_CAL_FAIL (2) + +/* PHY manager command addresses. */ + +#define PHY_MGR_CMD_INC_VFIFO_FR (BASE_PHY_MGR + 0x0000) +#define PHY_MGR_CMD_INC_VFIFO_HR (BASE_PHY_MGR + 0x0004) +#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY (BASE_PHY_MGR + 0x0004) +#define PHY_MGR_CMD_FIFO_RESET (BASE_PHY_MGR + 0x0008) +#define PHY_MGR_CMD_INC_VFIFO_FR_HR (BASE_PHY_MGR + 0x000C) +#define PHY_MGR_CMD_INC_VFIFO_QR (BASE_PHY_MGR + 0x0010) + +/* PHY manager parameters. */ + +#define PHY_MGR_MAX_RLAT_WIDTH (BASE_PHY_MGR + 0x0000) +#define PHY_MGR_MAX_AFI_WLAT_WIDTH (BASE_PHY_MGR + 0x0004) +#define PHY_MGR_MAX_AFI_RLAT_WIDTH (BASE_PHY_MGR + 0x0008) +#define PHY_MGR_CALIB_SKIP_STEPS (BASE_PHY_MGR + 0x000c) +#define PHY_MGR_CALIB_VFIFO_OFFSET (BASE_PHY_MGR + 0x0010) +#define PHY_MGR_CALIB_LFIFO_OFFSET (BASE_PHY_MGR + 0x0014) +#define PHY_MGR_RDIMM (BASE_PHY_MGR + 0x0018) +#define PHY_MGR_MEM_T_WL (BASE_PHY_MGR + 0x001c) +#define PHY_MGR_MEM_T_RL (BASE_PHY_MGR + 0x0020) + +/* Data Manager */ +#define DATA_MGR_DRAM_CFG (BASE_DATA_MGR + 0x0000) +#define DATA_MGR_MEM_T_WL (BASE_DATA_MGR + 0x0004) +#define DATA_MGR_MEM_T_ADD (BASE_DATA_MGR + 0x0008) +#define DATA_MGR_MEM_T_RL (BASE_DATA_MGR + 0x000C) +#define DATA_MGR_MEM_T_RFC (BASE_DATA_MGR + 0x0010) +#define DATA_MGR_MEM_T_REFI (BASE_DATA_MGR + 0x0014) +#define DATA_MGR_MEM_T_WR (BASE_DATA_MGR + 0x0018) +#define DATA_MGR_MEM_T_MRD (BASE_DATA_MGR + 0x001C) +#define DATA_MGR_COL_WIDTH (BASE_DATA_MGR + 0x0020) +#define DATA_MGR_ROW_WIDTH (BASE_DATA_MGR + 0x0024) +#define DATA_MGR_BANK_WIDTH (BASE_DATA_MGR + 0x0028) +#define DATA_MGR_CS_WIDTH (BASE_DATA_MGR + 0x002C) +#define DATA_MGR_ITF_WIDTH (BASE_DATA_MGR + 0x0030) +#define DATA_MGR_DVC_WIDTH (BASE_DATA_MGR + 0x0034) + +#if HARD_PHY + #define MEM_T_WL_ADD DATA_MGR_MEM_T_WL + #define MEM_T_RL_ADD DATA_MGR_MEM_T_RL +#else + #define MEM_T_WL_ADD PHY_MGR_MEM_T_WL + #define MEM_T_RL_ADD PHY_MGR_MEM_T_RL +#endif + +#define CALIB_SKIP_DELAY_LOOPS (1 << 0) +#define CALIB_SKIP_ALL_BITS_CHK (1 << 1) +#define CALIB_SKIP_DELAY_SWEEPS (1 << 2) +#define CALIB_SKIP_VFIFO (1 << 3) +#define CALIB_SKIP_LFIFO (1 << 4) +#define CALIB_SKIP_WLEVEL (1 << 5) +#define CALIB_SKIP_WRITES (1 << 6) +#define CALIB_SKIP_FULL_TEST (1 << 7) +#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST) +#define CALIB_IN_RTL_SIM (1 << 8) + +/* Scan chain manager command addresses */ + +#define WRITE_SCC_DQS_IN_DELAY(group, delay) IOWR_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2, delay) +#define WRITE_SCC_DQS_EN_DELAY(group, delay) IOWR_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2, (delay) + IO_DQS_EN_DELAY_OFFSET) +#define WRITE_SCC_DQS_EN_PHASE(group, phase) IOWR_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2, phase) +#define WRITE_SCC_DQDQS_OUT_PHASE(group, phase) IOWR_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2, phase) +#define WRITE_SCC_OCT_OUT1_DELAY(group, delay) IOWR_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group) << 2, delay) +#if HHP_HPS +#define WRITE_SCC_OCT_OUT2_DELAY(group, delay) +#else +#define WRITE_SCC_OCT_OUT2_DELAY(group, delay) IOWR_32DIRECT(SCC_MGR_OCT_OUT2_DELAY, (group) << 2, delay) +#endif +#if HHP_HPS +#define WRITE_SCC_DQS_BYPASS(group, bypass) +#else +#define WRITE_SCC_DQS_BYPASS(group, bypass) IOWR_32DIRECT(SCC_MGR_DQS_BYPASS, (group) << 2, bypass) +#endif + +#define WRITE_SCC_DQ_OUT1_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2, delay) + +#if HHP_HPS +#define WRITE_SCC_DQ_OUT2_DELAY(pin, delay) +#else +#define WRITE_SCC_DQ_OUT2_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_OUT2_DELAY, (pin) << 2, delay) +#endif + +#define WRITE_SCC_DQ_IN_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2, delay) + +#if HHP_HPS +#define WRITE_SCC_DQ_BYPASS(pin, bypass) +#else +#define WRITE_SCC_DQ_BYPASS(pin, bypass) IOWR_32DIRECT(SCC_MGR_DQ_BYPASS, (pin) << 2, bypass) +#endif + +#if HHP_HPS +#define WRITE_SCC_RFIFO_MODE(pin, mode) +#else +#define WRITE_SCC_RFIFO_MODE(pin, mode) IOWR_32DIRECT(SCC_MGR_RFIFO_MODE, (pin) << 2, mode) +#endif + +#if HHP_HPS +#define WRITE_SCC_HHP_EXTRAS(value) IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_EXTRAS_OFFSET, value) +#define WRITE_SCC_HHP_DQSE_MAP(value) IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_DQSE_MAP_OFFSET, value) +#else +#define WRITE_SCC_HHP_EXTRAS(value) +#define WRITE_SCC_HHP_DQSE_MAP(value) +#endif + +#define WRITE_SCC_DQS_IO_OUT1_DELAY(delay) IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay) + +#if HHP_HPS +#define WRITE_SCC_DQS_IO_OUT2_DELAY(delay) +#else +#define WRITE_SCC_DQS_IO_OUT2_DELAY(delay) IOWR_32DIRECT(SCC_MGR_IO_OUT2_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay) +#endif + +#define WRITE_SCC_DQS_IO_IN_DELAY(delay) IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay) + +#define WRITE_SCC_DM_IO_OUT1_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay) + +#if HHP_HPS +#define WRITE_SCC_DM_IO_OUT2_DELAY(pin, delay) +#else +#define WRITE_SCC_DM_IO_OUT2_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_OUT2_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay) +#endif + +#define WRITE_SCC_DM_IO_IN_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay) + +#if HHP_HPS +#define WRITE_SCC_DM_BYPASS(pin, bypass) +#else +#define WRITE_SCC_DM_BYPASS(pin, bypass) IOWR_32DIRECT(SCC_MGR_DQ_BYPASS, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, bypass) +#endif + +#define READ_SCC_DQS_IN_DELAY(group) IORD_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2) +#define READ_SCC_DQS_EN_DELAY(group) (IORD_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2) - IO_DQS_EN_DELAY_OFFSET) +#define READ_SCC_DQS_EN_PHASE(group) IORD_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2) +#define READ_SCC_DQDQS_OUT_PHASE(group) IORD_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2) +#define READ_SCC_OCT_OUT1_DELAY(group) IORD_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) << 2) +#if HHP_HPS +#define READ_SCC_OCT_OUT2_DELAY(group) 0 +#else +#define READ_SCC_OCT_OUT2_DELAY(group) IORD_32DIRECT(SCC_MGR_OCT_OUT2_DELAY, (group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) << 2) +#endif +#if HHP_HPS +#define READ_SCC_DQS_BYPASS(group) 0 +#else +#define READ_SCC_DQS_BYPASS(group) IORD_32DIRECT(SCC_MGR_DQS_BYPASS, (group) << 2) +#endif +#if HHP_HPS +#define READ_SCC_DQS_BYPASS(group) 0 +#else +#define READ_SCC_DQS_BYPASS(group) IORD_32DIRECT(SCC_MGR_DQS_BYPASS, (group) << 2) +#endif + +#define READ_SCC_DQ_OUT1_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2) +#if HHP_HPS +#define READ_SCC_DQ_OUT2_DELAY(pin) 0 +#else +#define READ_SCC_DQ_OUT2_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_OUT2_DELAY, (pin) << 2) +#endif +#define READ_SCC_DQ_IN_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2) +#if HHP_HPS +#define READ_SCC_DQ_BYPASS(pin) 0 +#else +#define READ_SCC_DQ_BYPASS(pin) IOWR_32DIRECT(SCC_MGR_DQ_BYPASS, (pin) << 2) +#endif +#if HHP_HPS +#define READ_SCC_RFIFO_MODE(pin) 0 +#else +#define READ_SCC_RFIFO_MODE(pin) IOWR_32DIRECT(SCC_MGR_RFIFO_MODE, (pin) << 2) +#endif + +#define READ_SCC_DQS_IO_OUT1_DELAY() IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2) +#if HHP_HPS +#define READ_SCC_DQS_IO_OUT2_DELAY() 0 +#else +#define READ_SCC_DQS_IO_OUT2_DELAY() IORD_32DIRECT(SCC_MGR_IO_OUT2_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2) +#endif +#define READ_SCC_DQS_IO_IN_DELAY() IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2) + +#define READ_SCC_DM_IO_OUT1_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2) +#if HHP_HPS +#define READ_SCC_DM_IO_OUT2_DELAY(pin) 0 +#else +#define READ_SCC_DM_IO_OUT2_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_OUT2_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2) +#endif +#define READ_SCC_DM_IO_IN_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2) +#if HHP_HPS +#define READ_SCC_DM_BYPASS(pin) 0 +#else +#define READ_SCC_DM_BYPASS(pin) IOWR_32DIRECT(SCC_MGR_DQ_BYPASS, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2) +#endif + + +#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000) +#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100) +#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200) +#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300) +#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400) +#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500) +#if !HHP_HPS +#define SCC_MGR_OCT_OUT2_DELAY (BASE_SCC_MGR + 0x0600) +#endif +#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700) +#if !HHP_HPS +#define SCC_MGR_IO_OUT2_DELAY (BASE_SCC_MGR + 0x0800) +#endif +#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900) + +#if !HHP_HPS +/* ACV-specific commands */ +#define SCC_MGR_DQS_BYPASS (BASE_SCC_MGR + 0x0A00) +#define SCC_MGR_DQ_BYPASS (BASE_SCC_MGR + 0x0B00) +#define SCC_MGR_RFIFO_MODE (BASE_SCC_MGR + 0x0C00) +#endif + +#if HHP_HPS +/* HHP-HPS-specific versions of some commands */ +#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600) +#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800) +#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00) +#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00) +#endif + +/* HHP-HPS-specific values */ +#define SCC_MGR_HHP_EXTRAS_OFFSET 0 +#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1 + +#define SCC_MGR_DQS_ENA (BASE_SCC_MGR + 0x0E00) +#define SCC_MGR_DQS_IO_ENA (BASE_SCC_MGR + 0x0E04) +#define SCC_MGR_DQ_ENA (BASE_SCC_MGR + 0x0E08) +#define SCC_MGR_DM_ENA (BASE_SCC_MGR + 0x0E0C) +#define SCC_MGR_UPD (BASE_SCC_MGR + 0x0E20) +#define SCC_MGR_ACTIVE_RANK (BASE_SCC_MGR + 0x0E40) +#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00) + +// PHY Debug mode flag constants +#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001 +#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002 +#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004 +#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008 +#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 +#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 + +// Init and Reset delay constants - Only use if defined by sequencer_defines.h, +// otherwise, revert to defaults +// Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 200.75us @ 266MHz +#ifdef TINIT_CNTR0_VAL + #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL +#else + #define SEQ_TINIT_CNTR0_VAL 0 +#endif + +#ifdef TINIT_CNTR1_VAL + #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL +#else + #define SEQ_TINIT_CNTR1_VAL 202 +#endif + +#ifdef TINIT_CNTR2_VAL + #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL +#else + #define SEQ_TINIT_CNTR2_VAL 131 +#endif + + +// Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 500.86us @ 266MHz +#ifdef TRESET_CNTR0_VAL + #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL +#else + #define SEQ_TRESET_CNTR0_VAL 2 +#endif + +#ifdef TRESET_CNTR1_VAL + #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL +#else + #define SEQ_TRESET_CNTR1_VAL 252 +#endif + +#ifdef TRESET_CNTR2_VAL + #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL +#else + #define SEQ_TRESET_CNTR2_VAL 131 +#endif + + + +/* Bitfield type changes depending on protocol */ +#if QDRII +typedef long long t_btfld; +#else +typedef alt_u32 t_btfld; +#endif + +#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800 +#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00 + +extern const alt_u32 inst_rom_init_size; +extern const alt_u32 inst_rom_init[]; +extern const alt_u32 ac_rom_init_size; +extern const alt_u32 ac_rom_init[]; + + + +/* parameter variable holder */ + +typedef struct param_type { + t_btfld dm_correct_mask; + t_btfld read_correct_mask; + t_btfld read_correct_mask_vg; + t_btfld write_correct_mask; + t_btfld write_correct_mask_vg; + + /* set a particular entry to 1 if we need to skip a particular rank */ + + alt_u32 skip_ranks[MAX_RANKS]; + + /* set a particular entry to 1 if we need to skip a particular group */ + + alt_u32 skip_groups; + + /* set a particular entry to 1 if the shadow register (which represents a set of ranks) needs to be skipped */ + + alt_u32 skip_shadow_regs[NUM_SHADOW_REGS]; + +} param_t; + + +/* global variable holder */ + +typedef struct gbl_type { + + alt_u32 phy_debug_mode_flags; + + /* current read latency */ + + alt_u32 curr_read_lat; + + /* current write latency */ + + alt_u32 curr_write_lat; + + /* error code */ + + alt_u32 error_substage; + alt_u32 error_stage; + alt_u32 error_group; + + /* figure-of-merit in, figure-of-merit out */ + + alt_u32 fom_in; + alt_u32 fom_out; + + //USER Number of RW Mgr NOP cycles between write command and write data +#if MULTIPLE_AFI_WLAT + alt_u32 rw_wl_nop_cycles_per_group[RW_MGR_MEM_IF_WRITE_DQS_WIDTH]; +#endif + alt_u32 rw_wl_nop_cycles; +} gbl_t; + +// External global variables +extern gbl_t *gbl; +extern param_t *param; + +// External functions +alt_u32 rw_mgr_mem_calibrate_full_test (alt_u32 min_correct, t_btfld *bit_chk, alt_u32 test_dm); +#if ENABLE_NON_DES_CAL +extern alt_u32 run_mem_calibrate (alt_u32 enable_non_des_c); +#else +extern alt_u32 run_mem_calibrate (void); +#endif +extern void rw_mgr_mem_calibrate_eye_diag_aid (void); +extern void rw_mgr_load_mrs_calib (void); +extern void rw_mgr_load_mrs_exec (void); +extern void rw_mgr_mem_initialize (void); +extern void rw_mgr_mem_dll_lock_wait(void); +extern inline void scc_mgr_set_dq_in_delay (alt_u32 write_group, alt_u32 dq_in_group, alt_u32 delay); +extern inline void scc_mgr_set_dq_out1_delay (alt_u32 write_group, alt_u32 dq_in_group, alt_u32 delay); +extern inline void scc_mgr_set_dq_out2_delay (alt_u32 write_group, alt_u32 dq_in_group, alt_u32 delay); +extern inline void scc_mgr_load_dq (alt_u32 dq_in_group); +extern inline void scc_mgr_set_dqs_bus_in_delay (alt_u32 read_group, alt_u32 delay); +extern inline void scc_mgr_load_dqs (alt_u32 dqs); +extern void scc_mgr_set_group_dqs_io_and_oct_out1_gradual (alt_u32 write_group, alt_u32 delay); +extern void scc_mgr_set_group_dqs_io_and_oct_out2_gradual (alt_u32 write_group, alt_u32 delay); +extern void scc_mgr_set_dqs_en_delay_all_ranks (alt_u32 read_group, alt_u32 delay); +extern void scc_mgr_set_dqs_en_phase_all_ranks (alt_u32 read_group, alt_u32 phase); +extern void scc_mgr_set_dqdqs_output_phase_all_ranks (alt_u32 write_group, alt_u32 phase); +extern inline void scc_mgr_set_dm_out1_delay (alt_u32 write_group, alt_u32 dm, alt_u32 delay); +extern inline void scc_mgr_set_dm_out2_delay (alt_u32 write_group, alt_u32 dm, alt_u32 delay); +extern inline void scc_mgr_load_dm (alt_u32 dm); +extern void rw_mgr_incr_vfifo_auto(alt_u32 grp); +extern void rw_mgr_decr_vfifo_auto(alt_u32 grp); +#if HPS_HW +extern int sdram_calibration(void); +#endif +#endif diff --git a/ip/altera/ddr3/ddr3_s0_software/sequencer_defines.h b/ip/altera/ddr3/ddr3_s0_software/sequencer_defines.h new file mode 100644 index 0000000..8ee38e7 --- /dev/null +++ b/ip/altera/ddr3/ddr3_s0_software/sequencer_defines.h @@ -0,0 +1,163 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _SEQUENCER_DEFINES_H_ +#define _SEQUENCER_DEFINES_H_ + +#define AC_ROM_MR1_MIRR 0000000100000 +#define AC_ROM_MR1_OCD_ENABLE +#define AC_ROM_MR2_MIRR 0000000010000 +#define AC_ROM_MR3_MIRR 0000000000000 +#define AC_ROM_MR0_CALIB +#define AC_ROM_MR0_DLL_RESET_MIRR 0001011001000 +#define AC_ROM_MR0_DLL_RESET 0001100110000 +#define AC_ROM_MR0_MIRR 0001001001001 +#define AC_ROM_MR0 0001000110001 +#define AC_ROM_MR1 0000001000000 +#define AC_ROM_MR2 0000000001000 +#define AC_ROM_MR3 0000000000000 +#define AC_ROM_USER_ADD_0 0_0000_0000_0000 +#define AC_ROM_USER_ADD_1 0_0000_0000_1000 +#define AFI_CLK_FREQ 301 +#define AFI_RATE_RATIO 1 +#define AP_MODE 0 +#define ARRIAVGZ 0 +#define ARRIAV 0 +#define AVL_CLK_FREQ 61 +#define BFM_MODE 0 +#define BURST2 0 +#define CALIBRATE_BIT_SLIPS 0 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define CYCLONEV 1 +#define DDR2 0 +#define DDR3 1 +#define DDRX 1 +#define DM_PINS_ENABLED 1 +#define ENABLE_ASSERT 0 +#define ENABLE_BRINGUP_DEBUGGING 0 +#define ENABLE_DELAY_CHAIN_WRITE 0 +#define ENABLE_DQS_IN_CENTERING 1 +#define ENABLE_DQS_OUT_CENTERING 0 +#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 +#define ENABLE_INST_ROM_WRITE 0 +#define ENABLE_MARGIN_REPORT_GEN 0 +#define ENABLE_NON_DESTRUCTIVE_CALIB 0 +#define ENABLE_NON_DES_CAL_TEST 0 +#define ENABLE_NON_DES_CAL 0 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define ENABLE_TCL_DEBUG 1 +#define FAKE_CAL_FAIL 0 +#define FULL_RATE 1 +#define GUARANTEED_READ_BRINGUP_TEST 0 +#define HALF_RATE 0 +#define HARD_PHY 1 +#define HARD_VFIFO 1 +#define HCX_COMPAT_MODE 0 +#define HHP_HPS_SIMULATION 0 +#define HHP_HPS_VERIFICATION 0 +#define HHP_HPS 0 +#define HPS_HW 0 +#define HR_DDIO_OUT_HAS_THREE_REGS 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 416 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DM_OUT_RESERVE 0 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_DQ_OUT_RESERVE 0 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define LPDDR1 0 +#define LPDDR2 0 +#define LRDIMM 0 +#define MARGIN_VARIATION_TEST 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define MEM_ADDR_WIDTH 13 +#define MRS_MIRROR_PING_PONG_ATSO 0 +#define MULTIPLE_AFI_WLAT 0 +#define NON_DES_CAL 0 +#define NUM_SHADOW_REGS 1 +#define QDRII 0 +#define QUARTER_RATE 0 +#define RDIMM 0 +#define READ_AFTER_WRITE_CALIBRATION 1 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550497 +#define RLDRAM3 0 +#define RLDRAMII 0 +#define RLDRAMX 0 +#define RUNTIME_CAL_REPORT 0 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_ADDRESS_WIDTH 13 +#define RW_MGR_MEM_BANK_WIDTH 3 +#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 +#define RW_MGR_MEM_CLK_EN_WIDTH 1 +#define RW_MGR_MEM_CONTROL_WIDTH 1 +#define RW_MGR_MEM_DATA_MASK_WIDTH 2 +#define RW_MGR_MEM_DATA_WIDTH 16 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 2 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 2 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_ODT_WIDTH 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_MR0_BL 1 +#define RW_MGR_MR0_CAS_LATENCY 3 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 2 +#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 +#define SKEW_CALIBRATION 0 +#define SKIP_PTAP_0_DQS_EN_CAL 1 +#define STATIC_FULL_CALIBRATION 1 +#define STATIC_SIM_FILESET 0 +#define STATIC_SKIP_MEM_INIT 0 +#define STRATIXV 0 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TINIT_CNTR0_VAL 74 +#define TRACKING_ERROR_TEST 0 +#define TRACKING_WATCH_TEST 0 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 +#define TRESET_CNTR0_VAL 74 +#define USE_DQS_TRACKING 0 +#define USE_SHADOW_REGS 0 +#define USE_USER_RDIMM_VALUE 0 + +#endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/ip/altera/ddr3/sequencer_reg_file.sv b/ip/altera/ddr3/sequencer_reg_file.sv new file mode 100644 index 0000000..6c3e990 --- /dev/null +++ b/ip/altera/ddr3/sequencer_reg_file.sv @@ -0,0 +1,260 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +// ****** +// reg_file +// ****** +// +// Register file +// +// General Description +// ------------------- +// +// This component stores all configuration/parameterization information +// that other components need to calibrate. +// +// Architecture +// ------------ +// +// The PHY Manager is organized as an +// - Avalon Interface: it's a Memory-Mapped interface to the Avalon +// Bus. +// - Register File: The "register file" of read/write registers +// + +module sequencer_reg_file ( + // Avalon Interface + + avl_clk, + avl_reset_n, + avl_address, + avl_write, + avl_writedata, + avl_read, + avl_readdata, + avl_waitrequest, + avl_be +); + +parameter AVL_DATA_WIDTH = 32; +parameter AVL_ADDR_WIDTH = 4; +parameter AVL_NUM_SYMBOLS = 4; +parameter AVL_SYMBOL_WIDTH = 8; +parameter REGISTER_RDATA = 0; +parameter NUM_REGFILE_WORDS = 16; +parameter DEBUG_REG_FILE_WORD = 2; + +input avl_clk; +input avl_reset_n; +input [AVL_ADDR_WIDTH - 1:0] avl_address; +input avl_write; +input [AVL_DATA_WIDTH - 1:0] avl_writedata; +input [AVL_NUM_SYMBOLS - 1:0] avl_be; +input avl_read; +output [AVL_DATA_WIDTH - 1:0] avl_readdata; +output avl_waitrequest; + +// synthesis translate_off +//Internal versions of request signals +reg [AVL_ADDR_WIDTH-1 : 0] int_addr; +reg [AVL_NUM_SYMBOLS - 1 : 0] int_be; +reg [AVL_DATA_WIDTH - 1 : 0] int_rdata; +reg [AVL_DATA_WIDTH - 1 : 0] int_rdata_reg; +// synthesis translate_on +logic int_waitrequest; +// synthesis translate_off +reg [AVL_DATA_WIDTH - 1 : 0] int_wdata; +logic [AVL_DATA_WIDTH - 1 : 0] int_wdata_wire; + +reg [AVL_DATA_WIDTH-1 : 0] reg_file [0 : NUM_REGFILE_WORDS-1] /* synthesis syn_ramstyle = "logic" */; + +integer i, b; + +// synthesis translate_on +//State machine states +typedef enum int unsigned { + INIT, + IDLE, + WRITE2, + READ2, + READ3, + READ4 +} avalon_state_t; + +avalon_state_t state; + +always_ff @ (posedge avl_clk or negedge avl_reset_n) begin + if (~avl_reset_n) + state <= INIT; + else begin + if (state == READ2) + state <= READ3; + else if ((state == READ3) && (REGISTER_RDATA)) + state <= READ4; + else if (state == IDLE) + if (avl_read) + state <= READ2; + else if (avl_write) + state <= WRITE2; + else + state <= IDLE; + else + state <= IDLE; + end +end + +assign int_waitrequest = (state == IDLE) || (state == WRITE2) || ((state == READ4) && (REGISTER_RDATA)) || ((state == READ3) && (REGISTER_RDATA == 0)) ? 1'b0 : 1'b1; + +// synthesis translate_off +generate +if (0) begin +// synthesis translate_on + +altsyncram altsyncram_component ( + .aclr0 (!avl_reset_n), + .address_a (avl_address), + .address_b (avl_address), + .byteena_a (avl_be), + .clock0 (avl_clk), + .clocken0 (1'b1), + .data_a (avl_writedata), + .q_b (avl_readdata), + .wren_a (avl_write)); +defparam + altsyncram_component.address_aclr_b = "CLEAR0", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Stratix III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.outdata_reg_b = REGISTER_RDATA ? "CLOCK0" : "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.ram_block_type = "MLAB", + altsyncram_component.rdcontrol_reg_b = "CLOCK0", + altsyncram_component.numwords_a = NUM_REGFILE_WORDS, + altsyncram_component.numwords_b = NUM_REGFILE_WORDS, + altsyncram_component.widthad_a = AVL_ADDR_WIDTH, + altsyncram_component.widthad_b = AVL_ADDR_WIDTH, + altsyncram_component.width_a = AVL_DATA_WIDTH, + altsyncram_component.width_b = AVL_DATA_WIDTH, + altsyncram_component.width_byteena_a = AVL_NUM_SYMBOLS, + altsyncram_component.width_byteena_b = AVL_NUM_SYMBOLS; + +// synthesis translate_off +end +endgenerate + +always_ff @ (posedge avl_clk or negedge avl_reset_n) begin + if (~avl_reset_n) begin + int_addr <= 0; + int_wdata <= 0; + int_be <= 0; + end + else if (int_waitrequest == 0) begin + int_addr <= avl_address; + int_wdata <= avl_writedata; + int_be <= avl_be; + end +end + +always_ff @ (posedge avl_clk or negedge avl_reset_n) begin + if (~avl_reset_n) begin + int_rdata <= 0; + end + else begin + if (state == READ2) + if (int_addr < NUM_REGFILE_WORDS) begin + int_rdata <= reg_file[int_addr]; + end + else begin + int_rdata <= 0; + end + else + int_rdata <= 0; + end +end + +property p_illegal_read_addr; + @(posedge avl_clk) + disable iff (!avl_reset_n) + (state == READ2) |-> (int_addr < NUM_REGFILE_WORDS); +endproperty + +a_illegal_read_addr : assert property (p_illegal_read_addr); + +always_comb begin + int_wdata_wire <= reg_file[int_addr]; + for (b=0; b < AVL_NUM_SYMBOLS; b++) + if (int_be[b]) + int_wdata_wire[(b+1)*AVL_SYMBOL_WIDTH-1-:AVL_SYMBOL_WIDTH] <= int_wdata[(b+1)*AVL_SYMBOL_WIDTH-1-:AVL_SYMBOL_WIDTH]; +end + +always_ff @ (posedge avl_clk or negedge avl_reset_n) begin + if (~avl_reset_n) begin + for (i=0; i < NUM_REGFILE_WORDS; i++) + reg_file[i] <= 0; + end + else begin + i = 0; + if (state == WRITE2) + if (int_addr < NUM_REGFILE_WORDS) begin + reg_file[int_addr] <= int_wdata_wire; + end + else begin + end + end +end + +property p_illegal_write_addr; + @(posedge avl_clk) + disable iff (!avl_reset_n) + (state == WRITE2) |-> (int_addr < NUM_REGFILE_WORDS); +endproperty + +a_illegal_write_addr : assert property (p_illegal_write_addr); + +generate + if (REGISTER_RDATA) begin + + always_ff @ (posedge avl_clk or negedge avl_reset_n) begin + if (~avl_reset_n) + int_rdata_reg <= 0; + else + int_rdata_reg <= int_rdata; + end + + assign avl_readdata = int_rdata_reg; + end + else + assign avl_readdata = int_rdata; +endgenerate + +// synthesis translate_on + +assign avl_waitrequest = ((state == IDLE) && ((avl_read == 1) || (avl_write == 1))) ? 1'b1 : int_waitrequest; + +// synthesis translate_off +//The register file has a specific word which is expected to be the current +wire [15:0] current_seq_stage; +wire [15:0] current_seq_group; + +assign current_seq_stage = reg_file[DEBUG_REG_FILE_WORD][15:0]; +assign current_seq_group = reg_file[DEBUG_REG_FILE_WORD][31:16]; + +// synthesis translate_on + + +endmodule diff --git a/ip/altera/ddr3/sequencer_scc_acv_phase_decode.v b/ip/altera/ddr3/sequencer_scc_acv_phase_decode.v new file mode 100644 index 0000000..a68c564 --- /dev/null +++ b/ip/altera/ddr3/sequencer_scc_acv_phase_decode.v @@ -0,0 +1,132 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module sequencer_scc_acv_phase_decode + # (parameter + + AVL_DATA_WIDTH = 32, + DLL_DELAY_CHAIN_LENGTH = 8, + USE_2X_DLL = "false" + + ) + ( + + avl_writedata, + dqse_phase + +); + + input [AVL_DATA_WIDTH - 1:0] avl_writedata; + + // Arria V and Cyclone V only have dqse_phase control + + + // phase decoding. + output [3:0] dqse_phase; + reg [3:0] dqse_phase; + +generate +if (USE_2X_DLL == "true") +begin + always @ (*) begin : decode_2x + + dqse_phase = 4'b0111; + + case (avl_writedata[2:0]) + 3'b000: + begin + dqse_phase = 4'b0100; + end + 3'b001: + begin + dqse_phase = 4'b0101; + end + 3'b010: + begin + dqse_phase = 4'b0110; + end + 3'b011: + begin + dqse_phase = 4'b0111; + end + 3'b100: + begin + dqse_phase = 4'b1000; + end + 3'b101: + begin + dqse_phase = 4'b1001; + end + 3'b110: + begin + dqse_phase = 4'b1010; + end + 3'b111: + begin + dqse_phase = 4'b1011; + end + default : begin end + endcase + end + +end +else +begin + always @ (*) begin : decode + + // DQSE = 270 + dqse_phase = 4'b0110; + + case (avl_writedata[2:0]) + 3'b000: // DQSE = 90 + begin + dqse_phase = 4'b0010; + end + 3'b001: // DQSE = 135 + begin + dqse_phase = 4'b0011; + end + 3'b010: // DQSE = 180 + begin + dqse_phase = 4'b0100; + end + 3'b011: // DQSE = 225 + begin + dqse_phase = 4'b0101; + end + 3'b100: // DQSE = 270 + begin + dqse_phase = 4'b0110; + end + 3'b101: // DQSE = 315 + begin + dqse_phase = 4'b1111; + end + 3'b110: // DQSE = 360 + begin + dqse_phase = 4'b1000; + end + 3'b111: // DQSE = 405 + begin + dqse_phase = 4'b1001; + end + default : begin end + endcase + end +end +endgenerate + +endmodule diff --git a/ip/altera/ddr3/sequencer_scc_acv_wrapper.sv b/ip/altera/ddr3/sequencer_scc_acv_wrapper.sv new file mode 100644 index 0000000..030427f --- /dev/null +++ b/ip/altera/ddr3/sequencer_scc_acv_wrapper.sv @@ -0,0 +1,146 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +// altera message_off 10230 +module sequencer_scc_acv_wrapper + # (parameter + + DATAWIDTH = 24, + IO_SDATA_BITS = 11, + DQS_SDATA_BITS = 46, + AVL_DATA_WIDTH = 32, + DLL_DELAY_CHAIN_LENGTH = 6, + USE_2X_DLL = "false" + + ) + ( + + reset_n_scc_clk, + scc_clk, + scc_dataout, + scc_io_cfg, + scc_dqs_cfg +); + + input scc_clk; + input reset_n_scc_clk; + input [DATAWIDTH-1:0] scc_dataout; + output [IO_SDATA_BITS - 1:0] scc_io_cfg; + output [DQS_SDATA_BITS - 1:0] scc_dqs_cfg; + + typedef enum integer { + SCC_ADDR_DQS_IN_DELAY = 'b0001, + SCC_ADDR_DQS_EN_PHASE = 'b0010, + SCC_ADDR_DQS_EN_DELAY = 'b0011, + SCC_ADDR_DQDQS_OUT_PHASE= 'b0100, + SCC_ADDR_OCT_OUT1_DELAY = 'b0101, + SCC_ADDR_OCT_OUT2_DELAY = 'b0110, + SCC_ADDR_IO_OUT1_DELAY = 'b0111, + SCC_ADDR_IO_OUT2_DELAY = 'b1000, + SCC_ADDR_IO_IN_DELAY = 'b1001, + SCC_ADDR_DQS_BYPASS = 'b1010, + SCC_ADDR_DQ_BYPASS = 'b1011, + SCC_ADDR_RFIFO_MODE = 'b1100 + } sdata_addr_t; + + wire [DATAWIDTH-1:0] scc_dataout; + reg [IO_SDATA_BITS - 1:0] scc_io_cfg; + reg [DQS_SDATA_BITS - 1:0] scc_dqs_cfg; + + wire [3:0] dqse_phase; + + typedef bit [6:0] t_setting_mask; + + integer unsigned setting_offsets[1:12] = '{ 'd0, 'd5, 'd8, 'd13, 'd13, 'd18, 'd0, 'd5, 'd5 , 'd18, 'd10, 'd11}; + t_setting_mask setting_masks [1:12] = '{ 'b011111, 'b0111, 'b011111, 'b0, 'b011111, 'b0, 'b011111, 'b0, 'b011111, 'b01, 'b01, 'b0111 }; + + // decode phases + + sequencer_scc_acv_phase_decode # ( + .AVL_DATA_WIDTH (DATAWIDTH ), + .DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH ), + .USE_2X_DLL (USE_2X_DLL) + ) sequencer_scc_phase_decode_dqe_inst ( + .avl_writedata ((scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_PHASE]) & setting_masks[SCC_ADDR_DQS_EN_PHASE]), + .dqse_phase (dqse_phase ) + ); + + always_ff @ (posedge scc_clk or negedge reset_n_scc_clk) begin + if (~reset_n_scc_clk) begin + scc_io_cfg <= '0; + scc_dqs_cfg <= '0; + end + else begin + scc_io_cfg <= '0; + scc_dqs_cfg <= '0; + + + // DQS + + // T11 Ungating (using same as T11 Gating for now) + scc_dqs_cfg[4:0] <= (scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]) & ({'0, setting_masks[SCC_ADDR_DQS_EN_DELAY]}); + + // T11 Gating (using same as T11 ungating for now) + scc_dqs_cfg[9:5] <= (scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]) & ({'0, setting_masks[SCC_ADDR_DQS_EN_DELAY]}); + + scc_dqs_cfg[10] <= dqse_phase[3]; + + scc_dqs_cfg[15:11] <= (scc_dataout >> setting_offsets[SCC_ADDR_OCT_OUT1_DELAY]) & ({'0, setting_masks[SCC_ADDR_OCT_OUT1_DELAY]}); + + // Bypass DQS Logic half-rate (0 engage, 1 bypass) + scc_dqs_cfg[16] <= (scc_dataout >> setting_offsets[SCC_ADDR_DQS_BYPASS]) & ({'0, setting_masks[SCC_ADDR_DQS_BYPASS]}); + + scc_dqs_cfg[21:17] <= (scc_dataout >> setting_offsets[SCC_ADDR_DQS_IN_DELAY]) & ({'0, setting_masks[SCC_ADDR_DQS_IN_DELAY]}); + + scc_dqs_cfg[22] <= dqse_phase[2]; + + scc_dqs_cfg[24:23] <= dqse_phase[1:0]; + + + // I/O + + scc_io_cfg[4:0] <= (scc_dataout >> setting_offsets[SCC_ADDR_IO_IN_DELAY]) & ({'0, setting_masks[SCC_ADDR_IO_IN_DELAY]}); + + // T9 OE (using same as T9 output) + scc_io_cfg[9:5] <= (scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT1_DELAY]) & ({'0, setting_masks[SCC_ADDR_IO_OUT1_DELAY]}); + + // T9 output (using same as T9 OE) + scc_io_cfg[14:10] <= (scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT1_DELAY]) & ({'0, setting_masks[SCC_ADDR_IO_OUT1_DELAY]}); + + // Input register Read Fifo mode: + // 000: half-rate read fifo + // 001: full-rate read fifo + // 010: deserializer bit slip + // 011: deserializer with input from bit-slip + // 100: deserializer with input from IO + // 101: serializer mode + scc_io_cfg[17:15] <= (scc_dataout >> setting_offsets[SCC_ADDR_RFIFO_MODE]) & ({'0, setting_masks[SCC_ADDR_RFIFO_MODE]}); + + // Read FIFO Read Clock Source Select + // 00: Select core CLKIN1 + // 01: Select DQS_CLK (PHY_CLK) + // 10: Select SEQ_HR_CLK (PHY_CLK) + // 11: Select VCC (Disabled) + scc_io_cfg[19:18] <= (((scc_dataout >> setting_offsets[SCC_ADDR_RFIFO_MODE]) & ({'0, setting_masks[SCC_ADDR_RFIFO_MODE]})) == 3'b001) ? 2'b01 : 2'b10; + + // bypass IOE Register half-rate register + // 0: engage half-rate register + // 1: bypass half-rate register + scc_io_cfg[20] <= (scc_dataout >> setting_offsets[SCC_ADDR_DQ_BYPASS]) & ({'0, setting_masks[SCC_ADDR_DQ_BYPASS]}); + end + end + +endmodule diff --git a/ip/altera/ddr3/sequencer_scc_mgr.sv b/ip/altera/ddr3/sequencer_scc_mgr.sv new file mode 100644 index 0000000..d4c1de5 --- /dev/null +++ b/ip/altera/ddr3/sequencer_scc_mgr.sv @@ -0,0 +1,1059 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// ****** +// scc_mgr +// ****** +// +// SCC Manager +// +// General Description +// ------------------- +// +// This component allows the NIOS to control the delay chains in the IOs. +// + +`timescale 1 ps / 1 ps + +// altera message_off 10230 +module sequencer_scc_mgr ( + // Avalon Interface + + avl_clk, + avl_reset_n, + avl_address, + avl_write, + avl_writedata, + avl_read, + avl_readdata, + avl_waitrequest, + + scc_reset_n, + scc_clk, + scc_data, + scc_dqs_ena, + scc_dqs_io_ena, + scc_dq_ena, + scc_dm_ena, + scc_upd, + + scc_sr_dqsenable_delayctrl, + scc_sr_dqsdisablen_delayctrl, + scc_sr_multirank_delayctrl, + + capture_strobe_tracking, + afi_init_req, + afi_cal_req +); + + parameter AVL_DATA_WIDTH = 32; + parameter AVL_ADDR_WIDTH = 13; + + parameter MEM_IF_READ_DQS_WIDTH = 1; + parameter MEM_IF_WRITE_DQS_WIDTH = 1; + parameter MEM_IF_DQ_WIDTH = 36; + parameter MEM_IF_DM_WIDTH = 4; + parameter MEM_NUMBER_OF_RANKS = 1; + + parameter DLL_DELAY_CHAIN_LENGTH = 8; + parameter FAMILY = "STRATIXIII"; + parameter USE_2X_DLL = "false"; + parameter USE_DQS_TRACKING = 0; + parameter USE_SHADOW_REGS = 0; + parameter DUAL_WRITE_CLOCK = 0; + + parameter TRK_PARALLEL_SCC_LOAD = 0; + parameter SCC_DATA_WIDTH = 1; + + localparam MAX_FAMILY_NAME_LEN = 30; + + function integer get_dqs_sdata_bits(input [8*MAX_FAMILY_NAME_LEN-1:0] family); + if (family == "STRATIXV" || family == "ARRIAVGZ") return 101; + else if (family == "ARRIAV" || family == "CYCLONEV") return 30; + else return 46; + endfunction + + function integer get_io_sdata_bits(input [8*MAX_FAMILY_NAME_LEN-1:0] family); + if (family == "STRATIXV" || family == "ARRIAVGZ") return 40; + else if (family == "ARRIAV" || family == "CYCLONEV") return 25; + else return 11; + endfunction + + function integer get_datawidth(input [8*MAX_FAMILY_NAME_LEN-1:0] family); + if (family == "STRATIXV" || family == "ARRIAVGZ") return 42; + else if (family == "ARRIAV" || family == "CYCLONEV") return 19; + else return 24; + endfunction + + + localparam DQS_IN_PHASE_MAX = 3; + localparam DQS_SDATA_BITS = get_dqs_sdata_bits(FAMILY); + localparam IO_SDATA_BITS = get_io_sdata_bits(FAMILY); + localparam DATAWIDTH = get_datawidth(FAMILY); + localparam RFILE_LATENCY = 3; + + localparam MEM_DQ_PER_DQS = (MEM_IF_DQ_WIDTH / MEM_IF_WRITE_DQS_WIDTH); + localparam MEM_DM_PER_DQS = (MEM_IF_DM_WIDTH > MEM_IF_WRITE_DQS_WIDTH) ? (MEM_IF_DM_WIDTH / MEM_IF_WRITE_DQS_WIDTH) : 1; + localparam MEM_DQS_PER_DM = (MEM_IF_DM_WIDTH < MEM_IF_WRITE_DQS_WIDTH) ? (MEM_IF_WRITE_DQS_WIDTH / MEM_IF_DM_WIDTH) : 1; + + localparam RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS + MEM_IF_READ_DQS_WIDTH - 1) + 1; + localparam RFILE_ADDR_WIDTH = 6; + localparam RFILE_USED_DEPTH = (RFILE_DEPTH > RFILE_ADDR_WIDTH) ? RFILE_DEPTH : RFILE_ADDR_WIDTH; + + localparam SCC_UPD_WIDTH = (USE_SHADOW_REGS == 1) ? MEM_IF_READ_DQS_WIDTH : 1; + localparam SAMPLE_COUNTER_WIDTH = 14; + + typedef enum integer { + SCC_SCAN_DQS = 'b0000, + SCC_SCAN_DQS_IO = 'b0001, + SCC_SCAN_DQ_IO = 'b0010, + SCC_SCAN_DM_IO = 'b0011, + SCC_SCAN_UPD = 'b1000 + } sdata_scan_t; + + input avl_clk; + input avl_reset_n; + input [AVL_ADDR_WIDTH - 1:0] avl_address; + input avl_write; + input [AVL_DATA_WIDTH - 1:0] avl_writedata; + input avl_read; + output [AVL_DATA_WIDTH - 1:0] avl_readdata; + output avl_waitrequest; + + input scc_clk; + input scc_reset_n; + output [SCC_DATA_WIDTH - 1:0] scc_data; + output [MEM_IF_READ_DQS_WIDTH - 1:0] scc_dqs_ena; + output [MEM_IF_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena; + output [MEM_IF_DQ_WIDTH - 1:0] scc_dq_ena; + output [MEM_IF_DM_WIDTH - 1:0] scc_dm_ena; + output [SCC_UPD_WIDTH - 1:0] scc_upd; + + output [7:0] scc_sr_dqsenable_delayctrl; + output [7:0] scc_sr_dqsdisablen_delayctrl; + output [7:0] scc_sr_multirank_delayctrl; + + input [MEM_IF_READ_DQS_WIDTH - 1:0] capture_strobe_tracking; + input afi_init_req; + input afi_cal_req; + + // internal versions of interfacing signals. + + reg [AVL_DATA_WIDTH - 1:0] avl_readdata; + reg avl_waitrequest; + + reg [SCC_DATA_WIDTH - 1:0] scc_data; + reg [MEM_IF_READ_DQS_WIDTH - 1:0] scc_dqs_ena; + reg [MEM_IF_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena; + reg [MEM_IF_DQ_WIDTH - 1:0] scc_dq_ena; + reg [MEM_IF_DM_WIDTH - 1:0] scc_dm_ena; + reg [SCC_UPD_WIDTH - 1:0] scc_upd; + + reg scc_data_c; + reg [MEM_IF_READ_DQS_WIDTH - 1:0] scc_dqs_ena_c; + reg [MEM_IF_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena_c; + reg [MEM_IF_DQ_WIDTH - 1:0] scc_dq_ena_c; + reg [MEM_IF_DM_WIDTH - 1:0] scc_dm_ena_c; + reg [SCC_UPD_WIDTH - 1:0] scc_upd_c; + + // IO config register + + reg [IO_SDATA_BITS - 1:0] scc_io_cfg; + reg [IO_SDATA_BITS - 1:0] scc_io_cfg_curr; + reg [IO_SDATA_BITS - 1:0] scc_io_cfg_next; + + // DQS config register + + reg [DQS_SDATA_BITS - 1:0] scc_dqs_cfg; + reg [DQS_SDATA_BITS - 1:0] scc_dqs_cfg_curr; + reg [DQS_SDATA_BITS - 1:0] scc_dqs_cfg_next; + + logic avl_cmd_parallel_scan; + logic [RFILE_ADDR_WIDTH-1:0] parallel_rfile_addr; + logic avl_par_read; + logic avl_load_done; + logic avl_load_done_r; + logic avl_cmd_par_end; + + logic scc_load_done; + logic scc_load_done_r; + logic avl_par_read_r; + logic [RFILE_ADDR_WIDTH-1:0] parallel_group; + logic parallel_cfg_loaded; + logic [SCC_DATA_WIDTH - 1:0] scc_data_p; + logic [DQS_SDATA_BITS - 1:0] scc_dqs_cfg_curr_p [SCC_DATA_WIDTH - 1:0]; + logic [DQS_SDATA_BITS - 1:0] scc_dqs_cfg_next_p [SCC_DATA_WIDTH - 1:0]; + logic scc_parallel; + logic scc_parallel_r; + + // is scc manager selected? + + reg sel_scc; + + // go signal going to the SCC clock side. + reg [3:0] scc_go_ena; + reg [3:0] scc_go_ena_r; + wire scc_go_group; + wire scc_go_io; + wire scc_go_update; + + // enable pattern. + + reg [7:0] scc_ena_addr; + reg [255:0] scc_ena_addr_decode; + + // done signal coming back from the scc side. + + reg scc_done; + + // avalon version of scc done signal + + reg avl_done; + + // tracking signals + reg avl_cmd_trk_afi_end; + wire [AVL_DATA_WIDTH - 1:0] read_sample_counter; + + // SCAN state machine + + typedef enum int unsigned { + STATE_SCC_IDLE, + STATE_SCC_LOAD, + STATE_SCC_DONE + } STATE_SCC_RAM_T; + + STATE_SCC_RAM_T scc_state_curr, scc_state_next; + reg [7:0] scc_shift_cnt_curr; + reg [7:0] scc_shift_cnt_next; + + reg [DATAWIDTH-1:0] datain; + wire [DATAWIDTH-1:0] dataout_sr0; + wire [DATAWIDTH-1:0] dataout_sr1; + wire [DATAWIDTH-1:0] dataout; + wire [RFILE_ADDR_WIDTH-1:0] write_addr; + wire [RFILE_ADDR_WIDTH-1:0] read_addr; + reg [3:0] group; + wire write_en_sr0; + wire write_en_sr1; + + reg [DATAWIDTH-1:0] scc_dataout; + + reg [7:0] group_counter; + wire avl_cmd_group_counter; + wire [3:0] avl_cmd_section; + wire avl_cmd_rfile_group_not_io; + wire [RFILE_ADDR_WIDTH-1:0] avl_cmd_rfile_addr; + + wire avl_cmd_rank; + reg [MEM_NUMBER_OF_RANKS - 1:0] avl_active_rank; + wire avl_active_shadow_reg; + + wire avl_cmd_scan; + wire avl_cmd_scan_begin; + wire avl_cmd_scan_end; + wire [RFILE_ADDR_WIDTH-1:0] avl_cmd_scan_addr; + + reg avl_doing_scan; + reg scc_doing_scan; + reg scc_doing_scan_r; + reg [7:0] scc_group_counter; + + wire avl_cmd_rfile; + wire avl_cmd_rfile_begin; + wire avl_cmd_rfile_end; + reg [RFILE_LATENCY-1:0] avl_cmd_rfile_latency; + + wire track_opr_check; + wire avl_cmd_counter_access; + + wire avl_cmd_afi_req; + + wire [AVL_DATA_WIDTH-1:0] shifted_dataout; + + // metastability flops + reg avl_init_req_r; + reg avl_cal_req_r; + reg avl_init_req_r2; + reg avl_cal_req_r2; + reg avl_init_req_r3; + reg avl_cal_req_r3; + + integer i,j,k,l; + + assign sel_scc = 1'b1; + integer scan_offsets; + + assign avl_cmd_section = avl_address[9:6]; + assign avl_cmd_group_counter = (sel_scc && (avl_cmd_section == 4'b0000)); + assign avl_cmd_rfile_group_not_io = ~(avl_address[9] == 1'b1 || avl_address[9:6] == 4'b0111) | (avl_address[9:6] == 4'b1010); + + assign avl_cmd_rfile = (sel_scc && (avl_address[9:7] != 3'b111) && avl_cmd_section != 4'b0000 && avl_cmd_section != 4'hd); + assign avl_cmd_rfile_begin = (avl_read || avl_write) && (avl_cmd_rfile || avl_cmd_group_counter) && ~(|avl_cmd_rfile_latency); + assign avl_cmd_rfile_end = avl_cmd_rfile_latency[0]; + assign avl_cmd_rfile_addr = {'0, (avl_cmd_rfile_group_not_io ? 0 : MEM_IF_READ_DQS_WIDTH) + avl_address[5:0]}; + + assign avl_cmd_rank = (sel_scc && avl_cmd_section == 4'he && avl_address[4] == 1'b1); + assign avl_cmd_parallel_scan = (avl_write && avl_cmd_section == 4'he && avl_address[10] == 1'b1); + + assign avl_cmd_scan = (sel_scc && avl_cmd_section == 4'he && ~avl_cmd_rank && ~avl_cmd_parallel_scan); + assign avl_cmd_scan_begin = (avl_read || avl_write) && avl_cmd_scan && ~(avl_doing_scan) && ~(avl_done); + assign avl_cmd_scan_end = avl_doing_scan && avl_done; + assign avl_cmd_scan_addr = {'0, scan_offsets + ((avl_writedata[7:0] == 8'hFF) ? 0 : avl_writedata[5:0])}; + + always_comb begin + case(avl_address[1:0]) + 3: scan_offsets = (MEM_IF_READ_DQS_WIDTH + MEM_DQ_PER_DQS + 1); + 2: scan_offsets = (MEM_IF_READ_DQS_WIDTH); + 1: scan_offsets = (MEM_IF_READ_DQS_WIDTH + MEM_DQ_PER_DQS); + default: scan_offsets = '0; + endcase + end + + assign track_opr_check = (avl_address[5:0] == 6'b111111) ? 1'b1 : 0; + assign avl_cmd_counter_access = sel_scc && avl_cmd_section == 4'hF && !track_opr_check; + assign avl_cmd_afi_req = (sel_scc && avl_cmd_section == 4'hd); + + + assign avl_waitrequest = (~avl_reset_n) || ((avl_read || avl_write) && ~avl_cmd_rfile_end && ~avl_cmd_scan_end && ~avl_cmd_trk_afi_end && ~avl_cmd_rank && ~avl_cmd_par_end); + always_comb begin + if (avl_cmd_rank) begin + avl_readdata[AVL_DATA_WIDTH - 1:MEM_NUMBER_OF_RANKS] = '0; + avl_readdata[MEM_NUMBER_OF_RANKS - 1:0] = avl_active_rank; + end else begin + if (avl_cmd_counter_access) + avl_readdata = read_sample_counter; + else + begin + if (avl_cmd_afi_req) + avl_readdata = {avl_cal_req_r3,avl_init_req_r3}; + else + begin + if (avl_cmd_rfile) + avl_readdata = shifted_dataout; + else + avl_readdata = group_counter; + end + end + end + end + + // Assert that the SCC manager only receives broadcast or single bit scan requests for DQS and DM I/Os. + ERROR_DQS_IO_SCAN_WRONG_DATA: + assert property (@(posedge avl_clk) (avl_cmd_scan_begin && avl_address[3:0] == SCC_SCAN_DQS_IO) |-> (avl_writedata[7:0] == 8'hFF || avl_writedata[7:0] == 8'h00)); + ERROR_DM_IO_SCAN_WRONG_DATA: + assert property (@(posedge avl_clk) (avl_cmd_scan_begin && avl_address[3:0] == SCC_SCAN_DM_IO) |-> (avl_writedata[7:0] == 8'hFF || avl_writedata[7:0] < MEM_DM_PER_DQS)); + ERROR_DQS_SCAN_WRONG_DATA: + assert property (@(posedge avl_clk) (avl_cmd_scan_begin && avl_address[3:0] == SCC_SCAN_DQS) |-> (avl_writedata[7:0] == 8'hFF || avl_writedata[7:0] < MEM_IF_READ_DQS_WIDTH)); + ERROR_DQ_IO_SCAN_WRONG_DATA: + assert property (@(posedge avl_clk) (avl_cmd_scan_begin && avl_address[3:0] == SCC_SCAN_DQ_IO) |-> (avl_writedata[7:0] == 8'hFF || avl_writedata[7:0] < MEM_DQ_PER_DQS)); + + + typedef bit [13:0] t_setting_mask; + typedef bit [DATAWIDTH+1:0] t_setting_shifted_mask; + + integer unsigned setting_offsets[1:12]; + t_setting_shifted_mask setting_masks_lshift [1:12]; + t_setting_mask setting_masks [1:12]; + + generate + if (FAMILY == "STRATIXV" || FAMILY == "ARRIAVGZ") + begin + assign setting_offsets[1] = 'd0; + assign setting_offsets[2] = 'd12; + assign setting_offsets[3] = 'd17; + assign setting_offsets[4] = 'd25; + assign setting_offsets[5] = 'd30; + assign setting_offsets[6] = 'd36; + assign setting_offsets[7] = 'd0; + assign setting_offsets[8] = 'd6; + assign setting_offsets[9] = 'd12; + assign setting_offsets[10] = 'd0; + assign setting_offsets[11] = 'd0; + assign setting_offsets[12] = 'd0; + + assign setting_masks_lshift [1] = 'b0111111111111; + assign setting_masks_lshift [2] = 'b011111000000000000; + assign setting_masks_lshift [3] = 'b01111111100000000000000000; + assign setting_masks_lshift [4] = 'b0111110000000000000000000000000; + assign setting_masks_lshift [5] = 37'b0111111000000000000000000000000000000; + assign setting_masks_lshift [6] = 43'b0111111000000000000000000000000000000000000; + assign setting_masks_lshift [7] = 'b0111111; + assign setting_masks_lshift [8] = 'b0111111000000; + assign setting_masks_lshift [9] = 'b0111111111111000000000000; + assign setting_masks_lshift [10] = 'b0; + assign setting_masks_lshift [11] = 'b0; + assign setting_masks_lshift [12] = 'b0; + + assign setting_masks [1] = 'b0111111111111; + assign setting_masks [2] = 'b011111; + assign setting_masks [3] = 'b011111111; + assign setting_masks [4] = 'b011111; + assign setting_masks [5] = 'b0111111; + assign setting_masks [6] = 'b0111111; + assign setting_masks [7] = 'b0111111; + assign setting_masks [8] = 'b0111111; + assign setting_masks [9] = 'b0111111111111; + assign setting_masks [10] = 'b0; + assign setting_masks [11] = 'b0; + assign setting_masks [12] = 'b0; + end + else if (FAMILY == "ARRIAV" || FAMILY == "CYCLONEV") + begin + assign setting_offsets[1] = 'd0; + assign setting_offsets[2] = 'd5; + assign setting_offsets[3] = 'd8; + assign setting_offsets[4] = 'd13; + assign setting_offsets[5] = 'd13; + assign setting_offsets[6] = 'd18; + assign setting_offsets[7] = 'd0; + assign setting_offsets[8] = 'd5; + assign setting_offsets[9] = 'd5; + assign setting_offsets[10] = 'd18; + assign setting_offsets[11] = 'd10; + assign setting_offsets[12] = 'd11; + + assign setting_masks_lshift [1] = 'b011111; + assign setting_masks_lshift [2] = 'b011100000; + assign setting_masks_lshift [3] = 'b01111100000000; + assign setting_masks_lshift [4] = 'b0; + assign setting_masks_lshift [5] = 'b0111110000000000000; + assign setting_masks_lshift [6] = 'b0; + assign setting_masks_lshift [7] = 'b011111; + assign setting_masks_lshift [8] = 'b0; + assign setting_masks_lshift [9] = 'b01111100000; + assign setting_masks_lshift [10] = 'b01000000000000000000; + assign setting_masks_lshift [11] = 'b010000000000; + assign setting_masks_lshift [12] = 'b011100000000000; + + assign setting_masks [1] = 'b011111; + assign setting_masks [2] = 'b0111; + assign setting_masks [3] = 'b011111; + assign setting_masks [4] = 'b0; + assign setting_masks [5] = 'b011111; + assign setting_masks [6] = 'b0; + assign setting_masks [7] = 'b011111; + assign setting_masks [8] = 'b0; + assign setting_masks [9] = 'b011111; + assign setting_masks [10] = 'b01; + assign setting_masks [11] = 'b01; + assign setting_masks [12] = 'b0111; + end + else + begin + assign setting_offsets[1] = 'd0; + assign setting_offsets[2] = 'd4; + assign setting_offsets[3] = 'd8; + assign setting_offsets[4] = 'd12; + assign setting_offsets[5] = 'd17; + assign setting_offsets[6] = 'd21; + assign setting_offsets[7] = 'd0; + assign setting_offsets[8] = 'd4; + assign setting_offsets[9] = 'd7; + assign setting_offsets[10] = 'd0; + assign setting_offsets[11] = 'd0; + assign setting_offsets[12] = 'd0; + + assign setting_masks_lshift [1] = 'b01111; + assign setting_masks_lshift [2] = 'b011110000; + assign setting_masks_lshift [3] = 'b0111100000000; + assign setting_masks_lshift [4] = 'b11111000000000000; + assign setting_masks_lshift [5] = 'b0111100000000000000000; + assign setting_masks_lshift [6] = 'b00111000000000000000000000; + assign setting_masks_lshift [7] = 'b01111; + assign setting_masks_lshift [8] = 'b001110000; + assign setting_masks_lshift [9] = 'b011110000000; + assign setting_masks_lshift [10] = 'b0; + assign setting_masks_lshift [11] = 'b0; + assign setting_masks_lshift [12] = 'b0; + + assign setting_masks [1] = 'b01111; + assign setting_masks [2] = 'b01111; + assign setting_masks [3] = 'b01111; + assign setting_masks [4] = 'b11111; + assign setting_masks [5] = 'b01111; + assign setting_masks [6] = 'b00111; + assign setting_masks [7] = 'b01111; + assign setting_masks [8] = 'b00111; + assign setting_masks [9] = 'b01111; + assign setting_masks [10] = 'b0; + assign setting_masks [11] = 'b0; + assign setting_masks [12] = 'b0; + end + endgenerate + + always_ff @(posedge avl_clk or negedge avl_reset_n) + begin + if (~avl_reset_n) + begin + avl_active_rank <= '0; + end + else begin + if (avl_cmd_rank && avl_write) begin + avl_active_rank <= avl_writedata[MEM_NUMBER_OF_RANKS - 1:0]; + end + end + end + + always_ff @(posedge avl_clk or negedge avl_reset_n) + begin + if (~avl_reset_n) + begin + avl_cmd_rfile_latency <= 0; + avl_doing_scan <= 0; + end + else begin + avl_cmd_rfile_latency <= {avl_cmd_rfile_begin, avl_cmd_rfile_latency[RFILE_LATENCY - 1 : 1]}; + avl_doing_scan <= (avl_cmd_scan_begin || avl_doing_scan) && ~avl_done; + end + end + + always_ff @(posedge avl_clk or negedge avl_reset_n) + begin + if (!avl_reset_n) + begin + avl_cmd_par_end <= 0; + parallel_rfile_addr <= 0; + avl_par_read <= 0; + avl_load_done <= 0; + avl_load_done_r <= 0; + end + else + begin + if (avl_cmd_parallel_scan && !avl_cmd_par_end && avl_done) + avl_cmd_par_end <= ~avl_cmd_par_end; + else + avl_cmd_par_end <= 0; + + avl_load_done <= scc_load_done; + avl_load_done_r <= avl_load_done; + + if (avl_cmd_parallel_scan) + begin + if (parallel_rfile_addr < SCC_DATA_WIDTH && avl_par_read && avl_load_done_r) + parallel_rfile_addr <= parallel_rfile_addr + 1'b1; + end + else + parallel_rfile_addr <= 0; + + if (!avl_par_read) + begin + if (avl_cmd_parallel_scan && parallel_rfile_addr < SCC_DATA_WIDTH && !avl_load_done_r) + avl_par_read <= ~avl_par_read; + end + else + begin + if (avl_load_done_r) + avl_par_read <= ~avl_par_read; + end + end + end + + assign read_addr = avl_cmd_parallel_scan ? parallel_rfile_addr : (avl_cmd_scan ? avl_cmd_scan_addr : avl_cmd_rfile_addr); + assign write_addr = avl_cmd_rfile_addr; + + assign datain = (dataout & (~setting_masks_lshift[avl_cmd_section])) | ((setting_masks[avl_cmd_section] & avl_writedata) << setting_offsets[avl_cmd_section]); + + assign shifted_dataout = (dataout >> setting_offsets[avl_cmd_section]) & setting_masks[avl_cmd_section]; + + // config data storage + + + sequencer_scc_reg_file #( + .WIDTH (DATAWIDTH), + .DEPTH (RFILE_USED_DEPTH) + ) sequencer_scc_reg_file_inst ( + .clock (avl_clk ), + .data (datain ), + .rdaddress (read_addr ), + .wraddress (write_addr ), + .wren (write_en_sr0), + .q (dataout_sr0) + ); + + generate + if (USE_SHADOW_REGS == 1) begin + + sequencer_scc_reg_file #( + .WIDTH (DATAWIDTH), + .DEPTH (RFILE_USED_DEPTH) + ) sequencer_scc_reg_file_inst1 ( + .clock (avl_clk ), + .data (datain ), + .rdaddress (read_addr ), + .wraddress (write_addr ), + .wren (write_en_sr1), + .q (dataout_sr1) + ); + + assign avl_active_shadow_reg = | avl_active_rank[MEM_NUMBER_OF_RANKS - 1 : MEM_NUMBER_OF_RANKS / 2]; + + assign write_en_sr0 = avl_cmd_rfile && avl_write && avl_cmd_rfile_latency[1] && (avl_active_shadow_reg == 1'b0); + assign write_en_sr1 = avl_cmd_rfile && avl_write && avl_cmd_rfile_latency[1] && (avl_active_shadow_reg == 1'b1); + assign dataout = (avl_active_shadow_reg == 1'b0 ? dataout_sr0 : dataout_sr1); + + end else begin + assign write_en_sr0 = avl_cmd_rfile && avl_write && avl_cmd_rfile_latency[1]; + assign dataout = dataout_sr0; + end + endgenerate + + always_ff @(posedge avl_clk or negedge avl_reset_n) + begin + if (~avl_reset_n) + begin + group_counter <= '0; + end + else begin + if (avl_cmd_group_counter && avl_write) + begin + group_counter <= avl_writedata; + end + end + end + + always_ff @(posedge scc_clk or negedge scc_reset_n) + begin + if (~scc_reset_n) + begin + scc_dataout <= 0; + scc_doing_scan <= 0; + scc_doing_scan_r <= 0; + end + else begin + scc_dataout <= dataout; + scc_doing_scan <= avl_doing_scan; + scc_doing_scan_r <= scc_doing_scan || (avl_cmd_parallel_scan && parallel_cfg_loaded); + end + end + + // family specific decoder + generate + if (FAMILY == "STRATIXV" || FAMILY == "ARRIAVGZ") + begin + sequencer_scc_sv_wrapper # ( + .DATAWIDTH (DATAWIDTH ), + .IO_SDATA_BITS (IO_SDATA_BITS ), + .DQS_SDATA_BITS (DQS_SDATA_BITS ), + .AVL_DATA_WIDTH (AVL_DATA_WIDTH ), + .DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH ), + .DUAL_WRITE_CLOCK (DUAL_WRITE_CLOCK) + ) sequencer_scc_family_wrapper ( + .reset_n_scc_clk (scc_reset_n ), + .scc_clk (scc_clk ), + .scc_dataout (scc_dataout ), + .scc_io_cfg (scc_io_cfg ), + .scc_dqs_cfg (scc_dqs_cfg ), + .scc_sr_dqsenable_delayctrl (scc_sr_dqsenable_delayctrl ), + .scc_sr_dqsdisablen_delayctrl (scc_sr_dqsdisablen_delayctrl ), + .scc_sr_multirank_delayctrl (scc_sr_multirank_delayctrl ) + ); + end + else if (FAMILY == "ARRIAV" || FAMILY == "CYCLONEV") + begin + assign scc_sr_dqsenable_delayctrl = '0; + assign scc_sr_dqsdisablen_delayctrl = '0; + assign scc_sr_multirank_delayctrl = '0; + + sequencer_scc_acv_wrapper # ( + .DATAWIDTH (DATAWIDTH ), + .IO_SDATA_BITS (IO_SDATA_BITS ), + .DQS_SDATA_BITS (DQS_SDATA_BITS ), + .AVL_DATA_WIDTH (AVL_DATA_WIDTH ), + .DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH ), + .USE_2X_DLL (USE_2X_DLL) + ) sequencer_scc_family_wrapper ( + .reset_n_scc_clk (scc_reset_n ), + .scc_clk (scc_clk ), + .scc_dataout (scc_dataout ), + .scc_io_cfg (scc_io_cfg ), + .scc_dqs_cfg (scc_dqs_cfg ) + ); + end + else + begin + + assign scc_sr_dqsenable_delayctrl = '0; + assign scc_sr_dqsdisablen_delayctrl = '0; + assign scc_sr_multirank_delayctrl = '0; + + sequencer_scc_siii_wrapper # ( + .DATAWIDTH (DATAWIDTH ), + .IO_SDATA_BITS (IO_SDATA_BITS ), + .DQS_SDATA_BITS (DQS_SDATA_BITS ), + .AVL_DATA_WIDTH (AVL_DATA_WIDTH ), + .DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH ) + ) sequencer_scc_family_wrapper ( + .reset_n_scc_clk (scc_reset_n ), + .scc_clk (scc_clk ), + .scc_dataout (scc_dataout ), + .scc_io_cfg (scc_io_cfg ), + .scc_dqs_cfg (scc_dqs_cfg ) + ); + end + endgenerate + + // data transfer from SCC to AVALON + + always_ff @ (posedge avl_clk) begin + avl_done <= scc_done; + end + + // scan chain side state update + // scan chain state machine transitions. + + always_ff @ (posedge scc_clk or negedge scc_reset_n) begin + if (~scc_reset_n) begin + scc_go_ena <= '0; + scc_go_ena_r <= '0; + scc_ena_addr <= '0; + scc_io_cfg_curr <= '0; + scc_dqs_cfg_curr <= '0; + scc_shift_cnt_curr <= '0; + scc_state_curr <= STATE_SCC_IDLE; + scc_group_counter <= '0; + for (k=0; k> log2(MEM_DQS_PER_DM)); + else + scc_ena_addr_decode[(scc_group_counter >> log2(MEM_DQS_PER_DM)) * MEM_DM_PER_DQS + scc_ena_addr] = 1; + end + else begin + if (scc_ena_addr == 8'b11111111) + scc_ena_addr_decode = '1; + else + scc_ena_addr_decode[scc_group_counter] = 1; + end + + scc_state_next = scc_state_curr; + scc_shift_cnt_next = '0; + scc_io_cfg_next = scc_io_cfg; + scc_dqs_cfg_next = scc_dqs_cfg; + scc_data_c = 0; + scc_dqs_ena_c = '0; + scc_dqs_io_ena_c = '0; + scc_dq_ena_c = '0; + scc_dm_ena_c = '0; + scc_upd_c = '0; + scc_done = 0; + scc_data_p = '0; + for (j=0; j> 1; + + for (j=0; j> 1; + end + end + else + begin + scc_data_c = scc_dqs_cfg_curr[DQS_SDATA_BITS - 1]; + scc_dqs_cfg_next = scc_dqs_cfg_curr << 1; + + for (j=0; j> 1; + end + else + begin + scc_data_c = scc_io_cfg_curr[IO_SDATA_BITS - 1]; + scc_io_cfg_next = scc_io_cfg_curr << 1; + end + end + + if (scc_shift_cnt_curr == 0) begin + scc_state_next = STATE_SCC_DONE; + end + end + STATE_SCC_DONE: begin + scc_done = 1; + + if (~scc_doing_scan_r) + scc_state_next = STATE_SCC_IDLE; + end + default : begin end + endcase + end + + always_ff @(posedge avl_clk, negedge avl_reset_n) + begin + if (~avl_reset_n) + avl_cmd_trk_afi_end <= 1'b0; + else + begin + if (sel_scc && (avl_cmd_section == 4'hF || avl_cmd_section == 4'hd) && (avl_write || avl_read) && ~avl_cmd_trk_afi_end) + avl_cmd_trk_afi_end <= 1'b1; + else + avl_cmd_trk_afi_end <= 1'b0; + end + end + + generate + wire avl_cmd_do_sample; + if (USE_DQS_TRACKING == 1) + begin + assign avl_cmd_do_sample = (avl_write && sel_scc && avl_cmd_section == 4'hF && track_opr_check && avl_cmd_trk_afi_end); + end + + if (USE_DQS_TRACKING == 1) + begin + reg [MEM_IF_READ_DQS_WIDTH - 1:0] capture_strobe_tracking_r; + reg signed [SAMPLE_COUNTER_WIDTH - 1:0] sample_counter [MEM_IF_READ_DQS_WIDTH - 1:0]; + assign read_sample_counter = {{(AVL_DATA_WIDTH-SAMPLE_COUNTER_WIDTH){sample_counter[avl_address[5:0]][SAMPLE_COUNTER_WIDTH - 1]}},sample_counter[avl_address[5:0]]}; + + always_ff @(posedge avl_clk, negedge avl_reset_n) + begin + if (~avl_reset_n) + capture_strobe_tracking_r <= 1'b0; + else + capture_strobe_tracking_r <= capture_strobe_tracking; + end + + always_ff @(posedge avl_clk, negedge avl_reset_n) + begin + if (~avl_reset_n) + begin + for (i=0; i> setting_offsets[SCC_ADDR_DQS_EN_PHASE]) & setting_masks[SCC_ADDR_DQS_EN_PHASE]), + .dqsi_phase (dqsi_phase ), + .dqse_phase (dqse_phase ) + ); + + sequencer_scc_siii_phase_decode # ( + .AVL_DATA_WIDTH (AVL_DATA_WIDTH ), + .DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH ) + ) sequencer_scc_phase_decode_dqdqs_inst ( + .avl_writedata ((scc_dataout >> setting_offsets[SCC_ADDR_DQDQS_OUT_PHASE]) & setting_masks[SCC_ADDR_DQDQS_OUT_PHASE]), + .dqs_phase (dqs_phase ), + .dq_phase (dq_phase ) + ); + + always_ff @ (posedge scc_clk or negedge reset_n_scc_clk) begin + if (~reset_n_scc_clk) begin + scc_io_cfg <= '0; + scc_dqs_cfg <= '0; + end + else begin + scc_dqs_cfg[23:19] <= '0; + scc_dqs_cfg[25] <= '0; + scc_dqs_cfg[37] <= '0; + scc_dqs_cfg[42:41] <= '0; + + scc_dqs_cfg[6:4] <= dqsi_phase; + + scc_dqs_cfg[3:0] <= maskTo4Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_IN_DELAY]); + scc_dqs_cfg[29:27] <= maskTo3Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]); + scc_dqs_cfg[33:30] <= maskTo4Bits(scc_dataout >> setting_offsets[SCC_ADDR_OCT_OUT1_DELAY]); + scc_dqs_cfg[36:34] <= maskTo3Bits(scc_dataout >> setting_offsets[SCC_ADDR_OCT_OUT2_DELAY]); + scc_dqs_cfg[10:7] <= dqse_phase[5:2]; + scc_dqs_cfg[43] <= dqse_phase[1]; + scc_dqs_cfg[38] <= dqse_phase[0]; + scc_dqs_cfg[14:11] <= dqs_phase[6:3]; + scc_dqs_cfg[45] <= dqs_phase[2]; + scc_dqs_cfg[39] <= dqs_phase[1]; + scc_dqs_cfg[24] <= dqs_phase[0]; + scc_dqs_cfg[18:15] <= dq_phase[6:3]; + scc_dqs_cfg[44] <= dq_phase[2]; + scc_dqs_cfg[40] <= dq_phase[1]; + scc_dqs_cfg[26] <= dq_phase[0]; + + scc_io_cfg[3:0] <= maskTo4Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT1_DELAY]); + scc_io_cfg[6:4] <= maskTo3Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT2_DELAY]); + scc_io_cfg[10:7] <= maskTo4Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_IN_DELAY]); + end + end + + function[2:0] maskTo3Bits; + input[DATAWIDTH-1:0] i; + maskTo3Bits = i[2:0]; + endfunction + + function[3:0] maskTo4Bits; + input[DATAWIDTH-1:0] i; + maskTo4Bits = i[3:0]; + endfunction + +endmodule diff --git a/ip/altera/ddr3/sequencer_scc_sv_phase_decode.v b/ip/altera/ddr3/sequencer_scc_sv_phase_decode.v new file mode 100644 index 0000000..9f0741d --- /dev/null +++ b/ip/altera/ddr3/sequencer_scc_sv_phase_decode.v @@ -0,0 +1,178 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module sequencer_scc_sv_phase_decode + # (parameter + + AVL_DATA_WIDTH = 32, + DLL_DELAY_CHAIN_LENGTH = 6 + + ) + ( + + avl_writedata, + + dqsi_phase, + dqs_phase, + dq_phase, + dqse_phase + +); + + input [AVL_DATA_WIDTH - 1:0] avl_writedata; + + output [2:0] dqsi_phase; + output [6:0] dqs_phase; + output [6:0] dq_phase; + output [5:0] dqse_phase; + + + reg [2:0] dqsi_phase; + reg [6:0] dqs_phase; + reg [6:0] dq_phase; + reg [5:0] dqse_phase; + + + always @ (*) begin + dqsi_phase = 3'b010; + dqs_phase = 7'b1110110; + dq_phase = 7'b0110100; + dqse_phase = 6'b000110; + + case (avl_writedata[4:0]) + 5'b00000: // DQS = 180, DQ = 90, DQSE = 90 + begin + dqs_phase = 7'b0010110; + dq_phase = 7'b1000110; + dqse_phase = 6'b000010; + end + 5'b00001: // DQS = 225, DQ = 135, DQSE = 135 + begin + dqs_phase = 7'b0110110; + dq_phase = 7'b1100110; + dqse_phase = 6'b000011; + end + 5'b00010: // DQS = 270, DQ = 180, DQSE = 180 + begin + dqs_phase = 7'b1010110; + dq_phase = 7'b0010110; + dqse_phase = 6'b000100; + end + 5'b00011: // DQS = 315, DQ = 225, DQSE = 225 + begin + dqs_phase = 7'b1110111; + dq_phase = 7'b0110110; + dqse_phase = 6'b000101; + end + 5'b00100: // DQS = 360, DQ = 270, DQSE = 270 + begin + dqs_phase = 7'b0000111; + dq_phase = 7'b1010110; + dqse_phase = 6'b000110; + end + 5'b00101: // DQS = 405, DQ = 315, DQSE = 315 + begin + dqs_phase = 7'b0100111; + dq_phase = 7'b1110111; + dqse_phase = 6'b001111; + end + 5'b00110: // DQS = 450, DQ = 360, DQSE = 360 + begin + dqs_phase = 7'b1001000; + dq_phase = 7'b0000111; + dqse_phase = 6'b001000; + end + 5'b00111: // DQS = 495, DQ = 405, DQSE = 405 + begin + dqs_phase = 7'b1101000; + dq_phase = 7'b0100111; + dqse_phase = 6'b001001; + end + 5'b01000: // DQS = 540, DQ = 450 + begin + dqs_phase = 7'b0011000; + dq_phase = 7'b1001000; + end + 5'b01001: + begin + dqs_phase = 7'b0111000; + dq_phase = 7'b1101000; + end + 5'b01010: + begin + dqs_phase = 7'b1011000; + dq_phase = 7'b0011000; + end + 5'b01011: + begin + dqs_phase = 7'b1111001; + dq_phase = 7'b0111000; + end + 5'b01100: + begin + dqs_phase = 7'b0001001; + dq_phase = 7'b1011000; + end + 5'b01101: + begin + dqs_phase = 7'b0101001; + dq_phase = 7'b1111001; + end + 5'b01110: + begin + dqs_phase = 7'b1001010; + dq_phase = 7'b0001001; + end + 5'b01111: + begin + dqs_phase = 7'b1101010; + dq_phase = 7'b0101001; + end + 5'b10000: + begin + dqs_phase = 7'b0011010; + dq_phase = 7'b1001010; + end + 5'b10001: + begin + dqs_phase = 7'b0111010; + dq_phase = 7'b1101010; + end + 5'b10010: + begin + dqs_phase = 7'b1011010; + dq_phase = 7'b0011010; + end + 5'b10011: + begin + dqs_phase = 7'b1111011; + dq_phase = 7'b0111010; + end + 5'b10100: + begin + dqs_phase = 7'b0001011; + dq_phase = 7'b1011010; + end + 5'b10101: + begin + dqs_phase = 7'b0101011; + dq_phase = 7'b1111011; + end + default : begin end + endcase + end + +endmodule diff --git a/ip/altera/ddr3/sequencer_scc_sv_wrapper.sv b/ip/altera/ddr3/sequencer_scc_sv_wrapper.sv new file mode 100644 index 0000000..bf1a81f --- /dev/null +++ b/ip/altera/ddr3/sequencer_scc_sv_wrapper.sv @@ -0,0 +1,219 @@ +// (C) 2001-2015 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module sequencer_scc_sv_wrapper + # (parameter + + DATAWIDTH = 24, + IO_SDATA_BITS = 11, + DQS_SDATA_BITS = 46, + AVL_DATA_WIDTH = 32, + DLL_DELAY_CHAIN_LENGTH = 6, + DUAL_WRITE_CLOCK = 0 + + ) + ( + + reset_n_scc_clk, + scc_clk, + scc_dataout, + scc_io_cfg, + scc_dqs_cfg, + scc_sr_dqsenable_delayctrl, + scc_sr_dqsdisablen_delayctrl, + scc_sr_multirank_delayctrl +); + + input scc_clk; + input reset_n_scc_clk; + input [DATAWIDTH-1:0] scc_dataout; + output [IO_SDATA_BITS - 1:0] scc_io_cfg; + output [DQS_SDATA_BITS - 1:0] scc_dqs_cfg; + + output [7:0] scc_sr_dqsenable_delayctrl; + output [7:0] scc_sr_dqsdisablen_delayctrl; + output [7:0] scc_sr_multirank_delayctrl; + + typedef enum integer { + SCC_ADDR_DQS_IN_DELAY = 'b0001, + SCC_ADDR_DQS_EN_PHASE = 'b0010, + SCC_ADDR_DQS_EN_DELAY = 'b0011, + SCC_ADDR_DQDQS_OUT_PHASE= 'b0100, + SCC_ADDR_OCT_OUT1_DELAY = 'b0101, + SCC_ADDR_OCT_OUT2_DELAY = 'b0110, + SCC_ADDR_IO_OUT1_DELAY = 'b0111, + SCC_ADDR_IO_OUT2_DELAY = 'b1000, + SCC_ADDR_IO_IN_DELAY = 'b1001 + } sdata_addr_t; + + wire [DATAWIDTH-1:0] scc_dataout; + reg [IO_SDATA_BITS - 1:0] scc_io_cfg; + reg [DQS_SDATA_BITS - 1:0] scc_dqs_cfg; + reg [7:0] scc_sr_dqsenable_delayctrl; + reg [7:0] scc_sr_dqsdisablen_delayctrl; + reg [7:0] scc_sr_multirank_delayctrl; + + wire [2:0] dqsi_phase; + wire [5:0] dqse_phase; + wire [6:0] dqs_phase; + wire [6:0] dq_phase; + + typedef bit [13:0] t_setting_mask; + + integer unsigned setting_offsets[1:9] = '{ 'd0, 'd12, 'd17, 'd25, 'd30, 'd36, 'd0, 'd6, 'd12 }; + t_setting_mask setting_masks [1:9] = '{ 'b0111111111111, 'b011111, 'b011111111, 'b011111, 'b0111111, 'b0111111, 'b0111111, 'b0111111, 'b0111111111111 }; + + // decode phases + + sequencer_scc_sv_phase_decode # ( + .AVL_DATA_WIDTH (DATAWIDTH ), + .DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH ) + ) sequencer_scc_phase_decode_dqe_inst ( + .avl_writedata ((scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_PHASE]) & setting_masks[SCC_ADDR_DQS_EN_PHASE]), + .dqsi_phase (dqsi_phase ), + .dqse_phase (dqse_phase ), + .dqs_phase(), + .dq_phase() + ); + + sequencer_scc_sv_phase_decode # ( + .AVL_DATA_WIDTH (DATAWIDTH ), + .DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH ) + ) sequencer_scc_phase_decode_dqdqs_inst ( + .avl_writedata ((scc_dataout >> setting_offsets[SCC_ADDR_DQDQS_OUT_PHASE]) & setting_masks[SCC_ADDR_DQDQS_OUT_PHASE]), + .dqs_phase (dqs_phase ), + .dq_phase (dq_phase ), + .dqsi_phase(), + .dqse_phase() + ); + + always_ff @ (posedge scc_clk or negedge reset_n_scc_clk) begin + if (~reset_n_scc_clk) begin + scc_io_cfg <= '0; + scc_dqs_cfg <= '0; + + scc_sr_dqsenable_delayctrl <= '0; + scc_sr_dqsdisablen_delayctrl <= '0; + scc_sr_multirank_delayctrl <= '0; + + scc_dqs_cfg[26] <= '1; + scc_dqs_cfg[30] <= '1; + scc_dqs_cfg[35] <= '1; + scc_dqs_cfg[39] <= '1; + scc_dqs_cfg[44] <= '1; + scc_dqs_cfg[48] <= '1; + scc_dqs_cfg[53] <= '1; + scc_dqs_cfg[57] <= '1; + scc_dqs_cfg[63] <= '1; + + end + else begin + scc_dqs_cfg <= '0; + + scc_dqs_cfg[26] <= '1; + scc_dqs_cfg[30] <= '1; + scc_dqs_cfg[35] <= '1; + scc_dqs_cfg[39] <= '1; + scc_dqs_cfg[44] <= '1; + scc_dqs_cfg[48] <= '1; + scc_dqs_cfg[53] <= '1; + scc_dqs_cfg[57] <= '1; + scc_dqs_cfg[63] <= '1; + + + scc_dqs_cfg[88:87] <= dqsi_phase[1:0]; + + scc_dqs_cfg[11:0] <= maskTo12Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_IN_DELAY]); + scc_dqs_cfg[85:78] <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]); + scc_dqs_cfg[77:70] <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]); + scc_dqs_cfg[17:12] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_OCT_OUT1_DELAY]); + scc_dqs_cfg[23:18] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_OCT_OUT2_DELAY]); + + + scc_dqs_cfg[42:41] <= dqse_phase[1:0]; + + scc_dqs_cfg[45] <= dqse_phase[2]; + scc_dqs_cfg[86] <= dqse_phase[3]; + if (DUAL_WRITE_CLOCK) begin + scc_dqs_cfg[29:28] <= dqs_phase[6:5]; + scc_dqs_cfg[31] <= dqs_phase[4]; + scc_dqs_cfg[69] <= dqs_phase[0]; + scc_dqs_cfg[89] <= dqs_phase[0]; + + scc_dqs_cfg[68:66] <= dqs_phase[3:1]; + scc_dqs_cfg[93:91] <= dqs_phase[3:1]; + + scc_dqs_cfg[47:46] <= dqs_phase[6:5]; + + scc_dqs_cfg[33:32] <= dqs_phase[6:5]; + scc_dqs_cfg[36] <= dqs_phase[4]; + scc_dqs_cfg[90] <= dqs_phase[0]; + scc_dqs_cfg[96:94] <= dqs_phase[3:1]; + + scc_dqs_cfg[51:50] <= dqs_phase[6:5]; + + scc_dqs_cfg[34] <= '1; + scc_dqs_cfg[52] <= '1; + end + else begin + scc_dqs_cfg[29:28] <= dqs_phase[6:5]; + scc_dqs_cfg[31] <= dqs_phase[4]; + scc_dqs_cfg[69] <= dqs_phase[0]; + scc_dqs_cfg[89] <= dqs_phase[0]; + + scc_dqs_cfg[68:66] <= dqs_phase[3:1]; + scc_dqs_cfg[93:91] <= dqs_phase[3:1]; + + scc_dqs_cfg[47:46] <= dqs_phase[6:5]; + + scc_dqs_cfg[33:32] <= dq_phase[6:5]; + scc_dqs_cfg[36] <= dq_phase[4]; + scc_dqs_cfg[90] <= dq_phase[0]; + scc_dqs_cfg[96:94] <= dq_phase[3:1]; + + scc_dqs_cfg[51:50] <= dq_phase[6:5]; + end + + scc_dqs_cfg[54] <= 1'b0; + scc_dqs_cfg[49] <= 1'b0; + + scc_io_cfg[17:12] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT1_DELAY]); + scc_io_cfg[23:18] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT2_DELAY]); + scc_io_cfg[11:0] <= maskTo12Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_IN_DELAY]); + scc_io_cfg[39:24] <= '0; + + scc_sr_dqsenable_delayctrl <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]); + scc_sr_dqsdisablen_delayctrl <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]); + scc_sr_multirank_delayctrl <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]); + end + end + + function[5:0] maskTo6Bits; + input[DATAWIDTH-1:0] i; + maskTo6Bits = i[5:0]; + endfunction + + function[7:0] maskTo8Bits; + input[DATAWIDTH-1:0] i; + maskTo8Bits = i[7:0]; + endfunction + + function[11:0] maskTo12Bits; + input[DATAWIDTH-1:0] i; + maskTo12Bits = i[11:0]; + endfunction + +endmodule diff --git a/ip/altera/ddr3_sim.f b/ip/altera/ddr3_sim.f new file mode 100644 index 0000000..d0b37f6 --- /dev/null +++ b/ip/altera/ddr3_sim.f @@ -0,0 +1,4 @@ +ddr3_sim/ddr3.vhd +ddr3_sim/ddr3/ddr3_0002.vhd +ddr3_sim/ddr3/ddr3_pll0.vho +ddr3_sim/ddr3/ddr3_pll0_sim_delay.vhd diff --git a/ip/altera/ddr3_sim/aldec/rivierapro_setup.tcl b/ip/altera/ddr3_sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..89f6219 --- /dev/null +++ b/ip/altera/ddr3_sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,235 @@ + +# (C) 2001-2016 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 15.1 185 linux 2016.01.17.15:36:30 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script can be used to simulate the following IP: +# ddr3 +# To create a top-level simulation script which compiles other +# IP, and manages other system issues, copy the following template +# and adapt it to your needs: +# +# # Start of template +# # If the copied and modified template file is "aldec.do", run it as: +# # vsim -c -do aldec.do +# # +# # Source the generated sim script +# source rivierapro_setup.tcl +# # Compile eda/sim_lib contents first +# dev_com +# # Override the top-level name (so that elab is useful) +# set TOP_LEVEL_NAME top +# # Compile the standalone IP. +# com +# # Compile the user top-level +# vlog -sv2k5 ../../top.sv +# # Elaborate the design. +# elab +# # Run the simulation +# run +# # Report success to the shell +# exit -code 0 +# # End of template +# ---------------------------------------- +# If ddr3 is one of several IP cores in your +# Quartus project, you can generate a simulation script +# suitable for inclusion in your top-level simulation +# script by running the following command line: +# +# ip-setup-simulation --quartus-project= +# +# ip-setup-simulation will discover the Altera IP +# within the Quartus project, and generate a unified +# script which supports all the Altera IP within the design. +# ---------------------------------------- + +# ---------------------------------------- +# Initialize variables +if ![info exists SYSTEM_INSTANCE_NAME] { + set SYSTEM_INSTANCE_NAME "" +} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { + set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME" +} + +if ![info exists TOP_LEVEL_NAME] { + set TOP_LEVEL_NAME "ddr3" +} + +if ![info exists QSYS_SIMDIR] { + set QSYS_SIMDIR "./../" +} + +if ![info exists QUARTUS_INSTALL_DIR] { + set QUARTUS_INSTALL_DIR "/opt/altera/15.1/quartus/" +} + +if ![info exists USER_DEFINED_COMPILE_OPTIONS] { + set USER_DEFINED_COMPILE_OPTIONS "" +} +if ![info exists USER_DEFINED_ELAB_OPTIONS] { + set USER_DEFINED_ELAB_OPTIONS "" +} + +# ---------------------------------------- +# Initialize simulation properties - DO NOT MODIFY! +set ELAB_OPTIONS "" +set SIM_OPTIONS "" +if ![ string match "*-64 vsim*" [ vsim -version ] ] { +} else { +} + +set Aldec "Riviera" +if { [ string match "*Active-HDL*" [ vsim -version ] ] } { + set Aldec "Active" +} + +if { [ string match "Active" $Aldec ] } { + scripterconf -tcl + createdesign "$TOP_LEVEL_NAME" "." + opendesign "$TOP_LEVEL_NAME" +} + +# ---------------------------------------- +# Copy ROM/RAM files to simulation directory +alias file_copy { + echo "\[exec\] file_copy" +} + +# ---------------------------------------- +# Create compilation libraries +proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } } +ensure_lib ./libraries +ensure_lib ./libraries/work +vmap work ./libraries/work +ensure_lib ./libraries/altera +vmap altera ./libraries/altera +ensure_lib ./libraries/lpm +vmap lpm ./libraries/lpm +ensure_lib ./libraries/sgate +vmap sgate ./libraries/sgate +ensure_lib ./libraries/altera_mf +vmap altera_mf ./libraries/altera_mf +ensure_lib ./libraries/altera_lnsim +vmap altera_lnsim ./libraries/altera_lnsim +ensure_lib ./libraries/cyclonev +vmap cyclonev ./libraries/cyclonev +ensure_lib ./libraries/pll0 +vmap pll0 ./libraries/pll0 +ensure_lib ./libraries/ddr3 +vmap ddr3 ./libraries/ddr3 + +# ---------------------------------------- +# Compile device library files +alias dev_com { + echo "\[exec\] dev_com" + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf + vlog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim + vlog -v2k5 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev + vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev +} + +# ---------------------------------------- +# Compile the design files in correct order +alias com { + echo "\[exec\] com" + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0.vho" -work pll0 + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0_sim_delay.vhd" -work pll0 + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_0002.vhd" -work ddr3 + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3.vhd" +} + +# ---------------------------------------- +# Elaborate top level design +alias elab { + echo "\[exec\] elab" + eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L pll0 -L ddr3 -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME +} + +# ---------------------------------------- +# Elaborate the top level design with -dbg -O2 option +alias elab_debug { + echo "\[exec\] elab_debug" + eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L pll0 -L ddr3 -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME +} + +# ---------------------------------------- +# Compile all the design files and elaborate the top level design +alias ld " + dev_com + com + elab +" + +# ---------------------------------------- +# Compile all the design files and elaborate the top level design with -dbg -O2 +alias ld_debug " + dev_com + com + elab_debug +" + +# ---------------------------------------- +# Print out user commmand line aliases +alias h { + echo "List Of Command Line Aliases" + echo + echo "file_copy -- Copy ROM/RAM files to simulation directory" + echo + echo "dev_com -- Compile device library files" + echo + echo "com -- Compile the design files in correct order" + echo + echo "elab -- Elaborate top level design" + echo + echo "elab_debug -- Elaborate the top level design with -dbg -O2 option" + echo + echo "ld -- Compile all the design files and elaborate the top level design" + echo + echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2" + echo + echo + echo + echo "List Of Variables" + echo + echo "TOP_LEVEL_NAME -- Top level module name." + echo " For most designs, this should be overridden" + echo " to enable the elab/elab_debug aliases." + echo + echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module." + echo + echo "QSYS_SIMDIR -- Qsys base simulation directory." + echo + echo "QUARTUS_INSTALL_DIR -- Quartus installation directory." + echo + echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases." + echo + echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases." +} +file_copy +h diff --git a/ip/altera/ddr3_sim/cadence/cds.lib b/ip/altera/ddr3_sim/cadence/cds.lib new file mode 100644 index 0000000..c16f365 --- /dev/null +++ b/ip/altera/ddr3_sim/cadence/cds.lib @@ -0,0 +1,19 @@ + +DEFINE std $CDS_ROOT/tools/inca/files/STD/ +DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ +DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ +DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ +DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ +DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ +DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ +DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ +DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ +DEFINE work ./libraries/work/ +DEFINE pll0 ./libraries/pll0/ +DEFINE ddr3 ./libraries/ddr3/ +DEFINE altera ./libraries/altera/ +DEFINE lpm ./libraries/lpm/ +DEFINE sgate ./libraries/sgate/ +DEFINE altera_mf ./libraries/altera_mf/ +DEFINE altera_lnsim ./libraries/altera_lnsim/ +DEFINE cyclonev ./libraries/cyclonev/ diff --git a/ip/altera/ddr3_sim/cadence/cds_libs/ddr3.cds.lib b/ip/altera/ddr3_sim/cadence/cds_libs/ddr3.cds.lib new file mode 100644 index 0000000..890439c --- /dev/null +++ b/ip/altera/ddr3_sim/cadence/cds_libs/ddr3.cds.lib @@ -0,0 +1,18 @@ + +DEFINE std $CDS_ROOT/tools/inca/files/STD/ +DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ +DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ +DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ +DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ +DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ +DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ +DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ +DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ +DEFINE work ./../libraries/work/ +DEFINE altera ./../libraries/altera/ +DEFINE lpm ./../libraries/lpm/ +DEFINE sgate ./../libraries/sgate/ +DEFINE altera_mf ./../libraries/altera_mf/ +DEFINE altera_lnsim ./../libraries/altera_lnsim/ +DEFINE cyclonev ./../libraries/cyclonev/ +DEFINE ddr3 ./../libraries/ddr3/ diff --git a/ip/altera/ddr3_sim/cadence/cds_libs/pll0.cds.lib b/ip/altera/ddr3_sim/cadence/cds_libs/pll0.cds.lib new file mode 100644 index 0000000..4d178b5 --- /dev/null +++ b/ip/altera/ddr3_sim/cadence/cds_libs/pll0.cds.lib @@ -0,0 +1,18 @@ + +DEFINE std $CDS_ROOT/tools/inca/files/STD/ +DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ +DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ +DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ +DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ +DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ +DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ +DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ +DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ +DEFINE work ./../libraries/work/ +DEFINE altera ./../libraries/altera/ +DEFINE lpm ./../libraries/lpm/ +DEFINE sgate ./../libraries/sgate/ +DEFINE altera_mf ./../libraries/altera_mf/ +DEFINE altera_lnsim ./../libraries/altera_lnsim/ +DEFINE cyclonev ./../libraries/cyclonev/ +DEFINE pll0 ./../libraries/pll0/ diff --git a/ip/altera/ddr3_sim/cadence/hdl.var b/ip/altera/ddr3_sim/cadence/hdl.var new file mode 100644 index 0000000..c1b7814 --- /dev/null +++ b/ip/altera/ddr3_sim/cadence/hdl.var @@ -0,0 +1,2 @@ + +DEFINE WORK work diff --git a/ip/altera/ddr3_sim/cadence/ncsim_setup.sh b/ip/altera/ddr3_sim/cadence/ncsim_setup.sh new file mode 100755 index 0000000..8acfaf0 --- /dev/null +++ b/ip/altera/ddr3_sim/cadence/ncsim_setup.sh @@ -0,0 +1,155 @@ + +# (C) 2001-2016 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 15.1 185 linux 2016.01.17.15:36:30 + +# ---------------------------------------- +# ncsim - auto-generated simulation script + +# ---------------------------------------- +# This script can be used to simulate the following IP: +# ddr3 +# To create a top-level simulation script which compiles other +# IP, and manages other system issues, copy the following template +# and adapt it to your needs: +# +# # Start of template +# # If the copied and modified template file is "ncsim.sh", run it as: +# # ./ncsim.sh +# # +# # Do the file copy, dev_com and com steps +# source ncsim_setup.sh \ +# SKIP_ELAB=1 \ +# SKIP_SIM=1 +# +# # Compile the top level module +# ncvlog -sv "$QSYS_SIMDIR/../top.sv" +# +# # Do the elaboration and sim steps +# # Override the top-level name +# # Override the user-defined sim options, so the simulation +# # runs forever (until $finish()). +# source ncsim_setup.sh \ +# SKIP_FILE_COPY=1 \ +# SKIP_DEV_COM=1 \ +# SKIP_COM=1 \ +# TOP_LEVEL_NAME=top \ +# USER_DEFINED_SIM_OPTIONS="" +# # End of template +# ---------------------------------------- +# If ddr3 is one of several IP cores in your +# Quartus project, you can generate a simulation script +# suitable for inclusion in your top-level simulation +# script by running the following command line: +# +# ip-setup-simulation --quartus-project= +# +# ip-setup-simulation will discover the Altera IP +# within the Quartus project, and generate a unified +# script which supports all the Altera IP within the design. +# ---------------------------------------- +# ACDS 15.1 185 linux 2016.01.17.15:36:30 +# ---------------------------------------- +# initialize variables +TOP_LEVEL_NAME="ddr3" +QSYS_SIMDIR="./../" +QUARTUS_INSTALL_DIR="/opt/altera/15.1/quartus/" +SKIP_FILE_COPY=0 +SKIP_DEV_COM=0 +SKIP_COM=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\"" + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_ELAB=1 SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `ncsim -version` != *"ncsim(64)"* ]]; then + : +else + : +fi + +# ---------------------------------------- +# create compilation libraries +mkdir -p ./libraries/work/ +mkdir -p ./libraries/pll0/ +mkdir -p ./libraries/ddr3/ +mkdir -p ./libraries/altera/ +mkdir -p ./libraries/lpm/ +mkdir -p ./libraries/sgate/ +mkdir -p ./libraries/altera_mf/ +mkdir -p ./libraries/altera_lnsim/ +mkdir -p ./libraries/cyclonev/ + +# ---------------------------------------- +# copy RAM/ROM files to simulation directory + +# ---------------------------------------- +# compile device library files +if [ $SKIP_DEV_COM -eq 0 ]; then + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf + ncvlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim + ncvlog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev +fi + +# ---------------------------------------- +# compile design files in correct order +if [ $SKIP_COM -eq 0 ]; then + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0.vho" -work pll0 -cdslib ./cds_libs/pll0.cds.lib + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0_sim_delay.vhd" -work pll0 -cdslib ./cds_libs/pll0.cds.lib + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_0002.vhd" -work ddr3 -cdslib ./cds_libs/ddr3.cds.lib + ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3.vhd" +fi + +# ---------------------------------------- +# elaborate top level design +if [ $SKIP_ELAB -eq 0 ]; then + ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME +fi + +# ---------------------------------------- +# simulate +if [ $SKIP_SIM -eq 0 ]; then + eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME +fi diff --git a/ip/altera/ddr3_sim/ddr3.vhd b/ip/altera/ddr3_sim/ddr3.vhd new file mode 100644 index 0000000..a0f27e9 --- /dev/null +++ b/ip/altera/ddr3_sim/ddr3.vhd @@ -0,0 +1,188 @@ +-- ddr3.vhd + +-- Generated using ACDS version 15.1 185 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ddr3 is + port ( + pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk + global_reset_n : in std_logic := '0'; -- global_reset.reset_n + soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n + afi_clk : out std_logic; -- afi_clk.clk + afi_half_clk : out std_logic; -- afi_half_clk.clk + afi_reset_n : out std_logic; -- afi_reset.reset_n + afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n + mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a + mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n + mem_reset_n : out std_logic; -- .mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt + avl_ready_0 : out std_logic; -- avl_0.waitrequest_n + avl_burstbegin_0 : in std_logic := '0'; -- .beginbursttransfer + avl_addr_0 : in std_logic_vector(24 downto 0) := (others => '0'); -- .address + avl_rdata_valid_0 : out std_logic; -- .readdatavalid + avl_rdata_0 : out std_logic_vector(31 downto 0); -- .readdata + avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + avl_be_0 : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable + avl_read_req_0 : in std_logic := '0'; -- .read + avl_write_req_0 : in std_logic := '0'; -- .write + avl_size_0 : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount + mp_cmd_clk_0_clk : in std_logic := '0'; -- mp_cmd_clk_0.clk + mp_cmd_reset_n_0_reset_n : in std_logic := '0'; -- mp_cmd_reset_n_0.reset_n + mp_rfifo_clk_0_clk : in std_logic := '0'; -- mp_rfifo_clk_0.clk + mp_rfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_rfifo_reset_n_0.reset_n + mp_wfifo_clk_0_clk : in std_logic := '0'; -- mp_wfifo_clk_0.clk + mp_wfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_wfifo_reset_n_0.reset_n + csr_clk : in std_logic := '0'; -- csr_clk.clk + csr_reset_n : in std_logic := '0'; -- csr_reset_n.reset_n + local_init_done : out std_logic; -- status.local_init_done + local_cal_success : out std_logic; -- .local_cal_success + local_cal_fail : out std_logic; -- .local_cal_fail + oct_rzqin : in std_logic := '0'; -- oct.rzqin + pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk + pll_write_clk : out std_logic; -- .pll_write_clk + pll_locked : out std_logic; -- .pll_locked + pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk + pll_avl_clk : out std_logic; -- .pll_avl_clk + pll_config_clk : out std_logic; -- .pll_config_clk + pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk + afi_phy_clk : out std_logic; -- .afi_phy_clk + pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk + ); +end entity ddr3; + +architecture rtl of ddr3 is + component ddr3_0002 is + port ( + pll_ref_clk : in std_logic := 'X'; -- clk + global_reset_n : in std_logic := 'X'; -- reset_n + soft_reset_n : in std_logic := 'X'; -- reset_n + afi_clk : out std_logic; -- clk + afi_half_clk : out std_logic; -- clk + afi_reset_n : out std_logic; -- reset_n + afi_reset_export_n : out std_logic; -- reset_n + mem_a : out std_logic_vector(12 downto 0); -- mem_a + mem_ba : out std_logic_vector(2 downto 0); -- mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n + mem_reset_n : out std_logic; -- mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + avl_ready_0 : out std_logic; -- waitrequest_n + avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- address + avl_rdata_valid_0 : out std_logic; -- readdatavalid + avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata + avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + avl_read_req_0 : in std_logic := 'X'; -- read + avl_write_req_0 : in std_logic := 'X'; -- write + avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + mp_cmd_clk_0_clk : in std_logic := 'X'; -- clk + mp_cmd_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + mp_rfifo_clk_0_clk : in std_logic := 'X'; -- clk + mp_rfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + mp_wfifo_clk_0_clk : in std_logic := 'X'; -- clk + mp_wfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n + csr_clk : in std_logic := 'X'; -- clk + csr_reset_n : in std_logic := 'X'; -- reset_n + local_init_done : out std_logic; -- local_init_done + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + oct_rzqin : in std_logic := 'X'; -- rzqin + pll_mem_clk : out std_logic; -- pll_mem_clk + pll_write_clk : out std_logic; -- pll_write_clk + pll_locked : out std_logic; -- pll_locked + pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk + pll_avl_clk : out std_logic; -- pll_avl_clk + pll_config_clk : out std_logic; -- pll_config_clk + pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk + afi_phy_clk : out std_logic; -- afi_phy_clk + pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk + ); + end component ddr3_0002; + +begin + + ddr3_inst : component ddr3_0002 + port map ( + pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk + global_reset_n => global_reset_n, -- global_reset.reset_n + soft_reset_n => soft_reset_n, -- soft_reset.reset_n + afi_clk => afi_clk, -- afi_clk.clk + afi_half_clk => afi_half_clk, -- afi_half_clk.clk + afi_reset_n => afi_reset_n, -- afi_reset.reset_n + afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n + mem_a => mem_a, -- memory.mem_a + mem_ba => mem_ba, -- .mem_ba + mem_ck => mem_ck, -- .mem_ck + mem_ck_n => mem_ck_n, -- .mem_ck_n + mem_cke => mem_cke, -- .mem_cke + mem_cs_n => mem_cs_n, -- .mem_cs_n + mem_dm => mem_dm, -- .mem_dm + mem_ras_n => mem_ras_n, -- .mem_ras_n + mem_cas_n => mem_cas_n, -- .mem_cas_n + mem_we_n => mem_we_n, -- .mem_we_n + mem_reset_n => mem_reset_n, -- .mem_reset_n + mem_dq => mem_dq, -- .mem_dq + mem_dqs => mem_dqs, -- .mem_dqs + mem_dqs_n => mem_dqs_n, -- .mem_dqs_n + mem_odt => mem_odt, -- .mem_odt + avl_ready_0 => avl_ready_0, -- avl_0.waitrequest_n + avl_burstbegin_0 => avl_burstbegin_0, -- .beginbursttransfer + avl_addr_0 => avl_addr_0, -- .address + avl_rdata_valid_0 => avl_rdata_valid_0, -- .readdatavalid + avl_rdata_0 => avl_rdata_0, -- .readdata + avl_wdata_0 => avl_wdata_0, -- .writedata + avl_be_0 => avl_be_0, -- .byteenable + avl_read_req_0 => avl_read_req_0, -- .read + avl_write_req_0 => avl_write_req_0, -- .write + avl_size_0 => avl_size_0, -- .burstcount + mp_cmd_clk_0_clk => mp_cmd_clk_0_clk, -- mp_cmd_clk_0.clk + mp_cmd_reset_n_0_reset_n => mp_cmd_reset_n_0_reset_n, -- mp_cmd_reset_n_0.reset_n + mp_rfifo_clk_0_clk => mp_rfifo_clk_0_clk, -- mp_rfifo_clk_0.clk + mp_rfifo_reset_n_0_reset_n => mp_rfifo_reset_n_0_reset_n, -- mp_rfifo_reset_n_0.reset_n + mp_wfifo_clk_0_clk => mp_wfifo_clk_0_clk, -- mp_wfifo_clk_0.clk + mp_wfifo_reset_n_0_reset_n => mp_wfifo_reset_n_0_reset_n, -- mp_wfifo_reset_n_0.reset_n + csr_clk => csr_clk, -- csr_clk.clk + csr_reset_n => csr_reset_n, -- csr_reset_n.reset_n + local_init_done => local_init_done, -- status.local_init_done + local_cal_success => local_cal_success, -- .local_cal_success + local_cal_fail => local_cal_fail, -- .local_cal_fail + oct_rzqin => oct_rzqin, -- oct.rzqin + pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk + pll_write_clk => pll_write_clk, -- .pll_write_clk + pll_locked => pll_locked, -- .pll_locked + pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk + pll_avl_clk => pll_avl_clk, -- .pll_avl_clk + pll_config_clk => pll_config_clk, -- .pll_config_clk + pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk + afi_phy_clk => afi_phy_clk, -- .afi_phy_clk + pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk + ); + +end architecture rtl; -- of ddr3 diff --git a/ip/altera/ddr3_sim/ddr3/ddr3_0002.vhd b/ip/altera/ddr3_sim/ddr3/ddr3_0002.vhd new file mode 100644 index 0000000..8f32830 --- /dev/null +++ b/ip/altera/ddr3_sim/ddr3/ddr3_0002.vhd @@ -0,0 +1,2061 @@ +-- ddr3_0002.vhd + +-- This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl. If you edit it your changes +-- will probably be lost. +-- +-- Generated using ACDS version 15.1 185 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ddr3_0002 is + port ( + pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk + global_reset_n : in std_logic := '0'; -- global_reset.reset_n + soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n + afi_clk : out std_logic; -- afi_clk.clk + afi_half_clk : out std_logic; -- afi_half_clk.clk + afi_reset_n : out std_logic; -- afi_reset.reset_n + afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n + mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a + mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n + mem_reset_n : out std_logic; -- .mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt + avl_ready_0 : out std_logic; -- avl_0.waitrequest_n + avl_burstbegin_0 : in std_logic := '0'; -- .beginbursttransfer + avl_addr_0 : in std_logic_vector(24 downto 0) := (others => '0'); -- .address + avl_rdata_valid_0 : out std_logic; -- .readdatavalid + avl_rdata_0 : out std_logic_vector(31 downto 0); -- .readdata + avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + avl_be_0 : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable + avl_read_req_0 : in std_logic := '0'; -- .read + avl_write_req_0 : in std_logic := '0'; -- .write + avl_size_0 : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount + mp_cmd_clk_0_clk : in std_logic := '0'; -- mp_cmd_clk_0.clk + mp_cmd_reset_n_0_reset_n : in std_logic := '0'; -- mp_cmd_reset_n_0.reset_n + mp_rfifo_clk_0_clk : in std_logic := '0'; -- mp_rfifo_clk_0.clk + mp_rfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_rfifo_reset_n_0.reset_n + mp_wfifo_clk_0_clk : in std_logic := '0'; -- mp_wfifo_clk_0.clk + mp_wfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_wfifo_reset_n_0.reset_n + csr_clk : in std_logic := '0'; -- csr_clk.clk + csr_reset_n : in std_logic := '0'; -- csr_reset_n.reset_n + local_init_done : out std_logic; -- status.local_init_done + local_cal_success : out std_logic; -- .local_cal_success + local_cal_fail : out std_logic; -- .local_cal_fail + oct_rzqin : in std_logic := '0'; -- oct.rzqin + pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk + pll_write_clk : out std_logic; -- .pll_write_clk + pll_locked : out std_logic; -- .pll_locked + pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk + pll_avl_clk : out std_logic; -- .pll_avl_clk + pll_config_clk : out std_logic; -- .pll_config_clk + pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk + afi_phy_clk : out std_logic; -- .afi_phy_clk + pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk + ); +end entity ddr3_0002; + +architecture rtl of ddr3_0002 is + component ddr3_pll0 is + port ( + global_reset_n : in std_logic := 'X'; -- reset_n + afi_clk : out std_logic; -- clk + afi_half_clk : out std_logic; -- clk + pll_ref_clk : in std_logic := 'X'; -- clk + pll_mem_clk : out std_logic; -- pll_mem_clk + pll_write_clk : out std_logic; -- pll_write_clk + pll_locked : out std_logic; -- pll_locked + pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk + pll_avl_clk : out std_logic; -- pll_avl_clk + pll_config_clk : out std_logic; -- pll_config_clk + pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk + afi_phy_clk : out std_logic; -- afi_phy_clk + pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk + ); + end component ddr3_pll0; + + component ddr3_p0 is + port ( + global_reset_n : in std_logic := 'X'; -- reset_n + soft_reset_n : in std_logic := 'X'; -- reset_n + csr_soft_reset_req : in std_logic := 'X'; -- reset + afi_reset_n : out std_logic; -- reset_n + afi_reset_export_n : out std_logic; -- reset_n + ctl_reset_n : out std_logic; -- reset_n + afi_clk : in std_logic := 'X'; -- clk + afi_half_clk : in std_logic := 'X'; -- clk + ctl_clk : out std_logic; -- clk + avl_clk : out std_logic; -- clk + avl_reset_n : out std_logic; -- reset_n + scc_clk : out std_logic; -- clk + scc_reset_n : out std_logic; -- reset_n + avl_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- address + avl_write : in std_logic := 'X'; -- write + avl_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + avl_read : in std_logic := 'X'; -- read + avl_readdata : out std_logic_vector(31 downto 0); -- readdata + avl_waitrequest : out std_logic; -- waitrequest + dll_clk : out std_logic; -- clk + afi_addr : in std_logic_vector(19 downto 0) := (others => 'X'); -- afi_addr + afi_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- afi_ba + afi_cke : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_cke + afi_cs_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_cs_n + afi_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_ras_n + afi_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_we_n + afi_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cas_n + afi_rst_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rst_n + afi_odt : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_odt + afi_dqs_burst : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_dqs_burst + afi_wdata_valid : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_wdata_valid + afi_wdata : in std_logic_vector(79 downto 0) := (others => 'X'); -- afi_wdata + afi_dm : in std_logic_vector(9 downto 0) := (others => 'X'); -- afi_dm + afi_rdata : out std_logic_vector(79 downto 0); -- afi_rdata + afi_rdata_en : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_rdata_en + afi_rdata_en_full : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_rdata_en_full + afi_rdata_valid : out std_logic_vector(0 downto 0); -- afi_rdata_valid + afi_wlat : out std_logic_vector(3 downto 0); -- afi_wlat + afi_rlat : out std_logic_vector(4 downto 0); -- afi_rlat + afi_cal_success : out std_logic; -- afi_cal_success + afi_cal_fail : out std_logic; -- afi_cal_fail + scc_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- scc_data + scc_dqs_ena : in std_logic_vector(1 downto 0) := (others => 'X'); -- scc_dqs_ena + scc_dqs_io_ena : in std_logic_vector(1 downto 0) := (others => 'X'); -- scc_dqs_io_ena + scc_dq_ena : in std_logic_vector(15 downto 0) := (others => 'X'); -- scc_dq_ena + scc_dm_ena : in std_logic_vector(1 downto 0) := (others => 'X'); -- scc_dm_ena + capture_strobe_tracking : out std_logic_vector(1 downto 0); -- capture_strobe_tracking + scc_upd : in std_logic_vector(0 downto 0) := (others => 'X'); -- scc_upd + cfg_addlat : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_addlat + cfg_bankaddrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_bankaddrwidth + cfg_caswrlat : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_caswrlat + cfg_coladdrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_coladdrwidth + cfg_csaddrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_csaddrwidth + cfg_devicewidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_devicewidth + cfg_dramconfig : in std_logic_vector(23 downto 0) := (others => 'X'); -- cfg_dramconfig + cfg_interfacewidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_interfacewidth + cfg_rowaddrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_rowaddrwidth + cfg_tcl : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_tcl + cfg_tmrd : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_tmrd + cfg_trefi : in std_logic_vector(15 downto 0) := (others => 'X'); -- cfg_trefi + cfg_trfc : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_trfc + cfg_twr : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_twr + afi_mem_clk_disable : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_mem_clk_disable + pll_mem_clk : in std_logic := 'X'; -- pll_mem_clk + pll_write_clk : in std_logic := 'X'; -- pll_write_clk + pll_locked : in std_logic := 'X'; -- pll_locked + pll_write_clk_pre_phy_clk : in std_logic := 'X'; -- pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : in std_logic := 'X'; -- pll_addr_cmd_clk + pll_avl_clk : in std_logic := 'X'; -- pll_avl_clk + pll_config_clk : in std_logic := 'X'; -- pll_config_clk + pll_mem_phy_clk : in std_logic := 'X'; -- pll_mem_phy_clk + afi_phy_clk : in std_logic := 'X'; -- afi_phy_clk + pll_avl_phy_clk : in std_logic := 'X'; -- pll_avl_phy_clk + dll_pll_locked : out std_logic; -- dll_pll_locked + dll_delayctrl : in std_logic_vector(6 downto 0) := (others => 'X'); -- dll_delayctrl + seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => 'X'); -- seriesterminationcontrol + parallelterminationcontrol : in std_logic_vector(15 downto 0) := (others => 'X'); -- parallelterminationcontrol + mem_a : out std_logic_vector(12 downto 0); -- mem_a + mem_ba : out std_logic_vector(2 downto 0); -- mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n + mem_reset_n : out std_logic; -- mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + csr_clk : in std_logic := 'X'; -- clk + csr_reset_n : in std_logic := 'X'; -- reset_n + csr_write_req : in std_logic := 'X'; -- write + csr_read_req : in std_logic := 'X'; -- read + csr_waitrequest : out std_logic; -- waitrequest + csr_addr : in std_logic_vector(7 downto 0) := (others => 'X'); -- address + csr_be : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + csr_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + csr_rdata : out std_logic_vector(31 downto 0); -- readdata + csr_rdata_valid : out std_logic; -- readdatavalid + io_intaficalfail : out std_logic; -- io_intaficalfail + io_intaficalsuccess : out std_logic; -- io_intaficalsuccess + io_intaddrdout : in std_logic_vector(63 downto 0) := (others => 'X'); -- io_intaddrdout + io_intbadout : in std_logic_vector(11 downto 0) := (others => 'X'); -- io_intbadout + io_intcasndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intcasndout + io_intckdout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intckdout + io_intckedout : in std_logic_vector(7 downto 0) := (others => 'X'); -- io_intckedout + io_intckndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intckndout + io_intcsndout : in std_logic_vector(7 downto 0) := (others => 'X'); -- io_intcsndout + io_intdmdout : in std_logic_vector(19 downto 0) := (others => 'X'); -- io_intdmdout + io_intdqdin : out std_logic_vector(179 downto 0); -- io_intdqdin + io_intdqdout : in std_logic_vector(179 downto 0) := (others => 'X'); -- io_intdqdout + io_intdqoe : in std_logic_vector(89 downto 0) := (others => 'X'); -- io_intdqoe + io_intdqsbdout : in std_logic_vector(19 downto 0) := (others => 'X'); -- io_intdqsbdout + io_intdqsboe : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqsboe + io_intdqsdout : in std_logic_vector(19 downto 0) := (others => 'X'); -- io_intdqsdout + io_intdqslogicdqsena : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicdqsena + io_intdqslogicfiforeset : in std_logic_vector(4 downto 0) := (others => 'X'); -- io_intdqslogicfiforeset + io_intdqslogicincrdataen : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicincrdataen + io_intdqslogicincwrptr : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicincwrptr + io_intdqslogicoct : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicoct + io_intdqslogicrdatavalid : out std_logic_vector(4 downto 0); -- io_intdqslogicrdatavalid + io_intdqslogicreadlatency : in std_logic_vector(24 downto 0) := (others => 'X'); -- io_intdqslogicreadlatency + io_intdqsoe : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqsoe + io_intodtdout : in std_logic_vector(7 downto 0) := (others => 'X'); -- io_intodtdout + io_intrasndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intrasndou + io_intresetndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intresetndout + io_intwendout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intwendout + io_intafirlat : out std_logic_vector(4 downto 0); -- io_intafirlat + io_intafiwlat : out std_logic_vector(3 downto 0) -- io_intafiwlat + ); + end component ddr3_p0; + + component ddr3_s0 is + port ( + avl_clk : in std_logic := 'X'; -- clk + avl_reset_n : in std_logic := 'X'; -- reset_n + scc_clk : in std_logic := 'X'; -- clk + reset_n_scc_clk : in std_logic := 'X'; -- reset_n + scc_data : out std_logic_vector(0 downto 0); -- scc_data + scc_dqs_ena : out std_logic_vector(1 downto 0); -- scc_dqs_ena + scc_dqs_io_ena : out std_logic_vector(1 downto 0); -- scc_dqs_io_ena + scc_dq_ena : out std_logic_vector(15 downto 0); -- scc_dq_ena + scc_dm_ena : out std_logic_vector(1 downto 0); -- scc_dm_ena + capture_strobe_tracking : in std_logic_vector(1 downto 0) := (others => 'X'); -- capture_strobe_tracking + scc_upd : out std_logic_vector(0 downto 0); -- scc_upd + afi_init_req : in std_logic := 'X'; -- afi_init_req + afi_cal_req : in std_logic := 'X'; -- afi_cal_req + avl_address : out std_logic_vector(15 downto 0); -- address + avl_write : out std_logic; -- write + avl_writedata : out std_logic_vector(31 downto 0); -- writedata + avl_read : out std_logic; -- read + avl_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata + avl_waitrequest : in std_logic := 'X'; -- waitrequest + seq_waitrequest : out std_logic; -- waitrequest + seq_readdata : out std_logic_vector(31 downto 0); -- readdata + seq_readdatavalid : out std_logic; -- readdatavalid + seq_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount + seq_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + seq_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address + seq_write : in std_logic := 'X'; -- write + seq_read : in std_logic := 'X'; -- read + seq_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + seq_debugaccess : in std_logic := 'X' -- debugaccess + ); + end component ddr3_s0; + + component ddr3_dmaster is + port ( + clk_clk : in std_logic := 'X'; -- clk + clk_reset_reset : in std_logic := 'X'; -- reset + master_address : out std_logic_vector(31 downto 0); -- address + master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata + master_read : out std_logic; -- read + master_write : out std_logic; -- write + master_writedata : out std_logic_vector(31 downto 0); -- writedata + master_waitrequest : in std_logic := 'X'; -- waitrequest + master_readdatavalid : in std_logic := 'X'; -- readdatavalid + master_byteenable : out std_logic_vector(3 downto 0); -- byteenable + master_reset_reset : out std_logic -- reset + ); + end component ddr3_dmaster; + + component altera_mem_if_hard_memory_controller_top_cyclonev is + generic ( + MEM_IF_DQS_WIDTH : integer := 0; + MEM_IF_CS_WIDTH : integer := 0; + MEM_IF_CHIP_BITS : integer := -1; + MEM_IF_CLK_PAIR_COUNT : integer := 1; + CSR_ADDR_WIDTH : integer := 8; + CSR_DATA_WIDTH : integer := 32; + CSR_BE_WIDTH : integer := 4; + AVL_ADDR_WIDTH : integer := 0; + AVL_DATA_WIDTH : integer := 0; + AVL_SIZE_WIDTH : integer := 0; + AVL_DATA_WIDTH_PORT_0 : integer := 0; + AVL_ADDR_WIDTH_PORT_0 : integer := 0; + AVL_NUM_SYMBOLS_PORT_0 : integer := 2; + LSB_WFIFO_PORT_0 : integer := 5; + MSB_WFIFO_PORT_0 : integer := 5; + LSB_RFIFO_PORT_0 : integer := 5; + MSB_RFIFO_PORT_0 : integer := 5; + AVL_DATA_WIDTH_PORT_1 : integer := 0; + AVL_ADDR_WIDTH_PORT_1 : integer := 0; + AVL_NUM_SYMBOLS_PORT_1 : integer := 2; + LSB_WFIFO_PORT_1 : integer := 5; + MSB_WFIFO_PORT_1 : integer := 5; + LSB_RFIFO_PORT_1 : integer := 5; + MSB_RFIFO_PORT_1 : integer := 5; + AVL_DATA_WIDTH_PORT_2 : integer := 0; + AVL_ADDR_WIDTH_PORT_2 : integer := 0; + AVL_NUM_SYMBOLS_PORT_2 : integer := 2; + LSB_WFIFO_PORT_2 : integer := 5; + MSB_WFIFO_PORT_2 : integer := 5; + LSB_RFIFO_PORT_2 : integer := 5; + MSB_RFIFO_PORT_2 : integer := 5; + AVL_DATA_WIDTH_PORT_3 : integer := 0; + AVL_ADDR_WIDTH_PORT_3 : integer := 0; + AVL_NUM_SYMBOLS_PORT_3 : integer := 2; + LSB_WFIFO_PORT_3 : integer := 5; + MSB_WFIFO_PORT_3 : integer := 5; + LSB_RFIFO_PORT_3 : integer := 5; + MSB_RFIFO_PORT_3 : integer := 5; + AVL_DATA_WIDTH_PORT_4 : integer := 0; + AVL_ADDR_WIDTH_PORT_4 : integer := 0; + AVL_NUM_SYMBOLS_PORT_4 : integer := 2; + LSB_WFIFO_PORT_4 : integer := 5; + MSB_WFIFO_PORT_4 : integer := 5; + LSB_RFIFO_PORT_4 : integer := 5; + MSB_RFIFO_PORT_4 : integer := 5; + AVL_DATA_WIDTH_PORT_5 : integer := 0; + AVL_ADDR_WIDTH_PORT_5 : integer := 0; + AVL_NUM_SYMBOLS_PORT_5 : integer := 2; + LSB_WFIFO_PORT_5 : integer := 5; + MSB_WFIFO_PORT_5 : integer := 5; + LSB_RFIFO_PORT_5 : integer := 5; + MSB_RFIFO_PORT_5 : integer := 5; + ENUM_ATTR_COUNTER_ONE_RESET : string := "DISABLED"; + ENUM_ATTR_COUNTER_ZERO_RESET : string := "DISABLED"; + ENUM_ATTR_STATIC_CONFIG_VALID : string := "DISABLED"; + ENUM_AUTO_PCH_ENABLE_0 : string := "DISABLED"; + ENUM_AUTO_PCH_ENABLE_1 : string := "DISABLED"; + ENUM_AUTO_PCH_ENABLE_2 : string := "DISABLED"; + ENUM_AUTO_PCH_ENABLE_3 : string := "DISABLED"; + ENUM_AUTO_PCH_ENABLE_4 : string := "DISABLED"; + ENUM_AUTO_PCH_ENABLE_5 : string := "DISABLED"; + ENUM_CAL_REQ : string := "DISABLED"; + ENUM_CFG_BURST_LENGTH : string := "BL_8"; + ENUM_CFG_INTERFACE_WIDTH : string := "DWIDTH_32"; + ENUM_CFG_SELF_RFSH_EXIT_CYCLES : string := ""; + ENUM_CFG_STARVE_LIMIT : string := "STARVE_LIMIT_32"; + ENUM_CFG_TYPE : string := "DDR3"; + ENUM_CLOCK_OFF_0 : string := "DISABLED"; + ENUM_CLOCK_OFF_1 : string := "DISABLED"; + ENUM_CLOCK_OFF_2 : string := "DISABLED"; + ENUM_CLOCK_OFF_3 : string := "DISABLED"; + ENUM_CLOCK_OFF_4 : string := "DISABLED"; + ENUM_CLOCK_OFF_5 : string := "DISABLED"; + ENUM_CLR_INTR : string := "NO_CLR_INTR"; + ENUM_CMD_PORT_IN_USE_0 : string := "FALSE"; + ENUM_CMD_PORT_IN_USE_1 : string := "FALSE"; + ENUM_CMD_PORT_IN_USE_2 : string := "FALSE"; + ENUM_CMD_PORT_IN_USE_3 : string := "FALSE"; + ENUM_CMD_PORT_IN_USE_4 : string := "FALSE"; + ENUM_CMD_PORT_IN_USE_5 : string := "FALSE"; + ENUM_CPORT0_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_CPORT0_RFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT0_TYPE : string := "DISABLE"; + ENUM_CPORT0_WFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT1_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_CPORT1_RFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT1_TYPE : string := "DISABLE"; + ENUM_CPORT1_WFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT2_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_CPORT2_RFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT2_TYPE : string := "DISABLE"; + ENUM_CPORT2_WFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT3_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_CPORT3_RFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT3_TYPE : string := "DISABLE"; + ENUM_CPORT3_WFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT4_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_CPORT4_RFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT4_TYPE : string := "DISABLE"; + ENUM_CPORT4_WFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT5_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_CPORT5_RFIFO_MAP : string := "FIFO_0"; + ENUM_CPORT5_TYPE : string := "DISABLE"; + ENUM_CPORT5_WFIFO_MAP : string := "FIFO_0"; + ENUM_CTL_ADDR_ORDER : string := "CHIP_BANK_ROW_COL"; + ENUM_CTL_ECC_ENABLED : string := "CTL_ECC_DISABLED"; + ENUM_CTL_ECC_RMW_ENABLED : string := "CTL_ECC_RMW_DISABLED"; + ENUM_CTL_REGDIMM_ENABLED : string := "REGDIMM_DISABLED"; + ENUM_CTL_USR_REFRESH : string := "CTL_USR_REFRESH_DISABLED"; + ENUM_CTRL_WIDTH : string := "DATA_WIDTH_64_BIT"; + ENUM_DELAY_BONDING : string := "BONDING_LATENCY_0"; + ENUM_DFX_BYPASS_ENABLE : string := "DFX_BYPASS_DISABLED"; + ENUM_DISABLE_MERGING : string := "MERGING_ENABLED"; + ENUM_ECC_DQ_WIDTH : string := "ECC_DQ_WIDTH_0"; + ENUM_ENABLE_ATPG : string := "DISABLED"; + ENUM_ENABLE_BONDING_0 : string := "DISABLED"; + ENUM_ENABLE_BONDING_1 : string := "DISABLED"; + ENUM_ENABLE_BONDING_2 : string := "DISABLED"; + ENUM_ENABLE_BONDING_3 : string := "DISABLED"; + ENUM_ENABLE_BONDING_4 : string := "DISABLED"; + ENUM_ENABLE_BONDING_5 : string := "DISABLED"; + ENUM_ENABLE_BONDING_WRAPBACK : string := "DISABLED"; + ENUM_ENABLE_DQS_TRACKING : string := "DISABLED"; + ENUM_ENABLE_ECC_CODE_OVERWRITES : string := "DISABLED"; + ENUM_ENABLE_FAST_EXIT_PPD : string := "DISABLED"; + ENUM_ENABLE_INTR : string := "DISABLED"; + ENUM_ENABLE_NO_DM : string := "DISABLED"; + ENUM_ENABLE_PIPELINEGLOBAL : string := "DISABLED"; + ENUM_GANGED_ARF : string := "DISABLED"; + ENUM_GEN_DBE : string := "GEN_DBE_DISABLED"; + ENUM_GEN_SBE : string := "GEN_SBE_DISABLED"; + ENUM_INC_SYNC : string := "FIFO_SET_2"; + ENUM_LOCAL_IF_CS_WIDTH : string := "ADDR_WIDTH_2"; + ENUM_MASK_CORR_DROPPED_INTR : string := "DISABLED"; + ENUM_MASK_DBE_INTR : string := "DISABLED"; + ENUM_MASK_SBE_INTR : string := "DISABLED"; + ENUM_MEM_IF_AL : string := "AL_0"; + ENUM_MEM_IF_BANKADDR_WIDTH : string := "ADDR_WIDTH_3"; + ENUM_MEM_IF_BURSTLENGTH : string := "MEM_IF_BURSTLENGTH_8"; + ENUM_MEM_IF_COLADDR_WIDTH : string := "ADDR_WIDTH_12"; + ENUM_MEM_IF_CS_PER_RANK : string := "MEM_IF_CS_PER_RANK_1"; + ENUM_MEM_IF_CS_WIDTH : string := "MEM_IF_CS_WIDTH_1"; + ENUM_MEM_IF_DQ_PER_CHIP : string := "MEM_IF_DQ_PER_CHIP_8"; + ENUM_MEM_IF_DQS_WIDTH : string := "DQS_WIDTH_4"; + ENUM_MEM_IF_DWIDTH : string := "MEM_IF_DWIDTH_32"; + ENUM_MEM_IF_MEMTYPE : string := "DDR3_SDRAM"; + ENUM_MEM_IF_ROWADDR_WIDTH : string := "ADDR_WIDTH_16"; + ENUM_MEM_IF_SPEEDBIN : string := "DDR3_1066_6_6_6"; + ENUM_MEM_IF_TCCD : string := "TCCD_4"; + ENUM_MEM_IF_TCL : string := "TCL_6"; + ENUM_MEM_IF_TCWL : string := "TCWL_5"; + ENUM_MEM_IF_TFAW : string := "TFAW_16"; + ENUM_MEM_IF_TMRD : string := ""; + ENUM_MEM_IF_TRAS : string := "TRAS_16"; + ENUM_MEM_IF_TRC : string := "TRC_22"; + ENUM_MEM_IF_TRCD : string := "TRCD_6"; + ENUM_MEM_IF_TRP : string := "TRP_6"; + ENUM_MEM_IF_TRRD : string := "TRRD_4"; + ENUM_MEM_IF_TRTP : string := "TRTP_4"; + ENUM_MEM_IF_TWR : string := "TWR_6"; + ENUM_MEM_IF_TWTR : string := "TWTR_4"; + ENUM_MMR_CFG_MEM_BL : string := "MP_BL_8"; + ENUM_OUTPUT_REGD : string := "DISABLED"; + ENUM_PDN_EXIT_CYCLES : string := "SLOW_EXIT"; + ENUM_PORT0_WIDTH : string := "PORT_64_BIT"; + ENUM_PORT1_WIDTH : string := "PORT_64_BIT"; + ENUM_PORT2_WIDTH : string := "PORT_64_BIT"; + ENUM_PORT3_WIDTH : string := "PORT_64_BIT"; + ENUM_PORT4_WIDTH : string := "PORT_64_BIT"; + ENUM_PORT5_WIDTH : string := "PORT_64_BIT"; + ENUM_PRIORITY_0_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_0_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_0_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_0_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_0_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_0_5 : string := "WEIGHT_0"; + ENUM_PRIORITY_1_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_1_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_1_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_1_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_1_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_1_5 : string := "WEIGHT_0"; + ENUM_PRIORITY_2_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_2_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_2_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_2_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_2_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_2_5 : string := "WEIGHT_0"; + ENUM_PRIORITY_3_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_3_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_3_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_3_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_3_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_3_5 : string := "WEIGHT_0"; + ENUM_PRIORITY_4_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_4_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_4_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_4_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_4_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_4_5 : string := "WEIGHT_0"; + ENUM_PRIORITY_5_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_5_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_5_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_5_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_5_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_5_5 : string := "WEIGHT_0"; + ENUM_PRIORITY_6_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_6_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_6_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_6_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_6_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_6_5 : string := "WEIGHT_0"; + ENUM_PRIORITY_7_0 : string := "WEIGHT_0"; + ENUM_PRIORITY_7_1 : string := "WEIGHT_0"; + ENUM_PRIORITY_7_2 : string := "WEIGHT_0"; + ENUM_PRIORITY_7_3 : string := "WEIGHT_0"; + ENUM_PRIORITY_7_4 : string := "WEIGHT_0"; + ENUM_PRIORITY_7_5 : string := "WEIGHT_0"; + ENUM_RCFG_STATIC_WEIGHT_0 : string := "WEIGHT_0"; + ENUM_RCFG_STATIC_WEIGHT_1 : string := "WEIGHT_0"; + ENUM_RCFG_STATIC_WEIGHT_2 : string := "WEIGHT_0"; + ENUM_RCFG_STATIC_WEIGHT_3 : string := "WEIGHT_0"; + ENUM_RCFG_STATIC_WEIGHT_4 : string := "WEIGHT_0"; + ENUM_RCFG_STATIC_WEIGHT_5 : string := "WEIGHT_0"; + ENUM_RCFG_USER_PRIORITY_0 : string := "PRIORITY_0"; + ENUM_RCFG_USER_PRIORITY_1 : string := "PRIORITY_0"; + ENUM_RCFG_USER_PRIORITY_2 : string := "PRIORITY_0"; + ENUM_RCFG_USER_PRIORITY_3 : string := "PRIORITY_0"; + ENUM_RCFG_USER_PRIORITY_4 : string := "PRIORITY_0"; + ENUM_RCFG_USER_PRIORITY_5 : string := "PRIORITY_0"; + ENUM_RD_DWIDTH_0 : string := "DWIDTH_0"; + ENUM_RD_DWIDTH_1 : string := "DWIDTH_0"; + ENUM_RD_DWIDTH_2 : string := "DWIDTH_0"; + ENUM_RD_DWIDTH_3 : string := "DWIDTH_0"; + ENUM_RD_DWIDTH_4 : string := "DWIDTH_0"; + ENUM_RD_DWIDTH_5 : string := "DWIDTH_0"; + ENUM_RD_FIFO_IN_USE_0 : string := "FALSE"; + ENUM_RD_FIFO_IN_USE_1 : string := "FALSE"; + ENUM_RD_FIFO_IN_USE_2 : string := "FALSE"; + ENUM_RD_FIFO_IN_USE_3 : string := "FALSE"; + ENUM_RD_PORT_INFO_0 : string := "USE_NO"; + ENUM_RD_PORT_INFO_1 : string := "USE_NO"; + ENUM_RD_PORT_INFO_2 : string := "USE_NO"; + ENUM_RD_PORT_INFO_3 : string := "USE_NO"; + ENUM_RD_PORT_INFO_4 : string := "USE_NO"; + ENUM_RD_PORT_INFO_5 : string := "USE_NO"; + ENUM_READ_ODT_CHIP : string := "ODT_DISABLED"; + ENUM_REORDER_DATA : string := "DATA_REORDERING"; + ENUM_RFIFO0_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_RFIFO1_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_RFIFO2_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_RFIFO3_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_SINGLE_READY_0 : string := "CONCATENATE_RDY"; + ENUM_SINGLE_READY_1 : string := "CONCATENATE_RDY"; + ENUM_SINGLE_READY_2 : string := "CONCATENATE_RDY"; + ENUM_SINGLE_READY_3 : string := "CONCATENATE_RDY"; + ENUM_STATIC_WEIGHT_0 : string := "WEIGHT_0"; + ENUM_STATIC_WEIGHT_1 : string := "WEIGHT_0"; + ENUM_STATIC_WEIGHT_2 : string := "WEIGHT_0"; + ENUM_STATIC_WEIGHT_3 : string := "WEIGHT_0"; + ENUM_STATIC_WEIGHT_4 : string := "WEIGHT_0"; + ENUM_STATIC_WEIGHT_5 : string := "WEIGHT_0"; + ENUM_SYNC_MODE_0 : string := "ASYNCHRONOUS"; + ENUM_SYNC_MODE_1 : string := "ASYNCHRONOUS"; + ENUM_SYNC_MODE_2 : string := "ASYNCHRONOUS"; + ENUM_SYNC_MODE_3 : string := "ASYNCHRONOUS"; + ENUM_SYNC_MODE_4 : string := "ASYNCHRONOUS"; + ENUM_SYNC_MODE_5 : string := "ASYNCHRONOUS"; + ENUM_TEST_MODE : string := "NORMAL_MODE"; + ENUM_THLD_JAR1_0 : string := "THRESHOLD_32"; + ENUM_THLD_JAR1_1 : string := "THRESHOLD_32"; + ENUM_THLD_JAR1_2 : string := "THRESHOLD_32"; + ENUM_THLD_JAR1_3 : string := "THRESHOLD_32"; + ENUM_THLD_JAR1_4 : string := "THRESHOLD_32"; + ENUM_THLD_JAR1_5 : string := "THRESHOLD_32"; + ENUM_THLD_JAR2_0 : string := "THRESHOLD_16"; + ENUM_THLD_JAR2_1 : string := "THRESHOLD_16"; + ENUM_THLD_JAR2_2 : string := "THRESHOLD_16"; + ENUM_THLD_JAR2_3 : string := "THRESHOLD_16"; + ENUM_THLD_JAR2_4 : string := "THRESHOLD_16"; + ENUM_THLD_JAR2_5 : string := "THRESHOLD_16"; + ENUM_USE_ALMOST_EMPTY_0 : string := "EMPTY"; + ENUM_USE_ALMOST_EMPTY_1 : string := "EMPTY"; + ENUM_USE_ALMOST_EMPTY_2 : string := "EMPTY"; + ENUM_USE_ALMOST_EMPTY_3 : string := "EMPTY"; + ENUM_USER_ECC_EN : string := "DISABLE"; + ENUM_USER_PRIORITY_0 : string := "PRIORITY_0"; + ENUM_USER_PRIORITY_1 : string := "PRIORITY_0"; + ENUM_USER_PRIORITY_2 : string := "PRIORITY_0"; + ENUM_USER_PRIORITY_3 : string := "PRIORITY_0"; + ENUM_USER_PRIORITY_4 : string := "PRIORITY_0"; + ENUM_USER_PRIORITY_5 : string := "PRIORITY_0"; + ENUM_WFIFO0_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_WFIFO0_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_WFIFO1_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_WFIFO1_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_WFIFO2_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_WFIFO2_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_WFIFO3_CPORT_MAP : string := "CMD_PORT_0"; + ENUM_WFIFO3_RDY_ALMOST_FULL : string := "NOT_FULL"; + ENUM_WR_DWIDTH_0 : string := "DWIDTH_0"; + ENUM_WR_DWIDTH_1 : string := "DWIDTH_0"; + ENUM_WR_DWIDTH_2 : string := "DWIDTH_0"; + ENUM_WR_DWIDTH_3 : string := "DWIDTH_0"; + ENUM_WR_DWIDTH_4 : string := "DWIDTH_0"; + ENUM_WR_DWIDTH_5 : string := "DWIDTH_0"; + ENUM_WR_FIFO_IN_USE_0 : string := "FALSE"; + ENUM_WR_FIFO_IN_USE_1 : string := "FALSE"; + ENUM_WR_FIFO_IN_USE_2 : string := "FALSE"; + ENUM_WR_FIFO_IN_USE_3 : string := "FALSE"; + ENUM_WR_PORT_INFO_0 : string := "USE_NO"; + ENUM_WR_PORT_INFO_1 : string := "USE_NO"; + ENUM_WR_PORT_INFO_2 : string := "USE_NO"; + ENUM_WR_PORT_INFO_3 : string := "USE_NO"; + ENUM_WR_PORT_INFO_4 : string := "USE_NO"; + ENUM_WR_PORT_INFO_5 : string := "USE_NO"; + ENUM_WRITE_ODT_CHIP : string := "ODT_DISABLED"; + INTG_MEM_AUTO_PD_CYCLES : integer := 0; + INTG_CYC_TO_RLD_JARS_0 : integer := 1; + INTG_CYC_TO_RLD_JARS_1 : integer := 1; + INTG_CYC_TO_RLD_JARS_2 : integer := 1; + INTG_CYC_TO_RLD_JARS_3 : integer := 1; + INTG_CYC_TO_RLD_JARS_4 : integer := 1; + INTG_CYC_TO_RLD_JARS_5 : integer := 1; + INTG_EXTRA_CTL_CLK_ACT_TO_ACT : integer := 0; + INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK : integer := 0; + INTG_EXTRA_CTL_CLK_ACT_TO_PCH : integer := 0; + INTG_EXTRA_CTL_CLK_ACT_TO_RDWR : integer := 0; + INTG_EXTRA_CTL_CLK_ARF_PERIOD : integer := 0; + INTG_EXTRA_CTL_CLK_ARF_TO_VALID : integer := 0; + INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT : integer := 0; + INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID : integer := 0; + INTG_EXTRA_CTL_CLK_PCH_TO_VALID : integer := 0; + INTG_EXTRA_CTL_CLK_PDN_PERIOD : integer := 0; + INTG_EXTRA_CTL_CLK_PDN_TO_VALID : integer := 0; + INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID : integer := 0; + INTG_EXTRA_CTL_CLK_RD_TO_PCH : integer := 0; + INTG_EXTRA_CTL_CLK_RD_TO_RD : integer := 0; + INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP : integer := 0; + INTG_EXTRA_CTL_CLK_RD_TO_WR : integer := 0; + INTG_EXTRA_CTL_CLK_RD_TO_WR_BC : integer := 0; + INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP : integer := 0; + INTG_EXTRA_CTL_CLK_SRF_TO_VALID : integer := 0; + INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL : integer := 0; + INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID : integer := 0; + INTG_EXTRA_CTL_CLK_WR_TO_PCH : integer := 0; + INTG_EXTRA_CTL_CLK_WR_TO_RD : integer := 0; + INTG_EXTRA_CTL_CLK_WR_TO_RD_BC : integer := 0; + INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP : integer := 0; + INTG_EXTRA_CTL_CLK_WR_TO_WR : integer := 0; + INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP : integer := 0; + INTG_MEM_IF_TREFI : integer := 3120; + INTG_MEM_IF_TRFC : integer := 34; + INTG_RCFG_SUM_WT_PRIORITY_0 : integer := 0; + INTG_RCFG_SUM_WT_PRIORITY_1 : integer := 0; + INTG_RCFG_SUM_WT_PRIORITY_2 : integer := 0; + INTG_RCFG_SUM_WT_PRIORITY_3 : integer := 0; + INTG_RCFG_SUM_WT_PRIORITY_4 : integer := 0; + INTG_RCFG_SUM_WT_PRIORITY_5 : integer := 0; + INTG_RCFG_SUM_WT_PRIORITY_6 : integer := 0; + INTG_RCFG_SUM_WT_PRIORITY_7 : integer := 0; + INTG_SUM_WT_PRIORITY_0 : integer := 0; + INTG_SUM_WT_PRIORITY_1 : integer := 0; + INTG_SUM_WT_PRIORITY_2 : integer := 0; + INTG_SUM_WT_PRIORITY_3 : integer := 0; + INTG_SUM_WT_PRIORITY_4 : integer := 0; + INTG_SUM_WT_PRIORITY_5 : integer := 0; + INTG_SUM_WT_PRIORITY_6 : integer := 0; + INTG_SUM_WT_PRIORITY_7 : integer := 0; + INTG_POWER_SAVING_EXIT_CYCLES : integer := 5; + INTG_MEM_CLK_ENTRY_CYCLES : integer := 10; + ENUM_ENABLE_BURST_INTERRUPT : string := "DISABLED"; + ENUM_ENABLE_BURST_TERMINATE : string := "DISABLED"; + AFI_RATE_RATIO : integer := 0; + AFI_ADDR_WIDTH : integer := 0; + AFI_BANKADDR_WIDTH : integer := 0; + AFI_CONTROL_WIDTH : integer := 0; + AFI_CS_WIDTH : integer := 0; + AFI_DM_WIDTH : integer := 0; + AFI_DQ_WIDTH : integer := 0; + AFI_ODT_WIDTH : integer := 0; + AFI_WRITE_DQS_WIDTH : integer := 0; + AFI_RLAT_WIDTH : integer := 0; + AFI_WLAT_WIDTH : integer := 0; + HARD_PHY : boolean := false + ); + port ( + afi_clk : in std_logic := 'X'; -- clk + afi_reset_n : in std_logic := 'X'; -- reset_n + ctl_reset_n : in std_logic := 'X'; -- reset_n + afi_half_clk : in std_logic := 'X'; -- clk + ctl_clk : in std_logic := 'X'; -- clk + mp_cmd_clk_0 : in std_logic := 'X'; -- clk + mp_cmd_reset_n_0 : in std_logic := 'X'; -- reset_n + mp_rfifo_clk_0 : in std_logic := 'X'; -- clk + mp_rfifo_reset_n_0 : in std_logic := 'X'; -- reset_n + mp_wfifo_clk_0 : in std_logic := 'X'; -- clk + mp_wfifo_reset_n_0 : in std_logic := 'X'; -- reset_n + csr_clk : in std_logic := 'X'; -- clk + csr_reset_n : in std_logic := 'X'; -- reset_n + avl_ready_0 : out std_logic; -- waitrequest_n + avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- address + avl_rdata_valid_0 : out std_logic; -- readdatavalid + avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata + avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + avl_read_req_0 : in std_logic := 'X'; -- read + avl_write_req_0 : in std_logic := 'X'; -- write + avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + local_init_done : out std_logic; -- local_init_done + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + csr_write_req : in std_logic := 'X'; -- write + csr_read_req : in std_logic := 'X'; -- read + csr_waitrequest : out std_logic; -- waitrequest + csr_addr : in std_logic_vector(9 downto 0) := (others => 'X'); -- address + csr_be : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable + csr_wdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata + csr_rdata : out std_logic_vector(7 downto 0); -- readdata + csr_rdata_valid : out std_logic; -- readdatavalid + afi_addr : out std_logic_vector(19 downto 0); -- afi_addr + afi_ba : out std_logic_vector(2 downto 0); -- afi_ba + afi_cke : out std_logic_vector(1 downto 0); -- afi_cke + afi_cs_n : out std_logic_vector(1 downto 0); -- afi_cs_n + afi_ras_n : out std_logic_vector(0 downto 0); -- afi_ras_n + afi_we_n : out std_logic_vector(0 downto 0); -- afi_we_n + afi_cas_n : out std_logic_vector(0 downto 0); -- afi_cas_n + afi_rst_n : out std_logic_vector(0 downto 0); -- afi_rst_n + afi_odt : out std_logic_vector(1 downto 0); -- afi_odt + afi_mem_clk_disable : out std_logic_vector(0 downto 0); -- afi_mem_clk_disable + afi_init_req : out std_logic; -- afi_init_req + afi_cal_req : out std_logic; -- afi_cal_req + afi_dqs_burst : out std_logic_vector(4 downto 0); -- afi_dqs_burst + afi_wdata_valid : out std_logic_vector(4 downto 0); -- afi_wdata_valid + afi_wdata : out std_logic_vector(79 downto 0); -- afi_wdata + afi_dm : out std_logic_vector(9 downto 0); -- afi_dm + afi_rdata : in std_logic_vector(79 downto 0) := (others => 'X'); -- afi_rdata + afi_rdata_en : out std_logic_vector(4 downto 0); -- afi_rdata_en + afi_rdata_en_full : out std_logic_vector(4 downto 0); -- afi_rdata_en_full + afi_rdata_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_valid + afi_wlat : in std_logic_vector(3 downto 0) := (others => 'X'); -- afi_wlat + afi_rlat : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_rlat + afi_cal_success : in std_logic := 'X'; -- afi_cal_success + afi_cal_fail : in std_logic := 'X'; -- afi_cal_fail + cfg_addlat : out std_logic_vector(7 downto 0); -- cfg_addlat + cfg_bankaddrwidth : out std_logic_vector(7 downto 0); -- cfg_bankaddrwidth + cfg_caswrlat : out std_logic_vector(7 downto 0); -- cfg_caswrlat + cfg_coladdrwidth : out std_logic_vector(7 downto 0); -- cfg_coladdrwidth + cfg_csaddrwidth : out std_logic_vector(7 downto 0); -- cfg_csaddrwidth + cfg_devicewidth : out std_logic_vector(7 downto 0); -- cfg_devicewidth + cfg_dramconfig : out std_logic_vector(23 downto 0); -- cfg_dramconfig + cfg_interfacewidth : out std_logic_vector(7 downto 0); -- cfg_interfacewidth + cfg_rowaddrwidth : out std_logic_vector(7 downto 0); -- cfg_rowaddrwidth + cfg_tcl : out std_logic_vector(7 downto 0); -- cfg_tcl + cfg_tmrd : out std_logic_vector(7 downto 0); -- cfg_tmrd + cfg_trefi : out std_logic_vector(15 downto 0); -- cfg_trefi + cfg_trfc : out std_logic_vector(7 downto 0); -- cfg_trfc + cfg_twr : out std_logic_vector(7 downto 0); -- cfg_twr + io_intaficalfail : in std_logic := 'X'; -- io_intaficalfail + io_intaficalsuccess : in std_logic := 'X'; -- io_intaficalsuccess + mp_cmd_clk_1 : in std_logic := 'X'; -- clk + mp_cmd_reset_n_1 : in std_logic := 'X'; -- reset_n + mp_cmd_clk_2 : in std_logic := 'X'; -- clk + mp_cmd_reset_n_2 : in std_logic := 'X'; -- reset_n + mp_cmd_clk_3 : in std_logic := 'X'; -- clk + mp_cmd_reset_n_3 : in std_logic := 'X'; -- reset_n + mp_cmd_clk_4 : in std_logic := 'X'; -- clk + mp_cmd_reset_n_4 : in std_logic := 'X'; -- reset_n + mp_cmd_clk_5 : in std_logic := 'X'; -- clk + mp_cmd_reset_n_5 : in std_logic := 'X'; -- reset_n + mp_rfifo_clk_1 : in std_logic := 'X'; -- clk + mp_rfifo_reset_n_1 : in std_logic := 'X'; -- reset_n + mp_wfifo_clk_1 : in std_logic := 'X'; -- clk + mp_wfifo_reset_n_1 : in std_logic := 'X'; -- reset_n + mp_rfifo_clk_2 : in std_logic := 'X'; -- clk + mp_rfifo_reset_n_2 : in std_logic := 'X'; -- reset_n + mp_wfifo_clk_2 : in std_logic := 'X'; -- clk + mp_wfifo_reset_n_2 : in std_logic := 'X'; -- reset_n + mp_rfifo_clk_3 : in std_logic := 'X'; -- clk + mp_rfifo_reset_n_3 : in std_logic := 'X'; -- reset_n + mp_wfifo_clk_3 : in std_logic := 'X'; -- clk + mp_wfifo_reset_n_3 : in std_logic := 'X'; -- reset_n + avl_ready_1 : out std_logic; -- waitrequest_n + avl_burstbegin_1 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_1 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address + avl_rdata_valid_1 : out std_logic; -- readdatavalid + avl_rdata_1 : out std_logic_vector(0 downto 0); -- readdata + avl_wdata_1 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata + avl_be_1 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable + avl_read_req_1 : in std_logic := 'X'; -- read + avl_write_req_1 : in std_logic := 'X'; -- write + avl_size_1 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + avl_ready_2 : out std_logic; -- waitrequest_n + avl_burstbegin_2 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_2 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address + avl_rdata_valid_2 : out std_logic; -- readdatavalid + avl_rdata_2 : out std_logic_vector(0 downto 0); -- readdata + avl_wdata_2 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata + avl_be_2 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable + avl_read_req_2 : in std_logic := 'X'; -- read + avl_write_req_2 : in std_logic := 'X'; -- write + avl_size_2 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + avl_ready_3 : out std_logic; -- waitrequest_n + avl_burstbegin_3 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_3 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address + avl_rdata_valid_3 : out std_logic; -- readdatavalid + avl_rdata_3 : out std_logic_vector(0 downto 0); -- readdata + avl_wdata_3 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata + avl_be_3 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable + avl_read_req_3 : in std_logic := 'X'; -- read + avl_write_req_3 : in std_logic := 'X'; -- write + avl_size_3 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + avl_ready_4 : out std_logic; -- waitrequest_n + avl_burstbegin_4 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_4 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address + avl_rdata_valid_4 : out std_logic; -- readdatavalid + avl_rdata_4 : out std_logic_vector(0 downto 0); -- readdata + avl_wdata_4 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata + avl_be_4 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable + avl_read_req_4 : in std_logic := 'X'; -- read + avl_write_req_4 : in std_logic := 'X'; -- write + avl_size_4 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + avl_ready_5 : out std_logic; -- waitrequest_n + avl_burstbegin_5 : in std_logic := 'X'; -- beginbursttransfer + avl_addr_5 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address + avl_rdata_valid_5 : out std_logic; -- readdatavalid + avl_rdata_5 : out std_logic_vector(0 downto 0); -- readdata + avl_wdata_5 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata + avl_be_5 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable + avl_read_req_5 : in std_logic := 'X'; -- read + avl_write_req_5 : in std_logic := 'X'; -- write + avl_size_5 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + afi_seq_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_seq_busy + afi_ctl_refresh_done : out std_logic_vector(0 downto 0); -- afi_ctl_refresh_done + afi_ctl_long_idle : out std_logic_vector(0 downto 0); -- afi_ctl_long_idle + local_multicast : in std_logic := 'X'; -- local_multicast + local_refresh_req : in std_logic := 'X'; -- local_refresh_req + local_refresh_chip : in std_logic_vector(0 downto 0) := (others => 'X'); -- local_refresh_chip + local_refresh_ack : out std_logic; -- local_refresh_ack + local_self_rfsh_req : in std_logic := 'X'; -- local_self_rfsh_req + local_self_rfsh_chip : in std_logic_vector(0 downto 0) := (others => 'X'); -- local_self_rfsh_chip + local_self_rfsh_ack : out std_logic; -- local_self_rfsh_ack + local_deep_powerdn_req : in std_logic := 'X'; -- local_deep_powerdn_req + local_deep_powerdn_chip : in std_logic_vector(0 downto 0) := (others => 'X'); -- local_deep_powerdn_chip + local_deep_powerdn_ack : out std_logic; -- local_deep_powerdn_ack + local_powerdn_ack : out std_logic; -- local_powerdn_ack + local_priority : in std_logic := 'X'; -- local_priority + bonding_in_1 : in std_logic_vector(3 downto 0) := (others => 'X'); -- bonding1 + bonding_in_2 : in std_logic_vector(5 downto 0) := (others => 'X'); -- bonding2 + bonding_in_3 : in std_logic_vector(5 downto 0) := (others => 'X'); -- bonding3 + bonding_out_1 : out std_logic_vector(3 downto 0); -- bonding1 + bonding_out_2 : out std_logic_vector(5 downto 0); -- bonding2 + bonding_out_3 : out std_logic_vector(5 downto 0) -- bonding3 + ); + end component altera_mem_if_hard_memory_controller_top_cyclonev; + + component altera_mem_if_oct_cyclonev is + generic ( + OCT_TERM_CONTROL_WIDTH : integer := 14 + ); + port ( + oct_rzqin : in std_logic := 'X'; -- rzqin + seriesterminationcontrol : out std_logic_vector(15 downto 0); -- seriesterminationcontrol + parallelterminationcontrol : out std_logic_vector(15 downto 0) -- parallelterminationcontrol + ); + end component altera_mem_if_oct_cyclonev; + + component altera_mem_if_dll_cyclonev is + generic ( + DLL_DELAY_CTRL_WIDTH : integer := 6; + DLL_OFFSET_CTRL_WIDTH : integer := 6; + DELAY_BUFFER_MODE : string := "HIGH"; + DELAY_CHAIN_LENGTH : integer := 8; + DLL_INPUT_FREQUENCY_PS_STR : string := "" + ); + port ( + clk : in std_logic := 'X'; -- clk + dll_pll_locked : in std_logic := 'X'; -- dll_pll_locked + dll_delayctrl : out std_logic_vector(6 downto 0) -- dll_delayctrl + ); + end component altera_mem_if_dll_cyclonev; + + component ddr3_mm_interconnect_1 is + port ( + p0_avl_clk_clk : in std_logic := 'X'; -- clk + dmaster_clk_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset + dmaster_master_translator_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset + dmaster_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address + dmaster_master_waitrequest : out std_logic; -- waitrequest + dmaster_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + dmaster_master_read : in std_logic := 'X'; -- read + dmaster_master_readdata : out std_logic_vector(31 downto 0); -- readdata + dmaster_master_readdatavalid : out std_logic; -- readdatavalid + dmaster_master_write : in std_logic := 'X'; -- write + dmaster_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + s0_seq_debug_address : out std_logic_vector(31 downto 0); -- address + s0_seq_debug_write : out std_logic; -- write + s0_seq_debug_read : out std_logic; -- read + s0_seq_debug_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata + s0_seq_debug_writedata : out std_logic_vector(31 downto 0); -- writedata + s0_seq_debug_burstcount : out std_logic_vector(0 downto 0); -- burstcount + s0_seq_debug_byteenable : out std_logic_vector(3 downto 0); -- byteenable + s0_seq_debug_readdatavalid : in std_logic := 'X'; -- readdatavalid + s0_seq_debug_waitrequest : in std_logic := 'X' -- waitrequest + ); + end component ddr3_mm_interconnect_1; + + component ddr3_mm_interconnect_2 is + port ( + csr_clk_out_clk_clk : in std_logic := 'X'; -- clk + if_csr_m0_clk_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset + p0_csr_reset_n_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset + if_csr_m0_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address + if_csr_m0_master_waitrequest : out std_logic; -- waitrequest + if_csr_m0_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable + if_csr_m0_master_read : in std_logic := 'X'; -- read + if_csr_m0_master_readdata : out std_logic_vector(31 downto 0); -- readdata + if_csr_m0_master_readdatavalid : out std_logic; -- readdatavalid + if_csr_m0_master_write : in std_logic := 'X'; -- write + if_csr_m0_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + c0_csr_address : out std_logic_vector(9 downto 0); -- address + c0_csr_write : out std_logic; -- write + c0_csr_read : out std_logic; -- read + c0_csr_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata + c0_csr_writedata : out std_logic_vector(7 downto 0); -- writedata + c0_csr_byteenable : out std_logic_vector(0 downto 0); -- byteenable + c0_csr_readdatavalid : in std_logic := 'X'; -- readdatavalid + c0_csr_waitrequest : in std_logic := 'X'; -- waitrequest + p0_csr_address : out std_logic_vector(7 downto 0); -- address + p0_csr_write : out std_logic; -- write + p0_csr_read : out std_logic; -- read + p0_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata + p0_csr_writedata : out std_logic_vector(31 downto 0); -- writedata + p0_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable + p0_csr_readdatavalid : in std_logic := 'X'; -- readdatavalid + p0_csr_waitrequest : in std_logic := 'X' -- waitrequest + ); + end component ddr3_mm_interconnect_2; + + component altera_reset_controller is + generic ( + NUM_RESET_INPUTS : integer := 6; + OUTPUT_RESET_SYNC_EDGES : string := "deassert"; + SYNC_DEPTH : integer := 2; + RESET_REQUEST_PRESENT : integer := 0; + RESET_REQ_WAIT_TIME : integer := 1; + MIN_RST_ASSERTION_TIME : integer := 3; + RESET_REQ_EARLY_DSRT_TIME : integer := 1; + USE_RESET_REQUEST_IN0 : integer := 0; + USE_RESET_REQUEST_IN1 : integer := 0; + USE_RESET_REQUEST_IN2 : integer := 0; + USE_RESET_REQUEST_IN3 : integer := 0; + USE_RESET_REQUEST_IN4 : integer := 0; + USE_RESET_REQUEST_IN5 : integer := 0; + USE_RESET_REQUEST_IN6 : integer := 0; + USE_RESET_REQUEST_IN7 : integer := 0; + USE_RESET_REQUEST_IN8 : integer := 0; + USE_RESET_REQUEST_IN9 : integer := 0; + USE_RESET_REQUEST_IN10 : integer := 0; + USE_RESET_REQUEST_IN11 : integer := 0; + USE_RESET_REQUEST_IN12 : integer := 0; + USE_RESET_REQUEST_IN13 : integer := 0; + USE_RESET_REQUEST_IN14 : integer := 0; + USE_RESET_REQUEST_IN15 : integer := 0; + ADAPT_RESET_REQUEST : integer := 0 + ); + port ( + reset_in0 : in std_logic := 'X'; -- reset + clk : in std_logic := 'X'; -- clk + reset_out : out std_logic; -- reset + reset_req : out std_logic; -- reset_req + reset_req_in0 : in std_logic := 'X'; -- reset_req + reset_in1 : in std_logic := 'X'; -- reset + reset_req_in1 : in std_logic := 'X'; -- reset_req + reset_in2 : in std_logic := 'X'; -- reset + reset_req_in2 : in std_logic := 'X'; -- reset_req + reset_in3 : in std_logic := 'X'; -- reset + reset_req_in3 : in std_logic := 'X'; -- reset_req + reset_in4 : in std_logic := 'X'; -- reset + reset_req_in4 : in std_logic := 'X'; -- reset_req + reset_in5 : in std_logic := 'X'; -- reset + reset_req_in5 : in std_logic := 'X'; -- reset_req + reset_in6 : in std_logic := 'X'; -- reset + reset_req_in6 : in std_logic := 'X'; -- reset_req + reset_in7 : in std_logic := 'X'; -- reset + reset_req_in7 : in std_logic := 'X'; -- reset_req + reset_in8 : in std_logic := 'X'; -- reset + reset_req_in8 : in std_logic := 'X'; -- reset_req + reset_in9 : in std_logic := 'X'; -- reset + reset_req_in9 : in std_logic := 'X'; -- reset_req + reset_in10 : in std_logic := 'X'; -- reset + reset_req_in10 : in std_logic := 'X'; -- reset_req + reset_in11 : in std_logic := 'X'; -- reset + reset_req_in11 : in std_logic := 'X'; -- reset_req + reset_in12 : in std_logic := 'X'; -- reset + reset_req_in12 : in std_logic := 'X'; -- reset_req + reset_in13 : in std_logic := 'X'; -- reset + reset_req_in13 : in std_logic := 'X'; -- reset_req + reset_in14 : in std_logic := 'X'; -- reset + reset_req_in14 : in std_logic := 'X'; -- reset_req + reset_in15 : in std_logic := 'X'; -- reset + reset_req_in15 : in std_logic := 'X' -- reset_req + ); + end component altera_reset_controller; + + signal pll0_afi_clk_clk : std_logic; -- pll0:afi_clk -> [afi_clk, c0:afi_clk, p0:afi_clk] + signal pll0_afi_half_clk_clk : std_logic; -- pll0:afi_half_clk -> [afi_half_clk, c0:afi_half_clk, p0:afi_half_clk] + signal p0_afi_reset_reset : std_logic; -- p0:afi_reset_n -> [afi_reset_n, c0:afi_reset_n] + signal p0_afi_afi_rlat : std_logic_vector(4 downto 0); -- p0:afi_rlat -> c0:afi_rlat + signal p0_afi_afi_cal_success : std_logic; -- p0:afi_cal_success -> c0:afi_cal_success + signal p0_afi_afi_rdata : std_logic_vector(79 downto 0); -- p0:afi_rdata -> c0:afi_rdata + signal p0_afi_afi_wlat : std_logic_vector(3 downto 0); -- p0:afi_wlat -> c0:afi_wlat + signal p0_afi_afi_cal_fail : std_logic; -- p0:afi_cal_fail -> c0:afi_cal_fail + signal p0_afi_afi_rdata_valid : std_logic_vector(0 downto 0); -- p0:afi_rdata_valid -> c0:afi_rdata_valid + signal p0_avl_clk_clk : std_logic; -- p0:avl_clk -> [dmaster:clk_clk, mm_interconnect_1:p0_avl_clk_clk, s0:avl_clk] + signal p0_avl_reset_reset : std_logic; -- p0:avl_reset_n -> [p0_avl_reset_reset:in, s0:avl_reset_n] + signal p0_scc_clk_clk : std_logic; -- p0:scc_clk -> s0:scc_clk + signal p0_scc_reset_reset : std_logic; -- p0:scc_reset_n -> s0:reset_n_scc_clk + signal s0_scc_scc_dq_ena : std_logic_vector(15 downto 0); -- s0:scc_dq_ena -> p0:scc_dq_ena + signal s0_scc_scc_upd : std_logic_vector(0 downto 0); -- s0:scc_upd -> p0:scc_upd + signal s0_scc_scc_dqs_io_ena : std_logic_vector(1 downto 0); -- s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena + signal s0_scc_scc_dm_ena : std_logic_vector(1 downto 0); -- s0:scc_dm_ena -> p0:scc_dm_ena + signal p0_scc_capture_strobe_tracking : std_logic_vector(1 downto 0); -- p0:capture_strobe_tracking -> s0:capture_strobe_tracking + signal s0_scc_scc_dqs_ena : std_logic_vector(1 downto 0); -- s0:scc_dqs_ena -> p0:scc_dqs_ena + signal s0_scc_scc_data : std_logic_vector(0 downto 0); -- s0:scc_data -> p0:scc_data + signal s0_avl_readdata : std_logic_vector(31 downto 0); -- p0:avl_readdata -> s0:avl_readdata + signal s0_avl_waitrequest : std_logic; -- p0:avl_waitrequest -> s0:avl_waitrequest + signal s0_avl_address : std_logic_vector(15 downto 0); -- s0:avl_address -> p0:avl_address + signal s0_avl_read : std_logic; -- s0:avl_read -> p0:avl_read + signal s0_avl_write : std_logic; -- s0:avl_write -> p0:avl_write + signal s0_avl_writedata : std_logic_vector(31 downto 0); -- s0:avl_writedata -> p0:avl_writedata + signal dmaster_master_reset_reset : std_logic; -- dmaster:master_reset_reset -> p0:csr_soft_reset_req + signal c0_afi_afi_rdata_en_full : std_logic_vector(4 downto 0); -- c0:afi_rdata_en_full -> p0:afi_rdata_en_full + signal c0_afi_afi_wdata_valid : std_logic_vector(4 downto 0); -- c0:afi_wdata_valid -> p0:afi_wdata_valid + signal c0_afi_afi_rst_n : std_logic_vector(0 downto 0); -- c0:afi_rst_n -> p0:afi_rst_n + signal c0_afi_afi_wdata : std_logic_vector(79 downto 0); -- c0:afi_wdata -> p0:afi_wdata + signal c0_afi_afi_cal_req : std_logic; -- c0:afi_cal_req -> s0:afi_cal_req + signal c0_afi_afi_dqs_burst : std_logic_vector(4 downto 0); -- c0:afi_dqs_burst -> p0:afi_dqs_burst + signal c0_afi_afi_addr : std_logic_vector(19 downto 0); -- c0:afi_addr -> p0:afi_addr + signal c0_afi_afi_ba : std_logic_vector(2 downto 0); -- c0:afi_ba -> p0:afi_ba + signal c0_afi_afi_dm : std_logic_vector(9 downto 0); -- c0:afi_dm -> p0:afi_dm + signal c0_afi_afi_mem_clk_disable : std_logic_vector(0 downto 0); -- c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable + signal c0_afi_afi_init_req : std_logic; -- c0:afi_init_req -> s0:afi_init_req + signal c0_afi_afi_we_n : std_logic_vector(0 downto 0); -- c0:afi_we_n -> p0:afi_we_n + signal c0_afi_afi_cas_n : std_logic_vector(0 downto 0); -- c0:afi_cas_n -> p0:afi_cas_n + signal c0_afi_afi_cs_n : std_logic_vector(1 downto 0); -- c0:afi_cs_n -> p0:afi_cs_n + signal c0_afi_afi_rdata_en : std_logic_vector(4 downto 0); -- c0:afi_rdata_en -> p0:afi_rdata_en + signal c0_afi_afi_odt : std_logic_vector(1 downto 0); -- c0:afi_odt -> p0:afi_odt + signal c0_afi_afi_ras_n : std_logic_vector(0 downto 0); -- c0:afi_ras_n -> p0:afi_ras_n + signal c0_afi_afi_cke : std_logic_vector(1 downto 0); -- c0:afi_cke -> p0:afi_cke + signal c0_hard_phy_cfg_cfg_tmrd : std_logic_vector(7 downto 0); -- c0:cfg_tmrd -> p0:cfg_tmrd + signal c0_hard_phy_cfg_cfg_dramconfig : std_logic_vector(23 downto 0); -- c0:cfg_dramconfig -> p0:cfg_dramconfig + signal c0_hard_phy_cfg_cfg_rowaddrwidth : std_logic_vector(7 downto 0); -- c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth + signal c0_hard_phy_cfg_cfg_devicewidth : std_logic_vector(7 downto 0); -- c0:cfg_devicewidth -> p0:cfg_devicewidth + signal c0_hard_phy_cfg_cfg_trefi : std_logic_vector(15 downto 0); -- c0:cfg_trefi -> p0:cfg_trefi + signal c0_hard_phy_cfg_cfg_tcl : std_logic_vector(7 downto 0); -- c0:cfg_tcl -> p0:cfg_tcl + signal c0_hard_phy_cfg_cfg_csaddrwidth : std_logic_vector(7 downto 0); -- c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth + signal c0_hard_phy_cfg_cfg_coladdrwidth : std_logic_vector(7 downto 0); -- c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth + signal c0_hard_phy_cfg_cfg_trfc : std_logic_vector(7 downto 0); -- c0:cfg_trfc -> p0:cfg_trfc + signal c0_hard_phy_cfg_cfg_addlat : std_logic_vector(7 downto 0); -- c0:cfg_addlat -> p0:cfg_addlat + signal c0_hard_phy_cfg_cfg_bankaddrwidth : std_logic_vector(7 downto 0); -- c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth + signal c0_hard_phy_cfg_cfg_interfacewidth : std_logic_vector(7 downto 0); -- c0:cfg_interfacewidth -> p0:cfg_interfacewidth + signal c0_hard_phy_cfg_cfg_twr : std_logic_vector(7 downto 0); -- c0:cfg_twr -> p0:cfg_twr + signal c0_hard_phy_cfg_cfg_caswrlat : std_logic_vector(7 downto 0); -- c0:cfg_caswrlat -> p0:cfg_caswrlat + signal p0_ctl_clk_clk : std_logic; -- p0:ctl_clk -> c0:ctl_clk + signal p0_ctl_reset_reset : std_logic; -- p0:ctl_reset_n -> c0:ctl_reset_n + signal p0_io_int_io_intaficalfail : std_logic; -- p0:io_intaficalfail -> c0:io_intaficalfail + signal p0_io_int_io_intaficalsuccess : std_logic; -- p0:io_intaficalsuccess -> c0:io_intaficalsuccess + signal oct0_oct_sharing_parallelterminationcontrol : std_logic_vector(15 downto 0); -- oct0:parallelterminationcontrol -> p0:parallelterminationcontrol + signal oct0_oct_sharing_seriesterminationcontrol : std_logic_vector(15 downto 0); -- oct0:seriesterminationcontrol -> p0:seriesterminationcontrol + signal pll0_pll_sharing_pll_write_clk : std_logic; -- pll0:pll_write_clk -> [pll_write_clk, p0:pll_write_clk] + signal pll0_pll_sharing_pll_avl_clk : std_logic; -- pll0:pll_avl_clk -> [pll_avl_clk, p0:pll_avl_clk] + signal pll0_pll_sharing_pll_write_clk_pre_phy_clk : std_logic; -- pll0:pll_write_clk_pre_phy_clk -> [pll_write_clk_pre_phy_clk, p0:pll_write_clk_pre_phy_clk] + signal pll0_pll_sharing_pll_addr_cmd_clk : std_logic; -- pll0:pll_addr_cmd_clk -> [pll_addr_cmd_clk, p0:pll_addr_cmd_clk] + signal pll0_pll_sharing_pll_config_clk : std_logic; -- pll0:pll_config_clk -> [pll_config_clk, p0:pll_config_clk] + signal pll0_pll_sharing_pll_avl_phy_clk : std_logic; -- pll0:pll_avl_phy_clk -> [pll_avl_phy_clk, p0:pll_avl_phy_clk] + signal pll0_pll_sharing_afi_phy_clk : std_logic; -- pll0:afi_phy_clk -> [afi_phy_clk, p0:afi_phy_clk] + signal pll0_pll_sharing_pll_mem_clk : std_logic; -- pll0:pll_mem_clk -> [pll_mem_clk, p0:pll_mem_clk] + signal pll0_pll_sharing_pll_locked : std_logic; -- pll0:pll_locked -> [pll_locked, p0:pll_locked] + signal pll0_pll_sharing_pll_mem_phy_clk : std_logic; -- pll0:pll_mem_phy_clk -> [pll_mem_phy_clk, p0:pll_mem_phy_clk] + signal p0_dll_clk_clk : std_logic; -- p0:dll_clk -> dll0:clk + signal p0_dll_sharing_dll_pll_locked : std_logic; -- p0:dll_pll_locked -> dll0:dll_pll_locked + signal dll0_dll_sharing_dll_delayctrl : std_logic_vector(6 downto 0); -- dll0:dll_delayctrl -> p0:dll_delayctrl + signal dmaster_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_1:dmaster_master_readdata -> dmaster:master_readdata + signal dmaster_master_waitrequest : std_logic; -- mm_interconnect_1:dmaster_master_waitrequest -> dmaster:master_waitrequest + signal dmaster_master_address : std_logic_vector(31 downto 0); -- dmaster:master_address -> mm_interconnect_1:dmaster_master_address + signal dmaster_master_read : std_logic; -- dmaster:master_read -> mm_interconnect_1:dmaster_master_read + signal dmaster_master_byteenable : std_logic_vector(3 downto 0); -- dmaster:master_byteenable -> mm_interconnect_1:dmaster_master_byteenable + signal dmaster_master_readdatavalid : std_logic; -- mm_interconnect_1:dmaster_master_readdatavalid -> dmaster:master_readdatavalid + signal dmaster_master_write : std_logic; -- dmaster:master_write -> mm_interconnect_1:dmaster_master_write + signal dmaster_master_writedata : std_logic_vector(31 downto 0); -- dmaster:master_writedata -> mm_interconnect_1:dmaster_master_writedata + signal mm_interconnect_1_s0_seq_debug_readdata : std_logic_vector(31 downto 0); -- s0:seq_readdata -> mm_interconnect_1:s0_seq_debug_readdata + signal mm_interconnect_1_s0_seq_debug_waitrequest : std_logic; -- s0:seq_waitrequest -> mm_interconnect_1:s0_seq_debug_waitrequest + signal mm_interconnect_1_s0_seq_debug_address : std_logic_vector(31 downto 0); -- mm_interconnect_1:s0_seq_debug_address -> s0:seq_address + signal mm_interconnect_1_s0_seq_debug_read : std_logic; -- mm_interconnect_1:s0_seq_debug_read -> s0:seq_read + signal mm_interconnect_1_s0_seq_debug_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_1:s0_seq_debug_byteenable -> s0:seq_byteenable + signal mm_interconnect_1_s0_seq_debug_readdatavalid : std_logic; -- s0:seq_readdatavalid -> mm_interconnect_1:s0_seq_debug_readdatavalid + signal mm_interconnect_1_s0_seq_debug_write : std_logic; -- mm_interconnect_1:s0_seq_debug_write -> s0:seq_write + signal mm_interconnect_1_s0_seq_debug_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_1:s0_seq_debug_writedata -> s0:seq_writedata + signal mm_interconnect_1_s0_seq_debug_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_1:s0_seq_debug_burstcount -> s0:seq_burstcount + signal if_csr_m0_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_2:if_csr_m0_master_readdata -> if_csr_m0:master_readdata + signal if_csr_m0_master_waitrequest : std_logic; -- mm_interconnect_2:if_csr_m0_master_waitrequest -> if_csr_m0:master_waitrequest + signal if_csr_m0_master_address : std_logic_vector(31 downto 0); -- if_csr_m0:master_address -> mm_interconnect_2:if_csr_m0_master_address + signal if_csr_m0_master_read : std_logic; -- if_csr_m0:master_read -> mm_interconnect_2:if_csr_m0_master_read + signal if_csr_m0_master_byteenable : std_logic_vector(3 downto 0); -- if_csr_m0:master_byteenable -> mm_interconnect_2:if_csr_m0_master_byteenable + signal if_csr_m0_master_readdatavalid : std_logic; -- mm_interconnect_2:if_csr_m0_master_readdatavalid -> if_csr_m0:master_readdatavalid + signal if_csr_m0_master_write : std_logic; -- if_csr_m0:master_write -> mm_interconnect_2:if_csr_m0_master_write + signal if_csr_m0_master_writedata : std_logic_vector(31 downto 0); -- if_csr_m0:master_writedata -> mm_interconnect_2:if_csr_m0_master_writedata + signal mm_interconnect_2_p0_csr_readdata : std_logic_vector(31 downto 0); -- p0:csr_rdata -> mm_interconnect_2:p0_csr_readdata + signal mm_interconnect_2_p0_csr_waitrequest : std_logic; -- p0:csr_waitrequest -> mm_interconnect_2:p0_csr_waitrequest + signal mm_interconnect_2_p0_csr_address : std_logic_vector(7 downto 0); -- mm_interconnect_2:p0_csr_address -> p0:csr_addr + signal mm_interconnect_2_p0_csr_read : std_logic; -- mm_interconnect_2:p0_csr_read -> p0:csr_read_req + signal mm_interconnect_2_p0_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_2:p0_csr_byteenable -> p0:csr_be + signal mm_interconnect_2_p0_csr_readdatavalid : std_logic; -- p0:csr_rdata_valid -> mm_interconnect_2:p0_csr_readdatavalid + signal mm_interconnect_2_p0_csr_write : std_logic; -- mm_interconnect_2:p0_csr_write -> p0:csr_write_req + signal mm_interconnect_2_p0_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_2:p0_csr_writedata -> p0:csr_wdata + signal mm_interconnect_2_c0_csr_readdata : std_logic_vector(7 downto 0); -- c0:csr_rdata -> mm_interconnect_2:c0_csr_readdata + signal mm_interconnect_2_c0_csr_waitrequest : std_logic; -- c0:csr_waitrequest -> mm_interconnect_2:c0_csr_waitrequest + signal mm_interconnect_2_c0_csr_address : std_logic_vector(9 downto 0); -- mm_interconnect_2:c0_csr_address -> c0:csr_addr + signal mm_interconnect_2_c0_csr_read : std_logic; -- mm_interconnect_2:c0_csr_read -> c0:csr_read_req + signal mm_interconnect_2_c0_csr_byteenable : std_logic_vector(0 downto 0); -- mm_interconnect_2:c0_csr_byteenable -> c0:csr_be + signal mm_interconnect_2_c0_csr_readdatavalid : std_logic; -- c0:csr_rdata_valid -> mm_interconnect_2:c0_csr_readdatavalid + signal mm_interconnect_2_c0_csr_write : std_logic; -- mm_interconnect_2:c0_csr_write -> c0:csr_write_req + signal mm_interconnect_2_c0_csr_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_2:c0_csr_writedata -> c0:csr_wdata + signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [mm_interconnect_2:if_csr_m0_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:p0_csr_reset_n_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in] + signal csr_reset_n_ports_inv : std_logic; -- csr_reset_n:inv -> [if_csr_m0:clk_reset_reset, rst_controller:reset_in0] + signal p0_avl_reset_reset_ports_inv : std_logic; -- p0_avl_reset_reset:inv -> [dmaster:clk_reset_reset, mm_interconnect_1:dmaster_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:dmaster_master_translator_reset_reset_bridge_in_reset_reset] + signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [c0:csr_reset_n, p0:csr_reset_n] + +begin + + pll0 : component ddr3_pll0 + port map ( + global_reset_n => global_reset_n, -- global_reset.reset_n + afi_clk => pll0_afi_clk_clk, -- afi_clk.clk + afi_half_clk => pll0_afi_half_clk_clk, -- afi_half_clk.clk + pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk + pll_mem_clk => pll0_pll_sharing_pll_mem_clk, -- pll_sharing.pll_mem_clk + pll_write_clk => pll0_pll_sharing_pll_write_clk, -- .pll_write_clk + pll_locked => pll0_pll_sharing_pll_locked, -- .pll_locked + pll_write_clk_pre_phy_clk => pll0_pll_sharing_pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk => pll0_pll_sharing_pll_addr_cmd_clk, -- .pll_addr_cmd_clk + pll_avl_clk => pll0_pll_sharing_pll_avl_clk, -- .pll_avl_clk + pll_config_clk => pll0_pll_sharing_pll_config_clk, -- .pll_config_clk + pll_mem_phy_clk => pll0_pll_sharing_pll_mem_phy_clk, -- .pll_mem_phy_clk + afi_phy_clk => pll0_pll_sharing_afi_phy_clk, -- .afi_phy_clk + pll_avl_phy_clk => pll0_pll_sharing_pll_avl_phy_clk -- .pll_avl_phy_clk + ); + + p0 : component ddr3_p0 + port map ( + global_reset_n => global_reset_n, -- global_reset.reset_n + soft_reset_n => soft_reset_n, -- soft_reset.reset_n + csr_soft_reset_req => dmaster_master_reset_reset, -- csr_soft_reset_req.reset + afi_reset_n => p0_afi_reset_reset, -- afi_reset.reset_n + afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n + ctl_reset_n => p0_ctl_reset_reset, -- ctl_reset.reset_n + afi_clk => pll0_afi_clk_clk, -- afi_clk.clk + afi_half_clk => pll0_afi_half_clk_clk, -- afi_half_clk.clk + ctl_clk => p0_ctl_clk_clk, -- ctl_clk.clk + avl_clk => p0_avl_clk_clk, -- avl_clk.clk + avl_reset_n => p0_avl_reset_reset, -- avl_reset.reset_n + scc_clk => p0_scc_clk_clk, -- scc_clk.clk + scc_reset_n => p0_scc_reset_reset, -- scc_reset.reset_n + avl_address => s0_avl_address, -- avl.address + avl_write => s0_avl_write, -- .write + avl_writedata => s0_avl_writedata, -- .writedata + avl_read => s0_avl_read, -- .read + avl_readdata => s0_avl_readdata, -- .readdata + avl_waitrequest => s0_avl_waitrequest, -- .waitrequest + dll_clk => p0_dll_clk_clk, -- dll_clk.clk + afi_addr => c0_afi_afi_addr, -- afi.afi_addr + afi_ba => c0_afi_afi_ba, -- .afi_ba + afi_cke => c0_afi_afi_cke, -- .afi_cke + afi_cs_n => c0_afi_afi_cs_n, -- .afi_cs_n + afi_ras_n => c0_afi_afi_ras_n, -- .afi_ras_n + afi_we_n => c0_afi_afi_we_n, -- .afi_we_n + afi_cas_n => c0_afi_afi_cas_n, -- .afi_cas_n + afi_rst_n => c0_afi_afi_rst_n, -- .afi_rst_n + afi_odt => c0_afi_afi_odt, -- .afi_odt + afi_dqs_burst => c0_afi_afi_dqs_burst, -- .afi_dqs_burst + afi_wdata_valid => c0_afi_afi_wdata_valid, -- .afi_wdata_valid + afi_wdata => c0_afi_afi_wdata, -- .afi_wdata + afi_dm => c0_afi_afi_dm, -- .afi_dm + afi_rdata => p0_afi_afi_rdata, -- .afi_rdata + afi_rdata_en => c0_afi_afi_rdata_en, -- .afi_rdata_en + afi_rdata_en_full => c0_afi_afi_rdata_en_full, -- .afi_rdata_en_full + afi_rdata_valid => p0_afi_afi_rdata_valid, -- .afi_rdata_valid + afi_wlat => p0_afi_afi_wlat, -- .afi_wlat + afi_rlat => p0_afi_afi_rlat, -- .afi_rlat + afi_cal_success => p0_afi_afi_cal_success, -- .afi_cal_success + afi_cal_fail => p0_afi_afi_cal_fail, -- .afi_cal_fail + scc_data => s0_scc_scc_data, -- scc.scc_data + scc_dqs_ena => s0_scc_scc_dqs_ena, -- .scc_dqs_ena + scc_dqs_io_ena => s0_scc_scc_dqs_io_ena, -- .scc_dqs_io_ena + scc_dq_ena => s0_scc_scc_dq_ena, -- .scc_dq_ena + scc_dm_ena => s0_scc_scc_dm_ena, -- .scc_dm_ena + capture_strobe_tracking => p0_scc_capture_strobe_tracking, -- .capture_strobe_tracking + scc_upd => s0_scc_scc_upd, -- .scc_upd + cfg_addlat => c0_hard_phy_cfg_cfg_addlat, -- hard_phy_cfg.cfg_addlat + cfg_bankaddrwidth => c0_hard_phy_cfg_cfg_bankaddrwidth, -- .cfg_bankaddrwidth + cfg_caswrlat => c0_hard_phy_cfg_cfg_caswrlat, -- .cfg_caswrlat + cfg_coladdrwidth => c0_hard_phy_cfg_cfg_coladdrwidth, -- .cfg_coladdrwidth + cfg_csaddrwidth => c0_hard_phy_cfg_cfg_csaddrwidth, -- .cfg_csaddrwidth + cfg_devicewidth => c0_hard_phy_cfg_cfg_devicewidth, -- .cfg_devicewidth + cfg_dramconfig => c0_hard_phy_cfg_cfg_dramconfig, -- .cfg_dramconfig + cfg_interfacewidth => c0_hard_phy_cfg_cfg_interfacewidth, -- .cfg_interfacewidth + cfg_rowaddrwidth => c0_hard_phy_cfg_cfg_rowaddrwidth, -- .cfg_rowaddrwidth + cfg_tcl => c0_hard_phy_cfg_cfg_tcl, -- .cfg_tcl + cfg_tmrd => c0_hard_phy_cfg_cfg_tmrd, -- .cfg_tmrd + cfg_trefi => c0_hard_phy_cfg_cfg_trefi, -- .cfg_trefi + cfg_trfc => c0_hard_phy_cfg_cfg_trfc, -- .cfg_trfc + cfg_twr => c0_hard_phy_cfg_cfg_twr, -- .cfg_twr + afi_mem_clk_disable => c0_afi_afi_mem_clk_disable, -- afi_mem_clk_disable.afi_mem_clk_disable + pll_mem_clk => pll0_pll_sharing_pll_mem_clk, -- pll_sharing.pll_mem_clk + pll_write_clk => pll0_pll_sharing_pll_write_clk, -- .pll_write_clk + pll_locked => pll0_pll_sharing_pll_locked, -- .pll_locked + pll_write_clk_pre_phy_clk => pll0_pll_sharing_pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk => pll0_pll_sharing_pll_addr_cmd_clk, -- .pll_addr_cmd_clk + pll_avl_clk => pll0_pll_sharing_pll_avl_clk, -- .pll_avl_clk + pll_config_clk => pll0_pll_sharing_pll_config_clk, -- .pll_config_clk + pll_mem_phy_clk => pll0_pll_sharing_pll_mem_phy_clk, -- .pll_mem_phy_clk + afi_phy_clk => pll0_pll_sharing_afi_phy_clk, -- .afi_phy_clk + pll_avl_phy_clk => pll0_pll_sharing_pll_avl_phy_clk, -- .pll_avl_phy_clk + dll_pll_locked => p0_dll_sharing_dll_pll_locked, -- dll_sharing.dll_pll_locked + dll_delayctrl => dll0_dll_sharing_dll_delayctrl, -- .dll_delayctrl + seriesterminationcontrol => oct0_oct_sharing_seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol + parallelterminationcontrol => oct0_oct_sharing_parallelterminationcontrol, -- .parallelterminationcontrol + mem_a => mem_a, -- memory.mem_a + mem_ba => mem_ba, -- .mem_ba + mem_ck => mem_ck, -- .mem_ck + mem_ck_n => mem_ck_n, -- .mem_ck_n + mem_cke => mem_cke, -- .mem_cke + mem_cs_n => mem_cs_n, -- .mem_cs_n + mem_dm => mem_dm, -- .mem_dm + mem_ras_n => mem_ras_n, -- .mem_ras_n + mem_cas_n => mem_cas_n, -- .mem_cas_n + mem_we_n => mem_we_n, -- .mem_we_n + mem_reset_n => mem_reset_n, -- .mem_reset_n + mem_dq => mem_dq, -- .mem_dq + mem_dqs => mem_dqs, -- .mem_dqs + mem_dqs_n => mem_dqs_n, -- .mem_dqs_n + mem_odt => mem_odt, -- .mem_odt + csr_clk => csr_clk, -- csr_clk.clk + csr_reset_n => rst_controller_reset_out_reset_ports_inv, -- csr_reset_n.reset_n + csr_write_req => mm_interconnect_2_p0_csr_write, -- csr.write + csr_read_req => mm_interconnect_2_p0_csr_read, -- .read + csr_waitrequest => mm_interconnect_2_p0_csr_waitrequest, -- .waitrequest + csr_addr => mm_interconnect_2_p0_csr_address, -- .address + csr_be => mm_interconnect_2_p0_csr_byteenable, -- .byteenable + csr_wdata => mm_interconnect_2_p0_csr_writedata, -- .writedata + csr_rdata => mm_interconnect_2_p0_csr_readdata, -- .readdata + csr_rdata_valid => mm_interconnect_2_p0_csr_readdatavalid, -- .readdatavalid + io_intaficalfail => p0_io_int_io_intaficalfail, -- io_int.io_intaficalfail + io_intaficalsuccess => p0_io_int_io_intaficalsuccess, -- .io_intaficalsuccess + io_intaddrdout => "0000000000000000000000000000000000000000000000000000000000000000", -- (terminated) + io_intbadout => "000000000000", -- (terminated) + io_intcasndout => "0000", -- (terminated) + io_intckdout => "0000", -- (terminated) + io_intckedout => "00000000", -- (terminated) + io_intckndout => "0000", -- (terminated) + io_intcsndout => "00000000", -- (terminated) + io_intdmdout => "00000000000000000000", -- (terminated) + io_intdqdin => open, -- (terminated) + io_intdqdout => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", -- (terminated) + io_intdqoe => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", -- (terminated) + io_intdqsbdout => "00000000000000000000", -- (terminated) + io_intdqsboe => "0000000000", -- (terminated) + io_intdqsdout => "00000000000000000000", -- (terminated) + io_intdqslogicdqsena => "0000000000", -- (terminated) + io_intdqslogicfiforeset => "00000", -- (terminated) + io_intdqslogicincrdataen => "0000000000", -- (terminated) + io_intdqslogicincwrptr => "0000000000", -- (terminated) + io_intdqslogicoct => "0000000000", -- (terminated) + io_intdqslogicrdatavalid => open, -- (terminated) + io_intdqslogicreadlatency => "0000000000000000000000000", -- (terminated) + io_intdqsoe => "0000000000", -- (terminated) + io_intodtdout => "00000000", -- (terminated) + io_intrasndout => "0000", -- (terminated) + io_intresetndout => "0000", -- (terminated) + io_intwendout => "0000", -- (terminated) + io_intafirlat => open, -- (terminated) + io_intafiwlat => open -- (terminated) + ); + + s0 : component ddr3_s0 + port map ( + avl_clk => p0_avl_clk_clk, -- avl_clk.clk + avl_reset_n => p0_avl_reset_reset, -- avl_reset.reset_n + scc_clk => p0_scc_clk_clk, -- scc_clk.clk + reset_n_scc_clk => p0_scc_reset_reset, -- scc_reset.reset_n + scc_data => s0_scc_scc_data, -- scc.scc_data + scc_dqs_ena => s0_scc_scc_dqs_ena, -- .scc_dqs_ena + scc_dqs_io_ena => s0_scc_scc_dqs_io_ena, -- .scc_dqs_io_ena + scc_dq_ena => s0_scc_scc_dq_ena, -- .scc_dq_ena + scc_dm_ena => s0_scc_scc_dm_ena, -- .scc_dm_ena + capture_strobe_tracking => p0_scc_capture_strobe_tracking, -- .capture_strobe_tracking + scc_upd => s0_scc_scc_upd, -- .scc_upd + afi_init_req => c0_afi_afi_init_req, -- afi_init_cal_req.afi_init_req + afi_cal_req => c0_afi_afi_cal_req, -- .afi_cal_req + avl_address => s0_avl_address, -- avl.address + avl_write => s0_avl_write, -- .write + avl_writedata => s0_avl_writedata, -- .writedata + avl_read => s0_avl_read, -- .read + avl_readdata => s0_avl_readdata, -- .readdata + avl_waitrequest => s0_avl_waitrequest, -- .waitrequest + seq_waitrequest => mm_interconnect_1_s0_seq_debug_waitrequest, -- seq_debug.waitrequest + seq_readdata => mm_interconnect_1_s0_seq_debug_readdata, -- .readdata + seq_readdatavalid => mm_interconnect_1_s0_seq_debug_readdatavalid, -- .readdatavalid + seq_burstcount => mm_interconnect_1_s0_seq_debug_burstcount, -- .burstcount + seq_writedata => mm_interconnect_1_s0_seq_debug_writedata, -- .writedata + seq_address => mm_interconnect_1_s0_seq_debug_address, -- .address + seq_write => mm_interconnect_1_s0_seq_debug_write, -- .write + seq_read => mm_interconnect_1_s0_seq_debug_read, -- .read + seq_byteenable => mm_interconnect_1_s0_seq_debug_byteenable, -- .byteenable + seq_debugaccess => '0' -- (terminated) + ); + + dmaster : component ddr3_dmaster + port map ( + clk_clk => p0_avl_clk_clk, -- clk.clk + clk_reset_reset => p0_avl_reset_reset_ports_inv, -- clk_reset.reset + master_address => dmaster_master_address, -- master.address + master_readdata => dmaster_master_readdata, -- .readdata + master_read => dmaster_master_read, -- .read + master_write => dmaster_master_write, -- .write + master_writedata => dmaster_master_writedata, -- .writedata + master_waitrequest => dmaster_master_waitrequest, -- .waitrequest + master_readdatavalid => dmaster_master_readdatavalid, -- .readdatavalid + master_byteenable => dmaster_master_byteenable, -- .byteenable + master_reset_reset => dmaster_master_reset_reset -- master_reset.reset + ); + + c0 : component altera_mem_if_hard_memory_controller_top_cyclonev + generic map ( + MEM_IF_DQS_WIDTH => 2, + MEM_IF_CS_WIDTH => 1, + MEM_IF_CHIP_BITS => 1, + MEM_IF_CLK_PAIR_COUNT => 1, + CSR_ADDR_WIDTH => 10, + CSR_DATA_WIDTH => 8, + CSR_BE_WIDTH => 1, + AVL_ADDR_WIDTH => 25, + AVL_DATA_WIDTH => 32, + AVL_SIZE_WIDTH => 3, + AVL_DATA_WIDTH_PORT_0 => 32, + AVL_ADDR_WIDTH_PORT_0 => 25, + AVL_NUM_SYMBOLS_PORT_0 => 4, + LSB_WFIFO_PORT_0 => 0, + MSB_WFIFO_PORT_0 => 0, + LSB_RFIFO_PORT_0 => 0, + MSB_RFIFO_PORT_0 => 0, + AVL_DATA_WIDTH_PORT_1 => 1, + AVL_ADDR_WIDTH_PORT_1 => 1, + AVL_NUM_SYMBOLS_PORT_1 => 1, + LSB_WFIFO_PORT_1 => 5, + MSB_WFIFO_PORT_1 => 5, + LSB_RFIFO_PORT_1 => 5, + MSB_RFIFO_PORT_1 => 5, + AVL_DATA_WIDTH_PORT_2 => 1, + AVL_ADDR_WIDTH_PORT_2 => 1, + AVL_NUM_SYMBOLS_PORT_2 => 1, + LSB_WFIFO_PORT_2 => 5, + MSB_WFIFO_PORT_2 => 5, + LSB_RFIFO_PORT_2 => 5, + MSB_RFIFO_PORT_2 => 5, + AVL_DATA_WIDTH_PORT_3 => 1, + AVL_ADDR_WIDTH_PORT_3 => 1, + AVL_NUM_SYMBOLS_PORT_3 => 1, + LSB_WFIFO_PORT_3 => 5, + MSB_WFIFO_PORT_3 => 5, + LSB_RFIFO_PORT_3 => 5, + MSB_RFIFO_PORT_3 => 5, + AVL_DATA_WIDTH_PORT_4 => 1, + AVL_ADDR_WIDTH_PORT_4 => 1, + AVL_NUM_SYMBOLS_PORT_4 => 1, + LSB_WFIFO_PORT_4 => 5, + MSB_WFIFO_PORT_4 => 5, + LSB_RFIFO_PORT_4 => 5, + MSB_RFIFO_PORT_4 => 5, + AVL_DATA_WIDTH_PORT_5 => 1, + AVL_ADDR_WIDTH_PORT_5 => 1, + AVL_NUM_SYMBOLS_PORT_5 => 1, + LSB_WFIFO_PORT_5 => 5, + MSB_WFIFO_PORT_5 => 5, + LSB_RFIFO_PORT_5 => 5, + MSB_RFIFO_PORT_5 => 5, + ENUM_ATTR_COUNTER_ONE_RESET => "DISABLED", + ENUM_ATTR_COUNTER_ZERO_RESET => "DISABLED", + ENUM_ATTR_STATIC_CONFIG_VALID => "DISABLED", + ENUM_AUTO_PCH_ENABLE_0 => "DISABLED", + ENUM_AUTO_PCH_ENABLE_1 => "DISABLED", + ENUM_AUTO_PCH_ENABLE_2 => "DISABLED", + ENUM_AUTO_PCH_ENABLE_3 => "DISABLED", + ENUM_AUTO_PCH_ENABLE_4 => "DISABLED", + ENUM_AUTO_PCH_ENABLE_5 => "DISABLED", + ENUM_CAL_REQ => "DISABLED", + ENUM_CFG_BURST_LENGTH => "BL_8", + ENUM_CFG_INTERFACE_WIDTH => "DWIDTH_16", + ENUM_CFG_SELF_RFSH_EXIT_CYCLES => "SELF_RFSH_EXIT_CYCLES_512", + ENUM_CFG_STARVE_LIMIT => "STARVE_LIMIT_4", + ENUM_CFG_TYPE => "DDR3", + ENUM_CLOCK_OFF_0 => "DISABLED", + ENUM_CLOCK_OFF_1 => "DISABLED", + ENUM_CLOCK_OFF_2 => "DISABLED", + ENUM_CLOCK_OFF_3 => "DISABLED", + ENUM_CLOCK_OFF_4 => "DISABLED", + ENUM_CLOCK_OFF_5 => "DISABLED", + ENUM_CLR_INTR => "NO_CLR_INTR", + ENUM_CMD_PORT_IN_USE_0 => "TRUE", + ENUM_CMD_PORT_IN_USE_1 => "FALSE", + ENUM_CMD_PORT_IN_USE_2 => "FALSE", + ENUM_CMD_PORT_IN_USE_3 => "FALSE", + ENUM_CMD_PORT_IN_USE_4 => "FALSE", + ENUM_CMD_PORT_IN_USE_5 => "FALSE", + ENUM_CPORT0_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_CPORT0_RFIFO_MAP => "FIFO_0", + ENUM_CPORT0_TYPE => "BI_DIRECTION", + ENUM_CPORT0_WFIFO_MAP => "FIFO_0", + ENUM_CPORT1_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_CPORT1_RFIFO_MAP => "FIFO_0", + ENUM_CPORT1_TYPE => "DISABLE", + ENUM_CPORT1_WFIFO_MAP => "FIFO_0", + ENUM_CPORT2_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_CPORT2_RFIFO_MAP => "FIFO_0", + ENUM_CPORT2_TYPE => "DISABLE", + ENUM_CPORT2_WFIFO_MAP => "FIFO_0", + ENUM_CPORT3_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_CPORT3_RFIFO_MAP => "FIFO_0", + ENUM_CPORT3_TYPE => "DISABLE", + ENUM_CPORT3_WFIFO_MAP => "FIFO_0", + ENUM_CPORT4_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_CPORT4_RFIFO_MAP => "FIFO_0", + ENUM_CPORT4_TYPE => "DISABLE", + ENUM_CPORT4_WFIFO_MAP => "FIFO_0", + ENUM_CPORT5_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_CPORT5_RFIFO_MAP => "FIFO_0", + ENUM_CPORT5_TYPE => "DISABLE", + ENUM_CPORT5_WFIFO_MAP => "FIFO_0", + ENUM_CTL_ADDR_ORDER => "CHIP_ROW_BANK_COL", + ENUM_CTL_ECC_ENABLED => "CTL_ECC_DISABLED", + ENUM_CTL_ECC_RMW_ENABLED => "CTL_ECC_RMW_DISABLED", + ENUM_CTL_REGDIMM_ENABLED => "REGDIMM_DISABLED", + ENUM_CTL_USR_REFRESH => "CTL_USR_REFRESH_DISABLED", + ENUM_CTRL_WIDTH => "DATA_WIDTH_32_BIT", + ENUM_DELAY_BONDING => "BONDING_LATENCY_0", + ENUM_DFX_BYPASS_ENABLE => "DFX_BYPASS_DISABLED", + ENUM_DISABLE_MERGING => "MERGING_ENABLED", + ENUM_ECC_DQ_WIDTH => "ECC_DQ_WIDTH_0", + ENUM_ENABLE_ATPG => "DISABLED", + ENUM_ENABLE_BONDING_0 => "DISABLED", + ENUM_ENABLE_BONDING_1 => "DISABLED", + ENUM_ENABLE_BONDING_2 => "DISABLED", + ENUM_ENABLE_BONDING_3 => "DISABLED", + ENUM_ENABLE_BONDING_4 => "DISABLED", + ENUM_ENABLE_BONDING_5 => "DISABLED", + ENUM_ENABLE_BONDING_WRAPBACK => "DISABLED", + ENUM_ENABLE_DQS_TRACKING => "DISABLED", + ENUM_ENABLE_ECC_CODE_OVERWRITES => "DISABLED", + ENUM_ENABLE_FAST_EXIT_PPD => "DISABLED", + ENUM_ENABLE_INTR => "DISABLED", + ENUM_ENABLE_NO_DM => "DISABLED", + ENUM_ENABLE_PIPELINEGLOBAL => "DISABLED", + ENUM_GANGED_ARF => "DISABLED", + ENUM_GEN_DBE => "GEN_DBE_DISABLED", + ENUM_GEN_SBE => "GEN_SBE_DISABLED", + ENUM_INC_SYNC => "FIFO_SET_2", + ENUM_LOCAL_IF_CS_WIDTH => "ADDR_WIDTH_0", + ENUM_MASK_CORR_DROPPED_INTR => "DISABLED", + ENUM_MASK_DBE_INTR => "DISABLED", + ENUM_MASK_SBE_INTR => "DISABLED", + ENUM_MEM_IF_AL => "AL_0", + ENUM_MEM_IF_BANKADDR_WIDTH => "ADDR_WIDTH_3", + ENUM_MEM_IF_BURSTLENGTH => "MEM_IF_BURSTLENGTH_8", + ENUM_MEM_IF_COLADDR_WIDTH => "ADDR_WIDTH_10", + ENUM_MEM_IF_CS_PER_RANK => "MEM_IF_CS_PER_RANK_1", + ENUM_MEM_IF_CS_WIDTH => "MEM_IF_CS_WIDTH_1", + ENUM_MEM_IF_DQ_PER_CHIP => "MEM_IF_DQ_PER_CHIP_8", + ENUM_MEM_IF_DQS_WIDTH => "DQS_WIDTH_2", + ENUM_MEM_IF_DWIDTH => "MEM_IF_DWIDTH_16", + ENUM_MEM_IF_MEMTYPE => "DDR3_SDRAM", + ENUM_MEM_IF_ROWADDR_WIDTH => "ADDR_WIDTH_13", + ENUM_MEM_IF_SPEEDBIN => "DDR3_1600_8_8_8", + ENUM_MEM_IF_TCCD => "TCCD_4", + ENUM_MEM_IF_TCL => "TCL_7", + ENUM_MEM_IF_TCWL => "TCWL_6", + ENUM_MEM_IF_TFAW => "TFAW_14", + ENUM_MEM_IF_TMRD => "TMRD_4", + ENUM_MEM_IF_TRAS => "TRAS_11", + ENUM_MEM_IF_TRC => "TRC_15", + ENUM_MEM_IF_TRCD => "TRCD_5", + ENUM_MEM_IF_TRP => "TRP_5", + ENUM_MEM_IF_TRRD => "TRRD_3", + ENUM_MEM_IF_TRTP => "TRTP_3", + ENUM_MEM_IF_TWR => "TWR_5", + ENUM_MEM_IF_TWTR => "TWTR_5", + ENUM_MMR_CFG_MEM_BL => "MP_BL_8", + ENUM_OUTPUT_REGD => "DISABLED", + ENUM_PDN_EXIT_CYCLES => "SLOW_EXIT", + ENUM_PORT0_WIDTH => "PORT_32_BIT", + ENUM_PORT1_WIDTH => "PORT_32_BIT", + ENUM_PORT2_WIDTH => "PORT_32_BIT", + ENUM_PORT3_WIDTH => "PORT_32_BIT", + ENUM_PORT4_WIDTH => "PORT_32_BIT", + ENUM_PORT5_WIDTH => "PORT_32_BIT", + ENUM_PRIORITY_0_0 => "WEIGHT_0", + ENUM_PRIORITY_0_1 => "WEIGHT_0", + ENUM_PRIORITY_0_2 => "WEIGHT_0", + ENUM_PRIORITY_0_3 => "WEIGHT_0", + ENUM_PRIORITY_0_4 => "WEIGHT_0", + ENUM_PRIORITY_0_5 => "WEIGHT_0", + ENUM_PRIORITY_1_0 => "WEIGHT_0", + ENUM_PRIORITY_1_1 => "WEIGHT_0", + ENUM_PRIORITY_1_2 => "WEIGHT_0", + ENUM_PRIORITY_1_3 => "WEIGHT_0", + ENUM_PRIORITY_1_4 => "WEIGHT_0", + ENUM_PRIORITY_1_5 => "WEIGHT_0", + ENUM_PRIORITY_2_0 => "WEIGHT_0", + ENUM_PRIORITY_2_1 => "WEIGHT_0", + ENUM_PRIORITY_2_2 => "WEIGHT_0", + ENUM_PRIORITY_2_3 => "WEIGHT_0", + ENUM_PRIORITY_2_4 => "WEIGHT_0", + ENUM_PRIORITY_2_5 => "WEIGHT_0", + ENUM_PRIORITY_3_0 => "WEIGHT_0", + ENUM_PRIORITY_3_1 => "WEIGHT_0", + ENUM_PRIORITY_3_2 => "WEIGHT_0", + ENUM_PRIORITY_3_3 => "WEIGHT_0", + ENUM_PRIORITY_3_4 => "WEIGHT_0", + ENUM_PRIORITY_3_5 => "WEIGHT_0", + ENUM_PRIORITY_4_0 => "WEIGHT_0", + ENUM_PRIORITY_4_1 => "WEIGHT_0", + ENUM_PRIORITY_4_2 => "WEIGHT_0", + ENUM_PRIORITY_4_3 => "WEIGHT_0", + ENUM_PRIORITY_4_4 => "WEIGHT_0", + ENUM_PRIORITY_4_5 => "WEIGHT_0", + ENUM_PRIORITY_5_0 => "WEIGHT_0", + ENUM_PRIORITY_5_1 => "WEIGHT_0", + ENUM_PRIORITY_5_2 => "WEIGHT_0", + ENUM_PRIORITY_5_3 => "WEIGHT_0", + ENUM_PRIORITY_5_4 => "WEIGHT_0", + ENUM_PRIORITY_5_5 => "WEIGHT_0", + ENUM_PRIORITY_6_0 => "WEIGHT_0", + ENUM_PRIORITY_6_1 => "WEIGHT_0", + ENUM_PRIORITY_6_2 => "WEIGHT_0", + ENUM_PRIORITY_6_3 => "WEIGHT_0", + ENUM_PRIORITY_6_4 => "WEIGHT_0", + ENUM_PRIORITY_6_5 => "WEIGHT_0", + ENUM_PRIORITY_7_0 => "WEIGHT_0", + ENUM_PRIORITY_7_1 => "WEIGHT_0", + ENUM_PRIORITY_7_2 => "WEIGHT_0", + ENUM_PRIORITY_7_3 => "WEIGHT_0", + ENUM_PRIORITY_7_4 => "WEIGHT_0", + ENUM_PRIORITY_7_5 => "WEIGHT_0", + ENUM_RCFG_STATIC_WEIGHT_0 => "WEIGHT_0", + ENUM_RCFG_STATIC_WEIGHT_1 => "WEIGHT_0", + ENUM_RCFG_STATIC_WEIGHT_2 => "WEIGHT_0", + ENUM_RCFG_STATIC_WEIGHT_3 => "WEIGHT_0", + ENUM_RCFG_STATIC_WEIGHT_4 => "WEIGHT_0", + ENUM_RCFG_STATIC_WEIGHT_5 => "WEIGHT_0", + ENUM_RCFG_USER_PRIORITY_0 => "PRIORITY_1", + ENUM_RCFG_USER_PRIORITY_1 => "PRIORITY_1", + ENUM_RCFG_USER_PRIORITY_2 => "PRIORITY_1", + ENUM_RCFG_USER_PRIORITY_3 => "PRIORITY_1", + ENUM_RCFG_USER_PRIORITY_4 => "PRIORITY_1", + ENUM_RCFG_USER_PRIORITY_5 => "PRIORITY_1", + ENUM_RD_DWIDTH_0 => "DWIDTH_32", + ENUM_RD_DWIDTH_1 => "DWIDTH_0", + ENUM_RD_DWIDTH_2 => "DWIDTH_0", + ENUM_RD_DWIDTH_3 => "DWIDTH_0", + ENUM_RD_DWIDTH_4 => "DWIDTH_0", + ENUM_RD_DWIDTH_5 => "DWIDTH_0", + ENUM_RD_FIFO_IN_USE_0 => "TRUE", + ENUM_RD_FIFO_IN_USE_1 => "FALSE", + ENUM_RD_FIFO_IN_USE_2 => "FALSE", + ENUM_RD_FIFO_IN_USE_3 => "FALSE", + ENUM_RD_PORT_INFO_0 => "USE_0", + ENUM_RD_PORT_INFO_1 => "USE_NO", + ENUM_RD_PORT_INFO_2 => "USE_NO", + ENUM_RD_PORT_INFO_3 => "USE_NO", + ENUM_RD_PORT_INFO_4 => "USE_NO", + ENUM_RD_PORT_INFO_5 => "USE_NO", + ENUM_READ_ODT_CHIP => "ODT_DISABLED", + ENUM_REORDER_DATA => "NO_DATA_REORDERING", + ENUM_RFIFO0_CPORT_MAP => "CMD_PORT_0", + ENUM_RFIFO1_CPORT_MAP => "CMD_PORT_0", + ENUM_RFIFO2_CPORT_MAP => "CMD_PORT_0", + ENUM_RFIFO3_CPORT_MAP => "CMD_PORT_0", + ENUM_SINGLE_READY_0 => "CONCATENATE_RDY", + ENUM_SINGLE_READY_1 => "CONCATENATE_RDY", + ENUM_SINGLE_READY_2 => "CONCATENATE_RDY", + ENUM_SINGLE_READY_3 => "CONCATENATE_RDY", + ENUM_STATIC_WEIGHT_0 => "WEIGHT_0", + ENUM_STATIC_WEIGHT_1 => "WEIGHT_0", + ENUM_STATIC_WEIGHT_2 => "WEIGHT_0", + ENUM_STATIC_WEIGHT_3 => "WEIGHT_0", + ENUM_STATIC_WEIGHT_4 => "WEIGHT_0", + ENUM_STATIC_WEIGHT_5 => "WEIGHT_0", + ENUM_SYNC_MODE_0 => "ASYNCHRONOUS", + ENUM_SYNC_MODE_1 => "ASYNCHRONOUS", + ENUM_SYNC_MODE_2 => "ASYNCHRONOUS", + ENUM_SYNC_MODE_3 => "ASYNCHRONOUS", + ENUM_SYNC_MODE_4 => "ASYNCHRONOUS", + ENUM_SYNC_MODE_5 => "ASYNCHRONOUS", + ENUM_TEST_MODE => "NORMAL_MODE", + ENUM_THLD_JAR1_0 => "THRESHOLD_32", + ENUM_THLD_JAR1_1 => "THRESHOLD_32", + ENUM_THLD_JAR1_2 => "THRESHOLD_32", + ENUM_THLD_JAR1_3 => "THRESHOLD_32", + ENUM_THLD_JAR1_4 => "THRESHOLD_32", + ENUM_THLD_JAR1_5 => "THRESHOLD_32", + ENUM_THLD_JAR2_0 => "THRESHOLD_16", + ENUM_THLD_JAR2_1 => "THRESHOLD_16", + ENUM_THLD_JAR2_2 => "THRESHOLD_16", + ENUM_THLD_JAR2_3 => "THRESHOLD_16", + ENUM_THLD_JAR2_4 => "THRESHOLD_16", + ENUM_THLD_JAR2_5 => "THRESHOLD_16", + ENUM_USE_ALMOST_EMPTY_0 => "EMPTY", + ENUM_USE_ALMOST_EMPTY_1 => "EMPTY", + ENUM_USE_ALMOST_EMPTY_2 => "EMPTY", + ENUM_USE_ALMOST_EMPTY_3 => "EMPTY", + ENUM_USER_ECC_EN => "DISABLE", + ENUM_USER_PRIORITY_0 => "PRIORITY_1", + ENUM_USER_PRIORITY_1 => "PRIORITY_1", + ENUM_USER_PRIORITY_2 => "PRIORITY_1", + ENUM_USER_PRIORITY_3 => "PRIORITY_1", + ENUM_USER_PRIORITY_4 => "PRIORITY_1", + ENUM_USER_PRIORITY_5 => "PRIORITY_1", + ENUM_WFIFO0_CPORT_MAP => "CMD_PORT_0", + ENUM_WFIFO0_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_WFIFO1_CPORT_MAP => "CMD_PORT_0", + ENUM_WFIFO1_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_WFIFO2_CPORT_MAP => "CMD_PORT_0", + ENUM_WFIFO2_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_WFIFO3_CPORT_MAP => "CMD_PORT_0", + ENUM_WFIFO3_RDY_ALMOST_FULL => "NOT_FULL", + ENUM_WR_DWIDTH_0 => "DWIDTH_32", + ENUM_WR_DWIDTH_1 => "DWIDTH_0", + ENUM_WR_DWIDTH_2 => "DWIDTH_0", + ENUM_WR_DWIDTH_3 => "DWIDTH_0", + ENUM_WR_DWIDTH_4 => "DWIDTH_0", + ENUM_WR_DWIDTH_5 => "DWIDTH_0", + ENUM_WR_FIFO_IN_USE_0 => "TRUE", + ENUM_WR_FIFO_IN_USE_1 => "FALSE", + ENUM_WR_FIFO_IN_USE_2 => "FALSE", + ENUM_WR_FIFO_IN_USE_3 => "FALSE", + ENUM_WR_PORT_INFO_0 => "USE_0", + ENUM_WR_PORT_INFO_1 => "USE_NO", + ENUM_WR_PORT_INFO_2 => "USE_NO", + ENUM_WR_PORT_INFO_3 => "USE_NO", + ENUM_WR_PORT_INFO_4 => "USE_NO", + ENUM_WR_PORT_INFO_5 => "USE_NO", + ENUM_WRITE_ODT_CHIP => "WRITE_CHIP0_ODT0_CHIP1", + INTG_MEM_AUTO_PD_CYCLES => 0, + INTG_CYC_TO_RLD_JARS_0 => 1, + INTG_CYC_TO_RLD_JARS_1 => 1, + INTG_CYC_TO_RLD_JARS_2 => 1, + INTG_CYC_TO_RLD_JARS_3 => 1, + INTG_CYC_TO_RLD_JARS_4 => 1, + INTG_CYC_TO_RLD_JARS_5 => 1, + INTG_EXTRA_CTL_CLK_ACT_TO_ACT => 0, + INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK => 0, + INTG_EXTRA_CTL_CLK_ACT_TO_PCH => 0, + INTG_EXTRA_CTL_CLK_ACT_TO_RDWR => 0, + INTG_EXTRA_CTL_CLK_ARF_PERIOD => 0, + INTG_EXTRA_CTL_CLK_ARF_TO_VALID => 0, + INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT => 0, + INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID => 0, + INTG_EXTRA_CTL_CLK_PCH_TO_VALID => 0, + INTG_EXTRA_CTL_CLK_PDN_PERIOD => 0, + INTG_EXTRA_CTL_CLK_PDN_TO_VALID => 0, + INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID => 0, + INTG_EXTRA_CTL_CLK_RD_TO_PCH => 0, + INTG_EXTRA_CTL_CLK_RD_TO_RD => 0, + INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP => 0, + INTG_EXTRA_CTL_CLK_RD_TO_WR => 2, + INTG_EXTRA_CTL_CLK_RD_TO_WR_BC => 2, + INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP => 2, + INTG_EXTRA_CTL_CLK_SRF_TO_VALID => 0, + INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL => 0, + INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID => 0, + INTG_EXTRA_CTL_CLK_WR_TO_PCH => 0, + INTG_EXTRA_CTL_CLK_WR_TO_RD => 3, + INTG_EXTRA_CTL_CLK_WR_TO_RD_BC => 3, + INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP => 3, + INTG_EXTRA_CTL_CLK_WR_TO_WR => 0, + INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP => 0, + INTG_MEM_IF_TREFI => 2341, + INTG_MEM_IF_TRFC => 34, + INTG_RCFG_SUM_WT_PRIORITY_0 => 0, + INTG_RCFG_SUM_WT_PRIORITY_1 => 0, + INTG_RCFG_SUM_WT_PRIORITY_2 => 0, + INTG_RCFG_SUM_WT_PRIORITY_3 => 0, + INTG_RCFG_SUM_WT_PRIORITY_4 => 0, + INTG_RCFG_SUM_WT_PRIORITY_5 => 0, + INTG_RCFG_SUM_WT_PRIORITY_6 => 0, + INTG_RCFG_SUM_WT_PRIORITY_7 => 0, + INTG_SUM_WT_PRIORITY_0 => 0, + INTG_SUM_WT_PRIORITY_1 => 0, + INTG_SUM_WT_PRIORITY_2 => 0, + INTG_SUM_WT_PRIORITY_3 => 0, + INTG_SUM_WT_PRIORITY_4 => 0, + INTG_SUM_WT_PRIORITY_5 => 0, + INTG_SUM_WT_PRIORITY_6 => 0, + INTG_SUM_WT_PRIORITY_7 => 0, + INTG_POWER_SAVING_EXIT_CYCLES => 5, + INTG_MEM_CLK_ENTRY_CYCLES => 10, + ENUM_ENABLE_BURST_INTERRUPT => "DISABLED", + ENUM_ENABLE_BURST_TERMINATE => "DISABLED", + AFI_RATE_RATIO => 1, + AFI_ADDR_WIDTH => 13, + AFI_BANKADDR_WIDTH => 3, + AFI_CONTROL_WIDTH => 1, + AFI_CS_WIDTH => 1, + AFI_DM_WIDTH => 4, + AFI_DQ_WIDTH => 32, + AFI_ODT_WIDTH => 1, + AFI_WRITE_DQS_WIDTH => 2, + AFI_RLAT_WIDTH => 6, + AFI_WLAT_WIDTH => 6, + HARD_PHY => true + ) + port map ( + afi_clk => pll0_afi_clk_clk, -- afi_clk.clk + afi_reset_n => p0_afi_reset_reset, -- afi_reset.reset_n + ctl_reset_n => p0_ctl_reset_reset, -- ctl_reset.reset_n + afi_half_clk => pll0_afi_half_clk_clk, -- afi_half_clk.clk + ctl_clk => p0_ctl_clk_clk, -- ctl_clk.clk + mp_cmd_clk_0 => mp_cmd_clk_0_clk, -- mp_cmd_clk_0.clk + mp_cmd_reset_n_0 => mp_cmd_reset_n_0_reset_n, -- mp_cmd_reset_n_0.reset_n + mp_rfifo_clk_0 => mp_rfifo_clk_0_clk, -- mp_rfifo_clk_0.clk + mp_rfifo_reset_n_0 => mp_rfifo_reset_n_0_reset_n, -- mp_rfifo_reset_n_0.reset_n + mp_wfifo_clk_0 => mp_wfifo_clk_0_clk, -- mp_wfifo_clk_0.clk + mp_wfifo_reset_n_0 => mp_wfifo_reset_n_0_reset_n, -- mp_wfifo_reset_n_0.reset_n + csr_clk => csr_clk, -- csr_clk.clk + csr_reset_n => rst_controller_reset_out_reset_ports_inv, -- csr_reset_n.reset_n + avl_ready_0 => avl_ready_0, -- avl_0.waitrequest_n + avl_burstbegin_0 => avl_burstbegin_0, -- .beginbursttransfer + avl_addr_0 => avl_addr_0, -- .address + avl_rdata_valid_0 => avl_rdata_valid_0, -- .readdatavalid + avl_rdata_0 => avl_rdata_0, -- .readdata + avl_wdata_0 => avl_wdata_0, -- .writedata + avl_be_0 => avl_be_0, -- .byteenable + avl_read_req_0 => avl_read_req_0, -- .read + avl_write_req_0 => avl_write_req_0, -- .write + avl_size_0 => avl_size_0, -- .burstcount + local_init_done => local_init_done, -- status.local_init_done + local_cal_success => local_cal_success, -- .local_cal_success + local_cal_fail => local_cal_fail, -- .local_cal_fail + csr_write_req => mm_interconnect_2_c0_csr_write, -- csr.write + csr_read_req => mm_interconnect_2_c0_csr_read, -- .read + csr_waitrequest => mm_interconnect_2_c0_csr_waitrequest, -- .waitrequest + csr_addr => mm_interconnect_2_c0_csr_address, -- .address + csr_be => mm_interconnect_2_c0_csr_byteenable, -- .byteenable + csr_wdata => mm_interconnect_2_c0_csr_writedata, -- .writedata + csr_rdata => mm_interconnect_2_c0_csr_readdata, -- .readdata + csr_rdata_valid => mm_interconnect_2_c0_csr_readdatavalid, -- .readdatavalid + afi_addr => c0_afi_afi_addr, -- afi.afi_addr + afi_ba => c0_afi_afi_ba, -- .afi_ba + afi_cke => c0_afi_afi_cke, -- .afi_cke + afi_cs_n => c0_afi_afi_cs_n, -- .afi_cs_n + afi_ras_n => c0_afi_afi_ras_n, -- .afi_ras_n + afi_we_n => c0_afi_afi_we_n, -- .afi_we_n + afi_cas_n => c0_afi_afi_cas_n, -- .afi_cas_n + afi_rst_n => c0_afi_afi_rst_n, -- .afi_rst_n + afi_odt => c0_afi_afi_odt, -- .afi_odt + afi_mem_clk_disable => c0_afi_afi_mem_clk_disable, -- .afi_mem_clk_disable + afi_init_req => c0_afi_afi_init_req, -- .afi_init_req + afi_cal_req => c0_afi_afi_cal_req, -- .afi_cal_req + afi_dqs_burst => c0_afi_afi_dqs_burst, -- .afi_dqs_burst + afi_wdata_valid => c0_afi_afi_wdata_valid, -- .afi_wdata_valid + afi_wdata => c0_afi_afi_wdata, -- .afi_wdata + afi_dm => c0_afi_afi_dm, -- .afi_dm + afi_rdata => p0_afi_afi_rdata, -- .afi_rdata + afi_rdata_en => c0_afi_afi_rdata_en, -- .afi_rdata_en + afi_rdata_en_full => c0_afi_afi_rdata_en_full, -- .afi_rdata_en_full + afi_rdata_valid => p0_afi_afi_rdata_valid, -- .afi_rdata_valid + afi_wlat => p0_afi_afi_wlat, -- .afi_wlat + afi_rlat => p0_afi_afi_rlat, -- .afi_rlat + afi_cal_success => p0_afi_afi_cal_success, -- .afi_cal_success + afi_cal_fail => p0_afi_afi_cal_fail, -- .afi_cal_fail + cfg_addlat => c0_hard_phy_cfg_cfg_addlat, -- hard_phy_cfg.cfg_addlat + cfg_bankaddrwidth => c0_hard_phy_cfg_cfg_bankaddrwidth, -- .cfg_bankaddrwidth + cfg_caswrlat => c0_hard_phy_cfg_cfg_caswrlat, -- .cfg_caswrlat + cfg_coladdrwidth => c0_hard_phy_cfg_cfg_coladdrwidth, -- .cfg_coladdrwidth + cfg_csaddrwidth => c0_hard_phy_cfg_cfg_csaddrwidth, -- .cfg_csaddrwidth + cfg_devicewidth => c0_hard_phy_cfg_cfg_devicewidth, -- .cfg_devicewidth + cfg_dramconfig => c0_hard_phy_cfg_cfg_dramconfig, -- .cfg_dramconfig + cfg_interfacewidth => c0_hard_phy_cfg_cfg_interfacewidth, -- .cfg_interfacewidth + cfg_rowaddrwidth => c0_hard_phy_cfg_cfg_rowaddrwidth, -- .cfg_rowaddrwidth + cfg_tcl => c0_hard_phy_cfg_cfg_tcl, -- .cfg_tcl + cfg_tmrd => c0_hard_phy_cfg_cfg_tmrd, -- .cfg_tmrd + cfg_trefi => c0_hard_phy_cfg_cfg_trefi, -- .cfg_trefi + cfg_trfc => c0_hard_phy_cfg_cfg_trfc, -- .cfg_trfc + cfg_twr => c0_hard_phy_cfg_cfg_twr, -- .cfg_twr + io_intaficalfail => p0_io_int_io_intaficalfail, -- io_int.io_intaficalfail + io_intaficalsuccess => p0_io_int_io_intaficalsuccess, -- .io_intaficalsuccess + mp_cmd_clk_1 => '0', -- (terminated) + mp_cmd_reset_n_1 => '1', -- (terminated) + mp_cmd_clk_2 => '0', -- (terminated) + mp_cmd_reset_n_2 => '1', -- (terminated) + mp_cmd_clk_3 => '0', -- (terminated) + mp_cmd_reset_n_3 => '1', -- (terminated) + mp_cmd_clk_4 => '0', -- (terminated) + mp_cmd_reset_n_4 => '1', -- (terminated) + mp_cmd_clk_5 => '0', -- (terminated) + mp_cmd_reset_n_5 => '1', -- (terminated) + mp_rfifo_clk_1 => '0', -- (terminated) + mp_rfifo_reset_n_1 => '1', -- (terminated) + mp_wfifo_clk_1 => '0', -- (terminated) + mp_wfifo_reset_n_1 => '1', -- (terminated) + mp_rfifo_clk_2 => '0', -- (terminated) + mp_rfifo_reset_n_2 => '1', -- (terminated) + mp_wfifo_clk_2 => '0', -- (terminated) + mp_wfifo_reset_n_2 => '1', -- (terminated) + mp_rfifo_clk_3 => '0', -- (terminated) + mp_rfifo_reset_n_3 => '1', -- (terminated) + mp_wfifo_clk_3 => '0', -- (terminated) + mp_wfifo_reset_n_3 => '1', -- (terminated) + avl_ready_1 => open, -- (terminated) + avl_burstbegin_1 => '0', -- (terminated) + avl_addr_1 => "0", -- (terminated) + avl_rdata_valid_1 => open, -- (terminated) + avl_rdata_1 => open, -- (terminated) + avl_wdata_1 => "0", -- (terminated) + avl_be_1 => "0", -- (terminated) + avl_read_req_1 => '0', -- (terminated) + avl_write_req_1 => '0', -- (terminated) + avl_size_1 => "000", -- (terminated) + avl_ready_2 => open, -- (terminated) + avl_burstbegin_2 => '0', -- (terminated) + avl_addr_2 => "0", -- (terminated) + avl_rdata_valid_2 => open, -- (terminated) + avl_rdata_2 => open, -- (terminated) + avl_wdata_2 => "0", -- (terminated) + avl_be_2 => "0", -- (terminated) + avl_read_req_2 => '0', -- (terminated) + avl_write_req_2 => '0', -- (terminated) + avl_size_2 => "000", -- (terminated) + avl_ready_3 => open, -- (terminated) + avl_burstbegin_3 => '0', -- (terminated) + avl_addr_3 => "0", -- (terminated) + avl_rdata_valid_3 => open, -- (terminated) + avl_rdata_3 => open, -- (terminated) + avl_wdata_3 => "0", -- (terminated) + avl_be_3 => "0", -- (terminated) + avl_read_req_3 => '0', -- (terminated) + avl_write_req_3 => '0', -- (terminated) + avl_size_3 => "000", -- (terminated) + avl_ready_4 => open, -- (terminated) + avl_burstbegin_4 => '0', -- (terminated) + avl_addr_4 => "0", -- (terminated) + avl_rdata_valid_4 => open, -- (terminated) + avl_rdata_4 => open, -- (terminated) + avl_wdata_4 => "0", -- (terminated) + avl_be_4 => "0", -- (terminated) + avl_read_req_4 => '0', -- (terminated) + avl_write_req_4 => '0', -- (terminated) + avl_size_4 => "000", -- (terminated) + avl_ready_5 => open, -- (terminated) + avl_burstbegin_5 => '0', -- (terminated) + avl_addr_5 => "0", -- (terminated) + avl_rdata_valid_5 => open, -- (terminated) + avl_rdata_5 => open, -- (terminated) + avl_wdata_5 => "0", -- (terminated) + avl_be_5 => "0", -- (terminated) + avl_read_req_5 => '0', -- (terminated) + avl_write_req_5 => '0', -- (terminated) + avl_size_5 => "000", -- (terminated) + afi_seq_busy => "0", -- (terminated) + afi_ctl_refresh_done => open, -- (terminated) + afi_ctl_long_idle => open, -- (terminated) + local_multicast => '0', -- (terminated) + local_refresh_req => '0', -- (terminated) + local_refresh_chip => "0", -- (terminated) + local_refresh_ack => open, -- (terminated) + local_self_rfsh_req => '0', -- (terminated) + local_self_rfsh_chip => "0", -- (terminated) + local_self_rfsh_ack => open, -- (terminated) + local_deep_powerdn_req => '0', -- (terminated) + local_deep_powerdn_chip => "0", -- (terminated) + local_deep_powerdn_ack => open, -- (terminated) + local_powerdn_ack => open, -- (terminated) + local_priority => '0', -- (terminated) + bonding_in_1 => "0000", -- (terminated) + bonding_in_2 => "000000", -- (terminated) + bonding_in_3 => "000000", -- (terminated) + bonding_out_1 => open, -- (terminated) + bonding_out_2 => open, -- (terminated) + bonding_out_3 => open -- (terminated) + ); + + oct0 : component altera_mem_if_oct_cyclonev + generic map ( + OCT_TERM_CONTROL_WIDTH => 16 + ) + port map ( + oct_rzqin => oct_rzqin, -- oct.rzqin + seriesterminationcontrol => oct0_oct_sharing_seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol + parallelterminationcontrol => oct0_oct_sharing_parallelterminationcontrol -- .parallelterminationcontrol + ); + + dll0 : component altera_mem_if_dll_cyclonev + generic map ( + DLL_DELAY_CTRL_WIDTH => 7, + DLL_OFFSET_CTRL_WIDTH => 6, + DELAY_BUFFER_MODE => "HIGH", + DELAY_CHAIN_LENGTH => 8, + DLL_INPUT_FREQUENCY_PS_STR => "3333 ps" + ) + port map ( + clk => p0_dll_clk_clk, -- clk.clk + dll_pll_locked => p0_dll_sharing_dll_pll_locked, -- dll_sharing.dll_pll_locked + dll_delayctrl => dll0_dll_sharing_dll_delayctrl -- .dll_delayctrl + ); + + if_csr_m0 : component ddr3_dmaster + port map ( + clk_clk => csr_clk, -- clk.clk + clk_reset_reset => csr_reset_n_ports_inv, -- clk_reset.reset + master_address => if_csr_m0_master_address, -- master.address + master_readdata => if_csr_m0_master_readdata, -- .readdata + master_read => if_csr_m0_master_read, -- .read + master_write => if_csr_m0_master_write, -- .write + master_writedata => if_csr_m0_master_writedata, -- .writedata + master_waitrequest => if_csr_m0_master_waitrequest, -- .waitrequest + master_readdatavalid => if_csr_m0_master_readdatavalid, -- .readdatavalid + master_byteenable => if_csr_m0_master_byteenable, -- .byteenable + master_reset_reset => open -- master_reset.reset + ); + + mm_interconnect_1 : component ddr3_mm_interconnect_1 + port map ( + p0_avl_clk_clk => p0_avl_clk_clk, -- p0_avl_clk.clk + dmaster_clk_reset_reset_bridge_in_reset_reset => p0_avl_reset_reset_ports_inv, -- dmaster_clk_reset_reset_bridge_in_reset.reset + dmaster_master_translator_reset_reset_bridge_in_reset_reset => p0_avl_reset_reset_ports_inv, -- dmaster_master_translator_reset_reset_bridge_in_reset.reset + dmaster_master_address => dmaster_master_address, -- dmaster_master.address + dmaster_master_waitrequest => dmaster_master_waitrequest, -- .waitrequest + dmaster_master_byteenable => dmaster_master_byteenable, -- .byteenable + dmaster_master_read => dmaster_master_read, -- .read + dmaster_master_readdata => dmaster_master_readdata, -- .readdata + dmaster_master_readdatavalid => dmaster_master_readdatavalid, -- .readdatavalid + dmaster_master_write => dmaster_master_write, -- .write + dmaster_master_writedata => dmaster_master_writedata, -- .writedata + s0_seq_debug_address => mm_interconnect_1_s0_seq_debug_address, -- s0_seq_debug.address + s0_seq_debug_write => mm_interconnect_1_s0_seq_debug_write, -- .write + s0_seq_debug_read => mm_interconnect_1_s0_seq_debug_read, -- .read + s0_seq_debug_readdata => mm_interconnect_1_s0_seq_debug_readdata, -- .readdata + s0_seq_debug_writedata => mm_interconnect_1_s0_seq_debug_writedata, -- .writedata + s0_seq_debug_burstcount => mm_interconnect_1_s0_seq_debug_burstcount, -- .burstcount + s0_seq_debug_byteenable => mm_interconnect_1_s0_seq_debug_byteenable, -- .byteenable + s0_seq_debug_readdatavalid => mm_interconnect_1_s0_seq_debug_readdatavalid, -- .readdatavalid + s0_seq_debug_waitrequest => mm_interconnect_1_s0_seq_debug_waitrequest -- .waitrequest + ); + + mm_interconnect_2 : component ddr3_mm_interconnect_2 + port map ( + csr_clk_out_clk_clk => csr_clk, -- csr_clk_out_clk.clk + if_csr_m0_clk_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- if_csr_m0_clk_reset_reset_bridge_in_reset.reset + p0_csr_reset_n_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- p0_csr_reset_n_reset_bridge_in_reset.reset + if_csr_m0_master_address => if_csr_m0_master_address, -- if_csr_m0_master.address + if_csr_m0_master_waitrequest => if_csr_m0_master_waitrequest, -- .waitrequest + if_csr_m0_master_byteenable => if_csr_m0_master_byteenable, -- .byteenable + if_csr_m0_master_read => if_csr_m0_master_read, -- .read + if_csr_m0_master_readdata => if_csr_m0_master_readdata, -- .readdata + if_csr_m0_master_readdatavalid => if_csr_m0_master_readdatavalid, -- .readdatavalid + if_csr_m0_master_write => if_csr_m0_master_write, -- .write + if_csr_m0_master_writedata => if_csr_m0_master_writedata, -- .writedata + c0_csr_address => mm_interconnect_2_c0_csr_address, -- c0_csr.address + c0_csr_write => mm_interconnect_2_c0_csr_write, -- .write + c0_csr_read => mm_interconnect_2_c0_csr_read, -- .read + c0_csr_readdata => mm_interconnect_2_c0_csr_readdata, -- .readdata + c0_csr_writedata => mm_interconnect_2_c0_csr_writedata, -- .writedata + c0_csr_byteenable => mm_interconnect_2_c0_csr_byteenable, -- .byteenable + c0_csr_readdatavalid => mm_interconnect_2_c0_csr_readdatavalid, -- .readdatavalid + c0_csr_waitrequest => mm_interconnect_2_c0_csr_waitrequest, -- .waitrequest + p0_csr_address => mm_interconnect_2_p0_csr_address, -- p0_csr.address + p0_csr_write => mm_interconnect_2_p0_csr_write, -- .write + p0_csr_read => mm_interconnect_2_p0_csr_read, -- .read + p0_csr_readdata => mm_interconnect_2_p0_csr_readdata, -- .readdata + p0_csr_writedata => mm_interconnect_2_p0_csr_writedata, -- .writedata + p0_csr_byteenable => mm_interconnect_2_p0_csr_byteenable, -- .byteenable + p0_csr_readdatavalid => mm_interconnect_2_p0_csr_readdatavalid, -- .readdatavalid + p0_csr_waitrequest => mm_interconnect_2_p0_csr_waitrequest -- .waitrequest + ); + + rst_controller : component altera_reset_controller + generic map ( + NUM_RESET_INPUTS => 1, + OUTPUT_RESET_SYNC_EDGES => "deassert", + SYNC_DEPTH => 2, + RESET_REQUEST_PRESENT => 0, + RESET_REQ_WAIT_TIME => 1, + MIN_RST_ASSERTION_TIME => 3, + RESET_REQ_EARLY_DSRT_TIME => 1, + USE_RESET_REQUEST_IN0 => 0, + USE_RESET_REQUEST_IN1 => 0, + USE_RESET_REQUEST_IN2 => 0, + USE_RESET_REQUEST_IN3 => 0, + USE_RESET_REQUEST_IN4 => 0, + USE_RESET_REQUEST_IN5 => 0, + USE_RESET_REQUEST_IN6 => 0, + USE_RESET_REQUEST_IN7 => 0, + USE_RESET_REQUEST_IN8 => 0, + USE_RESET_REQUEST_IN9 => 0, + USE_RESET_REQUEST_IN10 => 0, + USE_RESET_REQUEST_IN11 => 0, + USE_RESET_REQUEST_IN12 => 0, + USE_RESET_REQUEST_IN13 => 0, + USE_RESET_REQUEST_IN14 => 0, + USE_RESET_REQUEST_IN15 => 0, + ADAPT_RESET_REQUEST => 0 + ) + port map ( + reset_in0 => csr_reset_n_ports_inv, -- reset_in0.reset + clk => csr_clk, -- clk.clk + reset_out => rst_controller_reset_out_reset, -- reset_out.reset + reset_req => open, -- (terminated) + reset_req_in0 => '0', -- (terminated) + reset_in1 => '0', -- (terminated) + reset_req_in1 => '0', -- (terminated) + reset_in2 => '0', -- (terminated) + reset_req_in2 => '0', -- (terminated) + reset_in3 => '0', -- (terminated) + reset_req_in3 => '0', -- (terminated) + reset_in4 => '0', -- (terminated) + reset_req_in4 => '0', -- (terminated) + reset_in5 => '0', -- (terminated) + reset_req_in5 => '0', -- (terminated) + reset_in6 => '0', -- (terminated) + reset_req_in6 => '0', -- (terminated) + reset_in7 => '0', -- (terminated) + reset_req_in7 => '0', -- (terminated) + reset_in8 => '0', -- (terminated) + reset_req_in8 => '0', -- (terminated) + reset_in9 => '0', -- (terminated) + reset_req_in9 => '0', -- (terminated) + reset_in10 => '0', -- (terminated) + reset_req_in10 => '0', -- (terminated) + reset_in11 => '0', -- (terminated) + reset_req_in11 => '0', -- (terminated) + reset_in12 => '0', -- (terminated) + reset_req_in12 => '0', -- (terminated) + reset_in13 => '0', -- (terminated) + reset_req_in13 => '0', -- (terminated) + reset_in14 => '0', -- (terminated) + reset_req_in14 => '0', -- (terminated) + reset_in15 => '0', -- (terminated) + reset_req_in15 => '0' -- (terminated) + ); + + p0_avl_reset_reset_ports_inv <= not p0_avl_reset_reset; + + rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset; + + afi_clk <= pll0_afi_clk_clk; + + afi_half_clk <= pll0_afi_half_clk_clk; + + afi_reset_n <= p0_afi_reset_reset; + + pll_write_clk <= pll0_pll_sharing_pll_write_clk; + + pll_avl_clk <= pll0_pll_sharing_pll_avl_clk; + + pll_write_clk_pre_phy_clk <= pll0_pll_sharing_pll_write_clk_pre_phy_clk; + + pll_addr_cmd_clk <= pll0_pll_sharing_pll_addr_cmd_clk; + + pll_config_clk <= pll0_pll_sharing_pll_config_clk; + + pll_avl_phy_clk <= pll0_pll_sharing_pll_avl_phy_clk; + + afi_phy_clk <= pll0_pll_sharing_afi_phy_clk; + + pll_mem_clk <= pll0_pll_sharing_pll_mem_clk; + + pll_locked <= pll0_pll_sharing_pll_locked; + + pll_mem_phy_clk <= pll0_pll_sharing_pll_mem_phy_clk; + +end architecture rtl; -- of ddr3_0002 diff --git a/ip/altera/ddr3_sim/ddr3/ddr3_pll0.vho b/ip/altera/ddr3_sim/ddr3/ddr3_pll0.vho new file mode 100644 index 0000000..e98d493 --- /dev/null +++ b/ip/altera/ddr3_sim/ddr3/ddr3_pll0.vho @@ -0,0 +1,225 @@ +--IP Functional Simulation Model +--VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:19:02:34:SJ cbx_simgen 2015:10:14:18:59:15:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus Prime License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY altera_lnsim; + USE altera_lnsim.altera_lnsim_components.all; + +--synthesis_resources = generic_pll 9 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY ddr3_pll0 IS + PORT + ( + afi_clk : OUT STD_LOGIC; + afi_half_clk : OUT STD_LOGIC; + afi_phy_clk : OUT STD_LOGIC; + global_reset_n : IN STD_LOGIC; + pll_addr_cmd_clk : OUT STD_LOGIC; + pll_avl_clk : OUT STD_LOGIC; + pll_avl_phy_clk : OUT STD_LOGIC; + pll_config_clk : OUT STD_LOGIC; + pll_locked : OUT STD_LOGIC; + pll_mem_clk : OUT STD_LOGIC; + pll_mem_phy_clk : OUT STD_LOGIC; + pll_ref_clk : IN STD_LOGIC; + pll_write_clk : OUT STD_LOGIC; + pll_write_clk_pre_phy_clk : OUT STD_LOGIC + ); + END ddr3_pll0; + + ARCHITECTURE RTL OF ddr3_pll0 IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_fboutclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_locked : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll1_phy_58_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll1_phy_58_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll2_60_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll2_60_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll2_phy_62_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll2_phy_62_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll3_64_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll3_64_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll4_66_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll4_66_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll6_68_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll6_68_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll6_phy_70_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll6_phy_70_rst : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll7_72_outclk : STD_LOGIC; + SIGNAL wire_ddr3_pll0_generic_pll_pll7_72_rst : STD_LOGIC; + SIGNAL wire_w_lg_global_reset_n1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_global_reset_n1w(0) <= NOT global_reset_n; + afi_clk <= wire_ddr3_pll0_generic_pll_pll1_56_outclk; + afi_half_clk <= '0'; + afi_phy_clk <= wire_ddr3_pll0_generic_pll_pll1_phy_58_outclk; + pll_addr_cmd_clk <= wire_ddr3_pll0_generic_pll_pll4_66_outclk; + pll_avl_clk <= wire_ddr3_pll0_generic_pll_pll6_68_outclk; + pll_avl_phy_clk <= wire_ddr3_pll0_generic_pll_pll6_phy_70_outclk; + pll_config_clk <= wire_ddr3_pll0_generic_pll_pll7_72_outclk; + pll_locked <= wire_ddr3_pll0_generic_pll_pll1_56_locked; + pll_mem_clk <= wire_ddr3_pll0_generic_pll_pll2_60_outclk; + pll_mem_phy_clk <= wire_ddr3_pll0_generic_pll_pll2_phy_62_outclk; + pll_write_clk <= wire_ddr3_pll0_generic_pll_pll3_64_outclk; + pll_write_clk_pre_phy_clk <= wire_ddr3_pll0_generic_pll_pll3_64_outclk; + wire_ddr3_pll0_generic_pll_pll1_56_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll1_56 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "3334 ps", + phase_shift => "0 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + fboutclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + locked => wire_ddr3_pll0_generic_pll_pll1_56_locked, + outclk => wire_ddr3_pll0_generic_pll_pll1_56_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll1_56_rst + ); + wire_ddr3_pll0_generic_pll_pll1_phy_58_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll1_phy_58 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "3334 ps", + phase_shift => "0 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll1_phy_58_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll1_phy_58_rst + ); + wire_ddr3_pll0_generic_pll_pll2_60_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll2_60 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "3334 ps", + phase_shift => "0 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll2_60_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll2_60_rst + ); + wire_ddr3_pll0_generic_pll_pll2_phy_62_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll2_phy_62 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "3334 ps", + phase_shift => "0 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll2_phy_62_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll2_phy_62_rst + ); + wire_ddr3_pll0_generic_pll_pll3_64_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll3_64 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "3334 ps", + phase_shift => "2500 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll3_64_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll3_64_rst + ); + wire_ddr3_pll0_generic_pll_pll4_66_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll4_66 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "3334 ps", + phase_shift => "2500 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll4_66_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll4_66_rst + ); + wire_ddr3_pll0_generic_pll_pll6_68_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll6_68 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "16670 ps", + phase_shift => "416 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll6_68_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll6_68_rst + ); + wire_ddr3_pll0_generic_pll_pll6_phy_70_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll6_phy_70 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "16670 ps", + phase_shift => "416 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll6_phy_70_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll6_phy_70_rst + ); + wire_ddr3_pll0_generic_pll_pll7_72_rst <= wire_w_lg_global_reset_n1w(0); + ddr3_pll0_generic_pll_pll7_72 : generic_pll + GENERIC MAP ( + duty_cycle => 50, + output_clock_frequency => "50010 ps", + phase_shift => "0 ps", + reference_clock_frequency => "50.0 MHz" + ) + PORT MAP ( + fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk, + outclk => wire_ddr3_pll0_generic_pll_pll7_72_outclk, + refclk => pll_ref_clk, + rst => wire_ddr3_pll0_generic_pll_pll7_72_rst + ); + + END RTL; --ddr3_pll0 +--synopsys translate_on +--VALID FILE diff --git a/ip/altera/ddr3_sim/ddr3/ddr3_pll0_sim_delay.vhd b/ip/altera/ddr3_sim/ddr3/ddr3_pll0_sim_delay.vhd new file mode 100644 index 0000000..a900c1d --- /dev/null +++ b/ip/altera/ddr3_sim/ddr3/ddr3_pll0_sim_delay.vhd @@ -0,0 +1,31 @@ +-- (C) 2001-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License Subscription +-- Agreement, Altera MegaCore Function License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + + +Library ieee; +use ieee.std_logic_1164.all; + +entity ddr3_pll0_sim_delay is + generic ( + delay : natural := 1); + + port ( + o : out std_logic; + i : in std_logic); +end ddr3_pll0_sim_delay; + +architecture behavior of ddr3_pll0_sim_delay is +begin + o <= i after delay * 1 ps; +end behavior; + diff --git a/ip/altera/ddr3_sim/mentor/msim_setup.tcl b/ip/altera/ddr3_sim/mentor/msim_setup.tcl new file mode 100644 index 0000000..45c7488 --- /dev/null +++ b/ip/altera/ddr3_sim/mentor/msim_setup.tcl @@ -0,0 +1,229 @@ + +# (C) 2001-2016 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ---------------------------------------- +# Auto-generated simulation script msim_setup.tcl +# ---------------------------------------- +# This script can be used to simulate the following IP: +# ddr3 +# To create a top-level simulation script which compiles other +# IP, and manages other system issues, copy the following template +# and adapt it to your needs: +# +# # Start of template +# # If the copied and modified template file is "mentor.do", run it as: +# # vsim -c -do mentor.do +# # +# # Source the generated sim script +# source msim_setup.tcl +# # Compile eda/sim_lib contents first +# dev_com +# # Override the top-level name (so that elab is useful) +# set TOP_LEVEL_NAME top +# # Compile the standalone IP. +# com +# # Compile the user top-level +# vlog -sv ../../top.sv +# # Elaborate the design. +# elab +# # Run the simulation +# run -a +# # Report success to the shell +# exit -code 0 +# # End of template +# ---------------------------------------- +# If ddr3 is one of several IP cores in your +# Quartus project, you can generate a simulation script +# suitable for inclusion in your top-level simulation +# script by running the following command line: +# +# ip-setup-simulation --quartus-project= +# +# ip-setup-simulation will discover the Altera IP +# within the Quartus project, and generate a unified +# script which supports all the Altera IP within the design. +# ---------------------------------------- +# ACDS 15.1 185 linux 2016.01.17.15:36:30 + +# ---------------------------------------- +# Initialize variables +if ![info exists SYSTEM_INSTANCE_NAME] { + set SYSTEM_INSTANCE_NAME "" +} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { + set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME" +} + +if ![info exists TOP_LEVEL_NAME] { + set TOP_LEVEL_NAME "ddr3" +} + +if ![info exists QSYS_SIMDIR] { + set QSYS_SIMDIR "./../" +} + +if ![info exists QUARTUS_INSTALL_DIR] { + set QUARTUS_INSTALL_DIR "/opt/altera/15.1/quartus/" +} + +if ![info exists USER_DEFINED_COMPILE_OPTIONS] { + set USER_DEFINED_COMPILE_OPTIONS "" +} +if ![info exists USER_DEFINED_ELAB_OPTIONS] { + set USER_DEFINED_ELAB_OPTIONS "" +} + +# ---------------------------------------- +# Initialize simulation properties - DO NOT MODIFY! +set ELAB_OPTIONS "" +set SIM_OPTIONS "" +if ![ string match "*-64 vsim*" [ vsim -version ] ] { +} else { +} + +# ---------------------------------------- +# Copy ROM/RAM files to simulation directory +alias file_copy { + echo "\[exec\] file_copy" +} + +# ---------------------------------------- +# Create compilation libraries +proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } } +ensure_lib ./libraries/ +ensure_lib ./libraries/work/ +vmap work ./libraries/work/ +vmap work_lib ./libraries/work/ +if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] { + ensure_lib ./libraries/altera/ + vmap altera ./libraries/altera/ + ensure_lib ./libraries/lpm/ + vmap lpm ./libraries/lpm/ + ensure_lib ./libraries/sgate/ + vmap sgate ./libraries/sgate/ + ensure_lib ./libraries/altera_mf/ + vmap altera_mf ./libraries/altera_mf/ + ensure_lib ./libraries/altera_lnsim/ + vmap altera_lnsim ./libraries/altera_lnsim/ + ensure_lib ./libraries/cyclonev/ + vmap cyclonev ./libraries/cyclonev/ +} +ensure_lib ./libraries/pll0/ +vmap pll0 ./libraries/pll0/ +ensure_lib ./libraries/ddr3/ +vmap ddr3 ./libraries/ddr3/ + +# ---------------------------------------- +# Compile device library files +alias dev_com { + echo "\[exec\] dev_com" + if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] { + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf + eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim + eval vlog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev + } +} + +# ---------------------------------------- +# Compile the design files in correct order +alias com { + echo "\[exec\] com" + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0.vho" -work pll0 + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0_sim_delay.vhd" -work pll0 + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_0002.vhd" -work ddr3 + eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3.vhd" +} + +# ---------------------------------------- +# Elaborate top level design +alias elab { + echo "\[exec\] elab" + eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L pll0 -L ddr3 -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME +} + +# ---------------------------------------- +# Elaborate the top level design with novopt option +alias elab_debug { + echo "\[exec\] elab_debug" + eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L pll0 -L ddr3 -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME +} + +# ---------------------------------------- +# Compile all the design files and elaborate the top level design +alias ld " + dev_com + com + elab +" + +# ---------------------------------------- +# Compile all the design files and elaborate the top level design with -novopt +alias ld_debug " + dev_com + com + elab_debug +" + +# ---------------------------------------- +# Print out user commmand line aliases +alias h { + echo "List Of Command Line Aliases" + echo + echo "file_copy -- Copy ROM/RAM files to simulation directory" + echo + echo "dev_com -- Compile device library files" + echo + echo "com -- Compile the design files in correct order" + echo + echo "elab -- Elaborate top level design" + echo + echo "elab_debug -- Elaborate the top level design with novopt option" + echo + echo "ld -- Compile all the design files and elaborate the top level design" + echo + echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt" + echo + echo + echo + echo "List Of Variables" + echo + echo "TOP_LEVEL_NAME -- Top level module name." + echo " For most designs, this should be overridden" + echo " to enable the elab/elab_debug aliases." + echo + echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module." + echo + echo "QSYS_SIMDIR -- Qsys base simulation directory." + echo + echo "QUARTUS_INSTALL_DIR -- Quartus installation directory." + echo + echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases." + echo + echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases." +} +file_copy +h diff --git a/ip/altera/ddr3_sim/synopsys/vcsmx/synopsys_sim.setup b/ip/altera/ddr3_sim/synopsys/vcsmx/synopsys_sim.setup new file mode 100644 index 0000000..ac93dc2 --- /dev/null +++ b/ip/altera/ddr3_sim/synopsys/vcsmx/synopsys_sim.setup @@ -0,0 +1,13 @@ + +WORK > DEFAULT +DEFAULT: ./libraries/work/ +work: ./libraries/work/ +pll0: ./libraries/pll0/ +ddr3: ./libraries/ddr3/ +altera: ./libraries/altera/ +lpm: ./libraries/lpm/ +sgate: ./libraries/sgate/ +altera_mf: ./libraries/altera_mf/ +altera_lnsim: ./libraries/altera_lnsim/ +cyclonev: ./libraries/cyclonev/ +LIBRARY_SCAN = TRUE diff --git a/ip/altera/ddr3_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/altera/ddr3_sim/synopsys/vcsmx/vcsmx_setup.sh new file mode 100755 index 0000000..0f065f4 --- /dev/null +++ b/ip/altera/ddr3_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -0,0 +1,155 @@ + +# (C) 2001-2016 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 15.1 185 linux 2016.01.17.15:36:30 + +# ---------------------------------------- +# vcsmx - auto-generated simulation script + +# ---------------------------------------- +# This script can be used to simulate the following IP: +# ddr3 +# To create a top-level simulation script which compiles other +# IP, and manages other system issues, copy the following template +# and adapt it to your needs: +# +# # Start of template +# # If the copied and modified template file is "vcsmx_sim.sh", run it as: +# # ./vcsmx_sim.sh +# # +# # Do the file copy, dev_com and com steps +# source vcsmx_setup.sh \ +# SKIP_ELAB=1 \ +# SKIP_SIM=1 +# +# # Compile the top level module +# vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" +# +# # Do the elaboration and sim steps +# # Override the top-level name +# # Override the user-defined sim options, so the simulation runs +# # forever (until $finish()). +# source vcsmx_setup.sh \ +# SKIP_FILE_COPY=1 \ +# SKIP_DEV_COM=1 \ +# SKIP_COM=1 \ +# TOP_LEVEL_NAME="'-top top'" \ +# USER_DEFINED_SIM_OPTIONS="" +# # End of template +# ---------------------------------------- +# If ddr3 is one of several IP cores in your +# Quartus project, you can generate a simulation script +# suitable for inclusion in your top-level simulation +# script by running the following command line: +# +# ip-setup-simulation --quartus-project= +# +# ip-setup-simulation will discover the Altera IP +# within the Quartus project, and generate a unified +# script which supports all the Altera IP within the design. +# ---------------------------------------- +# ACDS 15.1 185 linux 2016.01.17.15:36:30 +# ---------------------------------------- +# initialize variables +TOP_LEVEL_NAME="ddr3" +QSYS_SIMDIR="./../../" +QUARTUS_INSTALL_DIR="/opt/altera/15.1/quartus/" +SKIP_FILE_COPY=0 +SKIP_DEV_COM=0 +SKIP_COM=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_ELAB=1 SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +# ---------------------------------------- +# create compilation libraries +mkdir -p ./libraries/work/ +mkdir -p ./libraries/pll0/ +mkdir -p ./libraries/ddr3/ +mkdir -p ./libraries/altera/ +mkdir -p ./libraries/lpm/ +mkdir -p ./libraries/sgate/ +mkdir -p ./libraries/altera_mf/ +mkdir -p ./libraries/altera_lnsim/ +mkdir -p ./libraries/cyclonev/ + +# ---------------------------------------- +# copy RAM/ROM files to simulation directory + +# ---------------------------------------- +# compile device library files +if [ $SKIP_DEV_COM -eq 0 ]; then + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf + vlogan +v2k -sverilog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim + vlogan +v2k $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev + vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev +fi + +# ---------------------------------------- +# compile design files in correct order +if [ $SKIP_COM -eq 0 ]; then + vhdlan -xlrm $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0.vho" -work pll0 + vhdlan -xlrm $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0_sim_delay.vhd" -work pll0 + vhdlan -xlrm $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_0002.vhd" -work ddr3 + vhdlan -xlrm $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3.vhd" +fi + +# ---------------------------------------- +# elaborate top level design +if [ $SKIP_ELAB -eq 0 ]; then + vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME +fi + +# ---------------------------------------- +# simulate +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS +fi diff --git a/ip/altera/ram0.qip b/ip/altera/ram0.qip new file mode 100644 index 0000000..212b9b1 --- /dev/null +++ b/ip/altera/ram0.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "15.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram0.vhd"] diff --git a/ip/altera/ram0.vhd b/ip/altera/ram0.vhd new file mode 100644 index 0000000..39459fa --- /dev/null +++ b/ip/altera/ram0.vhd @@ -0,0 +1,165 @@ +-- megafunction wizard: %RAM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: ram0.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY ram0 IS + PORT + ( + address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END ram0; + + +ARCHITECTURE SYN OF ram0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + byte_size => 8, + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "datasets/ram_init.hex", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2048, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => 11, + width_a => 32, + width_byteena_a => 4 + ) + PORT MAP ( + address_a => address, + byteena_a => byteena, + clock0 => clock, + data_a => data, + wren_a => wren, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrData NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "../datasets/ram_init.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegData NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +-- Retrieval info: PRIVATE: WidthData NUMERIC "32" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "../datasets/ram_init.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" +-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +-- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +-- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram0.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram0.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/ip/altera/spiFifo.qip b/ip/altera/spiFifo.qip new file mode 100644 index 0000000..bdf61cb --- /dev/null +++ b/ip/altera/spiFifo.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "15.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "spiFifo.vhd"] diff --git a/ip/altera/spiFifo.vhd b/ip/altera/spiFifo.vhd new file mode 100644 index 0000000..4354798 --- /dev/null +++ b/ip/altera/spiFifo.vhd @@ -0,0 +1,205 @@ +-- megafunction wizard: %FIFO% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo + +-- ============================================================ +-- File Name: spiFifo.vhd +-- Megafunction Name(s): +-- dcfifo +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spiFifo IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrfull : OUT STD_LOGIC + ); +END spiFifo; + + +ARCHITECTURE SYN OF spififo IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + + + + COMPONENT dcfifo + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + read_aclr_synch : STRING; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrfull : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + rdempty <= sub_wire1; + wrfull <= sub_wire2; + + dcfifo_component : dcfifo + GENERIC MAP ( + intended_device_family => "Cyclone V", + lpm_numwords => 8, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 8, + lpm_widthu => 3, + overflow_checking => "ON", + rdsync_delaypipe => 4, + read_aclr_synch => "OFF", + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 4 + ) + PORT MAP ( + aclr => aclr, + data => data, + rdclk => rdclk, + rdreq => rdreq, + wrclk => wrclk, + wrreq => wrreq, + q => sub_wire0, + rdempty => sub_wire1, + wrfull => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "8" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "1" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/ip/intercon/rtl/clock_crossing.vhd b/ip/intercon/rtl/clock_crossing.vhd new file mode 100644 index 0000000..9e8430d --- /dev/null +++ b/ip/intercon/rtl/clock_crossing.vhd @@ -0,0 +1,141 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; +use work.fifo_package.all; + +entity clock_crossing is + generic( + sync_depth : natural := 2; + log2fifo : natural := 4); + port( + -- Common wishbone signals + rst : in std_logic; + -- Slave control port + slave_clk : in std_logic; + slave_i : in wishbone_slave_in; + slave_o : out wishbone_slave_out; + -- Master reader port + master_clk : in std_logic; + master_i : in wishbone_master_in; + master_o : out wishbone_master_out); +end clock_crossing; + +architecture rtl of clock_crossing is + constant mWE_start : natural := 0; + constant mWE_end : natural := mWE_start; + constant mADR_start : natural := mWE_end + 1; + constant mADR_end : natural := mADR_start + wishbone_address_width - 1; + constant mDAT_start : natural := mADR_end + 1; + constant mDAT_end : natural := mDAT_start + wishbone_data_width - 1; + constant mSEL_start : natural := mDAT_end + 1; + constant mSEL_end : natural := mSEL_start + (wishbone_data_width/8) - 1; + constant mlen : natural := mSEL_end + 1; + + signal msend, mrecv : wishbone_master_out; + signal msend_vect, mrecv_vect : std_logic_vector(mlen-1 downto 0); + signal mw_rdy, mw_en, mr_rdy, mr_en : std_logic; + + constant sACK_start : natural := 0; + constant sACK_end : natural := sACK_start; + constant sRTY_start : natural := sACK_end + 1; + constant sRTY_end : natural := sRTY_start; + constant sERR_start : natural := sRTY_end + 1; + constant sERR_end : natural := sERR_start; + constant sDAT_start : natural := sERR_end + 1; + constant sDAT_end : natural := sDAT_start + wishbone_data_width - 1; + constant slen : natural := sDAT_end + 1; + + signal ssend, srecv : wishbone_slave_out; + signal ssend_vect, srecv_vect : std_logic_vector(slen-1 downto 0); + signal sw_rdy, sw_en, sr_rdy, sr_en, sa_rdy, sa_en : std_logic; + + signal master_o_STB : std_logic; + signal slave_o_PUSH : std_logic; +begin + mfifo : fifo + generic map(addr_width => log2fifo, data_width => mlen, sync_depth => sync_depth, gray_code => true) + port map(w_clk => slave_clk, w_rdy => mw_rdy, w_en => mw_en, w_data => msend_vect, + r_clk => master_clk, r_rdy => mr_rdy, r_en => mr_en, r_data => mrecv_vect, + a_clk => '0', a_rdy => open, a_en => '0', rst => rst); + + msend_vect(mWE_start) <= msend.WE; + msend_vect(mADR_end downto mADR_start) <= msend.ADR; + msend_vect(mDAT_end downto mDAT_start) <= msend.DAT; + msend_vect(mSEL_end downto mSEL_start) <= msend.SEL; + + mrecv.WE <= mrecv_vect(mWE_start); + mrecv.ADR <= mrecv_vect(mADR_end downto mADR_start); + mrecv.DAT <= mrecv_vect(mDAT_end downto mDAT_start); + mrecv.SEL <= mrecv_vect(mSEL_end downto mSEL_start); + + sfifo : fifo + generic map(addr_width => log2fifo, data_width => slen, sync_depth => sync_depth, gray_code => true) + port map(w_clk => master_clk, w_rdy => open, w_en => sw_en, w_data => ssend_vect, + r_clk => slave_clk, r_rdy => sr_rdy, r_en => sr_en, r_data => srecv_vect, + a_clk => slave_clk, a_rdy => sa_rdy, a_en => sa_en, rst => rst); + + ssend_vect(sACK_start) <= ssend.ACK; + ssend_vect(sRTY_start) <= ssend.RTY; + ssend_vect(sERR_start) <= ssend.ERR; + ssend_vect(sDAT_end downto sDAT_start) <= ssend.DAT; + + srecv.ACK <= srecv_vect(sACK_start); + srecv.RTY <= srecv_vect(sRTY_start); + srecv.ERR <= srecv_vect(sERR_start); + srecv.DAT <= srecv_vect(sDAT_end downto sDAT_start); + + -- Slave clock domain: slave -> mFIFO + mw_en <= mw_rdy and sa_rdy and slave_i.CYC and slave_i.STB; + sa_en <= mw_rdy and sa_rdy and slave_i.CYC and slave_i.STB; + slave_o.STALL <= not mw_rdy or not sa_rdy; + msend.ADR <= slave_i.ADR; + msend.WE <= slave_i.WE; + msend.SEL <= slave_i.SEL; + msend.DAT <= slave_i.DAT; + + -- Master clock domain: mFIFO -> master + mr_en <= mr_rdy and (not master_o_STB or not master_i.STALL); + master_o.CYC <= '1'; + master_o.STB <= master_o_STB; + master_o.ADR <= mrecv.ADR; + master_o.WE <= mrecv.WE; + master_o.SEL <= mrecv.SEL; + master_o.DAT <= mrecv.DAT; + + drive_master_port : process(master_clk) + begin + if rising_edge(master_clk) then + if rst = '1' then + master_o_STB <= '0'; + else + master_o_STB <= mr_en or (master_o_STB and master_i.STALL); + end if; + end if; + end process; + + -- Master clock domain: master -> sFIFO + sw_en <= master_i.ACK or master_i.ERR or master_i.RTY; + ssend.ACK <= master_i.ACK; + ssend.ERR <= master_i.ERR; + ssend.RTY <= master_i.RTY; + ssend.DAT <= master_i.DAT; + + -- Slave clock domain: sFIFO -> slave + sr_en <= sr_rdy; + slave_o.DAT <= srecv.DAT; + slave_o.ACK <= srecv.ACK and slave_o_PUSH; + slave_o.RTY <= srecv.RTY and slave_o_PUSH; + slave_o.ERR <= srecv.ERR and slave_o_PUSH; + + drive_slave_port : process(slave_clk) + begin + if rising_edge(slave_clk) then + if rst = '1' then + slave_o_PUSH <= '0'; + else + slave_o_PUSH <= sr_en; + end if; + end if; + end process; +end rtl; diff --git a/ip/intercon/rtl/clock_crossing_package.vhd b/ip/intercon/rtl/clock_crossing_package.vhd new file mode 100644 index 0000000..7036487 --- /dev/null +++ b/ip/intercon/rtl/clock_crossing_package.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +package clock_crossing_package is + component clock_crossing is + generic( + sync_depth : natural := 2; + log2fifo : natural := 4); + port( + -- Common wishbone signals + rst : in std_logic; + -- Slave control port + slave_clk : in std_logic; + slave_i : in wishbone_slave_in; + slave_o : out wishbone_slave_out; + -- Master reader port + master_clk : in std_logic; + master_i : in wishbone_master_in; + master_o : out wishbone_master_out); + end component; +end package; diff --git a/ip/intercon/rtl/crossbar.vhd b/ip/intercon/rtl/crossbar.vhd new file mode 100644 index 0000000..06080a5 --- /dev/null +++ b/ip/intercon/rtl/crossbar.vhd @@ -0,0 +1,242 @@ +-- An MxS Wishbone crossbar switch. +-- +-- All masters, slaves, and the crossbar itself must share the same WB clock. +-- All participants must support the same data bus width. +-- +-- If a master raises STB_O with an address not mapped by the crossbar, +-- ERR_I will be raised. If the crossbar has overlapping address ranges, +-- the lowest numbered slave is selected. If two masters address the same +-- slave simultaneously, the lowest numbered master is granted access. +-- +-- The implementation of this crossbar locks a master to a slave so long as +-- CYC_O is held high. If the master tries to address outside the slave's +-- address range, ERR_I will be raised. +-- +-- WARN: !!! NO LICENSE SPECIFIED !!! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +entity crossbar is + generic( + masters : integer := 2; + slaves : integer := 1; + async : boolean := false + ); + port( + clk : in std_logic; + rst : in std_logic; + -- Master connections (INTERCON is a slave) + slave_i : in wishbone_slave_in_vector(masters - 1 downto 0); + slave_o : out wishbone_slave_out_vector(masters - 1 downto 0); + -- Slave connections (INTERCON is a master) + master_i : in wishbone_master_in_vector(slaves - 1 downto 0); + master_o : out wishbone_master_out_vector(slaves - 1 downto 0); + -- Address of the slaves connected + address : in wishbone_address_vector(slaves - 1 downto 0); + mask : in wishbone_address_vector(slaves - 1 downto 0) + ); +end crossbar; + +architecture rtl of crossbar is + type matrix is array (masters - 1 downto 0, slaves downto 0) of std_logic; + type column is array (masters - 1 downto 0) of std_logic; + type row is array (slaves downto 0) of std_logic; + + -- synchronous signals: + signal previous : matrix; -- Previously connected pairs 1 - + -- (a)synchronous signals (depending on generic): + signal granted : matrix; -- The connections to form this cycle 1 selected previous busy + signal issue : column; -- Did last cycle issue a request + + procedure main_logic( + signal granted : out matrix; + signal issue : out column; + signal slave_i : in wishbone_slave_in_vector(masters - 1 downto 0); + signal previous : in matrix) is + variable acc, tmp : std_logic; + variable request : matrix; -- Which slaves do the masters address log(S) - + variable selected : matrix; -- Which master wins arbitration log(M) request + variable sbusy : row; -- Does the slave's previous connection persist? + variable mbusy : column; -- Does the master's previous connection persist? + begin + -- A slave is busy iff it services an in-progress cycle + for slave in slaves - 1 downto 0 loop + acc := '0'; + for master in masters - 1 downto 0 loop + acc := acc or (previous(master, slave) and slave_i(master).CYC); + end loop; + sbusy(slave) := acc; + end loop; + sbusy(slaves) := '0'; -- Special case because the 'error device' supports multiple masters + + -- A master is busy iff it services an in-progress cycle + for master in masters - 1 downto 0 loop + acc := '0'; + for slave in slaves downto 0 loop + acc := acc or previous(master, slave); + end loop; + mbusy(master) := acc and slave_i(master).CYC; + end loop; + + -- Decode the request address to see if master wants access + for master in masters - 1 downto 0 loop + acc := '0'; + for slave in slaves - 1 downto 0 loop + if (slave_i(master).ADR and mask(slave)) = address(slave) then + tmp := '1'; + else + tmp := '0'; + end if; + acc := acc or tmp; + request(master, slave) := slave_i(master).CYC and slave_i(master).STB and tmp; + end loop; + -- If no slaves match request, bind to 'error device' + request(master, slaves) := slave_i(master).CYC and slave_i(master).STB and not acc; + end loop; + + -- Arbitrate among the requesting masters + -- Policy: lowest numbered master first + for slave in slaves - 1 downto 0 loop + acc := '0'; + -- It is possible to break the chain of LUTs here using a sort of kogge-stone network + -- This probably only makes sense if you have more than 32 masters + for master in 0 to masters - 1 loop + selected(master, slave) := request(master, slave) and not acc; + acc := acc or request(master, slave); + end loop; + end loop; + + -- Multiple masters can be granted access to the 'error device' + for master in masters - 1 downto 0 loop + selected(master, slaves) := request(master, slaves); + end loop; + + -- Determine the master granted access + -- Policy: if cycle still in progress, preserve the previous choice + for slave in slaves downto 0 loop + for master in masters - 1 downto 0 loop + if sbusy(slave) = '1' or mbusy(master) = '1' then + granted(master, slave) <= previous(master, slave); + else + granted(master, slave) <= selected(master, slave); + end if; + end loop; + end loop; + + -- Record strobe status for virtual error device + for master in masters - 1 downto 0 loop + issue(master) <= slave_i(master).CYC and slave_i(master).STB; + end loop; + end main_logic; + + -- Select the master pins the slave will receive + procedure slave_logic(signal o : out wishbone_master_out; + signal slave_i : in wishbone_slave_in_vector(masters - 1 downto 0); + signal granted : in matrix; + slave : integer) is + variable acc : wishbone_master_out; + variable granted_address : wishbone_address; + variable granted_select : wishbone_byte_select; + variable granted_data : wishbone_data; + begin + acc := ( + CYC => '0', + STB => '0', + ADR => (others => '0'), + SEL => (others => '0'), + WE => '0', + DAT => (others => '0')); + + for master in masters - 1 downto 0 loop + granted_address := (others => granted(master, slave)); + granted_select := (others => granted(master, slave)); + granted_data := (others => granted(master, slave)); + acc := ( + CYC => acc.CYC or (slave_i(master).CYC and granted(master, slave)), + STB => acc.STB or (slave_i(master).STB and granted(master, slave)), + ADR => acc.ADR or (slave_i(master).ADR and granted_address), + SEL => acc.SEL or (slave_i(master).SEL and granted_select), + WE => acc.WE or (slave_i(master).WE and granted(master, slave)), + DAT => acc.DAT or (slave_i(master).DAT and granted_data)); + end loop; + -- acc.ADR := std_logic_vector(unsigned(acc.ADR) - unsigned(address(slave))); -- Address translation + o <= acc; + end slave_logic; + + -- Select the slave pins the master will receive + procedure master_logic(signal o : out wishbone_slave_out; + signal master_i : in wishbone_master_in_vector(slaves - 1 downto 0); + signal issue : in column; + signal previous : in matrix; + signal granted : in matrix; + master : integer) is + variable acc : wishbone_slave_out; + variable granted_data : wishbone_data; + begin + acc := ( + ACK => '0', + ERR => issue(master) and previous(master, slaves), -- Error device connected and strobed? + RTY => '0', + STALL => granted(master, slaves), + DAT => (others => '0')); + + -- We use inverted logic on STALL so that if no slave granted => stall + for slave in slaves - 1 downto 0 loop + granted_data := (others => granted(master, slave)); + acc := ( + ACK => acc.ACK or (master_i(slave).ACK and granted(master, slave)), + ERR => acc.ERR or (master_i(slave).ERR and granted(master, slave)), + RTY => acc.RTY or (master_i(slave).RTY and granted(master, slave)), + STALL => acc.STALL or (not master_i(slave).STALL and granted(master, slave)), + DAT => acc.DAT or (master_i(slave).DAT and granted_data)); + end loop; + acc.STALL := not acc.STALL; + + o <= acc; + end master_logic; +begin + -- If async determine granted devices + granted_matrix : if async generate + main_logic(granted, issue, slave_i, previous); + end generate; + + granted_driver : if not async generate + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + granted <= (others => (others => '0')); + issue <= (others => '0'); + else + main_logic(granted, issue, slave_i, previous); + end if; + end if; + end process; + end generate; + + -- Make the slave connections + slave_matrix : for slave in slaves - 1 downto 0 generate + slave_logic(master_o(slave), slave_i, granted, slave); + end generate; + + -- Make the master connections + master_matrix : for master in masters - 1 downto 0 generate + master_logic(slave_o(master), master_i, issue, previous, granted, master); + end generate; + + -- Store the current grant to the previous registers + main : process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + previous <= (others => (others => '0')); + else + previous <= granted; + end if; + end if; + end process main; + +end rtl; diff --git a/ip/intercon/rtl/crossbar_package.vhd b/ip/intercon/rtl/crossbar_package.vhd new file mode 100644 index 0000000..3f95cad --- /dev/null +++ b/ip/intercon/rtl/crossbar_package.vhd @@ -0,0 +1,41 @@ +-- An MxS Wishbone crossbar switch. +-- +-- All masters, slaves, and the crossbar itself must share the same WB clock. +-- All participants must support the same data bus width. +-- +-- If a master raises STB_O with an address not mapped by the crossbar, +-- ERR_I will be raised. If the crossbar has overlapping address ranges, +-- the lowest numbered slave is selected. If two masters address the same +-- slave simultaneously, the lowest numbered master is granted access. +-- +-- The implementation of this crossbar locks a master to a slave so long as +-- CYC_O is held high. If the master tries to address outside the slave's +-- address range, ERR_I will be raised. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +package crossbar_package is + component crossbar is + generic( + masters : integer := 2; + slaves : integer := 1; + async : boolean := false + ); + port( + clk : in std_logic; + rst : in std_logic; + -- Master connections (INTERCON is a slave) + slave_i : in wishbone_slave_in_vector(masters-1 downto 0); + slave_o : out wishbone_slave_out_vector(masters-1 downto 0); + -- Slave connections (INTERCON is a master) + master_i : in wishbone_master_in_vector(slaves-1 downto 0); + master_o : out wishbone_master_out_vector(slaves-1 downto 0); + -- Address of the slaves connected + address : in wishbone_address_vector(slaves-1 downto 0); + mask : in wishbone_address_vector(slaves-1 downto 0) + ); + end component; +end; diff --git a/ip/intercon/rtl/crossbar_v3.vhd b/ip/intercon/rtl/crossbar_v3.vhd new file mode 100644 index 0000000..785e7fc --- /dev/null +++ b/ip/intercon/rtl/crossbar_v3.vhd @@ -0,0 +1,253 @@ +-- An MxS Wishbone crossbar switch. +-- +-- All masters, slaves, and the crossbar itself must share the same WB clock. +-- All participants must support the same data bus width. +-- +-- If a master raises STB_O with an address not mapped by the crossbar, +-- ERR_I will be raised. If the crossbar has overlapping address ranges, +-- the lowest numbered slave is selected. If two masters address the same +-- slave simultaneously, the lowest numbered master is granted access. +-- +-- The implementation of this crossbar locks a master to a slave so long as +-- CYC_O is held high. If the master tries to address outside the slave's +-- address range, ERR_I will be raised. +-- +-- Note: The LOCK signal is ignored, but the crossbar switch will not reassign +-- the current bus master until it relinquishes CYC anyways. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +entity crossbar is + generic( + masters : integer := 2; + slaves : integer := 1; + async : boolean := false + ); + port( + clk : in std_logic; + rst : in std_logic; + -- Master connections (INTERCON is a slave) + slave_i : in wishbone_v3_slave_in_vector(masters - 1 downto 0); + slave_o : out wishbone_v3_slave_out_vector(masters - 1 downto 0); + -- Slave connections (INTERCON is a master) + master_i : in wishbone_v3_master_in_vector(slaves - 1 downto 0); + master_o : out wishbone_v3_master_out_vector(slaves - 1 downto 0); + -- Address of the slaves connected + address : in wishbone_address_vector(slaves - 1 downto 0); + mask : in wishbone_address_vector(slaves - 1 downto 0) + ); +end crossbar; + +architecture rtl of crossbar is + type matrix is array (masters - 1 downto 0, slaves downto 0) of std_logic; + type column is array (masters - 1 downto 0) of std_logic; + type row is array (slaves downto 0) of std_logic; + + -- synchronous signals: + signal previous : matrix; -- Previously connected pairs 1 - + -- (a)synchronous signals (depending on generic): + signal granted : matrix; -- The connections to form this cycle 1 selected previous busy + signal issue : column; -- Did last cycle issue a request + + procedure main_logic( + signal granted : out matrix; + signal issue : out column; + signal slave_i : in wishbone_v3_slave_in_vector(masters - 1 downto 0); + signal previous : in matrix) is + variable acc, tmp : std_logic; + variable request : matrix; -- Which slaves do the masters address log(S) - + variable selected : matrix; -- Which master wins arbitration log(M) request + variable sbusy : row; -- Does the slave's previous connection persist? + variable mbusy : column; -- Does the master's previous connection persist? + begin + -- A slave is busy if it services an in-progress cycle + for slave in slaves - 1 downto 0 loop + acc := '0'; + for master in masters - 1 downto 0 loop + acc := acc or (previous(master, slave) and slave_i(master).CYC); + end loop; + sbusy(slave) := acc; + end loop; + sbusy(slaves) := '0'; -- Special case because the 'error device' supports multiple masters + + -- A master is busy iff it services an in-progress cycle + for master in masters - 1 downto 0 loop + acc := '0'; + for slave in slaves downto 0 loop + acc := acc or previous(master, slave); + end loop; + mbusy(master) := acc and slave_i(master).CYC; + end loop; + + -- Decode the request address to see if master wants access + for master in masters - 1 downto 0 loop + acc := '0'; + for slave in slaves - 1 downto 0 loop + if (slave_i(master).ADR and mask(slave)) = address(slave) then + tmp := '1'; + else + tmp := '0'; + end if; + acc := acc or tmp; + request(master, slave) := slave_i(master).CYC and slave_i(master).STB and tmp; + end loop; + -- If no slaves match request, bind to 'error device' + request(master, slaves) := slave_i(master).CYC and slave_i(master).STB and not acc; + end loop; + + -- Arbitrate among the requesting masters + -- Policy: lowest numbered master first + for slave in slaves - 1 downto 0 loop + acc := '0'; + -- It is possible to break the chain of LUTs here using a sort of kogge-stone network + -- This probably only makes sense if you have more than 32 masters + for master in 0 to masters - 1 loop + selected(master, slave) := request(master, slave) and not acc; + acc := acc or request(master, slave); + end loop; + end loop; + + -- Multiple masters can be granted access to the 'error device' + for master in masters - 1 downto 0 loop + selected(master, slaves) := request(master, slaves); + end loop; + + -- Determine the master granted access + -- Policy: if cycle still in progress, preserve the previous choice + for slave in slaves downto 0 loop + for master in masters - 1 downto 0 loop + if sbusy(slave) = '1' or mbusy(master) = '1' then + granted(master, slave) <= previous(master, slave); + else + granted(master, slave) <= selected(master, slave); + end if; + end loop; + end loop; + + -- Record strobe status for virtual error device + for master in masters - 1 downto 0 loop + issue(master) <= slave_i(master).CYC and slave_i(master).STB; + end loop; + end main_logic; + + -- Select the master pins the slave will receive + procedure slave_logic(signal o : out wishbone_v3_master_out; + signal slave_i : in wishbone_v3_slave_in_vector(masters - 1 downto 0); + signal granted : in matrix; + slave : integer) is + variable acc : wishbone_v3_master_out; + variable granted_address : wishbone_address; + variable granted_bte : wishbone_burst_type; + variable granted_cti : wishbone_cycle_type; + variable granted_select : wishbone_byte_select; + variable granted_data : wishbone_data; + begin + acc := ( + CYC => '0', + STB => '0', + ADR => (others => '0'), + BTE => (others => '0'), + CTI => (others => '0'), + LOCK => '0', + SEL => (others => '0'), + WE => '0', + DAT => (others => '0')); + + for master in masters - 1 downto 0 loop + granted_address := (others => granted(master, slave)); + granted_bte := (others => granted(master, slave)); + granted_cti := (others => granted(master, slave)); + granted_select := (others => granted(master, slave)); + granted_data := (others => granted(master, slave)); + acc := ( + CYC => acc.CYC or (slave_i(master).CYC and granted(master, slave)), + STB => acc.STB or (slave_i(master).STB and granted(master, slave)), + ADR => acc.ADR or (slave_i(master).ADR and granted_address), + BTE => acc.BTE or (slave_i(master).BTE and granted_bte), + CTI => acc.CTI or (slave_i(master).CTI and granted_cti), + SEL => acc.SEL or (slave_i(master).SEL and granted_select), + WE => acc.WE or (slave_i(master).WE and granted(master, slave)), + LOCK => acc.LOCK or (slave_i(master).LOCK and granted(master, slave)), + DAT => acc.DAT or (slave_i(master).DAT and granted_data)); + end loop; + -- acc.ADR := std_logic_vector(unsigned(acc.ADR) - unsigned(address(slave))); -- Address translation + o <= acc; + end slave_logic; + + -- Select the slave pins the master will receive + procedure master_logic(signal o : out wishbone_v3_slave_out; + signal master_i : in wishbone_v3_master_in_vector(slaves - 1 downto 0); + signal issue : in column; + signal previous : in matrix; + signal granted : in matrix; + master : integer) is + variable acc : wishbone_v3_slave_out; + variable granted_data : wishbone_data; + begin + acc := ( + ACK => '0', + ERR => issue(master) and previous(master, slaves), -- Error device connected and strobed? + RTY => '0', + --STALL => granted(master, slaves), + DAT => (others => '0')); + + -- We use inverted logic on STALL so that if no slave granted => stall + for slave in slaves - 1 downto 0 loop + granted_data := (others => granted(master, slave)); + acc := ( + ACK => acc.ACK or (master_i(slave).ACK and granted(master, slave)), + ERR => acc.ERR or (master_i(slave).ERR and granted(master, slave)), + RTY => acc.RTY or (master_i(slave).RTY and granted(master, slave)), + --STALL => acc.STALL or (not master_i(slave).STALL and granted(master, slave)), + DAT => acc.DAT or (master_i(slave).DAT and granted_data)); + end loop; + --acc.STALL := not acc.STALL; + + o <= acc; + end master_logic; +begin + -- If async determine granted devices + granted_matrix : if async generate + main_logic(granted, issue, slave_i, previous); + end generate; + + granted_driver : if not async generate + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + granted <= (others => (others => '0')); + issue <= (others => '0'); + else + main_logic(granted, issue, slave_i, previous); + end if; + end if; + end process; + end generate; + + -- Make the slave connections + slave_matrix : for slave in slaves - 1 downto 0 generate + slave_logic(master_o(slave), slave_i, granted, slave); + end generate; + + -- Make the master connections + master_matrix : for master in masters - 1 downto 0 generate + master_logic(slave_o(master), master_i, issue, previous, granted, master); + end generate; + + -- Store the current grant to the previous registers + main : process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + previous <= (others => (others => '0')); + else + previous <= granted; + end if; + end if; + end process main; + +end rtl; diff --git a/ip/intercon/rtl/dma.vhd b/ip/intercon/rtl/dma.vhd new file mode 100644 index 0000000..c8a5243 --- /dev/null +++ b/ip/intercon/rtl/dma.vhd @@ -0,0 +1,240 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +-- Assumption: wishbone_data_width >= wishbone_address_Width +entity dma is + generic( + -- Value 0 cannot stream + -- Value 1 only slaves with async ACK can stream + -- Value 2 only slaves with combined latency = 2 can stream + -- Value 3 only slaves with combined latency = 6 can stream + -- Value 4 only slaves with combined latency = 14 can stream + -- .... + logRingLen : integer := 4 + ); + port( + -- Common wishbone signals + clk : in std_logic; + rst : in std_logic; + -- Slave control port + slave_i : in wishbone_slave_in; + slave_o : out wishbone_slave_out; + -- Master reader port + r_master_i : in wishbone_master_in; + r_master_o : out wishbone_master_out; + -- Master writer port + w_master_i : in wishbone_master_in; + w_master_o : out wishbone_master_out; + -- Pulsed high completion signal + interrupt : out std_logic + ); +end dma; + +architecture rtl of dma is + constant ringLen : integer := 2**logRingLen; + type ring_t is array (ringLen-1 downto 0) of wishbone_data; + + -- Ring buffer for shipping data from read master to write master + signal ring : ring_t; + + -- State registers (pointer into the ring) + -- Invariant: read_issue_offset >= read_result_offset >= write_issue_offset >= write_result_offset + -- read_issue_offset - write_result_offset <= ringLen (*NOT* strict '<') + signal read_issue_offset : unsigned(logRingLen downto 0); + signal read_result_offset : unsigned(logRingLen downto 0); + signal write_issue_offset : unsigned(logRingLen downto 0); + signal write_result_offset : unsigned(logRingLen downto 0); + + -- DMA control registers + signal read_issue_address : wishbone_address; + signal write_issue_address : wishbone_address; + signal read_stride : wishbone_address; + signal write_stride : wishbone_address; + signal transfer_count : wishbone_address; + -- result status: fail/ok ? + + -- Registered wishbone control signals + signal r_master_o_CYC : std_logic; + signal w_master_o_CYC : std_logic; + signal r_master_o_STB : std_logic; + signal w_master_o_STB : std_logic; + signal slave_o_ACK : std_logic; + signal slave_o_DAT : wishbone_data; + + function active_high(x : boolean) + return std_logic is + begin + if (x) then + return '1'; + else + return '0'; + end if; + end active_high; + + function index(x : unsigned(logRingLen downto 0)) + return integer is + begin + if logRingLen > 0 then + return to_integer(x(logRingLen-1 downto 0)); + else + return 0; + end if; + end index; + + procedure update(signal o : out wishbone_address) is + begin + for i in (wishbone_data_width/8)-1 downto 0 loop + if slave_i.SEL(i) = '1' then + o(i*8+7 downto i*8) <= slave_i.DAT(i*8+7 downto i*8); + end if; + end loop; + end update; + +begin + -- Hard-wired slave pins + slave_o.ACK <= slave_o_ACK; + slave_o.ERR <= '0'; + slave_o.RTY <= '0'; + slave_o.STALL <= '0'; + slave_o.DAT <= slave_o_DAT; + + -- Hard-wired master pins + r_master_o.CYC <= r_master_o_CYC; + w_master_o.CYC <= w_master_o_CYC; + r_master_o.STB <= r_master_o_STB; + w_master_o.STB <= w_master_o_STB; + r_master_o.ADR <= read_issue_address; + w_master_o.ADR <= write_issue_address; + r_master_o.SEL <= (others => '1'); + w_master_o.SEL <= (others => '1'); + r_master_o.WE <= '0'; + w_master_o.WE <= '1'; + r_master_o.DAT <= (others => '0'); + w_master_o.DAT <= ring(index(write_issue_offset)); + + main : process(clk) + variable read_issue_progress : boolean; + variable read_result_progress : boolean; + variable write_issue_progress : boolean; + variable write_result_progress : boolean; + + variable new_read_issue_offset : unsigned(logRingLen downto 0); + variable new_read_result_offset : unsigned(logRingLen downto 0); + variable new_write_issue_offset : unsigned(logRingLen downto 0); + variable new_write_result_offset : unsigned(logRingLen downto 0); + variable new_transfer_count : wishbone_address; + + variable ring_boundary : boolean; + variable ring_high : boolean; + variable ring_full : boolean; + variable ring_empty : boolean; + variable done_transfer : boolean; + begin + if (rising_edge(clk)) then + if (rst = '1') then + read_issue_offset <= (others => '0'); + read_result_offset <= (others => '0'); + write_issue_offset <= (others => '0'); + write_result_offset <= (others => '0'); + + read_issue_address <= (others => '0'); + write_issue_address <= (others => '0'); + read_stride <= (others => '0'); + write_stride <= (others => '0'); + transfer_count <= (others => '0'); + + r_master_o_CYC <= '0'; + w_master_o_CYC <= '0'; + r_master_o_STB <= '0'; + w_master_o_STB <= '0'; + slave_o_ACK <= '0'; + slave_o_DAT <= (others => '0'); + interrupt <= '0'; + else + -- Output any read the user requests + case to_integer(unsigned(slave_i.ADR(4 downto 2))) is + when 0 => slave_o_DAT <= read_issue_address; + when 1 => slave_o_DAT <= write_issue_address; + when 2 => slave_o_DAT <= read_stride; + when 3 => slave_o_DAT <= write_stride; + when 4 => slave_o_DAT <= transfer_count; + when others => slave_o_DAT <= (others => '0'); + end case; + + -- Detect bus progress + read_issue_progress := r_master_o_STB = '1' and r_master_i.STALL = '0'; + write_issue_progress := w_master_o_STB = '1' and w_master_i.STALL = '0'; + read_result_progress := r_master_o_CYC = '1' and (r_master_i.ACK = '1' or r_master_i.ERR = '1' or r_master_i.RTY = '1'); + write_result_progress := w_master_o_CYC = '1' and (w_master_i.ACK = '1' or w_master_i.ERR = '1' or w_master_i.RTY = '1'); + + -- Advance read pointers + if read_issue_progress then + read_issue_address <= std_logic_vector(unsigned(read_issue_address) + unsigned(read_stride)); + new_read_issue_offset := read_issue_offset + 1; + new_transfer_count := std_logic_vector(unsigned(transfer_count) - 1); + else + new_read_issue_offset := read_issue_offset; + new_transfer_count := transfer_count; + end if; + if read_result_progress then + ring(index(read_result_offset)) <= r_master_i.DAT; + new_read_result_offset := read_result_offset + 1; + else + new_read_result_offset := read_result_offset; + end if; + + -- Advance write pointers + if write_issue_progress then + write_issue_address <= std_logic_vector(unsigned(write_issue_address) + unsigned(write_stride)); + new_write_issue_offset := write_issue_offset + 1; + else + new_write_issue_offset := write_issue_offset; + end if; + if write_result_progress then + new_write_result_offset := write_result_offset + 1; + else + new_write_result_offset := write_result_offset; + end if; + + ring_boundary := index(new_read_issue_offset) = index(new_write_result_offset); + ring_high := new_read_issue_offset(logRingLen) /= new_write_result_offset(logRingLen); + ring_full := ring_boundary and ring_high; + ring_empty := ring_boundary and not ring_high; + + -- Shorten the critical path by comparing to the undecremented value + --done_transfer := unsigned(new_transfer_count) = 0; + done_transfer := unsigned(transfer_count(wishbone_address_width-1 downto 1)) = 0 + and (read_issue_progress or transfer_count(0) = '0'); + + r_master_o_STB <= active_high (not ring_full and not done_transfer); + r_master_o_CYC <= active_high((not ring_full and not done_transfer) or + (new_read_result_offset /= new_read_issue_offset)); + w_master_o_STB <= active_high (new_write_issue_offset /= new_read_result_offset); + w_master_o_CYC <= active_high (new_write_result_offset /= new_read_result_offset); + interrupt <= active_high (write_result_progress and done_transfer and ring_empty); + + transfer_count <= new_transfer_count; + read_issue_offset <= new_read_issue_offset; + read_result_offset <= new_read_result_offset; + write_issue_offset <= new_write_issue_offset; + write_result_offset <= new_write_result_offset; + + -- Control logic + if (slave_i.CYC = '1' and slave_i.STB = '1' and slave_i.WE = '1') then + case to_integer(unsigned(slave_i.ADR(4 downto 2))) is + when 0 => update(read_issue_address); + when 1 => update(write_issue_address); + when 2 => update(read_stride); + when 3 => update(write_stride); + when 4 => update(transfer_count); + when others => null; + end case; + end if; + + slave_o_ACK <= slave_i.CYC and slave_i.STB; + end if; + end if; + end process; +end rtl; diff --git a/ip/intercon/rtl/dma_package.vhd b/ip/intercon/rtl/dma_package.vhd new file mode 100644 index 0000000..48ee6e3 --- /dev/null +++ b/ip/intercon/rtl/dma_package.vhd @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +package dma_package is + component dma is + generic( + -- Value 0 cannot stream + -- Value 1 only slaves with async ACK can stream + -- Value 2 only slaves with combined latency <= 2 can stream + -- Value 3 only slaves with combined latency <= 6 can stream + -- Value 4 only slaves with combined latency <= 14 can stream + -- .... + logRingLen : integer := 4 + ); + port( + -- Common wishbone signals + clk : in std_logic; + rst : in std_logic; + -- Slave control port + slave_i : in wishbone_slave_in; + slave_o : out wishbone_slave_out; + -- Master reader port + r_master_i : in wishbone_master_in; + r_master_o : out wishbone_master_out; + -- Master writer port + w_master_i : in wishbone_master_in; + w_master_o : out wishbone_master_out; + -- Pulsed high completion signal + interrupt : out std_logic + ); + end component; +end dma_package; diff --git a/ip/intercon/rtl/example.vhd b/ip/intercon/rtl/example.vhd new file mode 100644 index 0000000..65b1d36 --- /dev/null +++ b/ip/intercon/rtl/example.vhd @@ -0,0 +1,109 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.wishbone_package.all; +use work.crossbar_package.all; +use work.ebr_package.all; +use work.lm32_package.all; +use work.simple_pll_package.all; + +entity example is + port( + clk_base : in std_logic; + rstn_base : in std_logic + ); +end example; + +architecture rtl of example is + constant masters : natural := 2; + constant slaves : natural := 2; + + signal clk : std_logic; + signal rst : std_logic; + signal locked : std_logic; + + signal intercon_slave_i : wishbone_slave_in_vector(masters-1 downto 0); + signal intercon_slave_o : wishbone_slave_out_vector(masters-1 downto 0); + signal intercon_master_i : wishbone_master_in_vector(slaves-1 downto 0); + signal intercon_master_o : wishbone_master_out_vector(slaves-1 downto 0); +begin + rst <= not rstn_base or not locked; + + clk_pll : simple_pll + generic map + ( + c0_mul => 2, + c0_div => 1, + c1_mul => 4, + c1_div => 1, + in_freq => 50000 + ) + port map + ( + inclk0 => clk_base, + c0 => clk, + c1 => open, + locked => locked + ); + + ebr_memory : ebr + generic map + ( + size => 4096 + ) + port map + ( + clk => clk, + rst => rst, + slave_i => intercon_master_o(0), + slave_o => intercon_master_i(0) + ); + + monitor_memory : ebr + generic map + ( + size => 2048 + ) + port map + ( + clk => clk, + rst => rst, + slave_i => intercon_master_o(1), + slave_o => intercon_master_i(1) + ); + + cpu0 : lm32_vhdl + port map + ( + clk => clk, + rst => rst, + interrupt => x"00000000", + data_o => intercon_slave_i(0), + data_i => intercon_slave_o(0), + inst_o => intercon_slave_i(1), + inst_i => intercon_slave_o(1) + ); + + intercon : crossbar + generic map + ( + masters => masters, + slaves => slaves, + -- Device 0 has range 00000000-00000fff + -- Device 1 has range 10000000-100007ff + address => (0 => x"00000000", + 1 => x"10000000"), + mask => (0 => x"fffff000", + 1 => x"fffff800") + ) + port map + ( + clk => clk, + rst => rst, + slave_i => intercon_slave_i, + slave_o => intercon_slave_o, + master_i => intercon_master_i, + master_o => intercon_master_o + ); +end; diff --git a/ip/intercon/rtl/fifo.vhd b/ip/intercon/rtl/fifo.vhd new file mode 100644 index 0000000..1381c4d --- /dev/null +++ b/ip/intercon/rtl/fifo.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.rwp_ram_package.all; + +entity fifo is + generic( + sync_depth : natural := 3; + gray_code : boolean := true; + addr_width : natural := 4; + data_width : natural := 32); + port( + rst : in std_logic; + -- write port, only set w_en when w_rdy + w_clk : in std_logic; + w_rdy : out std_logic; + w_en : in std_logic; + w_data : in std_logic_vector(data_width-1 downto 0); + -- (pre)alloc port, can be unused + a_clk : in std_logic; + a_rdy : out std_logic; + a_en : in std_logic; + -- read port, only set r_en when r_rdy + -- data is valid the cycle after r_en raised + r_clk : in std_logic; + r_rdy : out std_logic; + r_en : in std_logic; + r_data : out std_logic_vector(data_width-1 downto 0)); +end fifo; + +architecture rtl of fifo is + subtype counter is unsigned(addr_width downto 0); + type counter_shift is array(sync_depth downto 0) of counter; + + signal r_idx_bnry : counter; + signal r_idx_gray : counter; + signal w_idx_bnry : counter; + signal w_idx_gray : counter; + signal a_idx_bnry : counter; + signal a_idx_gray : counter; + + signal r_idx_shift_w : counter_shift; -- r_idx_gray in w_clk + signal r_idx_shift_a : counter_shift; -- r_idx_gray in a_clk + signal w_idx_shift_r : counter_shift; -- w_idx_gray in r_clk + + function bin2gray(a : unsigned) return unsigned is + variable o : unsigned(a'length downto 0); + begin + if gray_code then + o := (a & '0') xor ('0' & a); + else + o := (a & '0'); + end if; + return o(a'length downto 1); + end bin2gray; + + function index(a : counter) return std_logic_vector is + begin + return std_logic_vector(a(addr_width-1 downto 0)); + end index; + + function empty(a, b : counter) return std_logic is + begin + if a = b then + return '1'; + else + return '0'; + end if; + end empty; + + function full(a, b : counter) return std_logic is + variable mask : counter := (others => '0'); + begin + -- In binary a full FIFO has indexes (a XOR 1000...00) = b + -- bin2gray is a linear function, thus: + -- a XOR 1000..00 = b iff + -- bin2gray(a XOR 1000...00) = bin2gray(b) iff + -- bin2gray(a) XOR bin2gray(1000...00) = bin2gray(b) iif + -- bin2gray(a) XOR 1100..00 = bin2gray(b) + mask(addr_width) := '1'; + mask := bin2gray(mask); + if (a xor mask) = b then + return '1'; + else + return '0'; + end if; + end full; +begin + ram : rwp_ram + generic map(addr_width => addr_width, data_width => data_width) + port map(w_clk => w_clk, w_en => w_en, w_addr => index(w_idx_bnry), w_data => w_data, + r_clk => r_clk, r_en => r_en, r_addr => index(r_idx_bnry), r_data => r_data); + + read : process(r_clk) + variable idx : counter; + begin + if rising_edge(r_clk) then + if rst = '1' then + idx := (others => '0'); + elsif r_en = '1' then + idx := r_idx_bnry + 1; + else + idx := r_idx_bnry; + end if; + r_idx_bnry <= idx; + r_idx_gray <= bin2gray(idx); + w_idx_shift_r(sync_depth downto 1) <= w_idx_shift_r(sync_depth-1 downto 0); + end if; + end process; + w_idx_shift_r(0) <= w_idx_gray; + r_rdy <= not empty(r_idx_gray, w_idx_shift_r(sync_depth)); + + write : process(w_clk) + variable idx : counter; + begin + if rising_edge(w_clk) then + if rst = '1' then + idx := (others => '0'); + elsif w_en = '1' then + idx := w_idx_bnry + 1; + else + idx := w_idx_bnry; + end if; + w_idx_bnry <= idx; + w_idx_gray <= bin2gray(idx); + r_idx_shift_w(sync_depth downto 1) <= r_idx_shift_w(sync_depth-1 downto 0); + end if; + end process; + r_idx_shift_w(0) <= r_idx_gray; + w_rdy <= not full(w_idx_gray, r_idx_shift_w(sync_depth)); + + alloc : process(a_clk) + variable idx : counter; + begin + if rising_edge(a_clk) then + if rst = '1' then + idx := (others => '0'); + elsif a_en = '1' then + idx := a_idx_bnry + 1; + else + idx := a_idx_bnry; + end if; + a_idx_bnry <= idx; + a_idx_gray <= bin2gray(idx); + r_idx_shift_a(sync_depth downto 1) <= r_idx_shift_a(sync_depth-1 downto 0); + end if; + end process; + r_idx_shift_a(0) <= r_idx_gray; + a_rdy <= not full(a_idx_gray, r_idx_shift_a(sync_depth)); +end rtl; diff --git a/ip/intercon/rtl/fifo_package.vhd b/ip/intercon/rtl/fifo_package.vhd new file mode 100644 index 0000000..9b0014d --- /dev/null +++ b/ip/intercon/rtl/fifo_package.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package fifo_package is + component fifo is + generic( + sync_depth : natural := 3; + gray_code : boolean := true; + addr_width : natural := 4; + data_width : natural := 32); + port( + rst : in std_logic; + -- write port, only set w_en when w_rdy + w_clk : in std_logic; + w_rdy : out std_logic; + w_en : in std_logic; + w_data : in std_logic_vector(data_width-1 downto 0); + -- (pre)alloc port, can be unused + a_clk : in std_logic; + a_rdy : out std_logic; + a_en : in std_logic; + -- read port, only set r_en when r_rdy + -- data is valid the cycle after r_en raised + r_clk : in std_logic; + r_rdy : out std_logic; + r_en : in std_logic; + r_data : out std_logic_vector(data_width-1 downto 0)); + end component; +end fifo_package; diff --git a/ip/intercon/rtl/rwp_ram.vhd b/ip/intercon/rtl/rwp_ram.vhd new file mode 100644 index 0000000..ee9e67f --- /dev/null +++ b/ip/intercon/rtl/rwp_ram.vhd @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Read during write has an undefined result +entity rwp_ram is + generic( + addr_width : natural := 4; + data_width : natural := 32); + port( + -- write port + w_clk : in std_logic; + w_en : in std_logic; + w_addr : in std_logic_vector(addr_width-1 downto 0); + w_data : in std_logic_vector(data_width-1 downto 0); + -- read port + r_clk : in std_logic; + r_en : in std_logic; + r_addr : in std_logic_vector(addr_width-1 downto 0); + r_data : out std_logic_vector(data_width-1 downto 0)); +end rwp_ram; + +architecture rtl of rwp_ram is + type ram_t is array(2**addr_width-1 downto 0) of std_logic_vector(data_width-1 downto 0); + signal ram : ram_t := (others => (others => '0')); + + -- Tell synthesizer we do not care about read during write behaviour + attribute ramstyle : string; + attribute ramstyle of ram : signal is "no_rw_check"; +begin + write : process(w_clk) + begin + if rising_edge(w_clk) then + if w_en = '1' then + ram(to_integer(unsigned(w_addr))) <= w_data; + end if; + end if; + end process; + + read : process(r_clk) + begin + if rising_edge(r_clk) then + if r_en = '1' then + r_data <= ram(to_integer(unsigned(r_addr))); + end if; + end if; + end process; +end rtl; diff --git a/ip/intercon/rtl/rwp_ram_package.vhd b/ip/intercon/rtl/rwp_ram_package.vhd new file mode 100644 index 0000000..fd41c4b --- /dev/null +++ b/ip/intercon/rtl/rwp_ram_package.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package rwp_ram_package is + -- Read during write has an undefined result + component rwp_ram is + generic( + addr_width : natural := 4; + data_width : natural := 32); + port( + -- write port + w_clk : in std_logic; + w_en : in std_logic; + w_addr : in std_logic_vector(addr_width-1 downto 0); + w_data : in std_logic_vector(data_width-1 downto 0); + -- read port + r_clk : in std_logic; + r_en : in std_logic; + r_addr : in std_logic_vector(addr_width-1 downto 0); + r_data : out std_logic_vector(data_width-1 downto 0)); + end component; +end rwp_ram_package; diff --git a/ip/intercon/rtl/test.vhd b/ip/intercon/rtl/test.vhd new file mode 100644 index 0000000..41f15d2 --- /dev/null +++ b/ip/intercon/rtl/test.vhd @@ -0,0 +1,188 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; +use work.crossbar_package.all; +use work.dma_package.all; +use work.test_slave_package.all; +use work.clock_crossing_package.all; + +entity test is +end test; + +architecture rtl of test is + constant masters : natural := 3; + constant slaves : natural := 3; + + signal m : wishbone_master_out; + signal s : wishbone_master_in; + + signal intercon_slave_i : wishbone_slave_in_vector(masters-1 downto 0); + signal intercon_slave_o : wishbone_slave_out_vector(masters-1 downto 0); + signal intercon_master_i : wishbone_master_in_vector(slaves-1 downto 0); + signal intercon_master_o : wishbone_master_out_vector(slaves-1 downto 0); + + signal ram_slave_i : wishbone_slave_in; + signal ram_slave_o : wishbone_slave_out; + + signal rst : std_logic := '1'; + signal clk : std_logic := '0'; + signal ram_clk : std_logic := '0'; + + procedure tick(signal clk : out std_logic) is + begin + wait for 20ns; + clk <= '0'; + wait for 20ns; + clk <= '1'; + wait for 0ns; + end tick; + + procedure write (signal clk : out std_logic; + signal m : out wishbone_master_out; + signal r : in wishbone_master_in; + constant a : in wishbone_address; + constant d : in wishbone_data) is + begin + m.CYC <= '1'; + m.STB <= '1'; + m.SEL <= (others => '1'); + m.WE <= '1'; + m.ADR <= a; + m.DAT <= d; + + tick(clk); + while r.STALL = '1' loop + tick(clk); + end loop; + + m.STB <= '0'; + m.SEL <= (others => '0'); + m.ADR <= (others => '0'); + m.DAT <= (others => '0'); + m.WE <= '0'; + + while r.ACK = '0' loop + tick(clk); + end loop; + + m.CYC <= '0'; + tick(clk); + end write; +begin + intercon : crossbar + generic map + ( + masters => masters, + slaves => slaves, + async => false + ) + port map + ( + clk => clk, + rst => rst, + slave_i => intercon_slave_i, + slave_o => intercon_slave_o, + master_i => intercon_master_i, + master_o => intercon_master_o, + address => (0 => x"00000000", + 1 => x"10000000", + 2 => x"80000000"), + mask => (0 => x"f0000000", + 1 => x"f0000000", + 2 => x"ffffffe0") + ); + + s0 : test_slave + generic map + ( + delay => 3 + ) + port map + ( + clk => clk, + rst => rst, + slave_i => intercon_master_o(0), + slave_o => intercon_master_i(0) + ); + + s1a : clock_crossing + port map( + rst => rst, + slave_clk => clk, + slave_i => intercon_master_o(1), + slave_o => intercon_master_i(1), + master_clk => ram_clk, + master_i => ram_slave_o, + master_o => ram_slave_i); + + s1r : test_slave + generic map + ( + delay => 1 + ) + port map + ( + rst => rst, + clk => ram_clk, + slave_i => ram_slave_i, + slave_o => ram_slave_o + ); + + dmac : dma + generic map + ( + logRingLen => 4 + ) + port map + ( + clk => clk, + rst => rst, + w_master_i => intercon_slave_o(1), + w_master_o => intercon_slave_i(1), + r_master_i => intercon_slave_o(2), + r_master_o => intercon_slave_i(2), + slave_i => intercon_master_o(2), + slave_o => intercon_master_i(2) + ); + + intercon_slave_i(0) <= m; + s <= intercon_slave_o(0); + + main : process + begin + m <= ( + CYC => '0', + STB => '0', + ADR => (others => '0'), + SEL => (others => '0'), + WE => '0', + DAT => (others => '0')); + + rst <= '1'; + tick(clk); + tick(clk); + tick(clk); + rst <= '0'; + tick(clk); + + write(clk, m, s, x"80000000", x"10fffff0"); + write(clk, m, s, x"80000004", x"02345670"); + write(clk, m, s, x"80000008", x"00000004"); + write(clk, m, s, x"8000000c", x"00000004"); + write(clk, m, s, x"80000010", x"00000007"); + for i in 0 to 1024 loop + tick(clk); + end loop; + end process; + + ram : process + begin + for i in 0 to 2048 loop + wait for 13ns; + ram_clk <= '0'; + wait for 13ns; + ram_clk <= '1'; + end loop; + end process; +end rtl; diff --git a/ip/intercon/rtl/test_slave.vhd b/ip/intercon/rtl/test_slave.vhd new file mode 100644 index 0000000..4034e69 --- /dev/null +++ b/ip/intercon/rtl/test_slave.vhd @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +entity test_slave is + generic( + delay : integer := 1 + ); + port( + -- Common wishbone signals + clk : in std_logic; + rst : in std_logic; + -- Slave control port + slave_i : in wishbone_slave_in; + slave_o : out wishbone_slave_out + ); +end test_slave; + +architecture rtl of test_slave is + type result_t is array(delay downto 0) of wishbone_data; + signal ack_shift : std_logic_vector(delay downto 0); + signal res_shift : result_t; +begin + slave_o.ACK <= ack_shift(0); + slave_o.ERR <= '0'; + slave_o.RTY <= '0'; + slave_o.DAT <= res_shift(0); + slave_o.STALL <= '0'; + + ack_shift(delay) <= slave_i.STB and slave_i.CYC; + + main : process(clk) + begin + if rising_edge(clk) then + if (rst = '1') then + ack_shift(delay-1 downto 0) <= (others => '0'); + res_shift <= (others => (others => '0')); + else + if (slave_i.CYC = '1' and slave_i.STB = '1' and slave_i.WE = '0') then + res_shift(delay) <= std_logic_vector(unsigned(res_shift(delay)) + 1); + end if; + ack_shift(delay-1 downto 0) <= ack_shift(delay downto 1); + res_shift(delay-1 downto 0) <= res_shift(delay downto 1); + end if; + end if; + end process; +end rtl; diff --git a/ip/intercon/rtl/test_slave_package.vhd b/ip/intercon/rtl/test_slave_package.vhd new file mode 100644 index 0000000..2d20c9c --- /dev/null +++ b/ip/intercon/rtl/test_slave_package.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_package.all; + +package test_slave_package is + component test_slave is + generic( + delay : integer := 1 + ); + port( + -- Common wishbone signals + clk : in std_logic; + rst : in std_logic; + -- Slave control port + slave_i : in wishbone_slave_in; + slave_o : out wishbone_slave_out + ); + end component; +end test_slave_package; diff --git a/ip/intercon/rtl/wave.do b/ip/intercon/rtl/wave.do new file mode 100644 index 0000000..0dd2543 --- /dev/null +++ b/ip/intercon/rtl/wave.do @@ -0,0 +1,34 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /test/dmac/interrupt +add wave -noupdate /test/rst +add wave -noupdate /test/clk +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/test/intercon_slave_i(0).cyc {-height 16 -radix hexadecimal} /test/intercon_slave_i(0).stb {-height 16 -radix hexadecimal} /test/intercon_slave_i(0).adr {-height 16 -radix hexadecimal} /test/intercon_slave_i(0).sel {-height 16 -radix hexadecimal} /test/intercon_slave_i(0).we {-height 16 -radix hexadecimal} /test/intercon_slave_i(0).dat {-height 16 -radix hexadecimal}} /test/intercon_slave_i(0) +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/test/intercon_slave_o(0).ack {-height 16 -radix hexadecimal} /test/intercon_slave_o(0).err {-height 16 -radix hexadecimal} /test/intercon_slave_o(0).rty {-height 16 -radix hexadecimal} /test/intercon_slave_o(0).stall {-height 16 -radix hexadecimal} /test/intercon_slave_o(0).dat {-height 16 -radix hexadecimal}} /test/intercon_slave_o(0) +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/test/intercon_slave_i(1).cyc {-height 16 -radix hexadecimal} /test/intercon_slave_i(1).stb {-height 16 -radix hexadecimal} /test/intercon_slave_i(1).adr {-height 16 -radix hexadecimal} /test/intercon_slave_i(1).sel {-height 16 -radix hexadecimal} /test/intercon_slave_i(1).we {-height 16 -radix hexadecimal} /test/intercon_slave_i(1).dat {-height 16 -radix hexadecimal}} /test/intercon_slave_i(1) +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/test/intercon_slave_o(1).ack {-height 16 -radix hexadecimal} /test/intercon_slave_o(1).err {-height 16 -radix hexadecimal} /test/intercon_slave_o(1).rty {-height 16 -radix hexadecimal} /test/intercon_slave_o(1).stall {-height 16 -radix hexadecimal} /test/intercon_slave_o(1).dat {-height 16 -radix hexadecimal}} /test/intercon_slave_o(1) +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/test/intercon_slave_i(2).cyc {-height 16 -radix hexadecimal} /test/intercon_slave_i(2).stb {-height 16 -radix hexadecimal} /test/intercon_slave_i(2).adr {-height 16 -radix hexadecimal} /test/intercon_slave_i(2).sel {-height 16 -radix hexadecimal} /test/intercon_slave_i(2).we {-height 16 -radix hexadecimal} /test/intercon_slave_i(2).dat {-height 16 -radix hexadecimal}} /test/intercon_slave_i(2) +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/test/intercon_slave_o(2).ack {-height 16 -radix hexadecimal} /test/intercon_slave_o(2).err {-height 16 -radix hexadecimal} /test/intercon_slave_o(2).rty {-height 16 -radix hexadecimal} /test/intercon_slave_o(2).stall {-height 16 -radix hexadecimal} /test/intercon_slave_o(2).dat {-height 16 -radix hexadecimal}} /test/intercon_slave_o(2) +add wave -noupdate /test/dmac/read_issue_offset +add wave -noupdate /test/dmac/read_result_offset +add wave -noupdate /test/dmac/write_issue_offset +add wave -noupdate /test/dmac/write_result_offset +add wave -noupdate /test/dmac/main/ring_full +add wave -noupdate /test/dmac/interrupt +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1585871 ps} 0} +configure wave -namecolwidth 140 +configure wave -valuecolwidth 66 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {3150 ns} diff --git a/ip/intercon/rtl/wishbone_package.vhd b/ip/intercon/rtl/wishbone_package.vhd new file mode 100644 index 0000000..1d814a6 --- /dev/null +++ b/ip/intercon/rtl/wishbone_package.vhd @@ -0,0 +1,75 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package wishbone_package is + + constant wishbone_address_width : integer := 32; + constant wishbone_data_width : integer := 32; + + subtype wishbone_address is + std_logic_vector(wishbone_address_width-1 downto 0); + subtype wishbone_data is + std_logic_vector(wishbone_data_width-1 downto 0); + subtype wishbone_byte_select is + std_logic_vector((wishbone_address_width/8)-1 downto 0); + subtype wishbone_cycle_type is + std_logic_vector(2 downto 0); + subtype wishbone_burst_type is + std_logic_vector(1 downto 0); + + -- A B.4 Wishbone pipelined master + -- Pipelined wishbone is always LOCKed during CYC (else ACKs would get lost) + type wishbone_master_out is record + CYC : std_logic; + STB : std_logic; + ADR : wishbone_address; + SEL : wishbone_byte_select; + WE : std_logic; + DAT : wishbone_data; + end record wishbone_master_out; + subtype wishbone_slave_in is wishbone_master_out; + + type wishbone_slave_out is record + ACK : std_logic; + ERR : std_logic; + RTY : std_logic; + STALL : std_logic; + DAT : wishbone_data; + end record wishbone_slave_out; + subtype wishbone_master_in is wishbone_slave_out; + + type wishbone_v3_master_out is record + CYC : std_logic; + STB : std_logic; + ADR : wishbone_address; + SEL : wishbone_byte_select; + WE : std_logic; + LOCK : std_logic; + DAT : wishbone_data; + CTI : wishbone_cycle_type; + BTE : wishbone_burst_type; + end record wishbone_v3_master_out; + subtype wishbone_v3_slave_in is wishbone_v3_master_out; + + type wishbone_v3_slave_out is record + ACK : std_logic; + ERR : std_logic; + RTY : std_logic; + DAT : wishbone_data; + end record wishbone_v3_slave_out; + subtype wishbone_v3_master_in is wishbone_v3_slave_out; + + type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out; + type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out; + subtype wishbone_slave_in_vector is wishbone_master_out_vector; + subtype wishbone_master_in_vector is wishbone_slave_out_vector; + + type wishbone_v3_master_out_vector is array (natural range <>) of wishbone_v3_master_out; + type wishbone_v3_slave_out_vector is array (natural range <>) of wishbone_v3_slave_out; + subtype wishbone_v3_slave_in_vector is wishbone_v3_master_out_vector; + subtype wishbone_v3_master_in_vector is wishbone_v3_slave_out_vector; + + type wishbone_address_vector is array (natural range <>) of wishbone_address; + type wishbone_data_vector is array (natural range <>) of wishbone_data; +end wishbone_package; diff --git a/ip/mor1kx-mor1kx_v4/LICENSE b/ip/mor1kx-mor1kx_v4/LICENSE new file mode 100644 index 0000000..da50884 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/LICENSE @@ -0,0 +1,370 @@ +Open Hardware Description License Version 1.0 +(Based on the MPL 2.0 RC2) +======================================================== + +1. Definitions +-------------- + +1.1. "Contributor" + means each individual or legal entity that creates, contributes to + the creation of, or owns a Covered Hardware Description. + +1.2. "Contributor Version" + means the combination of the Contributions of others (if any) used + by a Contributor and that particular Contributor's Contribution. + +1.3. "Contribution" + means Covered Hardware Description of a particular Contributor. + +1.4. "Covered Hardware Description" + means Source Code Form to which the initial Contributor has attached + the notice in Exhibit A, the Processed Form of such Source Code + Form, and Modifications of such Source Code Form, in each case + including portions thereof. + +1.5. "Incompatible With Secondary Licenses" + means that the initial Contributor has attached the notice described in + Exhibit B to the Covered Hardware Description + +1.6. "Processed Form" + means any form of the work other than Source Code Form. + +1.7. "Larger Work" + means a work that combines a Covered Hardware Description with code in a + separate file or files not governed by the terms of this License. + +1.8. "License" + means this document. + +1.9. "Licensable" + means having the right to grant, to the maximum extent possible, + whether at the time of the initial grant or subsequently, any and + all of the rights conveyed by this License. + +1.10. "Modifications" + means any of the following: + + (a) any file in Source Code Form that results from an addition to, + deletion from, or modification of the contents of a Covered + Hardware Description; or + + (b) any new file in Source Code Form that contains any Covered + Hardware Description Source. + +1.11. "Patent Claims" of a Contributor + means any patent claim(s), including without limitation, method, + process, and apparatus claims, in any patent Licensable by such + Contributor that would be infringed, but for the grant of the + License, by the making, using, selling, offering for sale, having + made, import, or transfer of either its Contributions or its + Contributor Version. + +1.12. "Secondary License" + means either the GNU General Public License, Version 2.0 or later, + the GNU Lesser General Public License, Version 2.1 or later, or the + GNU Affero General Public License, Version 3.0 or later, or the + TAPR Open Hardware License, Version 1.0 or later, or the CERN OHL, + Verstion 1.1 or later. + +1.13. "Source Code Form" + means the form of the work preferred for making modifications. + +1.14. "You" (or "Your") + means an individual or a legal entity exercising rights under this + License. For legal entities, "You" includes any entity that + controls, is controlled by, or is under common control with You. For + purposes of this definition, "control" means (a) the power, direct + or indirect, to cause the direction or management of such entity, + whether by contract or otherwise, or (b) ownership of more than + fifty percent (50%) of the outstanding shares or beneficial + ownership of such entity. + +2. License Grants and Conditions +-------------------------------- + +2.1. Grants + +Each Contributor hereby grants You a world-wide, royalty-free, +non-exclusive license: + +(a) under intellectual property rights (other than patent or trademark) + Licensable by such Contributor to use, reproduce, make available, + modify, display, perform, distribute, and otherwise exploit its + Contributions, either on an unmodified basis, with Modifications, or + as part of a Larger Work; and + +(b) under Patent Claims of such Contributor to make, use, sell, offer + for sale, have made, import, and otherwise transfer either its + Contributions or its Contributor Version. + +2.2. Effective Date + +The licenses granted in Section 2.1 with respect to any Contribution +become effective for each Contribution on the date the Contributor first +distributes such Contribution. + +2.3. Limitations on Grant Scope + +The licenses granted in this Section 2 are the only rights granted under +this License. No additional rights or licenses will be implied from the +distribution or licensing of Covered Hardware Description under this License. +Notwithstanding Section 2.1(b) above, no patent license is granted by a +Contributor: + +(a) for any code that a Contributor has removed from Covered Hardware + Description; or + +(b) for infringements caused by: (i) Your and any other third party's + modifications of a Covered Hardware Description, or (ii) the combination + of its Contributions with other Source (except as part of its Contributor + Version); or + +(c) under Patent Claims infringed by a Covered Hardware Description in the + absence of its Contributions. + +This License does not grant any rights in the trademarks, service marks, +or logos of any Contributor (except as may be necessary to comply with +the notice requirements in Section 3.4). + +2.4. Subsequent Licenses + +No Contributor makes additional grants as a result of Your choice to +distribute the Covered Hardware Description under a subsequent version of this +License (see Section 10.2) or under the terms of a Secondary License (if +permitted under the terms of Section 3.3). + +2.5. Representation + +Each Contributor represents that the Contributor believes its +Contributions are its original creation(s) or it has sufficient rights +to grant the rights to its Contributions conveyed by this License. + +2.6. Fair Use + +This License is not intended to limit any rights You have under +applicable copyright doctrines of fair use, fair dealing, or other +equivalents. + +2.7. Conditions + +Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted +in Section 2.1. + +3. Responsibilities +------------------- + +3.1. Distribution of Source Form + +All distribution of Covered Hardware Description in Source Code Form, +including any Modifications that You create or to which You contribute, must be +under the terms of this License. You must inform recipients that the Source +Code Form of the Covered Hardware Description is governed by the terms of this +License, and how they can obtain a copy of this License. You may not +attempt to alter or restrict the recipients' rights in the Source Code +Form. + +3.2. Distribution of Processed Form + +If You distribute Covered Hardware Description in Processed Form then: + +(a) such Covered Hardware Description must also be made available in Source + Code Form, as described in Section 3.1, and You must inform recipients of + the Processed Form how they can obtain a copy of such Source Code + Form by reasonable means in a timely manner, at a charge no more + than the cost of distribution to the recipient; and + +(b) You may distribute such Processed Form under the terms of this + License, or sublicense it under different terms, provided that the + license for the Processed Form does not attempt to limit or alter + the recipients' rights in the Source Code Form under this License. + +3.3. Distribution of a Larger Work + +You may create and distribute a Larger Work under terms of Your choice, +provided that You also comply with the requirements of this License for +the Covered Hardware Description. If the Larger Work is a combination of a +Covered Hardware Description with a work governed by a Secondary License, and +the Covered Hardware Description is not Incompatible With Secondary Licenses, +this License permits You to additionally distribute such Covered Hardware +Description under the terms of that Secondary License, so that the recipient of +the Larger Work may, at their option, further distribute the Covered Hardware +Description under the terms of either this License or that Secondary License. + +3.4. Notices + +You may not remove or alter the substance of any license notices +(including copyright notices, patent notices, disclaimers of warranty, +or limitations of liability) contained within the Source Code Form of +the Covered Hardware Description, except that You may alter any license notices +to the extent required to remedy known factual inaccuracies. + +3.5. Application of Additional Terms + +You may choose to offer, and to charge a fee for, warranty, support, +indemnity or liability obligations to one or more recipients of a Covered +Hardware Description. However, You may do so only on Your own behalf, and not +on behalf of any Contributor. You must make it absolutely clear that any +such warranty, support, indemnity, or liability obligation is offered by +You alone, and You hereby agree to indemnify every Contributor for any +liability incurred by such Contributor as a result of warranty, support, +indemnity or liability terms You offer. You may include additional +disclaimers of warranty and limitations of liability specific to any +jurisdiction. + +4. Inability to Comply Due to Statute or Regulation +--------------------------------------------------- + +If it is impossible for You to comply with any of the terms of this +License with respect to some or all of the Covered Hardware Description due to +statute, judicial order, or regulation then You must: (a) comply with +the terms of this License to the maximum extent possible; and (b) +describe the limitations and the code they affect. Such description must +be placed in a text file included with all distributions of the Covered +Hardware Description under this License. Except to the extent prohibited by +statute or regulation, such description must be sufficiently detailed for a +recipient of ordinary skill to be able to understand it. + +5. Termination +-------------- + +5.1. The rights granted under this License will terminate automatically +if You fail to comply with any of its terms. However, if You become +compliant, then the rights granted under this License from a particular +Contributor are reinstated (a) provisionally, unless and until such +Contributor explicitly and finally terminates Your grants, and (b) on an +ongoing basis, if such Contributor fails to notify You of the +non-compliance by some reasonable means prior to 60 days after You have +come back into compliance. Moreover, Your grants from a particular +Contributor are reinstated on an ongoing basis if such Contributor +notifies You of the non-compliance by some reasonable means, this is the +first time You have received notice of non-compliance with this License +from such Contributor, and You become compliant prior to 30 days after +Your receipt of the notice. + +5.2. If You initiate litigation against any entity by asserting a patent +infringement claim (excluding declaratory judgment actions, +counter-claims, and cross-claims) alleging that a Contributor Version +directly or indirectly infringes any patent, then the rights granted to +You by any and all Contributors for the Covered Hardware Description under +Section 2.1 of this License shall terminate. + +5.3. In the event of termination under Sections 5.1 or 5.2 above, all +end user license agreements (excluding distributors and resellers) which +have been validly granted by You or Your distributors under this License +prior to termination shall survive termination. + +************************************************************************ +* * +* 6. Disclaimer of Warranty * +* ------------------------- * +* * +* The Covered Hardware Description is provided under this License on * +* an "as is" basis, without warranty of any kind, either expressed, * +* implied, or statutory, including, without limitation, warranties * +* that the Covered Hardware Description is free of defects, * +* merchantable, fit for a particular purpose or non-infringing. The * +* entire risk as to the quality and performance of the Covered * +* Hardware Description is with You. Should any Covered Hardware * +* Description prove defective in any respect, You (not any * +* Contributor) assume the cost of any necessary servicing, repair, or * +* correction. This disclaimer of warranty constitutes an essential * +* part of this License. No use of any Covered Hardware Description is * +* authorized under this License except under this disclaimer. * +* * +************************************************************************ + +************************************************************************ +* * +* 7. Limitation of Liability * +* -------------------------- * +* * +* Under no circumstances and under no legal theory, whether tort * +* (including negligence), contract, or otherwise, shall any * +* Contributor, or anyone who distributes Covered Hardware Description * +* as permitted above, be liable to You for any direct, indirect, * +* special, incidental, or consequential damages of any character * +* including, without limitation, damages for lost profits, loss of * +* goodwill, work stoppage, computer failure or malfunction, or any * +* and all other commercial damages or losses, even if such party * +* shall have been informed of the possibility of such damages. This * +* limitation of liability shall not apply to liability for death or * +* personal injury resulting from such party's negligence to the * +* extent applicable law prohibits such limitation. Some * +* jurisdictions do not allow the exclusion or limitation of * +* incidental or consequential damages, so this exclusion and * +* limitation may not apply to You. * +* * +************************************************************************ + +8. Litigation +------------- + +Any litigation relating to this License may be brought only in the +courts of a jurisdiction where the defendant maintains its principal +place of business and such litigation shall be governed by laws of that +jurisdiction, without reference to its conflict-of-law provisions. +Nothing in this Section shall prevent a party's ability to bring +cross-claims or counter-claims. + +9. Miscellaneous +---------------- + +This License represents the complete agreement concerning the subject +matter hereof. If any provision of this License is held to be +unenforceable, such provision shall be reformed only to the extent +necessary to make it enforceable. Any law or regulation which provides +that the language of a contract shall be construed against the drafter +shall not be used to construe this License against a Contributor. + +10. Versions of the License +--------------------------- + +10.1. New Versions + +Julius Baxter is the license steward. Except as provided in Section +10.3, no one other than the license steward has the right to modify or +publish new versions of this License. Each version will be given a +distinguishing version number. + +10.2. Effect of New Versions + +You may distribute the Covered Hardware Description under the terms of the +version of the License under which You originally received the Covered Hardware +Description, or under the terms of any subsequent version published by the +license steward. + +10.3. Modified Versions + +If you create designs not governed by this License, and you want to +create a new license for such designs, you may create and use a +modified version of this License if you rename the license and remove +any references to the name of the license steward (except to note that +such modified license differs from this License). + +10.4. Distributing Source Code Form that is Incompatible With Secondary +Licenses + +If You choose to distribute Source Code Form that is Incompatible With +Secondary Licenses under the terms of this version of the License, the +notice described in Exhibit B of this License must be attached. + +Exhibit A - Source Code Form License Notice +------------------------------------------- + + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + +If it is not possible or desirable to put the notice in a particular +file, then You may include the notice in a location (such as a LICENSE +file in a relevant directory) where a recipient would be likely to look +for such a notice. + +You may add additional accurate notices of copyright ownership. + +Exhibit B - "Incompatible With Secondary Licenses" Notice +--------------------------------------------------------- + + This Source Code Form is "Incompatible With Secondary Licenses", as + defined by the Open Hardware Description License, v. 1.0. diff --git a/ip/mor1kx-mor1kx_v4/README.pod b/ip/mor1kx-mor1kx_v4/README.pod new file mode 100644 index 0000000..8bebd89 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/README.pod @@ -0,0 +1,29 @@ + +=pod + +=head1 I<< mor1kx >> - an OpenRISC processor IP core + +=head2 The Basics + +This repository contains an OpenRISC 1000 compliant processor IP core. + +It is written in Verilog HDL. + +This repository only contains the IP source code and some documentation. For +a verification environment, please see other projects. + +=head2 Documentation + +The documentation is located in the doc/ directory. + +It is asciidoc format, and there's a makefile in there to build HTML or PDF. To +build the HTML documentation, run the following in the doc/ directory: + + make html + +=head2 License + +It is licensed under the Open Hardware Description License (OHDL). For +details please see the LICENSE file or http://juliusbaxter.net/ohdl/ + +=cut diff --git a/ip/mor1kx-mor1kx_v4/bench/verilog/mor1kx_monitor.v b/ip/mor1kx-mor1kx_v4/bench/verilog/mor1kx_monitor.v new file mode 100644 index 0000000..7150570 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/bench/verilog/mor1kx_monitor.v @@ -0,0 +1,923 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx monitor module + + Attaches to hooks provided in the mor1kx pipeline wrapper and provides + execution trace, disassembly, and l.nop instruction functions. + + Copyright (C) 2012, 2013 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +/* Configure these defines to point to the mor1kx instantiation */ +`ifndef MOR1KX_INST + `define MOR1KX_INST dut.mor1kx0 +`endif + +/* The rest of these shouldn't need changing if the wrapper hooks have been + set up correctly in mor1kx_cpu. */ +`ifndef CPU_WRAPPER + `define CPU_WRAPPER `MOR1KX_INST.mor1kx_cpu +`endif +`define CPU_INST `CPU_WRAPPER.`MOR1KX_CPU_PIPELINE.mor1kx_cpu +`define EXECUTE_STAGE_INSN `CPU_WRAPPER.monitor_execute_insn +`define EXECUTE_STAGE_ADV `CPU_WRAPPER.monitor_execute_advance +`define CPU_clk `CPU_WRAPPER.monitor_clk +`define CPU_FLAG `CPU_WRAPPER.monitor_flag +`define CPU_SR `CPU_WRAPPER.monitor_spr_sr +`define EXECUTE_PC `CPU_WRAPPER.monitor_execute_pc +`define GPR_GET(x) `CPU_INST.get_gpr(x) +`define GPR_SET(x, y) `CPU_INST.set_gpr(x, y) + +`include "mor1kx-defines.v" + +// Pull in an ORPSoC-specific file +`include "test-defines.v" // indicate if we should trace or not + +// OR1K ISA defines used in this file + +`define OR1K_OPCODE_POS 31:26 +`define OR1K_J_BR_IMM_POS 25:0 +`define OR1K_RD_POS 25:21 +`define OR1K_RA_POS 20:16 +`define OR1K_RB_POS 15:11 +`define OR1K_ALU_OP_POS 3:0 +`define OR1K_SF_OP 25:21 +`define OR1K_XSYNC_OP_POS 25:21 + +module mor1kx_monitor #(parameter LOG_DIR= "../out") (); + + // General output file descriptor + integer fgeneral = 0; + integer ftrace = 0; + integer insns = 0; + + wire clk; + + parameter OPTION_OPERAND_WIDTH = 32; + + reg TRACE_ENABLE; + initial TRACE_ENABLE = $test$plusargs("trace_enable"); + + reg TRACE_TO_SCREEN; + initial TRACE_TO_SCREEN = $test$plusargs("trace_to_screen"); + + assign clk = `CPU_clk; + + reg [63:0] cycle_counter = 0 ; + + /* Log file management code */ + initial + begin + $timeformat (-9, 2, " ns", 12); + fgeneral = $fopen({LOG_DIR,"/",`TEST_NAME_STRING,"-general.log"}); + ftrace = $fopen({LOG_DIR,"/",`TEST_NAME_STRING,"-trace.log"}); + end + + /* Simulation support code */ + + reg [1:80*8] decode_insn_disas; + reg [1:80*8] execute_insn_disas; + reg [OPTION_OPERAND_WIDTH-1:0] decode_pc; + reg [OPTION_OPERAND_WIDTH-1:0] execute_pc; + + reg [`OR1K_INSN_WIDTH-1:0] execute_insn; + reg flag_4stage; + + always @(`EXECUTE_STAGE_INSN) + mor1k_insn_to_string(`EXECUTE_STAGE_INSN, execute_insn_disas); + //$write("%tns: decode insn PC %08h %08h %s\n",$time, pc_decode_i, + // decode_insn_i, insn_disassembled_string); + + always @(negedge `CPU_clk) begin + + cycle_counter = cycle_counter + 1; + + if (`EXECUTE_STAGE_ADV) + begin + insns = insns + 1; + execute_insn = `EXECUTE_STAGE_INSN; + + if(TRACE_ENABLE) + mor1k_trace_print(execute_insn, `CPU_SR, `EXECUTE_PC, `CPU_FLAG); + + // Check instructions for simulation controls + if (execute_insn == 32'h15_00_00_01) + begin + $fdisplay(fgeneral,"%0t:exit(0x%08h);",$time,`GPR_GET(3)); + $fdisplay(ftrace,"exit(0x%08h);",`GPR_GET(3)); + $display("exit(0x%08h);",`GPR_GET(3)); + $finish; + end + if (execute_insn == 32'h15_00_00_02) + begin + $fdisplay(fgeneral,"%0t:report(0x%08h);",$time,`GPR_GET(3)); + $fdisplay(ftrace,"report(0x%08h);",`GPR_GET(3)); + $display("report(0x%08h);",`GPR_GET(3)); + end + if (execute_insn == 32'h15_00_00_04) + begin + $write("%c",`GPR_GET(3)); + $fdisplay(fgeneral, "%0t: l.nop putc (%c)", $time,`GPR_GET(3)); + end + if (execute_insn == 32'h15_00_00_05) + begin + cycle_counter = 0; + $fdisplay(fgeneral, "%0t: l.nop reset counter", $time); + end + if (execute_insn == 32'h15_00_00_06) + begin + $fdisplay(fgeneral, "%0t: l.nop report cycle counter: %d", $time, cycle_counter); + `GPR_SET(11,cycle_counter[31:0]); + `GPR_SET(12,cycle_counter[63:32]); + end + + if (execute_insn == 32'h15_00_00_0c) + begin + // Silent exit + $finish; + + end + + end // if (`EXECUTE_STAGE_ADV) + end + + task mor1k_trace_print; + input [31:0] insn; + input [31:0] sr; + input [31:0] pc; + input flag; + + + reg rD_used; + reg [4:0] rD_num, rA_num, rB_num; + reg [15:0] imm_16bit; + reg [25:0] imm_26bit; + reg [31:0] signext_imm_16bit; + + reg [1:80*8] insn_disas; + // Actual things happening + reg [15:0] regimm_chars; + reg [31:0] addr_result; + begin + + // Get instruction info + mor1kx_insn_info(insn,rA_num,rB_num,rD_num,rD_used,imm_16bit, + imm_26bit,regimm_chars); + + /* Sign-extend the 16-bit immediate to 32-bit so we can add it to other + 32-bit numbers and it should subtract if necessary */ + signext_imm_16bit = {{16{imm_16bit[15]}},imm_16bit}; + + // Display useful line of stuff, like or1ksim trace + if (sr[`OR1K_SPR_SR_SM] === 1'b0) + begin + $fwrite(ftrace,"U "); + if(TRACE_TO_SCREEN) + $write("U "); + end + else + begin + $fwrite(ftrace,"S "); + if(TRACE_TO_SCREEN) + $write("S "); + end + + // PC next + $fwrite(ftrace,"%08h: ", pc); + if(TRACE_TO_SCREEN) + $write("%08h: ", pc); + + // Instruction raw + $fwrite(ftrace,"%08h ",insn); + if(TRACE_TO_SCREEN) + $write("%08h ",insn); + + mor1k_insn_to_string(insn, insn_disas); + + // Instruction, disassembled + $fwrite(ftrace,"%0s", insn_disas); + if(TRACE_TO_SCREEN) + $write("%0s", insn_disas); + + for (regimm_chars=regimm_chars; + regimm_chars < 16; regimm_chars = regimm_chars + 1) + begin + $fwrite(ftrace," "); + if(TRACE_TO_SCREEN) + $write(" "); + end + + if (rD_used) + begin + if (insn[`OR1K_OPCODE_SELECT]===`OR1K_OPCODE_MFSPR) + begin + // Wait 1 cycle for MFSPR result + @(posedge `CPU_clk); + $fwrite(ftrace,"r%0d",rD_num); + if(TRACE_TO_SCREEN) + $write("r%0d",rD_num); + end + else + begin + $fwrite(ftrace,"r%0d",rD_num); + if(TRACE_TO_SCREEN) + $write("r%0d",rD_num); + end // else: !if(insn[`OR1K_OPCODE_SELECT]===`OR1K_OPCODE_MFSPR) + + // Tab 1 more if we're a single-number register + if (rD_num < 10) begin + $fwrite(ftrace,"\t\t"); + if(TRACE_TO_SCREEN) + $write("\t\t"); + end + else begin + $fwrite(ftrace,"\t"); + if(TRACE_TO_SCREEN) + $write("\t"); + end + + // Finally write what ended up in the in rD + $fwrite(ftrace,"= %08h ",`GPR_GET(rD_num)); + if(TRACE_TO_SCREEN) + $write("= %08h ",`GPR_GET(rD_num)); + end + else if (insn[`OR1K_OPCODE_SELECT]===`OR1K_OPCODE_MTSPR) + begin + // Clobber imm_16bit here to calculate MTSPR + imm_16bit = imm_16bit | `GPR_GET(rA_num); + $fwrite(ftrace,"SPR[%04x] = %08h ", imm_16bit, `GPR_GET(rB_num)); + if(TRACE_TO_SCREEN) + $write("SPR[%04x] = %08h ", imm_16bit, `GPR_GET(rB_num)); + + end // if (insn[`OR1K_OPCODE_SELECT]===`OR1K_OPCODE_MTSPR) + else if (insn[`OR1K_OPCODE_SELECT]>=`OR1K_OPCODE_SD && + insn[`OR1K_OPCODE_SELECT]<=`OR1K_OPCODE_SH) + begin + addr_result = signext_imm_16bit + `GPR_GET(rA_num); + $fwrite(ftrace,"[%08h] = %08h ",addr_result[31:0], + `GPR_GET(rB_num)); + if(TRACE_TO_SCREEN) + $write("[%08h] = %08h ",addr_result[31:0], + `GPR_GET(rB_num)); + end + else + begin + // Skip destination field + $fwrite(ftrace,"\t\t\t "); + if(TRACE_TO_SCREEN) + $write("\t\t\t "); + end + + /* Write flag */ + $fwrite(ftrace,"flag: %0d", flag); + if(TRACE_TO_SCREEN) + $write("flag: %0d", flag); + + /* End of line */ + $fwrite(ftrace,"\n"); + if(TRACE_TO_SCREEN) + $write("\n"); + + end + endtask // mor1k_trace_print + + task mor1kx_insn_info; + input [31:0] insn; + output [4:0] rA_num; + output [4:0] rB_num; + output [4:0] rD_num; + output rD_used; + output [15:0] imm_16bit; + output [25:0] imm_26bit; + + output [7:0] num_chars; + + // To count how long disassembled immediates/regs + // are - what a pain! + reg rA_used, rB_used, imm_16bit_used, + imm_26bit_used; + + reg [5:0] opcode; + + reg opc_store; + + begin + + // Register numbers (D, A and B) + rD_num = insn[`OR1K_RD_POS]; + rA_num = insn[`OR1K_RA_POS]; + rB_num = insn[`OR1K_RB_POS]; + + opcode = insn[`OR1K_OPCODE_POS]; + + + opc_store = (opcode==`OR1K_OPCODE_SD) || + (opcode==`OR1K_OPCODE_SW) || + (opcode==`OR1K_OPCODE_SB) || + (opcode==`OR1K_OPCODE_SH); + + case (opcode) + `OR1K_OPCODE_LWZ, + `OR1K_OPCODE_LBZ, + `OR1K_OPCODE_LBS, + `OR1K_OPCODE_LHZ, + `OR1K_OPCODE_LHS, + `OR1K_OPCODE_MFSPR, + `OR1K_OPCODE_MOVHI, + `OR1K_OPCODE_ADDI, + `OR1K_OPCODE_ADDIC, + `OR1K_OPCODE_ANDI, + `OR1K_OPCODE_ORI, + `OR1K_OPCODE_XORI, + `OR1K_OPCODE_MULI, + `OR1K_OPCODE_ALU, + `OR1K_OPCODE_SHRTI: + rD_used = 1; + default: + rD_used=0; + endcase // case (opcode) + + case (opcode) + `OR1K_OPCODE_J , + `OR1K_OPCODE_JAL , + `OR1K_OPCODE_BNF , + `OR1K_OPCODE_BF , + `OR1K_OPCODE_NOP , + `OR1K_OPCODE_MOVHI, + `OR1K_OPCODE_MACRC, + `OR1K_OPCODE_SYSTRAPSYNC, + `OR1K_OPCODE_RFE, + `OR1K_OPCODE_JR, + `OR1K_OPCODE_JALR: + /* + rD of store insns, is in rA field + `OR1K_OPCODE_SD, + `OR1K_OPCODE_SW, + `OR1K_OPCODE_SB, + `OR1K_OPCODE_SH + */ + rA_used = 0; + default: + rA_used=1; + endcase // case (opcode) + + case (opcode) + `OR1K_OPCODE_JR, + `OR1K_OPCODE_JALR, + `OR1K_OPCODE_MTSPR, + `OR1K_OPCODE_MAC, + `OR1K_OPCODE_MSB, + `OR1K_OPCODE_SD, + `OR1K_OPCODE_SW, + `OR1K_OPCODE_SB, + `OR1K_OPCODE_SH, + `OR1K_OPCODE_SF: + rB_used = 1; + `OR1K_OPCODE_ALU: + case(insn[`OR1K_ALU_OPC_SELECT]) + `OR1K_ALU_OPC_EXTBH, + `OR1K_ALU_OPC_EXTW, + `OR1K_ALU_OPC_FFL1: + rB_used = 0; + default: + rB_used = 1; + endcase // case (insn[`OR1K_ALU_OPC_SELECT]) + default: + rB_used = 0; + endcase // case (opcode) + + case (opcode) + `OR1K_OPCODE_MOVHI, + `OR1K_OPCODE_NOP, + `OR1K_OPCODE_SD, + `OR1K_OPCODE_SW, + `OR1K_OPCODE_SB, + `OR1K_OPCODE_SH, + `OR1K_OPCODE_LD , + `OR1K_OPCODE_LWZ , + `OR1K_OPCODE_LWS , + `OR1K_OPCODE_LBZ , + `OR1K_OPCODE_LBS , + `OR1K_OPCODE_LHZ , + `OR1K_OPCODE_LHS , + `OR1K_OPCODE_ADDI , + `OR1K_OPCODE_ADDIC, + `OR1K_OPCODE_ANDI , + `OR1K_OPCODE_ORI , + `OR1K_OPCODE_XORI , + `OR1K_OPCODE_MULI , + `OR1K_OPCODE_MACI , + `OR1K_OPCODE_SFIMM, + `OR1K_OPCODE_MTSPR, + `OR1K_OPCODE_MFSPR: + imm_16bit_used = 1; + default: + imm_16bit_used = 0; + endcase // case (opcode) + + case (opcode) + `OR1K_OPCODE_J , + `OR1K_OPCODE_JAL, + `OR1K_OPCODE_BNF, + `OR1K_OPCODE_BF: + imm_26bit_used = 1; + default: + imm_26bit_used = 0; + endcase + + // Extract immediate + case (opcode) + `OR1K_OPCODE_SW, + `OR1K_OPCODE_SB, + `OR1K_OPCODE_SH, + `OR1K_OPCODE_SD, + `OR1K_OPCODE_MTSPR: + imm_16bit = {insn[25:21],insn[10:0]}; + default: + imm_16bit = insn[15:0]; + endcase // case (opcode) + + imm_26bit = insn[25:0]; + + // Extra chars (commas, brackets) + case (opcode) +/* + `OR1K_OPCODE_J : + num_chars = 0; + `OR1K_OPCODE_JAL : + num_chars = 0; + `OR1K_OPCODE_BNF : + num_chars = 0; + `OR1K_OPCODE_BF : + num_chars = 0; + `OR1K_OPCODE_MACRC: + num_chars = 0; + `OR1K_OPCODE_SYSTRAPSYNC: + num_chars = 0; + `OR1K_OPCODE_RFE: + num_chars = 0; + `OR1K_OPCODE_JR : + num_chars = 0; + `OR1K_OPCODE_JALR : + num_chars = 0; + `OR1K_OPCODE_CUST1: + num_chars = 0; + `OR1K_OPCODE_CUST2: + num_chars = 0; + `OR1K_OPCODE_CUST3: + num_chars = 0; + `OR1K_OPCODE_CUST4: + num_chars = 0; + `OR1K_OPCODE_NOP : + num_chars = 0; + */ + `OR1K_OPCODE_MOVHI: + num_chars = 1; + `OR1K_OPCODE_MACI : + num_chars = 1; + `OR1K_OPCODE_LD : + num_chars = 3; + `OR1K_OPCODE_LWZ : + num_chars = 3; + `OR1K_OPCODE_LWS : + num_chars = 3; + `OR1K_OPCODE_LBZ : + num_chars = 3; + `OR1K_OPCODE_LBS : + num_chars = 3; + `OR1K_OPCODE_LHZ : + num_chars = 3; + `OR1K_OPCODE_LHS : + num_chars = 3; + `OR1K_OPCODE_ADDI : + num_chars = 2; + `OR1K_OPCODE_ADDIC: + num_chars = 2; + `OR1K_OPCODE_ANDI : + num_chars = 2; + `OR1K_OPCODE_ORI : + num_chars = 2; + `OR1K_OPCODE_XORI : + num_chars = 2; + `OR1K_OPCODE_MULI : + num_chars = 2; + `OR1K_OPCODE_MFSPR: + num_chars = 2; + `OR1K_OPCODE_SFIMM: + num_chars = 1; + `OR1K_OPCODE_MTSPR : + num_chars = 2; + `OR1K_OPCODE_MAC : + num_chars = 1; + `OR1K_OPCODE_MSB : + num_chars = 1; + `OR1K_OPCODE_SD : + num_chars = 3; + `OR1K_OPCODE_SW : + num_chars = 3; + `OR1K_OPCODE_SB : + num_chars = 3; + `OR1K_OPCODE_SH: + num_chars = 3; + `OR1K_OPCODE_ALU: + case(insn[`OR1K_ALU_OPC_SELECT]) + `OR1K_ALU_OPC_EXTBH, + `OR1K_ALU_OPC_EXTW, + `OR1K_ALU_OPC_FFL1: + num_chars = 1; + default: + num_chars = 2; + endcase // case (insn[`OR1K_ALU_OPC_SELECT]) + `OR1K_OPCODE_SF: + num_chars =1; + `OR1K_OPCODE_SHRTI: + /* + if (insn[5:0] < 6'h10) + num_chars = 5; + else + */ + num_chars = 6; + + default: + num_chars = 0; + + endcase // case (opcode) + + + // Determine length of register/immediate + // disassembly in characters + if (rA_used) + num_chars = (rA_num > 9) ? num_chars + 3 : + num_chars + 2; + + if (rB_used) + num_chars = (rB_num > 9) ? num_chars + 3 : + num_chars + 2; + + if (rD_used) + num_chars = (rD_num > 9) ? num_chars + 3 : + num_chars + 2; + + if (imm_16bit_used) + num_chars = num_chars + 6; + + if (imm_26bit_used) + num_chars = num_chars + 9; + + /* + $write("%b %b %b %b %b\n",rA_used, rB_used, rD_used, imm_16bit_used, + imm_26bit_used); + */ + //$write("%0d\n",num_chars); + + end + endtask // mor1k_insn_info + + + + + + task mor1k_insn_to_string; + input [31:0] insn; + output [80*8:1] insnstring; + + reg [5:0] opcode; + + reg [25:0] j_imm; + + reg [25:0] br_imm; + + reg [31:0] rA_val, rB_val; + + reg [3:0] alu_op; + + reg [5:0] sf_op; + + reg [5:0] xsync_op; + + reg [4:0] rD_num, rA_num, rB_num; + + reg [15:0] imm_16bit; + reg [15:0] imm_split16bit; + + + begin + + // Instruction opcode + opcode = insn[`OR1K_OPCODE_POS]; + // Immediates for jump or branch instructions + j_imm = insn[`OR1K_J_BR_IMM_POS]; + br_imm = insn[`OR1K_J_BR_IMM_POS]; + // Register numbers (D, A and B) + rD_num = insn[`OR1K_RD_POS]; + rA_num = insn[`OR1K_RA_POS]; + rB_num = insn[`OR1K_RB_POS]; + // Bottom 16 bits when used as immediates in various instructions + imm_16bit = insn[15:0]; + // Bottom 11 bits used as immediates for l.sX instructions + + // Split 16-bit immediate for l.mtspr/l.sX instructions + imm_split16bit = {insn[25:21],insn[10:0]}; + // ALU op for ALU instructions + alu_op = insn[`OR1K_ALU_OP_POS]; + + + // Set flag op + sf_op = insn[`OR1K_SF_OP]; + + // Xsync/syscall/trap opcode + xsync_op = insn[`OR1K_XSYNC_OP_POS]; + + case (opcode) + `OR1K_OPCODE_J: + begin + $sformat(insnstring, "l.j 0x%07h", j_imm); + end + + `OR1K_OPCODE_JAL: + begin + $sformat(insnstring, "l.jal 0x%07h", j_imm); + end + + `OR1K_OPCODE_BNF: + begin + $sformat(insnstring, "l.bnf 0x%07h", br_imm); + end + + `OR1K_OPCODE_BF: + begin + $sformat(insnstring, "l.bf 0x%07h", br_imm); + end + + `OR1K_OPCODE_RFE: + begin + $sformat(insnstring, "l.rfe "); + end + + `OR1K_OPCODE_JR: + begin + $sformat(insnstring, "l.jr r%0d",rB_num); + end + + `OR1K_OPCODE_JALR: + begin + $sformat(insnstring, "l.jalr r%0d",rB_num); + end + + `OR1K_OPCODE_LWZ: + begin + $sformat(insnstring, "l.lwz r%0d,0x%04h(r%0d)",rD_num,imm_16bit,rA_num); + end + + `OR1K_OPCODE_LBZ: + begin + $sformat(insnstring, "l.lbz r%0d,0x%04h(r%0d)",rD_num,imm_16bit,rA_num); + end + + `OR1K_OPCODE_LBS: + begin + $sformat(insnstring, "l.lbs r%0d,0x%04h(r%0d)",rD_num,imm_16bit,rA_num); + end + + `OR1K_OPCODE_LHZ: + begin + $sformat(insnstring, "l.lhz r%0d,0x%04h(r%0d)",rD_num,imm_16bit,rA_num); + end + + `OR1K_OPCODE_LHS: + begin + $sformat(insnstring, "l.lhs r%0d,0x%04h(r%0d)",rD_num,imm_16bit,rA_num); + end + + `OR1K_OPCODE_SW: + begin + $sformat(insnstring, "l.sw 0x%04h(r%0d),r%0d",imm_split16bit,rA_num,rB_num); + end + + `OR1K_OPCODE_SB: + begin + $sformat(insnstring, "l.sb 0x%04h(r%0d),r%0d",imm_split16bit,rA_num,rB_num); + end + + `OR1K_OPCODE_SH: + begin + $sformat(insnstring, "l.sh 0x%04h(r%0d),r%0d",imm_split16bit,rA_num,rB_num); + end + + `OR1K_OPCODE_MFSPR: + begin + $sformat(insnstring, "l.mfspr r%0d,r%0d,0x%04h",rD_num,rA_num,imm_16bit); + end + + `OR1K_OPCODE_MTSPR: + begin + $sformat(insnstring, "l.mtspr r%0d,r%0d,0x%04h",rA_num,rB_num,imm_split16bit); + end + + `OR1K_OPCODE_MOVHI: + begin + if (!insn[16])begin + $sformat(insnstring, "l.movhi r%0d,0x%04h",rD_num,imm_16bit); + end + else + $sformat(insnstring, "l.macrc r%0d",rD_num); + end + + `OR1K_OPCODE_ADDI: + begin + $sformat(insnstring, "l.addi r%0d,r%0d,0x%04h",rD_num,rA_num,imm_16bit); + end + + `OR1K_OPCODE_ADDIC: + begin + $sformat(insnstring, "l.addic r%0d,r%0d,0x%04h",rD_num,rA_num,imm_16bit); + end + + `OR1K_OPCODE_ANDI: + begin + $sformat(insnstring, "l.andi r%0d,r%0d,0x%04h",rD_num,rA_num,imm_16bit); + end + + `OR1K_OPCODE_ORI: + begin + $sformat(insnstring, "l.ori r%0d,r%0d,0x%04h",rD_num,rA_num,imm_16bit); + end + + `OR1K_OPCODE_XORI: + begin + $sformat(insnstring, "l.xori r%0d,r%0d,0x%04h",rD_num,rA_num,imm_16bit); + end + + `OR1K_OPCODE_MULI: + begin + $sformat(insnstring, "l.muli r%0d,r%0d,0x%04h",rD_num,rA_num,imm_16bit); + end + + `OR1K_OPCODE_ALU: + begin + case(insn[`OR1K_ALU_OPC_SELECT]) + `OR1K_ALU_OPC_ADD: + $sformat(insnstring, "l.add r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_ADDC: + $sformat(insnstring, "l.addc r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_SUB: + $sformat(insnstring, "l.sub r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_AND: + $sformat(insnstring, "l.and r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_OR: + $sformat(insnstring, "l.or r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_XOR: + $sformat(insnstring, "l.xor r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_MUL: + $sformat(insnstring, "l.mul r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_SHRT: + begin + case(insn[`OR1K_ALU_OPC_SECONDARY_SELECT]) + `OR1K_ALU_OPC_SECONDARY_SHRT_SLL: + $sformat(insnstring, "l.sll r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_SECONDARY_SHRT_SRL: + $sformat(insnstring, "l.srl r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_SECONDARY_SHRT_SRA: + $sformat(insnstring, "l.sra r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_SECONDARY_SHRT_ROR: + $sformat(insnstring, "l.ror r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + endcase // case (insn[`OR1K_ALU_OPC_SECONDARY_SELECT]) + end + `OR1K_ALU_OPC_DIV: + $sformat(insnstring, "l.div r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_DIVU: + $sformat(insnstring, "l.divu r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_MULU: + $sformat(insnstring, "l.mulu r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_CMOV: + $sformat(insnstring, "l.cmov r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + `OR1K_ALU_OPC_FFL1: + begin + case(insn[8]) + 0: + $sformat(insnstring, "l.ff1 r%0d,r%0d",rD_num,rA_num); + 1: + $sformat(insnstring, "l.fl1 r%0d,r%0d",rD_num,rA_num); + endcase // case (insn[8]) + end + + endcase // case (alu_op) + //$sformat(insnstring, "r%0d,r%0d,r%0d",rD_num,rA_num,rB_num); + end + + `OR1K_OPCODE_SHRTI: + begin + case(insn[`OR1K_ALU_OPC_SECONDARY_SELECT]) + `OR1K_ALU_OPC_SECONDARY_SHRT_SLL: + $sformat(insnstring, "l.slli r%0d,r%0d,0x%01h",rD_num,rA_num,insn[5:0]); + `OR1K_ALU_OPC_SECONDARY_SHRT_SRL: + $sformat(insnstring, "l.srli r%0d,r%0d,0x%01h",rD_num,rA_num,insn[5:0]); + `OR1K_ALU_OPC_SECONDARY_SHRT_SRA: + $sformat(insnstring, "l.srai r%0d,r%0d,0x%01h",rD_num,rA_num,insn[5:0]); + `OR1K_ALU_OPC_SECONDARY_SHRT_ROR: + $sformat(insnstring, "l.rori r%0d,r%0d,0x%01h",rD_num,rA_num,insn[5:0]); + endcase // case (insn[`OR1K_ALU_OPC_SECONDARY_SELECT]) + //$sformat(insnstring, "r%0d,r%0d,0x%0h",rD_num,rA_num,insn[5:0]); + end // case: `OR1K_OPCODE_SHRTI + + `OR1K_OPCODE_SFIMM: + begin + case(insn[`OR1K_COMP_OPC_SELECT]) + `OR1K_COMP_OPC_EQ: + $sformat(insnstring, "l.sfeqi r%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_NE: + $sformat(insnstring, "l.sfnei r%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_GTU: + $sformat(insnstring, "l.sfgtuir%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_GEU: + $sformat(insnstring, "l.sfgeuir%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_LTU: + $sformat(insnstring, "l.sfltuir%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_LEU: + $sformat(insnstring, "l.sfleuir%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_GTS: + $sformat(insnstring, "l.sfgtsir%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_GES: + $sformat(insnstring, "l.sfgesir%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_LTS: + $sformat(insnstring, "l.sfltsir%0d,0x%04h",rA_num, imm_16bit); + `OR1K_COMP_OPC_LES: + $sformat(insnstring, "l.sflesir%0d,0x%04h",rA_num, imm_16bit); + endcase // case (sf_op[2:0]) + + //$sformat(insnstring, "r%0d,0x%0h",rA_num, imm_16bit); + + end // case: `OR1K_OPCODE_SFXXI + + `OR1K_OPCODE_SF: + begin + case(insn[`OR1K_COMP_OPC_SELECT]) + `OR1K_COMP_OPC_EQ: + $sformat(insnstring, "l.sfeq r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_NE: + $sformat(insnstring, "l.sfne r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_GTU: + $sformat(insnstring, "l.sfgtu r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_GEU: + $sformat(insnstring, "l.sfgeu r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_LTU: + $sformat(insnstring, "l.sfltu r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_LEU: + $sformat(insnstring, "l.sfleu r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_GTS: + $sformat(insnstring, "l.sfgts r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_GES: + $sformat(insnstring, "l.sfges r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_LTS: + $sformat(insnstring, "l.sflts r%0d,r%0d",rA_num, rB_num); + `OR1K_COMP_OPC_LES: + $sformat(insnstring, "l.sfles r%0d,r%0d",rA_num, rB_num); + endcase // case (sf_op[2:0]) + //$sformat(insnstring, "r%0d,r%0d",rA_num, rB_num); + + end + + `OR1K_OPCODE_MACI: + begin + $sformat(insnstring, "l.maci r%0d,0x%04h",rA_num,imm_16bit); + end + + `OR1K_OPCODE_NOP: + begin + $sformat(insnstring, "l.nop 0x%04h",imm_16bit); + end + + `OR1K_OPCODE_SYSTRAPSYNC: + begin + case (insn[`OR1K_SYSTRAPSYNC_OPC_SELECT]) + `OR1K_SYSTRAPSYNC_OPC_SYSCALL: + $sformat(insnstring, "l.sys 0x%04h",imm_16bit); + `OR1K_SYSTRAPSYNC_OPC_TRAP: + $sformat(insnstring, "l.trap 0x%04h",imm_16bit); + `OR1K_SYSTRAPSYNC_OPC_MSYNC: + $sformat(insnstring, "l.msync"); + `OR1K_SYSTRAPSYNC_OPC_PSYNC: + $sformat(insnstring, "l.psync"); + `OR1K_SYSTRAPSYNC_OPC_CSYNC: + $sformat(insnstring, "l.csync"); + endcase // case (insn[`OR1K_SYSTRAPSYNC_OPC_SELECT]) + end + default: + begin + $sformat(insnstring, "%t: Unknown opcode 0x%0h",$time,opcode); + $sformat(insnstring, "%t: Unknown opcode 0x%0h",$time,opcode); + end + + endcase // case (opcode) + + end + endtask // mor1k_insn_to_string + +endmodule // mor1kx_module diff --git a/ip/mor1kx-mor1kx_v4/bench/verilog/mor1kx_traceport_monitor.v b/ip/mor1kx-mor1kx_v4/bench/verilog/mor1kx_traceport_monitor.v new file mode 100644 index 0000000..9bd6d3a --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/bench/verilog/mor1kx_traceport_monitor.v @@ -0,0 +1,128 @@ +`include "mor1kx-defines.v" + +`define OR1K_OPCODE_POS 31:26 +`define OR1K_J_BR_IMM_POS 25:0 +`define OR1K_RD_POS 25:21 +`define OR1K_RA_POS 20:16 +`define OR1K_RB_POS 15:11 +`define OR1K_ALU_OP_POS 3:0 +`define OR1K_SF_OP 25:21 +`define OR1K_XSYNC_OP_POS 25:21 + +module mor1kx_traceport_monitor(/*AUTOARG*/ + // Outputs + finish, + // Inputs + clk, rst, traceport_exec_valid, traceport_exec_pc, + traceport_exec_insn, traceport_exec_wbdata, traceport_exec_wbreg, + traceport_exec_wben, finish_cross + ); + + parameter OPTION_OPERAND_WIDTH = 32; + parameter OPTION_RF_ADDR_WIDTH = 5; + + parameter LOG_DIR = "../out"; + + parameter COREID = 0; + parameter NUMCORES = 1; + + integer fgeneral = 0; + integer ftrace = 0; + integer insns = 0; + + input clk; + input rst; + + input traceport_exec_valid; + input [31:0] traceport_exec_pc; + input [`OR1K_INSN_WIDTH-1:0] traceport_exec_insn; + input [OPTION_OPERAND_WIDTH-1:0] traceport_exec_wbdata; + input [OPTION_RF_ADDR_WIDTH-1:0] traceport_exec_wbreg; + input traceport_exec_wben; + + input [NUMCORES-1:0] finish_cross; + output reg finish; + + reg TRACE_ENABLE; + initial TRACE_ENABLE = $test$plusargs("trace_enable"); + + reg TRACE_TO_SCREEN; + initial TRACE_TO_SCREEN = $test$plusargs("trace_to_screen"); + + reg [63:0] cycle_counter = 0 ; + + reg [OPTION_OPERAND_WIDTH-1:0] r3; + reg [7:0] printstring [0:255]; + integer printstringpos; + + /* Log file management code */ + initial + begin + $timeformat (-9, 2, " ns", 12); +// fgeneral = $fopen({LOG_DIR,"/",`TEST_NAME_STRING,"-general.log"}); +// ftrace = $fopen({LOG_DIR,"/",`TEST_NAME_STRING,"-trace.log"}); + finish = 0; + printstringpos = 0; + end + + reg [`OR1K_INSN_WIDTH-1:0] execute_insn; + integer i; + + always @(negedge clk) begin + if ((COREID == 0) && &finish_cross) begin + $finish; + end + + cycle_counter = cycle_counter + 1; + + if (traceport_exec_valid) + begin + insns = insns + 1; + execute_insn = traceport_exec_insn; + + if (traceport_exec_wben && (traceport_exec_wbreg == 3)) begin + r3 = traceport_exec_wbdata; + end + +/* TODO: Re-enable + if(TRACE_ENABLE) + mor1k_trace_print(execute_insn, `CPU_SR, `EXECUTE_PC, `CPU_FLAG);*/ + + // Check instructions for simulation controls + if (execute_insn == 32'h15_00_00_01) + begin +// $fdisplay(fgeneral,"%0t:exit(0x%08h);",$time,r3); +// $fdisplay(ftrace,"exit(0x%08h);",r3); + $display("[%0d] exit(0x%08h);",COREID,r3); + $finish; + end + if (execute_insn == 32'h15_00_00_02) + begin +// $fdisplay(fgeneral,"%0t:report(0x%08h);",$time,r3); +// $fdisplay(ftrace,"report(0x%08h);",r3); + $display("[%0d, %0t] report(0x%08h);",COREID,$time,r3); + end + if (execute_insn == 32'h15_00_00_04) + begin + printstring[printstringpos] = r3[7:0]; + printstringpos = printstringpos + 1; + if (r3 == 32'h0a) begin + $write("[%0d, %0t] ",COREID,$time); + for (i = 0; i < printstringpos; i = i + 1) begin + $write("%s",printstring[i]); + end + printstringpos = 0; + end +// $fdisplay(fgeneral, "%0t: l.nop putc (%c)", $time,r3); + end + + if (execute_insn == 32'h15_00_00_0c) + begin + // Silent exit + finish = 1; + end + + end // if (`EXECUTE_STAGE_ADV) + end + +endmodule // mor1kx_traceport_monitor diff --git a/ip/mor1kx-mor1kx_v4/doc/Makefile b/ip/mor1kx-mor1kx_v4/doc/Makefile new file mode 100644 index 0000000..f29aac4 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/doc/Makefile @@ -0,0 +1,70 @@ +ASCIIDOC=asciidoc +XSLTPROC=xsltproc +DBLATEX=dblatex + +RM ?= rm -f +CP ?= cp +MV ?= mv +CAT ?= cat +GEN-DOCINFO=gen-docinfo.pl + +ifndef PERL_PATH + PERL_PATH = /usr/bin/perl +endif + +ASCIIDOC_EXTRA += -a docinfo + +SPEC_TXT=mor1kx.asciidoc +SPEC_HTML=$(patsubst %.asciidoc,%.html,$(SPEC_TXT)) +SPEC_XML=$(patsubst %.asciidoc,%.xml,$(SPEC_TXT)) +SPEC_PDF=$(patsubst %.asciidoc,%.pdf,$(SPEC_TXT)) + +SPEC_DOCINFO=$(patsubst %.asciidoc,%-docinfo.xml,$(SPEC_TXT)) + +ifneq ($(findstring $(MAKEFLAGS),s),s) +ifndef V + QUIET_ASCIIDOC = @echo ' ' ASCIIDOC $@; + QUIET_XSLTPROC = @echo ' ' XSLTPROC $@; + QUIET_DBLATEX = @echo ' ' DBLATEX $@; + QUIET_GEN-DOCINFO = @echo ' ' GEN-DOCINFO $@; + export V +endif +endif + +all: html + +html: $(SPEC_HTML) +pdf: $(SPEC_PDF) + +$(SPEC_DOCINFO): $(SPEC_TXT) $(GEN-DOCINFO) + $(QUIET_GEN-DOCINFO)$(CAT) $< | \ + $(PERL_PATH) -ne 'if (/__vstart__/../__vend__/) {print unless /__v(start|end)__/}' | \ + $(PERL_PATH) $(GEN-DOCINFO) > $@ + +$(SPEC_XML): $(SPEC_TXT) $(SPEC_DOCINFO) + $(QUIET_ASCIIDOC)$(ASCIIDOC) $(ASCIIDOC_EXTRA) -b docbook $< + +XSLT = docbook.xsl +XSLTOPTS = --xinclude --stringparam html.stylesheet docbook-xsl.css \ + --stringparam section.autolabel 1 \ + --stringparam section.label.includes.component.label 1 + +$(SPEC_HTML): $(SPEC_XML) + $(QUIET_XSLTPROC)$(RM) $@+ $@ && \ + $(XSLTPROC) $(XSLTOPTS) -o $@+ $(XSLT) $< && \ + $(MV) $@+ $@ + +DBLATEXOPTS = --param=doc.publisher.show=0 + +$(SPEC_PDF): $(SPEC_XML) + $(QUIET_DBLATEX)$(RM) $@+ $@ && \ + $(DBLATEX) $(DBLATEXOPTS) -o $@+ \ + -p /etc/asciidoc/dblatex/asciidoc-dblatex.xsl \ + -s /etc/asciidoc/dblatex/asciidoc-dblatex.sty $< && \ + $(MV) $@+ $@ + +clean: + $(RM) *.xml *.xml+ *.html *.html+ + $(RM) openrisc1200_spec.pdf+ openrisc1200_spec.txt+ + +.PHONY: all clean html diff --git a/ip/mor1kx-mor1kx_v4/doc/docbook-xsl.css b/ip/mor1kx-mor1kx_v4/doc/docbook-xsl.css new file mode 100644 index 0000000..e11c8f0 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/doc/docbook-xsl.css @@ -0,0 +1,296 @@ +/* + CSS stylesheet for XHTML produced by DocBook XSL stylesheets. + Tested with XSL stylesheets 1.61.2, 1.67.2 +*/ + +span.strong { + font-weight: bold; +} + +body blockquote { + margin-top: .75em; + line-height: 1.5; + margin-bottom: .75em; +} + +html body { + margin: 1em 5% 1em 5%; + line-height: 1.2; + font-family: sans-serif; +} + +body div { + margin: 0; +} + +h1, h2, h3, h4, h5, h6, +div.toc p b, +div.list-of-figures p b, +div.list-of-tables p b, +div.abstract p.title +{ + color: #527bbd; + font-family: tahoma, verdana, sans-serif; +} + +div.toc p:first-child, +div.list-of-figures p:first-child, +div.list-of-tables p:first-child, +div.example p.title +{ + margin-bottom: 0.2em; +} + +body h1 { + margin: .0em 0 0 -4%; + line-height: 1.3; + border-bottom: 2px solid silver; +} + +body h2 { + margin: 0.5em 0 0 -4%; + line-height: 1.3; + border-bottom: 2px solid silver; +} + +body h3 { + margin: .8em 0 0 -3%; + line-height: 1.3; +} + +body h4 { + margin: .8em 0 0 -3%; + line-height: 1.3; +} + +body h5 { + margin: .8em 0 0 -2%; + line-height: 1.3; +} + +body h6 { + margin: .8em 0 0 -1%; + line-height: 1.3; +} + +body hr { + border: none; /* Broken on IE6 */ +} +div.footnotes hr { + border: 1px solid silver; +} + +div.navheader th, div.navheader td, div.navfooter td { + font-family: sans-serif; + font-size: 0.9em; + font-weight: bold; + color: #527bbd; +} +div.navheader img, div.navfooter img { + border-style: none; +} +div.navheader a, div.navfooter a { + font-weight: normal; +} +div.navfooter hr { + border: 1px solid silver; +} + +body td { + line-height: 1.2 +} + +body th { + line-height: 1.2; +} + +ol { + line-height: 1.2; +} + +ul, body dir, body menu { + line-height: 1.2; +} + +html { + margin: 0; + padding: 0; +} + +body h1, body h2, body h3, body h4, body h5, body h6 { + margin-left: 0 +} + +body pre { + margin: 0.5em 10% 0.5em 1em; + line-height: 1.0; + color: navy; +} + +tt.literal, code.literal { + color: navy; + font-family: sans-serif; +} + +code.literal:before { content: "'"; } +code.literal:after { content: "'"; } + +em { + font-style: italic; + color: #064; +} + +div.literallayout p { + padding: 0em; + margin: 0em; +} + +div.literallayout { + font-family: monospace; + margin: 0em; + color: navy; + border: 1px solid silver; + background: #f4f4f4; + padding: 0.5em; +} + +.programlisting, .screen { + border: 1px solid silver; + background: #f4f4f4; + margin: 0.5em 10% 0.5em 0; + padding: 0.5em 1em; +} + +div.sidebar { + background: #ffffee; + margin: 1.0em 10% 0.5em 0; + padding: 0.5em 1em; + border: 1px solid silver; +} +div.sidebar * { padding: 0; } +div.sidebar div { margin: 0; } +div.sidebar p.title { + font-family: sans-serif; + margin-top: 0.5em; + margin-bottom: 0.2em; +} + +div.bibliomixed { + margin: 0.5em 5% 0.5em 1em; +} + +div.glossary dt { + font-weight: bold; +} +div.glossary dd p { + margin-top: 0.2em; +} + +dl { + margin: .8em 0; + line-height: 1.2; +} + +dt { + margin-top: 0.5em; +} + +dt span.term { + font-style: normal; + color: navy; +} + +div.variablelist dd p { + margin-top: 0; +} + +div.itemizedlist li, div.orderedlist li { + margin-left: -0.8em; + margin-top: 0.5em; +} + +ul, ol { + list-style-position: outside; +} + +div.sidebar ul, div.sidebar ol { + margin-left: 2.8em; +} + +div.itemizedlist p.title, +div.orderedlist p.title, +div.variablelist p.title +{ + margin-bottom: -0.8em; +} + +div.revhistory table { + border-collapse: collapse; + border: none; +} +div.revhistory th { + border: none; + color: #527bbd; + font-family: tahoma, verdana, sans-serif; +} +div.revhistory td { + border: 1px solid silver; +} + +/* Keep TOC and index lines close together. */ +div.toc dl, div.toc dt, +div.list-of-figures dl, div.list-of-figures dt, +div.list-of-tables dl, div.list-of-tables dt, +div.indexdiv dl, div.indexdiv dt +{ + line-height: normal; + margin-top: 0; + margin-bottom: 0; +} + +/* + Table styling does not work because of overriding attributes in + generated HTML. +*/ +div.table table, +div.informaltable table +{ + margin-left: 0; + margin-right: 5%; + margin-bottom: 0.8em; +} +div.informaltable table +{ + margin-top: 0.4em +} +div.table thead, +div.table tfoot, +div.table tbody, +div.informaltable thead, +div.informaltable tfoot, +div.informaltable tbody +{ + /* No effect in IE6. */ + border-top: 2px solid #527bbd; + border-bottom: 2px solid #527bbd; +} +div.table thead, div.table tfoot, +div.informaltable thead, div.informaltable tfoot +{ + font-weight: bold; +} + +div.mediaobject img { + border: 1px solid silver; + margin-bottom: 0.8em; +} +div.figure p.title, +div.table p.title +{ + margin-top: 1em; + margin-bottom: 0.4em; +} + +@media print { + div.navheader, div.navfooter { display: none; } +} diff --git a/ip/mor1kx-mor1kx_v4/doc/docbook.xsl b/ip/mor1kx-mor1kx_v4/doc/docbook.xsl new file mode 100644 index 0000000..8be773a --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/doc/docbook.xsl @@ -0,0 +1,17 @@ + + + + + appendix nop + article toc,title + book toc,title,figure,table,example,equation + part nop + preface nop + qandadiv nop + qandaset nop + reference toc,title + section nop + set toc + + diff --git a/ip/mor1kx-mor1kx_v4/doc/gen-docinfo.pl b/ip/mor1kx-mor1kx_v4/doc/gen-docinfo.pl new file mode 100644 index 0000000..7ad11f2 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/doc/gen-docinfo.pl @@ -0,0 +1,36 @@ +#!/usr/bin/perl + +use warnings; +use strict; + +my @keys = qw(number date author comment); +my @revs; +{ + local $/ = ''; + + while (<>) { + my @values = split(/\|/); + my %rev; + foreach (@keys) { + $rev{$_} = shift @values; + $rev{$_} =~ s/^\s+|\s+$//g; + } + push @revs, \%rev; + } +} + +if (@revs) { + print "\n"; + foreach my $rev (@revs) { + print " \n"; + print " $rev->{number}\n"; + print " $rev->{date}\n"; + print " $rev->{author}\n"; + print " \n"; + print " $rev->{comment}\n"; + print " \n"; + print " \n"; + } + print "\n"; +} + diff --git a/ip/mor1kx-mor1kx_v4/doc/mor1kx.asciidoc b/ip/mor1kx-mor1kx_v4/doc/mor1kx.asciidoc new file mode 100644 index 0000000..542b8ff --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/doc/mor1kx.asciidoc @@ -0,0 +1,527 @@ +mor1kx IP core specification +============================ +:doctype: book + +Introduction +------------ + +This document describes the mor1kx processor block and its various configurable +components. The core is an implementation of an OpenRISC 1000 compliant +processor which is highly configurable and contains multiple pipeline +implementations along with a configurable set of peripherals such as caches, +timers, debug and bus interfaces. This documentation will contain a section +detailing each optional block such as pipeline, caches, bus interface etc. It +can outline as much implementation detail as it wants but should ultimately +provide information to users on how to program and use the peripheral, or what +to expect during execution of software on a particular configuration. + +.Document Status +****************************************************************************** +This documentation is far from complete. It is expected that the documentation +will become more extensive over time. +****************************************************************************** + +OpenRISC Family +~~~~~~~~~~~~~~~ +(((OpenRISC,Family))) +OpenRISC 1000 is architecture for a family of free, open source RISC processor +cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and +system implementations at a variety of price/performance points for a range of +applications. It is a 32/64-bit load and store RISC architecture designed with +emphasis on performance, simplicity, low power requirements, scalability and +versatility. OpenRISC 1000 architecture targets medium and high performance +networking, embedded, automotive and portable computer environments. + +mor1kx CPU +~~~~~~~~~~ + +The mor1kx implementation was developed in order to provide a better platform +for processor component development than previous implementations. The goal of +the implementation is to provide a greater level of flexibility in terms of +implementation trade-offs such as area and performance. + +The blocks within the core have been designed for maximum re-use within +different configurations. Based on this, different pipeline implementations are +a major focus of the core. With this, the core should be very useful for +developers and users alike. For developers as a base for either +high-performance or low-overhead pipeline implementations based on re-usable +components eg. decode and ALU block. For users as a wider variety of +capabilities should be available to suit the processor's use case. + +Implementation Overview +----------------------- + +The implementation is heavily modular, with each particular functional block +of the design being contained within its own Verilog module or modules. + +The implementation configuration makes use of Verilog parameters. There should +be no configuration performed with the use of Verilog defines. + +Hierarchy +~~~~~~~~~ + +The top few levels of hierarchy are as follows + +mor1kx:: Top-level, instantiatng bus interfaces and CPU top-level +* mor1kx_bus_if_xx - Bus interface, depending on desired bus standard +* mor1kx_cpu - Pipeline implementation wrapper +** mor1kx_cpu_xx - Pipeline implementation, depending on configuration +*** mor1kx_fetch_xx - Pipeline-implementation-dependent fetch stage +**** mor1kx_icache - Instruction cache implementation +**** mor1kx_immu - Instruction memory management unit implementation +*** mor1kx_decode - Generic decode stage +*** mor1kx_execute_alu - Generic ALU for execute stage +*** mor1kx_lsu_xx - Pipeline-implementation-dependent load/store unit +**** mor1kx_dcache - Data cache implementation +**** mor1kx_dmmu - Data memory management unit implementation +*** mor1kx_wb_mux_xx - Pipeline-implementation-dependent writeback stage mux +*** mor1kx_rf_xx - Pipeline-implementation-dependent register file +*** mor1kx_ctrl_xx - Pipeline-implementation-dependent control stage, usually containing features such as tick timer, interrupts etc. + + +The above hierarchy is not always the same for each pipeline implementation +(from _mor1kx_cpu_xx_ level down) but as a good indicator as to how the +existing pipeline implementations have been structured. + +Coding Style +~~~~~~~~~~~~ + +The coding style is a relatively simple Verilog style and should be adhered to +for any future development. All of the following detail how the existing code +base has been implemented, and it should be realtively easy to continue in that +style, but if in doubt, the following details some of the rules: + +* module names should be prefixed with _mor1kx_ and be in lowercase and stored in a source file of the same name plus the standard verilog suffix, _.v_. +* port names should have their direction abbreviation appended to the name +** E.g the instruction bus address output should be ibus_adr_o +** The only exceptions are the clock and reset ports, commonly referred to as _clk_ and _rst_ in the Verilog, and don't really require direction suffixes. The only exception is if a clock or reset generation module is outputting one of these, in which case it should have _o appended, otherwise for clock and reset inputs it can be inferred that they are inputs from the absence of _o. +* Parameter names should be in UPPERCASE, with parameter values, if strings, also in uppercase. +* Verilog reg and wire names should be named usefully, in lowercase, and make use of underscores in the name. +* There should be no reason to alter the mor1kx-defines.v or mor1kx-sprs.v files unless it is expanding upon or fixing what is already there. _No new class of defines controlling implementation should be added_ (use parameters instead!) Those files are only for storing architectural information in Verilog format, which can then be used in the design. + +There has been heavy use of the Emacs Verilog mode auto-implement and wire +features throughout the code. This is a useful tool and it would be useful to +stick to using this for future pipeline implementations, to speed up the +tedious task of wiring up new blocks. + + +Architecture compliance +~~~~~~~~~~~~~~~~~~~~~~~ + +The mor1kx aims to be fully OpenRISC 1000 compliant. It implements the VR2, +AVR and ISRs (still largely unused). The current OR1K architecture version +supported is 1.0. + +Version Register 2 definition +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Bits 23:0 of the VR2 are implementation-specific. They are defined, for mor1kx, +to be 3 bytes, interpreted as 3 unsigned 8-bit integers, as the following: + +* 23:16 - Major version number +* 15:8 - Minor version number +* 7:0 - Pipeline identifier +** Where this pipeline identifier means +*** 1 - Cappuccino +*** 2 - Espresso +*** 3 - Pronto Espresso + +However, the mor1kx does not implement the following at present: + +* arithmetic exception control/status registers (AECR, AESR) +* l.muld[u] and thus access to full 64-bit result as there is no MAC unit + +CPU Components +============== + +This section will outline each of the CPU component modules. + +CPU Pipeline Implementations +---------------------------- + +Available Implementations +~~~~~~~~~~~~~~~~~~~~~~~~~ + +At present the following pipeline implementations are available. These +combine various of the components, outlined in a following section, to +implement the bulk of the processor. + +- cappuccino - 6 stage, single issue, delay slot, debug unit, timers, PIC, + tightly coupled cache, MMU, ORBIS32 support +- espresso - 2 stage, single issue, delay slot, debug unit, timers, PIC, ORBIS32 support +- pronto espresso - 2 stage, single issue, no delay slot, debug unit, timers, PIC, ORBIS32 support + +Cappuccino pipeline +~~~~~~~~~~~~~~~~~~~ + +A 6 stage pipeline. (address, fetch, decode, execute, control/memory and writeback) + +Caches supported (optional). + +MMUs supported (optional). + +It has a delay slot on jump and branch instructions. + +It features the EVBAR. + +Pipeline consists of the following modules: + +* Fetch: +** <> +** <> +** <> +* Decode +** <> +* Execute stage +** <> +** <> +** <> +** <> +* Control/memory stage +** <> +** <> +** <> +** <> +** <> + +The following sections outline the pipeline-specific modules + +[[mor1kx_ctrl_branch_cappuccino]] +mor1kx_ctrl_branch_cappuccino +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This is the pipelines branch control unit, selecting the jump/branch address +and opcode input from execute stage, with flag input from control stage. +Indication of whether a branch needs to be evaluated (based on flag) comes +from the control stage. + +The block then outputs the appropriate indication of whether a branch is going +to occur and the target address to the fetch stage. + +It is wholly combinatorial. + +[[mor1kx_ctrl_cappuccino]] +mor1kx_ctrl_cappuccino +^^^^^^^^^^^^^^^^^^^^^^ + +This module contains a lot of the core functionality of the pipeline, such as: + +* SPRs (NPC, PPC, etc.) and accesses to them +* PIC +* Debug unit +* Tick timer +* Pipeline control signals +** Advance/stall signaling to each pipeline stage +** Exception handling + +It's in a big monolithic file but perhaps things like the PIC and tick timer +could be split out and made genering among pipeline implementations. + +[[mor1kx_execute_ctrl_cappuccino]] +mor1kx_execute_ctrl_cappuccino +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Determine the status of execute-stage units in play (ALU or LSU) and: + +* Determine when they're done +* Control the write-enable to the register file for any result +* Correctly propagate exception signals from either execute or earlier stages + +[[mor1kx_fetch_cappuccino]] +mor1kx_fetch_cappuccino +^^^^^^^^^^^^^^^^^^^^^^^ + +Fetch stage, tightly coupled with instruction cache. + +[[mor1kx_lsu_cappuccino]] +mor1kx_lsu_cappuccino +^^^^^^^^^^^^^^^^^^^^^ + +Load/store unit. + +Performs accesses of the generic bus which may or may not be then going to +a data cache, and finally out onto the bus via the selected bus interface. + +Is 32-bit specific. + +Combinatorial outputs to pipeline control logic to reduce latency, may +introduce long paths effecting timing, though. + +Handles sign extension if load/store requires it. +Generates alignment exception, and handles bus error exception back to +the mor1kx_execute_ctrl_cappuccino module. + +[[mor1kx_rf_cappuccino]] +mor1kx_rf_cappuccino +^^^^^^^^^^^^^^^^^^^^ + +Register file for the pipeline. 2 lots of 32 general purpose registers (GPRs.) + +Handles forwarding from control/memory and writeback to execute stage. + +Instantiates a RAM for each of the two register files (_mor1kx_rf_ram_ module.) + +[[mor1kx_wb_mux_cappuccino]] +mor1kx_wb_mux_cappuccino +^^^^^^^^^^^^^^^^^^^^^^^^ + +Writeback stage mux. Inputs are ALU result, LSU result, SPR value for l.mfspr +instruction. Generates link address for jump-and-link instructions. + + +Espresso pipeline +~~~~~~~~~~~~~~~~~ + +The espresso pipeline essentially contains two stages: a fetch and "the-rest" +stages. There is no registering in the decode stage, so the register outputting +the fetched instruction from the fetch stage is what is used for the remainder +of that instruction's processing. + +No support for caches. + +It has a delay slot. + +Supports DSX bit in SR. + +Pipeline consists of the following modules: + +* Fetch: +** <> +* Decode +** <> +* Execute/memory stage +** <> +** <> +** <> +** <> +* Control stage +** <> + +The following sections outline the pipeline-specific modules + +[[mor1kx_fetch_espresso]] +mor1kx_fetch_espresso +^^^^^^^^^^^^^^^^^^^^^ + +This is the fetch stage for the espresso pipeline. + +It is tightly coupled with the control stage. + +The block attempts to stream in bursts from the bus interface. + +The block outputs register addresses for the next read from the RF. + +[[mor1kx_lsu_espresso]] +mor1kx_lsu_espresso +^^^^^^^^^^^^^^^^^^^ + +A LSU specific to the espresso pipeline. Its features are similar to the +<> block. + +[[mor1kx_wb_mux_espresso]] +mor1kx_wb_mux_espresso +^^^^^^^^^^^^^^^^^^^^^^ + +Writeback stage mux for the espresso pipeline. Similar to the +<> block. + +[[mor1kx_rf_espresso]] +mor1kx_rf_espresso +^^^^^^^^^^^^^^^^^^ + +Register file for the espresso pipeline. Simlar to the +<> block. + +[[mor1kx_ctrl_espresso]] +mor1kx_ctrl_espresso +^^^^^^^^^^^^^^^^^^^^ + +This module contains a lot of the core functionality of the pipeline, such as: + +* SPRs (NPC, PPC, etc.) and accesses to them +* PIC +* Debug unit +* Tick timer +* Pipeline control signals +** Advance/stall signaling to each pipeline stage +** Exception handling +** Branch indication to fetch stage +** Register file write enable + + +Pronto Espresso pipeline +~~~~~~~~~~~~~~~~~~~~~~~~ + +The pronto espresso pipeline essentially contains two stages: a fetch and "the-rest" +stages. It is based on the Espresso pipeline, but does not have a delay slot on jumps +and branches. As such, it reuses a lot of Espresso's pipeline. + +No support for caches. + +It has _no_ delay slot. + +Pipeline consists of the following modules: + +* Fetch: +** <> +* Decode +** <> +* Execute/memory stage +** <> +** <> +** <> +** <> +* Control stage +** <> + +The following sections outline the pipeline-specific modules + +[[mor1kx_fetch_prontoespresso]] +mor1kx_fetch_prontoespresso +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This is the fetch stage for the pronto espresso pipeline + +It is tightly coupled with the control stage. + +The block attempts to stream in bursts from the bus interface. + +The block outputs register addresses for the next read from the RF. + +It takes into account that the pipeline does not support a delay slot on jumps/branches. + +[[mor1kx_ctrl_prontoespresso]] +mor1kx_ctrl_prontoespresso +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This module contains a lot of the core functionality of the pipeline, such as: + +* SPRs (NPC, PPC, etc.) and accesses to them +* PIC +* Debug unit +* Tick timer +* Pipeline control signals +** Advance/stall signaling to each pipeline stage +** Exception handling +** Branch indication to fetch stage +** Register file write enable + +It is based on the espresso pipeline, however is modified in such a way as to make sure it doesn't have a delay slot on branches. + +Components +---------- + +[[mor1kx_bus_if_wb32]] +mor1kx_bus_if_wb32 +~~~~~~~~~~~~~~~~~~ + +This module is a Wishbone bus interface block and sits between the pipeline's +fetch and load/store units and the Wishbone bus. + +It is Wishbone version B3 compliant and can perform burst reads. + +At present there are two configurations of the block, one is "classic" +configuration and the other is "B3 read bursting". + +The "classic" configuration performs all access as single cycle reads or +writes to the bus. + +The "B3 read bursting" mode will perform burst reads over the bus, but writes +are still single cycle accesses. + +[[mor1kx_cpu]] +mor1kx_cpu +~~~~~~~~~~ + +The CPU pipeline wrapper layer. This selects the appropriate pipeline CPU +implementation toplevel. + +Additionally, some signals intended to be used as hooks for monitor modules are +provided. + +[[mor1kx_decode]] +mor1kx_decode +~~~~~~~~~~~~~ + +This is a generic OR1K decode stage module, which can ideally be reused by each +CPU implementation. + +The module can either register the its decode output or be wholly combinatorial. + +It generates ALU, LSU and control operation signals for the remainder of the pipeline +units. Exceptions caused in this stage (ie, illegal instruction, system call etc.) or +earlier (fetch stage exceptions like bus error) are also generated or passed through. + +[[mor1kx_execute_alu]] +mor1kx_execute_alu +~~~~~~~~~~~~~~~~~~ + +This is a generic ALU implementation. It contains all of the integer arithmetic and +logical operations which are supported in the ORBIS32 instruction set. + +The following features are optional. All can be disabled, or enabled with the +implementation options listed, if any: + +* Multiplier +** Three stage, three cycle, full 32-bit parallel multiplier +** Serial, 32-cycle serial multiplication implementation +** Simulation, single cycle multiplication, not advisable for synthesis +* Divider +** Serial, 32-cycle serial division implementation +** Simulation, single cycle division, not synthesisable +* Shift-right-arithmetic +* Rotate right +* Shift instructions, logical shift left and right, and shift right arithmetic and rotate right can be chosen to be implemented in a single-cycle barrel shifter implementation or done serially to save implementation area. +* Conditional move +* Find first and last '1' + +The following is not yet supported: + +* Add with carry +* Sign extension instructions + +The module also implements comparison logic for the set flag instructions. + + +[[mor1kx_icache]] +mor1kx_icache +~~~~~~~~~~~~~ + +Instruction cache module. + +[[mor1kx_dcache]] +mor1kx_dcache +~~~~~~~~~~~~~ + +Data cache module. + + +[[mor1kx_immu]] +mor1kx_immu +~~~~~~~~~~~ + +Instruction memory management module. + +[[mor1kx_dmmu]] +mor1kx_dmmu +~~~~~~~~~~~ + +Data memory management module. + +[[mor1kx_rf_ram]] +mor1kx_rf_ram +~~~~~~~~~~~~~ + +[[mor1kx_spram]] +mor1kx_spram +~~~~~~~~~~~~ + +Generic single port ram with seperate read and write addresses. + +Has explicit bypass logic to correctly present write-first behaviour on +different platforms. + +[[mor1kx_dpram_sclk]] +mor1kx_dpram_sclk +~~~~~~~~~~~~~~~~~ + +Generic single clocked dual port ram. diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-defines.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-defines.v new file mode 100644 index 0000000..b93f362 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-defines.v @@ -0,0 +1,267 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx defines + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +/* ORBIS32 opcodes - top 6 bits */ + +`define OR1K_INSN_WIDTH 32 + +`define OR1K_RD_SELECT 25:21 +`define OR1K_RA_SELECT 20:16 +`define OR1K_RB_SELECT 15:11 + +`define OR1K_IMM_WIDTH 16 +`define OR1K_IMM_SELECT 15:0 + +`define OR1K_ALU_OPC_WIDTH 4 +`define OR1K_ALU_OPC_SELECT 3:0 + +`define OR1K_ALU_OPC_ADD `OR1K_ALU_OPC_WIDTH'h0 +`define OR1K_ALU_OPC_ADDC `OR1K_ALU_OPC_WIDTH'h1 +`define OR1K_ALU_OPC_SUB `OR1K_ALU_OPC_WIDTH'h2 +`define OR1K_ALU_OPC_AND `OR1K_ALU_OPC_WIDTH'h3 +`define OR1K_ALU_OPC_OR `OR1K_ALU_OPC_WIDTH'h4 +`define OR1K_ALU_OPC_XOR `OR1K_ALU_OPC_WIDTH'h5 +`define OR1K_ALU_OPC_MUL `OR1K_ALU_OPC_WIDTH'h6 +`define OR1K_ALU_OPC_RESV `OR1K_ALU_OPC_WIDTH'h7 +`define OR1K_ALU_OPC_SHRT `OR1K_ALU_OPC_WIDTH'h8 +`define OR1K_ALU_OPC_DIV `OR1K_ALU_OPC_WIDTH'h9 +`define OR1K_ALU_OPC_DIVU `OR1K_ALU_OPC_WIDTH'ha +`define OR1K_ALU_OPC_MULU `OR1K_ALU_OPC_WIDTH'hb +`define OR1K_ALU_OPC_EXTBH `OR1K_ALU_OPC_WIDTH'hc +`define OR1K_ALU_OPC_EXTW `OR1K_ALU_OPC_WIDTH'hd +`define OR1K_ALU_OPC_CMOV `OR1K_ALU_OPC_WIDTH'he +`define OR1K_ALU_OPC_FFL1 `OR1K_ALU_OPC_WIDTH'hf + +`define OR1K_ALU_OPC_SECONDARY_WIDTH 3 +`define OR1K_ALU_OPC_SECONDARY_SELECT 8:6 + +`define OR1K_ALU_OPC_SECONDARY_SHRT_SLL `OR1K_ALU_OPC_SECONDARY_WIDTH'h0 +`define OR1K_ALU_OPC_SECONDARY_SHRT_SRL `OR1K_ALU_OPC_SECONDARY_WIDTH'h1 +`define OR1K_ALU_OPC_SECONDARY_SHRT_SRA `OR1K_ALU_OPC_SECONDARY_WIDTH'h2 +`define OR1K_ALU_OPC_SECONDARY_SHRT_ROR `OR1K_ALU_OPC_SECONDARY_WIDTH'h3 + +`define OR1K_COMP_OPC_WIDTH 4 +`define OR1K_COMP_OPC_SELECT 24:21 +`define OR1K_COMP_OPC_EQ `OR1K_COMP_OPC_WIDTH'h0 +`define OR1K_COMP_OPC_NE `OR1K_COMP_OPC_WIDTH'h1 +`define OR1K_COMP_OPC_GTU `OR1K_COMP_OPC_WIDTH'h2 +`define OR1K_COMP_OPC_GEU `OR1K_COMP_OPC_WIDTH'h3 +`define OR1K_COMP_OPC_LTU `OR1K_COMP_OPC_WIDTH'h4 +`define OR1K_COMP_OPC_LEU `OR1K_COMP_OPC_WIDTH'h5 +`define OR1K_COMP_OPC_GTS `OR1K_COMP_OPC_WIDTH'ha +`define OR1K_COMP_OPC_GES `OR1K_COMP_OPC_WIDTH'hb +`define OR1K_COMP_OPC_LTS `OR1K_COMP_OPC_WIDTH'hc +`define OR1K_COMP_OPC_LES `OR1K_COMP_OPC_WIDTH'hd + +`define OR1K_JUMPBRANCH_IMMEDIATE_SELECT 25:0 + +`define OR1K_SYSTRAPSYNC_OPC_WIDTH 3 +`define OR1K_SYSTRAPSYNC_OPC_SELECT 25:23 +`define OR1K_SYSTRAPSYNC_OPC_SYSCALL `OR1K_SYSTRAPSYNC_OPC_WIDTH'h0 +`define OR1K_SYSTRAPSYNC_OPC_TRAP `OR1K_SYSTRAPSYNC_OPC_WIDTH'h2 +`define OR1K_SYSTRAPSYNC_OPC_MSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h4 +`define OR1K_SYSTRAPSYNC_OPC_PSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h5 +`define OR1K_SYSTRAPSYNC_OPC_CSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h6 + +`define OR1K_OPCODE_WIDTH 6 +`define OR1K_OPCODE_SELECT 31:26 + +`define OR1K_OPCODE_J {2'b00, 4'h0} +`define OR1K_OPCODE_JAL {2'b00, 4'h1} +`define OR1K_OPCODE_BNF {2'b00, 4'h3} +`define OR1K_OPCODE_BF {2'b00, 4'h4} +`define OR1K_OPCODE_NOP {2'b00, 4'h5} +`define OR1K_OPCODE_MOVHI {2'b00, 4'h6} +`define OR1K_OPCODE_MACRC {2'b00, 4'h6} + +/* +`define OR1K_OPCODE_SYS {2'b00, 4'h8} +`define OR1K_OPCODE_TRAP {2'b00, 4'h8} +`define OR1K_OPCODE_MSYNC {2'b00, 4'h8} +`define OR1K_OPCODE_PSYNC {2'b00, 4'h8} +`define OR1K_OPCODE_CSYNC {2'b00, 4'h8} + */ +`define OR1K_OPCODE_SYSTRAPSYNC {2'b00, 4'h8} +`define OR1K_OPCODE_RFE {2'b00, 4'h9} + +`define OR1K_OPCODE_JR {2'b01, 4'h1} +`define OR1K_OPCODE_JALR {2'b01, 4'h2} +`define OR1K_OPCODE_MACI {2'b01, 4'h3} +`define OR1K_OPCODE_LWA {2'b01, 4'hB} +`define OR1K_OPCODE_CUST1 {2'b01, 4'hC} +`define OR1K_OPCODE_CUST2 {2'b01, 4'hD} +`define OR1K_OPCODE_CUST3 {2'b01, 4'hE} +`define OR1K_OPCODE_CUST4 {2'b01, 4'hF} + +`define OR1K_OPCODE_LD {2'b10, 4'h0} +`define OR1K_OPCODE_LWZ {2'b10, 4'h1} +`define OR1K_OPCODE_LWS {2'b10, 4'h2} +`define OR1K_OPCODE_LBZ {2'b10, 4'h3} +`define OR1K_OPCODE_LBS {2'b10, 4'h4} +`define OR1K_OPCODE_LHZ {2'b10, 4'h5} +`define OR1K_OPCODE_LHS {2'b10, 4'h6} + +`define OR1K_OPCODE_ADDI {2'b10, 4'h7} +`define OR1K_OPCODE_ADDIC {2'b10, 4'h8} +`define OR1K_OPCODE_ANDI {2'b10, 4'h9} +`define OR1K_OPCODE_ORI {2'b10, 4'hA} +`define OR1K_OPCODE_XORI {2'b10, 4'hB} +`define OR1K_OPCODE_MULI {2'b10, 4'hC} +`define OR1K_OPCODE_MFSPR {2'b10, 4'hD} +/* +`define OR1K_OPCODE_SLLI {2'b10, 4'hE} +`define OR1K_OPCODE_SRLI {2'b10, 4'hE} +`define OR1K_OPCODE_SRAI {2'b10, 4'hE} +`define OR1K_OPCODE_RORI {2'b10, 4'hE} +*/ +`define OR1K_OPCODE_SHRTI {2'b10, 4'hE} + +/* +`define OR1K_OPCODE_SFEQI {2'b10, 4'hF} +`define OR1K_OPCODE_SFNEI {2'b10, 4'hF} +`define OR1K_OPCODE_SFGTUI {2'b10, 4'hF} +`define OR1K_OPCODE_SFGEUI {2'b10, 4'hF} +`define OR1K_OPCODE_SFLTUI {2'b10, 4'hF} +`define OR1K_OPCODE_SFLEUI {2'b10, 4'hF} +`define OR1K_OPCODE_SFGTSI {2'b10, 4'hF} +`define OR1K_OPCODE_SFGESI {2'b10, 4'hF} +`define OR1K_OPCODE_SFLTSI {2'b10, 4'hF} +`define OR1K_OPCODE_SFLESI {2'b10, 4'hF} +*/ +`define OR1K_OPCODE_SFIMM {2'b10, 4'hF} + +`define OR1K_OPCODE_MTSPR {2'b11, 4'h0} +`define OR1K_OPCODE_MAC {2'b11, 4'h1} +`define OR1K_OPCODE_MSB {2'b11, 4'h1} + +`define OR1K_OPCODE_SWA {2'b11, 4'h3} +`define OR1K_OPCODE_SD {2'b11, 4'h4} +`define OR1K_OPCODE_SW {2'b11, 4'h5} +`define OR1K_OPCODE_SB {2'b11, 4'h6} +`define OR1K_OPCODE_SH {2'b11, 4'h7} + +/* +`define OR1K_OPCODE_ADD {2'b11, 4'h8} +`define OR1K_OPCODE_ADDC {2'b11, 4'h8} +`define OR1K_OPCODE_SUB {2'b11, 4'h8} +`define OR1K_OPCODE_AND {2'b11, 4'h8} +`define OR1K_OPCODE_OR {2'b11, 4'h8} +`define OR1K_OPCODE_XOR {2'b11, 4'h8} +`define OR1K_OPCODE_MUL {2'b11, 4'h8} + +`define OR1K_OPCODE_SLL {2'b11, 4'h8} +`define OR1K_OPCODE_SRL {2'b11, 4'h8} +`define OR1K_OPCODE_SRA {2'b11, 4'h8} +`define OR1K_OPCODE_ROR {2'b11, 4'h8} +`define OR1K_OPCODE_DIV {2'b11, 4'h8} +`define OR1K_OPCODE_DIVU {2'b11, 4'h8} +`define OR1K_OPCODE_MULU {2'b11, 4'h8} +`define OR1K_OPCODE_EXTBS {2'b11, 4'h8} +`define OR1K_OPCODE_EXTHS {2'b11, 4'h8} +`define OR1K_OPCODE_EXTWS {2'b11, 4'h8} +`define OR1K_OPCODE_EXTBZ {2'b11, 4'h8} +`define OR1K_OPCODE_EXTHZ {2'b11, 4'h8} +`define OR1K_OPCODE_EXTWZ {2'b11, 4'h8} +`define OR1K_OPCODE_CMOV {2'b11, 4'h8} +`define OR1K_OPCODE_FF1 {2'b11, 4'h8} +`define OR1K_OPCODE_FL1 {2'b11, 4'h8} +*/ +`define OR1K_OPCODE_ALU {2'b11, 4'h8} + +/* +`define OR1K_OPCODE_SFEQ {2'b11, 4'h9} +`define OR1K_OPCODE_SFNE {2'b11, 4'h9} +`define OR1K_OPCODE_SFGTU {2'b11, 4'h9} +`define OR1K_OPCODE_SFGEU {2'b11, 4'h9} +`define OR1K_OPCODE_SFLTU {2'b11, 4'h9} +`define OR1K_OPCODE_SFLEU {2'b11, 4'h9} +`define OR1K_OPCODE_SFGTS {2'b11, 4'h9} +`define OR1K_OPCODE_SFGES {2'b11, 4'h9} +`define OR1K_OPCODE_SFLTS {2'b11, 4'h9} +`define OR1K_OPCODE_SFLES {2'b11, 4'h9} +*/ +`define OR1K_OPCODE_SF {2'b11, 4'h9} + +`define OR1K_OPCODE_CUST5 {2'b11, 4'hC} +`define OR1K_OPCODE_CUST6 {2'b11, 4'hD} +`define OR1K_OPCODE_CUST7 {2'b11, 4'hE} +`define OR1K_OPCODE_CUST8 {2'b11, 4'hF} + +// +// ORFPX32 opcodes +// +`define OR1K_OPCODE_FPU {2'b11, 4'h2} +// FP OPs +// MSbit indicates FPU operation valid +`define OR1K_FPUOP_WIDTH 8 +`define OR1K_FPUOP_SELECT 7:0 +// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles +`define OR1K_FPUOP_CYCLES 3'd4 +// FP instruction is double precision if bit 4 is set. We're a 32-bit +// implementation thus do not support double precision FP +`define OR1K_FPUOP_DOUBLE_BIT 4 +`define OR1K_FPUOP_ADD 8'b0000_0000 +`define OR1K_FPUOP_SUB 8'b0000_0001 +`define OR1K_FPUOP_MUL 8'b0000_0010 +`define OR1K_FPUOP_DIV 8'b0000_0011 +`define OR1K_FPUOP_ITOF 8'b0000_0100 +`define OR1K_FPUOP_FTOI 8'b0000_0101 +`define OR1K_FPUOP_REM 8'b0000_0110 +`define OR1K_FPUOP_RESERVED 8'b0000_0111 +// FP Compare instructions +`define OR1K_FPCOP_SFEQ 8'b0000_1000 +`define OR1K_FPCOP_SFNE 8'b0000_1001 +`define OR1K_FPCOP_SFGT 8'b0000_1010 +`define OR1K_FPCOP_SFGE 8'b0000_1011 +`define OR1K_FPCOP_SFLT 8'b0000_1100 +`define OR1K_FPCOP_SFLE 8'b0000_1101 + + +// +// OR1K SPR defines +// +`include "mor1kx-sprs.v" + +/* Exception addresses */ +`define OR1K_RESET_VECTOR 5'h01 +`define OR1K_BERR_VECTOR 5'h02 +`define OR1K_DPF_VECTOR 5'h03 +`define OR1K_IPF_VECTOR 5'h04 +`define OR1K_TT_VECTOR 5'h05 +`define OR1K_ALIGN_VECTOR 5'h06 +`define OR1K_ILLEGAL_VECTOR 5'h07 +`define OR1K_INT_VECTOR 5'h08 +`define OR1K_DTLB_VECTOR 5'h09 +`define OR1K_ITLB_VECTOR 5'h0a +`define OR1K_RANGE_VECTOR 5'h0b +`define OR1K_SYSCALL_VECTOR 5'h0c +`define OR1K_FP_VECTOR 5'h0d +`define OR1K_TRAP_VECTOR 5'h0e + +// Whether we'll allow things using AYNC reset to have it: +//`define OR_ASYNC_RST or posedge rst +`define OR_ASYNC_RST + +// Implementation version defines +`define MOR1KX_CPUID 8'h01 +// mor1kx breaks up the VR2 version register to be 3 8-bit fields +// MSB is major version, middle byte is minor version number +// and final byte is the pipeline identifier. +`define MOR1KX_VERSION_MAJOR 8'd4 +`define MOR1KX_VERSION_MINOR 8'd1 + +// mor1kx implementation-specific register definitions +`define MOR1KX_PIPEID_CAPPUCCINO 8'd1 +`define MOR1KX_PIPEID_ESPRESSO 8'd2 +`define MOR1KX_PIPEID_PRONTOESPRESSO 8'd3 diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-sprs.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-sprs.v new file mode 100644 index 0000000..32c3487 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-sprs.v @@ -0,0 +1,344 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: SPR definitions + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ +`define SPR_BASE(x) (x/(2**11)) +`define SPR_OFFSET(x) (x%(2**11)) + +// +// Addresses +// +`define OR1K_SPR_SYS_BASE {5'd0} +`define OR1K_SPR_VR_ADDR {5'd0,11'd0} +`define OR1K_SPR_UPR_ADDR {5'd0,11'd1} +`define OR1K_SPR_CPUCFGR_ADDR {5'd0,11'd2} +`define OR1K_SPR_DMMUCFGR_ADDR {5'd0,11'd3} +`define OR1K_SPR_IMMUCFGR_ADDR {5'd0,11'd4} +`define OR1K_SPR_DCCFGR_ADDR {5'd0,11'd5} +`define OR1K_SPR_ICCFGR_ADDR {5'd0,11'd6} +`define OR1K_SPR_DCFGR_ADDR {5'd0,11'd7} +`define OR1K_SPR_PCCFGR_ADDR {5'd0,11'd8} +`define OR1K_SPR_VR2_ADDR {5'd0,11'd9} +`define OR1K_SPR_AVR_ADDR {5'd0,11'd10} +`define OR1K_SPR_EVBAR_ADDR {5'd0,11'd11} +`define OR1K_SPR_AECR_ADDR {5'd0,11'd12} +`define OR1K_SPR_AESR_ADDR {5'd0,11'd13} +`define OR1K_SPR_NPC_ADDR {5'd0,11'd16} +`define OR1K_SPR_SR_ADDR {5'd0,11'd17} +`define OR1K_SPR_PPC_ADDR {5'd0,11'd18} +`define OR1K_SPR_FPCSR_ADDR {5'd0,11'd20} +`define OR1K_SPR_ISR0_ADDR {5'd0,11'd21} +`define OR1K_SPR_EPCR0_ADDR {5'd0,11'd32} +`define OR1K_SPR_EEAR0_ADDR {5'd0,11'd48} +`define OR1K_SPR_ESR0_ADDR {5'd0,11'd64} +`define OR1K_SPR_COREID_ADDR {5'd0,11'd128} +`define OR1K_SPR_NUMCORES_ADDR {5'd0,11'd129} +`define OR1K_SPR_GPR0_ADDR {5'd0,11'd1024} + +`define OR1K_SPR_DMMU_BASE {5'd1} +`define OR1K_SPR_DMMUCR_ADDR {5'd1,11'd0} +`define OR1K_SPR_DMMUPR_ADDR {5'd1,11'd1} +`define OR1K_SPR_DTLBEIR_ADDR {5'd1,11'd2} +`define OR1K_SPR_DATBMR0_ADDR {5'd1,11'd4} +`define OR1K_SPR_DATBTR0_ADDR {5'd1,11'd8} +`define OR1K_SPR_DTLBW0MR0_ADDR {5'd1,11'd512} +`define OR1K_SPR_DTLBW0TR0_ADDR {5'd1,11'd640} +`define OR1K_SPR_DTLBW1MR0_ADDR {5'd1,11'd768} +`define OR1K_SPR_DTLBW1TR0_ADDR {5'd1,11'd896} +`define OR1K_SPR_DTLBW2MR0_ADDR {5'd1,11'd1024} +`define OR1K_SPR_DTLBW2TR0_ADDR {5'd1,11'd1152} +`define OR1K_SPR_DTLBW3MR0_ADDR {5'd1,11'd1280} +`define OR1K_SPR_DTLBW3TR0_ADDR {5'd1,11'd1408} + +`define OR1K_SPR_IMMU_BASE {5'd2} +`define OR1K_SPR_IMMUCR_ADDR {5'd2,11'd0} +`define OR1K_SPR_IMMUPR_ADDR {5'd2,11'd1} +`define OR1K_SPR_ITLBEIR_ADDR {5'd2,11'd2} +`define OR1K_SPR_IATBMR0_ADDR {5'd2,11'd4} +`define OR1K_SPR_IATBTR0_ADDR {5'd2,11'd8} +`define OR1K_SPR_ITLBW0MR0_ADDR {5'd2,11'd512} +`define OR1K_SPR_ITLBW0TR0_ADDR {5'd2,11'd640} +`define OR1K_SPR_ITLBW1MR0_ADDR {5'd2,11'd768} +`define OR1K_SPR_ITLBW1TR0_ADDR {5'd2,11'd896} +`define OR1K_SPR_ITLBW2MR0_ADDR {5'd2,11'd1024} +`define OR1K_SPR_ITLBW2TR0_ADDR {5'd2,11'd1152} +`define OR1K_SPR_ITLBW3MR0_ADDR {5'd2,11'd1280} +`define OR1K_SPR_ITLBW3TR0_ADDR {5'd2,11'd1408} + +`define OR1K_SPR_DC_BASE {5'd3} +`define OR1K_SPR_DCCR_ADDR {5'd3,11'd0} +`define OR1K_SPR_DCBPR_ADDR {5'd3,11'd1} +`define OR1K_SPR_DCBFR_ADDR {5'd3,11'd2} +`define OR1K_SPR_DCBIR_ADDR {5'd3,11'd3} +`define OR1K_SPR_DCBWR_ADDR {5'd3,11'd4} +`define OR1K_SPR_DCBLR_ADDR {5'd3,11'd5} + +`define OR1K_SPR_IC_BASE {5'd4} +`define OR1K_SPR_ICCR_ADDR {5'd4,11'd0} +`define OR1K_SPR_ICBPR_ADDR {5'd4,11'd1} +`define OR1K_SPR_ICBIR_ADDR {5'd4,11'd2} +`define OR1K_SPR_ICBLR_ADDR {5'd4,11'd3} + +`define OR1K_SPR_MAC_BASE {5'd5} +`define OR1K_SPR_MACLO_ADDR {5'd5,11'd1} +`define OR1K_SPR_MACHI_ADDR {5'd5,11'd2} + +`define OR1K_SPR_DU_BASE {5'd6} +`define OR1K_SPR_DVR0_ADDR {5'd6,11'd0} +`define OR1K_SPR_DCR0_ADDR {5'd6,11'd8} +`define OR1K_SPR_DMR1_ADDR {5'd6,11'd16} +`define OR1K_SPR_DMR2_ADDR {5'd6,11'd17} +`define OR1K_SPR_DCWR0_ADDR {5'd6,11'd18} +`define OR1K_SPR_DSR_ADDR {5'd6,11'd20} +`define OR1K_SPR_DRR_ADDR {5'd6,11'd21} + +`define OR1K_SPR_PC_BASE {5'd7} +`define OR1K_SPR_PCCR0_ADDR {5'd7,11'd0} +`define OR1K_SPR_PCMR0_ADDR {5'd7,11'd8} + +`define OR1K_SPR_PM_BASE {5'd8} +`define OR1K_SPR_PMR_ADDR {5'd8,11'd0} + +`define OR1K_SPR_PIC_BASE {5'd9} +`define OR1K_SPR_PICMR_ADDR {5'd9,11'd0} +`define OR1K_SPR_PICSR_ADDR {5'd9,11'd2} + +`define OR1K_SPR_TT_BASE {5'd10} +`define OR1K_SPR_TTMR_ADDR {5'd10,11'd0} +`define OR1K_SPR_TTCR_ADDR {5'd10,11'd1} + +`define OR1K_SPR_FPU_BASE {5'd11} + +// +// Register bit defines +// + +// Supervision Register +`define OR1K_SPR_SR_SM 0 /* Supervisor mode */ +`define OR1K_SPR_SR_TEE 1 /* Timer exception enable */ +`define OR1K_SPR_SR_IEE 2 /* Interrupt exception enable */ +`define OR1K_SPR_SR_DCE 3 /* Data cache enable */ +`define OR1K_SPR_SR_ICE 4 /* Instruction cache enable */ +`define OR1K_SPR_SR_DME 5 /* Data MMU enable */ +`define OR1K_SPR_SR_IME 6 /* Instruction MMU enable */ +`define OR1K_SPR_SR_LEE 7 /* Little-endian enable */ +`define OR1K_SPR_SR_CE 8 /* CID enable */ +`define OR1K_SPR_SR_F 9 /* Flag */ +`define OR1K_SPR_SR_CY 10 /* Carry flag */ +`define OR1K_SPR_SR_OV 11 /* Overflow flag */ +`define OR1K_SPR_SR_OVE 12 /* Overflow exception enable */ +`define OR1K_SPR_SR_DSX 13 /* Delay slot exception */ +`define OR1K_SPR_SR_EPH 14 /* Exception prefix high */ +`define OR1K_SPR_SR_FO 15 /* Fixed to one */ +`define OR1K_SPR_SR_SUMRA 16 /* SPR user read mode access */ +`define OR1K_SPR_SR_RESERVED 27:17 /* Reserved */ +`define OR1K_SPR_SR_CID 31:28 /* Context ID */ + +// Version register - DEPRECATED +`define OR1K_SPR_VR_REV 5:0 /* Revision */ +`define OR1K_SPR_VR_UVRP 6 /* Updated Version Registers Present */ +`define OR1K_SPR_VR_RESERVED 15:7 /* Reserved */ +`define OR1K_SPR_VR_CFG 23:16 /* Configuration Template */ +`define OR1K_SPR_VR_VER 31:24 /* Version */ + + +// Unit Present register +`define OR1K_SPR_UPR_UP 0 +`define OR1K_SPR_UPR_DCP 1 +`define OR1K_SPR_UPR_ICP 2 +`define OR1K_SPR_UPR_DMP 3 +`define OR1K_SPR_UPR_IMP 4 +`define OR1K_SPR_UPR_MP 5 +`define OR1K_SPR_UPR_DUP 6 +`define OR1K_SPR_UPR_PCUP 7 +`define OR1K_SPR_UPR_PICP 8 +`define OR1K_SPR_UPR_PMP 9 +`define OR1K_SPR_UPR_TTP 10 +`define OR1K_SPR_UPR_RESERVED 23:11 +`define OR1K_SPR_UPR_CUP 31:24 + +// CPU Configuration register +`define OR1K_SPR_CPUCFGR_NSGF 3:0 /* Number of shadow GPRs */ +`define OR1K_SPR_CPUCFGR_CFG 4 +`define OR1K_SPR_CPUCFGR_OB32S 5 +`define OR1K_SPR_CPUCFGR_OB64S 6 +`define OR1K_SPR_CPUCFGR_OF32S 7 +`define OR1K_SPR_CPUCFGR_OF64S 8 +`define OR1K_SPR_CPUCFGR_OV64S 9 +`define OR1K_SPR_CPUCFGR_ND 10 /* No delay-slot implementation */ +`define OR1K_SPR_CPUCFGR_AVRP 11 /* Arch. version registers */ +`define OR1K_SPR_CPUCFGR_EVBARP 12 /* Exception vector base addr reg */ +`define OR1K_SPR_CPUCFGR_ISRP 13 /* Implementation specific regs */ +`define OR1K_SPR_CPUCFGR_AECSRP 14 /* Arith. exception regs */ +`define OR1K_SPR_CPUCFGR_RESERVED 31:15 + +// Version register 2 (new with OR1K 1.0) +`define OR1K_SPR_VR2_VER 23:0 +`define OR1K_SPR_VR2_CPUID 31:24 + +// Architecture Version register +`define OR1K_SPR_AVR_RESERVED 7:0 +`define OR1K_SPR_AVR_REV 15:8 +`define OR1K_SPR_AVR_MIN 23:16 +`define OR1K_SPR_AVR_MAJ 31:24 + +// Exception Vector Base Address register +`define OR1K_SPR_EVBAR_RESERVED 12:0 +`define OR1K_SPR_EVBAR_EVBA 31:13 + +// Arithmetic Exception Control register +`define OR1K_SPR_AECR_CYADDE 0 +`define OR1K_SPR_AECR_OVADDE 1 +`define OR1K_SPR_AECR_CYMULE 2 +`define OR1K_SPR_AECR_OVMULE 3 +`define OR1K_SPR_AECR_DBZE 4 +`define OR1K_SPR_AECR_CYMACADDE 5 +`define OR1K_SPR_AECR_OVMACADDE 6 +`define OR1K_SPR_AECR_RESERVED 31:7 + +// Arithmetic Exception Status register +`define OR1K_SPR_AESR_CYADDE 0 +`define OR1K_SPR_AESR_OVADDE 1 +`define OR1K_SPR_AESR_CYMULE 2 +`define OR1K_SPR_AESR_OVMULE 3 +`define OR1K_SPR_AESR_DBZE 4 +`define OR1K_SPR_AESR_CYMACADDE 5 +`define OR1K_SPR_AESR_OVMACADDE 6 +`define OR1K_SPR_AESR_RESERVED 31:7 + +// Tick timer registers +`define OR1K_SPR_TTMR_TP 27:0 /* Time period */ +`define OR1K_SPR_TTMR_IP 28 /* Interrupt pending */ +`define OR1K_SPR_TTMR_IE 29 /* Interrupt enable */ +`define OR1K_SPR_TTMR_M 31:30 /* Mode */ +// Tick timer mode values +`define OR1K_SPR_TTMR_M_DIS 2'b00 /* Disabled */ +`define OR1K_SPR_TTMR_M_RST 2'b01 /* Restart-on-match mode */ +`define OR1K_SPR_TTMR_M_STP 2'b10 /* Stop-on-match mode */ +`define OR1K_SPR_TTMR_M_CNT 2'b11 /* Continue counting mode */ + +// Data Cache Configuration register +`define OR1K_SPR_DCCFGR_NCW 2:0 /* Number of Cache Ways */ +`define OR1K_SPR_DCCFGR_NCS 6:3 /* Number of Cache Sets */ +`define OR1K_SPR_DCCFGR_CBS 7 /* Cache Block Size */ +`define OR1K_SPR_DCCFGR_CWS 8 /* Cache Write Strategy */ +`define OR1K_SPR_DCCFGR_CCRI 9 /* Cache Control Register Implemented */ +`define OR1K_SPR_DCCFGR_CBIRI 10 /* Cache Block Invalidate Register Implemented */ +`define OR1K_SPR_DCCFGR_CBPRI 11 /* Cache Block Prefetch Register Implemented */ +`define OR1K_SPR_DCCFGR_CBLRI 12 /* Cache Block Lock Register Implemented */ +`define OR1K_SPR_DCCFGR_CBFRI 13 /* Cache Block Flush Register Implemented */ +`define OR1K_SPR_DCCFGR_CBWBRI 14 /* Cache Block Write-Back Register Implemented */ + +// Instruction Cache Configuration register +`define OR1K_SPR_ICCFGR_NCW 2:0 /* Number of Cache Ways */ +`define OR1K_SPR_ICCFGR_NCS 6:3 /* Number of Cache Sets */ +`define OR1K_SPR_ICCFGR_CBS 7 /* Cache Block Size */ +`define OR1K_SPR_ICCFGR_CCRI 9 /* Cache Control Register Implemented */ +`define OR1K_SPR_ICCFGR_CBIRI 10 /* Cache Block Invalidate Register Implemented */ +`define OR1K_SPR_ICCFGR_CBPRI 11 /* Cache Block Prefetch Register Implemented */ +`define OR1K_SPR_ICCFGR_CBLRI 12 /* Cache Block Lock Register Implemented */ + +// Data MMU Configuration register +`define OR1K_SPR_DMMUFGR_NTW 1:0 /* Number of TLB ways */ +`define OR1K_SPR_DMMUFGR_NTS 4:2 /* Number of TLB sets */ +`define OR1K_SPR_DMMUFGR_NAE 7:5 /* Number of ATB entries */ +`define OR1K_SPR_DMMUFGR_CRI 8 /* Control Register Implemented */ +`define OR1K_SPR_DMMUFGR_PRI 9 /* Protection Register Implemented */ +`define OR1K_SPR_DMMUFGR_TEIRI 10 /* TLB Entry Invalidate Register Implemented */ +`define OR1K_SPR_DMMUFGR_HTR 11 /* Hardware TLB Reload */ + +// Instruction MMU Configuration register +`define OR1K_SPR_IMMUFGR_NTW 1:0 /* Number of TLB ways */ +`define OR1K_SPR_IMMUFGR_NTS 4:2 /* Number of TLB sets */ +`define OR1K_SPR_IMMUFGR_NAE 7:5 /* Number of ATB entries */ +`define OR1K_SPR_IMMUFGR_CRI 8 /* Control Register Implemented */ +`define OR1K_SPR_IMMUFGR_PRI 9 /* Protection Register Implemented */ +`define OR1K_SPR_IMMUFGR_TEIRI 10 /* TLB Entry Invalidate Register Implemented */ +`define OR1K_SPR_IMMUFGR_HTR 11 /* Hardware TLB Reload */ + +// Debug Mode Register 1 +`define OR1K_SPR_DMR1_ST 22 +`define OR1K_SPR_DMR1_BT 23 + +// Debug Stop Register +`define OR1K_SPR_DSR_RSTE 0 +`define OR1K_SPR_DSR_BUSEE 1 +`define OR1K_SPR_DSR_DPFE 2 +`define OR1K_SPR_DSR_IPFE 3 +`define OR1K_SPR_DSR_TTE 4 +`define OR1K_SPR_DSR_AE 5 +`define OR1K_SPR_DSR_IIE 6 +`define OR1K_SPR_DSR_INTE 7 +`define OR1K_SPR_DSR_DME 8 +`define OR1K_SPR_DSR_IME 9 +`define OR1K_SPR_DSR_RE 10 +`define OR1K_SPR_DSR_SCE 11 +`define OR1K_SPR_DSR_FPE 12 +`define OR1K_SPR_DSR_TE 13 + +`define OR1K_SPR_DRR_RSTE 0 +`define OR1K_SPR_DRR_BUSEE 1 +`define OR1K_SPR_DRR_DPFE 2 +`define OR1K_SPR_DRR_IPFE 3 +`define OR1K_SPR_DRR_TTE 4 +`define OR1K_SPR_DRR_AE 5 +`define OR1K_SPR_DRR_IIE 6 +`define OR1K_SPR_DRR_IE 7 +`define OR1K_SPR_DRR_DME 8 +`define OR1K_SPR_DRR_IME 9 +`define OR1K_SPR_DRR_RE 10 +`define OR1K_SPR_DRR_SCE 11 +`define OR1K_SPR_DRR_FPE 12 +`define OR1K_SPR_DRR_TE 13 + +// FPCSR bits +`define OR1K_FPCSR_FPEE 0 +`define OR1K_FPCSR_RM 2:1 +`define OR1K_FPCSR_OVF 3 +`define OR1K_FPCSR_UNF 4 +`define OR1K_FPCSR_SNF 5 +`define OR1K_FPCSR_QNF 6 +`define OR1K_FPCSR_ZF 7 +`define OR1K_FPCSR_IXF 8 +`define OR1K_FPCSR_IVF 9 +`define OR1K_FPCSR_INF 10 +`define OR1K_FPCSR_DZF 11 +// FPCSR sizes of fields +`define OR1K_FPCSR_WIDTH 12 // [11:0] +`define OR1K_FPCSR_RM_SIZE 2 +`define OR1K_FPCSR_ALLF_SIZE 9 // [11:3] +// FPCSR flags +`define OR1K_FPCSR_ALLF `OR1K_FPCSR_DZF:`OR1K_FPCSR_OVF +// FPCSR reset value +`define OR1K_FPCSR_RESET_VALUE `OR1K_FPCSR_WIDTH'd1 +// FPCSR extention: maskable FPU flags. +// -vvvv- uncomment the next line to switch the extention on -vvvv- +//`define OR1K_FPCSR_MASK_FLAGS +// bits +`define OR1K_FPCSR_MASK_OVF 12 +`define OR1K_FPCSR_MASK_UNF 13 +`define OR1K_FPCSR_MASK_SNF 14 +`define OR1K_FPCSR_MASK_QNF 15 +`define OR1K_FPCSR_MASK_ZF 16 +`define OR1K_FPCSR_MASK_IXF 17 +`define OR1K_FPCSR_MASK_IVF 18 +`define OR1K_FPCSR_MASK_INF 19 +`define OR1K_FPCSR_MASK_DZF 20 +// bus select +`define OR1K_FPCSR_MASK_ALL `OR1K_FPCSR_MASK_DZF:`OR1K_FPCSR_MASK_OVF +// reset value. enables: dzf,inf,ivf,snf,ovf +`define OR1K_FPCSR_MASK_RESET_VALUE `OR1K_FPCSR_ALLF_SIZE'b1_1100_0101 + + +// Implementation-specific SPR defines +`define MOR1KX_SPR_SR_WIDTH 16 +`define MOR1KX_SPR_SR_RESET_VALUE `MOR1KX_SPR_SR_WIDTH'h8001 diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx.v new file mode 100644 index 0000000..e0f1bfe --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx.v @@ -0,0 +1,579 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx processor top level + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx + #( + parameter OPTION_OPERAND_WIDTH = 32, + + parameter OPTION_CPU0 = "CAPPUCCINO", + + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter OPTION_DCACHE_LIMIT_WIDTH = 32, + parameter OPTION_DCACHE_SNOOP = "NONE", + parameter FEATURE_DMMU = "NONE", + parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_DMMU_SET_WIDTH = 6, + parameter OPTION_DMMU_WAYS = 1, + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter OPTION_ICACHE_LIMIT_WIDTH = 32, + parameter FEATURE_IMMU = "NONE", + parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_IMMU_SET_WIDTH = 6, + parameter OPTION_IMMU_WAYS = 1, + parameter FEATURE_TIMER = "ENABLED", + parameter FEATURE_DEBUGUNIT = "NONE", + parameter FEATURE_PERFCOUNTERS = "NONE", + parameter FEATURE_MAC = "NONE", + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + + parameter FEATURE_PIC = "ENABLED", + parameter OPTION_PIC_TRIGGER = "LEVEL", + parameter OPTION_PIC_NMI_WIDTH = 0, + + parameter FEATURE_DSX = "ENABLED", + parameter FEATURE_OVERFLOW = "ENABLED", + parameter FEATURE_CARRY_FLAG = "ENABLED", + + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter OPTION_RF_CLEAR_ON_INIT = 0, + parameter OPTION_RF_NUM_SHADOW_GPR = 0, + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter OPTION_RF_WORDS = 32, + + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + + parameter FEATURE_MULTIPLIER = "THREESTAGE", + parameter FEATURE_DIVIDER = "SERIAL", + + parameter FEATURE_ADDC = "ENABLED", + parameter FEATURE_SRA = "ENABLED", + parameter FEATURE_ROR = "NONE", + parameter FEATURE_EXT = "NONE", + parameter FEATURE_CMOV = "ENABLED", + parameter FEATURE_FFL1 = "ENABLED", + parameter FEATURE_ATOMIC = "ENABLED", + + parameter FEATURE_CUST1 = "NONE", + parameter FEATURE_CUST2 = "NONE", + parameter FEATURE_CUST3 = "NONE", + parameter FEATURE_CUST4 = "NONE", + parameter FEATURE_CUST5 = "NONE", + parameter FEATURE_CUST6 = "NONE", + parameter FEATURE_CUST7 = "NONE", + parameter FEATURE_CUST8 = "NONE", + + parameter FEATURE_FPU = "NONE", // ENABLED|NONE: actual for cappuccino pipeline only + + parameter OPTION_SHIFTER = "BARREL", + + parameter FEATURE_STORE_BUFFER = "ENABLED", + parameter OPTION_STORE_BUFFER_DEPTH_WIDTH = 8, + + parameter FEATURE_MULTICORE = "NONE", + + parameter FEATURE_TRACEPORT_EXEC = "NONE", + + parameter BUS_IF_TYPE = "WISHBONE32", + + parameter IBUS_WB_TYPE = "B3_READ_BURSTING", + parameter DBUS_WB_TYPE = "CLASSIC" + ) + ( + input clk, + input rst, + + // Wishbone interface + output [31:0] iwbm_adr_o, + output iwbm_stb_o, + output iwbm_cyc_o, + output [3:0] iwbm_sel_o, + output iwbm_we_o, + output [2:0] iwbm_cti_o, + output [1:0] iwbm_bte_o, + output [31:0] iwbm_dat_o, + input iwbm_err_i, + input iwbm_ack_i, + input [31:0] iwbm_dat_i, + input iwbm_rty_i, + + output [31:0] dwbm_adr_o, + output dwbm_stb_o, + output dwbm_cyc_o, + output [3:0] dwbm_sel_o, + output dwbm_we_o, + output [2:0] dwbm_cti_o, + output [1:0] dwbm_bte_o, + output [31:0] dwbm_dat_o, + input dwbm_err_i, + input dwbm_ack_i, + input [31:0] dwbm_dat_i, + input dwbm_rty_i, + + // Avalon interface + output [31:0] avm_d_address_o, + output [3:0] avm_d_byteenable_o, + output avm_d_read_o, + input [31:0] avm_d_readdata_i, + output [3:0] avm_d_burstcount_o, + output avm_d_write_o, + output [31:0] avm_d_writedata_o, + input avm_d_waitrequest_i, + input avm_d_readdatavalid_i, + + output [31:0] avm_i_address_o, + output [3:0] avm_i_byteenable_o, + output avm_i_read_o, + input [31:0] avm_i_readdata_i, + output [3:0] avm_i_burstcount_o, + input avm_i_waitrequest_i, + input avm_i_readdatavalid_i, + + input [31:0] irq_i, + + // Debug interface + input [15:0] du_addr_i, + input du_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i, + input du_we_i, + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o, + output du_ack_o, + // Stall control from debug interface + input du_stall_i, + output du_stall_o, + + output traceport_exec_valid_o, + output [31:0] traceport_exec_pc_o, + output [`OR1K_INSN_WIDTH-1:0] traceport_exec_insn_o, + output [OPTION_OPERAND_WIDTH-1:0] traceport_exec_wbdata_o, + output [OPTION_RF_ADDR_WIDTH-1:0] traceport_exec_wbreg_o, + output traceport_exec_wben_o, + + // The multicore core identifier + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i, + // The number of cores + input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i, + + input [31:0] snoop_adr_i, + input snoop_en_i + ); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire avm_i_write_o; // From ibus_bridge of mor1kx_bus_if_avalon.v + wire avm_i_writedata_o; // From ibus_bridge of mor1kx_bus_if_avalon.v + wire [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o; // From mor1kx_cpu of mor1kx_cpu.v + wire [3:0] dbus_bsel_o; // From mor1kx_cpu of mor1kx_cpu.v + wire dbus_burst_o; // From mor1kx_cpu of mor1kx_cpu.v + wire [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o; // From mor1kx_cpu of mor1kx_cpu.v + wire dbus_req_o; // From mor1kx_cpu of mor1kx_cpu.v + wire dbus_we_o; // From mor1kx_cpu of mor1kx_cpu.v + wire [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o; // From mor1kx_cpu of mor1kx_cpu.v + wire ibus_burst_o; // From mor1kx_cpu of mor1kx_cpu.v + wire ibus_req_o; // From mor1kx_cpu of mor1kx_cpu.v + wire [15:0] spr_bus_addr_o; // From mor1kx_cpu of mor1kx_cpu.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o;// From mor1kx_cpu of mor1kx_cpu.v + wire spr_bus_stb_o; // From mor1kx_cpu of mor1kx_cpu.v + wire spr_bus_we_o; // From mor1kx_cpu of mor1kx_cpu.v + wire [15:0] spr_sr_o; // From mor1kx_cpu of mor1kx_cpu.v + // End of automatics + + wire ibus_ack_i; + wire [OPTION_OPERAND_WIDTH-1:0] ibus_dat_i; + wire ibus_err_i; + + wire dbus_ack_i; + wire [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i; + wire dbus_err_i; + + generate + if (BUS_IF_TYPE=="WISHBONE32") begin : bus_gen + + /* mor1kx_bus_if_wb32 AUTO_TEMPLATE ( + .cpu_err_o (ibus_err_i), + .cpu_ack_o (ibus_ack_i), + .cpu_dat_o (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .wbm_adr_o (iwbm_adr_o), + .wbm_stb_o (iwbm_stb_o), + .wbm_cyc_o (iwbm_cyc_o), + .wbm_sel_o (iwbm_sel_o), + .wbm_we_o (iwbm_we_o), + .wbm_cti_o (iwbm_cti_o), + .wbm_bte_o (iwbm_bte_o), + .wbm_dat_o (iwbm_dat_o), + // Inputs + .cpu_adr_i (ibus_adr_o), + .cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}), + .cpu_req_i (ibus_req_o), + .cpu_we_i (1'b0), + .cpu_bsel_i (4'b1111), + .cpu_burst_i (ibus_burst_o), + .wbm_err_i (iwbm_err_i), + .wbm_ack_i (iwbm_ack_i), + .wbm_dat_i (iwbm_dat_i), + .wbm_rty_i (iwbm_rty_i), + ); */ + + mor1kx_bus_if_wb32 + #(.BUS_IF_TYPE(IBUS_WB_TYPE), + .BURST_LENGTH((FEATURE_INSTRUCTIONCACHE != "NONE") ? + ((OPTION_ICACHE_BLOCK_WIDTH == 4) ? 4 : + ((OPTION_ICACHE_BLOCK_WIDTH == 5) ? 8 : 1)) + : 1 )) + ibus_bridge + (/*AUTOINST*/ + // Outputs + .cpu_err_o (ibus_err_i), // Templated + .cpu_ack_o (ibus_ack_i), // Templated + .cpu_dat_o (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), // Templated + .wbm_adr_o (iwbm_adr_o), // Templated + .wbm_stb_o (iwbm_stb_o), // Templated + .wbm_cyc_o (iwbm_cyc_o), // Templated + .wbm_sel_o (iwbm_sel_o), // Templated + .wbm_we_o (iwbm_we_o), // Templated + .wbm_cti_o (iwbm_cti_o), // Templated + .wbm_bte_o (iwbm_bte_o), // Templated + .wbm_dat_o (iwbm_dat_o), // Templated + // Inputs + .clk (clk), + .rst (rst), + .cpu_adr_i (ibus_adr_o), // Templated + .cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}), // Templated + .cpu_req_i (ibus_req_o), // Templated + .cpu_bsel_i (4'b1111), // Templated + .cpu_we_i (1'b0), // Templated + .cpu_burst_i (ibus_burst_o), // Templated + .wbm_err_i (iwbm_err_i), // Templated + .wbm_ack_i (iwbm_ack_i), // Templated + .wbm_dat_i (iwbm_dat_i), // Templated + .wbm_rty_i (iwbm_rty_i)); // Templated + + /* mor1kx_bus_if_wb32 AUTO_TEMPLATE ( + .cpu_err_o (dbus_err_i), + .cpu_ack_o (dbus_ack_i), + .cpu_dat_o (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .wbm_adr_o (dwbm_adr_o), + .wbm_stb_o (dwbm_stb_o), + .wbm_cyc_o (dwbm_cyc_o), + .wbm_sel_o (dwbm_sel_o), + .wbm_we_o (dwbm_we_o), + .wbm_cti_o (dwbm_cti_o), + .wbm_bte_o (dwbm_bte_o), + .wbm_dat_o (dwbm_dat_o), + // Inputs + .cpu_adr_i (dbus_adr_o[31:0]), + .cpu_dat_i (dbus_dat_o), + .cpu_req_i (dbus_req_o), + .cpu_we_i (dbus_we_o), + .cpu_bsel_i (dbus_bsel_o), + .cpu_burst_i (dbus_burst_o), + .wbm_err_i (dwbm_err_i), + .wbm_ack_i (dwbm_ack_i), + .wbm_dat_i (dwbm_dat_i), + .wbm_rty_i (dwbm_rty_i), + ); */ + + mor1kx_bus_if_wb32 + #(.BUS_IF_TYPE(DBUS_WB_TYPE), + .BURST_LENGTH((FEATURE_DATACACHE != "NONE") ? + ((OPTION_DCACHE_BLOCK_WIDTH == 4) ? 4 : + ((OPTION_DCACHE_BLOCK_WIDTH == 5) ? 8 : 1)) + : 1 )) + dbus_bridge + (/*AUTOINST*/ + // Outputs + .cpu_err_o (dbus_err_i), // Templated + .cpu_ack_o (dbus_ack_i), // Templated + .cpu_dat_o (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]), // Templated + .wbm_adr_o (dwbm_adr_o), // Templated + .wbm_stb_o (dwbm_stb_o), // Templated + .wbm_cyc_o (dwbm_cyc_o), // Templated + .wbm_sel_o (dwbm_sel_o), // Templated + .wbm_we_o (dwbm_we_o), // Templated + .wbm_cti_o (dwbm_cti_o), // Templated + .wbm_bte_o (dwbm_bte_o), // Templated + .wbm_dat_o (dwbm_dat_o), // Templated + // Inputs + .clk (clk), + .rst (rst), + .cpu_adr_i (dbus_adr_o[31:0]), // Templated + .cpu_dat_i (dbus_dat_o), // Templated + .cpu_req_i (dbus_req_o), // Templated + .cpu_bsel_i (dbus_bsel_o), // Templated + .cpu_we_i (dbus_we_o), // Templated + .cpu_burst_i (dbus_burst_o), // Templated + .wbm_err_i (dwbm_err_i), // Templated + .wbm_ack_i (dwbm_ack_i), // Templated + .wbm_dat_i (dwbm_dat_i), // Templated + .wbm_rty_i (dwbm_rty_i)); // Templated + + end else if (BUS_IF_TYPE=="AVALON") begin // block: bus_gen + /* mor1kx_bus_if_avalon AUTO_TEMPLATE ( + .cpu_err_o (ibus_err_i), + .cpu_ack_o (ibus_ack_i), + .cpu_dat_o (ibus_dat_i), + .avm_address_o (avm_i_address_o), + .avm_byteenable_o (avm_i_byteenable_o), + .avm_read_o (avm_i_read_o), + .avm_burstcount_o (avm_i_burstcount_o), + .avm_write_o (avm_i_write_o), + .avm_writedata_o (avm_i_writedata_o), + // Inputs + .cpu_adr_i (ibus_adr_o), + .cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}), + .cpu_req_i (ibus_req_o), + .cpu_we_i (1'b0), + .cpu_bsel_i (4'b1111), + .cpu_burst_i (ibus_burst_o), + .avm_readdata_i (avm_i_readdata_i), + .avm_waitrequest_i (avm_i_waitrequest_i), + .avm_readdatavalid_i (avm_i_readdatavalid_i), + ); */ + + mor1kx_bus_if_avalon + #(.OPTION_AVALON_BURST_LENGTH((1< + + ******************************************************************************/ + +`include "mor1kx-defines.v" + +module mor1kx_branch_prediction + #( + parameter OPTION_OPERAND_WIDTH = 32 + ) + ( + input clk, + input rst, + + // Signals belonging to the stage where the branch is predicted. + input op_bf_i, + input op_bnf_i, + input [9:0] immjbr_upper_i, + output predicted_flag_o, + + // Signals belonging to the stage where the branch is resolved. + input prev_op_brcond_i, + input prev_predicted_flag_i, + input flag_i, + + // Branch misprediction indicator + output branch_mispredict_o + ); + + // Compare the real flag with the previously predicted flag and signal a + // misprediction in case of a mismatch. + assign branch_mispredict_o = prev_op_brcond_i & + (flag_i != prev_predicted_flag_i); + + // Static branch prediction - backward branches are predicted as taken, + // forward branches as not taken. + assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] | + op_bnf_i & !immjbr_upper_i[9]; + +endmodule diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_avalon.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_avalon.v new file mode 100644 index 0000000..243c786 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_avalon.v @@ -0,0 +1,94 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx processor avalon bus bridge + + Copyright (C) 2013 Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_bus_if_avalon +#( + parameter OPTION_AVALON_BURST_LENGTH = 4 + ) + ( + input clk, + input rst, + + output cpu_err_o, + output cpu_ack_o, + output [31:0] cpu_dat_o, + input [31:0] cpu_adr_i, + input [31:0] cpu_dat_i, + input cpu_req_i, + input [3:0] cpu_bsel_i, + input cpu_we_i, + input cpu_burst_i, + + output [31:0] avm_address_o, + output [3:0] avm_byteenable_o, + output avm_read_o, + input [31:0] avm_readdata_i, + output [3:0] avm_burstcount_o, + output avm_write_o, + output [31:0] avm_writedata_o, + input avm_waitrequest_i, + input avm_readdatavalid_i + ); + + localparam IDLE = 4'b0001; + localparam READ = 4'b0010; + localparam BURST = 4'b0100; + localparam WRITE = 4'b1000; + + reg [3:0] state; + + always @(posedge clk) begin + case (state) + IDLE: begin + if (cpu_req_i & !avm_waitrequest_i) begin + if (cpu_we_i) + state <= WRITE; + else if (cpu_burst_i) begin + state <= BURST; + end else + state <= READ; + end + end + + READ: begin + if (avm_readdatavalid_i) + state <= IDLE; + end + + BURST: begin + /* cpu_burst_i deasserts when the last burst access starts */ + if (!cpu_burst_i & avm_readdatavalid_i) + state <= IDLE; + end + + WRITE: begin + state <= IDLE; + end + endcase + end + + assign avm_address_o = cpu_adr_i; + assign avm_read_o = cpu_req_i & !cpu_we_i & (state == IDLE); + assign avm_byteenable_o = cpu_bsel_i; + assign avm_write_o = cpu_req_i & cpu_we_i & (state == IDLE); + assign avm_burstcount_o = cpu_burst_i & (state != BURST) ? + OPTION_AVALON_BURST_LENGTH : 4'd1; + assign avm_writedata_o = cpu_dat_i; + + assign cpu_err_o = 0; + assign cpu_ack_o = avm_readdatavalid_i | state == WRITE; + assign cpu_dat_o = avm_readdata_i; + + +endmodule diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_wb32.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_wb32.v new file mode 100644 index 0000000..dfce41a --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_wb32.v @@ -0,0 +1,186 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx processor Wishbone bus bridge + + For now, very simple, not registering, assumes 32-bit data, addressing + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_bus_if_wb32 + #( + parameter BUS_IF_TYPE = "CLASSIC", + parameter BURST_LENGTH = 8 + ) + ( + input clk, + input rst, + + output cpu_err_o, + output cpu_ack_o, + output [31:0] cpu_dat_o, + input [31:0] cpu_adr_i, + input [31:0] cpu_dat_i, + input cpu_req_i, + input [3:0] cpu_bsel_i, + input cpu_we_i, + input cpu_burst_i, + + output [31:0] wbm_adr_o, + output wbm_stb_o, + output wbm_cyc_o, + output [3:0] wbm_sel_o, + output wbm_we_o, + output [2:0] wbm_cti_o, + output [1:0] wbm_bte_o, + output [31:0] wbm_dat_o, + input wbm_err_i, + input wbm_ack_i, + input [31:0] wbm_dat_i, + input wbm_rty_i + ); + + localparam BADDR_WITH = (BURST_LENGTH==4) ? 2 : + (BURST_LENGTH==8) ? 3 : + (BURST_LENGTH==16)? 4 : 30; + + initial + $display("%m: Wishbone bus IF is %s",BUS_IF_TYPE); + + generate + /* verilator lint_off WIDTH */ + if (BUS_IF_TYPE=="B3_READ_BURSTING") begin : b3_read_bursting + /* verilator lint_on WIDTH */ + + // Burst until the incoming address is not what it should be + wire finish_burst; + reg finish_burst_r; + reg bursting; + reg [31:2] burst_address; + reg [BADDR_WITH-1:0] burst_wrap_start; + wire [BADDR_WITH-1:0] burst_wrap_finish; + wire address_differs; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + bursting <= 0; + else if (wbm_err_i) + bursting <= 0; + else if (bursting & finish_burst & wbm_ack_i) + bursting <= 0; + else if (cpu_req_i & !bursting & !cpu_we_i) + bursting <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + begin + burst_address <= 0; + burst_wrap_start <= 0; + end + else if (cpu_req_i & !bursting) + begin + burst_address <= cpu_adr_i[31:2]; + burst_wrap_start <= cpu_adr_i[BADDR_WITH+2-1:2]; + end + else if (wbm_ack_i) + burst_address[BADDR_WITH+2-1:2] <= burst_address[BADDR_WITH+2-1:2] + + 1; + + + assign address_differs = (burst_address!=cpu_adr_i[31:2]); + assign burst_wrap_finish = burst_wrap_start - 1; + assign finish_burst = (bursting & ( + (BURST_LENGTH!=0 && + burst_address[BADDR_WITH+2-1:2]==(burst_wrap_finish)) + | address_differs + | !cpu_req_i + ) + ) + ; + always @(posedge clk `OR_ASYNC_RST) + if (rst) + finish_burst_r <= 0; + else if (wbm_ack_i) + finish_burst_r <= finish_burst; + else + finish_burst_r <= 0; + + assign wbm_adr_o = bursting ? {burst_address,2'b00} : cpu_adr_i; + assign wbm_stb_o = bursting & !finish_burst_r; + assign wbm_cyc_o = bursting & !finish_burst_r; + assign wbm_sel_o = cpu_bsel_i; + assign wbm_we_o = cpu_we_i; + assign wbm_cti_o = bursting ? (finish_burst ? 3'b111 : 3'b010) : + 3'b000; + assign wbm_bte_o = BURST_LENGTH==4 ? 2'b01 : + BURST_LENGTH==8 ? 2'b10 : + BURST_LENGTH==16 ? 2'b11 : + 2'b00; // Linear burst + + assign wbm_dat_o = cpu_dat_i; + + assign cpu_err_o = wbm_err_i; + assign cpu_ack_o = (wbm_ack_i) & + !(bursting & address_differs) & cpu_req_i; + assign cpu_dat_o = wbm_err_i ? 0 : wbm_dat_i; + + /* verilator lint_off WIDTH */ + end else if (BUS_IF_TYPE=="B3_REGISTERED_FEEDBACK") begin : b3_registered_feedback + /* verilator lint_on WIDTH */ + + assign wbm_adr_o = cpu_adr_i; + assign wbm_stb_o = cpu_req_i; + assign wbm_cyc_o = cpu_req_i; + assign wbm_sel_o = cpu_bsel_i; + assign wbm_we_o = cpu_we_i; + assign wbm_cti_o = cpu_burst_i ? 3'b010 : 3'b111; + assign wbm_bte_o = BURST_LENGTH==4 ? 2'b01 : + BURST_LENGTH==8 ? 2'b10 : + BURST_LENGTH==16 ? 2'b11 : + 2'b00; // Linear burst + + assign wbm_dat_o = cpu_dat_i; + assign cpu_err_o = wbm_err_i; + assign cpu_ack_o = wbm_ack_i; + assign cpu_dat_o = wbm_dat_i; + + end else begin : classic // CLASSIC only + + // Only classic, single cycle accesses + + // A register to force de-assertion of access request signals after + // each ack + reg cycle_end; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + cycle_end <= 1; + else + cycle_end <= wbm_ack_i | wbm_err_i; + + assign cpu_err_o = wbm_err_i; + assign cpu_ack_o = wbm_ack_i; + assign cpu_dat_o = wbm_dat_i; + + assign wbm_adr_o = cpu_adr_i; + assign wbm_stb_o = cpu_req_i & !cycle_end; + assign wbm_cyc_o = cpu_req_i; + assign wbm_sel_o = cpu_bsel_i; + assign wbm_we_o = cpu_we_i; + assign wbm_cti_o = 0; + assign wbm_bte_o = 0; + assign wbm_dat_o = cpu_dat_i; + + end // else: !if(BUS_IF_TYPE=="READ_B3_BURSTING") + endgenerate + +endmodule // mor1kx_bus_if_wb diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cache_lru.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cache_lru.v new file mode 100644 index 0000000..88ea116 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cache_lru.v @@ -0,0 +1,281 @@ +/****************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Data cache LRU implementation + + Copyright (C) 2012 Stefan Wallentowitz + + ******************************************************************************/ + +// This is the least-recently-used (LRU) calculation module. It +// essentially has two types of input and output. First, the history +// information needs to be evaluated to calculate the LRU value. +// Second, the current access and the LRU are one hot values of the +// ways. +// +// This module is pure combinational. All registering is done outside +// this module. The following parameter exists: +// +// * NUMWAYS: Number of ways (must be greater than 1) +// +// The following ports exist: +// +// * current: The current LRU history +// * update: The new LRU history after access +// +// * access: 0 if no access or one-hot of the way that accesses +// * lru_pre: LRU before the access (one hot of ways) +// * lru_post: LRU after the access (one hot of ways) +// +// The latter three have the width of NUMWAYS apparently. The first +// three are more complicated as this is an optimized way of storing +// the history information, which will be shortly described in the +// following. +// +// A naive approach to store the history of the access is to store the +// relative "age" of each element in a vector, for example for four +// ways: +// +// 0: 1 1: 3 2: 1 3:0 +// +// This needs 4x2 bits, but more important it also needs a set of +// comparators and adders. This can become increasingly complex when +// using a higher number of cache ways with an impact on area and +// timing. +// +// Similarly, it is possible to store a "stack" of the access and +// reorder this stack on an access. But the problems are similar, it +// needs comparators etc. +// +// A neat approach is to store the history efficiently coded, while +// also easing the calculation. This approach stores the information +// whether each entry is older than the others. For example for the +// four-way example (x>1)-1:0])), +// .update (updated_history[((NUMWAYS*(NUMWAYS-1))>>1)-1:0])), +// .access (access[NUMWAYS-1:0]), +// .lru_pre (lru_pre[NUMWAYS-1:0]), +// .lru_post (lru_post[NUMWAYS-1:0])); + + +module mor1kx_cache_lru(/*AUTOARG*/ + // Outputs + update, lru_pre, lru_post, + // Inputs + current, access + ); + parameter NUMWAYS = 2; + + // Triangular number + localparam WIDTH = NUMWAYS*(NUMWAYS-1) >> 1; + + input [WIDTH-1:0] current; + output reg [WIDTH-1:0] update; + + input [NUMWAYS-1:0] access; + output reg [NUMWAYS-1:0] lru_pre; + output reg [NUMWAYS-1:0] lru_post; + + reg [NUMWAYS-1:0] expand [0:NUMWAYS-1]; + + integer i, j; + integer offset; + + // + // < 0 1 2 3 + // 0 1 (0<1) (0<2) (0<3) + // 1 (1<0) 1 (1<2) (1<3) + // 2 (2<0) (2<1) 1 (2<3) + // 3 (3<0) (3<1) (3<2) 1 + // + // As two entries can never be equally old (needs to be avoided on + // the outside) this is equivalent to: + // + // < 0 1 2 3 + // 0 1 (0<1) (0<2) (0<3) + // 1 !(0<1) 1 (1<2) (1<3) + // 2 !(0<2) !(1<2) 1 (2<3) + // 3 !(0<3) !(1<3) !(2<3) 1 + // + // The lower half below the diagonal is the inverted mirror of the + // upper half. The number of entries in each half is of course + // equal to the width of our LRU vector and the upper half is + // filled with the values from the vector. + // + // The algorithm works as follows: + // + // 1. Fill the matrix (expand) with the values. The entry (i,i) is + // statically one. + // + // 2. The LRU_pre vector is the vector of the ANDs of the each row. + // + // 3. Update the values with the access vector (if any) in the + // following way: If access[i] is set, the values in row i are + // set to 0. Similarly, the values in column i are set to 1. + // + // 4. The update vector of the lru history is then generated by + // copying the upper half of the matrix back. + // + // 5. The LRU_post vector is the vector of the ANDs of each row. + // + // In the following an example will be used to demonstrate the algorithm: + // + // NUMWAYS = 4 + // current = 6'b110100; + // access = 4'b0010; + // + // This current history is: + // + // 0<1 0<2 0<3 1<2 1<3 2<3 + // 0 0 1 0 1 1 + // + // and way 2 is accessed. + // + // The history of accesses is 3>0>1>2 and the expected result is an + // update to 2>3>0>1 with LRU_pre=2 and LRU_post=1 + + + always @(*) begin : comb + // The offset is used to transfer the flat history vector into + // the upper half of the + offset = 0; + + // 1. Fill the matrix (expand) with the values. The entry (i,i) is + // statically one. + for (i = 0; i < NUMWAYS; i = i + 1) begin + expand[i][i] = 1'b1; + + for (j = i + 1; j < NUMWAYS; j = j + 1) begin + expand[i][j] = current[offset+j-i-1]; + end + for (j = 0; j < i; j = j + 1) begin + expand[i][j] = !expand[j][i]; + end + + offset = offset + NUMWAYS - i - 1; + end // for (i = 0; i < NUMWAYS; i = i + 1) + + // For the example expand is now: + // < 0 1 2 3 0 1 2 3 + // 0 1 (0<1) (0<2) (0<3) 0 1 0 0 1 + // 1 (1<0) 1 (1<2) (1<3) => 1 1 1 0 1 + // 2 (2<0) (2<1) 1 (2<3) 2 1 1 1 1 + // 3 (3<0) (3<1) (3<2) 1 3 0 0 0 1 + + + // 2. The LRU_pre vector is the vector of the ANDs of the each + // row. + for (i = 0; i < NUMWAYS; i = i + 1) begin + lru_pre[i] = &expand[i]; + end + + // We derive why this is the case for the example here: + // lru_pre[2] is high when the following condition holds: + // + // (2<0) & (2<1) & (2<3). + // + // Applying the negation transform we get: + // + // !(0<2) & !(1<2) & (2<3) + // + // and this is exactly row [2], so that here + // + // lru_pre[2] = &expand[2] = 1'b1; + // + // At this point you can also see why we initialize the diagonal + // with 1. + + // 3. Update the values with the access vector (if any) in the + // following way: If access[i] is set, the values in row i + // are set to 0. Similarly, the values in column i are set + // to 1. + for (i = 0; i < NUMWAYS; i = i + 1) begin + if (access[i]) begin + for (j = 0; j < NUMWAYS; j = j + 1) begin + if (i != j) begin + expand[i][j] = 1'b0; + end + end + for (j = 0; j < NUMWAYS; j = j + 1) begin + if (i != j) begin + expand[j][i] = 1'b1; + end + end + end + end // for (i = 0; i < NUMWAYS; i = i + 1) + + // Again this becomes obvious when you see what we do here. + // Accessing way 2 leads means now + // + // (0<2) = (1<2) = (3<2) = 1, and + // (2<0) = (2<1) = (2<3) = 0 + // + // The matrix changes accordingly + // + // 0 1 2 3 0 1 2 3 + // 0 1 0 0 1 0 1 0 1 1 + // 1 1 1 0 1 => 1 1 1 1 1 + // 2 1 1 1 1 2 0 0 1 0 + // 3 0 0 0 1 3 0 0 1 1 + + // 4. The update vector of the lru history is then generated by + // copying the upper half of the matrix back. + offset = 0; + for (i = 0; i < NUMWAYS; i = i + 1) begin + for (j = i + 1; j < NUMWAYS; j = j + 1) begin + update[offset+j-i-1] = expand[i][j]; + end + offset = offset + NUMWAYS - i - 1; + end + + // This is the opposite operation of step 1 and is clear now. + // Update becomes: + // + // update = 6'b011110 + // + // This is translated to + // + // 0<1 0<2 0<3 1<2 1<3 2<3 + // 0 1 1 1 1 0 + // + // which is: 2>3>0>1, which is what we expected. + + // 5. The LRU_post vector is the vector of the ANDs of each row. + for (i = 0; i < NUMWAYS; i = i + 1) begin + lru_post[i] = &expand[i]; + end + + // This final step is equal to step 2 and also clear now. + // + // lru_post[1] = &expand[1] = 1'b1; + // + // lru_post = 4'b0010 is what we expected. + end + + +endmodule // mor1kx_dcache_lru diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cfgrs.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cfgrs.v new file mode 100644 index 0000000..a14496b --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cfgrs.v @@ -0,0 +1,239 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx SPRs indicating configuration and version + + All registers are read only and configured at synthesis time. + + Note that the outputs do not have the usual "_o" prefix on the port names + as this module is intended to be instantiated without a Verilog-mode + AUTO_TEMPLATE, and as the module is providing read-only signals, there's + no confusion about the direction of the ports. + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_cfgrs + #( + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter FEATURE_DMMU = "NONE", + parameter OPTION_DMMU_SET_WIDTH = 6, + parameter OPTION_DMMU_WAYS = 1, + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter FEATURE_IMMU = "NONE", + parameter OPTION_IMMU_SET_WIDTH = 6, + parameter OPTION_IMMU_WAYS = 1, + parameter FEATURE_PIC = "ENABLED", + parameter FEATURE_TIMER = "ENABLED", + parameter FEATURE_DEBUGUNIT = "NONE", + parameter FEATURE_PERFCOUNTERS = "NONE", + parameter FEATURE_PMU = "NONE", + parameter FEATURE_MAC = "NONE", + parameter FEATURE_FPU = "NONE", + + parameter OPTION_PIC_TRIGGER = "LEVEL", + + parameter FEATURE_DSX = "NONE", + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter OPTION_RF_NUM_SHADOW_GPR = 0, + parameter FEATURE_OVERFLOW = "NONE", + + parameter FEATURE_DELAYSLOT = "NONE", + + parameter FEATURE_EVBAR = "NONE", + parameter FEATURE_AECSR = "NONE" + ) + ( + output [31:0] spr_vr, + output [31:0] spr_vr2, + output [31:0] spr_upr, + output [31:0] spr_cpucfgr, + output [31:0] spr_dmmucfgr, + output [31:0] spr_immucfgr, + output [31:0] spr_dccfgr, + output [31:0] spr_iccfgr, + output [31:0] spr_dcfgr, + output [31:0] spr_pccfgr, + output [31:0] spr_avr + ); + + assign spr_vr[`OR1K_SPR_VR_REV] = 0; + assign spr_vr[`OR1K_SPR_VR_UVRP] = 1; + assign spr_vr[`OR1K_SPR_VR_RESERVED] = 0; + assign spr_vr[`OR1K_SPR_VR_CFG] = 0; + assign spr_vr[`OR1K_SPR_VR_VER] = 8'h10; + + assign spr_upr[`OR1K_SPR_UPR_UP] = 1; + assign spr_upr[`OR1K_SPR_UPR_DCP] = (FEATURE_DATACACHE!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_ICP] = (FEATURE_INSTRUCTIONCACHE!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_DMP] = (FEATURE_DMMU!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_IMP] = (FEATURE_IMMU!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_MP] = (FEATURE_MAC!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_DUP] = (FEATURE_DEBUGUNIT!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_PCUP] = (FEATURE_PERFCOUNTERS!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_PICP] = (FEATURE_PIC!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_PMP] = (FEATURE_PMU!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_TTP] = (FEATURE_TIMER!="NONE"); + assign spr_upr[`OR1K_SPR_UPR_RESERVED] = 0; + assign spr_upr[`OR1K_SPR_UPR_CUP] = 0; + + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_NSGF] = OPTION_RF_NUM_SHADOW_GPR; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_CFG] = 0; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB32S] = 1; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB64S] = 0; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF32S] = (FEATURE_FPU!="NONE"); + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF64S] = 0; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OV64S] = 0; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ND] = (FEATURE_DELAYSLOT=="NONE"); + /* AVR will always be present in mor1kx */ + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AVRP] = 1; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_EVBARP] = (FEATURE_EVBAR!="NONE"); + /* ISRs will always be present */ + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ISRP] = 1; + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AECSRP] = (FEATURE_AECSR!="NONE"); + assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_RESERVED] = 0; + + /* Version register 2 */ + /* Implementation ID as per: + http://opencores.org/or1k/OR1K_CPU_Cores#CPU_ID_Table + mor1kx breaks up the VR2[23:0] to be 3 8-bit fields + 23:16 - Major version number + 15:8 - Minor version number + 7:0 - Pipeline implementation identifier (set outside of this module) + */ + assign spr_vr2[`OR1K_SPR_VR2_CPUID] = `MOR1KX_CPUID; + assign spr_vr2[`OR1K_SPR_VR2_VER] = {`MOR1KX_VERSION_MAJOR, + `MOR1KX_VERSION_MINOR, + 8'd0}; + + /* Currently supporting OR1K version 1.1 rev0 */ + assign spr_avr[`OR1K_SPR_AVR_MAJ] = 8'd1; + assign spr_avr[`OR1K_SPR_AVR_MIN] = 8'd1; + assign spr_avr[`OR1K_SPR_AVR_REV] = 8'd0; + assign spr_avr[`OR1K_SPR_AVR_RESERVED] = 0; + + /* Data MMU Configuration Register */ + /* Reserved */ + assign spr_dmmucfgr[31:15] = 0; + /* Hardware TLB Reload */ + assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_HTR] = 0; + /* TLB Entry Invalidate Register Implemented */ + assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_TEIRI] = 0; + /* Protection Register Implemented */ + assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_PRI] = 0; + /* Control Register Implemented */ + assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_CRI] = 0; + /* Number of ATB entries */ + assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NAE] = 0; + /* Number of TLB sets */ + assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTS] = (FEATURE_DMMU!="NONE") ? + OPTION_DMMU_SET_WIDTH : 0; + /* Number of TLB ways */ + assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTW] = (FEATURE_DMMU!="NONE") ? + OPTION_DMMU_WAYS-1 : 0; + + /* Instruction MMU Configuration Register */ + /* Reserved */ + assign spr_immucfgr[31:15] = 0; + /* Hardware TLB Reload */ + assign spr_immucfgr[`OR1K_SPR_IMMUFGR_HTR] = 0; + /* TLB Entry Invalidate Register Implemented */ + assign spr_immucfgr[`OR1K_SPR_IMMUFGR_TEIRI] = 0; + /* Protection Register Implemented */ + assign spr_immucfgr[`OR1K_SPR_IMMUFGR_PRI] = 0; + /* Control Register Implemented */ + assign spr_immucfgr[`OR1K_SPR_IMMUFGR_CRI] = 0; + /* Number of ATB entries */ + assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NAE] = 0; + /* Number of TLB sets */ + assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTS] = (FEATURE_IMMU!="NONE") ? + OPTION_IMMU_SET_WIDTH : 0; + /* Number of TLB ways */ + assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTW] = (FEATURE_IMMU!="NONE") ? + OPTION_IMMU_WAYS-1 : 0; + + /* Data Cache Configuration register */ + /* Reserved */ + assign spr_dccfgr[31:15] = 0; + /* Cache Block Write-Back Register Implemented */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBWBRI] = 0; + /* Cache Block Flush Register Implemented */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBFRI] = (FEATURE_DATACACHE!="NONE"); + /* Cache Block Lock Register Implemented */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBLRI] = 0; + /* Cache Block Prefetch Register Implemented */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBPRI] = 0; + /* Cache Block Invalidate Register Implemented */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBIRI] = (FEATURE_DATACACHE!="NONE"); + /* Cache Control Register Implemented */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CCRI] = 0; + /* Cache Write Strategy (0 = write-through, 1 = write-back) */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CWS] = 0; + /* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBS] = (FEATURE_DATACACHE!="NONE") ? + (OPTION_DCACHE_BLOCK_WIDTH == 5 ? + 1 : 0) : 0; + /* Number of Cache Sets */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCS] = (FEATURE_DATACACHE!="NONE") ? + OPTION_DCACHE_SET_WIDTH : 0; + /* Number of Cache Ways */ + assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCW] = (FEATURE_DATACACHE!="NONE") ? + (OPTION_DCACHE_WAYS == 1) ? 3'd0 : + (OPTION_DCACHE_WAYS == 2) ? 3'd1 : + (OPTION_DCACHE_WAYS == 4) ? 3'd2 : + (OPTION_DCACHE_WAYS == 8) ? 3'd3 : + (OPTION_DCACHE_WAYS == 16) ? 3'd4 : + (OPTION_DCACHE_WAYS == 32) ? 3'd5 : + 3'd0 : 3'd0; + + /* Instruction Cache Configuration register */ + /* Reserved */ + assign spr_iccfgr[31:13] = 0; + assign spr_iccfgr[8] = 0; + /* Cache Block Lock Register Implemented */ + assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBLRI] = 0; + /* Cache Block Prefetch Register Implemented */ + assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBPRI] = 0; + /* Cache Block Invalidate Register Implemented */ + assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBIRI] = (FEATURE_INSTRUCTIONCACHE!="NONE"); + /* Cache Control Register Implemented */ + assign spr_iccfgr[`OR1K_SPR_ICCFGR_CCRI] = 0; + /* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */ + assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ? + (OPTION_ICACHE_BLOCK_WIDTH == 5 ? + 1 : 0) : 0; + /* Number of Cache Sets */ + assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ? + OPTION_ICACHE_SET_WIDTH : 0; + /* Number of Cache Ways */ + assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCW] = (FEATURE_INSTRUCTIONCACHE!="NONE") ? + (OPTION_ICACHE_WAYS == 1) ? 3'd0 : + (OPTION_ICACHE_WAYS == 2) ? 3'd1 : + (OPTION_ICACHE_WAYS == 4) ? 3'd2 : + (OPTION_ICACHE_WAYS == 8) ? 3'd3 : + (OPTION_ICACHE_WAYS == 16) ? 3'd4 : + (OPTION_ICACHE_WAYS == 32) ? 3'd5 : + 3'd0 : 3'd0; + + assign spr_dcfgr = 0; + assign spr_pccfgr = 0; + +endmodule // mor1kx_cfgrs diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu.v new file mode 100644 index 0000000..64cd7fb --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu.v @@ -0,0 +1,625 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: CPU wrapper module + + Allows selection of CPU pipeline implementation based on parameter. + + Also provides some API-like hooks into the pipeline for monitors. + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_cpu + #( + parameter OPTION_OPERAND_WIDTH = 32, + + parameter OPTION_CPU = "CAPPUCCINO", + + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter OPTION_DCACHE_LIMIT_WIDTH = 32, + parameter OPTION_DCACHE_SNOOP = "NONE", + parameter FEATURE_DMMU = "NONE", + parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_DMMU_SET_WIDTH = 6, + parameter OPTION_DMMU_WAYS = 1, + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter OPTION_ICACHE_LIMIT_WIDTH = 32, + parameter FEATURE_IMMU = "NONE", + parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_IMMU_SET_WIDTH = 6, + parameter OPTION_IMMU_WAYS = 1, + parameter FEATURE_TIMER = "ENABLED", + parameter FEATURE_DEBUGUNIT = "NONE", + parameter FEATURE_PERFCOUNTERS = "NONE", + parameter FEATURE_MAC = "NONE", + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + + parameter FEATURE_PIC = "ENABLED", + parameter OPTION_PIC_TRIGGER = "LEVEL", + parameter OPTION_PIC_NMI_WIDTH = 0, + + parameter FEATURE_DSX = "NONE", + parameter FEATURE_OVERFLOW = "NONE", + parameter FEATURE_CARRY_FLAG = "ENABLED", + + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter OPTION_RF_CLEAR_ON_INIT = 0, + parameter OPTION_RF_NUM_SHADOW_GPR = 0, + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter OPTION_RF_WORDS = 32, + + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + + parameter OPTION_TCM_FETCHER = "DISABLED", + + parameter FEATURE_MULTIPLIER = "THREESTAGE", + parameter FEATURE_DIVIDER = "NONE", + + parameter OPTION_SHIFTER = "BARREL", + + parameter FEATURE_ADDC = "NONE", + parameter FEATURE_SRA = "ENABLED", + parameter FEATURE_ROR = "NONE", + parameter FEATURE_EXT = "NONE", + parameter FEATURE_CMOV = "NONE", + parameter FEATURE_FFL1 = "NONE", + parameter FEATURE_MSYNC = "ENABLED", + parameter FEATURE_PSYNC = "NONE", + parameter FEATURE_CSYNC = "NONE", + parameter FEATURE_ATOMIC = "ENABLED", + + parameter FEATURE_FPU = "NONE", // ENABLED|NONE + + parameter FEATURE_CUST1 = "NONE", + parameter FEATURE_CUST2 = "NONE", + parameter FEATURE_CUST3 = "NONE", + parameter FEATURE_CUST4 = "NONE", + parameter FEATURE_CUST5 = "NONE", + parameter FEATURE_CUST6 = "NONE", + parameter FEATURE_CUST7 = "NONE", + parameter FEATURE_CUST8 = "NONE", + + parameter FEATURE_STORE_BUFFER = "ENABLED", + parameter OPTION_STORE_BUFFER_DEPTH_WIDTH = 8, + + parameter FEATURE_MULTICORE = "NONE", + + parameter FEATURE_TRACEPORT_EXEC = "NONE" + ) + ( + input clk, + input rst, + + // Instruction bus + input ibus_err_i, + input ibus_ack_i, + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o, + output ibus_req_o, + output ibus_burst_o, + + // Data bus + input dbus_err_i, + input dbus_ack_i, + input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o, + output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o, + output dbus_req_o, + output [3:0] dbus_bsel_o, + output dbus_we_o, + output dbus_burst_o, + + // Interrupts + input [31:0] irq_i, + + // Debug interface + input [15:0] du_addr_i, + input du_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i, + input du_we_i, + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o, + output du_ack_o, + // Stall control from debug interface + input du_stall_i, + output du_stall_o, + + output traceport_exec_valid_o, + output [31:0] traceport_exec_pc_o, + output [`OR1K_INSN_WIDTH-1:0] traceport_exec_insn_o, + output [OPTION_OPERAND_WIDTH-1:0] traceport_exec_wbdata_o, + output [OPTION_RF_ADDR_WIDTH-1:0] traceport_exec_wbreg_o, + output traceport_exec_wben_o, + + // SPR accesses to external units (cache, mmu, etc.) + output [15:0] spr_bus_addr_o, + output spr_bus_we_o, + output spr_bus_stb_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i, + input spr_bus_ack_dmmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i, + input spr_bus_ack_immu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i, + input spr_bus_ack_mac_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i, + input spr_bus_ack_pmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i, + input spr_bus_ack_pcu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i, + input spr_bus_ack_fpu_i, + output [15:0] spr_sr_o, + + // The multicore core identifier + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i, + // The number of cores + input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i, + + input [31:0] snoop_adr_i, + input snoop_en_i + ); + + wire [`OR1K_INSN_WIDTH-1:0] monitor_execute_insn/* verilator public */; + wire monitor_execute_advance/* verilator public */; + wire monitor_flag_set/* verilator public */; + wire monitor_flag_clear/* verilator public */; + wire monitor_flag_sr/* verilator public */; + wire monitor_flag/* verilator public */; + wire [OPTION_OPERAND_WIDTH-1:0] monitor_spr_sr/* verilator public */; + wire [OPTION_OPERAND_WIDTH-1:0] monitor_execute_pc/* verilator public */; + wire [OPTION_OPERAND_WIDTH-1:0] monitor_rf_result_in/* verilator public */; + wire monitor_clk/* verilator public */; + wire [OPTION_OPERAND_WIDTH-1:0] monitor_spr_epcr/* verilator public */; + wire [OPTION_OPERAND_WIDTH-1:0] monitor_spr_eear/* verilator public */; + wire [OPTION_OPERAND_WIDTH-1:0] monitor_spr_esr/* verilator public */; + wire monitor_branch_mispredict/* verilator public */; + + + generate + /* verilator lint_off WIDTH */ + if (OPTION_CPU=="CAPPUCCINO") begin : cappuccino + /* verilator lint_on WIDTH */ + mor1kx_cpu_cappuccino + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .FEATURE_DATACACHE(FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .OPTION_DCACHE_LIMIT_WIDTH(OPTION_DCACHE_LIMIT_WIDTH), + .OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP), + .FEATURE_DMMU(FEATURE_DMMU), + .FEATURE_DMMU_HW_TLB_RELOAD(FEATURE_DMMU_HW_TLB_RELOAD), + .OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH), + .OPTION_DMMU_WAYS(OPTION_DMMU_WAYS), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .OPTION_ICACHE_LIMIT_WIDTH(OPTION_ICACHE_LIMIT_WIDTH), + .FEATURE_IMMU(FEATURE_IMMU), + .FEATURE_IMMU_HW_TLB_RELOAD(FEATURE_IMMU_HW_TLB_RELOAD), + .OPTION_IMMU_SET_WIDTH(OPTION_IMMU_SET_WIDTH), + .OPTION_IMMU_WAYS(OPTION_IMMU_WAYS), + .FEATURE_PIC(FEATURE_PIC), + .FEATURE_TIMER(FEATURE_TIMER), + .FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTICORE(FEATURE_MULTICORE), + .FEATURE_TRACEPORT_EXEC(FEATURE_TRACEPORT_EXEC), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE), + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH), + .FEATURE_DSX(FEATURE_DSX), + .FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS), + .OPTION_RF_CLEAR_ON_INIT(OPTION_RF_CLEAR_ON_INIT), + .OPTION_RF_NUM_SHADOW_GPR(OPTION_RF_NUM_SHADOW_GPR), + .FEATURE_OVERFLOW(FEATURE_OVERFLOW), + .FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RF_WORDS(OPTION_RF_WORDS), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_MSYNC(FEATURE_MSYNC), + .FEATURE_PSYNC(FEATURE_PSYNC), + .FEATURE_CSYNC(FEATURE_CSYNC), + .FEATURE_ATOMIC(FEATURE_ATOMIC), + .FEATURE_FPU(FEATURE_FPU), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8), + .OPTION_SHIFTER(OPTION_SHIFTER), + .FEATURE_STORE_BUFFER(FEATURE_STORE_BUFFER), + .OPTION_STORE_BUFFER_DEPTH_WIDTH(OPTION_STORE_BUFFER_DEPTH_WIDTH) + ) + mor1kx_cpu + (/*AUTOINST*/ + // Outputs + .ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ibus_req_o (ibus_req_o), + .ibus_burst_o (ibus_burst_o), + .dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_req_o (dbus_req_o), + .dbus_bsel_o (dbus_bsel_o[3:0]), + .dbus_we_o (dbus_we_o), + .dbus_burst_o (dbus_burst_o), + .du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .du_ack_o (du_ack_o), + .du_stall_o (du_stall_o), + .traceport_exec_valid_o (traceport_exec_valid_o), + .traceport_exec_pc_o (traceport_exec_pc_o[31:0]), + .traceport_exec_insn_o (traceport_exec_insn_o[`OR1K_INSN_WIDTH-1:0]), + .traceport_exec_wbdata_o (traceport_exec_wbdata_o[OPTION_OPERAND_WIDTH-1:0]), + .traceport_exec_wbreg_o (traceport_exec_wbreg_o[OPTION_RF_ADDR_WIDTH-1:0]), + .traceport_exec_wben_o (traceport_exec_wben_o), + .spr_bus_addr_o (spr_bus_addr_o[15:0]), + .spr_bus_we_o (spr_bus_we_o), + .spr_bus_stb_o (spr_bus_stb_o), + .spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_sr_o (spr_sr_o[15:0]), + // Inputs + .clk (clk), + .rst (rst), + .ibus_err_i (ibus_err_i), + .ibus_ack_i (ibus_ack_i), + .ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .dbus_err_i (dbus_err_i), + .dbus_ack_i (dbus_ack_i), + .dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .irq_i (irq_i[31:0]), + .du_addr_i (du_addr_i[15:0]), + .du_stb_i (du_stb_i), + .du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .du_we_i (du_we_i), + .du_stall_i (du_stall_i), + .spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_mac_i (spr_bus_ack_mac_i), + .spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pmu_i (spr_bus_ack_pmu_i), + .spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pcu_i (spr_bus_ack_pcu_i), + .spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_fpu_i (spr_bus_ack_fpu_i), + .multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0]), + .multicore_numcores_i (multicore_numcores_i[OPTION_OPERAND_WIDTH-1:0]), + .snoop_adr_i (snoop_adr_i[31:0]), + .snoop_en_i (snoop_en_i)); + + // synthesis translate_off +`ifndef SYNTHESIS + + assign monitor_flag = monitor_flag_set ? 1 : + monitor_flag_clear ? 0 : + monitor_flag_sr; + assign monitor_clk = clk; + + assign monitor_execute_advance = cappuccino.mor1kx_cpu.padv_execute_o; + assign monitor_flag_set = cappuccino.mor1kx_cpu.mor1kx_execute_ctrl_cappuccino.flag_set_i; + assign monitor_flag_clear = cappuccino.mor1kx_cpu.mor1kx_execute_ctrl_cappuccino.flag_clear_i; + assign monitor_flag_sr = cappuccino.mor1kx_cpu.mor1kx_ctrl_cappuccino.ctrl_flag_o; + assign monitor_spr_sr = {16'd0,cappuccino.mor1kx_cpu.mor1kx_ctrl_cappuccino.spr_sr[15:`OR1K_SPR_SR_F+1],cappuccino.mor1kx_cpu.mor1kx_ctrl_cappuccino.ctrl_flag_o,cappuccino.mor1kx_cpu.mor1kx_ctrl_cappuccino.spr_sr[`OR1K_SPR_SR_F-1:0]}; + assign monitor_execute_pc = cappuccino.mor1kx_cpu.pc_decode_to_execute; + assign monitor_rf_result_in = cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.result_i; + assign monitor_spr_esr = {16'd0,cappuccino.mor1kx_cpu.mor1kx_ctrl_cappuccino.spr_esr}; + assign monitor_spr_epcr = cappuccino.mor1kx_cpu.mor1kx_ctrl_cappuccino.spr_epcr; + assign monitor_spr_eear = cappuccino.mor1kx_cpu.mor1kx_ctrl_cappuccino.spr_eear; + assign monitor_branch_mispredict = cappuccino.mor1kx_cpu.branch_mispredict_o; + + reg [`OR1K_INSN_WIDTH-1:0] monitor_execute_insn_reg; + always @(posedge clk) + if (cappuccino.mor1kx_cpu.padv_decode_o) + monitor_execute_insn_reg <= cappuccino.mor1kx_cpu.mor1kx_decode.decode_insn_i; + + assign monitor_execute_insn = monitor_execute_insn_reg; + +`endif + // synthesis translate_on + + + end // block: cappuccino + /* verilator lint_off WIDTH */ + if (OPTION_CPU=="ESPRESSO") begin : espresso + /* verilator lint_on WIDTH */ + mor1kx_cpu_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .FEATURE_DATACACHE(FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .FEATURE_DMMU(FEATURE_DMMU), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .FEATURE_IMMU(FEATURE_IMMU), + .FEATURE_PIC(FEATURE_PIC), + .FEATURE_TIMER(FEATURE_TIMER), + .FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTICORE(FEATURE_MULTICORE), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE), + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH), + .FEATURE_DSX(FEATURE_DSX), + .FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS), + .FEATURE_OVERFLOW(FEATURE_OVERFLOW), + .FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RF_WORDS(OPTION_RF_WORDS), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_MSYNC(FEATURE_MSYNC), + .FEATURE_PSYNC(FEATURE_PSYNC), + .FEATURE_CSYNC(FEATURE_CSYNC), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8), + .OPTION_SHIFTER(OPTION_SHIFTER) + ) + mor1kx_cpu + (/*AUTOINST*/ + // Outputs + .ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ibus_req_o (ibus_req_o), + .ibus_burst_o (ibus_burst_o), + .dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_req_o (dbus_req_o), + .dbus_bsel_o (dbus_bsel_o[3:0]), + .dbus_we_o (dbus_we_o), + .dbus_burst_o (dbus_burst_o), + .du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .du_ack_o (du_ack_o), + .du_stall_o (du_stall_o), + .spr_bus_addr_o (spr_bus_addr_o[15:0]), + .spr_bus_we_o (spr_bus_we_o), + .spr_bus_stb_o (spr_bus_stb_o), + .spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_sr_o (spr_sr_o[15:0]), + // Inputs + .clk (clk), + .rst (rst), + .ibus_err_i (ibus_err_i), + .ibus_ack_i (ibus_ack_i), + .ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .dbus_err_i (dbus_err_i), + .dbus_ack_i (dbus_ack_i), + .dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .irq_i (irq_i[31:0]), + .du_addr_i (du_addr_i[15:0]), + .du_stb_i (du_stb_i), + .du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .du_we_i (du_we_i), + .du_stall_i (du_stall_i), + .spr_bus_dat_dmmu_i (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dmmu_i (spr_bus_ack_dmmu_i), + .spr_bus_dat_immu_i (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_immu_i (spr_bus_ack_immu_i), + .spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_mac_i (spr_bus_ack_mac_i), + .spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pmu_i (spr_bus_ack_pmu_i), + .spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pcu_i (spr_bus_ack_pcu_i), + .spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_fpu_i (spr_bus_ack_fpu_i), + .multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0])); + + // synthesis translate_off +`ifndef SYNTHESIS + assign monitor_flag = monitor_flag_set ? 1 : + monitor_flag_clear ? 0 : + monitor_flag_sr; + assign monitor_clk = clk; + assign monitor_execute_insn = espresso.mor1kx_cpu.mor1kx_fetch_espresso.decode_insn_o; + assign monitor_execute_advance = espresso.mor1kx_cpu.mor1kx_ctrl_espresso.execute_done; + assign monitor_flag_set = espresso.mor1kx_cpu.mor1kx_ctrl_espresso.ctrl_flag_set_i; + assign monitor_flag_clear = espresso.mor1kx_cpu.mor1kx_ctrl_espresso.ctrl_flag_clear_i; + assign monitor_flag_sr = espresso.mor1kx_cpu.mor1kx_ctrl_espresso.flag; + assign monitor_spr_sr = {16'd0,espresso.mor1kx_cpu.mor1kx_ctrl_espresso.spr_sr[15:`OR1K_SPR_SR_F+1], + // Use the locally calculated flag value + monitor_flag, + espresso.mor1kx_cpu.mor1kx_ctrl_espresso.spr_sr[`OR1K_SPR_SR_F-1:0]}; + assign monitor_execute_pc = espresso.mor1kx_cpu.mor1kx_ctrl_espresso.spr_ppc; + assign monitor_rf_result_in = espresso.mor1kx_cpu.mor1kx_rf_espresso.result_i; + assign monitor_spr_esr = {16'd0,espresso.mor1kx_cpu.mor1kx_ctrl_espresso.spr_esr}; + assign monitor_spr_epcr = espresso.mor1kx_cpu.mor1kx_ctrl_espresso.spr_epcr; + assign monitor_spr_eear = espresso.mor1kx_cpu.mor1kx_ctrl_espresso.spr_eear; + assign monitor_branch_mispredict = 0; +`endif + // synthesis translate_on + + end // block: espresso + /* verilator lint_off WIDTH */ + if (OPTION_CPU=="PRONTO_ESPRESSO") begin : prontoespresso + /* verilator lint_on WIDTH */ + mor1kx_cpu_prontoespresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .FEATURE_DATACACHE(FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .FEATURE_DMMU(FEATURE_DMMU), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .FEATURE_IMMU(FEATURE_IMMU), + .FEATURE_PIC(FEATURE_PIC), + .FEATURE_TIMER(FEATURE_TIMER), + .FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTICORE(FEATURE_MULTICORE), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE), + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH), + .FEATURE_DSX(FEATURE_DSX), + .FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS), + .FEATURE_OVERFLOW(FEATURE_OVERFLOW), + .FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RF_WORDS(OPTION_RF_WORDS), + .OPTION_RESET_PC(OPTION_RESET_PC), + .OPTION_TCM_FETCHER(OPTION_TCM_FETCHER), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_MSYNC(FEATURE_MSYNC), + .FEATURE_PSYNC(FEATURE_PSYNC), + .FEATURE_CSYNC(FEATURE_CSYNC), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8), + .OPTION_SHIFTER(OPTION_SHIFTER) + ) + mor1kx_cpu + (/*AUTOINST*/ + // Outputs + .ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ibus_req_o (ibus_req_o), + .ibus_burst_o (ibus_burst_o), + .dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_req_o (dbus_req_o), + .dbus_bsel_o (dbus_bsel_o[3:0]), + .dbus_we_o (dbus_we_o), + .dbus_burst_o (dbus_burst_o), + .du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .du_ack_o (du_ack_o), + .du_stall_o (du_stall_o), + .spr_bus_addr_o (spr_bus_addr_o[15:0]), + .spr_bus_we_o (spr_bus_we_o), + .spr_bus_stb_o (spr_bus_stb_o), + .spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_sr_o (spr_sr_o[15:0]), + // Inputs + .clk (clk), + .rst (rst), + .ibus_err_i (ibus_err_i), + .ibus_ack_i (ibus_ack_i), + .ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .dbus_err_i (dbus_err_i), + .dbus_ack_i (dbus_ack_i), + .dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .irq_i (irq_i[31:0]), + .du_addr_i (du_addr_i[15:0]), + .du_stb_i (du_stb_i), + .du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .du_we_i (du_we_i), + .du_stall_i (du_stall_i), + .spr_bus_dat_dmmu_i (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dmmu_i (spr_bus_ack_dmmu_i), + .spr_bus_dat_immu_i (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_immu_i (spr_bus_ack_immu_i), + .spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_mac_i (spr_bus_ack_mac_i), + .spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pmu_i (spr_bus_ack_pmu_i), + .spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pcu_i (spr_bus_ack_pcu_i), + .spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_fpu_i (spr_bus_ack_fpu_i), + .multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0])); + + // synthesis translate_off +`ifndef SYNTHESIS + assign monitor_flag = monitor_flag_set ? 1 : + monitor_flag_clear ? 0 : + monitor_flag_sr; + assign monitor_clk = clk; + assign monitor_execute_insn = prontoespresso.mor1kx_cpu.insn_fetch_to_decode; + assign monitor_execute_advance = prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.execute_done; + assign monitor_flag_set = prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.ctrl_flag_set_i; + assign monitor_flag_clear = prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.ctrl_flag_clear_i; + assign monitor_flag_sr = prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.flag; + assign monitor_spr_sr = {16'd0,prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.spr_sr[15:`OR1K_SPR_SR_F+1], + // Use the locally calculated flag value + monitor_flag, + prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.spr_sr[`OR1K_SPR_SR_F-1:0]}; + assign monitor_execute_pc = prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.spr_ppc; + assign monitor_rf_result_in = prontoespresso.mor1kx_cpu.mor1kx_rf_espresso.result_i; + assign monitor_spr_esr = {16'd0,prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.spr_esr}; + assign monitor_spr_epcr = prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.spr_epcr; + assign monitor_spr_eear = prontoespresso.mor1kx_cpu.mor1kx_ctrl_prontoespresso.spr_eear; + assign monitor_branch_mispredict = 0; +`endif + // synthesis translate_on + + end + /* verilator lint_off WIDTH */ + if (OPTION_CPU!="CAPPUCCINO" && OPTION_CPU!="ESPRESSO" && + OPTION_CPU!="PRONTO_ESPRESSO") + /* verilator lint_on WIDTH */ + begin + initial begin + $display("Error: OPTION_CPU, %s, not valid", OPTION_CPU); + $finish(); + end + end // else: !if(OPTION_CPU=="ESPRESSO") + endgenerate + +endmodule // mor1kx_cpu diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_cappuccino.v new file mode 100644 index 0000000..f282374 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_cappuccino.v @@ -0,0 +1,1540 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: "Cappuccino" pipeline CPU module + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_cpu_cappuccino + #( + parameter OPTION_OPERAND_WIDTH = 32, + + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter OPTION_DCACHE_LIMIT_WIDTH = 32, + parameter OPTION_DCACHE_SNOOP = "NONE", + parameter FEATURE_DMMU = "NONE", + parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_DMMU_SET_WIDTH = 6, + parameter OPTION_DMMU_WAYS = 1, + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter OPTION_ICACHE_LIMIT_WIDTH = 32, + parameter FEATURE_IMMU = "NONE", + parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_IMMU_SET_WIDTH = 6, + parameter OPTION_IMMU_WAYS = 1, + parameter FEATURE_TIMER = "ENABLED", + parameter FEATURE_DEBUGUNIT = "NONE", + parameter FEATURE_PERFCOUNTERS = "NONE", + parameter FEATURE_MAC = "NONE", + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + + parameter FEATURE_PIC = "ENABLED", + parameter OPTION_PIC_TRIGGER = "LEVEL", + parameter OPTION_PIC_NMI_WIDTH = 0, + + parameter FEATURE_DSX = "NONE", + parameter FEATURE_OVERFLOW = "NONE", + parameter FEATURE_CARRY_FLAG = "ENABLED", + + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter OPTION_RF_CLEAR_ON_INIT = 0, + parameter OPTION_RF_NUM_SHADOW_GPR = 0, + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter OPTION_RF_WORDS = 32, + + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + + parameter FEATURE_MULTIPLIER = "THREESTAGE", + parameter FEATURE_DIVIDER = "NONE", + + parameter OPTION_SHIFTER = "BARREL", + + parameter FEATURE_ADDC = "NONE", + parameter FEATURE_SRA = "ENABLED", + parameter FEATURE_ROR = "NONE", + parameter FEATURE_EXT = "NONE", + parameter FEATURE_CMOV = "NONE", + parameter FEATURE_FFL1 = "NONE", + parameter FEATURE_MSYNC = "ENABLED", + parameter FEATURE_PSYNC = "NONE", + parameter FEATURE_CSYNC = "NONE", + + parameter FEATURE_ATOMIC = "ENABLED", + + parameter FEATURE_FPU = "NONE", // ENABLED|NONE: pipeline cappuccino + + parameter FEATURE_CUST1 = "NONE", + parameter FEATURE_CUST2 = "NONE", + parameter FEATURE_CUST3 = "NONE", + parameter FEATURE_CUST4 = "NONE", + parameter FEATURE_CUST5 = "NONE", + parameter FEATURE_CUST6 = "NONE", + parameter FEATURE_CUST7 = "NONE", + parameter FEATURE_CUST8 = "NONE", + + parameter FEATURE_STORE_BUFFER = "ENABLED", + parameter OPTION_STORE_BUFFER_DEPTH_WIDTH = 8, + + parameter FEATURE_MULTICORE = "NONE", + + parameter FEATURE_TRACEPORT_EXEC = "NONE" + ) + ( + input clk, + input rst, + + // Instruction bus + input ibus_err_i, + input ibus_ack_i, + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o, + output ibus_req_o, + output ibus_burst_o, + + // Data bus + input dbus_err_i, + input dbus_ack_i, + input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o, + output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o, + output dbus_req_o, + output [3:0] dbus_bsel_o, + output dbus_we_o, + output dbus_burst_o, + + // Interrupts + input [31:0] irq_i, + + // Debug interface + input [15:0] du_addr_i, + input du_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i, + input du_we_i, + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o, + output du_ack_o, + // Stall control from debug interface + input du_stall_i, + output du_stall_o, + + output reg traceport_exec_valid_o, + output reg [31:0] traceport_exec_pc_o, + output reg [`OR1K_INSN_WIDTH-1:0] traceport_exec_insn_o, + output [OPTION_OPERAND_WIDTH-1:0] traceport_exec_wbdata_o, + output [OPTION_RF_ADDR_WIDTH-1:0] traceport_exec_wbreg_o, + output traceport_exec_wben_o, + + // SPR accesses to external units (cache, mmu, etc.) + output [15:0] spr_bus_addr_o, + output spr_bus_we_o, + output spr_bus_stb_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i, + input spr_bus_ack_mac_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i, + input spr_bus_ack_pmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i, + input spr_bus_ack_pcu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i, + input spr_bus_ack_fpu_i, + output [15:0] spr_sr_o, + + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i, + input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i, + + input [31:0] snoop_adr_i, + input snoop_en_i + ); + + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_to_decode; + wire [`OR1K_INSN_WIDTH-1:0] insn_fetch_to_decode; + wire [OPTION_OPERAND_WIDTH-1:0] pc_decode_to_execute; + wire [OPTION_OPERAND_WIDTH-1:0] pc_execute_to_ctrl; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [OPTION_OPERAND_WIDTH-1:0] adder_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire [OPTION_OPERAND_WIDTH-1:0] alu_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire alu_valid_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire atomic_flag_clear_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire atomic_flag_set_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire branch_mispredict_o; // From mor1kx_branch_prediction of mor1kx_branch_prediction.v + wire carry_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire carry_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc_o;// From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_branch_exception_o;// From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_bubble_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_carry_clear_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_carry_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_carry_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_epcr_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_except_align_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_dbus_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_dpagefault_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_dtlb_miss_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_ibus_align_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_ibus_err_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_illegal_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_ipagefault_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_itlb_miss_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_syscall_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_except_trap_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_flag_clear_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_flag_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_flag_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [1:0] ctrl_lsu_length_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_lsu_zext_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_mfspr_ack_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_mtspr_ack_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_op_lsu_atomic_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_op_lsu_load_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_op_lsu_store_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_op_mfspr_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_op_msync_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_op_mtspr_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_op_mul_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_op_rfe_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_overflow_clear_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_overflow_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [`OR1K_FPCSR_WIDTH-1:0] ctrl_fpcsr_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_fpcsr_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [`OR1K_FPCSR_RM_SIZE-1:0] ctrl_fpu_round_mode_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire ctrl_rf_wb_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [OPTION_RF_ADDR_WIDTH-1:0] ctrl_rfd_adr_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire ctrl_valid_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire decode_adder_do_carry_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_adder_do_sub_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_branch_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] decode_branch_target_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire decode_bubble_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire decode_except_ibus_err_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire decode_except_illegal_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_except_ipagefault_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire decode_except_itlb_miss_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire decode_except_syscall_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_except_trap_o; // From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_IMM_WIDTH-1:0] decode_imm16_o; // From mor1kx_decode of mor1kx_decode.v + wire [OPTION_OPERAND_WIDTH-1:0] decode_immediate_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_immediate_sel_o; // From mor1kx_decode of mor1kx_decode.v + wire [9:0] decode_immjbr_upper_o; // From mor1kx_decode of mor1kx_decode.v + wire [1:0] decode_lsu_length_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_lsu_zext_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_add_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_alu_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_bf_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_bnf_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_branch_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_brcond_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_signed_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_unsigned_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_op_ffl1_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jal_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jbr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_atomic_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_load_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_store_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mfspr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_movhi_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_msync_o; // From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_FPUOP_WIDTH-1:0] decode_op_fpu_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mtspr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_signed_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_unsigned_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_op_rfe_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_setflag_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_shift_o; // From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_o;// From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_o;// From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_rf_wb_o; // From mor1kx_decode of mor1kx_decode.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire [OPTION_OPERAND_WIDTH-1:0] decode_rfa_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire [OPTION_OPERAND_WIDTH-1:0] decode_rfb_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_valid_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire doing_rfe_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire du_restart_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o;// From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire execute_adder_do_carry_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_adder_do_sub_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_bubble_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_except_ibus_align_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_except_ibus_err_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_except_illegal_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_except_ipagefault_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_except_itlb_miss_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_except_syscall_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_except_trap_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [`OR1K_IMM_WIDTH-1:0] execute_imm16_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] execute_immediate_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_immediate_sel_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [9:0] execute_immjbr_upper_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] execute_jal_result_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [1:0] execute_lsu_length_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_lsu_zext_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] execute_mispredict_target_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_add_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_alu_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_branch_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_brcond_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_div_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_div_signed_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_div_unsigned_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_ffl1_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_jal_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_jbr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_jr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_lsu_atomic_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_lsu_load_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_lsu_store_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_mfspr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_movhi_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_msync_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [`OR1K_FPUOP_WIDTH-1:0] execute_op_fpu_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_mtspr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_mul_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_mul_signed_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_mul_unsigned_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_rfe_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_setflag_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_op_shift_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] execute_opc_alu_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] execute_opc_alu_secondary_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [`OR1K_OPCODE_WIDTH-1:0] execute_opc_insn_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_predicted_flag_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_rf_wb_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] execute_rfa_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] execute_rfb_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v + wire [OPTION_RF_ADDR_WIDTH-1:0] execute_rfd_adr_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v + wire execute_valid_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire fetch_exception_taken_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire fetch_rf_adr_valid_o; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire fetch_valid_o; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire flag_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire flag_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire lsu_except_align_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire lsu_except_dbus_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire lsu_except_dpagefault_o;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire lsu_except_dtlb_miss_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] lsu_result_o;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire lsu_valid_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire msync_stall_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] mul_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire overflow_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire overflow_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire[`OR1K_FPCSR_WIDTH-1:0] fpcsr_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire fpcsr_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire padv_ctrl_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire padv_decode_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire padv_execute_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire padv_fetch_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire pipeline_flush_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v + wire predicted_flag_o; // From mor1kx_branch_prediction of mor1kx_branch_prediction.v + wire [OPTION_OPERAND_WIDTH-1:0] rf_result_o; // From mor1kx_wb_mux_cappuccino of mor1kx_wb_mux_cappuccino.v + wire spr_bus_ack_dc_i; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire spr_bus_ack_dmmu_i; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire spr_bus_ack_ic_i; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire spr_bus_ack_immu_i; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v + wire spr_gpr_ack_o; // From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_gpr_dat_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v + wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_epcr_o;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire store_buffer_err_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v + wire wb_rf_wb_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + wire [OPTION_RF_ADDR_WIDTH-1:0] wb_rfd_adr_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v + // End of automatics + + /* mor1kx_fetch_cappuccino AUTO_TEMPLATE ( + .padv_i (padv_fetch_o), + .padv_ctrl_i (padv_ctrl_o), + .decode_branch_i (decode_branch_o), + .decode_branch_target_i (decode_branch_target_o), + .ctrl_branch_exception_i (ctrl_branch_exception_o), + .ctrl_branch_except_pc_i (ctrl_branch_except_pc_o), + .doing_rfe_i (doing_rfe_o), + .pipeline_flush_i (pipeline_flush_o), + .pc_decode_o (pc_fetch_to_decode), + .decode_insn_o (insn_fetch_to_decode), + .du_restart_pc_i (du_restart_pc_o), + .du_restart_i (du_restart_o), + .decode_op_brcond_i (decode_op_brcond_o), + .branch_mispredict_i (branch_mispredict_o), + .execute_mispredict_target_i (execute_mispredict_target_o), + .spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_ic_o (spr_bus_ack_ic_i), + .spr_bus_dat_immu_o (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_immu_o (spr_bus_ack_immu_i), + .spr_bus_addr_i (spr_bus_addr_o[15:0]), + .spr_bus_we_i (spr_bus_we_o), + .spr_bus_stb_i (spr_bus_stb_o), + .spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]), + .immu_enable_i (spr_sr_o[`OR1K_SPR_SR_IME]), + .supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]), + ); */ + mor1kx_fetch_cappuccino + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .OPTION_ICACHE_LIMIT_WIDTH(OPTION_ICACHE_LIMIT_WIDTH), + .FEATURE_IMMU(FEATURE_IMMU), + .FEATURE_IMMU_HW_TLB_RELOAD(FEATURE_IMMU_HW_TLB_RELOAD), + .OPTION_IMMU_SET_WIDTH(OPTION_IMMU_SET_WIDTH), + .OPTION_IMMU_WAYS(OPTION_IMMU_WAYS) + ) + mor1kx_fetch_cappuccino + (/*AUTOINST*/ + // Outputs + .spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), // Templated + .spr_bus_ack_ic_o (spr_bus_ack_ic_i), // Templated + .spr_bus_dat_immu_o (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), // Templated + .spr_bus_ack_immu_o (spr_bus_ack_immu_i), // Templated + .ibus_req_o (ibus_req_o), + .ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ibus_burst_o (ibus_burst_o), + .pc_decode_o (pc_fetch_to_decode), // Templated + .decode_insn_o (insn_fetch_to_decode), // Templated + .fetch_valid_o (fetch_valid_o), + .fetch_rfa_adr_o (fetch_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .fetch_rfb_adr_o (fetch_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .fetch_rf_adr_valid_o (fetch_rf_adr_valid_o), + .decode_except_ibus_err_o (decode_except_ibus_err_o), + .decode_except_itlb_miss_o (decode_except_itlb_miss_o), + .decode_except_ipagefault_o (decode_except_ipagefault_o), + .fetch_exception_taken_o (fetch_exception_taken_o), + // Inputs + .clk (clk), + .rst (rst), + .spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated + .spr_bus_we_i (spr_bus_we_o), // Templated + .spr_bus_stb_i (spr_bus_stb_o), // Templated + .spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), // Templated + .ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]), // Templated + .immu_enable_i (spr_sr_o[`OR1K_SPR_SR_IME]), // Templated + .supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]), // Templated + .ibus_err_i (ibus_err_i), + .ibus_ack_i (ibus_ack_i), + .ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .padv_i (padv_fetch_o), // Templated + .padv_ctrl_i (padv_ctrl_o), // Templated + .decode_branch_i (decode_branch_o), // Templated + .decode_branch_target_i (decode_branch_target_o), // Templated + .ctrl_branch_exception_i (ctrl_branch_exception_o), // Templated + .ctrl_branch_except_pc_i (ctrl_branch_except_pc_o), // Templated + .du_restart_i (du_restart_o), // Templated + .du_restart_pc_i (du_restart_pc_o), // Templated + .decode_op_brcond_i (decode_op_brcond_o), // Templated + .branch_mispredict_i (branch_mispredict_o), // Templated + .execute_mispredict_target_i (execute_mispredict_target_o), // Templated + .pipeline_flush_i (pipeline_flush_o), // Templated + .doing_rfe_i (doing_rfe_o)); // Templated + + /* mor1kx_decode AUTO_TEMPLATE ( + .decode_insn_i (insn_fetch_to_decode), + ); */ + mor1kx_decode + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_MSYNC(FEATURE_MSYNC), + .FEATURE_PSYNC(FEATURE_PSYNC), + .FEATURE_CSYNC(FEATURE_CSYNC), + .FEATURE_ATOMIC(FEATURE_ATOMIC), + .FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: decode instance + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8) + ) + mor1kx_decode + (/*AUTOINST*/ + // Outputs + .decode_opc_alu_o (decode_opc_alu_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .decode_opc_alu_secondary_o (decode_opc_alu_secondary_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .decode_imm16_o (decode_imm16_o[`OR1K_IMM_WIDTH-1:0]), + .decode_immediate_o (decode_immediate_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_immediate_sel_o (decode_immediate_sel_o), + .decode_immjbr_upper_o (decode_immjbr_upper_o[9:0]), + .decode_rfd_adr_o (decode_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rfa_adr_o (decode_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rfb_adr_o (decode_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rf_wb_o (decode_rf_wb_o), + .decode_op_jbr_o (decode_op_jbr_o), + .decode_op_jr_o (decode_op_jr_o), + .decode_op_jal_o (decode_op_jal_o), + .decode_op_bf_o (decode_op_bf_o), + .decode_op_bnf_o (decode_op_bnf_o), + .decode_op_brcond_o (decode_op_brcond_o), + .decode_op_branch_o (decode_op_branch_o), + .decode_op_alu_o (decode_op_alu_o), + .decode_op_lsu_load_o (decode_op_lsu_load_o), + .decode_op_lsu_store_o (decode_op_lsu_store_o), + .decode_op_lsu_atomic_o (decode_op_lsu_atomic_o), + .decode_lsu_length_o (decode_lsu_length_o[1:0]), + .decode_lsu_zext_o (decode_lsu_zext_o), + .decode_op_mfspr_o (decode_op_mfspr_o), + .decode_op_mtspr_o (decode_op_mtspr_o), + .decode_op_rfe_o (decode_op_rfe_o), + .decode_op_setflag_o (decode_op_setflag_o), + .decode_op_add_o (decode_op_add_o), + .decode_op_mul_o (decode_op_mul_o), + .decode_op_mul_signed_o (decode_op_mul_signed_o), + .decode_op_mul_unsigned_o (decode_op_mul_unsigned_o), + .decode_op_div_o (decode_op_div_o), + .decode_op_div_signed_o (decode_op_div_signed_o), + .decode_op_div_unsigned_o (decode_op_div_unsigned_o), + .decode_op_shift_o (decode_op_shift_o), + .decode_op_ffl1_o (decode_op_ffl1_o), + .decode_op_movhi_o (decode_op_movhi_o), + .decode_op_msync_o (decode_op_msync_o), + .decode_op_fpu_o (decode_op_fpu_o), + .decode_adder_do_sub_o (decode_adder_do_sub_o), + .decode_adder_do_carry_o (decode_adder_do_carry_o), + .decode_except_illegal_o (decode_except_illegal_o), + .decode_except_syscall_o (decode_except_syscall_o), + .decode_except_trap_o (decode_except_trap_o), + .decode_opc_insn_o (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .decode_insn_i (insn_fetch_to_decode)); // Templated + + /* mor1kx_decode_execute_cappuccino AUTO_TEMPLATE ( + .padv_i (padv_decode_o), + .pc_decode_i (pc_fetch_to_decode), + .decode_rfb_i (decode_rfb_o), + .execute_rfb_i (execute_rfb_o), + .predicted_flag_i (predicted_flag_o), + .flag_i (ctrl_flag_o), + .pc_execute_o (pc_decode_to_execute), + .pipeline_flush_i (pipeline_flush_o), + .decode_opc_alu_i (decode_opc_alu_o), + .decode_opc_alu_secondary_i (decode_opc_alu_secondary_o), + .decode_imm16_i (decode_imm16_o), + .decode_immediate_i (decode_immediate_o), + .decode_immediate_sel_i (decode_immediate_sel_o), + .decode_immjbr_upper_i (decode_immjbr_upper_o), + .decode_adder_do_sub_i (decode_adder_do_sub_o), + .decode_adder_do_carry_i (decode_adder_do_carry_o), + .decode_rfd_adr_i (decode_rfd_adr_o), + .decode_rfa_adr_i (decode_rfa_adr_o), + .decode_rfb_adr_i (decode_rfb_adr_o), + .ctrl_rfd_adr_i (ctrl_rfd_adr_o), + .ctrl_op_lsu_load_i (ctrl_op_lsu_load_o), + .ctrl_op_mfspr_i (ctrl_op_mfspr_o), + .ctrl_op_mul_i (ctrl_op_mul_o), + .decode_rf_wb_i (decode_rf_wb_o), + .decode_op_alu_i (decode_op_alu_o), + .decode_op_setflag_i (decode_op_setflag_o), + .decode_op_jbr_i (decode_op_jbr_o), + .decode_op_jr_i (decode_op_jr_o), + .decode_op_jal_i (decode_op_jal_o), + .decode_op_bf_i (decode_op_bf_o), + .decode_op_bnf_i (decode_op_bnf_o), + .decode_op_brcond_i (decode_op_brcond_o), + .decode_op_branch_i (decode_op_branch_o), + .decode_op_lsu_load_i (decode_op_lsu_load_o), + .decode_op_lsu_store_i (decode_op_lsu_store_o), + .decode_op_lsu_atomic_i (decode_op_lsu_atomic_o), + .decode_lsu_length_i (decode_lsu_length_o[1:0]), + .decode_lsu_zext_i (decode_lsu_zext_o), + .decode_op_mfspr_i (decode_op_mfspr_o), + .decode_op_mtspr_i (decode_op_mtspr_o), + .decode_op_rfe_i (decode_op_rfe_o), + .decode_op_add_i (decode_op_add_o), + .decode_op_mul_i (decode_op_mul_o), + .decode_op_mul_signed_i (decode_op_mul_signed_o), + .decode_op_mul_unsigned_i (decode_op_mul_unsigned_o), + .decode_op_div_i (decode_op_div_o), + .decode_op_div_signed_i (decode_op_div_signed_o), + .decode_op_div_unsigned_i (decode_op_div_unsigned_o), + .decode_op_shift_i (decode_op_shift_o), + .decode_op_ffl1_i (decode_op_ffl1_o), + .decode_op_movhi_i (decode_op_movhi_o), + .decode_op_msync_i (decode_op_msync_o), + .decode_op_fpu_i (decode_op_fpu_o), + .decode_opc_insn_i (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]), + .decode_except_ibus_err_i (decode_except_ibus_err_o), + .decode_except_itlb_miss_i (decode_except_itlb_miss_o), + .decode_except_ipagefault_i (decode_except_ipagefault_o), + .decode_except_illegal_i (decode_except_illegal_o), + .decode_except_syscall_i (decode_except_syscall_o), + .decode_except_trap_i (decode_except_trap_o), + ); */ + mor1kx_decode_execute_cappuccino + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: decode_execute instance + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER) + ) + mor1kx_decode_execute_cappuccino + (/*AUTOINST*/ + // Outputs + .execute_predicted_flag_o (execute_predicted_flag_o), + .execute_mispredict_target_o (execute_mispredict_target_o[OPTION_OPERAND_WIDTH-1:0]), + .execute_opc_alu_o (execute_opc_alu_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .execute_opc_alu_secondary_o (execute_opc_alu_secondary_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .execute_imm16_o (execute_imm16_o[`OR1K_IMM_WIDTH-1:0]), + .execute_immediate_o (execute_immediate_o[OPTION_OPERAND_WIDTH-1:0]), + .execute_immediate_sel_o (execute_immediate_sel_o), + .execute_adder_do_sub_o (execute_adder_do_sub_o), + .execute_adder_do_carry_o (execute_adder_do_carry_o), + .execute_immjbr_upper_o (execute_immjbr_upper_o[9:0]), + .execute_rfd_adr_o (execute_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .execute_rf_wb_o (execute_rf_wb_o), + .execute_op_alu_o (execute_op_alu_o), + .execute_op_setflag_o (execute_op_setflag_o), + .execute_op_jbr_o (execute_op_jbr_o), + .execute_op_jr_o (execute_op_jr_o), + .execute_op_jal_o (execute_op_jal_o), + .execute_op_brcond_o (execute_op_brcond_o), + .execute_op_branch_o (execute_op_branch_o), + .execute_op_lsu_load_o (execute_op_lsu_load_o), + .execute_op_lsu_store_o (execute_op_lsu_store_o), + .execute_op_lsu_atomic_o (execute_op_lsu_atomic_o), + .execute_lsu_length_o (execute_lsu_length_o[1:0]), + .execute_lsu_zext_o (execute_lsu_zext_o), + .execute_op_mfspr_o (execute_op_mfspr_o), + .execute_op_mtspr_o (execute_op_mtspr_o), + .execute_op_rfe_o (execute_op_rfe_o), + .execute_op_add_o (execute_op_add_o), + .execute_op_mul_o (execute_op_mul_o), + .execute_op_mul_signed_o (execute_op_mul_signed_o), + .execute_op_mul_unsigned_o (execute_op_mul_unsigned_o), + .execute_op_div_o (execute_op_div_o), + .execute_op_div_signed_o (execute_op_div_signed_o), + .execute_op_div_unsigned_o (execute_op_div_unsigned_o), + .execute_op_shift_o (execute_op_shift_o), + .execute_op_ffl1_o (execute_op_ffl1_o), + .execute_op_movhi_o (execute_op_movhi_o), + .execute_op_msync_o (execute_op_msync_o), + .execute_op_fpu_o (execute_op_fpu_o), + .execute_jal_result_o (execute_jal_result_o[OPTION_OPERAND_WIDTH-1:0]), + .execute_opc_insn_o (execute_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]), + .decode_branch_o (decode_branch_o), + .decode_branch_target_o (decode_branch_target_o[OPTION_OPERAND_WIDTH-1:0]), + .execute_except_ibus_err_o (execute_except_ibus_err_o), + .execute_except_itlb_miss_o (execute_except_itlb_miss_o), + .execute_except_ipagefault_o (execute_except_ipagefault_o), + .execute_except_illegal_o (execute_except_illegal_o), + .execute_except_ibus_align_o (execute_except_ibus_align_o), + .execute_except_syscall_o (execute_except_syscall_o), + .execute_except_trap_o (execute_except_trap_o), + .pc_execute_o (pc_decode_to_execute), // Templated + .decode_valid_o (decode_valid_o), + .decode_bubble_o (decode_bubble_o), + .execute_bubble_o (execute_bubble_o), + // Inputs + .clk (clk), + .rst (rst), + .padv_i (padv_decode_o), // Templated + .pc_decode_i (pc_fetch_to_decode), // Templated + .decode_rfb_i (decode_rfb_o), // Templated + .execute_rfb_i (execute_rfb_o), // Templated + .predicted_flag_i (predicted_flag_o), // Templated + .pipeline_flush_i (pipeline_flush_o), // Templated + .decode_opc_alu_i (decode_opc_alu_o), // Templated + .decode_opc_alu_secondary_i (decode_opc_alu_secondary_o), // Templated + .decode_imm16_i (decode_imm16_o), // Templated + .decode_immediate_i (decode_immediate_o), // Templated + .decode_immediate_sel_i (decode_immediate_sel_o), // Templated + .decode_adder_do_sub_i (decode_adder_do_sub_o), // Templated + .decode_adder_do_carry_i (decode_adder_do_carry_o), // Templated + .decode_immjbr_upper_i (decode_immjbr_upper_o), // Templated + .decode_rfd_adr_i (decode_rfd_adr_o), // Templated + .decode_rfa_adr_i (decode_rfa_adr_o), // Templated + .decode_rfb_adr_i (decode_rfb_adr_o), // Templated + .ctrl_rfd_adr_i (ctrl_rfd_adr_o), // Templated + .ctrl_op_lsu_load_i (ctrl_op_lsu_load_o), // Templated + .ctrl_op_mfspr_i (ctrl_op_mfspr_o), // Templated + .ctrl_op_mul_i (ctrl_op_mul_o), // Templated + .decode_rf_wb_i (decode_rf_wb_o), // Templated + .decode_op_alu_i (decode_op_alu_o), // Templated + .decode_op_setflag_i (decode_op_setflag_o), // Templated + .decode_op_jbr_i (decode_op_jbr_o), // Templated + .decode_op_jr_i (decode_op_jr_o), // Templated + .decode_op_jal_i (decode_op_jal_o), // Templated + .decode_op_bf_i (decode_op_bf_o), // Templated + .decode_op_bnf_i (decode_op_bnf_o), // Templated + .decode_op_brcond_i (decode_op_brcond_o), // Templated + .decode_op_branch_i (decode_op_branch_o), // Templated + .decode_op_lsu_load_i (decode_op_lsu_load_o), // Templated + .decode_op_lsu_store_i (decode_op_lsu_store_o), // Templated + .decode_op_lsu_atomic_i (decode_op_lsu_atomic_o), // Templated + .decode_lsu_length_i (decode_lsu_length_o[1:0]), // Templated + .decode_lsu_zext_i (decode_lsu_zext_o), // Templated + .decode_op_mfspr_i (decode_op_mfspr_o), // Templated + .decode_op_mtspr_i (decode_op_mtspr_o), // Templated + .decode_op_rfe_i (decode_op_rfe_o), // Templated + .decode_op_add_i (decode_op_add_o), // Templated + .decode_op_mul_i (decode_op_mul_o), // Templated + .decode_op_mul_signed_i (decode_op_mul_signed_o), // Templated + .decode_op_mul_unsigned_i (decode_op_mul_unsigned_o), // Templated + .decode_op_div_i (decode_op_div_o), // Templated + .decode_op_div_signed_i (decode_op_div_signed_o), // Templated + .decode_op_div_unsigned_i (decode_op_div_unsigned_o), // Templated + .decode_op_shift_i (decode_op_shift_o), // Templated + .decode_op_ffl1_i (decode_op_ffl1_o), // Templated + .decode_op_movhi_i (decode_op_movhi_o), // Templated + .decode_op_msync_i (decode_op_msync_o), // Templated + .decode_op_fpu_i (decode_op_fpu_o), // Templated + .decode_opc_insn_i (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]), // Templated + .decode_except_ibus_err_i (decode_except_ibus_err_o), // Templated + .decode_except_itlb_miss_i (decode_except_itlb_miss_o), // Templated + .decode_except_ipagefault_i (decode_except_ipagefault_o), // Templated + .decode_except_illegal_i (decode_except_illegal_o), // Templated + .decode_except_syscall_i (decode_except_syscall_o), // Templated + .decode_except_trap_i (decode_except_trap_o)); // Templated + + /* mor1kx_branch_prediction AUTO_TEMPLATE ( + .op_bf_i (decode_op_bf_o), + .op_bnf_i (decode_op_bnf_o), + .immjbr_upper_i (decode_immjbr_upper_o), + .prev_op_brcond_i (execute_op_brcond_o), + .prev_predicted_flag_i (execute_predicted_flag_o), + .flag_i (ctrl_flag_o), + );*/ + mor1kx_branch_prediction + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH) + ) + mor1kx_branch_prediction + (/*AUTOINST*/ + // Outputs + .predicted_flag_o (predicted_flag_o), + .branch_mispredict_o (branch_mispredict_o), + // Inputs + .clk (clk), + .rst (rst), + .op_bf_i (decode_op_bf_o), // Templated + .op_bnf_i (decode_op_bnf_o), // Templated + .immjbr_upper_i (decode_immjbr_upper_o), // Templated + .prev_op_brcond_i (execute_op_brcond_o), // Templated + .prev_predicted_flag_i (execute_predicted_flag_o), // Templated + .flag_i (ctrl_flag_o)); // Templated + + /* mor1kx_execute_alu AUTO_TEMPLATE ( + .padv_decode_i (padv_decode_o), + .padv_execute_i (padv_execute_o), + .padv_ctrl_i (padv_ctrl_o), + .opc_alu_i (execute_opc_alu_o), + .opc_alu_secondary_i (execute_opc_alu_secondary_o), + .imm16_i (execute_imm16_o), + .decode_immediate_i (decode_immediate_o), + .decode_immediate_sel_i (decode_immediate_sel_o), + .immediate_i (execute_immediate_o), + .immediate_sel_i (execute_immediate_sel_o), + .decode_valid_i (decode_valid_o), + .decode_op_mul_i (decode_op_mul_o), + .op_alu_i (execute_op_alu_o), + .op_add_i (execute_op_add_o), + .op_mul_i (execute_op_mul_o), + .op_mul_signed_i (execute_op_mul_signed_o), + .op_mul_unsigned_i (execute_op_mul_unsigned_o), + .op_div_i (execute_op_div_o), + .op_div_signed_i (execute_op_div_signed_o), + .op_div_unsigned_i (execute_op_div_unsigned_o), + .op_shift_i (execute_op_shift_o), + .op_ffl1_i (execute_op_ffl1_o), + .op_setflag_i (execute_op_setflag_o), + .op_mtspr_i (execute_op_mtspr_o), + .op_mfspr_i (execute_op_mfspr_o), + .op_movhi_i (execute_op_movhi_o), + .op_fpu_i (execute_op_fpu_o), + .fpu_round_mode_i (ctrl_fpu_round_mode_o), + .op_jbr_i (execute_op_jbr_o), + .op_jr_i (execute_op_jr_o), + .immjbr_upper_i (execute_immjbr_upper_o), + .pc_execute_i (pc_decode_to_execute), + .adder_do_sub_i (execute_adder_do_sub_o), + .adder_do_carry_i (execute_adder_do_carry_o), + .decode_rfa_i (decode_rfa_o), + .decode_rfb_i (decode_rfb_o), + .rfa_i (execute_rfa_o), + .rfb_i (execute_rfb_o), + .flag_i (ctrl_flag_o), + .carry_i (ctrl_carry_o), + ); */ + mor1kx_execute_alu + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .FEATURE_OVERFLOW(FEATURE_OVERFLOW), + .FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8), + .FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: execute_alu instance + .OPTION_SHIFTER(OPTION_SHIFTER), + .CALCULATE_BRANCH_DEST("FALSE") + ) + mor1kx_execute_alu + (/*AUTOINST*/ + // Outputs + .flag_set_o (flag_set_o), + .flag_clear_o (flag_clear_o), + .carry_set_o (carry_set_o), + .carry_clear_o (carry_clear_o), + .overflow_set_o (overflow_set_o), + .overflow_clear_o (overflow_clear_o), + .fpcsr_o (fpcsr_o), + .fpcsr_set_o (fpcsr_set_o), + .alu_result_o (alu_result_o[OPTION_OPERAND_WIDTH-1:0]), + .alu_valid_o (alu_valid_o), + .mul_result_o (mul_result_o[OPTION_OPERAND_WIDTH-1:0]), + .adder_result_o (adder_result_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .padv_decode_i (padv_decode_o), // Templated + .padv_execute_i (padv_execute_o), // Templated + .padv_ctrl_i (padv_ctrl_o), // Templated + .pipeline_flush_i (pipeline_flush_o), + .opc_alu_i (execute_opc_alu_o), // Templated + .opc_alu_secondary_i (execute_opc_alu_secondary_o), // Templated + .imm16_i (execute_imm16_o), // Templated + .immediate_i (execute_immediate_o), // Templated + .immediate_sel_i (execute_immediate_sel_o), // Templated + .decode_immediate_i (decode_immediate_o), // Templated + .decode_immediate_sel_i (decode_immediate_sel_o), // Templated + .decode_valid_i (decode_valid_o), // Templated + .decode_op_mul_i (decode_op_mul_o), // Templated + .op_alu_i (execute_op_alu_o), // Templated + .op_add_i (execute_op_add_o), // Templated + .op_mul_i (execute_op_mul_o), // Templated + .op_mul_signed_i (execute_op_mul_signed_o), // Templated + .op_mul_unsigned_i (execute_op_mul_unsigned_o), // Templated + .op_div_i (execute_op_div_o), // Templated + .op_div_signed_i (execute_op_div_signed_o), // Templated + .op_div_unsigned_i (execute_op_div_unsigned_o), // Templated + .op_shift_i (execute_op_shift_o), // Templated + .op_ffl1_i (execute_op_ffl1_o), // Templated + .op_setflag_i (execute_op_setflag_o), // Templated + .op_mtspr_i (execute_op_mtspr_o), // Templated + .op_mfspr_i (execute_op_mfspr_o), // Templated + .op_movhi_i (execute_op_movhi_o), // Templated + .op_fpu_i (execute_op_fpu_o), // Templated + .fpu_round_mode_i (ctrl_fpu_round_mode_o), // Templated + .op_jbr_i (execute_op_jbr_o), // Templated + .op_jr_i (execute_op_jr_o), // Templated + .immjbr_upper_i (execute_immjbr_upper_o), // Templated + .pc_execute_i (pc_decode_to_execute), // Templated + .adder_do_sub_i (execute_adder_do_sub_o), // Templated + .adder_do_carry_i (execute_adder_do_carry_o), // Templated + .decode_rfa_i (decode_rfa_o), // Templated + .decode_rfb_i (decode_rfb_o), // Templated + .rfa_i (execute_rfa_o), // Templated + .rfb_i (execute_rfb_o), // Templated + .flag_i (ctrl_flag_o), // Templated + .carry_i (ctrl_carry_o)); // Templated + + + /* mor1kx_lsu_cappuccino AUTO_TEMPLATE ( + .padv_execute_i (padv_execute_o), + .padv_ctrl_i (padv_ctrl_o), + .decode_valid_i (decode_valid_o), + .exec_lsu_adr_i (adder_result_o), + .ctrl_lsu_adr_i (ctrl_lsu_adr_o), + .ctrl_rfb_i (ctrl_rfb_o), + .exec_op_lsu_load_i (execute_op_lsu_load_o), + .exec_op_lsu_store_i (execute_op_lsu_store_o), + .exec_op_lsu_atomic_i (execute_op_lsu_atomic_o), + .ctrl_op_lsu_load_i (ctrl_op_lsu_load_o), + .ctrl_op_lsu_store_i (ctrl_op_lsu_store_o), + .ctrl_op_lsu_atomic_i (ctrl_op_lsu_atomic_o), + .ctrl_op_msync_i (ctrl_op_msync_o), + .ctrl_lsu_length_i (ctrl_lsu_length_o), + .ctrl_lsu_zext_i (ctrl_lsu_zext_o), + .ctrl_epcr_i (ctrl_epcr_o), + .pipeline_flush_i (pipeline_flush_o), + .dc_enable_i (spr_sr_o[`OR1K_SPR_SR_DCE]), + .dmmu_enable_i (spr_sr_o[`OR1K_SPR_SR_DME]), + .supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]), + .spr_bus_dat_dc_o (spr_bus_dat_dc_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dc_o (spr_bus_ack_dc_i), + .spr_bus_dat_dmmu_o (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dmmu_o (spr_bus_ack_dmmu_i), + .spr_bus_addr_i (spr_bus_addr_o[15:0]), + .spr_bus_we_i (spr_bus_we_o), + .spr_bus_stb_i (spr_bus_stb_o), + .spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + ); */ + mor1kx_lsu_cappuccino + #( + .FEATURE_DATACACHE(FEATURE_DATACACHE), + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .OPTION_DCACHE_LIMIT_WIDTH(OPTION_DCACHE_LIMIT_WIDTH), + .OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP), + .FEATURE_DMMU(FEATURE_DMMU), + .FEATURE_DMMU_HW_TLB_RELOAD(FEATURE_DMMU_HW_TLB_RELOAD), + .OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH), + .OPTION_DMMU_WAYS(OPTION_DMMU_WAYS), + .FEATURE_STORE_BUFFER(FEATURE_STORE_BUFFER), + .OPTION_STORE_BUFFER_DEPTH_WIDTH(OPTION_STORE_BUFFER_DEPTH_WIDTH), + .FEATURE_ATOMIC(FEATURE_ATOMIC) + ) + mor1kx_lsu_cappuccino + (/*AUTOINST*/ + // Outputs + .store_buffer_epcr_o (store_buffer_epcr_o[OPTION_OPERAND_WIDTH-1:0]), + .lsu_result_o (lsu_result_o[OPTION_OPERAND_WIDTH-1:0]), + .lsu_valid_o (lsu_valid_o), + .lsu_except_dbus_o (lsu_except_dbus_o), + .lsu_except_align_o (lsu_except_align_o), + .lsu_except_dtlb_miss_o (lsu_except_dtlb_miss_o), + .lsu_except_dpagefault_o (lsu_except_dpagefault_o), + .store_buffer_err_o (store_buffer_err_o), + .atomic_flag_set_o (atomic_flag_set_o), + .atomic_flag_clear_o (atomic_flag_clear_o), + .msync_stall_o (msync_stall_o), + .spr_bus_dat_dc_o (spr_bus_dat_dc_i[OPTION_OPERAND_WIDTH-1:0]), // Templated + .spr_bus_ack_dc_o (spr_bus_ack_dc_i), // Templated + .spr_bus_dat_dmmu_o (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), // Templated + .spr_bus_ack_dmmu_o (spr_bus_ack_dmmu_i), // Templated + .dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_req_o (dbus_req_o), + .dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_bsel_o (dbus_bsel_o[3:0]), + .dbus_we_o (dbus_we_o), + .dbus_burst_o (dbus_burst_o), + // Inputs + .clk (clk), + .rst (rst), + .padv_execute_i (padv_execute_o), // Templated + .padv_ctrl_i (padv_ctrl_o), // Templated + .decode_valid_i (decode_valid_o), // Templated + .exec_lsu_adr_i (adder_result_o), // Templated + .ctrl_lsu_adr_i (ctrl_lsu_adr_o), // Templated + .ctrl_rfb_i (ctrl_rfb_o), // Templated + .exec_op_lsu_load_i (execute_op_lsu_load_o), // Templated + .exec_op_lsu_store_i (execute_op_lsu_store_o), // Templated + .exec_op_lsu_atomic_i (execute_op_lsu_atomic_o), // Templated + .ctrl_op_lsu_load_i (ctrl_op_lsu_load_o), // Templated + .ctrl_op_lsu_store_i (ctrl_op_lsu_store_o), // Templated + .ctrl_op_lsu_atomic_i (ctrl_op_lsu_atomic_o), // Templated + .ctrl_op_msync_i (ctrl_op_msync_o), // Templated + .ctrl_lsu_length_i (ctrl_lsu_length_o), // Templated + .ctrl_lsu_zext_i (ctrl_lsu_zext_o), // Templated + .ctrl_epcr_i (ctrl_epcr_o), // Templated + .spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated + .spr_bus_we_i (spr_bus_we_o), // Templated + .spr_bus_stb_i (spr_bus_stb_o), // Templated + .spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), // Templated + .dc_enable_i (spr_sr_o[`OR1K_SPR_SR_DCE]), // Templated + .dmmu_enable_i (spr_sr_o[`OR1K_SPR_SR_DME]), // Templated + .supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]), // Templated + .dbus_err_i (dbus_err_i), + .dbus_ack_i (dbus_ack_i), + .dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .pipeline_flush_i (pipeline_flush_o), // Templated + .snoop_adr_i (snoop_adr_i[31:0]), + .snoop_en_i (snoop_en_i)); + + + /* mor1kx_wb_mux_cappuccino AUTO_TEMPLATE ( + .alu_result_i (ctrl_alu_result_o), + .lsu_result_i (lsu_result_o), + .mul_result_i (mul_result_o), + .spr_i (mfspr_dat_o), + .op_mul_i (ctrl_op_mul_o), + .op_lsu_load_i (ctrl_op_lsu_load_o), + .pc_i (pc_execute_to_ctrl), + .op_mfspr_i (ctrl_op_mfspr_o), + ); */ + mor1kx_wb_mux_cappuccino + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH) + ) + mor1kx_wb_mux_cappuccino + (/*AUTOINST*/ + // Outputs + .rf_result_o (rf_result_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .alu_result_i (ctrl_alu_result_o), // Templated + .lsu_result_i (lsu_result_o), // Templated + .mul_result_i (mul_result_o), // Templated + .spr_i (mfspr_dat_o), // Templated + .op_mul_i (ctrl_op_mul_o), // Templated + .op_lsu_load_i (ctrl_op_lsu_load_o), // Templated + .op_mfspr_i (ctrl_op_mfspr_o)); // Templated + + + /* mor1kx_rf_cappuccino AUTO_TEMPLATE ( + .padv_decode_i (padv_decode_o), + .padv_execute_i (padv_execute_o), + .padv_ctrl_i (padv_ctrl_o), + .fetch_rf_adr_valid_i (fetch_rf_adr_valid_o), + .fetch_rfa_adr_i (fetch_rfa_adr_o), + .fetch_rfb_adr_i (fetch_rfb_adr_o), + .decode_valid_i (decode_valid_o), + .decode_rfa_adr_i (decode_rfa_adr_o), + .decode_rfb_adr_i (decode_rfb_adr_o), + .execute_rfd_adr_i (execute_rfd_adr_o), + .ctrl_rfd_adr_i (ctrl_rfd_adr_o), + .wb_rfd_adr_i (wb_rfd_adr_o), + .spr_bus_addr_i (spr_bus_addr_o[15:0]), + .spr_bus_stb_i (spr_bus_stb_o), + .spr_bus_we_i (spr_bus_we_o), + .spr_bus_dat_i (spr_bus_dat_o), + .execute_rf_wb_i (execute_rf_wb_o), + .ctrl_rf_wb_i (ctrl_rf_wb_o), + .wb_rf_wb_i (wb_rf_wb_o), + .result_i (rf_result_o), + .ctrl_alu_result_i (ctrl_alu_result_o), + .pipeline_flush_i (pipeline_flush_o), + ); */ + mor1kx_rf_cappuccino + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS), + .OPTION_RF_CLEAR_ON_INIT(OPTION_RF_CLEAR_ON_INIT), + .OPTION_RF_NUM_SHADOW_GPR(OPTION_RF_NUM_SHADOW_GPR), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RF_WORDS(OPTION_RF_WORDS), + .FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT) + ) + mor1kx_rf_cappuccino + (/*AUTOINST*/ + // Outputs + .spr_gpr_ack_o (spr_gpr_ack_o), + .spr_gpr_dat_o (spr_gpr_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_rfa_o (decode_rfa_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_rfb_o (decode_rfb_o[OPTION_OPERAND_WIDTH-1:0]), + .execute_rfa_o (execute_rfa_o[OPTION_OPERAND_WIDTH-1:0]), + .execute_rfb_o (execute_rfb_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .padv_decode_i (padv_decode_o), // Templated + .padv_execute_i (padv_execute_o), // Templated + .padv_ctrl_i (padv_ctrl_o), // Templated + .decode_valid_i (decode_valid_o), // Templated + .fetch_rf_adr_valid_i (fetch_rf_adr_valid_o), // Templated + .fetch_rfa_adr_i (fetch_rfa_adr_o), // Templated + .fetch_rfb_adr_i (fetch_rfb_adr_o), // Templated + .decode_rfa_adr_i (decode_rfa_adr_o), // Templated + .decode_rfb_adr_i (decode_rfb_adr_o), // Templated + .execute_rfd_adr_i (execute_rfd_adr_o), // Templated + .ctrl_rfd_adr_i (ctrl_rfd_adr_o), // Templated + .wb_rfd_adr_i (wb_rfd_adr_o), // Templated + .spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated + .spr_bus_stb_i (spr_bus_stb_o), // Templated + .spr_bus_we_i (spr_bus_we_o), // Templated + .spr_bus_dat_i (spr_bus_dat_o), // Templated + .execute_rf_wb_i (execute_rf_wb_o), // Templated + .ctrl_rf_wb_i (ctrl_rf_wb_o), // Templated + .wb_rf_wb_i (wb_rf_wb_o), // Templated + .result_i (rf_result_o), // Templated + .ctrl_alu_result_i (ctrl_alu_result_o), // Templated + .pipeline_flush_i (pipeline_flush_o)); // Templated + + +`ifndef SYNTHESIS +// synthesis translate_off + /* Debug signals required for the debug monitor */ + function [OPTION_OPERAND_WIDTH-1:0] get_gpr; + // verilator public + input [4:0] gpr_num; + begin + // TODO: handle load ops + if ((mor1kx_rf_cappuccino.execute_rfd_adr_i == gpr_num) & + mor1kx_rf_cappuccino.execute_rf_wb_i) + get_gpr = alu_result_o; + else if ((mor1kx_rf_cappuccino.ctrl_rfd_adr_i == gpr_num) & + mor1kx_rf_cappuccino.ctrl_rf_wb_i) + get_gpr = ctrl_alu_result_o; + else if ((mor1kx_rf_cappuccino.wb_rfd_adr_i == gpr_num) & + mor1kx_rf_cappuccino.wb_rf_wb_i) + get_gpr = mor1kx_rf_cappuccino.result_i; + else + get_gpr = mor1kx_rf_cappuccino.rfa.mem[gpr_num]; + end + endfunction // + + + task set_gpr; + // verilator public + input [4:0] gpr_num; + input [OPTION_OPERAND_WIDTH-1:0] gpr_value; + begin + mor1kx_rf_cappuccino.rfa.mem[gpr_num] = gpr_value; + mor1kx_rf_cappuccino.rfb.mem[gpr_num] = gpr_value; + end + endtask +// synthesis translate_on +`endif + + + /* mor1kx_execute_ctrl_cappuccino AUTO_TEMPLATE ( + .padv_i (padv_execute_o), + .padv_ctrl_i (padv_ctrl_o), + .execute_except_ibus_err_i (execute_except_ibus_err_o), + .execute_except_itlb_miss_i (execute_except_itlb_miss_o), + .execute_except_ipagefault_i (execute_except_ipagefault_o), + .execute_except_illegal_i (execute_except_illegal_o), + .execute_except_ibus_align_i (execute_except_ibus_align_o), + .execute_except_syscall_i (execute_except_syscall_o), + .execute_except_trap_i (execute_except_trap_o), + .lsu_except_dbus_i (lsu_except_dbus_o), + .lsu_except_align_i (lsu_except_align_o), + .lsu_except_dtlb_miss_i (lsu_except_dtlb_miss_o), + .lsu_except_dpagefault_i (lsu_except_dpagefault_o), + .op_mul_i (execute_op_mul_o), + .op_lsu_load_i (execute_op_lsu_load_o), + .op_lsu_store_i (execute_op_lsu_store_o), + .op_lsu_atomic_i (execute_op_lsu_atomic_o), + .lsu_length_i (execute_lsu_length_o), + .lsu_zext_i (execute_lsu_zext_o), + .op_msync_i (execute_op_msync_o), + .op_mfspr_i (execute_op_mfspr_o), + .op_mtspr_i (execute_op_mtspr_o), + .alu_valid_i (alu_valid_o), + .lsu_valid_i (lsu_valid_o), + .msync_stall_i (msync_stall_o), + .alu_result_i (alu_result_o), + .adder_result_i (adder_result_o), + .execute_jal_result_i (execute_jal_result_o), + .op_jr_i (execute_op_jr_o), + .op_jal_i (execute_op_jal_o), + .op_rfe_i (execute_op_rfe_o), + .rfb_i (execute_rfb_o), + .flag_set_i (flag_set_o), + .flag_clear_i (flag_clear_o), + .pc_execute_i (pc_decode_to_execute), + .execute_rf_wb_i (execute_rf_wb_o), + .execute_rfd_adr_i (execute_rfd_adr_o), + .ctrl_mfspr_ack_i (ctrl_mfspr_ack_o), + .ctrl_mtspr_ack_i (ctrl_mtspr_ack_o), + .pipeline_flush_i (pipeline_flush_o), + .pc_ctrl_o (pc_execute_to_ctrl), + .execute_bubble_i (execute_bubble_o), + .carry_set_i (carry_set_o), + .carry_clear_i (carry_clear_o), + .overflow_set_i (overflow_set_o), + .overflow_clear_i (overflow_clear_o), + .fpcsr_i(fpcsr_o), + .fpcsr_set_i(fpcsr_set_o) + ); */ + mor1kx_execute_ctrl_cappuccino + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: execute_ctrl instance + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER) + ) + mor1kx_execute_ctrl_cappuccino + (/*AUTOINST*/ + // Outputs + .ctrl_rf_wb_o (ctrl_rf_wb_o), + .wb_rf_wb_o (wb_rf_wb_o), + .ctrl_rfd_adr_o (ctrl_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .wb_rfd_adr_o (wb_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .ctrl_alu_result_o (ctrl_alu_result_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_lsu_adr_o (ctrl_lsu_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_rfb_o (ctrl_rfb_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_flag_set_o (ctrl_flag_set_o), + .ctrl_flag_clear_o (ctrl_flag_clear_o), + .ctrl_carry_set_o (ctrl_carry_set_o), + .ctrl_carry_clear_o (ctrl_carry_clear_o), + .ctrl_overflow_set_o (ctrl_overflow_set_o), + .ctrl_overflow_clear_o (ctrl_overflow_clear_o), + .ctrl_fpcsr_o (ctrl_fpcsr_o), + .ctrl_fpcsr_set_o (ctrl_fpcsr_set_o), + .pc_ctrl_o (pc_execute_to_ctrl), // Templated + .ctrl_op_mul_o (ctrl_op_mul_o), + .ctrl_op_lsu_load_o (ctrl_op_lsu_load_o), + .ctrl_op_lsu_store_o (ctrl_op_lsu_store_o), + .ctrl_op_lsu_atomic_o (ctrl_op_lsu_atomic_o), + .ctrl_lsu_length_o (ctrl_lsu_length_o[1:0]), + .ctrl_lsu_zext_o (ctrl_lsu_zext_o), + .ctrl_op_msync_o (ctrl_op_msync_o), + .ctrl_op_mfspr_o (ctrl_op_mfspr_o), + .ctrl_op_mtspr_o (ctrl_op_mtspr_o), + .ctrl_op_rfe_o (ctrl_op_rfe_o), + .ctrl_except_ibus_err_o (ctrl_except_ibus_err_o), + .ctrl_except_itlb_miss_o (ctrl_except_itlb_miss_o), + .ctrl_except_ipagefault_o (ctrl_except_ipagefault_o), + .ctrl_except_ibus_align_o (ctrl_except_ibus_align_o), + .ctrl_except_illegal_o (ctrl_except_illegal_o), + .ctrl_except_syscall_o (ctrl_except_syscall_o), + .ctrl_except_dbus_o (ctrl_except_dbus_o), + .ctrl_except_dtlb_miss_o (ctrl_except_dtlb_miss_o), + .ctrl_except_dpagefault_o (ctrl_except_dpagefault_o), + .ctrl_except_align_o (ctrl_except_align_o), + .ctrl_except_trap_o (ctrl_except_trap_o), + .execute_valid_o (execute_valid_o), + .ctrl_valid_o (ctrl_valid_o), + // Inputs + .clk (clk), + .rst (rst), + .padv_i (padv_execute_o), // Templated + .padv_ctrl_i (padv_ctrl_o), // Templated + .execute_except_ibus_err_i (execute_except_ibus_err_o), // Templated + .execute_except_itlb_miss_i (execute_except_itlb_miss_o), // Templated + .execute_except_ipagefault_i (execute_except_ipagefault_o), // Templated + .execute_except_illegal_i (execute_except_illegal_o), // Templated + .execute_except_ibus_align_i (execute_except_ibus_align_o), // Templated + .execute_except_syscall_i (execute_except_syscall_o), // Templated + .lsu_except_dbus_i (lsu_except_dbus_o), // Templated + .lsu_except_align_i (lsu_except_align_o), // Templated + .lsu_except_dtlb_miss_i (lsu_except_dtlb_miss_o), // Templated + .lsu_except_dpagefault_i (lsu_except_dpagefault_o), // Templated + .execute_except_trap_i (execute_except_trap_o), // Templated + .pipeline_flush_i (pipeline_flush_o), // Templated + .op_mul_i (execute_op_mul_o), // Templated + .op_lsu_load_i (execute_op_lsu_load_o), // Templated + .op_lsu_store_i (execute_op_lsu_store_o), // Templated + .op_lsu_atomic_i (execute_op_lsu_atomic_o), // Templated + .lsu_length_i (execute_lsu_length_o), // Templated + .lsu_zext_i (execute_lsu_zext_o), // Templated + .op_msync_i (execute_op_msync_o), // Templated + .op_mfspr_i (execute_op_mfspr_o), // Templated + .op_mtspr_i (execute_op_mtspr_o), // Templated + .alu_valid_i (alu_valid_o), // Templated + .lsu_valid_i (lsu_valid_o), // Templated + .msync_stall_i (msync_stall_o), // Templated + .op_jr_i (execute_op_jr_o), // Templated + .op_jal_i (execute_op_jal_o), // Templated + .op_rfe_i (execute_op_rfe_o), // Templated + .alu_result_i (alu_result_o), // Templated + .adder_result_i (adder_result_o), // Templated + .rfb_i (execute_rfb_o), // Templated + .execute_jal_result_i (execute_jal_result_o), // Templated + .flag_set_i (flag_set_o), // Templated + .flag_clear_i (flag_clear_o), // Templated + .carry_set_i (carry_set_o), // Templated + .carry_clear_i (carry_clear_o), // Templated + .overflow_set_i (overflow_set_o), // Templated + .overflow_clear_i (overflow_clear_o), // Templated + .fpcsr_i (fpcsr_o), + .fpcsr_set_i (fpcsr_set_o), + .pc_execute_i (pc_decode_to_execute), // Templated + .execute_rf_wb_i (execute_rf_wb_o), // Templated + .execute_rfd_adr_i (execute_rfd_adr_o), // Templated + .execute_bubble_i (execute_bubble_o), // Templated + .ctrl_mfspr_ack_i (ctrl_mfspr_ack_o), // Templated + .ctrl_mtspr_ack_i (ctrl_mtspr_ack_o)); // Templated + + /* mor1kx_ctrl_cappuccino AUTO_TEMPLATE ( + .ctrl_alu_result_i (ctrl_alu_result_o), + .ctrl_lsu_adr_i (ctrl_lsu_adr_o), + .ctrl_rfb_i (ctrl_rfb_o), + .ctrl_flag_set_i (ctrl_flag_set_o), + .ctrl_flag_clear_i (ctrl_flag_clear_o), + .atomic_flag_set_i (atomic_flag_set_o), + .atomic_flag_clear_i (atomic_flag_clear_o), + .pc_ctrl_i (pc_execute_to_ctrl), + .pc_execute_i (pc_decode_to_execute), + .execute_op_branch_i (execute_op_branch_o), + .ctrl_op_mfspr_i (ctrl_op_mfspr_o), + .ctrl_op_mtspr_i (ctrl_op_mtspr_o), + .ctrl_op_rfe_i (ctrl_op_rfe_o), + .decode_branch_i (decode_branch_o), + .decode_branch_target_i (decode_branch_target_o), + .branch_mispredict_i (branch_mispredict_o), + .execute_mispredict_target_i (execute_mispredict_target_o), + .except_ibus_err_i (ctrl_except_ibus_err_o), + .except_itlb_miss_i (ctrl_except_itlb_miss_o), + .except_ipagefault_i (ctrl_except_ipagefault_o), + .except_ibus_align_i (ctrl_except_ibus_align_o), + .except_illegal_i (ctrl_except_illegal_o), + .except_syscall_i (ctrl_except_syscall_o), + .except_dbus_i (ctrl_except_dbus_o), + .except_dtlb_miss_i (ctrl_except_dtlb_miss_o), + .except_dpagefault_i (ctrl_except_dpagefault_o), + .except_trap_i (ctrl_except_trap_o), + .except_align_i (ctrl_except_align_o), + .fetch_valid_i (fetch_valid_o), + .decode_valid_i (decode_valid_o), + .execute_valid_i (execute_valid_o), + .ctrl_valid_i (ctrl_valid_o), + .fetch_exception_taken_i (fetch_exception_taken_o), + .decode_bubble_i (decode_bubble_o), + .execute_bubble_i (execute_bubble_o), + .store_buffer_epcr_i (store_buffer_epcr_o), + .store_buffer_err_i (store_buffer_err_o), + .ctrl_carry_set_i (ctrl_carry_set_o), + .ctrl_carry_clear_i (ctrl_carry_clear_o), + .ctrl_overflow_set_i (ctrl_overflow_set_o), + .ctrl_overflow_clear_i (ctrl_overflow_clear_o), + .ctrl_fpcsr_i (ctrl_fpcsr_o), + .ctrl_fpcsr_set_i (ctrl_fpcsr_set_o), + .spr_gpr_ack_i (spr_gpr_ack_o), + .spr_gpr_dat_i (spr_gpr_dat_o), + ) */ + mor1kx_ctrl_cappuccino + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_PIC(FEATURE_PIC), + .FEATURE_TIMER(FEATURE_TIMER), + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH), + .FEATURE_DATACACHE(FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .FEATURE_DMMU(FEATURE_DMMU), + .OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH), + .OPTION_DMMU_WAYS(OPTION_DMMU_WAYS), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .FEATURE_IMMU(FEATURE_IMMU), + .OPTION_IMMU_SET_WIDTH(OPTION_IMMU_SET_WIDTH), + .OPTION_IMMU_WAYS(OPTION_IMMU_WAYS), + .FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: ctrl instance + .FEATURE_MULTICORE(FEATURE_MULTICORE), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE), + .FEATURE_DSX(FEATURE_DSX), + .FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS), + .OPTION_RF_NUM_SHADOW_GPR(OPTION_RF_NUM_SHADOW_GPR), + .FEATURE_OVERFLOW(FEATURE_OVERFLOW), + .FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG) + ) + mor1kx_ctrl_cappuccino + (/*AUTOINST*/ + // Outputs + .ctrl_epcr_o (ctrl_epcr_o[OPTION_OPERAND_WIDTH-1:0]), + .mfspr_dat_o (mfspr_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_mfspr_ack_o (ctrl_mfspr_ack_o), + .ctrl_mtspr_ack_o (ctrl_mtspr_ack_o), + .ctrl_flag_o (ctrl_flag_o), + .ctrl_carry_o (ctrl_carry_o), + .ctrl_fpu_round_mode_o (ctrl_fpu_round_mode_o), + .ctrl_branch_exception_o (ctrl_branch_exception_o), + .ctrl_branch_except_pc_o (ctrl_branch_except_pc_o[OPTION_OPERAND_WIDTH-1:0]), + .pipeline_flush_o (pipeline_flush_o), + .doing_rfe_o (doing_rfe_o), + .padv_fetch_o (padv_fetch_o), + .padv_decode_o (padv_decode_o), + .padv_execute_o (padv_execute_o), + .padv_ctrl_o (padv_ctrl_o), + .du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .du_ack_o (du_ack_o), + .du_stall_o (du_stall_o), + .du_restart_pc_o (du_restart_pc_o[OPTION_OPERAND_WIDTH-1:0]), + .du_restart_o (du_restart_o), + .spr_bus_addr_o (spr_bus_addr_o[15:0]), + .spr_bus_we_o (spr_bus_we_o), + .spr_bus_stb_o (spr_bus_stb_o), + .spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_sr_o (spr_sr_o[15:0]), + .ctrl_bubble_o (ctrl_bubble_o), + // Inputs + .clk (clk), + .rst (rst), + .ctrl_alu_result_i (ctrl_alu_result_o), // Templated + .ctrl_lsu_adr_i (ctrl_lsu_adr_o), // Templated + .ctrl_rfb_i (ctrl_rfb_o), // Templated + .ctrl_flag_set_i (ctrl_flag_set_o), // Templated + .ctrl_flag_clear_i (ctrl_flag_clear_o), // Templated + .atomic_flag_set_i (atomic_flag_set_o), // Templated + .atomic_flag_clear_i (atomic_flag_clear_o), // Templated + .pc_ctrl_i (pc_execute_to_ctrl), // Templated + .ctrl_op_mfspr_i (ctrl_op_mfspr_o), // Templated + .ctrl_op_mtspr_i (ctrl_op_mtspr_o), // Templated + .ctrl_op_rfe_i (ctrl_op_rfe_o), // Templated + .decode_branch_i (decode_branch_o), // Templated + .decode_branch_target_i (decode_branch_target_o), // Templated + .branch_mispredict_i (branch_mispredict_o), // Templated + .execute_mispredict_target_i (execute_mispredict_target_o), // Templated + .pc_execute_i (pc_decode_to_execute), // Templated + .execute_op_branch_i (execute_op_branch_o), // Templated + .except_ibus_err_i (ctrl_except_ibus_err_o), // Templated + .except_itlb_miss_i (ctrl_except_itlb_miss_o), // Templated + .except_ipagefault_i (ctrl_except_ipagefault_o), // Templated + .except_ibus_align_i (ctrl_except_ibus_align_o), // Templated + .except_illegal_i (ctrl_except_illegal_o), // Templated + .except_syscall_i (ctrl_except_syscall_o), // Templated + .except_dbus_i (ctrl_except_dbus_o), // Templated + .except_dtlb_miss_i (ctrl_except_dtlb_miss_o), // Templated + .except_dpagefault_i (ctrl_except_dpagefault_o), // Templated + .except_trap_i (ctrl_except_trap_o), // Templated + .except_align_i (ctrl_except_align_o), // Templated + .fetch_valid_i (fetch_valid_o), // Templated + .decode_valid_i (decode_valid_o), // Templated + .execute_valid_i (execute_valid_o), // Templated + .ctrl_valid_i (ctrl_valid_o), // Templated + .fetch_exception_taken_i (fetch_exception_taken_o), // Templated + .decode_bubble_i (decode_bubble_o), // Templated + .execute_bubble_i (execute_bubble_o), // Templated + .irq_i (irq_i[31:0]), + .store_buffer_epcr_i (store_buffer_epcr_o), // Templated + .store_buffer_err_i (store_buffer_err_o), // Templated + .ctrl_carry_set_i (ctrl_carry_set_o), // Templated + .ctrl_carry_clear_i (ctrl_carry_clear_o), // Templated + .ctrl_overflow_set_i (ctrl_overflow_set_o), // Templated + .ctrl_overflow_clear_i (ctrl_overflow_clear_o), // Templated + .ctrl_fpcsr_i (ctrl_fpcsr_o), + .ctrl_fpcsr_set_i (ctrl_fpcsr_set_o), + .du_addr_i (du_addr_i[15:0]), + .du_stb_i (du_stb_i), + .du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .du_we_i (du_we_i), + .du_stall_i (du_stall_i), + .spr_bus_dat_dc_i (spr_bus_dat_dc_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dc_i (spr_bus_ack_dc_i), + .spr_bus_dat_ic_i (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_ic_i (spr_bus_ack_ic_i), + .spr_bus_dat_dmmu_i (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dmmu_i (spr_bus_ack_dmmu_i), + .spr_bus_dat_immu_i (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_immu_i (spr_bus_ack_immu_i), + .spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_mac_i (spr_bus_ack_mac_i), + .spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pmu_i (spr_bus_ack_pmu_i), + .spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pcu_i (spr_bus_ack_pcu_i), + .spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_fpu_i (spr_bus_ack_fpu_i), + .spr_gpr_dat_i (spr_gpr_dat_o), // Templated + .spr_gpr_ack_i (spr_gpr_ack_o), // Templated + .multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0]), + .multicore_numcores_i (multicore_numcores_i[OPTION_OPERAND_WIDTH-1:0])); + + reg [`OR1K_INSN_WIDTH-1:0] traceport_stage_decode_insn; + reg [`OR1K_INSN_WIDTH-1:0] traceport_stage_exec_insn; + + reg traceport_waitexec; + + always @(posedge clk) begin + if (FEATURE_TRACEPORT_EXEC != "NONE") begin + if (rst) begin + traceport_waitexec <= 0; + end else begin + if (padv_decode_o) begin + traceport_stage_decode_insn <= insn_fetch_to_decode; + end + + if (padv_execute_o) begin + traceport_stage_exec_insn <= traceport_stage_decode_insn; + end + + if (padv_ctrl_o) begin + traceport_exec_insn_o <= traceport_stage_exec_insn; + end + + traceport_exec_pc_o <= pc_execute_to_ctrl; + if (!traceport_waitexec) begin + if (padv_ctrl_o & !ctrl_bubble_o) begin + if (execute_valid_o) begin + traceport_exec_valid_o <= 1'b1; + end else begin + traceport_exec_valid_o <= 1'b0; + traceport_waitexec <= 1'b1; + end + end else begin + traceport_exec_valid_o <= 1'b0; + end + end else begin + if (execute_valid_o) begin + traceport_exec_valid_o <= 1'b1; + traceport_waitexec <= 1'b0; + end else begin + traceport_exec_valid_o <= 1'b0; + end + end // else: !if(!traceport_waitexec) + end // else: !if(rst) + end else begin // if (FEATURE_TRACEPORT_EXEC != "NONE") + traceport_stage_decode_insn <= {`OR1K_INSN_WIDTH{1'b0}}; + traceport_stage_exec_insn <= {`OR1K_INSN_WIDTH{1'b0}}; + traceport_exec_insn_o <= {`OR1K_INSN_WIDTH{1'b0}}; + traceport_exec_pc_o <= 32'h0; + traceport_exec_valid_o <= 1'b0; + end + end + + generate + if (FEATURE_TRACEPORT_EXEC != "NONE") begin + assign traceport_exec_wbreg_o = wb_rfd_adr_o; + assign traceport_exec_wben_o = wb_rf_wb_o; + assign traceport_exec_wbdata_o = rf_result_o; + end else begin + assign traceport_exec_wbreg_o = {OPTION_RF_ADDR_WIDTH{1'b0}}; + assign traceport_exec_wben_o = 1'b0; + assign traceport_exec_wbdata_o = {OPTION_OPERAND_WIDTH{1'b0}}; + end + endgenerate + +endmodule // mor1kx_cpu_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_espresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_espresso.v new file mode 100644 index 0000000..3b40603 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_espresso.v @@ -0,0 +1,761 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Espresso pipeline CPU module + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_cpu_espresso + #( + parameter OPTION_OPERAND_WIDTH = 32, + + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter FEATURE_DMMU = "NONE", + parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE", + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter FEATURE_IMMU = "NONE", + parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE", + parameter FEATURE_TIMER = "ENABLED", + parameter FEATURE_DEBUGUNIT = "NONE", + parameter FEATURE_PERFCOUNTERS = "NONE", + parameter FEATURE_MAC = "NONE", + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + + parameter FEATURE_PIC = "ENABLED", + parameter OPTION_PIC_TRIGGER = "LEVEL", + parameter OPTION_PIC_NMI_WIDTH = 0, + + parameter FEATURE_DSX = "NONE", + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter FEATURE_OVERFLOW = "NONE", + parameter FEATURE_CARRY_FLAG = "ENABLED", + + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter OPTION_RF_WORDS = 32, + + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + + parameter FEATURE_MULTIPLIER = "THREESTAGE", + parameter FEATURE_DIVIDER = "NONE", + + parameter FEATURE_ADDC = "NONE", + parameter FEATURE_SRA = "ENABLED", + parameter FEATURE_ROR = "NONE", + parameter FEATURE_EXT = "NONE", + parameter FEATURE_CMOV = "NONE", + parameter FEATURE_FFL1 = "NONE", + parameter FEATURE_MSYNC = "NONE", + parameter FEATURE_PSYNC = "NONE", + parameter FEATURE_CSYNC = "NONE", + + parameter FEATURE_CUST1 = "NONE", + parameter FEATURE_CUST2 = "NONE", + parameter FEATURE_CUST3 = "NONE", + parameter FEATURE_CUST4 = "NONE", + parameter FEATURE_CUST5 = "NONE", + parameter FEATURE_CUST6 = "NONE", + parameter FEATURE_CUST7 = "NONE", + parameter FEATURE_CUST8 = "NONE", + + parameter OPTION_SHIFTER = "BARREL", + + parameter FEATURE_MULTICORE = "NONE", + + parameter FEATURE_TRACEPORT_EXEC = "NONE" + ) + ( + input clk, + input rst, + + // Instruction bus + input ibus_err_i, + input ibus_ack_i, + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o, + output ibus_req_o, + output ibus_burst_o, + + // Data bus + input dbus_err_i, + input dbus_ack_i, + input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o, + output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o, + output dbus_req_o, + output [3:0] dbus_bsel_o, + output dbus_we_o, + output dbus_burst_o, + + // Interrupts + input [31:0] irq_i, + + // Debug interface + input [15:0] du_addr_i, + input du_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i, + input du_we_i, + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o, + output du_ack_o, + // Stall control from debug interface + input du_stall_i, + output du_stall_o, + + // SPR accesses to external units (cache, mmu, etc.) + output [15:0] spr_bus_addr_o, + output spr_bus_we_o, + output spr_bus_stb_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i, + input spr_bus_ack_dmmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i, + input spr_bus_ack_immu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i, + input spr_bus_ack_mac_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i, + input spr_bus_ack_pmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i, + input spr_bus_ack_pcu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i, + input spr_bus_ack_fpu_i, + output [15:0] spr_sr_o, + + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i + ); + + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_to_decode; + wire [`OR1K_INSN_WIDTH-1:0] insn_fetch_to_decode; + wire [OPTION_OPERAND_WIDTH-1:0] pc_decode_to_execute; + wire [OPTION_OPERAND_WIDTH-1:0] pc_execute_to_ctrl; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [OPTION_OPERAND_WIDTH-1:0] adder_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire [OPTION_OPERAND_WIDTH-1:0] alu_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire alu_valid_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire carry_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire carry_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire carry_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire ctrl_branch_occur_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_target_o;// From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire ctrl_mfspr_we_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire decode_adder_do_carry_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_adder_do_sub_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_except_ibus_err_o;// From mor1kx_fetch_espresso of mor1kx_fetch_espresso.v + wire decode_except_illegal_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_except_syscall_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_except_trap_o; // From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_IMM_WIDTH-1:0] decode_imm16_o; // From mor1kx_decode of mor1kx_decode.v + wire [OPTION_OPERAND_WIDTH-1:0] decode_immediate_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_immediate_sel_o; // From mor1kx_decode of mor1kx_decode.v + wire [9:0] decode_immjbr_upper_o; // From mor1kx_decode of mor1kx_decode.v + wire [1:0] decode_lsu_length_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_lsu_zext_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_add_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_alu_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_bf_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_bnf_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_branch_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_brcond_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_signed_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_unsigned_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_op_ffl1_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jal_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jbr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_atomic_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_load_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_store_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mfspr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_movhi_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mtspr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_signed_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_unsigned_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_op_rfe_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_setflag_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_shift_o; // From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_o;// From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_o;// From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_rf_wb_o; // From mor1kx_decode of mor1kx_decode.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire du_restart_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o;// From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire exception_taken_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire execute_waiting_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire fetch_advancing_o; // From mor1kx_fetch_espresso of mor1kx_fetch_espresso.v + wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;// From mor1kx_fetch_espresso of mor1kx_fetch_espresso.v + wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;// From mor1kx_fetch_espresso of mor1kx_fetch_espresso.v + wire fetch_take_exception_branch_o;// From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire flag_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire flag_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire flag_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire lsu_except_align_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire lsu_except_dbus_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] lsu_result_o;// From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire lsu_valid_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] mul_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire next_fetch_done_o; // From mor1kx_fetch_espresso of mor1kx_fetch_espresso.v + wire overflow_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire overflow_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire padv_decode_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire padv_execute_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire padv_fetch_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;// From mor1kx_fetch_espresso of mor1kx_fetch_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_o; // From mor1kx_fetch_espresso of mor1kx_fetch_espresso.v + wire pipeline_flush_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] rf_result_o; // From mor1kx_wb_mux_espresso of mor1kx_wb_mux_espresso.v + wire rf_we_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] rfa_o; // From mor1kx_rf_espresso of mor1kx_rf_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] rfb_o; // From mor1kx_rf_espresso of mor1kx_rf_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_npc_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_ppc_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + wire stepping_o; // From mor1kx_ctrl_espresso of mor1kx_ctrl_espresso.v + // End of automatics + + /* mor1kx_fetch_espresso AUTO_TEMPLATE ( + .padv_i (padv_fetch_o), + .branch_occur_i (ctrl_branch_occur_o), + .branch_dest_i (ctrl_branch_target_o), + .pipeline_flush_i (pipeline_flush_o), + .pc_decode_o (pc_fetch_to_decode), + .decode_insn_o (insn_fetch_to_decode), + .du_restart_pc_i (du_restart_pc_o), + .du_restart_i (du_restart_o), + .fetch_take_exception_branch_i (fetch_take_exception_branch_o), + .execute_waiting_i (execute_waiting_o), + .stepping_i (stepping_o), + ); */ + mor1kx_fetch_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC) + ) + mor1kx_fetch_espresso + (/*AUTOINST*/ + // Outputs + .ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ibus_req_o (ibus_req_o), + .ibus_burst_o (ibus_burst_o), + .decode_insn_o (insn_fetch_to_decode), // Templated + .next_fetch_done_o (next_fetch_done_o), + .fetch_rfa_adr_o (fetch_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .fetch_rfb_adr_o (fetch_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .pc_fetch_o (pc_fetch_o[OPTION_OPERAND_WIDTH-1:0]), + .pc_fetch_next_o (pc_fetch_next_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_except_ibus_err_o (decode_except_ibus_err_o), + .fetch_advancing_o (fetch_advancing_o), + // Inputs + .clk (clk), + .rst (rst), + .ibus_err_i (ibus_err_i), + .ibus_ack_i (ibus_ack_i), + .ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .padv_i (padv_fetch_o), // Templated + .branch_occur_i (ctrl_branch_occur_o), // Templated + .branch_dest_i (ctrl_branch_target_o), // Templated + .du_restart_i (du_restart_o), // Templated + .du_restart_pc_i (du_restart_pc_o), // Templated + .fetch_take_exception_branch_i (fetch_take_exception_branch_o), // Templated + .execute_waiting_i (execute_waiting_o), // Templated + .du_stall_i (du_stall_i), + .stepping_i (stepping_o)); // Templated + + /* mor1kx_decode AUTO_TEMPLATE ( + .decode_insn_i (insn_fetch_to_decode), + .decode_op_lsu_atomic_o (), + ); */ + mor1kx_decode + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_MSYNC(FEATURE_MSYNC), + .FEATURE_PSYNC(FEATURE_PSYNC), + .FEATURE_CSYNC(FEATURE_CSYNC), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8) + ) + mor1kx_decode + (/*AUTOINST*/ + // Outputs + .decode_opc_alu_o (decode_opc_alu_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .decode_opc_alu_secondary_o (decode_opc_alu_secondary_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .decode_imm16_o (decode_imm16_o[`OR1K_IMM_WIDTH-1:0]), + .decode_immediate_o (decode_immediate_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_immediate_sel_o (decode_immediate_sel_o), + .decode_immjbr_upper_o (decode_immjbr_upper_o[9:0]), + .decode_rfd_adr_o (decode_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rfa_adr_o (decode_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rfb_adr_o (decode_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rf_wb_o (decode_rf_wb_o), + .decode_op_jbr_o (decode_op_jbr_o), + .decode_op_jr_o (decode_op_jr_o), + .decode_op_jal_o (decode_op_jal_o), + .decode_op_bf_o (decode_op_bf_o), + .decode_op_bnf_o (decode_op_bnf_o), + .decode_op_brcond_o (decode_op_brcond_o), + .decode_op_branch_o (decode_op_branch_o), + .decode_op_alu_o (decode_op_alu_o), + .decode_op_lsu_load_o (decode_op_lsu_load_o), + .decode_op_lsu_store_o (decode_op_lsu_store_o), + .decode_op_lsu_atomic_o (decode_op_lsu_atomic_o), + .decode_lsu_length_o (decode_lsu_length_o[1:0]), + .decode_lsu_zext_o (decode_lsu_zext_o), + .decode_op_mfspr_o (decode_op_mfspr_o), + .decode_op_mtspr_o (decode_op_mtspr_o), + .decode_op_rfe_o (decode_op_rfe_o), + .decode_op_setflag_o (decode_op_setflag_o), + .decode_op_add_o (decode_op_add_o), + .decode_op_mul_o (decode_op_mul_o), + .decode_op_mul_signed_o (decode_op_mul_signed_o), + .decode_op_mul_unsigned_o (decode_op_mul_unsigned_o), + .decode_op_div_o (decode_op_div_o), + .decode_op_div_signed_o (decode_op_div_signed_o), + .decode_op_div_unsigned_o (decode_op_div_unsigned_o), + .decode_op_shift_o (decode_op_shift_o), + .decode_op_ffl1_o (decode_op_ffl1_o), + .decode_op_movhi_o (decode_op_movhi_o), + .decode_adder_do_sub_o (decode_adder_do_sub_o), + .decode_adder_do_carry_o (decode_adder_do_carry_o), + .decode_except_illegal_o (decode_except_illegal_o), + .decode_except_syscall_o (decode_except_syscall_o), + .decode_except_trap_o (decode_except_trap_o), + .decode_opc_insn_o (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .decode_insn_i (insn_fetch_to_decode)); // Templated + + /* mor1kx_execute_alu AUTO_TEMPLATE ( + .padv_execute_i (padv_execute_o), + .padv_ctrl_i (1'b1), + .opc_alu_i (decode_opc_alu_o), + .opc_alu_secondary_i (decode_opc_alu_secondary_o), + .imm16_i (decode_imm16_o), + .immediate_i (decode_immediate_o), + .immediate_sel_i (decode_immediate_sel_o), + .decode_valid_i (padv_decode_o), + .op_alu_i (decode_op_alu_o), + .op_add_i (decode_op_add_o), + .op_mul_i (decode_op_mul_o), + .op_mul_signed_i (decode_op_mul_signed_o), + .op_mul_unsigned_i (decode_op_mul_unsigned_o), + .op_div_i (decode_op_div_o), + .op_div_signed_i (decode_op_div_signed_o), + .op_div_unsigned_i (decode_op_div_unsigned_o), + .op_shift_i (decode_op_shift_o), + .op_ffl1_i (decode_op_ffl1_o), + .op_setflag_i (decode_op_setflag_o), + .op_mtspr_i (decode_op_mtspr_o), + .op_mfspr_i (decode_op_mfspr_o), + .op_movhi_i (decode_op_movhi_o), + .op_jbr_i (decode_op_jbr_o), + .op_jr_i (decode_op_jr_o), + .immjbr_upper_i (decode_immjbr_upper_o), + .pc_execute_i (spr_ppc_o), + .adder_do_sub_i (decode_adder_do_sub_o), + .adder_do_carry_i (decode_adder_do_carry_o), + .rfa_i (rfa_o), + .rfb_i (rfb_o), + .flag_i (flag_o), + .carry_i (carry_o), + ); */ + mor1kx_execute_alu + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8), + .OPTION_SHIFTER(OPTION_SHIFTER) + ) + mor1kx_execute_alu + (/*AUTOINST*/ + // Outputs + .flag_set_o (flag_set_o), + .flag_clear_o (flag_clear_o), + .carry_set_o (carry_set_o), + .carry_clear_o (carry_clear_o), + .overflow_set_o (overflow_set_o), + .overflow_clear_o (overflow_clear_o), + .alu_result_o (alu_result_o[OPTION_OPERAND_WIDTH-1:0]), + .alu_valid_o (alu_valid_o), + .mul_result_o (mul_result_o[OPTION_OPERAND_WIDTH-1:0]), + .adder_result_o (adder_result_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .padv_execute_i (padv_execute_o), // Templated + .padv_ctrl_i (1'b1), // Templated + .opc_alu_i (decode_opc_alu_o), // Templated + .opc_alu_secondary_i (decode_opc_alu_secondary_o), // Templated + .imm16_i (decode_imm16_o), // Templated + .immediate_i (decode_immediate_o), // Templated + .immediate_sel_i (decode_immediate_sel_o), // Templated + .decode_valid_i (padv_decode_o), // Templated + .op_alu_i (decode_op_alu_o), // Templated + .op_add_i (decode_op_add_o), // Templated + .op_mul_i (decode_op_mul_o), // Templated + .op_mul_signed_i (decode_op_mul_signed_o), // Templated + .op_mul_unsigned_i (decode_op_mul_unsigned_o), // Templated + .op_div_i (decode_op_div_o), // Templated + .op_div_signed_i (decode_op_div_signed_o), // Templated + .op_div_unsigned_i (decode_op_div_unsigned_o), // Templated + .op_shift_i (decode_op_shift_o), // Templated + .op_ffl1_i (decode_op_ffl1_o), // Templated + .op_setflag_i (decode_op_setflag_o), // Templated + .op_mtspr_i (decode_op_mtspr_o), // Templated + .op_mfspr_i (decode_op_mfspr_o), // Templated + .op_movhi_i (decode_op_movhi_o), // Templated + .op_jbr_i (decode_op_jbr_o), // Templated + .op_jr_i (decode_op_jr_o), // Templated + .immjbr_upper_i (decode_immjbr_upper_o), // Templated + .pc_execute_i (spr_ppc_o), // Templated + .adder_do_sub_i (decode_adder_do_sub_o), // Templated + .adder_do_carry_i (decode_adder_do_carry_o), // Templated + .rfa_i (rfa_o), // Templated + .rfb_i (rfb_o), // Templated + .flag_i (flag_o), // Templated + .carry_i (carry_o)); // Templated + + + /* mor1kx_lsu_espresso AUTO_TEMPLATE ( + .padv_fetch_i (padv_fetch_o), + .lsu_adr_i (adder_result_o), + .rfb_i (rfb_o), + .op_lsu_load_i (decode_op_lsu_load_o), + .op_lsu_store_i (decode_op_lsu_store_o), + .lsu_length_i (decode_lsu_length_o), + .lsu_zext_i (decode_lsu_zext_o), + .exception_taken_i (exception_taken_o), + .du_restart_i (du_restart_o), + .stepping_i (stepping_o), + .next_fetch_done_i (next_fetch_done_o), + ); */ + mor1kx_lsu_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH) + ) + mor1kx_lsu_espresso + (/*AUTOINST*/ + // Outputs + .lsu_result_o (lsu_result_o[OPTION_OPERAND_WIDTH-1:0]), + .lsu_valid_o (lsu_valid_o), + .lsu_except_dbus_o (lsu_except_dbus_o), + .lsu_except_align_o (lsu_except_align_o), + .dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_req_o (dbus_req_o), + .dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_bsel_o (dbus_bsel_o[3:0]), + .dbus_we_o (dbus_we_o), + .dbus_burst_o (dbus_burst_o), + // Inputs + .clk (clk), + .rst (rst), + .padv_fetch_i (padv_fetch_o), // Templated + .lsu_adr_i (adder_result_o), // Templated + .rfb_i (rfb_o), // Templated + .op_lsu_load_i (decode_op_lsu_load_o), // Templated + .op_lsu_store_i (decode_op_lsu_store_o), // Templated + .lsu_length_i (decode_lsu_length_o), // Templated + .lsu_zext_i (decode_lsu_zext_o), // Templated + .exception_taken_i (exception_taken_o), // Templated + .du_restart_i (du_restart_o), // Templated + .stepping_i (stepping_o), // Templated + .next_fetch_done_i (next_fetch_done_o), // Templated + .dbus_err_i (dbus_err_i), + .dbus_ack_i (dbus_ack_i), + .dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0])); + + + /* mor1kx_wb_mux_espresso AUTO_TEMPLATE ( + .alu_result_i (alu_result_o), + .lsu_result_i (lsu_result_o), + .spr_i (mfspr_dat_o), + .op_jal_i (decode_op_jal_o), + .op_lsu_load_i (decode_op_lsu_load_o), + .ppc_i (spr_ppc_o), + .op_mfspr_i (decode_op_mfspr_o), + .pc_fetch_next_i (pc_fetch_next_o), + ); */ + mor1kx_wb_mux_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH) + ) + mor1kx_wb_mux_espresso + (/*AUTOINST*/ + // Outputs + .rf_result_o (rf_result_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .alu_result_i (alu_result_o), // Templated + .lsu_result_i (lsu_result_o), // Templated + .ppc_i (spr_ppc_o), // Templated + .pc_fetch_next_i (pc_fetch_next_o), // Templated + .spr_i (mfspr_dat_o), // Templated + .op_jal_i (decode_op_jal_o), // Templated + .op_lsu_load_i (decode_op_lsu_load_o), // Templated + .op_mfspr_i (decode_op_mfspr_o)); // Templated + + /* mor1kx_rf_espresso AUTO_TEMPLATE ( + .rf_we_i (rf_we_o), + .rf_re_i (fetch_advancing_o), + .rfd_adr_i (decode_rfd_adr_o), + .rfa_adr_i (fetch_rfa_adr_o), + .rfb_adr_i (fetch_rfb_adr_o), + .result_i (rf_result_o), + ); */ + mor1kx_rf_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RF_WORDS(OPTION_RF_WORDS) + ) + mor1kx_rf_espresso + (/*AUTOINST*/ + // Outputs + .rfa_o (rfa_o[OPTION_OPERAND_WIDTH-1:0]), + .rfb_o (rfb_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .rfd_adr_i (decode_rfd_adr_o), // Templated + .rfa_adr_i (fetch_rfa_adr_o), // Templated + .rfb_adr_i (fetch_rfb_adr_o), // Templated + .rf_we_i (rf_we_o), // Templated + .rf_re_i (fetch_advancing_o), // Templated + .result_i (rf_result_o)); // Templated + + + /* Debug signals required for the debug monitor */ + function [OPTION_OPERAND_WIDTH-1:0] get_gpr; + // verilator public + input [4:0] gpr_num; + begin + // If we're writing, the value won't be in the GPR yet, so snoop + // it off the result in line. + if (rf_we_o) + get_gpr = rf_result_o; + else + get_gpr = mor1kx_rf_espresso.rfa.mem[gpr_num]; + end + endfunction + +`ifndef SYNTHESIS +// synthesis translate_off + task set_gpr; + // verilator public + input [4:0] gpr_num; + input [OPTION_OPERAND_WIDTH-1:0] gpr_value; + begin + mor1kx_rf_espresso.rfa.mem[gpr_num] = gpr_value; + mor1kx_rf_espresso.rfb.mem[gpr_num] = gpr_value; + end + endtask +// synthesis translate_on +`endif + + /* mor1kx_ctrl_espresso AUTO_TEMPLATE ( + .ctrl_alu_result_i (alu_result_o), + .ctrl_rfb_i (rfb_o), + .ctrl_flag_set_i (flag_set_o), + .ctrl_flag_clear_i (flag_clear_o), + .pc_ctrl_i (), + .pc_fetch_i (pc_fetch_o), + .ctrl_opc_insn_i (decode_opc_insn_o), + .ctrl_branch_target_i (ctrl_branch_target_o), + .op_lsu_load_i (decode_op_lsu_load_o), + .op_lsu_store_i (decode_op_lsu_store_o), + .alu_valid_i (alu_valid_o), + .lsu_valid_i (lsu_valid_o), + .op_jr_i (decode_op_jr_o), + .op_jbr_i (decode_op_jbr_o), + .except_ibus_err_i (decode_except_ibus_err_o), + .except_illegal_i (decode_except_illegal_o), + .except_syscall_i (decode_except_syscall_o), + .except_dbus_i (lsu_except_dbus_o), + .except_trap_i (decode_except_trap_o), + .except_align_i (lsu_except_align_o), + .next_fetch_done_i (next_fetch_done_o), + .execute_valid_i (execute_valid_o), + .execute_waiting_i (execute_waiting_o), + .fetch_branch_taken_i (fetch_branch_taken_o), + .rf_wb_i (decode_rf_wb_o), + .fetch_advancing_i (fetch_advancing_o), + .carry_set_i (carry_set_o), + .carry_clear_i (carry_clear_o), + .overflow_set_i (overflow_set_o), + .overflow_clear_i (overflow_clear_o), + .spr_bus_dat_dc_i (), + .spr_bus_ack_dc_i (), + .spr_bus_dat_ic_i (), + .spr_bus_ack_ic_i (), + ); */ + mor1kx_ctrl_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_PIC(FEATURE_PIC), + .FEATURE_TIMER(FEATURE_TIMER), + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH), + .FEATURE_DSX(FEATURE_DSX), + .FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS), + .FEATURE_OVERFLOW(FEATURE_OVERFLOW), + .FEATURE_DATACACHE(FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .FEATURE_DMMU(FEATURE_DMMU), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .FEATURE_IMMU(FEATURE_IMMU), + .FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTICORE(FEATURE_MULTICORE), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE) + ) + mor1kx_ctrl_espresso + (/*AUTOINST*/ + // Outputs + .flag_o (flag_o), + .spr_npc_o (spr_npc_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_ppc_o (spr_ppc_o[OPTION_OPERAND_WIDTH-1:0]), + .mfspr_dat_o (mfspr_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_mfspr_we_o (ctrl_mfspr_we_o), + .carry_o (carry_o), + .pipeline_flush_o (pipeline_flush_o), + .padv_fetch_o (padv_fetch_o), + .padv_decode_o (padv_decode_o), + .padv_execute_o (padv_execute_o), + .fetch_take_exception_branch_o (fetch_take_exception_branch_o), + .exception_taken_o (exception_taken_o), + .execute_waiting_o (execute_waiting_o), + .stepping_o (stepping_o), + .du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .du_ack_o (du_ack_o), + .du_stall_o (du_stall_o), + .du_restart_pc_o (du_restart_pc_o[OPTION_OPERAND_WIDTH-1:0]), + .du_restart_o (du_restart_o), + .spr_bus_addr_o (spr_bus_addr_o[15:0]), + .spr_bus_we_o (spr_bus_we_o), + .spr_bus_stb_o (spr_bus_stb_o), + .spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_sr_o (spr_sr_o[15:0]), + .ctrl_branch_target_o (ctrl_branch_target_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_branch_occur_o (ctrl_branch_occur_o), + .rf_we_o (rf_we_o), + // Inputs + .clk (clk), + .rst (rst), + .ctrl_alu_result_i (alu_result_o), // Templated + .ctrl_rfb_i (rfb_o), // Templated + .ctrl_flag_set_i (flag_set_o), // Templated + .ctrl_flag_clear_i (flag_clear_o), // Templated + .ctrl_opc_insn_i (decode_opc_insn_o), // Templated + .pc_fetch_i (pc_fetch_o), // Templated + .fetch_advancing_i (fetch_advancing_o), // Templated + .except_ibus_err_i (decode_except_ibus_err_o), // Templated + .except_illegal_i (decode_except_illegal_o), // Templated + .except_syscall_i (decode_except_syscall_o), // Templated + .except_dbus_i (lsu_except_dbus_o), // Templated + .except_trap_i (decode_except_trap_o), // Templated + .except_align_i (lsu_except_align_o), // Templated + .next_fetch_done_i (next_fetch_done_o), // Templated + .alu_valid_i (alu_valid_o), // Templated + .lsu_valid_i (lsu_valid_o), // Templated + .op_lsu_load_i (decode_op_lsu_load_o), // Templated + .op_lsu_store_i (decode_op_lsu_store_o), // Templated + .op_jr_i (decode_op_jr_o), // Templated + .op_jbr_i (decode_op_jbr_o), // Templated + .irq_i (irq_i[31:0]), + .carry_set_i (carry_set_o), // Templated + .carry_clear_i (carry_clear_o), // Templated + .overflow_set_i (overflow_set_o), // Templated + .overflow_clear_i (overflow_clear_o), // Templated + .du_addr_i (du_addr_i[15:0]), + .du_stb_i (du_stb_i), + .du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .du_we_i (du_we_i), + .du_stall_i (du_stall_i), + .spr_bus_dat_dc_i (), // Templated + .spr_bus_ack_dc_i (), // Templated + .spr_bus_dat_ic_i (), // Templated + .spr_bus_ack_ic_i (), // Templated + .spr_bus_dat_dmmu_i (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dmmu_i (spr_bus_ack_dmmu_i), + .spr_bus_dat_immu_i (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_immu_i (spr_bus_ack_immu_i), + .spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_mac_i (spr_bus_ack_mac_i), + .spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pmu_i (spr_bus_ack_pmu_i), + .spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pcu_i (spr_bus_ack_pcu_i), + .spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_fpu_i (spr_bus_ack_fpu_i), + .multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0]), + .rf_wb_i (decode_rf_wb_o)); // Templated + +endmodule // mor1kx_cpu_espresso diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_prontoespresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_prontoespresso.v new file mode 100644 index 0000000..61896cb --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_prontoespresso.v @@ -0,0 +1,867 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: "Pronto espresso" pipeline CPU module + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_cpu_prontoespresso + #( + parameter OPTION_OPERAND_WIDTH = 32, + + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter FEATURE_DMMU = "NONE", + parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE", + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter FEATURE_IMMU = "NONE", + parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE", + parameter FEATURE_TIMER = "ENABLED", + parameter FEATURE_DEBUGUNIT = "NONE", + parameter FEATURE_PERFCOUNTERS = "NONE", + parameter FEATURE_MAC = "NONE", + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + + parameter FEATURE_PIC = "ENABLED", + parameter OPTION_PIC_TRIGGER = "LEVEL", + parameter OPTION_PIC_NMI_WIDTH = 0, + + parameter FEATURE_DSX = "NONE", + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter FEATURE_OVERFLOW = "NONE", + parameter FEATURE_CARRY_FLAG = "ENABLED", + + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter OPTION_RF_WORDS = 32, + + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + + parameter OPTION_TCM_FETCHER = "DISABLED", + + parameter FEATURE_MULTIPLIER = "THREESTAGE", + parameter FEATURE_DIVIDER = "NONE", + + parameter FEATURE_ADDC = "NONE", + parameter FEATURE_SRA = "ENABLED", + parameter FEATURE_ROR = "NONE", + parameter FEATURE_EXT = "NONE", + parameter FEATURE_CMOV = "NONE", + parameter FEATURE_FFL1 = "NONE", + parameter FEATURE_MSYNC = "NONE", + parameter FEATURE_PSYNC = "NONE", + parameter FEATURE_CSYNC = "NONE", + + parameter FEATURE_CUST1 = "NONE", + parameter FEATURE_CUST2 = "NONE", + parameter FEATURE_CUST3 = "NONE", + parameter FEATURE_CUST4 = "NONE", + parameter FEATURE_CUST5 = "NONE", + parameter FEATURE_CUST6 = "NONE", + parameter FEATURE_CUST7 = "NONE", + parameter FEATURE_CUST8 = "NONE", + + parameter OPTION_SHIFTER = "BARREL", + + parameter FEATURE_MULTICORE = "NONE", + + parameter FEATURE_TRACEPORT_EXEC = "NONE" + ) + ( + input clk, + input rst, + + // Instruction bus + input ibus_err_i, + input ibus_ack_i, + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o, + output ibus_req_o, + output ibus_burst_o, + + // Data bus + input dbus_err_i, + input dbus_ack_i, + input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o, + output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o, + output dbus_req_o, + output [3:0] dbus_bsel_o, + output dbus_we_o, + output dbus_burst_o, + + // Interrupts + input [31:0] irq_i, + + // Debug interface + input [15:0] du_addr_i, + input du_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i, + input du_we_i, + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o, + output du_ack_o, + // Stall control from debug interface + input du_stall_i, + output du_stall_o, + + // SPR accesses to external units (cache, mmu, etc.) + output [15:0] spr_bus_addr_o, + output spr_bus_we_o, + output spr_bus_stb_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i, + input spr_bus_ack_dmmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i, + input spr_bus_ack_immu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i, + input spr_bus_ack_mac_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i, + input spr_bus_ack_pmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i, + input spr_bus_ack_pcu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i, + input spr_bus_ack_fpu_i, + output [15:0] spr_sr_o, + + // The multicore core identifier + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i + ); + + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_to_decode; + wire [`OR1K_INSN_WIDTH-1:0] insn_fetch_to_decode; + wire [OPTION_OPERAND_WIDTH-1:0] pc_decode_to_execute; + wire [OPTION_OPERAND_WIDTH-1:0] pc_execute_to_ctrl; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [OPTION_OPERAND_WIDTH-1:0] adder_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire [OPTION_OPERAND_WIDTH-1:0] alu_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire alu_valid_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire carry_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire carry_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire carry_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire ctrl_branch_occur_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_target_o;// From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire ctrl_insn_done_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire ctrl_mfspr_we_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire decode_adder_do_carry_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_adder_do_sub_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_except_ibus_err_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire decode_except_illegal_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_except_syscall_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_except_trap_o; // From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_IMM_WIDTH-1:0] decode_imm16_o; // From mor1kx_decode of mor1kx_decode.v + wire [OPTION_OPERAND_WIDTH-1:0] decode_immediate_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_immediate_sel_o; // From mor1kx_decode of mor1kx_decode.v + wire [9:0] decode_immjbr_upper_o; // From mor1kx_decode of mor1kx_decode.v + wire [1:0] decode_lsu_length_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_lsu_zext_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_add_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_alu_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_bf_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_bnf_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_branch_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_brcond_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_signed_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_div_unsigned_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_op_ffl1_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jal_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jbr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_jr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_atomic_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_load_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_lsu_store_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mfspr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_movhi_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mtspr_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_signed_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_mul_unsigned_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_op_rfe_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_setflag_o; // From mor1kx_decode of mor1kx_decode.v + wire decode_op_shift_o; // From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_o;// From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_o;// From mor1kx_decode of mor1kx_decode.v + wire [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_o;// From mor1kx_decode of mor1kx_decode.v + wire decode_rf_wb_o; // From mor1kx_decode of mor1kx_decode.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_o;// From mor1kx_decode of mor1kx_decode.v + wire du_restart_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o;// From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire exception_taken_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire execute_waiting_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire fetch_quick_branch_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_prontoespresso.v + wire fetch_ready_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire fetch_rf_re_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire fetch_sleep_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire fetch_take_exception_branch_o;// From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] fetched_pc_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire flag_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire flag_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire flag_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire [OPTION_OPERAND_WIDTH-1:0] link_addr_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire lsu_except_align_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire lsu_except_dbus_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] lsu_result_o;// From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire lsu_valid_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] mul_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v + wire overflow_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire overflow_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v + wire padv_decode_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire padv_execute_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire padv_fetch_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ... + wire pipeline_flush_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] rf_result_o; // From mor1kx_wb_mux_espresso of mor1kx_wb_mux_espresso.v + wire rf_we_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] rfa_o; // From mor1kx_rf_espresso of mor1kx_rf_espresso.v + wire [OPTION_OPERAND_WIDTH-1:0] rfb_o; // From mor1kx_rf_espresso of mor1kx_rf_espresso.v + wire spr_bus_ack_ic_i; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_npc_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire [OPTION_OPERAND_WIDTH-1:0] spr_ppc_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + wire stepping_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v + // End of automatics + + generate + if (OPTION_TCM_FETCHER=="ENABLED") + begin : fetch_tcm + + /* mor1kx_fetch_tcm_prontoespresso AUTO_TEMPLATE ( + .padv_i (padv_fetch_o), + .branch_occur_i (ctrl_branch_occur_o), + .branch_dest_i (ctrl_branch_target_o), + .pipeline_flush_i (pipeline_flush_o), + .pc_decode_o (pc_fetch_to_decode), + .decode_insn_o (insn_fetch_to_decode), + .du_restart_pc_i (du_restart_pc_o), + .du_restart_i (du_restart_o), + .fetch_take_exception_branch_i (fetch_take_exception_branch_o), + .execute_waiting_i (execute_waiting_o), + .stepping_i (stepping_o), + .flag_i (flag_o), + .flag_clear_i (flag_clear_o), + .flag_set_i (flag_set_o), + ); */ + mor1kx_fetch_tcm_prontoespresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC) + ) + mor1kx_fetch_prontoespresso + (/*AUTOINST*/ + // Outputs + .ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ibus_req_o (ibus_req_o), + .decode_insn_o (insn_fetch_to_decode), // Templated + .fetched_pc_o (fetched_pc_o[OPTION_OPERAND_WIDTH-1:0]), + .fetch_ready_o (fetch_ready_o), + .fetch_rfa_adr_o (fetch_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .fetch_rfb_adr_o (fetch_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .fetch_rf_re_o (fetch_rf_re_o), + .pc_fetch_next_o (pc_fetch_next_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_except_ibus_err_o (decode_except_ibus_err_o), + .fetch_sleep_o (fetch_sleep_o), + // Inputs + .clk (clk), + .rst (rst), + .ibus_err_i (ibus_err_i), + .ibus_ack_i (ibus_ack_i), + .ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .padv_i (padv_fetch_o), // Templated + .branch_occur_i (ctrl_branch_occur_o), // Templated + .branch_dest_i (ctrl_branch_target_o), // Templated + .du_restart_i (du_restart_o), // Templated + .du_restart_pc_i (du_restart_pc_o), // Templated + .fetch_take_exception_branch_i(fetch_take_exception_branch_o), // Templated + .execute_waiting_i (execute_waiting_o), // Templated + .du_stall_i (du_stall_i), + .stepping_i (stepping_o), // Templated + .flag_i (flag_o), // Templated + .flag_clear_i (flag_clear_o), // Templated + .flag_set_i (flag_set_o)); // Templated + + end + else + begin : fetch + + /* mor1kx_fetch_prontoespresso AUTO_TEMPLATE ( + .padv_i (padv_fetch_o), + .branch_occur_i (ctrl_branch_occur_o), + .branch_dest_i (ctrl_branch_target_o), + .ctrl_insn_done_i (ctrl_insn_done_o), + .pipeline_flush_i (pipeline_flush_o), + .pc_decode_o (pc_fetch_to_decode), + .decode_insn_o (insn_fetch_to_decode), + .du_restart_pc_i (du_restart_pc_o), + .du_restart_i (du_restart_o), + .fetch_take_exception_branch_i (fetch_take_exception_branch_o), + .execute_waiting_i (execute_waiting_o), + .stepping_i (stepping_o), + .flag_i (flag_o), + .flag_clear_i (flag_clear_o), + .flag_set_i (flag_set_o), + .spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_ic_o (spr_bus_ack_ic_i), + .spr_bus_addr_i (spr_bus_addr_o[15:0]), + .spr_bus_we_i (spr_bus_we_o), + .spr_bus_stb_i (spr_bus_stb_o), + .spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]), + ); */ + mor1kx_fetch_prontoespresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH) + ) + mor1kx_fetch_prontoespresso + (/*AUTOINST*/ + // Outputs + .ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .ibus_req_o (ibus_req_o), + .ibus_burst_o (ibus_burst_o), + .decode_insn_o (insn_fetch_to_decode), // Templated + .fetched_pc_o (fetched_pc_o[OPTION_OPERAND_WIDTH-1:0]), + .fetch_ready_o (fetch_ready_o), + .fetch_rfa_adr_o (fetch_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .fetch_rfb_adr_o (fetch_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .fetch_rf_re_o (fetch_rf_re_o), + .pc_fetch_next_o (pc_fetch_next_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_except_ibus_err_o (decode_except_ibus_err_o), + .fetch_sleep_o (fetch_sleep_o), + .fetch_quick_branch_o (fetch_quick_branch_o), + .spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), // Templated + .spr_bus_ack_ic_o (spr_bus_ack_ic_i), // Templated + // Inputs + .clk (clk), + .rst (rst), + .ibus_err_i (ibus_err_i), + .ibus_ack_i (ibus_ack_i), + .ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), + .ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]), // Templated + .padv_i (padv_fetch_o), // Templated + .branch_occur_i (ctrl_branch_occur_o), // Templated + .branch_dest_i (ctrl_branch_target_o), // Templated + .ctrl_insn_done_i (ctrl_insn_done_o), // Templated + .du_restart_i (du_restart_o), // Templated + .du_restart_pc_i (du_restart_pc_o), // Templated + .fetch_take_exception_branch_i(fetch_take_exception_branch_o), // Templated + .execute_waiting_i (execute_waiting_o), // Templated + .du_stall_i (du_stall_i), + .stepping_i (stepping_o), // Templated + .flag_i (flag_o), // Templated + .flag_clear_i (flag_clear_o), // Templated + .flag_set_i (flag_set_o), // Templated + .spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated + .spr_bus_we_i (spr_bus_we_o), // Templated + .spr_bus_stb_i (spr_bus_stb_o), // Templated + .spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0])); // Templated + end // else: !if(OPTION_TCM_FETCHER=="ENABLED") + endgenerate + + /* mor1kx_decode AUTO_TEMPLATE ( + .decode_insn_i (insn_fetch_to_decode), + .decode_op_lsu_atomic_o (), + ); */ + mor1kx_decode + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_MSYNC(FEATURE_MSYNC), + .FEATURE_PSYNC(FEATURE_PSYNC), + .FEATURE_CSYNC(FEATURE_CSYNC), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8) + ) + mor1kx_decode + (/*AUTOINST*/ + // Outputs + .decode_opc_alu_o (decode_opc_alu_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .decode_opc_alu_secondary_o (decode_opc_alu_secondary_o[`OR1K_ALU_OPC_WIDTH-1:0]), + .decode_imm16_o (decode_imm16_o[`OR1K_IMM_WIDTH-1:0]), + .decode_immediate_o (decode_immediate_o[OPTION_OPERAND_WIDTH-1:0]), + .decode_immediate_sel_o (decode_immediate_sel_o), + .decode_immjbr_upper_o (decode_immjbr_upper_o[9:0]), + .decode_rfd_adr_o (decode_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rfa_adr_o (decode_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rfb_adr_o (decode_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]), + .decode_rf_wb_o (decode_rf_wb_o), + .decode_op_jbr_o (decode_op_jbr_o), + .decode_op_jr_o (decode_op_jr_o), + .decode_op_jal_o (decode_op_jal_o), + .decode_op_bf_o (decode_op_bf_o), + .decode_op_bnf_o (decode_op_bnf_o), + .decode_op_brcond_o (decode_op_brcond_o), + .decode_op_branch_o (decode_op_branch_o), + .decode_op_alu_o (decode_op_alu_o), + .decode_op_lsu_load_o (decode_op_lsu_load_o), + .decode_op_lsu_store_o (decode_op_lsu_store_o), + .decode_op_lsu_atomic_o (decode_op_lsu_atomic_o), + .decode_lsu_length_o (decode_lsu_length_o[1:0]), + .decode_lsu_zext_o (decode_lsu_zext_o), + .decode_op_mfspr_o (decode_op_mfspr_o), + .decode_op_mtspr_o (decode_op_mtspr_o), + .decode_op_rfe_o (decode_op_rfe_o), + .decode_op_setflag_o (decode_op_setflag_o), + .decode_op_add_o (decode_op_add_o), + .decode_op_mul_o (decode_op_mul_o), + .decode_op_mul_signed_o (decode_op_mul_signed_o), + .decode_op_mul_unsigned_o (decode_op_mul_unsigned_o), + .decode_op_div_o (decode_op_div_o), + .decode_op_div_signed_o (decode_op_div_signed_o), + .decode_op_div_unsigned_o (decode_op_div_unsigned_o), + .decode_op_shift_o (decode_op_shift_o), + .decode_op_ffl1_o (decode_op_ffl1_o), + .decode_op_movhi_o (decode_op_movhi_o), + .decode_adder_do_sub_o (decode_adder_do_sub_o), + .decode_adder_do_carry_o (decode_adder_do_carry_o), + .decode_except_illegal_o (decode_except_illegal_o), + .decode_except_syscall_o (decode_except_syscall_o), + .decode_except_trap_o (decode_except_trap_o), + .decode_opc_insn_o (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .decode_insn_i (insn_fetch_to_decode)); // Templated + + /* mor1kx_execute_alu AUTO_TEMPLATE ( + .padv_execute_i (padv_execute_o), + .padv_ctrl_i (1'b1), + .opc_alu_i (decode_opc_alu_o), + .opc_alu_secondary_i (decode_opc_alu_secondary_o), + .imm16_i (decode_imm16_o), + .immediate_i (decode_immediate_o), + .immediate_sel_i (decode_immediate_sel_o), + .decode_valid_i (padv_decode_o), + .op_alu_i (decode_op_alu_o), + .op_add_i (decode_op_add_o), + .op_mul_i (decode_op_mul_o), + .op_mul_signed_i (decode_op_mul_signed_o), + .op_mul_unsigned_i (decode_op_mul_unsigned_o), + .op_div_i (decode_op_div_o), + .op_div_signed_i (decode_op_div_signed_o), + .op_div_unsigned_i (decode_op_div_unsigned_o), + .op_shift_i (decode_op_shift_o), + .op_ffl1_i (decode_op_ffl1_o), + .op_setflag_i (decode_op_setflag_o), + .op_mtspr_i (decode_op_mtspr_o), + .op_mfspr_i (decode_op_mfspr_o), + .op_movhi_i (decode_op_movhi_o), + .op_jbr_i (decode_op_jbr_o), + .op_jr_i (decode_op_jr_o), + .immjbr_upper_i (decode_immjbr_upper_o), + .pc_execute_i (spr_ppc_o), + .adder_do_sub_i (decode_adder_do_sub_o), + .adder_do_carry_i (decode_adder_do_carry_o), + .rfa_i (rfa_o), + .rfb_i (rfb_o), + .flag_i (flag_o), + .carry_i (carry_o), + ); */ + mor1kx_execute_alu + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .FEATURE_MULTIPLIER(FEATURE_MULTIPLIER), + .FEATURE_DIVIDER(FEATURE_DIVIDER), + .FEATURE_ADDC(FEATURE_ADDC), + .FEATURE_SRA(FEATURE_SRA), + .FEATURE_ROR(FEATURE_ROR), + .FEATURE_EXT(FEATURE_EXT), + .FEATURE_CMOV(FEATURE_CMOV), + .FEATURE_FFL1(FEATURE_FFL1), + .FEATURE_CUST1(FEATURE_CUST1), + .FEATURE_CUST2(FEATURE_CUST2), + .FEATURE_CUST3(FEATURE_CUST3), + .FEATURE_CUST4(FEATURE_CUST4), + .FEATURE_CUST5(FEATURE_CUST5), + .FEATURE_CUST6(FEATURE_CUST6), + .FEATURE_CUST7(FEATURE_CUST7), + .FEATURE_CUST8(FEATURE_CUST8), + .OPTION_SHIFTER(OPTION_SHIFTER) + ) + mor1kx_execute_alu + (/*AUTOINST*/ + // Outputs + .flag_set_o (flag_set_o), + .flag_clear_o (flag_clear_o), + .carry_set_o (carry_set_o), + .carry_clear_o (carry_clear_o), + .overflow_set_o (overflow_set_o), + .overflow_clear_o (overflow_clear_o), + .alu_result_o (alu_result_o[OPTION_OPERAND_WIDTH-1:0]), + .alu_valid_o (alu_valid_o), + .mul_result_o (mul_result_o[OPTION_OPERAND_WIDTH-1:0]), + .adder_result_o (adder_result_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .padv_execute_i (padv_execute_o), // Templated + .padv_ctrl_i (1'b1), // Templated + .opc_alu_i (decode_opc_alu_o), // Templated + .opc_alu_secondary_i (decode_opc_alu_secondary_o), // Templated + .imm16_i (decode_imm16_o), // Templated + .immediate_i (decode_immediate_o), // Templated + .immediate_sel_i (decode_immediate_sel_o), // Templated + .decode_valid_i (padv_decode_o), // Templated + .op_alu_i (decode_op_alu_o), // Templated + .op_add_i (decode_op_add_o), // Templated + .op_mul_i (decode_op_mul_o), // Templated + .op_mul_signed_i (decode_op_mul_signed_o), // Templated + .op_mul_unsigned_i (decode_op_mul_unsigned_o), // Templated + .op_div_i (decode_op_div_o), // Templated + .op_div_signed_i (decode_op_div_signed_o), // Templated + .op_div_unsigned_i (decode_op_div_unsigned_o), // Templated + .op_shift_i (decode_op_shift_o), // Templated + .op_ffl1_i (decode_op_ffl1_o), // Templated + .op_setflag_i (decode_op_setflag_o), // Templated + .op_mtspr_i (decode_op_mtspr_o), // Templated + .op_mfspr_i (decode_op_mfspr_o), // Templated + .op_movhi_i (decode_op_movhi_o), // Templated + .op_jbr_i (decode_op_jbr_o), // Templated + .op_jr_i (decode_op_jr_o), // Templated + .immjbr_upper_i (decode_immjbr_upper_o), // Templated + .pc_execute_i (spr_ppc_o), // Templated + .adder_do_sub_i (decode_adder_do_sub_o), // Templated + .adder_do_carry_i (decode_adder_do_carry_o), // Templated + .rfa_i (rfa_o), // Templated + .rfb_i (rfb_o), // Templated + .flag_i (flag_o), // Templated + .carry_i (carry_o)); // Templated + + + /* mor1kx_lsu_espresso AUTO_TEMPLATE ( + .padv_fetch_i (padv_fetch_o), + .lsu_adr_i (adder_result_o), + .rfb_i (rfb_o), + .op_lsu_load_i (decode_op_lsu_load_o), + .op_lsu_store_i (decode_op_lsu_store_o), + .lsu_length_i (decode_lsu_length_o), + .lsu_zext_i (decode_lsu_zext_o), + .exception_taken_i (exception_taken_o), + .du_restart_i (du_restart_o), + .stepping_i (stepping_o), + .next_fetch_done_i (fetch_ready_o), + ); */ + mor1kx_lsu_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH) + ) + mor1kx_lsu_espresso + (/*AUTOINST*/ + // Outputs + .lsu_result_o (lsu_result_o[OPTION_OPERAND_WIDTH-1:0]), + .lsu_valid_o (lsu_valid_o), + .lsu_except_dbus_o (lsu_except_dbus_o), + .lsu_except_align_o (lsu_except_align_o), + .dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_req_o (dbus_req_o), + .dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .dbus_bsel_o (dbus_bsel_o[3:0]), + .dbus_we_o (dbus_we_o), + .dbus_burst_o (dbus_burst_o), + // Inputs + .clk (clk), + .rst (rst), + .padv_fetch_i (padv_fetch_o), // Templated + .lsu_adr_i (adder_result_o), // Templated + .rfb_i (rfb_o), // Templated + .op_lsu_load_i (decode_op_lsu_load_o), // Templated + .op_lsu_store_i (decode_op_lsu_store_o), // Templated + .lsu_length_i (decode_lsu_length_o), // Templated + .lsu_zext_i (decode_lsu_zext_o), // Templated + .exception_taken_i (exception_taken_o), // Templated + .du_restart_i (du_restart_o), // Templated + .stepping_i (stepping_o), // Templated + .next_fetch_done_i (fetch_ready_o), // Templated + .dbus_err_i (dbus_err_i), + .dbus_ack_i (dbus_ack_i), + .dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0])); + + + /* mor1kx_wb_mux_espresso AUTO_TEMPLATE ( + .alu_result_i (alu_result_o), + .lsu_result_i (lsu_result_o), + .spr_i (mfspr_dat_o), + .op_jal_i (decode_op_jal_o), + .op_lsu_load_i (decode_op_lsu_load_o), + .ppc_i (spr_ppc_o), + .op_mfspr_i (decode_op_mfspr_o), + .pc_fetch_next_i (link_addr_o), + ); */ + mor1kx_wb_mux_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH) + ) + mor1kx_wb_mux_espresso + (/*AUTOINST*/ + // Outputs + .rf_result_o (rf_result_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .alu_result_i (alu_result_o), // Templated + .lsu_result_i (lsu_result_o), // Templated + .ppc_i (spr_ppc_o), // Templated + .pc_fetch_next_i (link_addr_o), // Templated + .spr_i (mfspr_dat_o), // Templated + .op_jal_i (decode_op_jal_o), // Templated + .op_lsu_load_i (decode_op_lsu_load_o), // Templated + .op_mfspr_i (decode_op_mfspr_o)); // Templated + + + /* mor1kx_rf_espresso AUTO_TEMPLATE ( + .rf_we_i (rf_we_o), + .rf_re_i (fetch_rf_re_o), + .rfd_adr_i (decode_rfd_adr_o), + .rfa_adr_i (fetch_rfa_adr_o), + .rfb_adr_i (fetch_rfb_adr_o), + .result_i (rf_result_o), + ); */ + mor1kx_rf_espresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH), + .OPTION_RF_WORDS(OPTION_RF_WORDS) + ) + mor1kx_rf_espresso + (/*AUTOINST*/ + // Outputs + .rfa_o (rfa_o[OPTION_OPERAND_WIDTH-1:0]), + .rfb_o (rfb_o[OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .rfd_adr_i (decode_rfd_adr_o), // Templated + .rfa_adr_i (fetch_rfa_adr_o), // Templated + .rfb_adr_i (fetch_rfb_adr_o), // Templated + .rf_we_i (rf_we_o), // Templated + .rf_re_i (fetch_rf_re_o), // Templated + .result_i (rf_result_o)); // Templated + + + /* Debug signals required for the debug monitor */ + function [OPTION_OPERAND_WIDTH-1:0] get_gpr; + // verilator public + input [4:0] gpr_num; + begin + // If we're writing, the value won't be in the GPR yet, so snoop + // it off the result in line. + if (rf_we_o) + get_gpr = rf_result_o; + else + get_gpr = mor1kx_rf_espresso.rfa.mem[gpr_num]; + end + endfunction // + + +`ifndef SYNTHESIS +// synthesis translate_off + task set_gpr; + // verilator public + input [4:0] gpr_num; + input [OPTION_OPERAND_WIDTH-1:0] gpr_value; + begin + mor1kx_rf_espresso.rfa.mem[gpr_num] = gpr_value; + mor1kx_rf_espresso.rfb.mem[gpr_num] = gpr_value; + end + endtask +// synthesis translate_on +`endif + + /* mor1kx_ctrl_prontoespresso AUTO_TEMPLATE ( + .ctrl_alu_result_i (alu_result_o), + .ctrl_rfb_i (rfb_o), + .ctrl_flag_set_i (flag_set_o), + .ctrl_flag_clear_i (flag_clear_o), + .pc_ctrl_i (), + .pc_fetch_next_i (pc_fetch_next_o), + .ctrl_opc_insn_i (decode_opc_insn_o), + .ctrl_branch_target_i (ctrl_branch_target_o), + .op_lsu_load_i (decode_op_lsu_load_o), + .op_lsu_store_i (decode_op_lsu_store_o), + .alu_valid_i (alu_valid_o), + .lsu_valid_i (lsu_valid_o), + .op_jr_i (decode_op_jr_o), + .op_jbr_i (decode_op_jbr_o), + .except_ibus_err_i (decode_except_ibus_err_o), + .except_illegal_i (decode_except_illegal_o), + .except_syscall_i (decode_except_syscall_o), + .except_dbus_i (lsu_except_dbus_o), + .except_trap_i (decode_except_trap_o), + .except_align_i (lsu_except_align_o), + .fetch_ready_i (fetch_ready_o), + .execute_valid_i (execute_valid_o), + .execute_waiting_i (execute_waiting_o), + .fetch_branch_taken_i (fetch_branch_taken_o), + .fetch_ppc_i (fetched_pc_o), + .fetch_sleep_i (fetch_sleep_o), + .fetch_quick_branch_i (fetch_quick_branch_o), + .rf_wb_i (decode_rf_wb_o), + .spr_bus_dat_dc_i (), + .spr_bus_ack_dc_i (), + .carry_set_i (carry_set_o), + .carry_clear_i (carry_clear_o), + .overflow_set_i (overflow_set_o), + .overflow_clear_i (overflow_clear_o), + ); */ + mor1kx_ctrl_prontoespresso + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_RESET_PC(OPTION_RESET_PC), + .FEATURE_PIC(FEATURE_PIC), + .FEATURE_TIMER(FEATURE_TIMER), + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH), + .FEATURE_DSX(FEATURE_DSX), + .FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS), + .FEATURE_OVERFLOW(FEATURE_OVERFLOW), + .FEATURE_DATACACHE(FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .FEATURE_DMMU(FEATURE_DMMU), + .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .FEATURE_IMMU(FEATURE_IMMU), + .FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS), + .FEATURE_MAC(FEATURE_MAC), + .FEATURE_MULTICORE(FEATURE_MULTICORE), + .FEATURE_SYSCALL(FEATURE_SYSCALL), + .FEATURE_TRAP(FEATURE_TRAP), + .FEATURE_RANGE(FEATURE_RANGE) + ) + mor1kx_ctrl_prontoespresso + (/*AUTOINST*/ + // Outputs + .spr_npc_o (spr_npc_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_ppc_o (spr_ppc_o[OPTION_OPERAND_WIDTH-1:0]), + .link_addr_o (link_addr_o[OPTION_OPERAND_WIDTH-1:0]), + .mfspr_dat_o (mfspr_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_mfspr_we_o (ctrl_mfspr_we_o), + .flag_o (flag_o), + .carry_o (carry_o), + .pipeline_flush_o (pipeline_flush_o), + .padv_fetch_o (padv_fetch_o), + .padv_decode_o (padv_decode_o), + .padv_execute_o (padv_execute_o), + .fetch_take_exception_branch_o (fetch_take_exception_branch_o), + .exception_taken_o (exception_taken_o), + .execute_waiting_o (execute_waiting_o), + .stepping_o (stepping_o), + .du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .du_ack_o (du_ack_o), + .du_stall_o (du_stall_o), + .du_restart_pc_o (du_restart_pc_o[OPTION_OPERAND_WIDTH-1:0]), + .du_restart_o (du_restart_o), + .spr_bus_addr_o (spr_bus_addr_o[15:0]), + .spr_bus_we_o (spr_bus_we_o), + .spr_bus_stb_o (spr_bus_stb_o), + .spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), + .spr_sr_o (spr_sr_o[15:0]), + .ctrl_branch_target_o (ctrl_branch_target_o[OPTION_OPERAND_WIDTH-1:0]), + .ctrl_insn_done_o (ctrl_insn_done_o), + .ctrl_branch_occur_o (ctrl_branch_occur_o), + .rf_we_o (rf_we_o), + // Inputs + .clk (clk), + .rst (rst), + .ctrl_alu_result_i (alu_result_o), // Templated + .ctrl_rfb_i (rfb_o), // Templated + .ctrl_flag_set_i (flag_set_o), // Templated + .ctrl_flag_clear_i (flag_clear_o), // Templated + .ctrl_opc_insn_i (decode_opc_insn_o), // Templated + .fetch_ppc_i (fetched_pc_o), // Templated + .pc_fetch_next_i (pc_fetch_next_o), // Templated + .fetch_sleep_i (fetch_sleep_o), // Templated + .except_ibus_err_i (decode_except_ibus_err_o), // Templated + .except_illegal_i (decode_except_illegal_o), // Templated + .except_syscall_i (decode_except_syscall_o), // Templated + .except_dbus_i (lsu_except_dbus_o), // Templated + .except_trap_i (decode_except_trap_o), // Templated + .except_align_i (lsu_except_align_o), // Templated + .fetch_ready_i (fetch_ready_o), // Templated + .fetch_quick_branch_i (fetch_quick_branch_o), // Templated + .alu_valid_i (alu_valid_o), // Templated + .lsu_valid_i (lsu_valid_o), // Templated + .op_lsu_load_i (decode_op_lsu_load_o), // Templated + .op_lsu_store_i (decode_op_lsu_store_o), // Templated + .op_jr_i (decode_op_jr_o), // Templated + .op_jbr_i (decode_op_jbr_o), // Templated + .irq_i (irq_i[31:0]), + .carry_set_i (carry_set_o), // Templated + .carry_clear_i (carry_clear_o), // Templated + .overflow_set_i (overflow_set_o), // Templated + .overflow_clear_i (overflow_clear_o), // Templated + .du_addr_i (du_addr_i[15:0]), + .du_stb_i (du_stb_i), + .du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]), + .du_we_i (du_we_i), + .du_stall_i (du_stall_i), + .spr_bus_dat_dc_i (), // Templated + .spr_bus_ack_dc_i (), // Templated + .spr_bus_dat_ic_i (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_ic_i (spr_bus_ack_ic_i), + .spr_bus_dat_dmmu_i (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_dmmu_i (spr_bus_ack_dmmu_i), + .spr_bus_dat_immu_i (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_immu_i (spr_bus_ack_immu_i), + .spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_mac_i (spr_bus_ack_mac_i), + .spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pmu_i (spr_bus_ack_pmu_i), + .spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_pcu_i (spr_bus_ack_pcu_i), + .spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_ack_fpu_i (spr_bus_ack_fpu_i), + .multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0]), + .rf_wb_i (decode_rf_wb_o)); // Templated + +endmodule // mor1kx_cpu_prontoespresso diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_cappuccino.v new file mode 100644 index 0000000..d6b8cd3 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_cappuccino.v @@ -0,0 +1,1501 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx control unit + + inputs from execute stage + + generate pipeline controls + + manage SPRs + + issue addresses for exceptions to fetch stage + control branches going to fetch stage + + contains tick timer + + contains PIC logic + + Copyright (C) 2012 Julius Baxter + Copyright (C) 2012-2013 Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_ctrl_cappuccino + #( + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter FEATURE_DMMU = "NONE", + parameter OPTION_DMMU_SET_WIDTH = 6, + parameter OPTION_DMMU_WAYS = 1, + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter FEATURE_IMMU = "NONE", + parameter OPTION_IMMU_SET_WIDTH = 6, + parameter OPTION_IMMU_WAYS = 1, + parameter FEATURE_TIMER = "ENABLED", + parameter FEATURE_DEBUGUNIT = "NONE", + parameter FEATURE_PERFCOUNTERS = "NONE", + parameter FEATURE_PMU = "NONE", + parameter FEATURE_MAC = "NONE", + parameter FEATURE_FPU = "NONE", + parameter FEATURE_MULTICORE = "NONE", + + parameter FEATURE_PIC = "ENABLED", + parameter OPTION_PIC_TRIGGER = "LEVEL", + parameter OPTION_PIC_NMI_WIDTH = 0, + + parameter FEATURE_DSX ="NONE", + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter OPTION_RF_NUM_SHADOW_GPR = 0, + parameter FEATURE_OVERFLOW = "NONE", + parameter FEATURE_CARRY_FLAG = "ENABLED", + + parameter SPR_SR_WIDTH = 16, + parameter SPR_SR_RESET_VALUE = 16'h8001 + ) + ( + input clk, + input rst, + + // ALU result - either jump target, SPR address + input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i, + + // LSU address, needed for effective address + input [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_i, + + // Operand B from RF might be jump address, might be value for SPR + input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i, + + input ctrl_flag_set_i, + input ctrl_flag_clear_i, + input atomic_flag_set_i, + input atomic_flag_clear_i, + + input [OPTION_OPERAND_WIDTH-1:0] pc_ctrl_i, + + input ctrl_op_mfspr_i, + input ctrl_op_mtspr_i, + input ctrl_op_rfe_i, + + // Indicate if branch will be taken based on instruction currently in + // decode stage. + input decode_branch_i, + input [OPTION_OPERAND_WIDTH-1:0] decode_branch_target_i, + + input branch_mispredict_i, + input [OPTION_OPERAND_WIDTH-1:0] execute_mispredict_target_i, + + // PC of execute stage (NPC) + input [OPTION_OPERAND_WIDTH-1:0] pc_execute_i, + + input execute_op_branch_i, + + // Exception inputs, registered on output of execute stage + input except_ibus_err_i, + input except_itlb_miss_i, + input except_ipagefault_i, + input except_ibus_align_i, + input except_illegal_i, + input except_syscall_i, + input except_dbus_i, + input except_dtlb_miss_i, + input except_dpagefault_i, + input except_trap_i, + input except_align_i, + + // Inputs from two units that can stall proceedings + input fetch_valid_i, + input decode_valid_i, + input execute_valid_i, + input ctrl_valid_i, + + input fetch_exception_taken_i, + + input decode_bubble_i, + input execute_bubble_i, + + // External IRQ lines in + input [31:0] irq_i, + + // Exception PC output, used in the lsu to properly signal dbus errors that + // has went through the store buffer + output [OPTION_OPERAND_WIDTH-1:0] ctrl_epcr_o, + // Exception PC input coming from the store buffer + input [OPTION_OPERAND_WIDTH-1:0] store_buffer_epcr_i, + + input store_buffer_err_i, + + // SPR data out + output [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o, + + // WE to RF for l.mfspr + output ctrl_mfspr_ack_o, + output ctrl_mtspr_ack_o, + + // Flag out to branch control, combinatorial + output ctrl_flag_o, + + // Arithmetic flags to and from ALU + output ctrl_carry_o, + input ctrl_carry_set_i, + input ctrl_carry_clear_i, + input ctrl_overflow_set_i, + input ctrl_overflow_clear_i, + + // FPU Status flags to and from ALU + output [`OR1K_FPCSR_RM_SIZE-1:0] ctrl_fpu_round_mode_o, + input [`OR1K_FPCSR_WIDTH-1:0] ctrl_fpcsr_i, + input ctrl_fpcsr_set_i, + + // Branch indicator from control unit (l.rfe/exception) + output ctrl_branch_exception_o, + // PC out to fetch stage for l.rfe, exceptions + output [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc_o, + + // Clear instructions from decode and fetch stage + output pipeline_flush_o, + + // Indicate that a rfe is going on + output doing_rfe_o, + + output padv_fetch_o, + output padv_decode_o, + output padv_execute_o, + output padv_ctrl_o, + + // Debug bus + input [15:0] du_addr_i, + input du_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i, + input du_we_i, + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o, + output du_ack_o, + // Stall control from debug interface + input du_stall_i, + output du_stall_o, + output [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o, + output du_restart_o, + + // SPR accesses to external units (cache, mmu, etc.) + output [15:0] spr_bus_addr_o, + output spr_bus_we_o, + output spr_bus_stb_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i, + input spr_bus_ack_dc_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i, + input spr_bus_ack_ic_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i, + input spr_bus_ack_dmmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i, + input spr_bus_ack_immu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i, + input spr_bus_ack_mac_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i, + input spr_bus_ack_pmu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i, + input spr_bus_ack_pcu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i, + input spr_bus_ack_fpu_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_gpr_dat_i, + input spr_gpr_ack_i, + output [15:0] spr_sr_o, + + output reg ctrl_bubble_o, + + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i, + input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i + ); + + // Internal signals + reg [SPR_SR_WIDTH-1:0] spr_sr; + reg [SPR_SR_WIDTH-1:0] spr_esr; + reg [OPTION_OPERAND_WIDTH-1:0] spr_epcr; + reg [OPTION_OPERAND_WIDTH-1:0] spr_eear; + reg [OPTION_OPERAND_WIDTH-1:0] spr_evbar; + + // Programmable Interrupt Control SPRs + wire [31:0] spr_picmr; + wire [31:0] spr_picsr; + + // Tick Timer SPRs + wire [31:0] spr_ttmr; + wire [31:0] spr_ttcr; + + // FPU Control & Status Register + // and related exeption signals + reg [`OR1K_FPCSR_WIDTH-1:0] spr_fpcsr; + wire except_fpu; + + reg [OPTION_OPERAND_WIDTH-1:0] spr_ppc; + reg [OPTION_OPERAND_WIDTH-1:0] spr_npc; + reg execute_delay_slot; + reg ctrl_delay_slot; + + wire execute_waiting; + reg execute_waiting_r; + + reg decode_execute_halt; + + reg exception_taken; + + reg [OPTION_OPERAND_WIDTH-1:0] last_branch_insn_pc; + reg [OPTION_OPERAND_WIDTH-1:0] last_branch_target_pc; + reg padv_ctrl; + + reg exception_r; + + reg [OPTION_OPERAND_WIDTH-1:0] exception_pc_addr; + + reg waiting_for_fetch; + + reg doing_rfe_r; + wire doing_rfe; + wire deassert_doing_rfe; + + wire exception, exception_pending; + + reg ctrl_stage_exceptions; + + wire exception_re; + + wire except_ticktimer; + wire except_pic; + + wire except_range; + + wire [15:0] spr_addr; + + wire [OPTION_OPERAND_WIDTH-1:0] b; + + wire deassert_decode_execute_halt; + + /* Debug SPRs */ + reg [31:0] spr_dmr1; + reg [31:0] spr_dmr2; + reg [31:0] spr_dsr; + reg [31:0] spr_drr; + + /* DU internal control signals */ + wire du_access; + reg cpu_stall; + wire du_restart_from_stall; + reg [5:0] pstep; + wire stepping; + wire stepped_into_delay_slot; + reg stepped_into_exception; + reg stepped_into_rfe; + wire du_npc_write; + reg du_npc_written; + wire stall_on_trap; + + /* Wires for SPR management */ + wire spr_access_valid; + wire spr_we; + wire spr_read; + wire spr_ack; + wire [OPTION_OPERAND_WIDTH-1:0] spr_write_dat; + reg [11:0] spr_access; + wire [11:0] spr_access_ack; + wire [31:0] spr_internal_read_dat [0:11]; + wire spr_read_access; + wire spr_write_access; + wire spr_bus_access; + reg [OPTION_OPERAND_WIDTH-1:0] spr_sys_group_read; + + /* Wires from mor1kx_cfgrs module */ + wire [31:0] spr_vr; + wire [31:0] spr_vr2; + wire [31:0] spr_avr; + wire [31:0] spr_upr; + wire [31:0] spr_cpucfgr; + wire [31:0] spr_dmmucfgr; + wire [31:0] spr_immucfgr; + wire [31:0] spr_dccfgr; + wire [31:0] spr_iccfgr; + wire [31:0] spr_dcfgr; + wire [31:0] spr_pccfgr; + wire [31:0] spr_isr [0:7]; + + assign b = ctrl_rfb_i; + + assign ctrl_branch_exception_o = (exception_r | ctrl_op_rfe_i | doing_rfe) & + !exception_taken; + assign exception_pending = (except_ibus_err_i | except_ibus_align_i | + except_illegal_i | except_syscall_i | + except_dbus_i | except_align_i | + except_ticktimer | except_range | except_fpu | + except_pic | except_trap_i | + except_itlb_miss_i | except_ipagefault_i | + except_dtlb_miss_i | except_dpagefault_i); + + assign exception = exception_pending & + (padv_ctrl & !ctrl_bubble_o | ctrl_stage_exceptions); + + assign exception_re = exception & !exception_r & !exception_taken; + + assign except_range = (FEATURE_RANGE!="NONE") ? spr_sr[`OR1K_SPR_SR_OVE] && + (spr_sr[`OR1K_SPR_SR_OV] | ctrl_overflow_set_i) & + !doing_rfe : 0; + + assign deassert_decode_execute_halt = fetch_exception_taken_i & + decode_execute_halt; + + assign ctrl_branch_except_pc_o = (ctrl_op_rfe_i | doing_rfe) ? spr_epcr : + exception_pc_addr; + + assign ctrl_epcr_o = ctrl_delay_slot ? pc_ctrl_i - 4 : pc_ctrl_i; + + always @(posedge clk) + ctrl_stage_exceptions <= except_align_i | except_dbus_i | except_range | + except_fpu | + except_dtlb_miss_i | except_dpagefault_i; + + always @(posedge clk) + if (exception & !exception_r) + casez( + { + except_itlb_miss_i, + except_ipagefault_i, + except_ibus_err_i, + except_illegal_i, + except_align_i, + except_ibus_align_i, + except_syscall_i, + except_dtlb_miss_i, + except_dpagefault_i, + except_trap_i, + except_dbus_i, + except_range, + except_fpu, + except_pic, + except_ticktimer + } + ) + 15'b1??????????????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_ITLB_VECTOR,8'd0}; + 15'b01?????????????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_IPF_VECTOR,8'd0}; + 15'b001????????????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_BERR_VECTOR,8'd0}; + 15'b0001???????????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_ILLEGAL_VECTOR,8'd0}; + 15'b00001??????????, + 15'b000001?????????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_ALIGN_VECTOR,8'd0}; + 15'b0000001????????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_SYSCALL_VECTOR,8'd0}; + 15'b00000001???????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_DTLB_VECTOR,8'd0}; + 15'b000000001??????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_DPF_VECTOR,8'd0}; + 15'b0000000001?????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_TRAP_VECTOR,8'd0}; + 15'b00000000001????: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_BERR_VECTOR,8'd0}; + 15'b000000000001???: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_RANGE_VECTOR,8'd0}; + 15'b0000000000001??: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_FP_VECTOR,8'd0}; + 15'b00000000000001?: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_INT_VECTOR,8'd0}; + //15'b00000000000001: + default: + exception_pc_addr <= spr_evbar | + {19'd0,`OR1K_TT_VECTOR,8'd0}; + endcase // casex (... + + assign execute_waiting = !execute_valid_i; + + assign padv_fetch_o = !execute_waiting & !cpu_stall & !decode_bubble_i + & (!stepping | (stepping & pstep[0] & !fetch_valid_i)); + + assign padv_decode_o = fetch_valid_i & !execute_waiting & + !decode_execute_halt & !cpu_stall + & (!stepping | (stepping & pstep[1])); + + assign padv_execute_o = ((decode_valid_i & !execute_waiting & + /* Stop fetch before exception branch continuing */ + !(exception_r & fetch_exception_taken_i)) | + (!execute_waiting & execute_waiting_r & + fetch_valid_i) | + // Case where execute became ready before fetch + // after delay in execute stage + (waiting_for_fetch & fetch_valid_i)) & + // Not exceptions occurring + !decode_execute_halt & !exception_re & !ctrl_op_rfe_i + & !cpu_stall & (!stepping | (stepping & pstep[2])); + + assign padv_ctrl_o = padv_ctrl; + + assign spr_addr = du_access ? du_addr_i : ctrl_alu_result_i[15:0]; + assign ctrl_mfspr_ack_o = spr_ack; + assign ctrl_mtspr_ack_o = spr_ack; + + // Pipeline flush + assign pipeline_flush_o = (padv_ctrl & ctrl_op_rfe_i) | + (exception_re) | + cpu_stall; + + // Flag output + wire ctrl_flag_clear = ctrl_flag_clear_i | atomic_flag_clear_i; + wire ctrl_flag_set = ctrl_flag_set_i | atomic_flag_set_i; + + assign ctrl_flag_o = (!ctrl_flag_clear & spr_sr[`OR1K_SPR_SR_F]) | + ctrl_flag_set; + + // Carry output + assign ctrl_carry_o = FEATURE_CARRY_FLAG!="NONE" & + (!ctrl_carry_clear_i & spr_sr[`OR1K_SPR_SR_CY] | + ctrl_carry_set_i); + + // Ctrl stage pipeline advance signal is one cycle behind execute stage's + always @(posedge clk `OR_ASYNC_RST) + if (rst) + padv_ctrl <= 0; + else + padv_ctrl <= padv_execute_o; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_waiting_r <= 0; + else if (!execute_waiting) + execute_waiting_r <= 0; + else if (decode_valid_i & execute_waiting) + execute_waiting_r <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_execute_halt <= 0; + else if (du_restart_from_stall) + decode_execute_halt <= 0; + else if (decode_execute_halt & deassert_decode_execute_halt) + decode_execute_halt <= 0; + else if ((ctrl_op_rfe_i | exception) & !decode_execute_halt & + !exception_taken) + decode_execute_halt <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + exception_r <= 0; + else if (exception_taken | du_restart_from_stall) + exception_r <= 0; + else if (exception & !exception_r) + exception_r <= 1; + + // Signal to indicate that the incoming exception or l.rfe has been taken + // and we're waiting for it to propagate through the pipeline. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + exception_taken <= 0; + else if (exception_taken) + exception_taken <= 0; + else if (exception_r & fetch_exception_taken_i) + exception_taken <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + last_branch_insn_pc <= 0; + else if (padv_execute_o & execute_op_branch_i) + last_branch_insn_pc <= pc_execute_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + last_branch_target_pc <= 0; + else if (padv_execute_o & branch_mispredict_i) + last_branch_target_pc <= execute_mispredict_target_i; + else if (padv_decode_o & decode_branch_i) + last_branch_target_pc <= decode_branch_target_i; + + // Used to gate execute stage's advance signal in the case where a LSU op has + // finished before the next instruction has been fetched. Typically this + // occurs when not using icache and doing lots of memory accesses. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + waiting_for_fetch <= 0; + else if (fetch_valid_i) + waiting_for_fetch <= 0; + else if (!execute_waiting & execute_waiting_r & !fetch_valid_i) + waiting_for_fetch <= 1; + + + assign doing_rfe = ((padv_ctrl & ctrl_op_rfe_i) | doing_rfe_r) & + !deassert_doing_rfe; + + assign doing_rfe_o = doing_rfe; + + assign deassert_doing_rfe = fetch_exception_taken_i & doing_rfe_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + doing_rfe_r <= 0; + else if (deassert_doing_rfe) + doing_rfe_r <= 0; + else if (padv_ctrl) + doing_rfe_r <= ctrl_op_rfe_i; + + assign spr_sr_o = spr_sr; + + + // FPU related: FPCSR and exception + generate + `ifdef OR1K_FPCSR_MASK_FLAGS + reg [`OR1K_FPCSR_ALLF_SIZE-1:0] spr_fpcsr_mf; // mask for FPU flags + `endif + + /* verilator lint_off WIDTH */ + if (FEATURE_FPU != "NONE") begin : fpu_csr_ena + /* verilator lint_on WIDTH */ + assign ctrl_fpu_round_mode_o = spr_fpcsr[`OR1K_FPCSR_RM]; + + // select all flags + `ifdef OR1K_FPCSR_MASK_FLAGS + wire [`OR1K_FPCSR_ALLF_SIZE-1:0] masked_fpres_flags = + ctrl_fpcsr_i[`OR1K_FPCSR_ALLF] & spr_fpcsr_mf; + + wire [`OR1K_FPCSR_ALLF_SIZE-1:0] masked_fpcsr_flags = + spr_fpcsr[`OR1K_FPCSR_ALLF] & spr_fpcsr_mf; + + + wire [`OR1K_FPCSR_ALLF_SIZE-1:0] fpu_allf = + ctrl_fpcsr_set_i ? masked_fpres_flags : + masked_fpcsr_flags; + `else + wire [`OR1K_FPCSR_ALLF_SIZE-1:0] fpu_allf = + ctrl_fpcsr_set_i ? ctrl_fpcsr_i[`OR1K_FPCSR_ALLF] : + spr_fpcsr[`OR1K_FPCSR_ALLF]; + `endif + + assign except_fpu = (~doing_rfe) & + spr_fpcsr[`OR1K_FPCSR_FPEE] & + (|fpu_allf); + + // FPU Control & status register + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + spr_fpcsr <= `OR1K_FPCSR_RESET_VALUE; + `ifdef OR1K_FPCSR_MASK_FLAGS + spr_fpcsr_mf <= `OR1K_FPCSR_MASK_RESET_VALUE; + `endif + end + else if (exception_re) begin + spr_fpcsr[`OR1K_FPCSR_ALLF] <= fpu_allf; + spr_fpcsr[`OR1K_FPCSR_RM] <= spr_fpcsr[`OR1K_FPCSR_RM]; + spr_fpcsr[`OR1K_FPCSR_FPEE] <= 1'b0; + end + else if ((spr_we & spr_access[`OR1K_SPR_SYS_BASE] & + (spr_sr[`OR1K_SPR_SR_SM] & padv_ctrl | du_access)) && + `SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR)) begin + spr_fpcsr <= spr_write_dat[`OR1K_FPCSR_WIDTH-1:0]; // update all fields + `ifdef OR1K_FPCSR_MASK_FLAGS + spr_fpcsr_mf <= spr_write_dat[`OR1K_FPCSR_MASK_ALL]; + `endif + end + else if (padv_ctrl & ctrl_fpcsr_set_i) begin + spr_fpcsr[`OR1K_FPCSR_ALLF] <= fpu_allf; + spr_fpcsr[`OR1K_FPCSR_RM] <= spr_fpcsr[`OR1K_FPCSR_RM]; + spr_fpcsr[`OR1K_FPCSR_FPEE] <= spr_fpcsr[`OR1K_FPCSR_FPEE]; + end + end // FPCSR reg's always(@posedge clk) + end + else begin : fpu_csr_none + assign ctrl_fpu_round_mode_o = {`OR1K_FPCSR_RM_SIZE{1'b0}}; + assign except_fpu = 0; + // FPU Control & status register + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + spr_fpcsr <= {`OR1K_FPCSR_WIDTH{1'b0}}; + `ifdef OR1K_FPCSR_MASK_FLAGS + spr_fpcsr_mf <= {`OR1K_FPCSR_ALLF_SIZE{1'b0}}; + `endif + end + end // FPCSR reg's always(@posedge clk) + end + endgenerate // FPU related: FPCSR and exception + + + // Supervision register + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_sr <= SPR_SR_RESET_VALUE; + else if (exception_re) + begin + // Go into supervisor mode, disable interrupts, MMUs + spr_sr[`OR1K_SPR_SR_SM ] <= 1'b1; + if (FEATURE_TIMER!="NONE") + spr_sr[`OR1K_SPR_SR_TEE ] <= 1'b0; + if (FEATURE_PIC!="NONE") + spr_sr[`OR1K_SPR_SR_IEE ] <= 1'b0; + if (FEATURE_DMMU!="NONE") + spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0; + if (FEATURE_IMMU!="NONE") + spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0; + if (FEATURE_DSX!="NONE") + spr_sr[`OR1K_SPR_SR_DSX ] <= ctrl_delay_slot; + if (FEATURE_OVERFLOW!="NONE") + spr_sr[`OR1K_SPR_SR_OVE ] <= 1'b0; + end + else if ((spr_we & spr_access[`OR1K_SPR_SYS_BASE] & + (spr_sr[`OR1K_SPR_SR_SM] & padv_ctrl | du_access)) && + `SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_SR_ADDR)) + begin + spr_sr[`OR1K_SPR_SR_SM ] <= spr_write_dat[`OR1K_SPR_SR_SM ]; + + spr_sr[`OR1K_SPR_SR_F ] <= spr_write_dat[`OR1K_SPR_SR_F ]; + + if (FEATURE_TIMER!="NONE") + spr_sr[`OR1K_SPR_SR_TEE ] <= spr_write_dat[`OR1K_SPR_SR_TEE ]; + + if (FEATURE_PIC!="NONE") + spr_sr[`OR1K_SPR_SR_IEE ] <= spr_write_dat[`OR1K_SPR_SR_IEE ]; + + if (FEATURE_DATACACHE!="NONE") + spr_sr[`OR1K_SPR_SR_DCE ] <= spr_write_dat[`OR1K_SPR_SR_DCE ]; + + if (FEATURE_INSTRUCTIONCACHE!="NONE") + spr_sr[`OR1K_SPR_SR_ICE ] <= spr_write_dat[`OR1K_SPR_SR_ICE ]; + + if (FEATURE_DMMU!="NONE") + spr_sr[`OR1K_SPR_SR_DME ] <= spr_write_dat[`OR1K_SPR_SR_DME ]; + + if (FEATURE_IMMU!="NONE") + spr_sr[`OR1K_SPR_SR_IME ] <= spr_write_dat[`OR1K_SPR_SR_IME ]; + + if (FEATURE_FASTCONTEXTS!="NONE") + spr_sr[`OR1K_SPR_SR_CE ] <= spr_write_dat[`OR1K_SPR_SR_CE ]; + + if (FEATURE_CARRY_FLAG!="NONE") + spr_sr[`OR1K_SPR_SR_CY] <= spr_write_dat[`OR1K_SPR_SR_CY]; + + if (FEATURE_OVERFLOW!="NONE") begin + spr_sr[`OR1K_SPR_SR_OV ] <= spr_write_dat[`OR1K_SPR_SR_OV ]; + spr_sr[`OR1K_SPR_SR_OVE ] <= spr_write_dat[`OR1K_SPR_SR_OVE ]; + end + + if (FEATURE_DSX!="NONE") + spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ]; + + spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ]; + end + else if (padv_ctrl) + begin + spr_sr[`OR1K_SPR_SR_F ] <= ctrl_flag_set ? 1 : + ctrl_flag_clear ? 0 : + spr_sr[`OR1K_SPR_SR_F ]; + + if (FEATURE_CARRY_FLAG!="NONE") + spr_sr[`OR1K_SPR_SR_CY] <= ctrl_carry_set_i ? 1 : + ctrl_carry_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_CY]; + if (FEATURE_OVERFLOW!="NONE") + spr_sr[`OR1K_SPR_SR_OV ] <= ctrl_overflow_set_i ? 1 : + ctrl_overflow_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_OV ]; + // Skip FO. TODO: make this even more selective. + if (ctrl_op_rfe_i) + spr_sr[14:0] <= spr_esr[14:0]; + end + + + // Exception SR + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_esr <= SPR_SR_RESET_VALUE; + else if (exception_re) + begin + spr_esr <= spr_sr; + if (FEATURE_OVERFLOW!="NONE") + begin + if (ctrl_overflow_set_i) + spr_esr[`OR1K_SPR_SR_OV] <= 1'b1; + else if (ctrl_overflow_clear_i) + spr_esr[`OR1K_SPR_SR_OV] <= 1'b0; + end + if (FEATURE_CARRY_FLAG!="NONE") begin + if (ctrl_carry_set_i) + spr_esr[`OR1K_SPR_SR_CY] <= 1'b1; + else if (ctrl_carry_clear_i) + spr_esr[`OR1K_SPR_SR_CY] <= 1'b0; + end + end + else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] && + `SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_ESR0_ADDR)) + spr_esr <= spr_write_dat[SPR_SR_WIDTH-1:0]; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_bubble_o <= 0; + else if (padv_execute_o) + ctrl_bubble_o <= execute_bubble_i; + + // Exception PC + always @(posedge clk) + if (exception_re) begin + if (except_ibus_err_i) + spr_epcr <= last_branch_insn_pc; + // Syscall is a special case, we return back to the instruction _after_ + // the syscall instruction, unless the syscall was in a delay slot + else if (except_syscall_i) + spr_epcr <= ctrl_delay_slot ? ctrl_epcr_o : pc_ctrl_i + 4; + else if (store_buffer_err_i) + spr_epcr <= store_buffer_epcr_i; + // Don't update EPCR on software breakpoint + else if (!(stall_on_trap & except_trap_i)) + spr_epcr <= ctrl_epcr_o; + end else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] && + `SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_EPCR0_ADDR)) begin + spr_epcr <= spr_write_dat; + end + + // Exception Effective Address + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}}; + else if (/*padv_ctrl & exception*/ exception_re) + begin + if (except_ibus_err_i | except_itlb_miss_i | except_ipagefault_i) + spr_eear <= pc_ctrl_i; + else + spr_eear <= ctrl_lsu_adr_i; + end + + // Track the PC + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_ppc <= OPTION_RESET_PC; + else if (padv_ctrl) + spr_ppc <= pc_ctrl_i; + + // Generate the NPC for SPR accesses + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_npc <= OPTION_RESET_PC; + else if (du_npc_write) + spr_npc <= du_dat_i; + else if (du_npc_written) + spr_npc <= spr_npc; + else if (stepping) begin + if (stepped_into_rfe) + spr_npc <= spr_epcr; + else if (stepped_into_delay_slot) + spr_npc <= last_branch_target_pc; + else if (stepped_into_exception) + spr_npc <= exception_pc_addr; + else + spr_npc <= pc_ctrl_i + 4; + end else if (stall_on_trap & padv_ctrl & except_trap_i) + spr_npc <= pc_ctrl_i; + else if (cpu_stall & padv_ctrl) + spr_npc <= ctrl_delay_slot ? pc_ctrl_i - 4 : pc_ctrl_i; + else if (!cpu_stall) + spr_npc <= pc_execute_i; + + // Exception Vector Address + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_evbar <= {OPTION_OPERAND_WIDTH{1'b0}}; + else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] && + `SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_EVBAR_ADDR)) + spr_evbar <= {spr_write_dat[OPTION_OPERAND_WIDTH-1:13], 13'd0}; + + // Remember when we're in a delay slot in execute stage. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_delay_slot <= 0; + else if (padv_execute_o) + execute_delay_slot <= execute_op_branch_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_delay_slot <= 0; + else if (padv_execute_o) + ctrl_delay_slot <= execute_delay_slot; + + mor1kx_cfgrs + #(.FEATURE_PIC (FEATURE_PIC), + .FEATURE_TIMER (FEATURE_TIMER), + .OPTION_PIC_TRIGGER (OPTION_PIC_TRIGGER), + .FEATURE_DSX (FEATURE_DSX), + .FEATURE_FASTCONTEXTS (FEATURE_FASTCONTEXTS), + .OPTION_RF_NUM_SHADOW_GPR (OPTION_RF_NUM_SHADOW_GPR), + .FEATURE_OVERFLOW (FEATURE_OVERFLOW), + .FEATURE_DATACACHE (FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH (OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH (OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS (OPTION_DCACHE_WAYS), + .FEATURE_DMMU (FEATURE_DMMU), + .OPTION_DMMU_SET_WIDTH (OPTION_DMMU_SET_WIDTH), + .OPTION_DMMU_WAYS (OPTION_DMMU_WAYS), + .FEATURE_INSTRUCTIONCACHE (FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH (OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH (OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS (OPTION_ICACHE_WAYS), + .FEATURE_IMMU (FEATURE_IMMU), + .OPTION_IMMU_SET_WIDTH (OPTION_IMMU_SET_WIDTH), + .OPTION_IMMU_WAYS (OPTION_IMMU_WAYS), + .FEATURE_DEBUGUNIT (FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS (FEATURE_PERFCOUNTERS), + .FEATURE_MAC (FEATURE_MAC), + .FEATURE_FPU (FEATURE_FPU), // mor1kx_cfgrs instance + .FEATURE_SYSCALL (FEATURE_SYSCALL), + .FEATURE_TRAP (FEATURE_TRAP), + .FEATURE_RANGE (FEATURE_RANGE), + .FEATURE_DELAYSLOT ("ENABLED"), + .FEATURE_EVBAR ("ENABLED") + ) + mor1kx_cfgrs + (/*AUTOINST*/ + // Outputs + .spr_vr (spr_vr[31:0]), + .spr_vr2 (spr_vr2[31:0]), + .spr_upr (spr_upr[31:0]), + .spr_cpucfgr (spr_cpucfgr[31:0]), + .spr_dmmucfgr (spr_dmmucfgr[31:0]), + .spr_immucfgr (spr_immucfgr[31:0]), + .spr_dccfgr (spr_dccfgr[31:0]), + .spr_iccfgr (spr_iccfgr[31:0]), + .spr_dcfgr (spr_dcfgr[31:0]), + .spr_pccfgr (spr_pccfgr[31:0]), + .spr_avr (spr_avr[31:0])); + + /* Implementation-specific registers */ + assign spr_isr[0] = 0; + assign spr_isr[1] = 0; + assign spr_isr[2] = 0; + assign spr_isr[3] = 0; + assign spr_isr[4] = 0; + assign spr_isr[5] = 0; + assign spr_isr[6] = 0; + assign spr_isr[7] = 0; + + // System group (0) SPR data out + always @* begin + spr_sys_group_read = 0; + if (spr_access[`OR1K_SPR_SYS_BASE]) + case(`SPR_OFFSET(spr_addr)) + `SPR_OFFSET(`OR1K_SPR_VR_ADDR): + spr_sys_group_read = spr_vr; + `SPR_OFFSET(`OR1K_SPR_VR2_ADDR): + spr_sys_group_read = {spr_vr2[31:8], `MOR1KX_PIPEID_CAPPUCCINO}; + `SPR_OFFSET(`OR1K_SPR_AVR_ADDR): + spr_sys_group_read = spr_avr; + `SPR_OFFSET(`OR1K_SPR_UPR_ADDR): + spr_sys_group_read = spr_upr; + `SPR_OFFSET(`OR1K_SPR_CPUCFGR_ADDR): + spr_sys_group_read = spr_cpucfgr; + `SPR_OFFSET(`OR1K_SPR_DMMUCFGR_ADDR): + spr_sys_group_read = spr_dmmucfgr; + `SPR_OFFSET(`OR1K_SPR_IMMUCFGR_ADDR): + spr_sys_group_read = spr_immucfgr; + `SPR_OFFSET(`OR1K_SPR_DCCFGR_ADDR): + spr_sys_group_read = spr_dccfgr; + `SPR_OFFSET(`OR1K_SPR_ICCFGR_ADDR): + spr_sys_group_read = spr_iccfgr; + `SPR_OFFSET(`OR1K_SPR_DCFGR_ADDR): + spr_sys_group_read = spr_dcfgr; + `SPR_OFFSET(`OR1K_SPR_PCCFGR_ADDR): + spr_sys_group_read = spr_pccfgr; + `SPR_OFFSET(`OR1K_SPR_NPC_ADDR): + spr_sys_group_read = spr_npc; + `SPR_OFFSET(`OR1K_SPR_SR_ADDR): + spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}}, + spr_sr}; + + `SPR_OFFSET(`OR1K_SPR_PPC_ADDR): + spr_sys_group_read = spr_ppc; + `ifdef OR1K_FPCSR_MASK_FLAGS + `SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR): + spr_sys_group_read = + {{(OPTION_OPERAND_WIDTH-`OR1K_FPCSR_WIDTH-`OR1K_FPCSR_ALLF_SIZE){1'b0}}, + spr_fpcsr_mf,spr_fpcsr}; + `else + `SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR): + spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-`OR1K_FPCSR_WIDTH){1'b0}}, + spr_fpcsr}; + `endif + `SPR_OFFSET(`OR1K_SPR_EPCR0_ADDR): + spr_sys_group_read = spr_epcr; + `SPR_OFFSET(`OR1K_SPR_EEAR0_ADDR): + spr_sys_group_read = spr_eear; + `SPR_OFFSET(`OR1K_SPR_ESR0_ADDR): + spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}}, + spr_esr}; + `SPR_OFFSET(`OR1K_SPR_EVBAR_ADDR): + spr_sys_group_read = spr_evbar; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR): + spr_sys_group_read = spr_isr[0]; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +1: + spr_sys_group_read = spr_isr[1]; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +2: + spr_sys_group_read = spr_isr[2]; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +3: + spr_sys_group_read = spr_isr[3]; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +4: + spr_sys_group_read = spr_isr[4]; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +5: + spr_sys_group_read = spr_isr[5]; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +6: + spr_sys_group_read = spr_isr[6]; + `SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +7: + spr_sys_group_read = spr_isr[7]; + + `SPR_OFFSET(`OR1K_SPR_COREID_ADDR): + // If the multicore feature is activated this address returns the + // core identifier, 0 otherwise + spr_sys_group_read = (FEATURE_MULTICORE!="NONE") ? + multicore_coreid_i : 0; + `SPR_OFFSET(`OR1K_SPR_NUMCORES_ADDR): + // If the multicore feature is activated this address returns the + // core identifier, 0 otherwise + spr_sys_group_read = (FEATURE_MULTICORE!="NONE") ? + multicore_numcores_i : 0; + + default: + // GPR read + if (spr_addr[10:9] == 2'h2) + spr_sys_group_read = spr_gpr_dat_i; // Register file + endcase + end + + /* System group read data MUX in */ + assign spr_internal_read_dat[`OR1K_SPR_SYS_BASE] = spr_sys_group_read; + /* System group ack generation */ + + assign spr_access_ack[`OR1K_SPR_SYS_BASE] = spr_access[`OR1K_SPR_SYS_BASE] & + ((spr_addr[10:9] == 2'h2) ? + spr_gpr_ack_i : 1); + + // + // Generate data to the register file for mfspr operations + // Read datas are simply ORed since set to 0 when not + // concerned by spr access. + // + assign mfspr_dat_o = spr_internal_read_dat[`OR1K_SPR_SYS_BASE] | + spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] | + spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] | + spr_internal_read_dat[`OR1K_SPR_DC_BASE] | + spr_internal_read_dat[`OR1K_SPR_IC_BASE] | + spr_internal_read_dat[`OR1K_SPR_MAC_BASE] | + spr_internal_read_dat[`OR1K_SPR_DU_BASE] | + spr_internal_read_dat[`OR1K_SPR_PC_BASE] | + spr_internal_read_dat[`OR1K_SPR_PM_BASE] | + spr_internal_read_dat[`OR1K_SPR_PIC_BASE] | + spr_internal_read_dat[`OR1K_SPR_TT_BASE] | + spr_internal_read_dat[`OR1K_SPR_FPU_BASE]; + + // PIC SPR control + generate + + if (FEATURE_PIC !="NONE") begin : pic + + /* mor1kx_pic AUTO_TEMPLATE ( + .spr_picsr_o (spr_picsr), + .spr_picmr_o (spr_picmr), + .spr_bus_ack (spr_access_ack[`OR1K_SPR_PIC_BASE]), + .spr_dat_o (spr_internal_read_dat[`OR1K_SPR_PIC_BASE]), + // Inputs + .spr_we_i (spr_we), + .spr_access_i (spr_access[`OR1K_SPR_PIC_BASE]) + .spr_addr_i (spr_addr), + .spr_dat_i (spr_write_dat), + );*/ + mor1kx_pic + #( + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH) + ) + mor1kx_pic + (/*AUTOINST*/ + // Outputs + .spr_picmr_o (spr_picmr), // Templated + .spr_picsr_o (spr_picsr), // Templated + .spr_bus_ack (spr_access_ack[`OR1K_SPR_PIC_BASE]), // Templated + .spr_dat_o (spr_internal_read_dat[`OR1K_SPR_PIC_BASE]), // Templated + // Inputs + .clk (clk), + .rst (rst), + .irq_i (irq_i[31:0]), + .spr_access_i (spr_access[`OR1K_SPR_PIC_BASE]), // Templated + .spr_we_i (spr_we), // Templated + .spr_addr_i (spr_addr), // Templated + .spr_dat_i (spr_write_dat)); // Templated + + + assign except_pic = (|spr_picsr) & spr_sr[`OR1K_SPR_SR_IEE] & + !ctrl_op_mtspr_i & !doing_rfe; + end + else begin + assign except_pic = 0; + assign spr_picsr = 0; + assign spr_picmr = 0; + assign spr_access_ack[`OR1K_SPR_PIC_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_PIC_BASE] = 0; + end // else: !if(FEATURE_PIC !="NONE") + endgenerate + + + generate + if (FEATURE_TIMER!="NONE") begin : tt + + /* mor1kx_ticktimer AUTO_TEMPLATE ( + .spr_ttmr_o (spr_ttmr), + .spr_ttcr_o (spr_ttcr), + .spr_bus_ack (spr_access_ack[`OR1K_SPR_TT_BASE]), + .spr_dat_o (spr_internal_read_dat[`OR1K_SPR_TT_BASE]), + // Inputs + .spr_access_i (spr_access[`OR1K_SPR_TT_BASE]), + .spr_we_i (spr_we), + .spr_addr_i (spr_addr), + .spr_dat_i (spr_write_dat), + );*/ + mor1kx_ticktimer mor1kx_ticktimer + (/*AUTOINST*/ + // Outputs + .spr_ttmr_o (spr_ttmr), // Templated + .spr_ttcr_o (spr_ttcr), // Templated + .spr_bus_ack (spr_access_ack[`OR1K_SPR_TT_BASE]), // Templated + .spr_dat_o (spr_internal_read_dat[`OR1K_SPR_TT_BASE]), // Templated + // Inputs + .clk (clk), + .rst (rst), + .spr_access_i (spr_access[`OR1K_SPR_TT_BASE]), // Templated + .spr_we_i (spr_we), // Templated + .spr_addr_i (spr_addr), // Templated + .spr_dat_i (spr_write_dat)); // Templated + + assign except_ticktimer = spr_ttmr[28] & spr_sr[`OR1K_SPR_SR_TEE] & + !ctrl_op_mtspr_i & !doing_rfe; + + end // if (FEATURE_TIMER!="NONE") + else begin + assign except_ticktimer = 0; + assign spr_ttmr = 0; + assign spr_ttcr = 0; + assign spr_access_ack[`OR1K_SPR_TT_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_TT_BASE] = 0; + end // else: !if(FEATURE_TIMER!="NONE") + endgenerate + + /* SPR access control - allow accesses from either the instructions or from + the debug interface */ + assign spr_read_access = (ctrl_op_mfspr_i | (du_access & !du_we_i)); + assign spr_write_access = (ctrl_op_mtspr_i | (du_access & du_we_i)); + + assign spr_write_dat = du_access ? du_dat_i : b; + assign spr_we = spr_write_access & spr_access_valid; + assign spr_read = spr_read_access & spr_access_valid; + + /* A bus out to other units that live outside of the control unit */ + assign spr_bus_addr_o = spr_addr; + assign spr_bus_we_o = spr_write_access & spr_access_valid & spr_bus_access; + assign spr_bus_stb_o = (spr_read_access | spr_write_access) & + spr_access_valid & spr_bus_access; + assign spr_bus_dat_o = spr_write_dat; + + /* Select spr */ + always @(*) begin + spr_access <= 0; + case(`SPR_BASE(spr_addr)) + // System group + `OR1K_SPR_SYS_BASE: + spr_access[`OR1K_SPR_SYS_BASE] <= 1'b1; + // DMMU + `OR1K_SPR_DMMU_BASE: + spr_access[`OR1K_SPR_DMMU_BASE] <= (FEATURE_DMMU!="NONE"); + // IMMU + `OR1K_SPR_IMMU_BASE: + spr_access[`OR1K_SPR_IMMU_BASE] <= (FEATURE_IMMU!="NONE"); + // Data cache + `OR1K_SPR_DC_BASE: + spr_access[`OR1K_SPR_DC_BASE] <= (FEATURE_DATACACHE!="NONE"); + // Instruction cache + `OR1K_SPR_IC_BASE: + spr_access[`OR1K_SPR_IC_BASE] <= (FEATURE_INSTRUCTIONCACHE!= "NONE"); + // MAC unit + `OR1K_SPR_MAC_BASE: + spr_access[`OR1K_SPR_MAC_BASE] <= (FEATURE_MAC!="NONE"); + // Debug unit + `OR1K_SPR_DU_BASE: + spr_access[`OR1K_SPR_DU_BASE] <= (FEATURE_DEBUGUNIT!="NONE"); + // Performance counters + `OR1K_SPR_PC_BASE: + spr_access[`OR1K_SPR_PC_BASE] <= (FEATURE_PERFCOUNTERS!="NONE"); + // Power Management + `OR1K_SPR_PM_BASE: + spr_access[`OR1K_SPR_PM_BASE] <= (FEATURE_PMU!="NONE"); + // PIC + `OR1K_SPR_PIC_BASE: + spr_access[`OR1K_SPR_PIC_BASE] <= (FEATURE_PIC!="NONE"); + // Tick timer + `OR1K_SPR_TT_BASE: + spr_access[`OR1K_SPR_TT_BASE] <= (FEATURE_TIMER!="NONE"); + // FPU + `OR1K_SPR_FPU_BASE: + spr_access[`OR1K_SPR_FPU_BASE] <= (FEATURE_FPU!="NONE"); + /* generate invalid if the group is not present in the design */ + default: + spr_access <= 0; + endcase + end + + // Is the SPR in the design? + assign spr_access_valid = |spr_access; + + assign spr_ack = (|spr_access_ack) | !spr_access_valid; + + /* Is a SPR bus access needed, or is the requested SPR in this file? */ + assign spr_bus_access = /* Any of the units we don't have in this file */ + /* System group */ + !(spr_access[`OR1K_SPR_SYS_BASE] || + /* Debug Group */ + spr_access[`OR1K_SPR_DU_BASE] || + /* PIC Group */ + spr_access[`OR1K_SPR_PIC_BASE] || + /* Tick Group */ + spr_access[`OR1K_SPR_TT_BASE]) || + // GPR + (spr_access[`OR1K_SPR_SYS_BASE] && + spr_addr[10:9]==2'h2); + + generate + if (FEATURE_DEBUGUNIT!="NONE") begin : du + + reg [OPTION_OPERAND_WIDTH-1:0] du_read_dat; + + reg du_ack; + reg du_stall_r; + reg [1:0] branch_step; + + assign du_access = du_stb_i; + + // Generate ack back to the debug interface bus + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_ack <= 0; + else if (du_ack) + du_ack <= 0; + else if (du_stb_i) begin + du_ack <= spr_ack; + end + + assign du_ack_o = du_ack; + + /* Data back to the debug bus */ + always @(posedge clk) + du_read_dat <= mfspr_dat_o; + + assign du_dat_o = du_read_dat; + + always @(posedge clk) + if (rst) + cpu_stall <= 0; + else if (!du_stall_i) + cpu_stall <= 0; + else if (padv_execute_o & !execute_bubble_i & du_stall_i | + du_stall_o) + cpu_stall <= 1; + + /* goes out to the debug interface and comes back 1 cycle later + via du_stall_i */ + assign du_stall_o = stepping & pstep[4] | + (stall_on_trap & padv_ctrl & except_trap_i); + + /* Pulse to indicate we're restarting after a stall */ + assign du_restart_from_stall = du_stall_r & !du_stall_i; + + /* NPC debug control logic */ + assign du_npc_write = (du_we_i && du_addr_i==`OR1K_SPR_NPC_ADDR && + du_ack_o); + + /* Pick the traps-cause-stall bit out of the DSR */ + assign stall_on_trap = spr_dsr[`OR1K_SPR_DSR_TE]; + + /* record if NPC was written while we were stalled. + If so, we will use this value for restarting */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_npc_written <= 0; + else if (du_restart_from_stall) + du_npc_written <= 0; + else if (du_npc_write) + du_npc_written <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + stepped_into_exception <= 0; + else if (du_restart_from_stall) + stepped_into_exception <= 0; + else if (exception & stepping & (padv_ctrl | ctrl_stage_exceptions)) + stepped_into_exception <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + stepped_into_rfe <= 0; + else if (du_restart_from_stall) + stepped_into_rfe <= 0; + else if (stepping & padv_ctrl) + stepped_into_rfe <= ctrl_op_rfe_i; + + assign du_restart_pc_o = spr_npc; + + assign du_restart_o = du_restart_from_stall; + + /* Indicate when we're stepping */ + assign stepping = spr_dmr1[`OR1K_SPR_DMR1_ST] & + spr_dsr[`OR1K_SPR_DSR_TE]; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + pstep <= 0; + else if (du_restart_from_stall & stepping) + pstep <= 6'h1; + else if ((pstep[0] & fetch_valid_i) | + /* decode is always single cycle */ + (pstep[1] & padv_decode_o) | + /* execute stage */ + (pstep[2] & (execute_valid_i | ctrl_stage_exceptions)) | + /* ctrl stage */ + (pstep[3] & (ctrl_valid_i | ctrl_stage_exceptions)) | + pstep[4]) + pstep <= {pstep[4:0],1'b0}; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + branch_step <= 0; + else if (du_npc_written) + branch_step <= 0; + else if (stepping & pstep[2]) + branch_step <= {branch_step[0], decode_branch_i}; + else if (!stepping & padv_ctrl) + branch_step <= {branch_step[0], ctrl_delay_slot}; + + assign stepped_into_delay_slot = branch_step[1] & stepping; + + /* Signals for waveform debuging */ + wire [31:0] spr_read_data_group_0; + assign spr_read_data_group_0 = spr_internal_read_dat[0]; + wire [31:0] spr_read_data_group_1; + assign spr_read_data_group_1 = spr_internal_read_dat[1]; + wire [31:0] spr_read_data_group_2; + assign spr_read_data_group_2 = spr_internal_read_dat[2]; + wire [31:0] spr_read_data_group_3; + assign spr_read_data_group_3 = spr_internal_read_dat[3]; + wire [31:0] spr_read_data_group_4; + assign spr_read_data_group_4 = spr_internal_read_dat[4]; + wire [31:0] spr_read_data_group_5; + assign spr_read_data_group_5 = spr_internal_read_dat[5]; + wire [31:0] spr_read_data_group_6; + assign spr_read_data_group_6 = spr_internal_read_dat[6]; + wire [31:0] spr_read_data_group_7; + assign spr_read_data_group_7 = spr_internal_read_dat[7]; + wire [31:0] spr_read_data_group_8; + assign spr_read_data_group_8 = spr_internal_read_dat[8]; + wire [31:0] spr_read_data_group_9; + assign spr_read_data_group_9 = spr_internal_read_dat[9]; + + + /* always single cycle access */ + assign spr_access_ack[`OR1K_SPR_DU_BASE] = spr_access[`OR1K_SPR_DU_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_DU_BASE] = + (spr_addr==`OR1K_SPR_DMR1_ADDR) ? + spr_dmr1 : + (spr_addr==`OR1K_SPR_DMR2_ADDR) ? + spr_dmr2 : + (spr_addr==`OR1K_SPR_DSR_ADDR) ? + spr_dsr : + (spr_addr==`OR1K_SPR_DRR_ADDR) ? + spr_drr : 0; + + /* Put the incoming stall signal through a register to detect FE */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_stall_r <= 0; + else + du_stall_r <= du_stall_i; + + /* DMR1 */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_dmr1 <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DMR1_ADDR) + spr_dmr1[23:0] <= spr_write_dat[23:0]; + + /* DMR2 */ + always @(posedge clk) + spr_dmr2 <= 0; + + /* DSR */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_dsr <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DSR_ADDR) + spr_dsr[13:0] <= spr_write_dat[13:0]; + + /* DRR */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_drr <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DRR_ADDR) + spr_drr[13:0] <= spr_write_dat[13:0]; + else if (stall_on_trap & padv_ctrl & except_trap_i) + spr_drr[`OR1K_SPR_DRR_TE] <= 1; + + end // block: du + else + begin : no_du + assign du_access = 0; + assign du_stall_o = 0; + assign du_ack_o = 0; + assign du_restart_o = 0; + assign du_restart_pc_o = 0; + assign stepping = 0; + assign du_npc_write = 0; + assign stepped_into_delay_slot = 0; + assign du_dat_o = 0; + assign du_restart_from_stall = 0; + assign spr_access_ack[`OR1K_SPR_DU_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_DU_BASE] = 0; + always @(posedge clk) + begin + spr_dmr1 <= 0; + spr_dmr2 <= 0; + spr_dsr <= 0; + spr_drr <= 0; + du_npc_written <= 0; + cpu_stall <= 0; + end + end + endgenerate + +// Controls to generate ACKs from units that are external to this module +generate +if (FEATURE_DMMU!="NONE") begin : dmmu_ctrl + assign spr_access_ack[`OR1K_SPR_DMMU_BASE] = spr_bus_ack_dmmu_i & + spr_access[`OR1K_SPR_DMMU_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] = + spr_bus_dat_dmmu_i & + {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_DMMU_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_DMMU_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] = 0; +end +endgenerate + +generate +if (FEATURE_IMMU!="NONE") begin : immu_ctrl + assign spr_access_ack[`OR1K_SPR_IMMU_BASE] = spr_bus_ack_immu_i & + spr_access[`OR1K_SPR_IMMU_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] = + spr_bus_dat_immu_i & + {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_IMMU_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_IMMU_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] = 0; +end +endgenerate + +generate +if (FEATURE_DATACACHE!="NONE") begin : datacache_ctrl + assign spr_access_ack[`OR1K_SPR_DC_BASE] = spr_bus_ack_dc_i & + spr_access[`OR1K_SPR_DC_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_DC_BASE] = + spr_bus_dat_dc_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_DC_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_DC_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_DC_BASE] = 0; +end +endgenerate + +generate +if (FEATURE_INSTRUCTIONCACHE!="NONE") begin : instructioncache_ctrl + assign spr_access_ack[`OR1K_SPR_IC_BASE] = spr_bus_ack_ic_i & + spr_access[`OR1K_SPR_IC_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_IC_BASE] = + spr_bus_dat_ic_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_IC_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_IC_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_IC_BASE] = 0; +end +endgenerate + +generate +if (FEATURE_MAC!="NONE") begin : mac_ctrl + assign spr_access_ack[`OR1K_SPR_MAC_BASE] = spr_bus_ack_mac_i & + spr_access[`OR1K_SPR_MAC_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_MAC_BASE] = + spr_bus_dat_mac_i & + {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_MAC_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_MAC_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_MAC_BASE] = 0; +end +endgenerate + +generate +if (FEATURE_PERFCOUNTERS!="NONE") begin : perfcounters_ctrl + assign spr_access_ack[`OR1K_SPR_PC_BASE] = spr_bus_ack_pcu_i & + spr_access[`OR1K_SPR_PC_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_PC_BASE] = + spr_bus_dat_pcu_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_PC_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_PC_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_PC_BASE] = 0; +end +endgenerate + +generate +if (FEATURE_PMU!="NONE") begin : pmu_ctrl + assign spr_access_ack[`OR1K_SPR_PM_BASE] = spr_bus_ack_pmu_i & + spr_access[`OR1K_SPR_PM_BASE]; + assign spr_internal_read_dat[`OR1K_SPR_PM_BASE] = + spr_bus_dat_pmu_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_PM_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_PM_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_PM_BASE] = 0; +end +endgenerate + +generate +if (FEATURE_FPU!="NONE") begin : fpu_ctrl + assign spr_access_ack[`OR1K_SPR_FPU_BASE] = spr_bus_ack_fpu_i; + assign spr_internal_read_dat[`OR1K_SPR_FPU_BASE] = + spr_bus_dat_fpu_i & + {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_FPU_BASE]}}; +end else begin + assign spr_access_ack[`OR1K_SPR_FPU_BASE] = 0; + assign spr_internal_read_dat[`OR1K_SPR_FPU_BASE] = 0; +end +endgenerate + +endmodule // mor1kx_ctrl_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_espresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_espresso.v new file mode 100644 index 0000000..c30d950 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_espresso.v @@ -0,0 +1,1449 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx espresso pipeline control unit + + inputs from execute stage + + generate pipeline controls + + manage SPRs + + issue addresses for exceptions to fetch stage + control branches going to fetch stage + + contains tick timer + + contains PIC logic + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_ctrl_espresso + (/*AUTOARG*/ + // Outputs + flag_o, spr_npc_o, spr_ppc_o, mfspr_dat_o, ctrl_mfspr_we_o, + carry_o, pipeline_flush_o, padv_fetch_o, padv_decode_o, + padv_execute_o, fetch_take_exception_branch_o, exception_taken_o, + execute_waiting_o, stepping_o, du_dat_o, du_ack_o, du_stall_o, + du_restart_pc_o, du_restart_o, spr_bus_addr_o, spr_bus_we_o, + spr_bus_stb_o, spr_bus_dat_o, spr_sr_o, ctrl_branch_target_o, + ctrl_branch_occur_o, rf_we_o, + // Inputs + clk, rst, ctrl_alu_result_i, ctrl_rfb_i, ctrl_flag_set_i, + ctrl_flag_clear_i, ctrl_opc_insn_i, pc_fetch_i, fetch_advancing_i, + except_ibus_err_i, except_illegal_i, except_syscall_i, + except_dbus_i, except_trap_i, except_align_i, next_fetch_done_i, + alu_valid_i, lsu_valid_i, op_lsu_load_i, op_lsu_store_i, op_jr_i, + op_jbr_i, irq_i, carry_set_i, carry_clear_i, overflow_set_i, + overflow_clear_i, du_addr_i, du_stb_i, du_dat_i, du_we_i, + du_stall_i, spr_bus_dat_dc_i, spr_bus_ack_dc_i, spr_bus_dat_ic_i, + spr_bus_ack_ic_i, spr_bus_dat_dmmu_i, spr_bus_ack_dmmu_i, + spr_bus_dat_immu_i, spr_bus_ack_immu_i, spr_bus_dat_mac_i, + spr_bus_ack_mac_i, spr_bus_dat_pmu_i, spr_bus_ack_pmu_i, + spr_bus_dat_pcu_i, spr_bus_ack_pcu_i, spr_bus_dat_fpu_i, + spr_bus_ack_fpu_i, multicore_coreid_i, rf_wb_i + ); + + parameter OPTION_OPERAND_WIDTH = 32; + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}; + + parameter FEATURE_SYSCALL = "ENABLED"; + parameter FEATURE_TRAP = "ENABLED"; + parameter FEATURE_RANGE = "ENABLED"; + + parameter FEATURE_DATACACHE = "NONE"; + parameter OPTION_DCACHE_BLOCK_WIDTH = 5; + parameter OPTION_DCACHE_SET_WIDTH = 9; + parameter OPTION_DCACHE_WAYS = 2; + parameter FEATURE_DMMU = "NONE"; + parameter FEATURE_INSTRUCTIONCACHE = "NONE"; + parameter OPTION_ICACHE_BLOCK_WIDTH = 5; + parameter OPTION_ICACHE_SET_WIDTH = 9; + parameter OPTION_ICACHE_WAYS = 2; + parameter FEATURE_IMMU = "NONE"; + parameter FEATURE_TIMER = "ENABLED"; + parameter FEATURE_DEBUGUNIT = "NONE"; + parameter FEATURE_PERFCOUNTERS = "NONE"; + parameter FEATURE_PMU = "NONE"; + parameter FEATURE_MAC = "NONE"; + parameter FEATURE_FPU = "NONE"; + + parameter FEATURE_MULTICORE = "NONE"; + + parameter FEATURE_PIC = "ENABLED"; + parameter OPTION_PIC_TRIGGER = "LEVEL"; + parameter OPTION_PIC_NMI_WIDTH = 0; + + parameter FEATURE_DSX = "NONE"; + parameter FEATURE_FASTCONTEXTS = "NONE"; + parameter FEATURE_OVERFLOW = "NONE"; + + parameter SPR_SR_WIDTH = 16; + parameter SPR_SR_RESET_VALUE = 16'h8001; + + input clk, rst; + + // ALU result - either jump target, SPR address + input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i; + + // Operand B from RF might be jump address, might be value for SPR + input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i; + + input ctrl_flag_set_i, ctrl_flag_clear_i; + output flag_o; + + output [OPTION_OPERAND_WIDTH-1:0] spr_npc_o; + output [OPTION_OPERAND_WIDTH-1:0] spr_ppc_o; + + input [`OR1K_OPCODE_WIDTH-1:0] ctrl_opc_insn_i; + + // PC of execute stage (NPC) + input [OPTION_OPERAND_WIDTH-1:0] pc_fetch_i; + input fetch_advancing_i; + + + // Exception inputs, registered on output of execute stage + input except_ibus_err_i, + except_illegal_i, + except_syscall_i, except_dbus_i, + except_trap_i, except_align_i; + + // Inputs from two units that can stall proceedings + input next_fetch_done_i; + + input alu_valid_i, lsu_valid_i; + + input op_lsu_load_i, op_lsu_store_i; + input op_jr_i, op_jbr_i; + + // External IRQ lines in + input [31:0] irq_i; + + // SPR data out + output [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o; + + // WE to RF for l.mfspr + output ctrl_mfspr_we_o; + + // Flag out to branch control, combinatorial + reg flag; + + // Arithmetic flags to and from ALU + output carry_o; + input carry_set_i; + input carry_clear_i; + input overflow_set_i; + input overflow_clear_i; + + // Branch indicator from control unit (l.rfe/exception) + wire ctrl_branch_exception; + // PC out to fetch stage for l.rfe, exceptions + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc; + + // Clear instructions from decode and fetch stage + output pipeline_flush_o; + + output padv_fetch_o; + output padv_decode_o; + output padv_execute_o; + + // This indicates to the fetch unit only that it should basically interrupt + // whatever it's doing and start fetching the exception + output fetch_take_exception_branch_o; + // This indicates to other parts of the CPU that we've handled an excption + // so can be used to clear exception indication registers + output exception_taken_o; + + output execute_waiting_o; + output stepping_o; + + // Debug bus + input [15:0] du_addr_i; + input du_stb_i; + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i; + input du_we_i; + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o; + output du_ack_o; + // Stall control from debug interface + input du_stall_i; + output du_stall_o; + output [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o; + output du_restart_o; + + // SPR accesses to external units (cache, mmu, etc.) + output [15:0] spr_bus_addr_o; + output spr_bus_we_o; + output spr_bus_stb_o; + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i; + input spr_bus_ack_dc_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i; + input spr_bus_ack_ic_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i; + input spr_bus_ack_dmmu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i; + input spr_bus_ack_immu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i; + input spr_bus_ack_mac_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i; + input spr_bus_ack_pmu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i; + input spr_bus_ack_pcu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i; + input spr_bus_ack_fpu_i; + output [15:0] spr_sr_o; + + // The multicore core identifier + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i; + + // Internal signals + reg [SPR_SR_WIDTH-1:0] spr_sr; + reg [SPR_SR_WIDTH-1:0] spr_esr; + reg [OPTION_OPERAND_WIDTH-1:0] spr_epcr; + reg [OPTION_OPERAND_WIDTH-1:0] spr_eear; + + // Programmable Interrupt Control SPRs + wire [31:0] spr_picmr; + wire [31:0] spr_picsr; + + // Tick Timer SPRs + wire [31:0] spr_ttmr; + wire [31:0] spr_ttcr; + + reg [OPTION_OPERAND_WIDTH-1:0] spr_ppc; + reg [OPTION_OPERAND_WIDTH-1:0] spr_npc; + reg execute_delay_slot; + reg delay_slot_rf_we_done; + + output [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_target_o; + + reg execute_go; + wire execute_done; + + reg execute_waiting_r; + + reg decode_execute_halt; + + reg exception_taken; + + reg [OPTION_OPERAND_WIDTH-1:0] last_branch_insn_pc; + reg [OPTION_OPERAND_WIDTH-1:0] last_branch_target_pc; + + reg take_exception; + reg exception_r; + + reg [OPTION_OPERAND_WIDTH-1:0] exception_pc_addr; + + reg waiting_for_fetch; + reg branched_and_waiting_for_fetch; + + reg doing_rfe_r; + wire doing_rfe; + wire deassert_doing_rfe; + + wire exception, exception_pending; + + wire execute_stage_exceptions; + wire decode_stage_exceptions; + + wire exception_re; + + wire except_ticktimer; + wire except_pic; + + wire except_ticktimer_nonsrmasked; + wire except_pic_nonsrmasked; + + wire except_range; + + wire [15:0] spr_addr; + + wire op_mtspr; + wire op_mfspr; + wire op_rfe; + + wire [OPTION_OPERAND_WIDTH-1:0] b; + + wire execute_waiting; + + wire execute_valid; + + wire deassert_decode_execute_halt; + + wire ctrl_branch_occur; + wire new_branch; + output ctrl_branch_occur_o; + output rf_we_o; + input rf_wb_i; + wire except_ibus_align; + wire fetch_advance; + wire rfete; + wire stall_on_trap; + + /* Debug SPRs */ + reg [31:0] spr_dmr1; + reg [31:0] spr_dmr2; + reg [31:0] spr_dsr; + reg [31:0] spr_drr; + + /* DU internal control signals */ + wire du_access; + wire cpu_stall; + wire du_restart_from_stall; + wire [1:0] pstep; + wire stepping; + wire stepped_into_delay_slot; + wire du_npc_write; + reg du_npc_written; + reg [OPTION_OPERAND_WIDTH-1:0] du_spr_npc; + + /* Wires for SPR management */ + wire spr_group_present; + wire [3:0] spr_group; + wire spr_we; + wire spr_read; + wire [OPTION_OPERAND_WIDTH-1:0] spr_write_dat; + wire [11:0] spr_access_ack; + wire [31:0] spr_internal_read_dat [0:12]; + wire spr_read_access; + wire spr_write_access; + wire spr_bus_access; + reg [OPTION_OPERAND_WIDTH-1:0] spr_sys_group_read; + + /* Wires from mor1kx_cfgrs module */ + wire [31:0] spr_vr; + wire [31:0] spr_vr2; + wire [31:0] spr_avr; + wire [31:0] spr_upr; + wire [31:0] spr_cpucfgr; + wire [31:0] spr_dmmucfgr; + wire [31:0] spr_immucfgr; + wire [31:0] spr_dccfgr; + wire [31:0] spr_iccfgr; + wire [31:0] spr_dcfgr; + wire [31:0] spr_pccfgr; + wire [31:0] spr_fpcsr = 0; + wire [31:0] spr_isr [0:7]; + + assign b = ctrl_rfb_i; + + assign ctrl_branch_exception = (exception_r | (op_rfe | doing_rfe)) & + !exception_taken; + assign exception_pending = (except_ibus_err_i | except_ibus_align | + except_illegal_i | except_syscall_i | + except_dbus_i | except_align_i | + except_ticktimer | except_range | + except_pic | except_trap_i ); + + assign exception = exception_pending; + + assign fetch_take_exception_branch_o = (take_exception | op_rfe) & + !stepping; + + assign execute_stage_exceptions = except_dbus_i | except_align_i | + except_range; + assign decode_stage_exceptions = except_trap_i | except_illegal_i; + + assign exception_re = exception & !exception_r & !exception_taken; + + assign deassert_decode_execute_halt = ctrl_branch_occur & + decode_execute_halt; + + assign ctrl_branch_except_pc = (op_rfe | doing_rfe) & !rfete ? spr_epcr : + exception_pc_addr; + + // Exceptions take precedence + assign ctrl_branch_occur = // instruction is branch, and flag is right + (op_jbr_i & + // is l.j or l.jal + (!(|ctrl_opc_insn_i[2:1]) | + // is l.bf/bnf and flag is right + (ctrl_opc_insn_i[2]==flag))) | + (op_jr_i & !(except_ibus_align)); + + assign ctrl_branch_occur_o = // Usual branch signaling + ((ctrl_branch_occur | ctrl_branch_exception) & + fetch_advance) | + // Need to tell the fetch stage to branch + // when it gets the next instruction because + // there was fetch stalls between the branch + // and the delay slot insn + (execute_delay_slot); + + assign ctrl_branch_target_o = ctrl_branch_exception ? + ctrl_branch_except_pc : + // jump or branch? + op_jbr_i ? ctrl_alu_result_i : + ctrl_rfb_i; + + // Do writeback when we register our output to the next stage, or if + // we're doing mfspr + assign rf_we_o = (execute_done & !delay_slot_rf_we_done) & + ((rf_wb_i & !op_mfspr + & !((op_lsu_load_i | op_lsu_store_i) & + except_dbus_i | except_align_i)) | + (op_mfspr)); + + assign except_range = (FEATURE_RANGE!="NONE") ? spr_sr[`OR1K_SPR_SR_OVE] && + (spr_sr[`OR1K_SPR_SR_OV] | overflow_set_i & + execute_done) & !doing_rfe : 0; + + // Check for unaligned jump address from register + assign except_ibus_align = op_jr_i & (|ctrl_rfb_i[1:0]); + + // Return from exception to exception (if pending tick or PIC ints) + assign rfete = (spr_esr[`OR1K_SPR_SR_IEE] & except_pic_nonsrmasked) | + (spr_esr[`OR1K_SPR_SR_TEE] & except_ticktimer_nonsrmasked); + + always @(posedge clk) + if (rst) + exception_pc_addr <= OPTION_RESET_PC; + else if (exception_re | (rfete & execute_done)) + casez( + {except_ibus_err_i, + except_illegal_i, + except_align_i, + except_ibus_align, + except_syscall_i, + except_trap_i, + except_dbus_i, + except_range, + except_pic_nonsrmasked, + except_ticktimer_nonsrmasked + } + ) + 10'b1?????????: + exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0}; + 10'b01????????: + exception_pc_addr <= {19'd0,`OR1K_ILLEGAL_VECTOR,8'd0}; + 10'b001???????, + 10'b0001??????: + exception_pc_addr <= {19'd0,`OR1K_ALIGN_VECTOR,8'd0}; + 10'b00001?????: + exception_pc_addr <= {19'd0,`OR1K_SYSCALL_VECTOR,8'd0}; + 10'b000001????: + exception_pc_addr <= {19'd0,`OR1K_TRAP_VECTOR,8'd0}; + 10'b0000001???: + exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0}; + 10'b00000001??: + exception_pc_addr <= {19'd0,`OR1K_RANGE_VECTOR,8'd0}; + 10'b000000001?: + exception_pc_addr <= {19'd0,`OR1K_INT_VECTOR,8'd0}; + //10'b0000000001: + default: + exception_pc_addr <= {19'd0,`OR1K_TT_VECTOR,8'd0}; + endcase // casex (... + + assign op_mtspr = ctrl_opc_insn_i==`OR1K_OPCODE_MTSPR; + assign op_mfspr = ctrl_opc_insn_i==`OR1K_OPCODE_MFSPR; + assign op_rfe = ctrl_opc_insn_i==`OR1K_OPCODE_RFE; + + reg waiting_for_except_fetch; + always @(posedge clk `OR_ASYNC_RST) + if (rst) + waiting_for_except_fetch <= 0; + else if (waiting_for_except_fetch & next_fetch_done_i) + waiting_for_except_fetch <= 0; + else if (fetch_take_exception_branch_o) + waiting_for_except_fetch <= 1; + + assign fetch_advance = (next_fetch_done_i | except_ibus_err_i) & + !execute_waiting & !cpu_stall & + (!stepping | + (stepping & pstep[0] & !next_fetch_done_i)); + + assign padv_fetch_o = fetch_advance & !exception_pending & !doing_rfe_r & + !cpu_stall; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + take_exception <= 0; + else + take_exception <= (exception_pending | exception_r | doing_rfe_r) & + (fetch_advance | + // Cause exception to always be 'taken' if stepping + (stepping & execute_done) + ) & + // Would like this as only a single pulse + !take_exception; + + reg padv_decode_r; + // Some bits of the pipeline (execute_alu for instance) require a falling + // edge of the decode signal to start work on multi-cycle ops. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + padv_decode_r <= 0; + else + padv_decode_r <= padv_fetch_o; + + assign padv_decode_o = padv_decode_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_go <= 0; + else + execute_go <= padv_fetch_o | execute_waiting | + (stepping & next_fetch_done_i); + + assign execute_done = execute_go & !execute_waiting; + + // ALU or LSU stall execution, nothing else can + assign execute_valid = !((op_lsu_load_i | op_lsu_store_i) & !lsu_valid_i | + !alu_valid_i); + + assign execute_waiting = !execute_valid & !waiting_for_fetch; + assign execute_waiting_o = execute_waiting; + + + assign padv_execute_o = execute_done; + + assign spr_addr = du_access ? du_addr_i : ctrl_alu_result_i[15:0]; + assign ctrl_mfspr_we_o = op_mfspr & execute_go; + + // Pipeline flush + assign pipeline_flush_o = (execute_done & op_rfe) | + (exception_re) | + cpu_stall; + + // Flag + always @(posedge clk `OR_ASYNC_RST) + if (rst) + flag <= 0; + else if (execute_done) + flag <= ctrl_flag_clear_i ? 0 : + ctrl_flag_set_i ? 1 : flag; + + assign flag_o = flag; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_waiting_r <= 0; + else if (!execute_waiting) + execute_waiting_r <= 0; + else if (execute_waiting) + execute_waiting_r <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_execute_halt <= 0; + else if (du_restart_from_stall) + decode_execute_halt <= 0; + else if (decode_execute_halt & deassert_decode_execute_halt) + decode_execute_halt <= 0; + else if ((op_rfe | exception) & !decode_execute_halt & !exception_taken) + decode_execute_halt <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + exception_r <= 0; + else if (exception_taken | du_restart_from_stall) + exception_r <= 0; + else if (exception & !exception_r) + exception_r <= 1; + + // Signal to indicate that the incoming exception or l.rfe has been taken + // and we're waiting for it to propagate through the pipeline. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + exception_taken <= 0; + else if (exception_taken) + exception_taken <= 0; + else if (exception_r & take_exception) + exception_taken <= 1; + + assign exception_taken_o = exception_taken; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + last_branch_insn_pc <= 0; + else if (fetch_advance & ctrl_branch_occur) + last_branch_insn_pc <= spr_ppc; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + last_branch_target_pc <= 0; + else if (execute_done & ctrl_branch_occur & stepping) + last_branch_target_pc <= ctrl_branch_target_o; + + // Used to gate execute stage's advance signal in the case where a LSU op has + // finished before the next instruction has been fetched. Typically this + // occurs when not using icache and doing lots of memory accesses. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + waiting_for_fetch <= 0; + else if (next_fetch_done_i) + waiting_for_fetch <= 0; + else if (!execute_waiting & execute_waiting_r & !next_fetch_done_i) + waiting_for_fetch <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + branched_and_waiting_for_fetch <= 0; + else if (exception_re) + branched_and_waiting_for_fetch <= 0; + else if (padv_fetch_o & ctrl_branch_occur_o) + branched_and_waiting_for_fetch <= 1; + else if (branched_and_waiting_for_fetch) + branched_and_waiting_for_fetch <= !next_fetch_done_i; + + + + assign doing_rfe = ((execute_done & op_rfe) | doing_rfe_r) & + !deassert_doing_rfe; + + // Basically, the fetch stage should always take the rfe immediately + assign deassert_doing_rfe = doing_rfe_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + doing_rfe_r <= 0; + else if (deassert_doing_rfe) + doing_rfe_r <= 0; + else if (execute_done) + doing_rfe_r <= op_rfe; + + assign spr_sr_o = spr_sr; + + // Supervision register + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_sr <= SPR_SR_RESET_VALUE; + else if (fetch_take_exception_branch_o) + begin + if (op_rfe & !rfete) + begin + spr_sr <= spr_esr; + end + else + begin + // Go into supervisor mode, disable interrupts, MMUs + spr_sr[`OR1K_SPR_SR_SM ] <= 1'b1; + if (FEATURE_TIMER!="NONE") + spr_sr[`OR1K_SPR_SR_TEE ] <= 1'b0; + if (FEATURE_PIC!="NONE") + spr_sr[`OR1K_SPR_SR_IEE ] <= 1'b0; + if (FEATURE_DMMU!="NONE") + spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0; + if (FEATURE_IMMU!="NONE") + spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0; + if (FEATURE_OVERFLOW!="NONE") + spr_sr[`OR1K_SPR_SR_OVE ] <= 1'b0; + end + end + else if (execute_done) + begin + spr_sr[`OR1K_SPR_SR_F ] <= ctrl_flag_set_i ? 1 : + ctrl_flag_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_F ]; + spr_sr[`OR1K_SPR_SR_CY ] <= carry_set_i ? 1 : + carry_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_CY ]; + + if (FEATURE_OVERFLOW!="NONE") + spr_sr[`OR1K_SPR_SR_OV ] <= overflow_set_i ? 1 : + overflow_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_OV ]; + + if ((spr_we & (spr_sr[`OR1K_SPR_SR_SM] | du_access)) && + spr_addr==`OR1K_SPR_SR_ADDR) + begin + spr_sr[`OR1K_SPR_SR_SM ] <= spr_write_dat[`OR1K_SPR_SR_SM ]; + + spr_sr[`OR1K_SPR_SR_F ] <= spr_write_dat[`OR1K_SPR_SR_F ]; + + if (FEATURE_TIMER!="NONE") + spr_sr[`OR1K_SPR_SR_TEE ] <= spr_write_dat[`OR1K_SPR_SR_TEE ]; + + if (FEATURE_PIC!="NONE") + spr_sr[`OR1K_SPR_SR_IEE ] <= spr_write_dat[`OR1K_SPR_SR_IEE ]; + + if (FEATURE_DATACACHE!="NONE") + spr_sr[`OR1K_SPR_SR_DCE ] <= spr_write_dat[`OR1K_SPR_SR_DCE ]; + + if (FEATURE_INSTRUCTIONCACHE!="NONE") + spr_sr[`OR1K_SPR_SR_ICE ] <= spr_write_dat[`OR1K_SPR_SR_ICE ]; + + if (FEATURE_DMMU!="NONE") + spr_sr[`OR1K_SPR_SR_DME ] <= spr_write_dat[`OR1K_SPR_SR_DME ]; + + if (FEATURE_IMMU!="NONE") + spr_sr[`OR1K_SPR_SR_IME ] <= spr_write_dat[`OR1K_SPR_SR_IME ]; + + if (FEATURE_FASTCONTEXTS!="NONE") + spr_sr[`OR1K_SPR_SR_CE ] <= spr_write_dat[`OR1K_SPR_SR_CE ]; + + spr_sr[`OR1K_SPR_SR_CY ] <= spr_write_dat[`OR1K_SPR_SR_CY ]; + + if (FEATURE_OVERFLOW!="NONE") begin + spr_sr[`OR1K_SPR_SR_OV ] <= spr_write_dat[`OR1K_SPR_SR_OV ]; + spr_sr[`OR1K_SPR_SR_OVE ] <= spr_write_dat[`OR1K_SPR_SR_OVE ]; + end + + if (FEATURE_DSX!="NONE") + spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ]; + + spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ]; + + end // if ((spr_we & (spr_sr[`OR1K_SPR_SR_SM] | du_access)) &&... + + /* Need to check for DSX being set on exception entry on execute_done + as the delay slot information is gone after it goes high */ + if (FEATURE_DSX!="NONE") + if (exception_r || exception_re) + spr_sr[`OR1K_SPR_SR_DSX ] <= execute_delay_slot; + + end // if (execute_done) + + assign carry_o = spr_sr[`OR1K_SPR_SR_CY]; + + // Exception SR + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_esr <= SPR_SR_RESET_VALUE; + else if (exception_re) + begin + spr_esr <= spr_sr; + /* + A bit odd, but if we had a l.sf instruction on an exception rising + edge, EPCR will point to the insn past the l.sf but the flag will + not have been saved to the SR properly. So we must put it in here + so it can be restored correctly. + Ditto for the other flags which may have been changed in a similar + fashion. + */ + if (execute_done) + begin + if (ctrl_flag_set_i) + spr_esr[`OR1K_SPR_SR_F ] <= 1'b1; + else if (ctrl_flag_clear_i) + spr_esr[`OR1K_SPR_SR_F ] <= 1'b0; + if (FEATURE_OVERFLOW!="NONE") + begin + if (overflow_set_i) + spr_esr[`OR1K_SPR_SR_OV ] <= 1'b1; + else if (overflow_clear_i) + spr_esr[`OR1K_SPR_SR_OV ] <= 1'b0; + end + if (carry_set_i) + spr_esr[`OR1K_SPR_SR_CY ] <= 1'b1; + else if (carry_clear_i) + spr_esr[`OR1K_SPR_SR_CY ] <= 1'b0; + end + end + else if (spr_we & spr_addr==`OR1K_SPR_ESR0_ADDR) + spr_esr <= spr_write_dat[SPR_SR_WIDTH-1:0]; + + // Exception PC + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_epcr <= OPTION_RESET_PC; + else if (exception_re & !(rfete & (op_rfe | deassert_doing_rfe))) + begin + if (except_ibus_err_i) + spr_epcr <= spr_ppc-4; + else if (except_syscall_i) + // EPCR after syscall is address of next not executed insn. + spr_epcr <= spr_npc; + else if (except_ticktimer | except_pic) + spr_epcr <= branched_and_waiting_for_fetch ? spr_npc : + execute_delay_slot ? spr_ppc-4 : spr_ppc+4; + else if (execute_stage_exceptions | + // Don't update EPCR on software breakpoint + (decode_stage_exceptions & !(stall_on_trap & except_trap_i))) + spr_epcr <= execute_delay_slot ? spr_ppc-4 : spr_ppc; + else if (!(stall_on_trap & except_trap_i)) + spr_epcr <= execute_delay_slot ? spr_ppc-4 : spr_ppc; + end + else if (spr_we && spr_addr==`OR1K_SPR_EPCR0_ADDR) + spr_epcr <= spr_write_dat; + + // Exception Effective Address + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}}; + else if (exception_re) + begin + if (except_ibus_err_i) + spr_eear <= pc_fetch_i; + else + spr_eear <= ctrl_alu_result_i; + end + + // Next PC (NPC) + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_npc <= OPTION_RESET_PC; + else if (deassert_doing_rfe) + spr_npc <= rfete ? exception_pc_addr : spr_epcr; + else if (du_restart_o) + spr_npc <= du_restart_pc_o; + else if (stepping & next_fetch_done_i) + spr_npc <= execute_delay_slot ? last_branch_target_pc : pc_fetch_i; + else if (stepping & exception_r) + spr_npc <= exception_pc_addr; + else if (fetch_advance) + // PC we're now executing + spr_npc <= fetch_take_exception_branch_o ? exception_pc_addr : + ctrl_branch_occur ? ctrl_branch_target_o : pc_fetch_i; + + // Previous PC (PPC) + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_ppc <= OPTION_RESET_PC; + else if (padv_fetch_o | (stepping & next_fetch_done_i)) + spr_ppc <= spr_npc; // PC we've got in execute stage (about to finish) + + assign spr_npc_o = spr_npc; + assign spr_ppc_o = spr_ppc; + + // Remember when we're in a delay slot in execute stage. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_delay_slot <= 0; + else if (execute_done) + execute_delay_slot <= execute_delay_slot ? 0 : + ctrl_branch_occur; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + delay_slot_rf_we_done <= 0; + else + delay_slot_rf_we_done <= rf_we_o & execute_delay_slot; + + mor1kx_cfgrs + #(.FEATURE_PIC (FEATURE_PIC), + .FEATURE_TIMER (FEATURE_TIMER), + .OPTION_PIC_TRIGGER (OPTION_PIC_TRIGGER), + .FEATURE_DSX (FEATURE_DSX), + .FEATURE_FASTCONTEXTS (FEATURE_FASTCONTEXTS), + .FEATURE_OVERFLOW (FEATURE_OVERFLOW), + .FEATURE_DATACACHE (FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH (OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH (OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS (OPTION_DCACHE_WAYS), + .FEATURE_DMMU (FEATURE_DMMU), + .FEATURE_INSTRUCTIONCACHE (FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH (OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH (OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS (OPTION_ICACHE_WAYS), + .FEATURE_IMMU (FEATURE_IMMU), + .FEATURE_DEBUGUNIT (FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS (FEATURE_PERFCOUNTERS), + .FEATURE_MAC (FEATURE_MAC), + .FEATURE_SYSCALL (FEATURE_SYSCALL), + .FEATURE_TRAP (FEATURE_TRAP), + .FEATURE_RANGE (FEATURE_RANGE), + .FEATURE_DELAYSLOT ("ENABLED") + ) + mor1kx_cfgrs + (/*AUTOINST*/ + // Outputs + .spr_vr (spr_vr[31:0]), + .spr_vr2 (spr_vr2[31:0]), + .spr_upr (spr_upr[31:0]), + .spr_cpucfgr (spr_cpucfgr[31:0]), + .spr_dmmucfgr (spr_dmmucfgr[31:0]), + .spr_immucfgr (spr_immucfgr[31:0]), + .spr_dccfgr (spr_dccfgr[31:0]), + .spr_iccfgr (spr_iccfgr[31:0]), + .spr_dcfgr (spr_dcfgr[31:0]), + .spr_pccfgr (spr_pccfgr[31:0]), + .spr_avr (spr_avr[31:0])); + + /* Implementation-specific registers */ + assign spr_isr[0] = 0; + assign spr_isr[1] = 0; + assign spr_isr[2] = 0; + assign spr_isr[3] = 0; + assign spr_isr[4] = 0; + assign spr_isr[5] = 0; + assign spr_isr[6] = 0; + assign spr_isr[7] = 0; + + // System group (0) SPR data out + always @* + case(spr_addr) + `OR1K_SPR_VR_ADDR: + spr_sys_group_read = spr_vr; + `OR1K_SPR_VR2_ADDR: + spr_sys_group_read = {spr_vr2[31:8], `MOR1KX_PIPEID_ESPRESSO}; + `OR1K_SPR_AVR_ADDR: + spr_sys_group_read = spr_avr; + `OR1K_SPR_UPR_ADDR: + spr_sys_group_read = spr_upr; + `OR1K_SPR_CPUCFGR_ADDR: + spr_sys_group_read = spr_cpucfgr; + `OR1K_SPR_DMMUCFGR_ADDR: + spr_sys_group_read = spr_dmmucfgr; + `OR1K_SPR_IMMUCFGR_ADDR: + spr_sys_group_read = spr_immucfgr; + `OR1K_SPR_DCCFGR_ADDR: + spr_sys_group_read = spr_dccfgr; + `OR1K_SPR_ICCFGR_ADDR: + spr_sys_group_read = spr_iccfgr; + `OR1K_SPR_DCFGR_ADDR: + spr_sys_group_read = spr_dcfgr; + `OR1K_SPR_PCCFGR_ADDR: + spr_sys_group_read = spr_pccfgr; + `OR1K_SPR_NPC_ADDR: + spr_sys_group_read = spr_npc; + `OR1K_SPR_SR_ADDR: + spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}}, + spr_sr}; + + `OR1K_SPR_PPC_ADDR: + spr_sys_group_read = spr_ppc; + `OR1K_SPR_FPCSR_ADDR: + spr_sys_group_read = spr_fpcsr; + `OR1K_SPR_EPCR0_ADDR: + spr_sys_group_read = spr_epcr; + `OR1K_SPR_EEAR0_ADDR: + spr_sys_group_read = spr_eear; + `OR1K_SPR_ESR0_ADDR: + spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}}, + spr_esr}; + `OR1K_SPR_ISR0_ADDR: + spr_sys_group_read = spr_isr[0]; + `OR1K_SPR_ISR0_ADDR +1: + spr_sys_group_read = spr_isr[1]; + `OR1K_SPR_ISR0_ADDR +2: + spr_sys_group_read = spr_isr[2]; + `OR1K_SPR_ISR0_ADDR +3: + spr_sys_group_read = spr_isr[3]; + `OR1K_SPR_ISR0_ADDR +4: + spr_sys_group_read = spr_isr[4]; + `OR1K_SPR_ISR0_ADDR +5: + spr_sys_group_read = spr_isr[5]; + `OR1K_SPR_ISR0_ADDR +6: + spr_sys_group_read = spr_isr[6]; + `OR1K_SPR_ISR0_ADDR +7: + spr_sys_group_read = spr_isr[7]; + + `OR1K_SPR_COREID_ADDR: + // If the multicore feature is activated this address returns the + // core identifier, 0 otherwise + spr_sys_group_read = (FEATURE_MULTICORE != "NONE") ? + multicore_coreid_i : 0; + + default: begin + /* GPR read */ + if (spr_addr >= `OR1K_SPR_GPR0_ADDR && + spr_addr <= (`OR1K_SPR_GPR0_ADDR + 32)) + spr_sys_group_read = b; /* Register file */ + else + /* Invalid address - read as zero*/ + spr_sys_group_read = 0; + end + endcase // case (spr_addr) + + /* System group read data MUX in */ + assign spr_internal_read_dat[0] = spr_sys_group_read; + /* System group ack generation */ + /* TODO - might be delay for register file reads! */ + assign spr_access_ack[0] = 1; + + + + /* Generate data to the register file for mfspr operations */ + assign mfspr_dat_o = spr_internal_read_dat[spr_addr[14:11]]; + + // PIC SPR control + generate + if (FEATURE_PIC !="NONE") begin : pic + + /* mor1kx_pic AUTO_TEMPLATE ( + .spr_picsr_o (spr_picsr), + .spr_picmr_o (spr_picmr), + .spr_bus_ack (spr_access_ack[9]), + .spr_dat_o (spr_internal_read_dat[9]), + // Inputs + .spr_we_i (spr_we), + .spr_addr_i (spr_addr), + .spr_dat_i (spr_write_dat), + );*/ + mor1kx_pic + #( + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH) + ) + mor1kx_pic + (/*AUTOINST*/ + // Outputs + .spr_picmr_o (spr_picmr), // Templated + .spr_picsr_o (spr_picsr), // Templated + .spr_bus_ack (spr_access_ack[9]), // Templated + .spr_dat_o (spr_internal_read_dat[9]), // Templated + // Inputs + .clk (clk), + .rst (rst), + .irq_i (irq_i[31:0]), + .spr_we_i (spr_we), // Templated + .spr_addr_i (spr_addr), // Templated + .spr_dat_i (spr_write_dat)); // Templated + + assign except_pic_nonsrmasked = (|spr_picsr) & + !op_mtspr & + // Stops back-to-back branch addresses going to + // fetch stage + !ctrl_branch_occur & + // Stops issues with PC when branching + !execute_delay_slot; + + assign except_pic = spr_sr[`OR1K_SPR_SR_IEE] & except_pic_nonsrmasked & + !doing_rfe; + end + else begin + assign except_pic_nonsrmasked = 0; + assign except_pic = 0; + assign spr_picsr = 0; + assign spr_picmr = 0; + assign spr_access_ack[9] = 0; + assign spr_internal_read_dat[9] = 0; + end // else: !if(FEATURE_PIC !="NONE") + endgenerate + + + generate + if (FEATURE_TIMER!="NONE") begin : tt + + /* mor1kx_ticktimer AUTO_TEMPLATE ( + .spr_ttmr_o (spr_ttmr), + .spr_ttcr_o (spr_ttcr), + .spr_bus_ack (spr_access_ack[10]), + .spr_dat_o (spr_internal_read_dat[10]), + // Inputs + .spr_we_i (spr_we), + .spr_addr_i (spr_addr), + .spr_dat_i (spr_write_dat), + );*/ + mor1kx_ticktimer mor1kx_ticktimer + (/*AUTOINST*/ + // Outputs + .spr_ttmr_o (spr_ttmr), // Templated + .spr_ttcr_o (spr_ttcr), // Templated + .spr_bus_ack (spr_access_ack[10]), // Templated + .spr_dat_o (spr_internal_read_dat[10]), // Templated + // Inputs + .clk (clk), + .rst (rst), + .spr_we_i (spr_we), // Templated + .spr_addr_i (spr_addr), // Templated + .spr_dat_i (spr_write_dat)); // Templated + + assign except_ticktimer_nonsrmasked = spr_ttmr[28] & + (!op_mtspr & !(spr_esr[`OR1K_SPR_SR_TEE] & execute_done)) & + // Stops back-to-back branch addresses to + // fetch stage. + !ctrl_branch_occur & + // Stops issues with PC when branching + !execute_delay_slot; + + assign except_ticktimer = except_ticktimer_nonsrmasked & + spr_sr[`OR1K_SPR_SR_TEE] & !doing_rfe; + end // if (FEATURE_TIMER!="NONE") + else begin + assign except_ticktimer_nonsrmasked = 0; + assign except_ticktimer = 0; + assign spr_ttmr = 0; + assign spr_ttcr = 0; + assign spr_access_ack[10] = 0; + assign spr_internal_read_dat[10] = 0; + end // else: !if(FEATURE_TIMER!="NONE") + endgenerate + + /* SPR access control - allow accesses from either the instructions or from + the debug interface */ + assign spr_read_access = (op_mfspr | (du_access & !du_we_i)); + assign spr_write_access = ((execute_done & op_mtspr) | (du_access & du_we_i)); + + assign spr_write_dat = du_access ? du_dat_i : b; + assign spr_we = spr_write_access & spr_group_present; + assign spr_read = spr_read_access & spr_group_present; + + /* A bus out to other units that live outside of the control unit */ + assign spr_bus_addr_o = spr_addr; + assign spr_bus_we_o = spr_write_access & spr_group_present & spr_bus_access; + assign spr_bus_stb_o = (spr_read_access | spr_write_access) & + spr_group_present & spr_bus_access; + assign spr_bus_dat_o = spr_write_dat; + + /* Is the SPR in the design? */ + assign spr_group_present = (// System group + (spr_addr[15:11]==5'h00) || + // DMMU + (spr_addr[15:11]==5'h01 && + FEATURE_DMMU!="NONE") || + // IMMU + (spr_addr[15:11]==5'h02 && + FEATURE_IMMU!="NONE") || + // Data cache + (spr_addr[15:11]==5'h03 && + FEATURE_DATACACHE!="NONE") || + // Instruction cache + (spr_addr[15:11]==5'h04 && + FEATURE_INSTRUCTIONCACHE!= "NONE") || + // MAC unit + (spr_addr[15:11]==5'h05 && + FEATURE_MAC!="NONE") || + // Debug unit + (spr_addr[15:11]==5'h06 && + FEATURE_DEBUGUNIT!="NONE") || + // Performance counters + (spr_addr[15:11]==5'h07 && + FEATURE_PERFCOUNTERS!="NONE") || + // Power Management + (spr_addr[15:11]==5'h08 && + FEATURE_PMU!="NONE") || + // PIC + (spr_addr[15:11]==5'h09 && + FEATURE_PIC!="NONE") || + // Tick timer + (spr_addr[15:11]==5'h0a && + FEATURE_TIMER!="NONE") || + // FPU + (spr_addr[15:11]==5'h0b && + FEATURE_FPU!="NONE") + ); + + /* Generate a SPR group signal - generate invalid if the group is not + present in the design */ + assign spr_group = (spr_group_present) ? spr_addr[14:11] : 4'd12; + + /* Default group when a selected one is not present - it reads as zero */ + assign spr_internal_read_dat[12] = 0; + + /* Is a SPR bus access needed, or is the requested SPR in this file? */ + assign spr_bus_access = /* Any of the units we don't have in this file */ + /* System group */ + !(spr_addr[15:11]==5'h00 || + /* Debug Group */ + spr_addr[15:11]==5'h06 || + /* PIC Group */ + spr_addr[15:11]==5'h09 || + /* Tick Group */ + spr_addr[15:11]==5'h0a); + + assign stepping_o = stepping; + + generate + if (FEATURE_DEBUGUNIT!="NONE") begin : du + + reg [OPTION_OPERAND_WIDTH-1:0] du_read_dat; + + reg du_ack; + reg du_stall_r; + reg [1:0] pstep_r; + reg [1:0] branch_step; + reg stepped_into_exception; + reg stepped_into_rfe; + + assign du_access = du_stb_i; + + // Generate ack back to the debug interface bus + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_ack <= 0; + else if (du_ack) + du_ack <= 0; + else if (du_stb_i) begin + if (!spr_group_present) + /* Unit doesn't exist, ACK to clear the access, nothing done */ + du_ack <= 1; + else if (spr_access_ack[spr_group]) + /* actual access occurred */ + du_ack <= 1; + end + + assign du_ack_o = du_ack; + + /* Data back to the debug bus */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_read_dat <= 0; + else if (spr_access_ack[spr_group]) begin + du_read_dat <= spr_internal_read_dat[spr_group]; + end + + assign du_dat_o = du_read_dat; + /* TODO: check into only letting stall go high when we've gracefully + completed the instruction currently in the ctrl stage. + Why? Potentially an instruction like l.mfspr from an external unit + hasn't completed fully, gets interrupted, and it's assumed it's + completed, but actually hasn't. */ + assign cpu_stall = du_stall_i | du_restart_from_stall; + + /* goes out to the debug interface and comes back 1 cycle later + via du_stall_i */ + assign du_stall_o = (stepping & execute_done)| + (stall_on_trap & execute_done & except_trap_i); + + /* Pulse to indicate we're restarting after a stall */ + assign du_restart_from_stall = du_stall_r & !du_stall_i; + + /* NPC debug control logic */ + assign du_npc_write = (du_we_i && du_addr_i==`OR1K_SPR_NPC_ADDR && + du_ack_o); + + /* Pick the traps-cause-stall bit out of the DSR */ + assign stall_on_trap = spr_dsr[`OR1K_SPR_DSR_TE]; + + /* record if NPC was written while we were stalled. + If so, we will use this value for restarting */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_npc_written <= 0; + else if (du_restart_from_stall) + du_npc_written <= 0; + else if (du_npc_write) + du_npc_written <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_spr_npc <= 0; + else if (du_npc_write) + du_spr_npc <= du_dat_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + stepped_into_exception <= 0; + else if (du_restart_from_stall) + stepped_into_exception <= 0; + else if (stepping & execute_done) + stepped_into_exception <= exception; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + stepped_into_rfe <= 0; + else if (du_restart_from_stall) + stepped_into_rfe <= 0; + else if (stepping & execute_done) + stepped_into_rfe <= op_rfe; + + assign du_restart_pc_o = du_npc_written ? du_spr_npc : + stepped_into_rfe ? spr_epcr : + stepped_into_delay_slot ? + last_branch_target_pc : spr_npc; + + assign du_restart_o = du_restart_from_stall; + + /* Indicate when we're stepping */ + assign stepping = spr_dmr1[`OR1K_SPR_DMR1_ST] & + spr_dsr[`OR1K_SPR_DSR_TE]; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + pstep_r <= 0; + else if (du_restart_from_stall & stepping) + pstep_r <= 2'd1; + else if ((pstep[0] & next_fetch_done_i) | + /* decode is always single cycle */ + (pstep[1] & execute_done)) + pstep_r <= {pstep_r[0],1'b0}; + + assign pstep = pstep_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + branch_step <= 0; + else if (stepping & pstep[1]) + branch_step <= {branch_step[0], ctrl_branch_occur}; + else if (!stepping & execute_done) + branch_step <= {branch_step[0], execute_delay_slot}; + + assign stepped_into_delay_slot = branch_step[1]; + + /* Signals for waveform debuging */ + wire [31:0] spr_read_data_group_0; + assign spr_read_data_group_0 = spr_internal_read_dat[0]; + wire [31:0] spr_read_data_group_1; + assign spr_read_data_group_1 = spr_internal_read_dat[1]; + wire [31:0] spr_read_data_group_2; + assign spr_read_data_group_2 = spr_internal_read_dat[2]; + wire [31:0] spr_read_data_group_3; + assign spr_read_data_group_3 = spr_internal_read_dat[3]; + wire [31:0] spr_read_data_group_4; + assign spr_read_data_group_4 = spr_internal_read_dat[4]; + wire [31:0] spr_read_data_group_5; + assign spr_read_data_group_5 = spr_internal_read_dat[5]; + wire [31:0] spr_read_data_group_6; + assign spr_read_data_group_6 = spr_internal_read_dat[6]; + wire [31:0] spr_read_data_group_7; + assign spr_read_data_group_7 = spr_internal_read_dat[7]; + wire [31:0] spr_read_data_group_8; + assign spr_read_data_group_8 = spr_internal_read_dat[8]; + wire [31:0] spr_read_data_group_9; + assign spr_read_data_group_9 = spr_internal_read_dat[9]; + + + /* always single cycle access */ + assign spr_access_ack[6] = 1; + assign spr_internal_read_dat[6] = (spr_addr==`OR1K_SPR_DMR1_ADDR) ? + spr_dmr1 : + (spr_addr==`OR1K_SPR_DMR2_ADDR) ? + spr_dmr2 : + (spr_addr==`OR1K_SPR_DSR_ADDR) ? + spr_dsr : + (spr_addr==`OR1K_SPR_DRR_ADDR) ? + spr_drr : 0; + + /* Put the incoming stall signal through a register to detect FE */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_stall_r <= 0; + else + du_stall_r <= du_stall_i; + + /* DMR1 */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_dmr1 <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DMR1_ADDR) + spr_dmr1[23:0] <= spr_write_dat[23:0]; + + /* DMR2 */ + always @(posedge clk) + spr_dmr2 <= 0; + + /* DSR */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_dsr <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DSR_ADDR) + spr_dsr[13:0] <= spr_write_dat[13:0]; + + /* DRR */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_drr <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DRR_ADDR) + spr_drr[13:0] <= spr_write_dat[13:0]; + else if (stall_on_trap & execute_done & except_trap_i) + spr_drr[`OR1K_SPR_DRR_TE] <= 1; + + end // block: du + else + begin : no_du + assign du_access = 0; + assign cpu_stall = 0; + assign du_stall_o = 0; + assign du_ack_o = 0; + assign du_restart_o = 0; + assign du_restart_pc_o = 0; + assign stepping = 0; + assign du_npc_write = 0; + assign stepped_into_delay_slot = 0; + assign du_dat_o = 0; + assign du_restart_from_stall = 0; + assign spr_access_ack[6] = 0; + + always @(posedge clk) + begin + spr_dmr1 <= 0; + spr_dmr2 <= 0; + spr_dsr <= 0; + spr_drr <= 0; + du_npc_written <= 0; + end + end + endgenerate + + /* Controls to generate ACKs from units that are external to this module */ + generate + if (FEATURE_DMMU!="NONE") begin : dmmu_ctrl + assign spr_access_ack[1] = spr_bus_ack_dmmu_i; + assign spr_internal_read_dat[1] = spr_bus_dat_dmmu_i; + end + else begin + assign spr_access_ack[1] = 0; + assign spr_internal_read_dat[1] = 0; + end + endgenerate + + generate + if (FEATURE_IMMU!="NONE") begin : immu_ctrl + assign spr_access_ack[2] = spr_bus_ack_immu_i; + assign spr_internal_read_dat[2] = spr_bus_dat_immu_i; + end + else begin + assign spr_access_ack[2] = 0; + assign spr_internal_read_dat[2] = 0; + end + endgenerate + + generate + if (FEATURE_DATACACHE!="NONE") begin : datacache_ctrl + assign spr_access_ack[3] = spr_bus_ack_dc_i; + assign spr_internal_read_dat[3] = spr_bus_dat_dc_i; + end + else begin + assign spr_access_ack[3] = 0; + assign spr_internal_read_dat[3] = 0; + end + endgenerate + + generate + if (FEATURE_INSTRUCTIONCACHE!="NONE") begin : instructioncache_ctrl + assign spr_access_ack[4] = spr_bus_ack_ic_i; + assign spr_internal_read_dat[4] = spr_bus_dat_ic_i; + end + else begin + assign spr_access_ack[4] = 0; + assign spr_internal_read_dat[4] = 0; + end + endgenerate + + generate + if (FEATURE_MAC!="NONE") begin : mac_ctrl + assign spr_access_ack[5] = spr_bus_ack_mac_i; + assign spr_internal_read_dat[5] = spr_bus_dat_mac_i; + end + else begin + assign spr_access_ack[5] = 0; + assign spr_internal_read_dat[5] = 0; + end + endgenerate + + generate + if (FEATURE_PERFCOUNTERS!="NONE") begin : perfcounters_ctrl + assign spr_access_ack[7] = spr_bus_ack_pcu_i; + assign spr_internal_read_dat[7] = spr_bus_dat_pcu_i; + end + else begin + assign spr_access_ack[7] = 0; + assign spr_internal_read_dat[7] = 0; + end + endgenerate + + generate + if (FEATURE_PMU!="NONE") begin : pmu_ctrl + assign spr_access_ack[8] = spr_bus_ack_pmu_i; + assign spr_internal_read_dat[8] = spr_bus_dat_pcu_i; + end + else begin + assign spr_access_ack[8] = 0; + assign spr_internal_read_dat[8] = 0; + end + endgenerate + + generate + if (FEATURE_FPU!="NONE") begin : fpu_ctrl + assign spr_access_ack[11] = spr_bus_ack_fpu_i; + assign spr_internal_read_dat[11] = spr_bus_dat_fpu_i; + end + else begin + assign spr_access_ack[11] = 0; + assign spr_internal_read_dat[11] = 0; + end + endgenerate + +endmodule // mor1kx_ctrl_espresso diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_prontoespresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_prontoespresso.v new file mode 100644 index 0000000..4951d7a --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_prontoespresso.v @@ -0,0 +1,1490 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx pronto espresso pipeline control unit + + inputs from execute stage + + generate pipeline controls + + manage SPRs + + issue addresses for exceptions to fetch stage + control branches going to fetch stage + + contains tick timer + + contains PIC logic + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_ctrl_prontoespresso + (/*AUTOARG*/ + // Outputs + spr_npc_o, spr_ppc_o, link_addr_o, mfspr_dat_o, ctrl_mfspr_we_o, + flag_o, carry_o, pipeline_flush_o, padv_fetch_o, padv_decode_o, + padv_execute_o, fetch_take_exception_branch_o, exception_taken_o, + execute_waiting_o, stepping_o, du_dat_o, du_ack_o, du_stall_o, + du_restart_pc_o, du_restart_o, spr_bus_addr_o, spr_bus_we_o, + spr_bus_stb_o, spr_bus_dat_o, spr_sr_o, ctrl_branch_target_o, + ctrl_insn_done_o, ctrl_branch_occur_o, rf_we_o, + // Inputs + clk, rst, ctrl_alu_result_i, ctrl_rfb_i, ctrl_flag_set_i, + ctrl_flag_clear_i, ctrl_opc_insn_i, fetch_ppc_i, pc_fetch_next_i, + fetch_sleep_i, except_ibus_err_i, except_illegal_i, + except_syscall_i, except_dbus_i, except_trap_i, except_align_i, + fetch_ready_i, fetch_quick_branch_i, alu_valid_i, lsu_valid_i, + op_lsu_load_i, op_lsu_store_i, op_jr_i, op_jbr_i, irq_i, + carry_set_i, carry_clear_i, overflow_set_i, overflow_clear_i, + du_addr_i, du_stb_i, du_dat_i, du_we_i, du_stall_i, + spr_bus_dat_dc_i, spr_bus_ack_dc_i, spr_bus_dat_ic_i, + spr_bus_ack_ic_i, spr_bus_dat_dmmu_i, spr_bus_ack_dmmu_i, + spr_bus_dat_immu_i, spr_bus_ack_immu_i, spr_bus_dat_mac_i, + spr_bus_ack_mac_i, spr_bus_dat_pmu_i, spr_bus_ack_pmu_i, + spr_bus_dat_pcu_i, spr_bus_ack_pcu_i, spr_bus_dat_fpu_i, + spr_bus_ack_fpu_i, multicore_coreid_i, rf_wb_i + ); + + parameter OPTION_OPERAND_WIDTH = 32; + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}; + + parameter FEATURE_SYSCALL = "ENABLED"; + parameter FEATURE_TRAP = "ENABLED"; + parameter FEATURE_RANGE = "ENABLED"; + + parameter FEATURE_DATACACHE = "NONE"; + parameter OPTION_DCACHE_BLOCK_WIDTH = 5; + parameter OPTION_DCACHE_SET_WIDTH = 9; + parameter OPTION_DCACHE_WAYS = 2; + parameter FEATURE_DMMU = "NONE"; + parameter FEATURE_INSTRUCTIONCACHE = "NONE"; + parameter OPTION_ICACHE_BLOCK_WIDTH = 5; + parameter OPTION_ICACHE_SET_WIDTH = 9; + parameter OPTION_ICACHE_WAYS = 2; + parameter FEATURE_IMMU = "NONE"; + parameter FEATURE_TIMER = "ENABLED"; + parameter FEATURE_DEBUGUNIT = "NONE"; + parameter FEATURE_PERFCOUNTERS = "NONE"; + parameter FEATURE_PMU = "NONE"; + parameter FEATURE_MAC = "NONE"; + parameter FEATURE_FPU = "NONE"; + + parameter FEATURE_MULTICORE = "NONE"; + + parameter FEATURE_PIC = "ENABLED"; + parameter OPTION_PIC_TRIGGER = "LEVEL"; + parameter OPTION_PIC_NMI_WIDTH = 0; + + parameter FEATURE_DSX = "NONE"; + parameter FEATURE_FASTCONTEXTS = "NONE"; + parameter FEATURE_OVERFLOW = "NONE"; + + parameter SPR_SR_WIDTH = 16; + parameter SPR_SR_RESET_VALUE = 16'h8001; + + parameter FEATURE_INBUILT_CHECKERS = "ENABLED"; + + input clk, rst; + + // ALU result - either jump target, SPR address + input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i; + + // Operand B from RF might be jump address, might be value for SPR + input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i; + + input ctrl_flag_set_i, ctrl_flag_clear_i; + + output [OPTION_OPERAND_WIDTH-1:0] spr_npc_o; + output [OPTION_OPERAND_WIDTH-1:0] spr_ppc_o; + + // Link address, to writeback stage + output [OPTION_OPERAND_WIDTH-1:0] link_addr_o; + + input [`OR1K_OPCODE_WIDTH-1:0] ctrl_opc_insn_i; + + // PCs from the fetch stage + // PC of the instruction from fetch stage + input [OPTION_OPERAND_WIDTH-1:0] fetch_ppc_i; + // Next PC we're going to deliver + input [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_i; + + // Input from fetch stage, indicating it's "sleeping", or not fetching + // anymore. + input fetch_sleep_i; + + + // Exception inputs, registered on output of execute stage + input except_ibus_err_i, + except_illegal_i, + except_syscall_i, except_dbus_i, + except_trap_i, except_align_i; + + // Inputs from two units that can stall proceedings + input fetch_ready_i; + input fetch_quick_branch_i; + + input alu_valid_i, lsu_valid_i; + + input op_lsu_load_i, op_lsu_store_i; + input op_jr_i, op_jbr_i; + + // External IRQ lines in + input [31:0] irq_i; + + // SPR data out + output [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o; + + // WE to RF for l.mfspr + output ctrl_mfspr_we_o; + + // Flag out to branch control, combinatorial + output flag_o; + + // Arithmetic flags to and from ALU + output carry_o; + input carry_set_i; + input carry_clear_i; + input overflow_set_i; + input overflow_clear_i; + + // Branch indicator from control unit (l.rfe/exception) + wire ctrl_branch_exception; + // PC out to fetch stage for l.rfe, exceptions + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc; + + // Clear instructions from decode and fetch stage + output pipeline_flush_o; + + output padv_fetch_o; + output padv_decode_o; + output padv_execute_o; + + // This indicates to the fetch unit only that it should basically interrupt + // whatever it's doing and start fetching the exception + output fetch_take_exception_branch_o; + // This indicates to other parts of the CPU that we've handled an excption + // so can be used to clear exception indication registers + output exception_taken_o; + + output execute_waiting_o; + output stepping_o; + + // Debug bus + input [15:0] du_addr_i; + input du_stb_i; + input [OPTION_OPERAND_WIDTH-1:0] du_dat_i; + input du_we_i; + output [OPTION_OPERAND_WIDTH-1:0] du_dat_o; + output du_ack_o; + // Stall control from debug interface + input du_stall_i; + output du_stall_o; + output [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o; + output du_restart_o; + + // SPR accesses to external units (cache, mmu, etc.) + output [15:0] spr_bus_addr_o; + output spr_bus_we_o; + output spr_bus_stb_o; + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i; + input spr_bus_ack_dc_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i; + input spr_bus_ack_ic_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i; + input spr_bus_ack_dmmu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i; + input spr_bus_ack_immu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i; + input spr_bus_ack_mac_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i; + input spr_bus_ack_pmu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i; + input spr_bus_ack_pcu_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i; + input spr_bus_ack_fpu_i; + output [15:0] spr_sr_o; + + // The multicore core identifier + input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i; + + // Internal signals + reg flag; + reg [SPR_SR_WIDTH-1:0] spr_sr; + reg [SPR_SR_WIDTH-1:0] spr_esr; + reg [OPTION_OPERAND_WIDTH-1:0] spr_epcr; + reg [OPTION_OPERAND_WIDTH-1:0] spr_eear; + + // Programmable Interrupt Control SPRs + wire [31:0] spr_picmr; + wire [31:0] spr_picsr; + + // Tick Timer SPRs + wire [31:0] spr_ttmr; + wire [31:0] spr_ttcr; + + reg [OPTION_OPERAND_WIDTH-1:0] spr_ppc; + reg [OPTION_OPERAND_WIDTH-1:0] spr_npc; + + output [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_target_o; + + reg execute_go; + wire execute_done; + + output ctrl_insn_done_o; + + reg execute_waiting_r; + + reg decode_execute_halt; + + reg exception_taken; + + reg take_exception; + reg exception_r; + + reg [OPTION_OPERAND_WIDTH-1:0] exception_pc_addr; + + reg waiting_for_fetch; + + reg doing_rfe_r; + wire doing_rfe; + wire deassert_doing_rfe; + + wire exception, exception_pending; + + wire execute_stage_exceptions; + wire decode_stage_exceptions; + + wire exception_re; + + wire [31:0] irq_unmasked; + + wire except_ticktimer; + wire except_pic; + + wire except_ticktimer_nonsrmasked; + wire except_pic_nonsrmasked; + + wire except_range; + + wire [15:0] spr_addr; + + wire op_mtspr; + wire op_mfspr; + wire op_rfe; + + wire [OPTION_OPERAND_WIDTH-1:0] b; + + wire execute_waiting; + + wire execute_valid; + + wire deassert_decode_execute_halt; + + wire ctrl_branch_occur; + wire new_branch; + output ctrl_branch_occur_o; + output rf_we_o; + input rf_wb_i; + wire except_ibus_align; + wire fetch_advance; + wire rfete; + wire stall_on_trap; + + /* Debug SPRs */ + reg [31:0] spr_dmr1; + reg [31:0] spr_dmr2; + reg [31:0] spr_dsr; + reg [31:0] spr_drr; + + /* DU internal control signals */ + wire du_access; + reg cpu_stall; + wire du_restart_from_stall; + wire [1:0] pstep; + wire stepping; + wire du_npc_write; + + /* Wires for SPR management */ + wire spr_group_present; + wire [3:0] spr_group; + wire spr_we; + wire spr_read; + wire [OPTION_OPERAND_WIDTH-1:0] spr_write_dat; + wire [11:0] spr_access_ack; + wire [31:0] spr_internal_read_dat [0:12]; + wire spr_read_access; + wire spr_write_access; + wire spr_bus_access; + reg [OPTION_OPERAND_WIDTH-1:0] spr_sys_group_read; + + /* Wires from mor1kx_cfgrs module */ + wire [31:0] spr_vr; + wire [31:0] spr_vr2; + wire [31:0] spr_avr; + wire [31:0] spr_upr; + wire [31:0] spr_cpucfgr; + wire [31:0] spr_dmmucfgr; + wire [31:0] spr_immucfgr; + wire [31:0] spr_dccfgr; + wire [31:0] spr_iccfgr; + wire [31:0] spr_dcfgr; + wire [31:0] spr_pccfgr; + wire [31:0] spr_fpcsr = 0; + wire [31:0] spr_isr [0:7]; + + assign b = ctrl_rfb_i; + + assign ctrl_branch_exception = (exception_r | (op_rfe | doing_rfe)) & + !exception_taken; + + assign exception_pending = (except_ibus_err_i | except_ibus_align | + except_illegal_i | except_syscall_i | + except_dbus_i | except_align_i | + except_ticktimer | except_range | + except_pic | except_trap_i ); + + assign exception = exception_pending; + + assign fetch_take_exception_branch_o = (take_exception | op_rfe) & + !stepping; + + assign execute_stage_exceptions = except_dbus_i | except_align_i | + except_range; + assign decode_stage_exceptions = except_trap_i | except_illegal_i; + + assign exception_re = exception & !exception_r & !exception_taken; + + assign deassert_decode_execute_halt = ctrl_branch_occur & + decode_execute_halt; + + assign ctrl_branch_except_pc = (op_rfe | doing_rfe) & !rfete ? spr_epcr : + exception_pc_addr; + + // Exceptions take precedence + assign ctrl_branch_occur = // instruction is branch, and flag is right + (op_jbr_i & + // is l.j or l.jal + (!(|ctrl_opc_insn_i[2:1]) | + // is l.bf/bnf and flag is right + (ctrl_opc_insn_i[2]==flag))) | + (op_jr_i & !(except_ibus_align)); + + assign ctrl_branch_occur_o = // Usual branch signaling + ((ctrl_branch_occur/* | ctrl_branch_exception*/) & + fetch_advance); + + assign ctrl_branch_target_o = ctrl_branch_exception ? + ctrl_branch_except_pc : + // jump or branch? + op_jbr_i ? ctrl_alu_result_i : + ctrl_rfb_i; + + // Do writeback when we register our output to the next stage, or if + // we're doing mfspr + assign rf_we_o = (execute_done /*& !delay_slot_rf_we_done*/) & + ((rf_wb_i & !op_mfspr + & !((op_lsu_load_i | op_lsu_store_i) & + except_dbus_i | except_align_i)) | + (op_mfspr)); + + assign except_range = (FEATURE_RANGE!="NONE") ? spr_sr[`OR1K_SPR_SR_OVE] && + (spr_sr[`OR1K_SPR_SR_OV] | overflow_set_i & + execute_done) & !doing_rfe: 0; + + // Check for unaligned jump address from register + assign except_ibus_align = op_jr_i & (|ctrl_rfb_i[1:0]); + + // Return from exception to exception (if pending tick or PIC ints) + assign rfete = (spr_esr[`OR1K_SPR_SR_IEE] & except_pic_nonsrmasked) | + (spr_esr[`OR1K_SPR_SR_TEE] & except_ticktimer_nonsrmasked); + + always @(posedge clk) + if (rst) + exception_pc_addr <= OPTION_RESET_PC; + else if (exception_re | (rfete & execute_done)) + casez( + {except_ibus_err_i, + except_illegal_i, + except_align_i, + except_ibus_align, + except_syscall_i, + except_trap_i, + except_dbus_i, + except_range, + except_pic_nonsrmasked, + except_ticktimer_nonsrmasked + } + ) + 10'b1?????????: + exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0}; + 10'b01????????: + exception_pc_addr <= {19'd0,`OR1K_ILLEGAL_VECTOR,8'd0}; + 10'b001???????, + 10'b0001??????: + exception_pc_addr <= {19'd0,`OR1K_ALIGN_VECTOR,8'd0}; + 10'b00001?????: + exception_pc_addr <= {19'd0,`OR1K_SYSCALL_VECTOR,8'd0}; + 10'b000001????: + exception_pc_addr <= {19'd0,`OR1K_TRAP_VECTOR,8'd0}; + 10'b0000001???: + exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0}; + 10'b00000001??: + exception_pc_addr <= {19'd0,`OR1K_RANGE_VECTOR,8'd0}; + 10'b000000001?: + exception_pc_addr <= {19'd0,`OR1K_INT_VECTOR,8'd0}; + //10'b00000000001: + default: + exception_pc_addr <= {19'd0,`OR1K_TT_VECTOR,8'd0}; + endcase // casex (... + + assign op_mtspr = ctrl_opc_insn_i==`OR1K_OPCODE_MTSPR; + assign op_mfspr = ctrl_opc_insn_i==`OR1K_OPCODE_MFSPR; + assign op_rfe = ctrl_opc_insn_i==`OR1K_OPCODE_RFE; + + reg waiting_for_except_fetch; + always @(posedge clk `OR_ASYNC_RST) + if (rst) + waiting_for_except_fetch <= 0; + else if (waiting_for_except_fetch & fetch_ready_i) + waiting_for_except_fetch <= 0; + else if (fetch_take_exception_branch_o) + waiting_for_except_fetch <= 1; + + assign fetch_advance = (fetch_ready_i | except_ibus_err_i) & + !execute_waiting & !cpu_stall & + (!stepping | + (stepping & pstep[0] & !fetch_ready_i)); + + assign padv_fetch_o = fetch_advance & !exception_pending & !doing_rfe_r & + !cpu_stall; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + take_exception <= 0; + else + take_exception <= (exception_pending/* | doing_rfe_r*/) & + (((fetch_advance & waiting_for_fetch) | execute_done | + fetch_sleep_i) | + // Cause exception to always be 'taken' if stepping + (stepping & execute_done) + ) & + // Would like this as only a single pulse + !take_exception; + + reg padv_decode_r; + // Some bits of the pipeline (execute_alu for instance) require a falling + // edge of the decode signal to start work on multi-cycle ops. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + padv_decode_r <= 0; + else + padv_decode_r <= padv_fetch_o; + + assign padv_decode_o = padv_decode_r; + + reg ctrl_branch_occur_r; + wire ctrl_branch_occur_re; + assign ctrl_branch_occur_re = ctrl_branch_occur & !ctrl_branch_occur_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_branch_occur_r <= 0; + else + ctrl_branch_occur_r <= ctrl_branch_occur; + + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_go <= 0; + else + // Note: turned padv_fetch_o here into (padv_fetch_o & + // !ctrl_branch_occur) for pronto version. This may have implications + // for exeception handling. + execute_go <= (padv_fetch_o & !(ctrl_branch_occur_re | op_rfe)) | + execute_waiting | (stepping & fetch_ready_i); + + assign execute_done = (execute_go | fetch_quick_branch_i) & + !execute_waiting & !cpu_stall; + // Note: we gate on cpu_stall here because a case was observed where + // the stall came during a multicycle instruction, and the rest of the + // pipeline had stalled and execute_done strobed, indicating the + // instruction completed but the PCs were not advanced. So it's best to + // just stop this signal asserting, meaning we don't allow the + // instruction to officially complete (result is not written to RF). + + assign ctrl_insn_done_o = execute_done; + + // ALU or LSU stall execution, nothing else can + assign execute_valid = !((op_lsu_load_i | op_lsu_store_i) & !lsu_valid_i | + !alu_valid_i); + + assign execute_waiting = !execute_valid & !waiting_for_fetch; + assign execute_waiting_o = execute_waiting; + + assign padv_execute_o = execute_done; + + assign spr_addr = du_access ? du_addr_i : ctrl_alu_result_i[15:0]; + assign ctrl_mfspr_we_o = op_mfspr & execute_go; + + // Pipeline flush + assign pipeline_flush_o = (execute_done & op_rfe) | + (exception_re) | + cpu_stall; + + // Flag + always @(posedge clk `OR_ASYNC_RST) + if (rst) + flag <= 0; + else if (execute_done) + flag <= ctrl_flag_clear_i ? 0 : + ctrl_flag_set_i ? 1 : flag; + + assign flag_o = flag; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_waiting_r <= 0; + else if (!execute_waiting) + execute_waiting_r <= 0; + else if (execute_waiting) + execute_waiting_r <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_execute_halt <= 0; + else if (du_restart_from_stall) + decode_execute_halt <= 0; + else if (decode_execute_halt & deassert_decode_execute_halt) + decode_execute_halt <= 0; + else if ((op_rfe | exception) & !decode_execute_halt & !exception_taken) + decode_execute_halt <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + exception_r <= 0; + else if (exception_taken | du_restart_from_stall) + exception_r <= 0; + else if (exception & !exception_r) + exception_r <= 1; + + // Signal to indicate that the incoming exception or l.rfe has been taken + // and we're waiting for it to propagate through the pipeline. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + exception_taken <= 0; + else if (exception_taken) + exception_taken <= 0; + else if (exception_r & take_exception) + exception_taken <= 1; + + assign exception_taken_o = exception_r & take_exception;//exception_taken; + + // Used to gate execute stage's advance signal in the case where a LSU op has + // finished before the next instruction has been fetched. Typically this + // occurs when not using icache and doing lots of memory accesses. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + waiting_for_fetch <= 0; + else if (fetch_ready_i) + waiting_for_fetch <= 0; + // Whenever execute not waiting and fetch not ready + else if (!execute_waiting /*& execute_waiting_r*/ & !fetch_ready_i) + waiting_for_fetch <= 1; + else if (execute_done & !fetch_ready_i) + waiting_for_fetch <= 1; + + assign doing_rfe = ((execute_done & op_rfe) | doing_rfe_r) & + !deassert_doing_rfe; + + // Basically, the fetch stage should always take the rfe immediately + assign deassert_doing_rfe = doing_rfe_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + doing_rfe_r <= 0; + else if (deassert_doing_rfe) + doing_rfe_r <= 0; + else if (execute_done) + doing_rfe_r <= op_rfe; + + assign spr_sr_o = spr_sr; + + // Supervision register + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_sr <= SPR_SR_RESET_VALUE; + else if (fetch_take_exception_branch_o) + begin + if (op_rfe & !rfete) + begin + spr_sr <= spr_esr; + end + else + begin + // Go into supervisor mode, disable interrupts, MMUs + spr_sr[`OR1K_SPR_SR_SM ] <= 1'b1; + if (FEATURE_TIMER!="NONE") + spr_sr[`OR1K_SPR_SR_TEE ] <= 1'b0; + if (FEATURE_PIC!="NONE") + spr_sr[`OR1K_SPR_SR_IEE ] <= 1'b0; + if (FEATURE_DMMU!="NONE") + spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0; + if (FEATURE_IMMU!="NONE") + spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0; + if (FEATURE_OVERFLOW!="NONE") + spr_sr[`OR1K_SPR_SR_OVE ] <= 1'b0; + end + end + else if (execute_done) + begin + spr_sr[`OR1K_SPR_SR_F ] <= ctrl_flag_set_i ? 1 : + ctrl_flag_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_F ]; + spr_sr[`OR1K_SPR_SR_CY ] <= carry_set_i ? 1 : + carry_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_CY ]; + if (FEATURE_OVERFLOW!="NONE") + spr_sr[`OR1K_SPR_SR_OV ] <= overflow_set_i ? 1 : + overflow_clear_i ? 0 : + spr_sr[`OR1K_SPR_SR_OV ]; + + if ((spr_we & (spr_sr[`OR1K_SPR_SR_SM] | du_access)) && + spr_addr==`OR1K_SPR_SR_ADDR) + begin + spr_sr[`OR1K_SPR_SR_SM ] <= spr_write_dat[`OR1K_SPR_SR_SM ]; + + spr_sr[`OR1K_SPR_SR_F ] <= spr_write_dat[`OR1K_SPR_SR_F ]; + + if (FEATURE_TIMER!="NONE") + spr_sr[`OR1K_SPR_SR_TEE ] <= spr_write_dat[`OR1K_SPR_SR_TEE ]; + + if (FEATURE_PIC!="NONE") + spr_sr[`OR1K_SPR_SR_IEE ] <= spr_write_dat[`OR1K_SPR_SR_IEE ]; + + if (FEATURE_DATACACHE!="NONE") + spr_sr[`OR1K_SPR_SR_DCE ] <= spr_write_dat[`OR1K_SPR_SR_DCE ]; + + if (FEATURE_INSTRUCTIONCACHE!="NONE") + spr_sr[`OR1K_SPR_SR_ICE ] <= spr_write_dat[`OR1K_SPR_SR_ICE ]; + + if (FEATURE_DMMU!="NONE") + spr_sr[`OR1K_SPR_SR_DME ] <= spr_write_dat[`OR1K_SPR_SR_DME ]; + + if (FEATURE_IMMU!="NONE") + spr_sr[`OR1K_SPR_SR_IME ] <= spr_write_dat[`OR1K_SPR_SR_IME ]; + + if (FEATURE_FASTCONTEXTS!="NONE") + spr_sr[`OR1K_SPR_SR_CE ] <= spr_write_dat[`OR1K_SPR_SR_CE ]; + + spr_sr[`OR1K_SPR_SR_CY ] <= spr_write_dat[`OR1K_SPR_SR_CY ]; + + if (FEATURE_OVERFLOW!="NONE") begin + spr_sr[`OR1K_SPR_SR_OV ] <= spr_write_dat[`OR1K_SPR_SR_OV ]; + spr_sr[`OR1K_SPR_SR_OVE ] <= spr_write_dat[`OR1K_SPR_SR_OVE ]; + end + + if (FEATURE_DSX!="NONE") + spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ]; + + spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ]; + + end // if ((spr_we & (spr_sr[`OR1K_SPR_SR_SM] | du_access)) &&... + + end // if (execute_done) + + assign carry_o = spr_sr[`OR1K_SPR_SR_CY]; + + // Exception SR + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_esr <= SPR_SR_RESET_VALUE; + else if (exception_re) + begin + spr_esr <= spr_sr; + /* + A bit odd, but if we had a l.sf instruction on an exception rising + edge, EPCR will point to the insn past the l.sf but the flag will + not have been saved to the SR properly. So we must put it in here + so it can be restored correctly. + Ditto for the other flags which may have been changed in a similar + fashion. + */ + if (execute_done) + begin + if (ctrl_flag_set_i) + spr_esr[`OR1K_SPR_SR_F ] <= 1'b1; + else if (ctrl_flag_clear_i) + spr_esr[`OR1K_SPR_SR_F ] <= 1'b0; + if (FEATURE_OVERFLOW!="NONE") + begin + if (overflow_set_i) + spr_esr[`OR1K_SPR_SR_OV ] <= 1'b1; + else if (overflow_clear_i) + spr_esr[`OR1K_SPR_SR_OV ] <= 1'b0; + end + if (carry_set_i) + spr_esr[`OR1K_SPR_SR_CY ] <= 1'b1; + else if (carry_clear_i) + spr_esr[`OR1K_SPR_SR_CY ] <= 1'b0; + end + end + else if (spr_we & spr_addr==`OR1K_SPR_ESR0_ADDR) + spr_esr <= spr_write_dat[SPR_SR_WIDTH-1:0]; + + // Exception PC + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_epcr <= OPTION_RESET_PC; + else if (exception_re & !(rfete & (op_rfe | deassert_doing_rfe))) + begin + if (except_ibus_err_i) + spr_epcr <= spr_ppc; + else if (except_syscall_i) + // EPCR after syscall is address of next not executed insn. + spr_epcr <= spr_npc; + else if (except_ticktimer | except_pic) + spr_epcr <= ctrl_branch_occur ? spr_ppc : spr_npc; + else if (execute_stage_exceptions | + // Don't update EPCR on software breakpoint + (decode_stage_exceptions & !(stall_on_trap & except_trap_i))) + spr_epcr <= spr_ppc; + else if (!(stall_on_trap & except_trap_i)) + spr_epcr <= spr_ppc; + end + else if (spr_we && spr_addr==`OR1K_SPR_EPCR0_ADDR) + spr_epcr <= spr_write_dat; + + // Exception Effective Address + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}}; + else if (exception_re) + begin + if (except_ibus_err_i) + spr_eear <= fetch_ppc_i; + else + spr_eear <= ctrl_alu_result_i; + end + + // Next PC (NPC) + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_npc <= OPTION_RESET_PC; + else if (deassert_doing_rfe) + spr_npc <= rfete ? exception_pc_addr : spr_epcr; + else if (du_npc_write) + spr_npc <= du_restart_pc_o; + else if (stepping & ctrl_branch_occur) + spr_npc <= ctrl_branch_target_o; + else if (stepping & fetch_ready_i) + spr_npc <= pc_fetch_next_i; + else if (stepping & exception_r) + spr_npc <= exception_pc_addr; + else if (stepping & execute_done & ctrl_branch_occur) + // The case where we stepped into a jump + spr_npc <= ctrl_branch_target_o; + else if (((fetch_advance & exception) | fetch_take_exception_branch_o) | + padv_fetch_o) + // PC we're now executing + spr_npc <= (fetch_take_exception_branch_o |(fetch_advance & exception)) ? + exception_pc_addr : (ctrl_branch_occur & !fetch_quick_branch_i) ? + ctrl_branch_target_o : pc_fetch_next_i; + + // Previous PC (PPC) + always @* + spr_ppc = fetch_ppc_i; + + assign spr_npc_o = spr_npc; + assign spr_ppc_o = spr_ppc; + + // This is for the writeback stage, when we have l.jal[r] instructions. + // Annoyingly, we can't rely on the link address being + // available without a dedicated bit of logic to calculate it, + // so do so here. + assign link_addr_o = spr_ppc + 4; + + mor1kx_cfgrs + #(.FEATURE_PIC (FEATURE_PIC), + .FEATURE_TIMER (FEATURE_TIMER), + .OPTION_PIC_TRIGGER (OPTION_PIC_TRIGGER), + .FEATURE_DSX (FEATURE_DSX), + .FEATURE_FASTCONTEXTS (FEATURE_FASTCONTEXTS), + .FEATURE_OVERFLOW (FEATURE_OVERFLOW), + .FEATURE_DATACACHE (FEATURE_DATACACHE), + .OPTION_DCACHE_BLOCK_WIDTH (OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH (OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS (OPTION_DCACHE_WAYS), + .FEATURE_DMMU (FEATURE_DMMU), + .FEATURE_INSTRUCTIONCACHE (FEATURE_INSTRUCTIONCACHE), + .OPTION_ICACHE_BLOCK_WIDTH (OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH (OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS (OPTION_ICACHE_WAYS), + .FEATURE_IMMU (FEATURE_IMMU), + .FEATURE_DEBUGUNIT (FEATURE_DEBUGUNIT), + .FEATURE_PERFCOUNTERS (FEATURE_PERFCOUNTERS), + .FEATURE_MAC (FEATURE_MAC), + .FEATURE_SYSCALL (FEATURE_SYSCALL), + .FEATURE_TRAP (FEATURE_TRAP), + .FEATURE_RANGE (FEATURE_RANGE) + ) + mor1kx_cfgrs + (/*AUTOINST*/ + // Outputs + .spr_vr (spr_vr[31:0]), + .spr_vr2 (spr_vr2[31:0]), + .spr_upr (spr_upr[31:0]), + .spr_cpucfgr (spr_cpucfgr[31:0]), + .spr_dmmucfgr (spr_dmmucfgr[31:0]), + .spr_immucfgr (spr_immucfgr[31:0]), + .spr_dccfgr (spr_dccfgr[31:0]), + .spr_iccfgr (spr_iccfgr[31:0]), + .spr_dcfgr (spr_dcfgr[31:0]), + .spr_pccfgr (spr_pccfgr[31:0]), + .spr_avr (spr_avr[31:0])); + + /* Implementation-specific registers */ + assign spr_isr[0] = 0; + assign spr_isr[1] = 0; + assign spr_isr[2] = 0; + assign spr_isr[3] = 0; + assign spr_isr[4] = 0; + assign spr_isr[5] = 0; + assign spr_isr[6] = 0; + assign spr_isr[7] = 0; + + // System group (0) SPR data out + always @* + case(spr_addr) + `OR1K_SPR_VR_ADDR: + spr_sys_group_read = spr_vr; + `OR1K_SPR_VR2_ADDR: + spr_sys_group_read = {spr_vr2[31:8], `MOR1KX_PIPEID_PRONTOESPRESSO}; + `OR1K_SPR_AVR_ADDR: + spr_sys_group_read = spr_avr; + `OR1K_SPR_UPR_ADDR: + spr_sys_group_read = spr_upr; + `OR1K_SPR_CPUCFGR_ADDR: + spr_sys_group_read = spr_cpucfgr; + `OR1K_SPR_DMMUCFGR_ADDR: + spr_sys_group_read = spr_dmmucfgr; + `OR1K_SPR_IMMUCFGR_ADDR: + spr_sys_group_read = spr_immucfgr; + `OR1K_SPR_DCCFGR_ADDR: + spr_sys_group_read = spr_dccfgr; + `OR1K_SPR_ICCFGR_ADDR: + spr_sys_group_read = spr_iccfgr; + `OR1K_SPR_DCFGR_ADDR: + spr_sys_group_read = spr_dcfgr; + `OR1K_SPR_PCCFGR_ADDR: + spr_sys_group_read = spr_pccfgr; + `OR1K_SPR_NPC_ADDR: + spr_sys_group_read = spr_npc; + `OR1K_SPR_SR_ADDR: + spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}}, + spr_sr}; + + `OR1K_SPR_PPC_ADDR: + spr_sys_group_read = spr_ppc; + `OR1K_SPR_FPCSR_ADDR: + spr_sys_group_read = spr_fpcsr; + `OR1K_SPR_EPCR0_ADDR: + spr_sys_group_read = spr_epcr; + `OR1K_SPR_EEAR0_ADDR: + spr_sys_group_read = spr_eear; + `OR1K_SPR_ESR0_ADDR: + spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}}, + spr_esr}; + `OR1K_SPR_ISR0_ADDR: + spr_sys_group_read = spr_isr[0]; + `OR1K_SPR_ISR0_ADDR +1: + spr_sys_group_read = spr_isr[1]; + `OR1K_SPR_ISR0_ADDR +2: + spr_sys_group_read = spr_isr[2]; + `OR1K_SPR_ISR0_ADDR +3: + spr_sys_group_read = spr_isr[3]; + `OR1K_SPR_ISR0_ADDR +4: + spr_sys_group_read = spr_isr[4]; + `OR1K_SPR_ISR0_ADDR +5: + spr_sys_group_read = spr_isr[5]; + `OR1K_SPR_ISR0_ADDR +6: + spr_sys_group_read = spr_isr[6]; + `OR1K_SPR_ISR0_ADDR +7: + spr_sys_group_read = spr_isr[7]; + + `OR1K_SPR_COREID_ADDR: + // If the multicore feature is activated this address returns the + // core identifier, 0 otherwise + spr_sys_group_read = (FEATURE_MULTICORE != "NONE") ? multicore_coreid_i : 0; + + default: begin + /* GPR read */ + if (spr_addr >= `OR1K_SPR_GPR0_ADDR && + spr_addr <= (`OR1K_SPR_GPR0_ADDR + 32)) + spr_sys_group_read = b; /* Register file */ + else + /* Invalid address - read as zero*/ + spr_sys_group_read = 0; + end + endcase // case (spr_addr) + + /* System group read data MUX in */ + assign spr_internal_read_dat[0] = spr_sys_group_read; + /* System group ack generation */ + /* TODO - might be delay for register file reads! */ + assign spr_access_ack[0] = 1; + + + + /* Generate data to the register file for mfspr operations */ + assign mfspr_dat_o = spr_internal_read_dat[spr_addr[14:11]]; + + // PIC SPR control + generate + if (FEATURE_PIC !="NONE") begin : pic + + /* mor1kx_pic AUTO_TEMPLATE ( + .spr_picsr_o (spr_picsr), + .spr_picmr_o (spr_picmr), + .spr_bus_ack (spr_access_ack[9]), + .spr_dat_o (spr_internal_read_dat[9]), + // Inputs + .spr_we_i (spr_we), + .spr_addr_i (spr_addr), + .spr_dat_i (spr_write_dat), + );*/ + mor1kx_pic + #( + .OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER), + .OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH) + ) + mor1kx_pic + (/*AUTOINST*/ + // Outputs + .spr_picmr_o (spr_picmr), // Templated + .spr_picsr_o (spr_picsr), // Templated + .spr_bus_ack (spr_access_ack[9]), // Templated + .spr_dat_o (spr_internal_read_dat[9]), // Templated + // Inputs + .clk (clk), + .rst (rst), + .irq_i (irq_i[31:0]), + .spr_we_i (spr_we), // Templated + .spr_addr_i (spr_addr), // Templated + .spr_dat_i (spr_write_dat)); // Templated + + assign except_pic_nonsrmasked = (|spr_picsr) & + !op_mtspr & + // Stops back-to-back branch addresses going to + // fetch stage + !ctrl_branch_occur; + + assign except_pic = spr_sr[`OR1K_SPR_SR_IEE] & except_pic_nonsrmasked & + !doing_rfe; + + end + else begin + assign except_pic_nonsrmasked = 0; + assign except_pic = 0; + assign spr_picsr = 0; + assign spr_picmr = 0; + assign spr_access_ack[9] = 0; + assign spr_internal_read_dat[9] = 0; + end // else: !if(FEATURE_PIC !="NONE") + endgenerate + + + generate + if (FEATURE_TIMER!="NONE") begin : tt + + /* mor1kx_ticktimer AUTO_TEMPLATE ( + .spr_ttmr_o (spr_ttmr), + .spr_ttcr_o (spr_ttcr), + .spr_bus_ack (spr_access_ack[10]), + .spr_dat_o (spr_internal_read_dat[10]), + // Inputs + .spr_we_i (spr_we), + .spr_addr_i (spr_addr), + .spr_dat_i (spr_write_dat), + );*/ + mor1kx_ticktimer mor1kx_ticktimer + (/*AUTOINST*/ + // Outputs + .spr_ttmr_o (spr_ttmr), // Templated + .spr_ttcr_o (spr_ttcr), // Templated + .spr_bus_ack (spr_access_ack[10]), // Templated + .spr_dat_o (spr_internal_read_dat[10]), // Templated + // Inputs + .clk (clk), + .rst (rst), + .spr_we_i (spr_we), // Templated + .spr_addr_i (spr_addr), // Templated + .spr_dat_i (spr_write_dat)); // Templated + + assign except_ticktimer_nonsrmasked = spr_ttmr[28] & + !(op_mtspr & !(spr_esr[`OR1K_SPR_SR_TEE] & execute_done)) & + // Stops back-to-back branch addresses to + // fetch stage. + !ctrl_branch_occur; + + assign except_ticktimer = except_ticktimer_nonsrmasked & + spr_sr[`OR1K_SPR_SR_TEE] & !doing_rfe; + end // if (FEATURE_TIMER!="NONE") + else begin + assign except_ticktimer_nonsrmasked = 0; + assign except_ticktimer = 0; + assign spr_ttmr = 0; + assign spr_ttcr = 0; + assign spr_access_ack[10] = 0; + assign spr_internal_read_dat[10] = 0; + end // else: !if(FEATURE_TIMER!="NONE") + endgenerate + + /* SPR access control - allow accesses from either the instructions or from + the debug interface */ + assign spr_read_access = (op_mfspr | (du_access & !du_we_i)); + assign spr_write_access = ((execute_done & op_mtspr) | (du_access & du_we_i)); + + assign spr_write_dat = du_access ? du_dat_i : b; + assign spr_we = spr_write_access & spr_group_present; + assign spr_read = spr_read_access & spr_group_present; + + /* A bus out to other units that live outside of the control unit */ + assign spr_bus_addr_o = spr_addr; + assign spr_bus_we_o = spr_write_access & spr_group_present & spr_bus_access; + assign spr_bus_stb_o = (spr_read_access | spr_write_access) & + spr_group_present & spr_bus_access; + assign spr_bus_dat_o = spr_write_dat; + + /* Is the SPR in the design? */ + assign spr_group_present = (// System group + (spr_addr[15:11]==5'h00) || + // DMMU + (spr_addr[15:11]==5'h01 && + FEATURE_DMMU!="NONE") || + // IMMU + (spr_addr[15:11]==5'h02 && + FEATURE_IMMU!="NONE") || + // Data cache + (spr_addr[15:11]==5'h03 && + FEATURE_DATACACHE!="NONE") || + // Instruction cache + (spr_addr[15:11]==5'h04 && + FEATURE_INSTRUCTIONCACHE!= "NONE") || + // MAC unit + (spr_addr[15:11]==5'h05 && + FEATURE_MAC!="NONE") || + // Debug unit + (spr_addr[15:11]==5'h06 && + FEATURE_DEBUGUNIT!="NONE") || + // Performance counters + (spr_addr[15:11]==5'h07 && + FEATURE_PERFCOUNTERS!="NONE") || + // Power Management + (spr_addr[15:11]==5'h08 && + FEATURE_PMU!="NONE") || + // PIC + (spr_addr[15:11]==5'h09 && + FEATURE_PIC!="NONE") || + // Tick timer + (spr_addr[15:11]==5'h0a && + FEATURE_TIMER!="NONE") || + // FPU + (spr_addr[15:11]==5'h0b && + FEATURE_FPU!="NONE") + ); + + /* Generate a SPR group signal - generate invalid if the group is not + present in the design */ + assign spr_group = (spr_group_present) ? spr_addr[14:11] : 4'd12; + + /* Default group when a selected one is not present - it reads as zero */ + assign spr_internal_read_dat[12] = 0; + + /* Is a SPR bus access needed, or is the requested SPR in this file? */ + assign spr_bus_access = /* Any of the units we don't have in this file */ + /* System group */ + !(spr_addr[15:11]==5'h00 || + /* Debug Group */ + spr_addr[15:11]==5'h06 || + /* PIC Group */ + spr_addr[15:11]==5'h09 || + /* Tick Group */ + spr_addr[15:11]==5'h0a); + + assign stepping_o = stepping; + + generate + if (FEATURE_DEBUGUNIT!="NONE") begin : du + + reg [OPTION_OPERAND_WIDTH-1:0] du_read_dat; + + reg du_ack; + reg du_stall_r; + reg [1:0] pstep_r; + reg [1:0] branch_step; + reg stepped_into_exception; + reg stepped_into_rfe; + + assign du_access = du_stb_i; + + // Generate ack back to the debug interface bus + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_ack <= 0; + else if (du_ack) + du_ack <= 0; + else if (du_stb_i) begin + if (!spr_group_present) + /* Unit doesn't exist, ACK to clear the access, nothing done */ + du_ack <= 1; + else if (spr_access_ack[spr_group]) + /* actual access occurred */ + du_ack <= 1; + end + + assign du_ack_o = du_ack; + + /* Data back to the debug bus */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_read_dat <= 0; + else if (spr_access_ack[spr_group]) begin + du_read_dat <= spr_internal_read_dat[spr_group]; + end + + assign du_dat_o = du_read_dat; + /* TODO: check into only letting stall go high when we've gracefully + completed the instruction currently in the ctrl stage. + Why? Potentially an instruction like l.mfspr from an external unit + hasn't completed fully, gets interrupted, and it's assumed it's + completed, but actually hasn't. */ + + always @(posedge clk) + cpu_stall <= du_stall_i | du_restart_from_stall; + + /* goes out to the debug interface and comes back 1 cycle later + via du_stall_i */ + assign du_stall_o = (stepping & execute_done) | + (stall_on_trap & execute_done & except_trap_i); + + /* Pulse to indicate we're restarting after a stall */ + assign du_restart_from_stall = du_stall_r & !du_stall_i; + + /* NPC debug control logic */ + assign du_npc_write = (du_we_i && du_addr_i==`OR1K_SPR_NPC_ADDR && + du_ack_o); + + /* Pick the traps-cause-stall bit out of the DSR */ + assign stall_on_trap = spr_dsr[`OR1K_SPR_DSR_TE]; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + stepped_into_exception <= 0; + else if (du_restart_from_stall) + stepped_into_exception <= 0; + else if (stepping & execute_done) + stepped_into_exception <= exception; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + stepped_into_rfe <= 0; + else if (du_restart_from_stall) + stepped_into_rfe <= 0; + else if (stepping & execute_done) + stepped_into_rfe <= op_rfe; + + assign du_restart_pc_o = du_npc_write ? du_dat_i : + stepped_into_rfe ? spr_epcr : spr_npc; + + assign du_restart_o = du_restart_from_stall; + + /* Indicate when we're stepping */ + assign stepping = spr_dmr1[`OR1K_SPR_DMR1_ST] & + spr_dsr[`OR1K_SPR_DSR_TE]; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + pstep_r <= 0; + else if (du_restart_from_stall & stepping) + pstep_r <= 2'd1; + else if ((pstep[0] & fetch_ready_i) | + /* decode is always single cycle */ + (pstep[1] & execute_done)) + pstep_r <= {pstep_r[0],1'b0}; + + assign pstep = pstep_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + branch_step <= 0; + else if (stepping & pstep[1]) + branch_step <= {branch_step[0], ctrl_branch_occur}; + else if (!stepping & execute_done) + branch_step <= {branch_step[0], /*execute_delay_slot*/ 1'b0}; + + /* Signals for waveform debuging */ + wire [31:0] spr_read_data_group_0; + assign spr_read_data_group_0 = spr_internal_read_dat[0]; + wire [31:0] spr_read_data_group_1; + assign spr_read_data_group_1 = spr_internal_read_dat[1]; + wire [31:0] spr_read_data_group_2; + assign spr_read_data_group_2 = spr_internal_read_dat[2]; + wire [31:0] spr_read_data_group_3; + assign spr_read_data_group_3 = spr_internal_read_dat[3]; + wire [31:0] spr_read_data_group_4; + assign spr_read_data_group_4 = spr_internal_read_dat[4]; + wire [31:0] spr_read_data_group_5; + assign spr_read_data_group_5 = spr_internal_read_dat[5]; + wire [31:0] spr_read_data_group_6; + assign spr_read_data_group_6 = spr_internal_read_dat[6]; + wire [31:0] spr_read_data_group_7; + assign spr_read_data_group_7 = spr_internal_read_dat[7]; + wire [31:0] spr_read_data_group_8; + assign spr_read_data_group_8 = spr_internal_read_dat[8]; + wire [31:0] spr_read_data_group_9; + assign spr_read_data_group_9 = spr_internal_read_dat[9]; + + + /* always single cycle access */ + assign spr_access_ack[6] = 1; + assign spr_internal_read_dat[6] = (spr_addr==`OR1K_SPR_DMR1_ADDR) ? + spr_dmr1 : + (spr_addr==`OR1K_SPR_DMR2_ADDR) ? + spr_dmr2 : + (spr_addr==`OR1K_SPR_DSR_ADDR) ? + spr_dsr : + (spr_addr==`OR1K_SPR_DRR_ADDR) ? + spr_drr : 0; + + /* Put the incoming stall signal through a register to detect FE */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + du_stall_r <= 0; + else + du_stall_r <= du_stall_i; + + /* DMR1 */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_dmr1 <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DMR1_ADDR) + spr_dmr1[23:0] <= spr_write_dat[23:0]; + + /* DMR2 */ + always @(posedge clk) + spr_dmr2 <= 0; + + /* DSR */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_dsr <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DSR_ADDR) + spr_dsr[13:0] <= spr_write_dat[13:0]; + + /* DRR */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_drr <= 0; + else if (spr_we && spr_addr==`OR1K_SPR_DRR_ADDR) + spr_drr[13:0] <= spr_write_dat[13:0]; + else if (stall_on_trap & execute_done & except_trap_i) + spr_drr[`OR1K_SPR_DRR_TE] <= 1; + + + end // block: du + else + begin : no_du + assign du_access = 0; + assign du_stall_o = 0; + assign du_ack_o = 0; + assign du_restart_o = 0; + assign du_restart_pc_o = 0; + assign stepping = 0; + assign du_npc_write = 0; + assign du_dat_o = 0; + assign du_restart_from_stall = 0; + assign spr_access_ack[6] = 0; + + always @(posedge clk) + begin + cpu_stall <= 0; + spr_dmr1 <= 0; + spr_dmr2 <= 0; + spr_dsr <= 0; + spr_drr <= 0; + end + end + endgenerate + + /* Controls to generate ACKs from units that are external to this module */ + generate + if (FEATURE_DMMU!="NONE") begin : dmmu_ctrl + assign spr_access_ack[1] = spr_bus_ack_dmmu_i; + assign spr_internal_read_dat[1] = spr_bus_dat_dmmu_i; + end + else begin + assign spr_access_ack[1] = 0; + assign spr_internal_read_dat[1] = 0; + end + endgenerate + + generate + if (FEATURE_IMMU!="NONE") begin : immu_ctrl + assign spr_access_ack[2] = spr_bus_ack_immu_i; + assign spr_internal_read_dat[2] = spr_bus_dat_immu_i; + end + else begin + assign spr_access_ack[2] = 0; + assign spr_internal_read_dat[2] = 0; + end + endgenerate + + generate + if (FEATURE_DATACACHE!="NONE") begin : datacache_ctrl + assign spr_access_ack[3] = spr_bus_ack_dc_i; + assign spr_internal_read_dat[3] = spr_bus_dat_dc_i; + end + else begin + assign spr_access_ack[3] = 0; + assign spr_internal_read_dat[3] = 0; + end + endgenerate + + generate + if (FEATURE_INSTRUCTIONCACHE!="NONE") begin : instructioncache_ctrl + assign spr_access_ack[4] = spr_bus_ack_ic_i; + assign spr_internal_read_dat[4] = spr_bus_dat_ic_i; + end + else begin + assign spr_access_ack[4] = 0; + assign spr_internal_read_dat[4] = 0; + end + endgenerate + + generate + if (FEATURE_MAC!="NONE") begin : mac_ctrl + assign spr_access_ack[5] = spr_bus_ack_mac_i; + assign spr_internal_read_dat[5] = spr_bus_dat_mac_i; + end + else begin + assign spr_access_ack[5] = 0; + assign spr_internal_read_dat[5] = 0; + end + endgenerate + + generate + if (FEATURE_PERFCOUNTERS!="NONE") begin : perfcounters_ctrl + assign spr_access_ack[7] = spr_bus_ack_pcu_i; + assign spr_internal_read_dat[7] = spr_bus_dat_pcu_i; + end + else begin + assign spr_access_ack[7] = 0; + assign spr_internal_read_dat[7] = 0; + end + endgenerate + + generate + if (FEATURE_PMU!="NONE") begin : pmu_ctrl + assign spr_access_ack[8] = spr_bus_ack_pmu_i; + assign spr_internal_read_dat[8] = spr_bus_dat_pcu_i; + end + else begin + assign spr_access_ack[8] = 0; + assign spr_internal_read_dat[8] = 0; + end + endgenerate + + generate + if (FEATURE_FPU!="NONE") begin : fpu_ctrl + assign spr_access_ack[11] = spr_bus_ack_fpu_i; + assign spr_internal_read_dat[11] = spr_bus_dat_fpu_i; + end + else begin + assign spr_access_ack[11] = 0; + assign spr_internal_read_dat[11] = 0; + end + endgenerate + + // synthesis translate_off + + generate + if (FEATURE_INBUILT_CHECKERS != "NONE") begin : execute_checker + + reg [OPTION_OPERAND_WIDTH-1:0] last_execute_pc; + reg just_branched = 1; + reg had_rfe = 0; + integer insns = 0; + + + // A monitor to do a rudimentary check of the processor's PC + // progression + always @(negedge clk) begin + + if (op_rfe) + had_rfe = 1; + + if (execute_done & !stepping) begin + + // First instruction of an exception vector, ie. + // 0x100, 0x200, 0x300 ... 0x2000 + if (~|spr_ppc[31:14] && ~|spr_ppc[7:0]) + just_branched = 1; + + if (!just_branched && spr_ppc != (last_execute_pc+4) && + (insns > 2)) + begin + /* verilator lint_off STMTDLY */ + #5; + /* verilator lint_on STMTDLY */ + $display("CPU didn't execute in correct order"); + $display("went: %08h, %08h",last_execute_pc, spr_ppc); + $finish(); + end + + insns = insns + 1; + last_execute_pc = spr_ppc; + + case (ctrl_opc_insn_i) + `OR1K_OPCODE_J, + `OR1K_OPCODE_JAL, + `OR1K_OPCODE_JALR, + `OR1K_OPCODE_JR, + `OR1K_OPCODE_BNF, + `OR1K_OPCODE_BF, + `OR1K_OPCODE_RFE, + `OR1K_OPCODE_SYSTRAPSYNC: + just_branched = 1; + default: + just_branched = 0; + endcase // case (`EXECUTE_STAGE_INSN[`OR1K_OPCODE_POS]) + + if (had_rfe) + begin + // Sometimes the RFE will pulse high, and the + // branch logic in the fetch stage will acknowledge + // it but the instruction isn't "acked" in the + // control stage. + just_branched = 1; + had_rfe = 0; + end + + end // if (execute_done & !stepping) + else if (du_npc_write) + just_branched = 1; + end // always @ (posedge `CPU_clk) + end + endgenerate + // synthesis translate_on + +endmodule // mor1kx_ctrl diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dcache.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dcache.v new file mode 100644 index 0000000..fbcaeef --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dcache.v @@ -0,0 +1,688 @@ +/****************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Data cache implementation + + Copyright (C) 2012-2013 + Stefan Kristiansson + Stefan Wallentowitz + + ******************************************************************************/ + +`include "mor1kx-defines.v" + +module mor1kx_dcache + #( + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter OPTION_DCACHE_LIMIT_WIDTH = 32, + parameter OPTION_DCACHE_SNOOP = "NONE" + ) + ( + input clk, + input rst, + + input dc_dbus_err_i, + input dc_enable_i, + input dc_access_i, + output refill_o, + output refill_req_o, + output refill_done_o, + + // CPU Interface + output cpu_err_o, + output cpu_ack_o, + output reg [OPTION_OPERAND_WIDTH-1:0] cpu_dat_o, + input [OPTION_OPERAND_WIDTH-1:0] cpu_dat_i, + input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_i, + input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_match_i, + input cpu_req_i, + input cpu_we_i, + input [3:0] cpu_bsel_i, + + input refill_allowed, + + input [OPTION_OPERAND_WIDTH-1:0] wradr_i, + input [OPTION_OPERAND_WIDTH-1:0] wrdat_i, + input we_i, + + // Snoop address + input [31:0] snoop_adr_i, + // Snoop event in this cycle + input snoop_valid_i, + // Whether the snoop hit. If so, there will be no tag memory write + // this cycle. The LSU may need to stall the pipeline. + output snoop_hit_o, + + + // SPR interface + input [15:0] spr_bus_addr_i, + input spr_bus_we_i, + input spr_bus_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i, + + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + output spr_bus_ack_o + ); + + // States + localparam IDLE = 5'b00001; + localparam READ = 5'b00010; + localparam WRITE = 5'b00100; + localparam REFILL = 5'b01000; + localparam INVALIDATE = 5'b10000; + + // Address space in bytes for a way + localparam WAY_WIDTH = OPTION_DCACHE_BLOCK_WIDTH + OPTION_DCACHE_SET_WIDTH; + /* + * Tag memory layout + * +---------------------------------------------------------+ + * (index) -> | LRU | wayN valid | wayN tag |...| way0 valid | way0 tag | + * +---------------------------------------------------------+ + */ + + // The tag is the part left of the index + localparam TAG_WIDTH = (OPTION_DCACHE_LIMIT_WIDTH - WAY_WIDTH); + + // The tag memory contains entries with OPTION_DCACHE_WAYS parts of + // each TAGMEM_WAY_WIDTH. Each of those is tag and a valid flag. + localparam TAGMEM_WAY_WIDTH = TAG_WIDTH + 1; + localparam TAGMEM_WAY_VALID = TAGMEM_WAY_WIDTH - 1; + + // Additionally, the tag memory entry contains an LRU value. The + // width of this is 0 for OPTION_DCACHE_LIMIT_WIDTH==1 + localparam TAG_LRU_WIDTH = OPTION_DCACHE_WAYS*(OPTION_DCACHE_WAYS-1) >> 1; + + // We have signals for the LRU which are not used for one way + // caches. To avoid signal width [-1:0] this generates [0:0] + // vectors for them, which are removed automatically then. + localparam TAG_LRU_WIDTH_BITS = (OPTION_DCACHE_WAYS >= 2) ? TAG_LRU_WIDTH : 1; + + // Compute the total sum of the entry elements + localparam TAGMEM_WIDTH = TAGMEM_WAY_WIDTH * OPTION_DCACHE_WAYS + TAG_LRU_WIDTH; + + // For convenience we define the position of the LRU in the tag + // memory entries + localparam TAG_LRU_MSB = TAGMEM_WIDTH - 1; + localparam TAG_LRU_LSB = TAG_LRU_MSB - TAG_LRU_WIDTH + 1; + + // FSM state signals + reg [4:0] state; + wire read; + wire write; + wire refill; + + reg [WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH] invalidate_adr; + wire [31:0] next_refill_adr; + reg [31:0] way_wr_dat; + wire refill_done; + wire refill_hit; + reg [(1<<(OPTION_DCACHE_BLOCK_WIDTH-2))-1:0] refill_valid; + reg [(1<<(OPTION_DCACHE_BLOCK_WIDTH-2))-1:0] refill_valid_r; + wire invalidate; + + // The index we read and write from tag memory + wire [OPTION_DCACHE_SET_WIDTH-1:0] tag_rindex; + reg [OPTION_DCACHE_SET_WIDTH-1:0] tag_windex; + + // The data from the tag memory + wire [TAGMEM_WIDTH-1:0] tag_dout; + wire [TAG_LRU_WIDTH_BITS-1:0] tag_lru_out; + wire [TAGMEM_WAY_WIDTH-1:0] tag_way_out [OPTION_DCACHE_WAYS-1:0]; + + // The data to the tag memory + wire [TAGMEM_WIDTH-1:0] tag_din; + reg [TAG_LRU_WIDTH_BITS-1:0] tag_lru_in; + reg [TAGMEM_WAY_WIDTH-1:0] tag_way_in [OPTION_DCACHE_WAYS-1:0]; + + reg [TAGMEM_WAY_WIDTH-1:0] tag_way_save[OPTION_DCACHE_WAYS-1:0]; + + // Whether to write to the tag memory in this cycle + reg tag_we; + + // This is the tag we need to write to the tag memory during refill + wire [TAG_WIDTH-1:0] tag_wtag; + + // This is the tag we check against + wire [TAG_WIDTH-1:0] tag_tag; + + // Access to the way memories + wire [WAY_WIDTH-3:0] way_raddr[OPTION_DCACHE_WAYS-1:0]; + wire [WAY_WIDTH-3:0] way_waddr[OPTION_DCACHE_WAYS-1:0]; + wire [OPTION_OPERAND_WIDTH-1:0] way_din[OPTION_DCACHE_WAYS-1:0]; + wire [OPTION_OPERAND_WIDTH-1:0] way_dout[OPTION_DCACHE_WAYS-1:0]; + reg [OPTION_DCACHE_WAYS-1:0] way_we; + + // Does any way hit? + wire hit; + wire [OPTION_DCACHE_WAYS-1:0] way_hit; + + // This is the least recently used value before access the memory. + // Those are one hot encoded. + wire [OPTION_DCACHE_WAYS-1:0] lru; + + // Register that stores the LRU value from lru + reg [OPTION_DCACHE_WAYS-1:0] tag_save_lru; + + // The access vector to update the LRU history is the way that has + // a hit or is refilled. It is also one-hot encoded. + reg [OPTION_DCACHE_WAYS-1:0] access; + + // The current LRU history as read from tag memory and the update + // value after we accessed it to write back to tag memory. + wire [TAG_LRU_WIDTH_BITS-1:0] current_lru_history; + wire [TAG_LRU_WIDTH_BITS-1:0] next_lru_history; + + // Intermediate signals to ease debugging + wire [TAG_WIDTH-1:0] check_way_tag [OPTION_DCACHE_WAYS-1:0]; + wire check_way_match [OPTION_DCACHE_WAYS-1:0]; + wire check_way_valid [OPTION_DCACHE_WAYS-1:0]; + + reg write_pending; + + // Extract index to read from snooped address + wire [OPTION_DCACHE_SET_WIDTH-1:0] snoop_index; + assign snoop_index = snoop_adr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH]; + + // Register that is high one cycle after the actual snoop event to + // drive the comparison + reg snoop_check; + // Register that stores the tag for one cycle + reg [TAG_WIDTH-1:0] snoop_tag; + // Also store the index for one cycle, for the succeeding write access + reg [OPTION_DCACHE_SET_WIDTH-1:0] snoop_windex; + + // Snoop tag memory interface + // Data out of tag memory + wire [TAGMEM_WIDTH-1:0] snoop_dout; + // Each ways information in the tag memory + wire [TAGMEM_WAY_WIDTH-1:0] snoop_way_out [OPTION_DCACHE_WAYS-1:0]; + // Each ways tag in the tag memory + wire [TAG_WIDTH-1:0] snoop_check_way_tag [OPTION_DCACHE_WAYS-1:0]; + // Whether the tag matches the snoop tag + wire snoop_check_way_match [OPTION_DCACHE_WAYS-1:0]; + // Whether the tag is valid + wire snoop_check_way_valid [OPTION_DCACHE_WAYS-1:0]; + // Whether the way hits + wire [OPTION_DCACHE_WAYS-1:0] snoop_way_hit; + // Whether any way hits + wire snoop_hit; + + assign snoop_hit_o = (OPTION_DCACHE_SNOOP != "NONE") ? snoop_hit : 0; + + genvar i; + + assign cpu_ack_o = ((read | refill) & hit & !write_pending | + refill_hit) & cpu_req_i & !snoop_hit; + + assign tag_rindex = cpu_adr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH]; + + assign tag_tag = cpu_adr_match_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH]; + assign tag_wtag = wradr_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH]; + + generate + if (OPTION_DCACHE_WAYS >= 2) begin + // Multiplex the LRU history from and to tag memory + assign current_lru_history = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB]; + assign tag_din[TAG_LRU_MSB:TAG_LRU_LSB] = tag_lru_in; + assign tag_lru_out = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB]; + end + + for (i = 0; i < OPTION_DCACHE_WAYS; i=i+1) begin : ways + assign way_raddr[i] = cpu_adr_i[WAY_WIDTH-1:2]; + assign way_waddr[i] = write ? cpu_adr_match_i[WAY_WIDTH-1:2] : + wradr_i[WAY_WIDTH-1:2]; + assign way_din[i] = way_wr_dat; + + // compare stored tag with incoming tag and check valid bit + assign check_way_tag[i] = tag_way_out[i][TAG_WIDTH-1:0]; + assign check_way_match[i] = (check_way_tag[i] == tag_tag); + assign check_way_valid[i] = tag_way_out[i][TAGMEM_WAY_VALID]; + + assign way_hit[i] = check_way_valid[i] & check_way_match[i]; + + // Multiplex the way entries in the tag memory + assign tag_din[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH] = tag_way_in[i]; + assign tag_way_out[i] = tag_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH]; + + if (OPTION_DCACHE_SNOOP != "NONE") begin + // The same for the snoop tag memory + assign snoop_way_out[i] = snoop_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH]; + + assign snoop_check_way_tag[i] = snoop_way_out[i][TAG_WIDTH-1:0]; + assign snoop_check_way_match[i] = (snoop_check_way_tag[i] == snoop_tag); + assign snoop_check_way_valid[i] = snoop_way_out[i][TAGMEM_WAY_VALID]; + + assign snoop_way_hit[i] = snoop_check_way_valid[i] & snoop_check_way_match[i]; + end + end + endgenerate + + assign hit = |way_hit; + + assign snoop_hit = (OPTION_DCACHE_SNOOP != "NONE") & + |snoop_way_hit & snoop_check; + + integer w0; + always @(*) begin + cpu_dat_o = {OPTION_OPERAND_WIDTH{1'bx}}; + + // Put correct way on the data port + for (w0 = 0; w0 < OPTION_DCACHE_WAYS; w0 = w0 + 1) begin + if (way_hit[w0] | (refill_hit & tag_save_lru[w0])) begin + cpu_dat_o = way_dout[w0]; + end + end + end + + assign next_refill_adr = (OPTION_DCACHE_BLOCK_WIDTH == 5) ? + {wradr_i[31:5], wradr_i[4:0] + 5'd4} : // 32 byte + {wradr_i[31:4], wradr_i[3:0] + 4'd4}; // 16 byte + + assign refill_done_o = refill_done; + assign refill_done = refill_valid[next_refill_adr[OPTION_DCACHE_BLOCK_WIDTH-1:2]]; + assign refill_hit = refill_valid_r[cpu_adr_match_i[OPTION_DCACHE_BLOCK_WIDTH-1:2]] & + cpu_adr_match_i[OPTION_DCACHE_LIMIT_WIDTH-1: + OPTION_DCACHE_BLOCK_WIDTH] == + wradr_i[OPTION_DCACHE_LIMIT_WIDTH-1: + OPTION_DCACHE_BLOCK_WIDTH] & + refill & !write_pending; + + assign refill = (state == REFILL); + assign read = (state == READ); + assign write = (state == WRITE); + + assign refill_o = refill; + + assign refill_req_o = read & cpu_req_i & !hit & !write_pending & refill_allowed | refill; + + /* + * SPR bus interface + */ + + // The SPR interface is used to invalidate the cache blocks. When + // an invalidation is started, the respective entry in the tag + // memory is cleared. When another transfer is in progress, the + // handling is delayed until it is possible to serve it. + // + // The invalidation is acknowledged to the SPR bus, but the cycle + // is terminated by the core. We therefore need to hold the + // invalidate acknowledgement. Meanwhile we continuously write the + // tag memory which is no problem. + + // Net that signals an acknowledgement + reg invalidate_ack; + + // An invalidate request is either a block flush or a block invalidate + assign invalidate = spr_bus_stb_i & spr_bus_we_i & + (spr_bus_addr_i == `OR1K_SPR_DCBFR_ADDR | + spr_bus_addr_i == `OR1K_SPR_DCBIR_ADDR); + + // Acknowledge to the SPR bus. + assign spr_bus_ack_o = invalidate_ack; + + /* + * Cache FSM + * Starts in IDLE. + * State changes between READ and WRITE happens cpu_we_i is asserted or not. + * cpu_we_i is in sync with cpu_adr_i, so that means that it's the + * *upcoming* write that it is indicating. It only toggles for one cycle, + * so if we are busy doing something else when this signal comes + * (i.e. refilling) we assert the write_pending signal. + * cpu_req_i is in sync with cpu_adr_match_i, so it can be used to + * determined if a cache hit should cause a refill or if a write should + * really be executed. + */ + integer w1; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + state <= IDLE; + write_pending <= 0; + end else if(dc_dbus_err_i) begin + state <= IDLE; + write_pending <= 0; + end else begin + if (cpu_we_i) + write_pending <= 1; + else if (!cpu_req_i) + write_pending <= 0; + + refill_valid_r <= refill_valid; + + if (snoop_valid_i) begin + // + // If there is a snoop event, we need to store this + // information. This happens independent of whether we + // have a snoop tag memory or not. + // + snoop_check <= 1; + snoop_windex <= snoop_index; + snoop_tag <= snoop_adr_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH]; + end else begin + snoop_check <= 0; + end + + case (state) + IDLE: begin + if (invalidate) begin + // If there is an invalidation request + // + // Store address in invalidate_adr that is muxed to the tag + // memory write address + invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH]; + + // Change to invalidate state that actually accesses + // the tag memory + state <= INVALIDATE; + end else if (cpu_we_i | write_pending) + state <= WRITE; + else if (cpu_req_i) + state <= READ; + end + + READ: begin + if (dc_access_i | cpu_we_i & dc_enable_i) begin + if (!hit & cpu_req_i & !write_pending & refill_allowed) begin + refill_valid <= 0; + refill_valid_r <= 0; + + // Store the LRU information for correct replacement + // on refill. Always one when only one way. + tag_save_lru <= (OPTION_DCACHE_WAYS==1) | lru; + + for (w1 = 0; w1 < OPTION_DCACHE_WAYS; w1 = w1 + 1) begin + tag_way_save[w1] <= tag_way_out[w1]; + end + + state <= REFILL; + end else if (cpu_we_i | write_pending) begin + state <= WRITE; + end else if (invalidate) begin + state <= IDLE; + end + end else if (!dc_enable_i | invalidate) begin + state <= IDLE; + end + end + + REFILL: begin + if (we_i) begin + refill_valid[wradr_i[OPTION_DCACHE_BLOCK_WIDTH-1:2]] <= 1; + + if (refill_done) + state <= IDLE; + end + // Abort refill on snoop-hit + // TODO: only abort on snoop-hits to refill address + if (snoop_hit) begin + refill_valid <= 0; + refill_valid_r <= 0; + state <= IDLE; + end + end + + WRITE: begin + if ((!dc_access_i | !cpu_req_i | !cpu_we_i) & !snoop_hit) begin + write_pending <= 0; + state <= READ; + end + end + + INVALIDATE: begin + if (invalidate) begin + // Store address in invalidate_adr that is muxed to the tag + // memory write address + invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH]; + + state <= INVALIDATE; + end else begin + state <= IDLE; + end + end + + default: + state <= IDLE; + endcase + end + end + + // + // This is the combinational part of the state machine that + // interfaces the tag and way memories. + // + integer w2; + always @(*) begin + // Default is to keep data, don't write and don't access + tag_lru_in = tag_lru_out; + for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin + tag_way_in[w2] = tag_way_out[w2]; + end + + tag_we = 1'b0; + way_we = {(OPTION_DCACHE_WAYS){1'b0}}; + + access = {(OPTION_DCACHE_WAYS){1'b0}}; + + way_wr_dat = wrdat_i; + + // The default is (of course) not to acknowledge the invalidate + invalidate_ack = 1'b0; + + if (snoop_hit) begin + // This is the write access + tag_we = 1'b1; + tag_windex = snoop_windex; + for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin + if (snoop_way_hit[w2]) begin + tag_way_in[w2] = 0; + end else begin + tag_way_in[w2] = snoop_way_out[w2]; + end + end + end else begin + // + // The tag mem is written during reads and writes to write + // the lru info and during refill and invalidate. + // + tag_windex = read | write ? + cpu_adr_match_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH] : + (state == INVALIDATE) ? invalidate_adr : + wradr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH]; + + case (state) + IDLE: begin + // + // When idle we can always acknowledge the invalidate as it + // has the highest priority in handling. When something is + // changed on the state machine handling above this needs + // to be changed. + // + invalidate_ack = 1'b1; + end + + READ: begin + if (hit) begin + // + // We got a hit. The LRU module gets the access + // information. Depending on this we update the LRU + // history in the tag. + // + access = way_hit; + + // This is the updated LRU history after hit + tag_lru_in = next_lru_history; + + tag_we = 1'b1; + end + end + + WRITE: begin + way_wr_dat = cpu_dat_i; + if (hit & cpu_req_i) begin + /* Mux cache output with write data */ + if (!cpu_bsel_i[3]) + way_wr_dat[31:24] = cpu_dat_o[31:24]; + if (!cpu_bsel_i[2]) + way_wr_dat[23:16] = cpu_dat_o[23:16]; + if (!cpu_bsel_i[1]) + way_wr_dat[15:8] = cpu_dat_o[15:8]; + if (!cpu_bsel_i[0]) + way_wr_dat[7:0] = cpu_dat_o[7:0]; + + way_we = way_hit; + + tag_lru_in = next_lru_history; + + tag_we = 1'b1; + end + end + + REFILL: begin + if (we_i) begin + // + // Write the data to the way that is replaced (which is + // the LRU) + // + way_we = tag_save_lru; + + // Access pattern + access = tag_save_lru; + + /* Invalidate the way on the first write */ + if (refill_valid == 0) begin + for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin + if (tag_save_lru[w2]) begin + tag_way_in[w2][TAGMEM_WAY_VALID] = 1'b0; + end + end + + tag_we = 1'b1; + end + + // + // After refill update the tag memory entry of the + // filled way with the LRU history, the tag and set + // valid to 1. + // + if (refill_done) begin + for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin + tag_way_in[w2] = tag_way_save[w2]; + if (tag_save_lru[w2]) begin + tag_way_in[w2] = { 1'b1, tag_wtag }; + end + end + tag_lru_in = next_lru_history; + + tag_we = 1'b1; + end + end + end + + INVALIDATE: begin + invalidate_ack = 1'b1; + + // Lazy invalidation, invalidate everything that matches tag address + tag_lru_in = 0; + for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin + tag_way_in[w2] = 0; + end + + tag_we = 1'b1; + end + + default: begin + end + endcase + end + end + + generate + for (i = 0; i < OPTION_DCACHE_WAYS; i=i+1) begin : way_memories + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH(WAY_WIDTH-2), + .DATA_WIDTH(OPTION_OPERAND_WIDTH), + .ENABLE_BYPASS(1) + ) + way_data_ram + ( + // Outputs + .dout (way_dout[i]), + // Inputs + .clk (clk), + .raddr (way_raddr[i][WAY_WIDTH-3:0]), + .re (1'b1), + .waddr (way_waddr[i][WAY_WIDTH-3:0]), + .we (way_we[i]), + .din (way_din[i][31:0])); + + end + + if (OPTION_DCACHE_WAYS >= 2) begin : gen_u_lru + /* mor1kx_cache_lru AUTO_TEMPLATE( + .current (current_lru_history), + .update (next_lru_history), + .lru_pre (lru), + .lru_post (), + .access (access), + ); */ + + mor1kx_cache_lru + #(.NUMWAYS(OPTION_DCACHE_WAYS)) + u_lru(/*AUTOINST*/ + // Outputs + .update (next_lru_history), // Templated + .lru_pre (lru), // Templated + .lru_post (), // Templated + // Inputs + .current (current_lru_history), // Templated + .access (access)); // Templated + end // if (OPTION_DCACHE_WAYS >= 2) + endgenerate + + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH(OPTION_DCACHE_SET_WIDTH), + .DATA_WIDTH(TAGMEM_WIDTH), + .ENABLE_BYPASS(OPTION_DCACHE_SNOOP != "NONE") + ) + tag_ram + ( + // Outputs + .dout (tag_dout[TAGMEM_WIDTH-1:0]), + // Inputs + .clk (clk), + .raddr (tag_rindex), + .re (1'b1), + .waddr (tag_windex), + .we (tag_we), + .din (tag_din)); + +generate +if (OPTION_DCACHE_SNOOP != "NONE") begin + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH(OPTION_DCACHE_SET_WIDTH), + .DATA_WIDTH(TAGMEM_WIDTH), + .ENABLE_BYPASS(1) + ) + snoop_tag_ram + ( + // Outputs + .dout (snoop_dout[TAGMEM_WIDTH-1:0]), + // Inputs + .clk (clk), + .raddr (snoop_index), + .re (1'b1), + .waddr (tag_windex), + .we (tag_we), + .din (tag_din)); +end +endgenerate + +endmodule diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode.v new file mode 100644 index 0000000..4df7646 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode.v @@ -0,0 +1,528 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx decode unit + + Completely combinatorial. + + Outputs: + - ALU operation + - indication of other type of op - LSU/SPR + - immediates + - register file addresses + - exception decodes: illegal, system call + + Copyright (C) 2012 Julius Baxter + Copyright (C) 2013 Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_decode + #( + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + parameter OPTION_RF_ADDR_WIDTH = 5, + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_RANGE = "ENABLED", + parameter FEATURE_MAC = "NONE", + parameter FEATURE_MULTIPLIER = "PARALLEL", + parameter FEATURE_DIVIDER = "NONE", + + parameter FEATURE_ADDC = "NONE", + parameter FEATURE_SRA = "ENABLED", + parameter FEATURE_ROR = "NONE", + parameter FEATURE_EXT = "NONE", + parameter FEATURE_CMOV = "NONE", + parameter FEATURE_FFL1 = "NONE", + parameter FEATURE_ATOMIC = "ENABLED", + parameter FEATURE_MSYNC = "ENABLED", + parameter FEATURE_PSYNC = "NONE", + parameter FEATURE_CSYNC = "NONE", + + parameter FEATURE_FPU = "NONE", // ENABLED|NONE + + parameter FEATURE_CUST1 = "NONE", + parameter FEATURE_CUST2 = "NONE", + parameter FEATURE_CUST3 = "NONE", + parameter FEATURE_CUST4 = "NONE", + parameter FEATURE_CUST5 = "NONE", + parameter FEATURE_CUST6 = "NONE", + parameter FEATURE_CUST7 = "NONE", + parameter FEATURE_CUST8 = "NONE" + ) + ( + input clk, + input rst, + + // input from fetch stage + input [`OR1K_INSN_WIDTH-1:0] decode_insn_i, + + // ALU opcodes + output [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_o, + output [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_o, + + output [`OR1K_IMM_WIDTH-1:0] decode_imm16_o, + output [OPTION_OPERAND_WIDTH-1:0] decode_immediate_o, + output decode_immediate_sel_o, + + // Upper 10 bits of immediate for jumps and branches + output [9:0] decode_immjbr_upper_o, + + // GPR numbers + output [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_o, + output [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_o, + output [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_o, + + output decode_rf_wb_o, + + output decode_op_jbr_o, + output decode_op_jr_o, + output decode_op_jal_o, + output decode_op_bf_o, + output decode_op_bnf_o, + output decode_op_brcond_o, + output decode_op_branch_o, + + output decode_op_alu_o, + + output decode_op_lsu_load_o, + output decode_op_lsu_store_o, + output decode_op_lsu_atomic_o, + output reg [1:0] decode_lsu_length_o, + output decode_lsu_zext_o, + + output decode_op_mfspr_o, + output decode_op_mtspr_o, + + output decode_op_rfe_o, + output decode_op_setflag_o, + output decode_op_add_o, + output decode_op_mul_o, + output decode_op_mul_signed_o, + output decode_op_mul_unsigned_o, + output decode_op_div_o, + output decode_op_div_signed_o, + output decode_op_div_unsigned_o, + output decode_op_shift_o, + output decode_op_ffl1_o, + output decode_op_movhi_o, + + // Sync operations + output decode_op_msync_o, + output [`OR1K_FPUOP_WIDTH-1:0] decode_op_fpu_o, + + + // Adder control logic + output decode_adder_do_sub_o, + output decode_adder_do_carry_o, + + // exception output - + output reg decode_except_illegal_o, + output decode_except_syscall_o, + output decode_except_trap_o, + + output [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_o + ); + + wire [`OR1K_OPCODE_WIDTH-1:0] opc_insn; + wire [`OR1K_ALU_OPC_WIDTH-1:0] opc_alu; + + wire [OPTION_OPERAND_WIDTH-1:0] imm_sext; + wire imm_sext_sel; + wire [OPTION_OPERAND_WIDTH-1:0] imm_zext; + wire imm_zext_sel; + wire [OPTION_OPERAND_WIDTH-1:0] imm_high; + wire imm_high_sel; + + wire decode_except_ibus_align; + + // Insn opcode + assign opc_insn = decode_insn_i[`OR1K_OPCODE_SELECT]; + assign decode_opc_insn_o = opc_insn; + + // load opcodes are 6'b10_0000 to 6'b10_0110, 0 to 6, so check for 7 and up + assign decode_op_lsu_load_o = (decode_insn_i[31:30] == 2'b10) & + !(&decode_insn_i[28:26]) & + !decode_insn_i[29] || + ((opc_insn == `OR1K_OPCODE_LWA) & + (FEATURE_ATOMIC!="NONE")); + + // Detect when instruction is store + assign decode_op_lsu_store_o = (opc_insn == `OR1K_OPCODE_SW) || + (opc_insn == `OR1K_OPCODE_SB) || + (opc_insn == `OR1K_OPCODE_SH) || + ((opc_insn == `OR1K_OPCODE_SWA) & + (FEATURE_ATOMIC!="NONE")); + + assign decode_op_lsu_atomic_o = ((opc_insn == `OR1K_OPCODE_LWA) || + (opc_insn == `OR1K_OPCODE_SWA)) & + (FEATURE_ATOMIC!="NONE"); + + // Decode length of load/store operation + always @(*) + case (opc_insn) + `OR1K_OPCODE_SB, + `OR1K_OPCODE_LBZ, + `OR1K_OPCODE_LBS: + decode_lsu_length_o = 2'b00; + + `OR1K_OPCODE_SH, + `OR1K_OPCODE_LHZ, + `OR1K_OPCODE_LHS: + decode_lsu_length_o = 2'b01; + + `OR1K_OPCODE_SW, + `OR1K_OPCODE_SWA, + `OR1K_OPCODE_LWZ, + `OR1K_OPCODE_LWS, + `OR1K_OPCODE_LWA: + decode_lsu_length_o = 2'b10; + + default: + decode_lsu_length_o = 2'b10; + endcase + + assign decode_lsu_zext_o = opc_insn[0]; + + assign decode_op_msync_o = FEATURE_MSYNC!="NONE" && + opc_insn == `OR1K_OPCODE_SYSTRAPSYNC && + decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_MSYNC; + + assign decode_op_mtspr_o = opc_insn == `OR1K_OPCODE_MTSPR; + + // Detect when setflag instruction + assign decode_op_setflag_o = opc_insn == `OR1K_OPCODE_SF || + opc_insn == `OR1K_OPCODE_SFIMM; + + assign decode_op_alu_o = opc_insn == `OR1K_OPCODE_ALU || + opc_insn == `OR1K_OPCODE_ORI || + opc_insn == `OR1K_OPCODE_ANDI || + opc_insn == `OR1K_OPCODE_XORI; + + // Bottom 4 opcodes branch against an immediate + assign decode_op_jbr_o = opc_insn < `OR1K_OPCODE_NOP; + + assign decode_op_jr_o = opc_insn == `OR1K_OPCODE_JR | + opc_insn == `OR1K_OPCODE_JALR; + + assign decode_op_jal_o = opc_insn == `OR1K_OPCODE_JALR | + opc_insn == `OR1K_OPCODE_JAL; + + assign decode_op_bf_o = opc_insn == `OR1K_OPCODE_BF; + assign decode_op_bnf_o = opc_insn == `OR1K_OPCODE_BNF; + assign decode_op_brcond_o = decode_op_bf_o | decode_op_bnf_o; + + // All branch instructions combined + assign decode_op_branch_o = decode_op_jbr_o | + decode_op_jr_o | + decode_op_jal_o; + + assign decode_op_mfspr_o = opc_insn == `OR1K_OPCODE_MFSPR; + + assign decode_op_rfe_o = opc_insn == `OR1K_OPCODE_RFE; + + assign decode_op_add_o = (opc_insn == `OR1K_OPCODE_ALU && + (opc_alu == `OR1K_ALU_OPC_ADDC || + opc_alu == `OR1K_ALU_OPC_ADD || + opc_alu == `OR1K_ALU_OPC_SUB)) || + opc_insn == `OR1K_OPCODE_ADDIC || + opc_insn == `OR1K_OPCODE_ADDI; + + assign decode_op_mul_signed_o = (opc_insn == `OR1K_OPCODE_ALU && + opc_alu == `OR1K_ALU_OPC_MUL) || + opc_insn == `OR1K_OPCODE_MULI; + + assign decode_op_mul_unsigned_o = opc_insn == `OR1K_OPCODE_ALU && + opc_alu == `OR1K_ALU_OPC_MULU; + + assign decode_op_mul_o = decode_op_mul_signed_o | decode_op_mul_unsigned_o; + + assign decode_op_div_signed_o = opc_insn == `OR1K_OPCODE_ALU && + opc_alu == `OR1K_ALU_OPC_DIV; + + assign decode_op_div_unsigned_o = opc_insn == `OR1K_OPCODE_ALU && + opc_alu == `OR1K_ALU_OPC_DIVU; + + assign decode_op_div_o = decode_op_div_signed_o | decode_op_div_unsigned_o; + + assign decode_op_shift_o = opc_insn == `OR1K_OPCODE_ALU && + opc_alu == `OR1K_ALU_OPC_SHRT || + opc_insn == `OR1K_OPCODE_SHRTI; + + assign decode_op_ffl1_o = opc_insn == `OR1K_OPCODE_ALU && + opc_alu == `OR1K_ALU_OPC_FFL1; + + assign decode_op_movhi_o = opc_insn == `OR1K_OPCODE_MOVHI; + + // FPU related + generate + /* verilator lint_off WIDTH */ + if (FEATURE_FPU!="NONE") begin : fpu_decode_ena + /* verilator lint_on WIDTH */ + assign decode_op_fpu_o = { (opc_insn == `OR1K_OPCODE_FPU), + decode_insn_i[`OR1K_FPUOP_WIDTH-2:0] }; + end + else begin : fpu_decode_none + assign decode_op_fpu_o = {`OR1K_FPUOP_WIDTH{1'b0}}; + end + endgenerate // FPU related + + // Which instructions cause writeback? + assign decode_rf_wb_o = (opc_insn == `OR1K_OPCODE_JAL | + opc_insn == `OR1K_OPCODE_MOVHI | + opc_insn == `OR1K_OPCODE_JALR | + opc_insn == `OR1K_OPCODE_LWA) | + // All '10????' opcodes except l.sfxxi + (decode_insn_i[31:30] == 2'b10 & + !(opc_insn == `OR1K_OPCODE_SFIMM)) | + // All '11????' opcodes except l.sfxx and l.mtspr + (decode_insn_i[31:30] == 2'b11 & + !(opc_insn == `OR1K_OPCODE_SF | + decode_op_mtspr_o | decode_op_lsu_store_o)); + + // Register file addresses + assign decode_rfa_adr_o = decode_insn_i[`OR1K_RA_SELECT]; + assign decode_rfb_adr_o = decode_insn_i[`OR1K_RB_SELECT]; + + assign decode_rfd_adr_o = decode_op_jal_o ? 9 : + decode_insn_i[`OR1K_RD_SELECT]; + + // Immediate in l.mtspr is broken up, reassemble + assign decode_imm16_o = (decode_op_mtspr_o | decode_op_lsu_store_o) ? + {decode_insn_i[25:21],decode_insn_i[10:0]} : + decode_insn_i[`OR1K_IMM_SELECT]; + + + // Upper 10 bits for jump/branch instructions + assign decode_immjbr_upper_o = decode_insn_i[25:16]; + + assign imm_sext = {{16{decode_imm16_o[15]}}, decode_imm16_o[15:0]}; + assign imm_sext_sel = ((opc_insn[5:4] == 2'b10) & + ~(opc_insn == `OR1K_OPCODE_ORI) & + ~(opc_insn == `OR1K_OPCODE_ANDI)) | + (opc_insn == `OR1K_OPCODE_SWA) | + (opc_insn == `OR1K_OPCODE_LWA) | + (opc_insn == `OR1K_OPCODE_SW) | + (opc_insn == `OR1K_OPCODE_SH) | + (opc_insn == `OR1K_OPCODE_SB); + + assign imm_zext = {{16{1'b0}}, decode_imm16_o[15:0]}; + assign imm_zext_sel = ((opc_insn[5:4] == 2'b10) & + ((opc_insn == `OR1K_OPCODE_ORI) | + (opc_insn == `OR1K_OPCODE_ANDI))) | + (opc_insn == `OR1K_OPCODE_MTSPR); + + assign imm_high = {decode_imm16_o, 16'd0}; + assign imm_high_sel = decode_op_movhi_o; + + assign decode_immediate_o = imm_sext_sel ? imm_sext : + imm_zext_sel ? imm_zext : imm_high; + + assign decode_immediate_sel_o = imm_sext_sel | imm_zext_sel | imm_high_sel; + + // ALU opcode + assign opc_alu = decode_insn_i[`OR1K_ALU_OPC_SELECT]; + assign decode_opc_alu_o = opc_insn == `OR1K_OPCODE_ORI ? `OR1K_ALU_OPC_OR : + opc_insn == `OR1K_OPCODE_ANDI ? `OR1K_ALU_OPC_AND : + opc_insn == `OR1K_OPCODE_XORI ? `OR1K_ALU_OPC_XOR : + opc_alu; + + assign decode_opc_alu_secondary_o = decode_op_setflag_o ? + decode_insn_i[`OR1K_COMP_OPC_SELECT]: + {1'b0, + decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]}; + + assign decode_except_syscall_o = opc_insn == `OR1K_OPCODE_SYSTRAPSYNC && + decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_SYSCALL; + + assign decode_except_trap_o = opc_insn == `OR1K_OPCODE_SYSTRAPSYNC && + decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_TRAP; + + // Illegal instruction decode + always @* + case (opc_insn) + `OR1K_OPCODE_J, + `OR1K_OPCODE_JAL, + `OR1K_OPCODE_BNF, + `OR1K_OPCODE_BF, + `OR1K_OPCODE_MOVHI, + `OR1K_OPCODE_RFE, + `OR1K_OPCODE_JR, + `OR1K_OPCODE_JALR, + `OR1K_OPCODE_LWZ, + `OR1K_OPCODE_LWS, + `OR1K_OPCODE_LBZ, + `OR1K_OPCODE_LBS, + `OR1K_OPCODE_LHZ, + `OR1K_OPCODE_LHS, + `OR1K_OPCODE_ADDI, + `OR1K_OPCODE_ANDI, + `OR1K_OPCODE_ORI, + `OR1K_OPCODE_XORI, + `OR1K_OPCODE_MFSPR, + /* + `OR1K_OPCODE_SLLI, + `OR1K_OPCODE_SRLI, + `OR1K_OPCODE_SRAI, + `OR1K_OPCODE_RORI, + */ + `OR1K_OPCODE_SFIMM, + `OR1K_OPCODE_MTSPR, + `OR1K_OPCODE_SW, + `OR1K_OPCODE_SB, + `OR1K_OPCODE_SH, + /* + `OR1K_OPCODE_SFEQ, + `OR1K_OPCODE_SFNE, + `OR1K_OPCODE_SFGTU, + `OR1K_OPCODE_SFGEU, + `OR1K_OPCODE_SFLTU, + `OR1K_OPCODE_SFLEU, + `OR1K_OPCODE_SFGTS, + `OR1K_OPCODE_SFGES, + `OR1K_OPCODE_SFLTS, + `OR1K_OPCODE_SFLES, + */ + `OR1K_OPCODE_SF, + `OR1K_OPCODE_NOP: + decode_except_illegal_o = 1'b0; + + `OR1K_OPCODE_SWA, + `OR1K_OPCODE_LWA: + decode_except_illegal_o = (FEATURE_ATOMIC=="NONE"); + + `OR1K_OPCODE_CUST1: + decode_except_illegal_o = (FEATURE_CUST1=="NONE"); + `OR1K_OPCODE_CUST2: + decode_except_illegal_o = (FEATURE_CUST2=="NONE"); + `OR1K_OPCODE_CUST3: + decode_except_illegal_o = (FEATURE_CUST3=="NONE"); + `OR1K_OPCODE_CUST4: + decode_except_illegal_o = (FEATURE_CUST4=="NONE"); + `OR1K_OPCODE_CUST5: + decode_except_illegal_o = (FEATURE_CUST5=="NONE"); + `OR1K_OPCODE_CUST6: + decode_except_illegal_o = (FEATURE_CUST6=="NONE"); + `OR1K_OPCODE_CUST7: + decode_except_illegal_o = (FEATURE_CUST7=="NONE"); + `OR1K_OPCODE_CUST8: + decode_except_illegal_o = (FEATURE_CUST8=="NONE"); + `OR1K_OPCODE_FPU: + decode_except_illegal_o = (FEATURE_FPU=="NONE"); + + `OR1K_OPCODE_LD, + `OR1K_OPCODE_SD: + decode_except_illegal_o = !(OPTION_OPERAND_WIDTH==64); + + `OR1K_OPCODE_ADDIC: + decode_except_illegal_o = (FEATURE_ADDC=="NONE"); + + //`OR1K_OPCODE_MACRC, // Same as movhi - check! + `OR1K_OPCODE_MACI, + `OR1K_OPCODE_MAC: + decode_except_illegal_o = (FEATURE_MAC=="NONE"); + + `OR1K_OPCODE_MULI: + decode_except_illegal_o = (FEATURE_MULTIPLIER=="NONE"); + + `OR1K_OPCODE_SHRTI: + case(decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]) + `OR1K_ALU_OPC_SECONDARY_SHRT_SLL, + `OR1K_ALU_OPC_SECONDARY_SHRT_SRL: + decode_except_illegal_o = 1'b0; + `OR1K_ALU_OPC_SECONDARY_SHRT_SRA: + decode_except_illegal_o = (FEATURE_SRA=="NONE"); + + `OR1K_ALU_OPC_SECONDARY_SHRT_ROR: + decode_except_illegal_o = (FEATURE_ROR=="NONE"); + default: + decode_except_illegal_o = 1'b1; + endcase // case (decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]) + + `OR1K_OPCODE_ALU: + case(decode_insn_i[`OR1K_ALU_OPC_SELECT]) + `OR1K_ALU_OPC_ADD, + `OR1K_ALU_OPC_SUB, + `OR1K_ALU_OPC_OR, + `OR1K_ALU_OPC_XOR, + `OR1K_ALU_OPC_AND: + decode_except_illegal_o = 1'b0; + `OR1K_ALU_OPC_CMOV: + decode_except_illegal_o = (FEATURE_CMOV=="NONE"); + `OR1K_ALU_OPC_FFL1: + decode_except_illegal_o = (FEATURE_FFL1=="NONE"); + `OR1K_ALU_OPC_DIV, + `OR1K_ALU_OPC_DIVU: + decode_except_illegal_o = (FEATURE_DIVIDER=="NONE"); + `OR1K_ALU_OPC_ADDC: + decode_except_illegal_o = (FEATURE_ADDC=="NONE"); + `OR1K_ALU_OPC_MUL, + `OR1K_ALU_OPC_MULU: + decode_except_illegal_o = (FEATURE_MULTIPLIER=="NONE"); + `OR1K_ALU_OPC_EXTBH, + `OR1K_ALU_OPC_EXTW: + decode_except_illegal_o = (FEATURE_EXT=="NONE"); + `OR1K_ALU_OPC_SHRT: + case(decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]) + `OR1K_ALU_OPC_SECONDARY_SHRT_SLL, + `OR1K_ALU_OPC_SECONDARY_SHRT_SRL: + decode_except_illegal_o = 1'b0; + `OR1K_ALU_OPC_SECONDARY_SHRT_SRA: + decode_except_illegal_o = (FEATURE_SRA=="NONE"); + `OR1K_ALU_OPC_SECONDARY_SHRT_ROR: + decode_except_illegal_o = (FEATURE_ROR=="NONE"); + default: + decode_except_illegal_o = 1'b1; + endcase // case (decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]) + default: + decode_except_illegal_o = 1'b1; + endcase // case (decode_insn_i[`OR1K_ALU_OPC_SELECT]) + + `OR1K_OPCODE_SYSTRAPSYNC: begin + if ((decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_SYSCALL && + FEATURE_SYSCALL=="ENABLED") || + (decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_TRAP && + FEATURE_TRAP=="ENABLED") || + (decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_MSYNC) || + (decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_PSYNC && + FEATURE_PSYNC!="NONE") || + (decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] == + `OR1K_SYSTRAPSYNC_OPC_CSYNC && + FEATURE_CSYNC!="NONE")) + decode_except_illegal_o = 1'b0; + else + decode_except_illegal_o = 1'b1; + end // case: endcase... + default: + decode_except_illegal_o = 1'b1; + + endcase // case (decode_insn_i[`OR1K_OPCODE_SELECT]) + + // Adder control logic + // Subtract when comparing to check if equal + assign decode_adder_do_sub_o = (opc_insn == `OR1K_OPCODE_ALU & + opc_alu == `OR1K_ALU_OPC_SUB) | + decode_op_setflag_o; + + // Generate carry-in select + assign decode_adder_do_carry_o = (FEATURE_ADDC!="NONE") && + ((opc_insn == `OR1K_OPCODE_ALU & + opc_alu == `OR1K_ALU_OPC_ADDC) || + (opc_insn == `OR1K_OPCODE_ADDIC)); + +endmodule // mor1kx_decode diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode_execute_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode_execute_cappuccino.v new file mode 100644 index 0000000..beadc5d --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode_execute_cappuccino.v @@ -0,0 +1,579 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Cappuccino decode to execute module. + - Decode to execute stage signal passing. + - Branches are resolved (in decode stage). + - Hazards that can not be resolved by bypassing are detected and + bubbles are inserted on such conditions. + + Generate valid signal when stage is done. + + Copyright (C) 2012 Julius Baxter + Copyright (C) 2013 Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_decode_execute_cappuccino + #( + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + + parameter OPTION_RF_ADDR_WIDTH = 5, + + parameter FEATURE_SYSCALL = "ENABLED", + parameter FEATURE_TRAP = "ENABLED", + parameter FEATURE_DELAY_SLOT = "ENABLED", + + parameter FEATURE_MULTIPLIER = "THREESTAGE", + + parameter FEATURE_FPU = "NONE", // ENABLED|NONE + + parameter FEATURE_INBUILT_CHECKERS = "ENABLED" + ) + ( + input clk, + input rst, + + // pipeline control signal in + input padv_i, + input [OPTION_OPERAND_WIDTH-1:0] pc_decode_i, + + // input from register file + input [OPTION_OPERAND_WIDTH-1:0] decode_rfb_i, + input [OPTION_OPERAND_WIDTH-1:0] execute_rfb_i, + + // Branch prediction signals + input predicted_flag_i, + output reg execute_predicted_flag_o, + // The target pc that should be used in case of branch misprediction + output reg [OPTION_OPERAND_WIDTH-1:0] execute_mispredict_target_o, + + input pipeline_flush_i, + + // ALU related inputs from decode + input [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_i, + input [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_i, + + input [`OR1K_IMM_WIDTH-1:0] decode_imm16_i, + input [OPTION_OPERAND_WIDTH-1:0] decode_immediate_i, + input decode_immediate_sel_i, + + // ALU related outputs to execute + output reg [`OR1K_ALU_OPC_WIDTH-1:0] execute_opc_alu_o, + output reg [`OR1K_ALU_OPC_WIDTH-1:0] execute_opc_alu_secondary_o, + + output reg [`OR1K_IMM_WIDTH-1:0] execute_imm16_o, + output reg [OPTION_OPERAND_WIDTH-1:0] execute_immediate_o, + output reg execute_immediate_sel_o, + + // Adder control logic from decode + input decode_adder_do_sub_i, + input decode_adder_do_carry_i, + + // Adder control logic to execute + output reg execute_adder_do_sub_o, + output reg execute_adder_do_carry_o, + + // Upper 10 bits of immediate for jumps and branches + input [9:0] decode_immjbr_upper_i, + output reg [9:0] execute_immjbr_upper_o, + + // GPR numbers + output reg [OPTION_RF_ADDR_WIDTH-1:0] execute_rfd_adr_o, + input [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_i, + input [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_i, + input [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_i, + input [OPTION_RF_ADDR_WIDTH-1:0] ctrl_rfd_adr_i, + input ctrl_op_lsu_load_i, + input ctrl_op_mfspr_i, + input ctrl_op_mul_i, + + // Control signal inputs from decode stage + input decode_rf_wb_i, + + input decode_op_alu_i, + + input decode_op_setflag_i, + + input decode_op_jbr_i, + input decode_op_jr_i, + input decode_op_jal_i, + input decode_op_bf_i, + input decode_op_bnf_i, + input decode_op_brcond_i, + input decode_op_branch_i, + + input decode_op_lsu_load_i, + input decode_op_lsu_store_i, + input decode_op_lsu_atomic_i, + input [1:0] decode_lsu_length_i, + input decode_lsu_zext_i, + + input decode_op_mfspr_i, + input decode_op_mtspr_i, + + input decode_op_rfe_i, + input decode_op_add_i, + input decode_op_mul_i, + input decode_op_mul_signed_i, + input decode_op_mul_unsigned_i, + input decode_op_div_i, + input decode_op_div_signed_i, + input decode_op_div_unsigned_i, + input decode_op_shift_i, + input decode_op_ffl1_i, + input decode_op_movhi_i, + input decode_op_msync_i, + input [`OR1K_FPUOP_WIDTH-1:0] decode_op_fpu_i, + + input [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_i, + + // Control signal outputs to execute stage + output reg execute_rf_wb_o, + + output reg execute_op_alu_o, + + output reg execute_op_setflag_o, + + output reg execute_op_jbr_o, + output reg execute_op_jr_o, + output reg execute_op_jal_o, + output reg execute_op_brcond_o, + output reg execute_op_branch_o, + + output reg execute_op_lsu_load_o, + output reg execute_op_lsu_store_o, + output reg execute_op_lsu_atomic_o, + output reg [1:0] execute_lsu_length_o, + output reg execute_lsu_zext_o, + + output reg execute_op_mfspr_o, + output reg execute_op_mtspr_o, + + output reg execute_op_rfe_o, + output reg execute_op_add_o, + output reg execute_op_mul_o, + output reg execute_op_mul_signed_o, + output reg execute_op_mul_unsigned_o, + output reg execute_op_div_o, + output reg execute_op_div_signed_o, + output reg execute_op_div_unsigned_o, + output reg execute_op_shift_o, + output reg execute_op_ffl1_o, + output reg execute_op_movhi_o, + output reg execute_op_msync_o, + output [`OR1K_FPUOP_WIDTH-1:0] execute_op_fpu_o, + + output reg [OPTION_OPERAND_WIDTH-1:0] execute_jal_result_o, + + output reg [`OR1K_OPCODE_WIDTH-1:0] execute_opc_insn_o, + + // branch detection + output decode_branch_o, + output [OPTION_OPERAND_WIDTH-1:0] decode_branch_target_o, + + // exceptions in + input decode_except_ibus_err_i, + input decode_except_itlb_miss_i, + input decode_except_ipagefault_i, + input decode_except_illegal_i, + input decode_except_syscall_i, + input decode_except_trap_i, + + // exception output - + output reg execute_except_ibus_err_o, + output reg execute_except_itlb_miss_o, + output reg execute_except_ipagefault_o, + output reg execute_except_illegal_o, + output reg execute_except_ibus_align_o, + output reg execute_except_syscall_o, + output reg execute_except_trap_o, + + output reg [OPTION_OPERAND_WIDTH-1:0] pc_execute_o, + + // output is valid, signal + output reg decode_valid_o, + + output decode_bubble_o, + output reg execute_bubble_o + ); + + wire ctrl_to_decode_interlock; + wire branch_to_imm; + wire [OPTION_OPERAND_WIDTH-1:0] branch_to_imm_target; + wire branch_to_reg; + + wire decode_except_ibus_align; + + wire [OPTION_OPERAND_WIDTH-1:0] next_pc_after_branch_insn; + wire [OPTION_OPERAND_WIDTH-1:0] decode_mispredict_target; + + // Op control signals to execute stage + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + execute_op_alu_o <= 1'b0; + execute_op_add_o <= 1'b0; + execute_op_mul_o <= 1'b0; + execute_op_mul_signed_o <= 1'b0; + execute_op_mul_unsigned_o <= 1'b0; + execute_op_div_o <= 1'b0; + execute_op_div_signed_o <= 1'b0; + execute_op_div_unsigned_o <= 1'b0; + execute_op_shift_o <= 1'b0; + execute_op_ffl1_o <= 1'b0; + execute_op_movhi_o <= 1'b0; + execute_op_msync_o <= 1'b0; + execute_op_mfspr_o <= 1'b0; + execute_op_mtspr_o <= 1'b0; + execute_op_lsu_load_o <= 1'b0; + execute_op_lsu_store_o <= 1'b0; + execute_op_lsu_atomic_o <= 1'b0; + execute_op_setflag_o <= 1'b0; + execute_op_jbr_o <= 1'b0; + execute_op_jr_o <= 1'b0; + execute_op_jal_o <= 1'b0; + execute_op_brcond_o <= 1'b0; + execute_op_branch_o <= 0; + end else if (pipeline_flush_i) begin + execute_op_alu_o <= 1'b0; + execute_op_add_o <= 1'b0; + execute_op_mul_o <= 1'b0; + execute_op_mul_signed_o <= 1'b0; + execute_op_mul_unsigned_o <= 1'b0; + execute_op_div_o <= 1'b0; + execute_op_div_signed_o <= 1'b0; + execute_op_div_unsigned_o <= 1'b0; + execute_op_shift_o <= 1'b0; + execute_op_ffl1_o <= 1'b0; + execute_op_movhi_o <= 1'b0; + execute_op_msync_o <= 1'b0; + execute_op_lsu_load_o <= 1'b0; + execute_op_lsu_store_o <= 1'b0; + execute_op_lsu_atomic_o <= 1'b0; + execute_op_setflag_o <= 1'b0; + execute_op_jbr_o <= 1'b0; + execute_op_jr_o <= 1'b0; + execute_op_jal_o <= 1'b0; + execute_op_brcond_o <= 1'b0; + execute_op_branch_o <= 1'b0; + end else if (padv_i) begin + execute_op_alu_o <= decode_op_alu_i; + execute_op_add_o <= decode_op_add_i; + execute_op_mul_o <= decode_op_mul_i; + execute_op_mul_signed_o <= decode_op_mul_signed_i; + execute_op_mul_unsigned_o <= decode_op_mul_unsigned_i; + execute_op_div_o <= decode_op_div_i; + execute_op_div_signed_o <= decode_op_div_signed_i; + execute_op_div_unsigned_o <= decode_op_div_unsigned_i; + execute_op_shift_o <= decode_op_shift_i; + execute_op_ffl1_o <= decode_op_ffl1_i; + execute_op_movhi_o <= decode_op_movhi_i; + execute_op_msync_o <= decode_op_msync_i; + execute_op_mfspr_o <= decode_op_mfspr_i; + execute_op_mtspr_o <= decode_op_mtspr_i; + execute_op_lsu_load_o <= decode_op_lsu_load_i; + execute_op_lsu_store_o <= decode_op_lsu_store_i; + execute_op_lsu_atomic_o <= decode_op_lsu_atomic_i; + execute_op_setflag_o <= decode_op_setflag_i; + execute_op_jbr_o <= decode_op_jbr_i; + execute_op_jr_o <= decode_op_jr_i; + execute_op_jal_o <= decode_op_jal_i; + execute_op_brcond_o <= decode_op_brcond_i; + execute_op_branch_o <= decode_op_branch_i; + if (decode_bubble_o) begin + execute_op_alu_o <= 1'b0; + execute_op_add_o <= 1'b0; + execute_op_mul_o <= 1'b0; + execute_op_mul_signed_o <= 1'b0; + execute_op_mul_unsigned_o <= 1'b0; + execute_op_div_o <= 1'b0; + execute_op_div_signed_o <= 1'b0; + execute_op_div_unsigned_o <= 1'b0; + execute_op_shift_o <= 1'b0; + execute_op_ffl1_o <= 1'b0; + execute_op_movhi_o <= 1'b0; + execute_op_msync_o <= 1'b0; + execute_op_mtspr_o <= 1'b0; + execute_op_mfspr_o <= 1'b0; + execute_op_lsu_load_o <= 1'b0; + execute_op_lsu_store_o <= 1'b0; + execute_op_lsu_atomic_o <= 1'b0; + execute_op_setflag_o <= 1'b0; + execute_op_jbr_o <= 1'b0; + execute_op_jr_o <= 1'b0; + execute_op_jal_o <= 1'b0; + execute_op_brcond_o <= 1'b0; + execute_op_branch_o <= 1'b0; + end + end + + // FPU related + generate + /* verilator lint_off WIDTH */ + if (FEATURE_FPU!="NONE") begin : fpu_decode_execute_ena + /* verilator lint_on WIDTH */ + reg [`OR1K_FPUOP_WIDTH-1:0] execute_op_fpu_r; + assign execute_op_fpu_o = execute_op_fpu_r; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + execute_op_fpu_r <= {`OR1K_FPUOP_WIDTH{1'b0}}; + else if (pipeline_flush_i) + execute_op_fpu_r <= {`OR1K_FPUOP_WIDTH{1'b0}}; + else if (padv_i) + execute_op_fpu_r <= (decode_bubble_o ? + {`OR1K_FPUOP_WIDTH{1'b0}} : decode_op_fpu_i); + end // @clk + end + else begin : fpu_decode_execute_none + assign execute_op_fpu_o = {`OR1K_FPUOP_WIDTH{1'b0}}; + end + endgenerate // FPU related + + // rfe is a special case, instead of pushing the pipeline full + // of nops on a decode_bubble_o, we push it full of rfes. + // The reason for this is that we need the rfe to reach control + // stage so it will cause the branch. + // It will clear itself by the pipeline_flush_i that the rfe + // will generate. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_op_rfe_o <= 0; + else if (pipeline_flush_i) + execute_op_rfe_o <= 0; + else if (padv_i) + execute_op_rfe_o <= decode_op_rfe_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + execute_rf_wb_o <= 0; + end else if (pipeline_flush_i) begin + execute_rf_wb_o <= 0; + end else if (padv_i) begin + execute_rf_wb_o <= decode_rf_wb_i; + if (decode_bubble_o) + execute_rf_wb_o <= 0; + end + + always @(posedge clk) + if (padv_i) + execute_rfd_adr_o <= decode_rfd_adr_i; + + always @(posedge clk) + if (padv_i) begin + execute_lsu_length_o <= decode_lsu_length_i; + execute_lsu_zext_o <= decode_lsu_zext_i; + end + + always @(posedge clk) + if (padv_i) begin + execute_imm16_o <= decode_imm16_i; + execute_immediate_o <= decode_immediate_i; + execute_immediate_sel_o <= decode_immediate_sel_i; + end + + always @(posedge clk) + if (padv_i ) + execute_immjbr_upper_o <= decode_immjbr_upper_i; + + always @(posedge clk) + if (padv_i) begin + execute_opc_alu_o <= decode_opc_alu_i; + execute_opc_alu_secondary_o <= decode_opc_alu_secondary_i; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + execute_opc_insn_o <= `OR1K_OPCODE_NOP; + end else if (pipeline_flush_i) begin + execute_opc_insn_o <= `OR1K_OPCODE_NOP; + end else if (padv_i) begin + execute_opc_insn_o <= decode_opc_insn_i; + if (decode_bubble_o) + execute_opc_insn_o <= `OR1K_OPCODE_NOP; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + execute_adder_do_sub_o <= 1'b0; + execute_adder_do_carry_o <= 1'b0; + end else if (pipeline_flush_i) begin + execute_adder_do_sub_o <= 1'b0; + execute_adder_do_carry_o <= 1'b0; + end else if (padv_i) begin + execute_adder_do_sub_o <= decode_adder_do_sub_i; + execute_adder_do_carry_o <= decode_adder_do_carry_i; + if (decode_bubble_o) begin + execute_adder_do_sub_o <= 1'b0; + execute_adder_do_carry_o <= 1'b0; + end + end + + // Decode for system call exception + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_except_syscall_o <= 0; + else if (padv_i && FEATURE_SYSCALL=="ENABLED") + execute_except_syscall_o <= decode_except_syscall_i; + + // Decode for system call exception + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_except_trap_o <= 0; + else if (padv_i && FEATURE_TRAP=="ENABLED") + execute_except_trap_o <= decode_except_trap_i; + + // Decode Illegal instruction + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_except_illegal_o <= 0; + else if (padv_i) + execute_except_illegal_o <= decode_except_illegal_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_except_ibus_err_o <= 1'b0; + else if (padv_i) + execute_except_ibus_err_o <= decode_except_ibus_err_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_except_itlb_miss_o <= 1'b0; + else if (padv_i) + execute_except_itlb_miss_o <= decode_except_itlb_miss_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_except_ipagefault_o <= 1'b0; + else if (padv_i) + execute_except_ipagefault_o <= decode_except_ipagefault_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_except_ibus_align_o <= 1'b0; + else if (padv_i) + execute_except_ibus_align_o <= decode_except_ibus_align; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_valid_o <= 0; + else + decode_valid_o <= padv_i; + + always @(posedge clk `OR_ASYNC_RST) + if (padv_i) + pc_execute_o <= pc_decode_i; + + // Branch detection + assign ctrl_to_decode_interlock = (ctrl_op_lsu_load_i | ctrl_op_mfspr_i | + ctrl_op_mul_i & + FEATURE_MULTIPLIER=="PIPELINED") & + ((decode_rfa_adr_i == ctrl_rfd_adr_i) || + (decode_rfb_adr_i == ctrl_rfd_adr_i)); + + assign branch_to_imm = (decode_op_jbr_i & + // l.j/l.jal + (!(|decode_opc_insn_i[2:1]) | + // l.bf/bnf and flag is right + (decode_opc_insn_i[2] == predicted_flag_i))); + + assign branch_to_imm_target = pc_decode_i + {{4{decode_immjbr_upper_i[9]}}, + decode_immjbr_upper_i, + decode_imm16_i,2'b00}; + assign branch_to_reg = decode_op_jr_i & + !(ctrl_to_decode_interlock | + execute_rf_wb_o & + (decode_rfb_adr_i == execute_rfd_adr_o)); + + assign decode_branch_o = (branch_to_imm | branch_to_reg) & + !pipeline_flush_i; + + assign decode_branch_target_o = branch_to_imm ? + branch_to_imm_target : + // If a bubble have been pushed out to get + // the instruction that will write the + // branch target to control stage, then we + // need to use the register result from + // execute stage instead of decode stage. + execute_bubble_o | execute_op_jr_o ? + execute_rfb_i : decode_rfb_i; + + assign decode_except_ibus_align = decode_branch_o & + (|decode_branch_target_o[1:0]); + + assign next_pc_after_branch_insn = FEATURE_DELAY_SLOT == "ENABLED" ? + pc_decode_i + 8 : pc_decode_i + 4; + + assign decode_mispredict_target = decode_op_bf_i & !predicted_flag_i | + decode_op_bnf_i & predicted_flag_i ? + branch_to_imm_target : + next_pc_after_branch_insn; + + // Forward branch prediction signals to execute stage + always @(posedge clk) + if (padv_i & decode_op_brcond_i) + execute_mispredict_target_o <= decode_mispredict_target; + + always @(posedge clk) + if (padv_i & decode_op_brcond_i) + execute_predicted_flag_o <= predicted_flag_i; + + // Calculate the link register result + // TODO: investigate if the ALU adder can be used for this without + // introducing critical paths + always @(posedge clk) + if (padv_i) + execute_jal_result_o <= next_pc_after_branch_insn; + + // Detect the situation where there is an instruction in execute stage + // that will produce it's result in control stage (i.e. load and mfspr), + // and an instruction currently in decode stage needing it's result as + // input in execute stage. + // Also detect the situation where there is a jump to register in decode + // stage and an instruction in execute stage that will write to that + // register. + // + // A bubble is also inserted when an rfe instruction is in decode stage, + // the main purpose of this is to stall fetch while the rfe is propagating + // up to ctrl stage. + + assign decode_bubble_o = ( + // load/mfspr/mul + (execute_op_lsu_load_o | execute_op_mfspr_o | + execute_op_mul_o & + FEATURE_MULTIPLIER=="PIPELINED") & + (decode_rfa_adr_i == execute_rfd_adr_o || + decode_rfb_adr_i == execute_rfd_adr_o) | + // mul + FEATURE_MULTIPLIER=="PIPELINED" & + (decode_op_mul_i & + (ctrl_to_decode_interlock | + execute_rf_wb_o & + (decode_rfa_adr_i == execute_rfd_adr_o || + decode_rfb_adr_i == execute_rfd_adr_o))) | + // jr + decode_op_jr_i & + (ctrl_to_decode_interlock | + execute_rf_wb_o & + (decode_rfb_adr_i == execute_rfd_adr_o)) | + // atomic store + execute_op_lsu_store_o & execute_op_lsu_atomic_o | + // rfe + decode_op_rfe_i + ) & padv_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_bubble_o <= 0; + else if (pipeline_flush_i) + execute_bubble_o <= 0; + else if (padv_i) + execute_bubble_o <= decode_bubble_o; + +endmodule // mor1kx_decode_execute_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dmmu.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dmmu.v new file mode 100644 index 0000000..308ecc9 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dmmu.v @@ -0,0 +1,450 @@ +/****************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Data MMU implementation + + Copyright (C) 2013 Stefan Kristiansson + + ******************************************************************************/ + +`include "mor1kx-defines.v" + +module mor1kx_dmmu + #( + parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_DMMU_SET_WIDTH = 6, + parameter OPTION_DMMU_WAYS = 1 + ) + ( + input clk, + input rst, + + input enable_i, + input [OPTION_OPERAND_WIDTH-1:0] virt_addr_i, + input [OPTION_OPERAND_WIDTH-1:0] virt_addr_match_i, + output reg [OPTION_OPERAND_WIDTH-1:0] phys_addr_o, + output reg cache_inhibit_o, + + input op_store_i, + input op_load_i, + input supervisor_mode_i, + + output reg tlb_miss_o, + output pagefault_o, + + output reg tlb_reload_req_o, + output tlb_reload_busy_o, + input tlb_reload_ack_i, + output reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr_o, + input [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data_i, + output tlb_reload_pagefault_o, + input tlb_reload_pagefault_clear_i, + + // SPR interface + input [15:0] spr_bus_addr_i, + input spr_bus_we_i, + input spr_bus_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i, + + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + output spr_bus_ack_o + ); + + wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_dout[OPTION_DMMU_WAYS-1:0]; + wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_match_addr; + reg [OPTION_DMMU_WAYS-1:0] dtlb_match_we; + wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_din; + + wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_huge_dout[OPTION_DMMU_WAYS-1:0]; + wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_match_huge_addr; + wire dtlb_match_huge_we; + + wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_dout[OPTION_DMMU_WAYS-1:0]; + wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_trans_addr; + reg [OPTION_DMMU_WAYS-1:0] dtlb_trans_we; + wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_din; + + wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_huge_dout[OPTION_DMMU_WAYS-1:0]; + wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_trans_huge_addr; + wire dtlb_trans_huge_we; + + reg dtlb_match_reload_we; + reg [OPTION_OPERAND_WIDTH-1:0] dtlb_match_reload_din; + + reg dtlb_trans_reload_we; + reg [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_reload_din; + + wire dtlb_match_spr_cs; + reg dtlb_match_spr_cs_r; + wire dtlb_trans_spr_cs; + reg dtlb_trans_spr_cs_r; + + wire dmmucr_spr_cs; + reg dmmucr_spr_cs_r; + reg [OPTION_OPERAND_WIDTH-1:0] dmmucr; + + wire [1:0] spr_way_idx; + reg [1:0] spr_way_idx_r; + + wire [OPTION_DMMU_WAYS-1:0] way_huge; + + wire [OPTION_DMMU_WAYS-1:0] way_hit; + wire [OPTION_DMMU_WAYS-1:0] way_huge_hit; + + reg tlb_reload_pagefault; + reg tlb_reload_huge; + + // ure: user read enable + // uwe: user write enable + // sre: supervisor read enable + // swe: supervisor write enable + reg ure; + reg uwe; + reg sre; + reg swe; + + reg spr_bus_ack; + + genvar i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_bus_ack <= 0; + else if (spr_bus_stb_i & spr_bus_addr_i[15:11] == 5'd1) + spr_bus_ack <= 1; + else + spr_bus_ack <= 0; + + assign spr_bus_ack_o = spr_bus_ack & spr_bus_stb_i & + spr_bus_addr_i[15:11] == 5'd1; + +generate +for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : ways + assign way_huge[i] = &dtlb_match_huge_dout[i][1:0]; // huge & valid + + assign way_hit[i] = (dtlb_match_dout[i][31:13] == virt_addr_match_i[31:13]) & + dtlb_match_dout[i][0]; // valid bit + + assign way_huge_hit[i] = (dtlb_match_huge_dout[i][31:24] == + virt_addr_match_i[31:24]) & + dtlb_match_huge_dout[i][0]; +end +endgenerate + + integer j; + always @(*) begin + tlb_miss_o = !tlb_reload_pagefault; + phys_addr_o = virt_addr_match_i[23:0]; + ure = 0; + uwe = 0; + sre = 0; + swe = 0; + cache_inhibit_o = 0; + + for (j = 0; j < OPTION_DMMU_WAYS; j=j+1) begin + if (way_huge[j] & way_huge_hit[j] | !way_huge[j] & way_hit[j]) + tlb_miss_o = 0; + + if (way_huge[j] & way_huge_hit[j]) begin + phys_addr_o = {dtlb_trans_huge_dout[j][31:24], virt_addr_match_i[23:0]}; + ure = dtlb_trans_huge_dout[j][6]; + uwe = dtlb_trans_huge_dout[j][7]; + sre = dtlb_trans_huge_dout[j][8]; + swe = dtlb_trans_huge_dout[j][9]; + cache_inhibit_o = dtlb_trans_huge_dout[j][1]; + end else if (!way_huge[j] & way_hit[j])begin + phys_addr_o = {dtlb_trans_dout[j][31:13], virt_addr_match_i[12:0]}; + ure = dtlb_trans_dout[j][6]; + uwe = dtlb_trans_dout[j][7]; + sre = dtlb_trans_dout[j][8]; + swe = dtlb_trans_dout[j][9]; + cache_inhibit_o = dtlb_trans_dout[j][1]; + end + + dtlb_match_we[j] = 0; + if (dtlb_match_reload_we) + dtlb_match_we[j] = 1; + if (j == spr_way_idx) + dtlb_match_we[j] = dtlb_match_spr_cs & spr_bus_we_i; + + dtlb_trans_we[j] = 0; + if (dtlb_trans_reload_we) + dtlb_trans_we[j] = 1; + if (j == spr_way_idx) + dtlb_trans_we[j] = dtlb_trans_spr_cs & spr_bus_we_i; + end + end + + assign pagefault_o = (supervisor_mode_i ? + !swe & op_store_i || !sre & op_load_i : + !uwe & op_store_i || !ure & op_load_i) & + !tlb_reload_busy_o; + + assign spr_way_idx = {spr_bus_addr_i[10], spr_bus_addr_i[8]}; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + dtlb_match_spr_cs_r <= 0; + dtlb_trans_spr_cs_r <= 0; + dmmucr_spr_cs_r <= 0; + spr_way_idx_r <= 0; + end else begin + dtlb_match_spr_cs_r <= dtlb_match_spr_cs; + dtlb_trans_spr_cs_r <= dtlb_trans_spr_cs; + dmmucr_spr_cs_r <= dmmucr_spr_cs; + spr_way_idx_r <= spr_way_idx; + end + +generate /* verilator lint_off WIDTH */ +if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED") begin +/* verilator lint_on WIDTH */ + assign dmmucr_spr_cs = spr_bus_stb_i & + spr_bus_addr_i == `OR1K_SPR_DMMUCR_ADDR; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + dmmucr <= 0; + else if (dmmucr_spr_cs & spr_bus_we_i) + dmmucr <= spr_bus_dat_i; + +end else begin + assign dmmucr_spr_cs = 0; + always @(posedge clk) + dmmucr <= 0; +end +endgenerate + + assign dtlb_match_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd1) & + |spr_bus_addr_i[10:9] & !spr_bus_addr_i[7]; + assign dtlb_trans_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd1) & + |spr_bus_addr_i[10:9] & spr_bus_addr_i[7]; + + assign dtlb_match_addr = dtlb_match_spr_cs ? + spr_bus_addr_i[OPTION_DMMU_SET_WIDTH-1:0] : + virt_addr_i[13+(OPTION_DMMU_SET_WIDTH-1):13]; + assign dtlb_trans_addr = dtlb_trans_spr_cs ? + spr_bus_addr_i[OPTION_DMMU_SET_WIDTH-1:0] : + virt_addr_i[13+(OPTION_DMMU_SET_WIDTH-1):13]; + + assign dtlb_match_din = dtlb_match_reload_we ? dtlb_match_reload_din : + spr_bus_dat_i; + assign dtlb_trans_din = dtlb_trans_reload_we ? dtlb_trans_reload_din : + spr_bus_dat_i; + + assign dtlb_match_huge_addr = virt_addr_i[24+(OPTION_DMMU_SET_WIDTH-1):24]; + assign dtlb_trans_huge_addr = virt_addr_i[24+(OPTION_DMMU_SET_WIDTH-1):24]; + + assign dtlb_match_huge_we = dtlb_match_reload_we & tlb_reload_huge; + assign dtlb_trans_huge_we = dtlb_trans_reload_we & tlb_reload_huge; + + assign spr_bus_dat_o = dtlb_match_spr_cs_r ? dtlb_match_dout[spr_way_idx_r] : + dtlb_trans_spr_cs_r ? dtlb_trans_dout[spr_way_idx_r] : + dmmucr_spr_cs_r ? dmmucr : 0; + + localparam TLB_IDLE = 2'd0; + localparam TLB_GET_PTE_POINTER = 2'd1; + localparam TLB_GET_PTE = 2'd2; + localparam TLB_READ = 2'd3; + +generate /* verilator lint_off WIDTH */ +if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED") begin + /* verilator lint_on WIDTH */ + + // Hardware TLB reload + // Compliant with the suggestion outlined in this thread: + // http://lists.openrisc.net/pipermail/openrisc/2013-July/001806.html + // + // PTE layout: + // | 31 ... 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + // | PPN | Reserved |PRESENT| L | X | W | U | D | A |WOM|WBC|CI |CC | + // + // Where X/W/U maps into SWE/SRE/UWE/URE like this: + // X | W | U SWE | SRE | UWE | URE + // ---------- --------------------- + // x | 0 | 0 = 0 | 1 | 0 | 0 + // x | 0 | 1 = 0 | 1 | 0 | 1 + // x | 1 | 0 = 1 | 1 | 0 | 0 + // x | 1 | 1 = 1 | 1 | 1 | 1 + + + + reg [1:0] tlb_reload_state = TLB_IDLE; + wire do_reload; + + assign do_reload = enable_i & tlb_miss_o & (dmmucr[31:10] != 0) & + (op_load_i | op_store_i); + + assign tlb_reload_busy_o = enable_i & (tlb_reload_state != TLB_IDLE) | do_reload; + + assign tlb_reload_pagefault_o = tlb_reload_pagefault & + !tlb_reload_pagefault_clear_i; + + always @(posedge clk) begin + if (tlb_reload_pagefault_clear_i) + tlb_reload_pagefault <= 0; + dtlb_trans_reload_we <= 0; + dtlb_trans_reload_din <= 0; + dtlb_match_reload_we <= 0; + dtlb_match_reload_din <= 0; + + case (tlb_reload_state) + TLB_IDLE: begin + tlb_reload_huge <= 0; + tlb_reload_req_o <= 0; + if (do_reload) begin + tlb_reload_req_o <= 1; + tlb_reload_addr_o <= {dmmucr[31:10], + virt_addr_match_i[31:24], 2'b00}; + tlb_reload_state <= TLB_GET_PTE_POINTER; + end + end + + // + // Here we get the pointer to the PTE table, next is to fetch + // the actual pte from the offset in the table. + // The offset is calculated by: + // ((virt_addr_match >> PAGE_BITS) & (PTE_CNT-1)) << 2 + // Where PAGE_BITS is 13 (8 kb page) and PTE_CNT is 2048 + // (number of PTEs in the PTE table) + // + TLB_GET_PTE_POINTER: begin + tlb_reload_huge <= 0; + if (tlb_reload_ack_i) begin + if (tlb_reload_data_i[31:13] == 0) begin + tlb_reload_pagefault <= 1; + tlb_reload_req_o <= 0; + tlb_reload_state <= TLB_IDLE; + end else if (tlb_reload_data_i[9]) begin + tlb_reload_huge <= 1; + tlb_reload_req_o <= 0; + tlb_reload_state <= TLB_GET_PTE; + end else begin + tlb_reload_addr_o <= {tlb_reload_data_i[31:13], + virt_addr_match_i[23:13], 2'b00}; + tlb_reload_state <= TLB_GET_PTE; + end + end + end + + // + // Here we get the actual PTE, left to do is to translate the + // PTE data into our translate and match registers. + // + TLB_GET_PTE: begin + if (tlb_reload_ack_i) begin + tlb_reload_req_o <= 0; + // Check PRESENT bit + if (!tlb_reload_data_i[10]) begin + tlb_reload_pagefault <= 1; + tlb_reload_state <= TLB_IDLE; + end else begin + // Translate register generation. + // PPN + dtlb_trans_reload_din[31:13] <= tlb_reload_data_i[31:13]; + // SWE = W + dtlb_trans_reload_din[9] <= tlb_reload_data_i[7]; + // SRE = 1 + dtlb_trans_reload_din[8] <= 1'b1; + // UWE = W & U + dtlb_trans_reload_din[7] <= tlb_reload_data_i[7] & + tlb_reload_data_i[6]; + // URE = U + dtlb_trans_reload_din[6] <= tlb_reload_data_i[6]; + // Dirty, Accessed, Weakly-Ordered-Memory, Writeback cache, + // Cache inhibit, Cache coherent + dtlb_trans_reload_din[5:0] <= tlb_reload_data_i[5:0]; + dtlb_trans_reload_we <= 1; + + // Match register generation. + // VPN + dtlb_match_reload_din[31:13] <= virt_addr_match_i[31:13]; + // Valid + dtlb_match_reload_din[0] <= 1; + dtlb_match_reload_we <= 1; + + tlb_reload_state <= TLB_READ; + end + end + end + + // Let the just written values propagate out on the read ports + TLB_READ: begin + tlb_reload_state <= TLB_IDLE; + end + + default: + tlb_reload_state <= TLB_IDLE; + endcase + + // Abort if enable deasserts in the middle of a reload + if (!enable_i | (dmmucr[31:10] == 0)) + tlb_reload_state <= TLB_IDLE; + + end +end else begin // if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED") + assign tlb_reload_pagefault_o = 0; + assign tlb_reload_busy_o = 0; + always @(posedge clk) begin + tlb_reload_req_o <= 0; + tlb_reload_addr_o <= 0; + tlb_reload_pagefault <= 0; + dtlb_trans_reload_we <= 0; + dtlb_trans_reload_din <= 0; + dtlb_match_reload_we <= 0; + dtlb_match_reload_din <= 0; + end +end +endgenerate + +generate +for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : dtlb + // DTLB match registers + mor1kx_true_dpram_sclk + #( + .ADDR_WIDTH(OPTION_DMMU_SET_WIDTH), + .DATA_WIDTH(OPTION_OPERAND_WIDTH) + ) + dtlb_match_regs + ( + // Outputs + .dout_a (dtlb_match_dout[i]), + .dout_b (dtlb_match_huge_dout[i]), + // Inputs + .clk (clk), + .addr_a (dtlb_match_addr), + .we_a (dtlb_match_we[i]), + .din_a (dtlb_match_din), + .addr_b (dtlb_match_huge_addr), + .we_b (dtlb_match_huge_we), + .din_b (dtlb_match_reload_din) + ); + + + // DTLB translate registers + mor1kx_true_dpram_sclk + #( + .ADDR_WIDTH(OPTION_DMMU_SET_WIDTH), + .DATA_WIDTH(OPTION_OPERAND_WIDTH) + ) + dtlb_translate_regs + ( + // Outputs + .dout_a (dtlb_trans_dout[i]), + .dout_b (dtlb_trans_huge_dout[i]), + // Inputs + .clk (clk), + .addr_a (dtlb_trans_addr), + .we_a (dtlb_trans_we[i]), + .din_a (dtlb_trans_din), + .addr_b (dtlb_trans_huge_addr), + .we_b (dtlb_trans_huge_we), + .din_b (dtlb_trans_reload_din) + ); +end +endgenerate + +endmodule // mor1kx_dmmu diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_alu.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_alu.v new file mode 100644 index 0000000..59558d0 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_alu.v @@ -0,0 +1,816 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx execute stage ALU + + Inputs are opcodes, the immediate field, operands from RF, instruction + opcode + + Copyright (C) 2012 Julius Baxter + Copyright (C) 2012-2014 Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_execute_alu + #( + parameter OPTION_OPERAND_WIDTH = 32, + + parameter FEATURE_OVERFLOW = "NONE", + parameter FEATURE_CARRY_FLAG = "ENABLED", + + parameter FEATURE_MULTIPLIER = "THREESTAGE", + parameter FEATURE_DIVIDER = "NONE", + + parameter FEATURE_ADDC = "NONE", + parameter FEATURE_SRA = "ENABLED", + parameter FEATURE_ROR = "NONE", + parameter FEATURE_EXT = "NONE", + parameter FEATURE_CMOV = "NONE", + parameter FEATURE_FFL1 = "NONE", + + parameter FEATURE_CUST1 = "NONE", + parameter FEATURE_CUST2 = "NONE", + parameter FEATURE_CUST3 = "NONE", + parameter FEATURE_CUST4 = "NONE", + parameter FEATURE_CUST5 = "NONE", + parameter FEATURE_CUST6 = "NONE", + parameter FEATURE_CUST7 = "NONE", + parameter FEATURE_CUST8 = "NONE", + + parameter FEATURE_FPU = "NONE", // ENABLED|NONE + parameter OPTION_SHIFTER = "BARREL", + + // Pipeline specific internal parameters + parameter CALCULATE_BRANCH_DEST = "TRUE" + ) + ( + input clk, + input rst, + + // pipeline control signal in + input padv_decode_i, + input padv_execute_i, + input padv_ctrl_i, + + input pipeline_flush_i ,// flush pipelined fpu + + // inputs to ALU + input [`OR1K_ALU_OPC_WIDTH-1:0] opc_alu_i, + input [`OR1K_ALU_OPC_WIDTH-1:0] opc_alu_secondary_i, + + input [`OR1K_IMM_WIDTH-1:0] imm16_i, + input [OPTION_OPERAND_WIDTH-1:0] immediate_i, + input immediate_sel_i, + + input [OPTION_OPERAND_WIDTH-1:0] decode_immediate_i, + input decode_immediate_sel_i, + + input decode_valid_i, + + input decode_op_mul_i, + + input op_alu_i, + input op_add_i, + input op_mul_i, + input op_mul_signed_i, + input op_mul_unsigned_i, + input op_div_i, + input op_div_signed_i, + input op_div_unsigned_i, + input op_shift_i, + input op_ffl1_i, + input op_setflag_i, + input op_mtspr_i, + input op_mfspr_i, + input op_movhi_i, + input [`OR1K_FPUOP_WIDTH-1:0] op_fpu_i, + input [`OR1K_FPCSR_RM_SIZE-1:0] fpu_round_mode_i, + input op_jbr_i, + input op_jr_i, + input [9:0] immjbr_upper_i, + input [OPTION_OPERAND_WIDTH-1:0] pc_execute_i, + + // Adder control logic + input adder_do_sub_i, + input adder_do_carry_i, + + input [OPTION_OPERAND_WIDTH-1:0] decode_rfa_i, + input [OPTION_OPERAND_WIDTH-1:0] decode_rfb_i, + + input [OPTION_OPERAND_WIDTH-1:0] rfa_i, + input [OPTION_OPERAND_WIDTH-1:0] rfb_i, + + // flag fed back from ctrl + input flag_i, + + output flag_set_o, + output flag_clear_o, + + input carry_i, + output carry_set_o, + output carry_clear_o, + + output overflow_set_o, + output overflow_clear_o, + + output [`OR1K_FPCSR_WIDTH-1:0] fpcsr_o, + output fpcsr_set_o, + + output [OPTION_OPERAND_WIDTH-1:0] alu_result_o, + output alu_valid_o, + output [OPTION_OPERAND_WIDTH-1:0] mul_result_o, + output [OPTION_OPERAND_WIDTH-1:0] adder_result_o + ); + + wire alu_stall; + + wire [OPTION_OPERAND_WIDTH-1:0] a; + wire [OPTION_OPERAND_WIDTH-1:0] b; + + // Adder & comparator wires + wire [OPTION_OPERAND_WIDTH-1:0] adder_result; + wire adder_carryout; + wire adder_signed_overflow; + wire adder_unsigned_overflow; + wire adder_result_sign; + + wire [OPTION_OPERAND_WIDTH-1:0] b_neg; + wire [OPTION_OPERAND_WIDTH-1:0] b_mux; + wire carry_in; + + wire a_eq_b; + wire a_lts_b; + wire a_ltu_b; + + // Shifter wires + wire [`OR1K_ALU_OPC_SECONDARY_WIDTH-1:0] opc_alu_shr; + wire [OPTION_OPERAND_WIDTH-1:0] shift_result; + wire shift_valid; + + // Comparison wires + reg flag_set; // comb. + + // Logic wires + wire op_logic; + reg [OPTION_OPERAND_WIDTH-1:0] logic_result; + + // Multiplier wires + wire [OPTION_OPERAND_WIDTH-1:0] mul_result; + wire mul_valid; + wire mul_signed_overflow; + wire mul_unsigned_overflow; + + wire [OPTION_OPERAND_WIDTH-1:0] div_result; + wire div_valid; + wire div_by_zero; + + + wire [OPTION_OPERAND_WIDTH-1:0] ffl1_result; + + wire op_cmov; + wire [OPTION_OPERAND_WIDTH-1:0] cmov_result; + + wire [OPTION_OPERAND_WIDTH-1:0] decode_a; + wire [OPTION_OPERAND_WIDTH-1:0] decode_b; +generate +if (CALCULATE_BRANCH_DEST=="TRUE") begin : calculate_branch_dest + assign a = (op_jbr_i | op_jr_i) ? pc_execute_i : rfa_i; + assign b = immediate_sel_i ? immediate_i : + op_jbr_i ? {{4{immjbr_upper_i[9]}},immjbr_upper_i,imm16_i,2'b00} : + rfb_i; +end else begin + assign a = rfa_i; + assign b = immediate_sel_i ? immediate_i : rfb_i; + + assign decode_a = decode_rfa_i; + assign decode_b = decode_immediate_sel_i ? decode_immediate_i : decode_rfb_i; + +end +endgenerate + + assign opc_alu_shr = opc_alu_secondary_i[`OR1K_ALU_OPC_SECONDARY_WIDTH-1:0]; + + // Adder/subtractor inputs + assign b_neg = ~b; + assign carry_in = adder_do_sub_i | adder_do_carry_i & carry_i; + assign b_mux = adder_do_sub_i ? b_neg : b; + // Adder + assign {adder_carryout, adder_result} = a + b_mux + + {{OPTION_OPERAND_WIDTH-1{1'b0}}, + carry_in}; + + assign adder_result_sign = adder_result[OPTION_OPERAND_WIDTH-1]; + + assign adder_signed_overflow = // Input signs are same and ... + (a[OPTION_OPERAND_WIDTH-1] == + b_mux[OPTION_OPERAND_WIDTH-1]) & + // result sign is different to input signs + (a[OPTION_OPERAND_WIDTH-1] ^ + adder_result[OPTION_OPERAND_WIDTH-1]); + + assign adder_unsigned_overflow = adder_carryout; + + assign adder_result_o = adder_result; + + generate + /* verilator lint_off WIDTH */ + if (FEATURE_MULTIPLIER=="THREESTAGE") begin : threestagemultiply + /* verilator lint_on WIDTH */ + // 32-bit multiplier with three registering stages to help with timing + reg [OPTION_OPERAND_WIDTH-1:0] mul_opa; + reg [OPTION_OPERAND_WIDTH-1:0] mul_opb; + reg [OPTION_OPERAND_WIDTH-1:0] mul_result1; + reg [OPTION_OPERAND_WIDTH-1:0] mul_result2; + reg [2:0] mul_valid_shr; + + always @(posedge clk) begin + if (op_mul_i) begin + mul_opa <= a; + mul_opb <= b; + end + mul_result1 <= mul_opa * mul_opb; + mul_result2 <= mul_result1; + end + + assign mul_result = mul_result2; + + always @(posedge clk) + if (decode_valid_i) + mul_valid_shr <= {2'b00, op_mul_i}; + else + mul_valid_shr <= mul_valid_shr[2] ? mul_valid_shr: + {mul_valid_shr[1:0], 1'b0}; + + assign mul_valid = mul_valid_shr[2] & !decode_valid_i; + + // Can't detect unsigned overflow in this implementation + assign mul_unsigned_overflow = 0; + + end // if (FEATURE_MULTIPLIER=="THREESTAGE") + /* verilator lint_off WIDTH */ + else if (FEATURE_MULTIPLIER=="PIPELINED") begin : pipelinedmultiply + /* verilator lint_on WIDTH */ + // 32-bit multiplier in sync with cpu pipeline + reg [OPTION_OPERAND_WIDTH-1:0] mul_opa; + reg [OPTION_OPERAND_WIDTH-1:0] mul_opb; + reg [OPTION_OPERAND_WIDTH-1:0] mul_result1; + reg [OPTION_OPERAND_WIDTH-1:0] mul_result2; + + always @(posedge clk) begin + if (decode_op_mul_i & padv_decode_i) begin + mul_opa <= decode_a; + mul_opb <= decode_b; + end + if (padv_execute_i) + mul_result1 <= mul_opa * mul_opb; + + mul_result2 <= mul_result1; + end + + assign mul_result = mul_result2; + + assign mul_valid = 1; + + // Can't detect unsigned overflow in this implementation + assign mul_unsigned_overflow = 0; + + end // if (FEATURE_MULTIPLIER=="PIPELINED") + else if (FEATURE_MULTIPLIER=="SERIAL") begin : serialmultiply + reg [(OPTION_OPERAND_WIDTH*2)-1:0] mul_prod_r; + reg [5:0] serial_mul_cnt; + reg mul_done; + wire [OPTION_OPERAND_WIDTH-1:0] mul_a, mul_b; + + // Check if it's a signed multiply and operand b is negative, + // convert to positive + assign mul_a = op_mul_signed_i & a[OPTION_OPERAND_WIDTH-1] ? + ~a + 1 : a; + assign mul_b = op_mul_signed_i & b[OPTION_OPERAND_WIDTH-1] ? + ~b + 1 : b; + + always @(posedge clk) + if (rst) begin + mul_prod_r <= 64'h0000_0000_0000_0000; + serial_mul_cnt <= 6'd0; + mul_done <= 1'b0; + end + else if (|serial_mul_cnt) begin + serial_mul_cnt <= serial_mul_cnt - 6'd1; + + if (mul_prod_r[0]) + mul_prod_r[(OPTION_OPERAND_WIDTH*2)-1:OPTION_OPERAND_WIDTH-1] + <= mul_prod_r[(OPTION_OPERAND_WIDTH*2)-1:OPTION_OPERAND_WIDTH] + mul_a; + else + mul_prod_r[(OPTION_OPERAND_WIDTH*2)-1:OPTION_OPERAND_WIDTH-1] + <= {1'b0,mul_prod_r[(OPTION_OPERAND_WIDTH*2)-1:OPTION_OPERAND_WIDTH]}; + + mul_prod_r[OPTION_OPERAND_WIDTH-2:0] <= mul_prod_r[OPTION_OPERAND_WIDTH-1:1]; + + if (serial_mul_cnt==6'd1) + mul_done <= 1'b1; + + end + else if (decode_valid_i && op_mul_i) begin + mul_prod_r[(OPTION_OPERAND_WIDTH*2)-1:OPTION_OPERAND_WIDTH] <= 32'd0; + mul_prod_r[OPTION_OPERAND_WIDTH-1:0] <= mul_b; + mul_done <= 0; + serial_mul_cnt <= 6'b10_0000; + end + else if (decode_valid_i) begin + mul_done <= 1'b0; + end + + assign mul_valid = mul_done & !decode_valid_i; + + assign mul_result = op_mul_signed_i ? + ((a[OPTION_OPERAND_WIDTH-1] ^ + b[OPTION_OPERAND_WIDTH-1]) ? + ~mul_prod_r[OPTION_OPERAND_WIDTH-1:0] + 1 : + mul_prod_r[OPTION_OPERAND_WIDTH-1:0]) : + mul_prod_r[OPTION_OPERAND_WIDTH-1:0]; + + assign mul_unsigned_overflow = OPTION_OPERAND_WIDTH==64 ? 0 : + |mul_prod_r[(OPTION_OPERAND_WIDTH*2)-1: + OPTION_OPERAND_WIDTH]; + + // synthesis translate_off + `ifndef verilator + always @(posedge mul_valid) + begin + @(posedge clk); + + if (((a*b) & {OPTION_OPERAND_WIDTH{1'b1}}) != mul_result) + begin + $display("%t incorrect serial multiply result at pc %08h", + $time, pc_execute_i); + $display("a=%08h b=%08h, mul_result=%08h, expected %08h", + a, b, mul_result, ((a*b) & {OPTION_OPERAND_WIDTH{1'b1}})); + end + end + `endif + // synthesis translate_on + + end // if (FEATURE_MULTIPLIER=="SERIAL") + else if (FEATURE_MULTIPLIER=="SIMULATION") begin + // Simple multiplier result + wire [(OPTION_OPERAND_WIDTH*2)-1:0] mul_full_result; + assign mul_full_result = a * b; + assign mul_result = mul_full_result[OPTION_OPERAND_WIDTH-1:0]; + + assign mul_unsigned_overflow = OPTION_OPERAND_WIDTH==64 ? 0 : + |mul_full_result[(OPTION_OPERAND_WIDTH*2)-1:OPTION_OPERAND_WIDTH]; + + assign mul_valid = 1; + end + else if (FEATURE_MULTIPLIER=="NONE") begin + // No multiplier + assign mul_result = 0; + assign mul_valid = 1'b1; + assign mul_unsigned_overflow = 0; + end + else begin + // Incorrect configuration option + initial begin + $display("%m: Error - chosen multiplier implementation (%s) not available", + FEATURE_MULTIPLIER); + $finish; + end + end + endgenerate + + // One signed overflow detection for all multiplication implmentations + assign mul_signed_overflow = (FEATURE_MULTIPLIER=="NONE") || + (FEATURE_MULTIPLIER=="PIPELINED") ? 0 : + // Same signs, check for negative result + // (should be positive) + ((a[OPTION_OPERAND_WIDTH-1] == + b[OPTION_OPERAND_WIDTH-1]) && + mul_result[OPTION_OPERAND_WIDTH-1]) || + // Differring signs, check for positive result + // (should be negative) + ((a[OPTION_OPERAND_WIDTH-1] ^ + b[OPTION_OPERAND_WIDTH-1]) && + !mul_result[OPTION_OPERAND_WIDTH-1]); + + assign mul_result_o = mul_result; + + generate + /* verilator lint_off WIDTH */ + if (FEATURE_DIVIDER=="SERIAL") begin + /* verilator lint_on WIDTH */ + reg [5:0] div_count; + reg [OPTION_OPERAND_WIDTH-1:0] div_n; + reg [OPTION_OPERAND_WIDTH-1:0] div_d; + reg [OPTION_OPERAND_WIDTH-1:0] div_r; + wire [OPTION_OPERAND_WIDTH:0] div_sub; + reg div_neg; + reg div_done; + reg div_by_zero_r; + + + assign div_sub = {div_r[OPTION_OPERAND_WIDTH-2:0], + div_n[OPTION_OPERAND_WIDTH-1]} - div_d; + + /* Cycle counter */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + div_done <= 0; + div_count <= 0; + end else if (decode_valid_i & op_div_i) begin + div_done <= 0; + div_count <= OPTION_OPERAND_WIDTH; + end else if (div_count == 1) + div_done <= 1; + else if (!div_done) + div_count <= div_count - 1; + + always @(posedge clk) begin + if (decode_valid_i & op_div_i) begin + div_n <= rfa_i; + div_d <= rfb_i; + div_r <= 0; + div_neg <= 1'b0; + div_by_zero_r <= !(|rfb_i); + + /* + * Convert negative operands in the case of signed division. + * If only one of the operands is negative, the result is + * converted back to negative later on + */ + if (op_div_signed_i) begin + if (rfa_i[OPTION_OPERAND_WIDTH-1] ^ + rfb_i[OPTION_OPERAND_WIDTH-1]) + div_neg <= 1'b1; + + if (rfa_i[OPTION_OPERAND_WIDTH-1]) + div_n <= ~rfa_i + 1; + + if (rfb_i[OPTION_OPERAND_WIDTH-1]) + div_d <= ~rfb_i + 1; + end + end else if (!div_done) begin + if (!div_sub[OPTION_OPERAND_WIDTH]) begin // div_sub >= 0 + div_r <= div_sub[OPTION_OPERAND_WIDTH-1:0]; + div_n <= {div_n[OPTION_OPERAND_WIDTH-2:0], 1'b1}; + end else begin // div_sub < 0 + div_r <= {div_r[OPTION_OPERAND_WIDTH-2:0], + div_n[OPTION_OPERAND_WIDTH-1]}; + div_n <= {div_n[OPTION_OPERAND_WIDTH-2:0], 1'b0}; + end + end + end + + assign div_valid = div_done & !decode_valid_i; + assign div_result = div_neg ? ~div_n + 1 : div_n; + assign div_by_zero = div_by_zero_r; + end + /* verilator lint_off WIDTH */ + else if (FEATURE_DIVIDER=="SIMULATION") begin + /* verilator lint_on WIDTH */ + assign div_result = a / b; + assign div_valid = 1; + assign div_by_zero = (opc_alu_i == `OR1K_ALU_OPC_DIV || + opc_alu_i == `OR1K_ALU_OPC_DIVU) && !(|b); + + end + else if (FEATURE_DIVIDER=="NONE") begin + assign div_result = 0; + assign div_valid = 1'b1; + assign div_by_zero = 0; + end + else begin + // Incorrect configuration option + initial begin + $display("%m: Error - chosen divider implementation (%s) not available", + FEATURE_DIVIDER); + $finish; + end + end + endgenerate + + + // FPU related + // arithmetic part interface + wire fpu_op_is_arith; + wire fpu_arith_valid; + wire [OPTION_OPERAND_WIDTH-1:0] fpu_result; + // comparator part interface + wire fpu_op_is_cmp; + wire fpu_cmp_valid; + wire fpu_cmp_flag; + // instance + generate + /* verilator lint_off WIDTH */ + if (FEATURE_FPU!="NONE") begin : fpu_alu_ena + /* verilator lint_on WIDTH */ + // fpu32 instance + pfpu32_top u_pfpu32 + ( + .clk(clk), + .rst(rst), + .flush_i(pipeline_flush_i), + .padv_decode_i(padv_decode_i), + .padv_execute_i(padv_execute_i), + .op_fpu_i(op_fpu_i), + .round_mode_i(fpu_round_mode_i), + .rfa_i(rfa_i), + .rfb_i(rfb_i), + .fpu_result_o(fpu_result), + .fpu_arith_valid_o(fpu_arith_valid), + .fpu_cmp_flag_o(fpu_cmp_flag), + .fpu_cmp_valid_o(fpu_cmp_valid), + .fpcsr_o(fpcsr_o) + ); + // flag to update FPCSR + assign fpcsr_set_o = fpu_arith_valid | fpu_cmp_valid; + // some glue logic + assign fpu_op_is_arith = op_fpu_i[`OR1K_FPUOP_WIDTH-1] & (~op_fpu_i[3]); + assign fpu_op_is_cmp = op_fpu_i[`OR1K_FPUOP_WIDTH-1] & op_fpu_i[3]; + end + else begin : fpu_alu_none + // arithmetic part + assign fpu_op_is_arith = 0; + assign fpu_arith_valid = 0; + assign fpu_result = {OPTION_OPERAND_WIDTH{1'b0}}; + // comparator part + assign fpu_op_is_cmp = 0; + assign fpu_cmp_valid = 0; + assign fpu_cmp_flag = 0; + // fpu's common + assign fpcsr_o = {`OR1K_FPCSR_WIDTH{1'b0}}; + assign fpcsr_set_o = 0; + end + endgenerate // FPU related + + + wire ffl1_valid; + generate + if (FEATURE_FFL1!="NONE") begin + wire [OPTION_OPERAND_WIDTH-1:0] ffl1_result_wire; + assign ffl1_result_wire = (opc_alu_secondary_i[2]) ? + (a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : + a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : + a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : + a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : + a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : + a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : + a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : + a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : + a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : + a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ) : + (a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : + a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : + a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : + a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : + a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : + a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : + a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : + a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : + a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : + a[30] ? 31 : a[31] ? 32 : 0); + /* verilator lint_off WIDTH */ + if (FEATURE_FFL1=="REGISTERED") begin + /* verilator lint_on WIDTH */ + reg [OPTION_OPERAND_WIDTH-1:0] ffl1_result_r; + + assign ffl1_valid = !decode_valid_i; + assign ffl1_result = ffl1_result_r; + + always @(posedge clk) + if (decode_valid_i) + ffl1_result_r = ffl1_result_wire; + end else begin + assign ffl1_result = ffl1_result_wire; + assign ffl1_valid = 1'b1; + end + end + else begin + assign ffl1_result = 0; + assign ffl1_valid = 1'b1; + end + endgenerate + + // Equal compare + assign a_eq_b = (a == b); + // Signed compare + assign a_lts_b = !(adder_result_sign == adder_signed_overflow); + // Unsigned compare + assign a_ltu_b = !adder_carryout; + + generate + /* verilator lint_off WIDTH */ + if (OPTION_SHIFTER=="BARREL") begin : barrel_shifter + /* verilator lint_on WIDTH */ + + function [OPTION_OPERAND_WIDTH-1:0] reverse; + input [OPTION_OPERAND_WIDTH-1:0] in; + integer i; + begin + for (i = 0; i < OPTION_OPERAND_WIDTH; i=i+1) begin + reverse[(OPTION_OPERAND_WIDTH-1)-i] = in[i]; + end + end + endfunction + + wire op_sll = (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_SLL); + wire op_srl = (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_SRL); + wire op_sra = (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_SRA) && + (FEATURE_SRA!="NONE"); + wire op_ror = (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_ROR) && + (FEATURE_ROR!="NONE"); + + wire [OPTION_OPERAND_WIDTH-1:0] shift_right; + wire [OPTION_OPERAND_WIDTH-1:0] shift_lsw; + wire [OPTION_OPERAND_WIDTH-1:0] shift_msw; + + // + // Bit-reverse on left shift, perform right shift, + // bit-reverse result on left shift. + // + assign shift_lsw = op_sll ? reverse(a) : a; + assign shift_msw = op_sra ? + {OPTION_OPERAND_WIDTH{a[OPTION_OPERAND_WIDTH-1]}} : + op_ror ? a : {OPTION_OPERAND_WIDTH{1'b0}}; + + assign shift_right = {shift_msw, shift_lsw} >> b[4:0]; + assign shift_result = op_sll ? reverse(shift_right) : shift_right; + + assign shift_valid = 1; + + end else if (OPTION_SHIFTER=="SERIAL") begin : serial_shifter + // Serial shifter + reg [4:0] shift_cnt; + reg shift_go; + reg [OPTION_OPERAND_WIDTH-1:0] shift_result_r; + always @(posedge clk `OR_ASYNC_RST) + if (rst) + shift_go <= 0; + else if (decode_valid_i) + shift_go <= op_shift_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + shift_cnt <= 0; + shift_result_r <= 0; + end + else if (decode_valid_i & op_shift_i) begin + shift_cnt <= 0; + shift_result_r <= a; + end + else if (shift_go && !(shift_cnt==b[4:0])) begin + shift_cnt <= shift_cnt + 1; + if (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_SRL) + shift_result_r <= {1'b0,shift_result_r[OPTION_OPERAND_WIDTH-1:1]}; + else if (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_SLL) + shift_result_r <= {shift_result_r[OPTION_OPERAND_WIDTH-2:0],1'b0}; + else if (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_ROR) + shift_result_r <= {shift_result_r[0] + ,shift_result_r[OPTION_OPERAND_WIDTH-1:1]}; + + else if (opc_alu_shr==`OR1K_ALU_OPC_SECONDARY_SHRT_SRA) + shift_result_r <= {a[OPTION_OPERAND_WIDTH-1], + shift_result_r[OPTION_OPERAND_WIDTH-1:1]}; + end // if (shift_go && !(shift_cnt==b[4:0])) + + assign shift_valid = (shift_cnt==b[4:0]) & shift_go & !decode_valid_i; + + assign shift_result = shift_result_r; + + end // if (OPTION_SHIFTER=="SERIAL") + else + initial begin + $display("%m: Error - chosen shifter implementation (%s) not available", + OPTION_SHIFTER); + $finish; + + end + endgenerate + + // Conditional move + generate + /* verilator lint_off WIDTH */ + if (FEATURE_CMOV=="ENABLED") begin + /* verilator lint_on WIDTH */ + assign cmov_result = flag_i ? a : b; + end + endgenerate + + // Comparison logic + // To update SR[F] either from integer or float point comparision + assign flag_set_o = fpu_op_is_cmp ? + (fpu_cmp_flag & fpu_cmp_valid) : + (flag_set & op_setflag_i); + assign flag_clear_o = fpu_op_is_cmp ? + ((~fpu_cmp_flag) & fpu_cmp_valid) : + ((~flag_set) & op_setflag_i); + + // Combinatorial block + always @* + case(opc_alu_secondary_i) + `OR1K_COMP_OPC_EQ: + flag_set = a_eq_b; + `OR1K_COMP_OPC_NE: + flag_set = !a_eq_b; + `OR1K_COMP_OPC_GTU: + flag_set = !(a_eq_b | a_ltu_b); + `OR1K_COMP_OPC_GTS: + flag_set = !(a_eq_b | a_lts_b); + `OR1K_COMP_OPC_GEU: + flag_set = !a_ltu_b; + `OR1K_COMP_OPC_GES: + flag_set = !a_lts_b; + `OR1K_COMP_OPC_LTU: + flag_set = a_ltu_b; + `OR1K_COMP_OPC_LTS: + flag_set = a_lts_b; + `OR1K_COMP_OPC_LEU: + flag_set = a_eq_b | a_ltu_b; + `OR1K_COMP_OPC_LES: + flag_set = a_eq_b | a_lts_b; + default: + flag_set = 0; + endcase // case (opc_alu_secondary_i) + + // + // Logic operations + // + // Create a look-up-table for AND/OR/XOR + reg [3:0] logic_lut; + always @(*) begin + case(opc_alu_i) + `OR1K_ALU_OPC_AND: + logic_lut = 4'b1000; + `OR1K_ALU_OPC_OR: + logic_lut = 4'b1110; + `OR1K_ALU_OPC_XOR: + logic_lut = 4'b0110; + default: + logic_lut = 0; + endcase + if (!op_alu_i) + logic_lut = 0; + // Threat mfspr/mtspr as 'OR' + if (op_mfspr_i | op_mtspr_i) + logic_lut = 4'b1110; + end + + // Extract the result, bit-for-bit, from the look-up-table + integer i; + always @(*) + for (i = 0; i < OPTION_OPERAND_WIDTH; i=i+1) begin + logic_result[i] = logic_lut[{a[i], b[i]}]; + end + + assign op_logic = |logic_lut; + + assign op_cmov = op_alu_i & opc_alu_i == `OR1K_ALU_OPC_CMOV; + + // Result muxing - result is registered in RF + assign alu_result_o = op_logic ? logic_result : + op_cmov ? cmov_result : + op_movhi_i ? immediate_i : + op_mul_i ? mul_result[OPTION_OPERAND_WIDTH-1:0] : + fpu_arith_valid ? fpu_result : + fpu_cmp_valid ? {OPTION_OPERAND_WIDTH{1'b0}} : + op_shift_i ? shift_result : + op_div_i ? div_result : + op_ffl1_i ? ffl1_result : + adder_result; + + // Carry and overflow flag generation + assign overflow_set_o = FEATURE_OVERFLOW!="NONE" & + (op_add_i & adder_signed_overflow | + op_mul_signed_i & mul_signed_overflow | + op_div_signed_i & div_by_zero); + + assign overflow_clear_o = FEATURE_OVERFLOW!="NONE" & + (op_add_i & !adder_signed_overflow | + op_mul_signed_i & !mul_signed_overflow | + op_div_signed_i & !div_by_zero); + + assign carry_set_o = FEATURE_CARRY_FLAG!="NONE" & + (op_add_i & adder_unsigned_overflow | + op_mul_unsigned_i & mul_unsigned_overflow | + op_div_unsigned_i & div_by_zero); + + assign carry_clear_o = FEATURE_CARRY_FLAG!="NONE" & + (op_add_i & !adder_unsigned_overflow | + op_mul_unsigned_i & !mul_unsigned_overflow | + op_div_unsigned_i & !div_by_zero); + + // Stall logic for multicycle ALU operations + assign alu_stall = op_div_i & !div_valid | + op_mul_i & !mul_valid | + fpu_op_is_arith & !fpu_arith_valid | + fpu_op_is_cmp & !fpu_cmp_valid | + op_shift_i & !shift_valid | + op_ffl1_i & !ffl1_valid; + + assign alu_valid_o = !alu_stall; + +endmodule // mor1kx_execute_alu diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v new file mode 100644 index 0000000..6e91801 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v @@ -0,0 +1,387 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: execute to control stage signal passing + + Generate valid signal when stage is done + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_execute_ctrl_cappuccino + #( + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter FEATURE_FPU = "NONE", // ENABLED|NONE + parameter FEATURE_MULTIPLIER = "THREESTAGE" + ) + ( + input clk, + input rst, + + input padv_i, + input padv_ctrl_i, + + input execute_except_ibus_err_i, + input execute_except_itlb_miss_i, + input execute_except_ipagefault_i, + input execute_except_illegal_i, + input execute_except_ibus_align_i, + input execute_except_syscall_i, + input lsu_except_dbus_i, + input lsu_except_align_i, + input lsu_except_dtlb_miss_i, + input lsu_except_dpagefault_i, + input execute_except_trap_i, + + input pipeline_flush_i, + + input op_mul_i, + + input op_lsu_load_i, + input op_lsu_store_i, + input op_lsu_atomic_i, + input [1:0] lsu_length_i, + input lsu_zext_i, + + input op_msync_i, + + input op_mfspr_i, + input op_mtspr_i, + input alu_valid_i, + input lsu_valid_i, + + input msync_stall_i, + + input op_jr_i, + input op_jal_i, + input op_rfe_i, + + input [OPTION_OPERAND_WIDTH-1:0] alu_result_i, + input [OPTION_OPERAND_WIDTH-1:0] adder_result_i, + input [OPTION_OPERAND_WIDTH-1:0] rfb_i, + input [OPTION_OPERAND_WIDTH-1:0] execute_jal_result_i, + input flag_set_i, + input flag_clear_i, + input carry_set_i, + input carry_clear_i, + input overflow_set_i, + input overflow_clear_i, + + input [`OR1K_FPCSR_WIDTH-1:0] fpcsr_i, + input fpcsr_set_i, + + + input [OPTION_OPERAND_WIDTH-1:0] pc_execute_i, + + input execute_rf_wb_i, + output reg ctrl_rf_wb_o, + output reg wb_rf_wb_o, + + + // address of destination register from execute stage + input [OPTION_RF_ADDR_WIDTH-1:0] execute_rfd_adr_i, + output reg [OPTION_RF_ADDR_WIDTH-1:0] ctrl_rfd_adr_o, + output reg [OPTION_RF_ADDR_WIDTH-1:0] wb_rfd_adr_o, + + input execute_bubble_i, + + // Input from control stage for mfspr/mtspr ack + input ctrl_mfspr_ack_i, + input ctrl_mtspr_ack_i, + + output reg [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_o, + output reg [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_o, + output reg [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_o, + output reg ctrl_flag_set_o, + output reg ctrl_flag_clear_o, + output reg ctrl_carry_set_o, + output reg ctrl_carry_clear_o, + output reg ctrl_overflow_set_o, + output reg ctrl_overflow_clear_o, + + output reg [`OR1K_FPCSR_WIDTH-1:0] ctrl_fpcsr_o, + output reg ctrl_fpcsr_set_o, + + + output reg [OPTION_OPERAND_WIDTH-1:0] pc_ctrl_o, + + output reg ctrl_op_mul_o, + + output reg ctrl_op_lsu_load_o, + output reg ctrl_op_lsu_store_o, + output reg ctrl_op_lsu_atomic_o, + output reg [1:0] ctrl_lsu_length_o, + output reg ctrl_lsu_zext_o, + + output reg ctrl_op_msync_o, + + output reg ctrl_op_mfspr_o, + output reg ctrl_op_mtspr_o, + + output reg ctrl_op_rfe_o, + + output reg ctrl_except_ibus_err_o, + output reg ctrl_except_itlb_miss_o, + output reg ctrl_except_ipagefault_o, + output reg ctrl_except_ibus_align_o, + output reg ctrl_except_illegal_o, + output reg ctrl_except_syscall_o, + output reg ctrl_except_dbus_o, + output reg ctrl_except_dtlb_miss_o, + output reg ctrl_except_dpagefault_o, + output reg ctrl_except_align_o, + output reg ctrl_except_trap_o, + + output execute_valid_o, + output ctrl_valid_o + ); + + wire ctrl_stall; + wire execute_stall; + + // LSU or MTSPR/MFSPR can stall from ctrl stage + assign ctrl_stall = (ctrl_op_lsu_load_o | ctrl_op_lsu_store_o) & + !lsu_valid_i | + ctrl_op_msync_o & msync_stall_i | + ctrl_op_mfspr_o & !ctrl_mfspr_ack_i | + ctrl_op_mtspr_o & !ctrl_mtspr_ack_i; + assign ctrl_valid_o = !ctrl_stall; + + // Execute stage can be stalled from ctrl stage and by ALU + assign execute_stall = ctrl_stall | !alu_valid_i; + assign execute_valid_o = !execute_stall; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + ctrl_except_ibus_err_o <= 0; + ctrl_except_itlb_miss_o <= 0; + ctrl_except_ipagefault_o <= 0; + ctrl_except_ibus_align_o <= 0; + ctrl_except_illegal_o <= 0; + ctrl_except_syscall_o <= 0; + ctrl_except_trap_o <= 0; + ctrl_except_dbus_o <= 0; + ctrl_except_align_o <= 0; + end + else if (pipeline_flush_i) begin + ctrl_except_ibus_err_o <= 0; + ctrl_except_itlb_miss_o <= 0; + ctrl_except_ipagefault_o <= 0; + ctrl_except_ibus_align_o <= 0; + ctrl_except_illegal_o <= 0; + ctrl_except_syscall_o <= 0; + ctrl_except_trap_o <= 0; + ctrl_except_dbus_o <= 0; + ctrl_except_align_o <= 0; + end + else begin + if (padv_i) begin + ctrl_except_ibus_err_o <= execute_except_ibus_err_i; + ctrl_except_itlb_miss_o <= execute_except_itlb_miss_i; + ctrl_except_ipagefault_o <= execute_except_ipagefault_i; + ctrl_except_ibus_align_o <= execute_except_ibus_align_i; + ctrl_except_illegal_o <= execute_except_illegal_i; + ctrl_except_syscall_o <= execute_except_syscall_i; + ctrl_except_trap_o <= execute_except_trap_i; + end + ctrl_except_dbus_o <= lsu_except_dbus_i; + ctrl_except_align_o <= lsu_except_align_i; + ctrl_except_dtlb_miss_o <= lsu_except_dtlb_miss_i; + ctrl_except_dpagefault_o <= lsu_except_dpagefault_i; + end + + always @(posedge clk) + if (padv_i) + if (op_jal_i) + ctrl_alu_result_o <= execute_jal_result_i; + else + ctrl_alu_result_o <= alu_result_i; + + always @(posedge clk) + if (padv_i & (op_lsu_store_i | op_lsu_load_i)) + ctrl_lsu_adr_o <= adder_result_i; + + always @(posedge clk) + if (padv_i) + ctrl_rfb_o <= rfb_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + ctrl_flag_set_o <= 0; + ctrl_flag_clear_o <= 0; + ctrl_carry_set_o <= 0; + ctrl_carry_clear_o <= 0; + ctrl_overflow_set_o <= 0; + ctrl_overflow_clear_o <= 0; + end + else if (padv_i) begin + ctrl_flag_set_o <= flag_set_i; + ctrl_flag_clear_o <= flag_clear_i; + ctrl_carry_set_o <= carry_set_i; + ctrl_carry_clear_o <= carry_clear_i; + ctrl_overflow_set_o <= overflow_set_i; + ctrl_overflow_clear_o <= overflow_clear_i; + end + + // pc_ctrl should not advance when a nop bubble moves from execute to + // ctrl/mem stage + always @(posedge clk `OR_ASYNC_RST) + if (rst) + pc_ctrl_o <= OPTION_RESET_PC; + else if (padv_i & !execute_bubble_i) + pc_ctrl_o <= pc_execute_i; + + // + // The pipeline flush comes when the instruction that has caused + // an exception or the instruction that has been interrupted is in + // ctrl stage, so the padv_execute signal has to have higher prioity + // than the pipeline flush in order to not accidently kill a valid + // instruction coming in from execute stage. + // + +generate +if (FEATURE_MULTIPLIER=="PIPELINED") begin + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_op_mul_o <= 0; + else if (padv_i) + ctrl_op_mul_o <= op_mul_i; + else if (pipeline_flush_i) + ctrl_op_mul_o <= 0; +end else begin + always @(posedge clk) + ctrl_op_mul_o <= 0; +end +endgenerate + + // FPU related + generate + /* verilator lint_off WIDTH */ + if (FEATURE_FPU!="NONE") begin : fpu_execute_ctrl_ena + /* verilator lint_on WIDTH */ + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + ctrl_fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}}; + ctrl_fpcsr_set_o <= 0; + end else if (pipeline_flush_i) begin + ctrl_fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}}; + ctrl_fpcsr_set_o <= 0; + end else if (padv_i) begin + ctrl_fpcsr_o <= fpcsr_i; + ctrl_fpcsr_set_o <= fpcsr_set_i; + end + end // @clk + end + else begin : fpu_execute_ctrl_none + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + ctrl_fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}}; + ctrl_fpcsr_set_o <= 0; + end + end // @clk + end + endgenerate // FPU related + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + ctrl_op_mfspr_o <= 0; + ctrl_op_mtspr_o <= 0; + end else if (padv_i) begin + ctrl_op_mfspr_o <= op_mfspr_i; + ctrl_op_mtspr_o <= op_mtspr_i; + end else if (pipeline_flush_i) begin + ctrl_op_mfspr_o <= 0; + ctrl_op_mtspr_o <= 0; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_op_rfe_o <= 0; + else if (padv_i) + ctrl_op_rfe_o <= op_rfe_i; + else if (pipeline_flush_i) + ctrl_op_rfe_o <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_op_msync_o <= 0; + else if (padv_i) + ctrl_op_msync_o <= op_msync_i; + else if (pipeline_flush_i) + ctrl_op_msync_o <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + ctrl_op_lsu_load_o <= 0; + ctrl_op_lsu_store_o <= 0; + ctrl_op_lsu_atomic_o <= 0; + end else if (ctrl_except_align_o | ctrl_except_dbus_o | + ctrl_except_dtlb_miss_o | ctrl_except_dpagefault_o) begin + ctrl_op_lsu_load_o <= 0; + ctrl_op_lsu_store_o <= 0; + ctrl_op_lsu_atomic_o <= 0; + end else if (padv_i) begin + ctrl_op_lsu_load_o <= op_lsu_load_i; + ctrl_op_lsu_store_o <= op_lsu_store_i; + ctrl_op_lsu_atomic_o <= op_lsu_atomic_i; + end else if (pipeline_flush_i) begin + ctrl_op_lsu_load_o <= 0; + ctrl_op_lsu_store_o <= 0; + ctrl_op_lsu_atomic_o <= 0; + end + + always @(posedge clk) + if (padv_i) begin + ctrl_lsu_length_o <= lsu_length_i; + ctrl_lsu_zext_o <= lsu_zext_i; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_rf_wb_o <= 0; + else if (padv_i) + ctrl_rf_wb_o <= execute_rf_wb_i; + else if (ctrl_op_mfspr_o & ctrl_mfspr_ack_i | + ctrl_op_lsu_load_o & lsu_valid_i) + // Deassert the write enable when the "bus" access is done, to avoid: + // 1) Writing multiple times to RF + // 2) Signaling a need to bypass from control stage, when it really + // should be a bypass from wb stage. + ctrl_rf_wb_o <= 0; + else if (pipeline_flush_i) + ctrl_rf_wb_o <= 0; + + always @(posedge clk) + if (padv_i) + ctrl_rfd_adr_o <= execute_rfd_adr_i; + + // load and mfpsr can stall from ctrl stage, so we have to hold off the + // write back on them + always @(posedge clk `OR_ASYNC_RST) + if (rst) + wb_rf_wb_o <= 0; + else if (pipeline_flush_i) + wb_rf_wb_o <= 0; + else if (ctrl_op_mfspr_o) + wb_rf_wb_o <= ctrl_rf_wb_o & ctrl_mfspr_ack_i; + else if (ctrl_op_lsu_load_o) + wb_rf_wb_o <= ctrl_rf_wb_o & lsu_valid_i; + else + wb_rf_wb_o <= ctrl_rf_wb_o & padv_ctrl_i; + + always @(posedge clk) + wb_rfd_adr_o <= ctrl_rfd_adr_o; + +endmodule // mor1kx_execute_ctrl_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_cappuccino.v new file mode 100644 index 0000000..17faed5 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_cappuccino.v @@ -0,0 +1,636 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx fetch/address stage unit + + basically an interface to the ibus/icache subsystem that can react to + exception and branch signals. + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_fetch_cappuccino + #( + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}, + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter FEATURE_INSTRUCTIONCACHE = "NONE", + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter OPTION_ICACHE_LIMIT_WIDTH = 32, + parameter FEATURE_IMMU = "NONE", + parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_IMMU_SET_WIDTH = 6, + parameter OPTION_IMMU_WAYS = 1 + ) + ( + input clk, + input rst, + + // SPR interface + input [15:0] spr_bus_addr_i, + input spr_bus_we_i, + input spr_bus_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_o, + output spr_bus_ack_ic_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_o, + output spr_bus_ack_immu_o, + + input ic_enable, + input immu_enable_i, + input supervisor_mode_i, + + // interface to ibus + input ibus_err_i, + input ibus_ack_i, + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i, + output ibus_req_o, + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o, + output ibus_burst_o, + + // pipeline control input + input padv_i, + input padv_ctrl_i, // needed for immu spr + + // interface to decode unit + output reg [OPTION_OPERAND_WIDTH-1:0] pc_decode_o, + output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o, + output reg fetch_valid_o, + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o, + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o, + output fetch_rf_adr_valid_o, + + // branch/jump indication + input decode_branch_i, + input [OPTION_OPERAND_WIDTH-1:0] decode_branch_target_i, + input ctrl_branch_exception_i, + input [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc_i, + input du_restart_i, + input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i, + input decode_op_brcond_i, + input branch_mispredict_i, + input [OPTION_OPERAND_WIDTH-1:0] execute_mispredict_target_i, + + // pipeline flush input from control unit + input pipeline_flush_i, + + // rfe instruction is being performed + input doing_rfe_i, + + // instruction ibus error indication out + output reg decode_except_ibus_err_o, + + // IMMU exceptions + output reg decode_except_itlb_miss_o, + output reg decode_except_ipagefault_o, + + output reg fetch_exception_taken_o + ); + + // registers + reg [OPTION_OPERAND_WIDTH-1:0] pc_fetch; + reg [OPTION_OPERAND_WIDTH-1:0] pc_addr; + reg ctrl_branch_exception_r; + + wire bus_access_done; + wire ctrl_branch_exception_edge; + wire stall_fetch_valid; + wire addr_valid; + reg flush; + wire flushing; + + reg nop_ack; + + reg imem_err; + wire imem_ack; + wire [`OR1K_INSN_WIDTH-1:0] imem_dat; + + wire ic_ack; + wire [`OR1K_INSN_WIDTH-1:0] ic_dat; + + wire ic_req; + wire ic_refill_allowed; + wire ic_refill; + wire ic_refill_req; + wire ic_refill_done; + wire ic_invalidate; + wire [OPTION_OPERAND_WIDTH-1:0] ic_addr; + wire [OPTION_OPERAND_WIDTH-1:0] ic_addr_match; + + wire ic_access; + + reg ic_enable_r; + wire ic_enabled; + + wire [OPTION_OPERAND_WIDTH-1:0] immu_phys_addr; + wire immu_cache_inhibit; + wire pagefault; + wire tlb_miss; + wire except_itlb_miss; + wire except_ipagefault; + + wire immu_busy; + + wire tlb_reload_req; + reg tlb_reload_ack; + wire [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr; + reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data; + wire tlb_reload_pagefault; + wire tlb_reload_busy; + + reg fetching_brcond; + reg fetching_mispredicted_branch; + wire mispredict_stall; + + reg exception_while_tlb_reload; + wire except_ipagefault_clear; + + assign bus_access_done = (imem_ack | imem_err | nop_ack) & !immu_busy & + !tlb_reload_busy; + assign ctrl_branch_exception_edge = ctrl_branch_exception_i & + !ctrl_branch_exception_r; + + /* used to keep fetch_valid_o high during stall */ + assign stall_fetch_valid = !padv_i & fetch_valid_o; + + assign addr_valid = bus_access_done & padv_i & + !(except_itlb_miss | except_ipagefault) | + decode_except_itlb_miss_o & ctrl_branch_exception_i | + decode_except_ipagefault_o & ctrl_branch_exception_i | + doing_rfe_i; + + assign except_itlb_miss = tlb_miss & immu_enable_i & bus_access_done & + !mispredict_stall & !doing_rfe_i; + assign except_ipagefault = pagefault & immu_enable_i & bus_access_done & + !mispredict_stall & !doing_rfe_i | + tlb_reload_pagefault; + + assign fetch_rfa_adr_o = imem_dat[`OR1K_RA_SELECT]; + assign fetch_rfb_adr_o = imem_dat[`OR1K_RB_SELECT]; + assign fetch_rf_adr_valid_o = bus_access_done & padv_i; + + // Signal to indicate that the ongoing bus access should be flushed + always @(posedge clk `OR_ASYNC_RST) + if (rst) + flush <= 0; + else if (bus_access_done & padv_i | du_restart_i) + flush <= 0; + else if (pipeline_flush_i) + flush <= 1; + + // pipeline_flush_i comes on the same edge as branch_except_occur during + // rfe, but on an edge later when an exception occurs, but we always need + // to keep on flushing when the branch signal comes in. + assign flushing = pipeline_flush_i | ctrl_branch_exception_edge | flush; + + // Branch misprediction stall logic + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetching_brcond <= 0; + else if (pipeline_flush_i) + fetching_brcond <= 0; + else if (decode_op_brcond_i & addr_valid) + fetching_brcond <= 1; + else if (bus_access_done & padv_i | du_restart_i) + fetching_brcond <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetching_mispredicted_branch <= 0; + else if (pipeline_flush_i) + fetching_mispredicted_branch <= 0; + else if (bus_access_done & padv_i | du_restart_i) + fetching_mispredicted_branch <= 0; + else if (fetching_brcond & branch_mispredict_i & padv_i) + fetching_mispredicted_branch <= 1; + + assign mispredict_stall = fetching_mispredicted_branch | + branch_mispredict_i & fetching_brcond; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ctrl_branch_exception_r <= 1'b0; + else + ctrl_branch_exception_r <= ctrl_branch_exception_i; + + // calculate address stage pc + always @(*) + if (rst) + pc_addr = OPTION_RESET_PC; + else if (du_restart_i) + pc_addr = du_restart_pc_i; + else if (ctrl_branch_exception_i & !fetch_exception_taken_o) + pc_addr = ctrl_branch_except_pc_i; + else if (branch_mispredict_i | fetching_mispredicted_branch) + pc_addr = execute_mispredict_target_i; + else if (decode_branch_i) + pc_addr = decode_branch_target_i; + else + pc_addr = pc_fetch + 4; + + // Register fetch pc from address stage + always @(posedge clk `OR_ASYNC_RST) + if (rst) + pc_fetch <= OPTION_RESET_PC; + else if (addr_valid | du_restart_i) + pc_fetch <= pc_addr; + + // fetch_exception_taken_o generation + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetch_exception_taken_o <= 1'b0; + else if (fetch_exception_taken_o) + fetch_exception_taken_o <= 1'b0; + else if (ctrl_branch_exception_i & bus_access_done & padv_i) + fetch_exception_taken_o <= 1'b1; + else + fetch_exception_taken_o <= 1'b0; + + // fetch_valid_o generation + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetch_valid_o <= 1'b0; + else if (pipeline_flush_i) + fetch_valid_o <= 1'b0; + else if (bus_access_done & padv_i & !mispredict_stall & !immu_busy & + !tlb_reload_busy | stall_fetch_valid) + fetch_valid_o <= 1'b1; + else + fetch_valid_o <= 1'b0; + + // Register instruction coming in + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (imem_err | flushing) + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (bus_access_done & padv_i & !mispredict_stall) + decode_insn_o <= imem_dat; + + // Register PC for later stages + always @(posedge clk) + if (bus_access_done & padv_i & !mispredict_stall) + pc_decode_o <= pc_fetch; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_except_ibus_err_o <= 0; + else if (du_restart_i) + decode_except_ibus_err_o <= 0; + else if (imem_err) + decode_except_ibus_err_o <= 1; + else if (decode_except_ibus_err_o & ctrl_branch_exception_i) + decode_except_ibus_err_o <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_except_itlb_miss_o <= 0; + else if (du_restart_i) + decode_except_itlb_miss_o <= 0; + else if (tlb_reload_busy) + decode_except_itlb_miss_o <= 0; + else if (except_itlb_miss) + decode_except_itlb_miss_o <= 1; + else if (decode_except_itlb_miss_o & ctrl_branch_exception_i) + decode_except_itlb_miss_o <= 0; + + assign except_ipagefault_clear = decode_except_ipagefault_o & + ctrl_branch_exception_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_except_ipagefault_o <= 0; + else if (du_restart_i) + decode_except_ipagefault_o <= 0; + else if (except_ipagefault) + decode_except_ipagefault_o <= 1; + else if (except_ipagefault_clear) + decode_except_ipagefault_o <= 0; + + // Bus access logic + localparam [2:0] + IDLE = 0, + READ = 1, + TLB_RELOAD = 2, + IC_REFILL = 3; + + reg [2:0] state; + + reg [OPTION_OPERAND_WIDTH-1:0] ibus_adr; + wire [OPTION_OPERAND_WIDTH-1:0] next_ibus_adr; + reg [`OR1K_INSN_WIDTH-1:0] ibus_dat; + reg ibus_req; + reg ibus_ack; + + wire ibus_access; + + // + // Under certain circumstances, there is a need to insert an nop + // into the pipeline in order for it to move forward. + // Here those conditions are handled and an acknowledged signal + // is generated. + // + always @(posedge clk `OR_ASYNC_RST) + if (rst) + nop_ack <= 0; + else + nop_ack <= padv_i & !bus_access_done & !(ibus_req & ibus_access) & + ((immu_enable_i & (tlb_miss | pagefault) & + !tlb_reload_busy) | + ctrl_branch_exception_edge & !tlb_reload_busy | + exception_while_tlb_reload & !tlb_reload_busy | + tlb_reload_pagefault | + mispredict_stall); + + assign ibus_access = (!ic_access | tlb_reload_busy | ic_invalidate) & + !ic_refill | + (state != IDLE) & (state != IC_REFILL) | + ibus_ack; + assign imem_ack = ibus_access ? ibus_ack : ic_ack; + assign imem_dat = (nop_ack | except_itlb_miss | except_ipagefault) ? + {`OR1K_OPCODE_NOP,26'd0} : + ibus_access ? ibus_dat : ic_dat; + assign ibus_adr_o = ibus_adr; + assign ibus_req_o = ibus_req; + assign ibus_burst_o = !ibus_access & ic_refill & !ic_refill_done; + + assign next_ibus_adr = (OPTION_ICACHE_BLOCK_WIDTH == 5) ? + {ibus_adr[31:5], ibus_adr[4:0] + 5'd4} : // 32 byte + {ibus_adr[31:4], ibus_adr[3:0] + 4'd4}; // 16 byte + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + imem_err <= 0; + else + imem_err <= ibus_err_i; + + always @(posedge clk) begin + ibus_ack <= 0; + exception_while_tlb_reload <= 0; + tlb_reload_ack <= 0; + + case (state) + IDLE: begin + ibus_req <= 0; + if (padv_i & ibus_access & !ibus_ack & !imem_err & !nop_ack) begin + if (tlb_reload_req) begin + ibus_adr <= tlb_reload_addr; + ibus_req <= 1; + state <= TLB_RELOAD; + end else if (immu_enable_i) begin + ibus_adr <= immu_phys_addr; + if (!tlb_miss & !pagefault & !immu_busy) begin + ibus_req <= 1; + state <= READ; + end + end else if (!ctrl_branch_exception_i | doing_rfe_i) begin + ibus_adr <= pc_fetch; + ibus_req <= 1; + state <= READ; + end + end else if (ic_refill_req) begin + ibus_adr <= ic_addr_match; + ibus_req <= 1; + state <= IC_REFILL; + end + end + + IC_REFILL: begin + ibus_req <= 1; + if (ibus_ack_i) begin + ibus_adr <= next_ibus_adr; + if (ic_refill_done) begin + ibus_req <= 0; + state <= IDLE; + end + end + end + + READ: begin + ibus_ack <= ibus_ack_i; + ibus_dat <= ibus_dat_i; + if (ibus_ack_i | ibus_err_i) begin + ibus_req <= 0; + state <= IDLE; + end + end + + TLB_RELOAD: begin + if (ctrl_branch_exception_i) + exception_while_tlb_reload <= 1; + + ibus_adr <= tlb_reload_addr; + tlb_reload_data <= ibus_dat_i; + tlb_reload_ack <= ibus_ack_i & tlb_reload_req; + + if (!tlb_reload_req) + state <= IDLE; + + ibus_req <= tlb_reload_req; + if (ibus_ack_i | tlb_reload_ack) + ibus_req <= 0; + end + + default: + state <= IDLE; + endcase // case (state) + + if (rst) begin + ibus_req <= 0; + state <= IDLE; + end + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + ic_enable_r <= 0; + else if (ic_enable & !ibus_req) + ic_enable_r <= 1; + else if (!ic_enable & !ic_refill) + ic_enable_r <= 0; + + assign ic_enabled = ic_enable & ic_enable_r; + assign ic_addr = (addr_valid | du_restart_i) ? pc_addr : pc_fetch; + assign ic_addr_match = immu_enable_i ? immu_phys_addr : pc_fetch; + assign ic_refill_allowed = (!((tlb_miss | pagefault) & immu_enable_i) & + !ctrl_branch_exception_i & !pipeline_flush_i & + !mispredict_stall | doing_rfe_i) & + !tlb_reload_busy & !immu_busy; + + assign ic_req = padv_i & !decode_except_ibus_err_o & + !decode_except_itlb_miss_o & !except_itlb_miss & + !decode_except_ipagefault_o & !except_ipagefault & + ic_access & ic_refill_allowed; + +generate +if (FEATURE_INSTRUCTIONCACHE!="NONE") begin : icache_gen + if (OPTION_ICACHE_LIMIT_WIDTH == OPTION_OPERAND_WIDTH) begin + assign ic_access = ic_enabled & + !(immu_cache_inhibit & immu_enable_i); + end else if (OPTION_ICACHE_LIMIT_WIDTH < OPTION_OPERAND_WIDTH) begin + assign ic_access = ic_enabled & + ic_addr_match[OPTION_OPERAND_WIDTH-1: + OPTION_ICACHE_LIMIT_WIDTH] == 0 & + !(immu_cache_inhibit & immu_enable_i); + end else begin + initial begin + $display("ERROR: OPTION_ICACHE_LIMIT_WIDTH > OPTION_OPERAND_WIDTH"); + $finish(); + end + end + + /* mor1kx_icache AUTO_TEMPLATE ( + // Outputs + .cpu_ack_o (ic_ack), + .cpu_dat_o (ic_dat[OPTION_OPERAND_WIDTH-1:0]), + .spr_bus_dat_o (spr_bus_dat_ic_o), + .spr_bus_ack_o (spr_bus_ack_ic_o), + .refill_o (ic_refill), + .refill_req_o (ic_refill_req), + .refill_done_o (ic_refill_done), + .invalidate_o (ic_invalidate), + // Inputs + .rst (rst), + .ic_imem_err_i (imem_err), + .ic_access_i (ic_access), + .cpu_adr_i (ic_addr), + .cpu_adr_match_i (ic_addr_match), + .cpu_req_i (ic_req), + .wradr_i (ibus_adr), + .wrdat_i (ibus_dat_i), + .we_i (ibus_ack_i), + );*/ + + mor1kx_icache + #( + .OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH), + .OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH), + .OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS), + .OPTION_ICACHE_LIMIT_WIDTH(OPTION_ICACHE_LIMIT_WIDTH) + ) + mor1kx_icache + (/*AUTOINST*/ + // Outputs + .refill_o (ic_refill), // Templated + .refill_req_o (ic_refill_req), // Templated + .refill_done_o (ic_refill_done), // Templated + .invalidate_o (ic_invalidate), // Templated + .cpu_ack_o (ic_ack), // Templated + .cpu_dat_o (ic_dat[OPTION_OPERAND_WIDTH-1:0]), // Templated + .spr_bus_dat_o (spr_bus_dat_ic_o), // Templated + .spr_bus_ack_o (spr_bus_ack_ic_o), // Templated + // Inputs + .clk (clk), + .rst (rst), // Templated + .ic_imem_err_i (imem_err), + .ic_access_i (ic_access), // Templated + .cpu_adr_i (ic_addr), // Templated + .cpu_adr_match_i (ic_addr_match), // Templated + .cpu_req_i (ic_req), // Templated + .wradr_i (ibus_adr), // Templated + .wrdat_i (ibus_dat_i), // Templated + .we_i (ibus_ack_i), // Templated + .spr_bus_addr_i (spr_bus_addr_i[15:0]), + .spr_bus_we_i (spr_bus_we_i), + .spr_bus_stb_i (spr_bus_stb_i), + .spr_bus_dat_i (spr_bus_dat_i[OPTION_OPERAND_WIDTH-1:0])); +end else begin // block: icache_gen + assign ic_access = 0; + assign ic_refill = 0; + assign ic_refill_done = 0; + assign ic_ack = 0; +end +endgenerate + +generate +if (FEATURE_IMMU!="NONE") begin : immu_gen + wire [OPTION_OPERAND_WIDTH-1:0] virt_addr = ic_addr; + wire immu_spr_bus_stb; + wire immu_enable; + // small hack to delay immu spr reads by one cycle + // ideally the spr accesses should work so that the address is presented + // in execute stage and the delayed data should be available in control + // stage, but this is not how things currently work. + assign immu_spr_bus_stb = spr_bus_stb_i & (!padv_ctrl_i | spr_bus_we_i); + + assign immu_enable = immu_enable_i & !pipeline_flush_i & !mispredict_stall; + + /* mor1kx_immu AUTO_TEMPLATE ( + .enable_i (immu_enable), + .busy_o (immu_busy), + .phys_addr_o (immu_phys_addr), + .cache_inhibit_o (immu_cache_inhibit), + .tlb_miss_o (tlb_miss), + .tlb_reload_req_o (tlb_reload_req), + .tlb_reload_addr_o (tlb_reload_addr), + .tlb_reload_pagefault_o (tlb_reload_pagefault), + .tlb_reload_ack_i (tlb_reload_ack), + .tlb_reload_data_i (tlb_reload_data), + .tlb_reload_busy_o (tlb_reload_busy), + .tlb_reload_pagefault_clear_i (except_ipagefault_clear), + .pagefault_o (pagefault), + .spr_bus_dat_o (spr_bus_dat_immu_o), + .spr_bus_ack_o (spr_bus_ack_immu_o), + .spr_bus_stb_i (immu_spr_bus_stb), + .virt_addr_i (virt_addr), + .virt_addr_match_i (pc_fetch), + ); */ + mor1kx_immu + #( + .FEATURE_IMMU_HW_TLB_RELOAD(FEATURE_IMMU_HW_TLB_RELOAD), + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_IMMU_SET_WIDTH(OPTION_IMMU_SET_WIDTH), + .OPTION_IMMU_WAYS(OPTION_IMMU_WAYS) + ) + mor1kx_immu + (/*AUTOINST*/ + // Outputs + .busy_o (immu_busy), // Templated + .phys_addr_o (immu_phys_addr), // Templated + .cache_inhibit_o (immu_cache_inhibit), // Templated + .tlb_miss_o (tlb_miss), // Templated + .pagefault_o (pagefault), // Templated + .tlb_reload_req_o (tlb_reload_req), // Templated + .tlb_reload_addr_o (tlb_reload_addr), // Templated + .tlb_reload_pagefault_o (tlb_reload_pagefault), // Templated + .tlb_reload_busy_o (tlb_reload_busy), // Templated + .spr_bus_dat_o (spr_bus_dat_immu_o), // Templated + .spr_bus_ack_o (spr_bus_ack_immu_o), // Templated + // Inputs + .clk (clk), + .rst (rst), + .enable_i (immu_enable), // Templated + .virt_addr_i (virt_addr), // Templated + .virt_addr_match_i (pc_fetch), // Templated + .supervisor_mode_i (supervisor_mode_i), + .tlb_reload_ack_i (tlb_reload_ack), // Templated + .tlb_reload_data_i (tlb_reload_data), // Templated + .tlb_reload_pagefault_clear_i (except_ipagefault_clear), // Templated + .spr_bus_addr_i (spr_bus_addr_i[15:0]), + .spr_bus_we_i (spr_bus_we_i), + .spr_bus_stb_i (immu_spr_bus_stb), // Templated + .spr_bus_dat_i (spr_bus_dat_i[OPTION_OPERAND_WIDTH-1:0])); +end else begin + assign immu_cache_inhibit = 0; + assign immu_busy = 0; + assign tlb_miss = 0; + assign pagefault = 0; + assign tlb_reload_busy = 0; + assign tlb_reload_req = 0; + assign tlb_reload_pagefault = 0; +end +endgenerate + +endmodule // mor1kx_fetch_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_espresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_espresso.v new file mode 100644 index 0000000..e44913e --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_espresso.v @@ -0,0 +1,287 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx espresso fetch unit + + Fetch insn, advance PC (or take new branch address) on padv_i. + + What we might want to do is have a 1-insn buffer here, so when the current + insn is fetched, but the main pipeline doesn't want it yet + + indicate ibus errors + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_fetch_espresso + (/*AUTOARG*/ + // Outputs + ibus_adr_o, ibus_req_o, ibus_burst_o, decode_insn_o, + next_fetch_done_o, fetch_rfa_adr_o, fetch_rfb_adr_o, pc_fetch_o, + pc_fetch_next_o, decode_except_ibus_err_o, fetch_advancing_o, + // Inputs + clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, padv_i, + branch_occur_i, branch_dest_i, du_restart_i, du_restart_pc_i, + fetch_take_exception_branch_i, execute_waiting_i, du_stall_i, + stepping_i + ); + + parameter OPTION_OPERAND_WIDTH = 32; + parameter OPTION_RF_ADDR_WIDTH = 5; + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}; + + + input clk, rst; + + // interface to ibus + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o; + output ibus_req_o; + output ibus_burst_o; + input ibus_err_i; + input ibus_ack_i; + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i; + + // pipeline control input + input padv_i; + + // interface to decode unit + output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o; + // Indication to pipeline control that the fetch is valid + output next_fetch_done_o; + + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o; + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o; + + // Signal back to the control + output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_o; + output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o; + + + // branch/jump indication + input branch_occur_i; + input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i; + + // restart signals from debug unit + input du_restart_i; + input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i; + + input fetch_take_exception_branch_i; + + input execute_waiting_i; + + // CPU is stalled + input du_stall_i; + + // We're single stepping - this should cause us to fetch only a single insn + input stepping_i; + + + // instruction ibus error indication out + output reg decode_except_ibus_err_o; + + output fetch_advancing_o; + + // registers + reg [OPTION_OPERAND_WIDTH-1:0] pc_fetch; + reg fetch_req; + reg next_insn_buffered; + reg [OPTION_OPERAND_WIDTH-1:0] insn_buffer; + reg branch_occur_r; + reg bus_access_done_re_r; + reg advancing_into_branch; + reg bus_access_done_r; + reg wait_for_exception_after_ibus_err; + + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next; + wire bus_access_done; + wire bus_access_done_fe; + wire branch_occur_re; + wire awkward_transition_to_branch_target; + wire taking_branch; + wire jal_buffered; + wire retain_fetch_pc; + + assign taking_branch = branch_occur_i & padv_i; + + assign bus_access_done = (ibus_ack_i | ibus_err_i) & !(taking_branch); + + assign pc_fetch_next = pc_fetch + 4; + + assign ibus_adr_o = pc_fetch; + assign ibus_req_o = fetch_req; + assign ibus_burst_o = 0; + + assign fetch_advancing_o = (padv_i | fetch_take_exception_branch_i | + stepping_i) & + next_fetch_done_o; + + // Early RF address fetch + assign fetch_rfa_adr_o = insn_buffer[`OR1K_RA_SELECT]; + assign fetch_rfb_adr_o = insn_buffer[`OR1K_RB_SELECT]; + + assign jal_buffered = insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JALR || + insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JAL; + + assign retain_fetch_pc = jal_buffered & bus_access_done; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + pc_fetch <= OPTION_RESET_PC; + else if (fetch_take_exception_branch_i | + (((bus_access_done & !ibus_err_i) | taking_branch) & + (!execute_waiting_i | !next_insn_buffered) & + !retain_fetch_pc) | + awkward_transition_to_branch_target | + du_restart_i) + // next PC - are we going somewhere else or advancing? + pc_fetch <= du_restart_i ? du_restart_pc_i : + (fetch_take_exception_branch_i | taking_branch) ? + branch_dest_i : pc_fetch_next; + + // Actually goes to pipeline control + assign pc_fetch_o = pc_fetch; + assign pc_fetch_next_o = pc_fetch_next; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetch_req <= 1; + else if (fetch_take_exception_branch_i | du_restart_i) + fetch_req <= 1; + else if (padv_i) + // Force de-assert of req signal when branching. + // This is to stop (ironically) the case where we've got the + // instruction we're branching to already coming in on the bus, + // which we usually don't assume will happen. + // TODO: fix things so that we don't have to force a penalty to make + // it work properly. + fetch_req <= !branch_occur_i & !du_stall_i; + else if (du_stall_i) + fetch_req <= fetch_req & !bus_access_done; + else if (!fetch_req & !execute_waiting_i & + !wait_for_exception_after_ibus_err & !retain_fetch_pc & + !du_stall_i & !stepping_i) + fetch_req <= 1; + else if (bus_access_done & (fetch_take_exception_branch_i | + execute_waiting_i | ibus_err_i | stepping_i)) + fetch_req <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + begin + bus_access_done_r <= 0; + branch_occur_r <= 0; + end + else + begin + bus_access_done_r <= bus_access_done; + branch_occur_r <= branch_occur_i; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + advancing_into_branch <= 0; + else + advancing_into_branch <= fetch_advancing_o & branch_occur_i; + + assign next_fetch_done_o = (bus_access_done_r | next_insn_buffered) & + // Whenever we've just changed the fetch PC to + // take a branch this will gate off any ACKs we + // might get (legit or otherwise) from where we're + // getting our instructions from (bus/cache). + !(advancing_into_branch); + + assign branch_occur_re = branch_occur_i & !branch_occur_r; + + /* When this occurs we had the insn burst stream finish just as we + had a new branch address requested. Because the control logic will + immediately continue onto the delay slot instruction, the branch target + is only valid for 1 cycle. The PC out to the bus/cache will then need + to change 1 cycle after it requested the insn after the delay slot. + This is annoying for the bus control/cache logic, but should result in + less cycles wasted fetching something we don't need, and as well reduce + the number of flops as we don't need to save the target PC which we had + for only 1 cycle */ + assign awkward_transition_to_branch_target = branch_occur_re & + bus_access_done_fe; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (fetch_take_exception_branch_i | (du_stall_i & !execute_waiting_i)) + // Put a NOP in the pipeline when starting exception - remove any state + // which may be causing the exception + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if ((padv_i & ( + bus_access_done_r | + bus_access_done | + next_insn_buffered + ) & + !branch_occur_r ) | + // This case is when we stalled to get the delay-slot instruction + // and we don't get enough padv to push it through the buffer + (branch_occur_i & padv_i & bus_access_done_re_r) | + (bus_access_done_fe & stepping_i)) + decode_insn_o <= insn_buffer; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_except_ibus_err_o <= 0; + else if ((padv_i | fetch_take_exception_branch_i) & branch_occur_i | + du_stall_i) + decode_except_ibus_err_o <= 0; + else if (fetch_req) + decode_except_ibus_err_o <= ibus_err_i; + + // Register rising edge on bus_access_done + always @(posedge clk `OR_ASYNC_RST) + if (rst) + bus_access_done_re_r <= 0; + else + bus_access_done_re_r <= bus_access_done & !bus_access_done_r; + + assign bus_access_done_fe = !bus_access_done & bus_access_done_r; + + /* If insn_buffer contains the next insn we need, save that information + here */ + always @(posedge clk `OR_ASYNC_RST) + if (rst) + next_insn_buffered <= 0; + else if (fetch_take_exception_branch_i) + next_insn_buffered <= 0; + else if (padv_i) + // Next instruction is usually buffered when we've got bus ack and + // pipeline advance, except when we're branching (usually throw + // away the fetch when branch is being indicated) + next_insn_buffered <= ibus_ack_i & !branch_occur_i; + else if (ibus_ack_i & execute_waiting_i) + next_insn_buffered <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + insn_buffer <= {`OR1K_OPCODE_NOP,26'd0}; + else if (ibus_ack_i & (!execute_waiting_i | !next_insn_buffered) & + // Don't buffer instruction after delay slot instruction + // (usually we're receiving it as taking branch is asserted) + // it could be another jump instruction and having it in + // the insn_buffer has annoying side-effects. + !taking_branch) + insn_buffer <= ibus_dat_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + wait_for_exception_after_ibus_err <= 0; + else if (fetch_take_exception_branch_i) + wait_for_exception_after_ibus_err <= 0; + else if (ibus_err_i) + wait_for_exception_after_ibus_err <= 1; + +endmodule // mor1kx_fetch_espresso diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_prontoespresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_prontoespresso.v new file mode 100644 index 0000000..ec187e2 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_prontoespresso.v @@ -0,0 +1,549 @@ + /* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx pronto espresso fetch unit + + Fetch insn, advance PC (or take new branch address) on padv_i. + + What we might want to do is have a 1-insn buffer here, so when the current + insn is fetched, but the main pipeline doesn't want it yet + + indicate ibus errors + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_fetch_prontoespresso + (/*AUTOARG*/ + // Outputs + ibus_adr_o, ibus_req_o, ibus_burst_o, decode_insn_o, fetched_pc_o, + fetch_ready_o, fetch_rfa_adr_o, fetch_rfb_adr_o, fetch_rf_re_o, + pc_fetch_next_o, decode_except_ibus_err_o, fetch_sleep_o, + fetch_quick_branch_o, spr_bus_dat_ic_o, spr_bus_ack_ic_o, + // Inputs + clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, ic_enable, padv_i, + branch_occur_i, branch_dest_i, ctrl_insn_done_i, du_restart_i, + du_restart_pc_i, fetch_take_exception_branch_i, execute_waiting_i, + du_stall_i, stepping_i, flag_i, flag_clear_i, flag_set_i, + spr_bus_addr_i, spr_bus_we_i, spr_bus_stb_i, spr_bus_dat_i + ); + + parameter OPTION_OPERAND_WIDTH = 32; + parameter OPTION_RF_ADDR_WIDTH = 5; + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}; + // Mini cache registers, signals + parameter FEATURE_INSTRUCTIONCACHE = "NONE"; + parameter OPTION_ICACHE_BLOCK_WIDTH = 3; // 3 for 8 words + parameter FEATURE_QUICK_BRANCH_DETECTION = "NONE"; + + input clk, rst; + + // interface to ibus + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o; + output ibus_req_o; + output ibus_burst_o; + input ibus_err_i; + input ibus_ack_i; + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i; + input ic_enable; + + // pipeline control input + input padv_i; + + // interface to decode unit + output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o; + + // PC of the current instruction, SPR_PPC basically + output [OPTION_OPERAND_WIDTH-1:0] fetched_pc_o; + + // Indication to pipeline control that the fetch stage is ready + output fetch_ready_o; + + // Signals going to register file to do the read access as we + // register the instruction out to the decode stage + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o; + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o; + output fetch_rf_re_o; + + // Signal back to the control + output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o; + + + // branch/jump indication + input branch_occur_i; + input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i; + + // Instruction "retire" indication from control stage + input ctrl_insn_done_i; + + // restart signals from debug unit + input du_restart_i; + input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i; + + input fetch_take_exception_branch_i; + + input execute_waiting_i; + + // CPU is stalled + input du_stall_i; + + // We're single stepping - this should cause us to fetch only a single insn + input stepping_i; + + // Flag status information + input flag_i, flag_clear_i, flag_set_i; + + // instruction ibus error indication out + output reg decode_except_ibus_err_o; + + // fetch sleep mode enabled (due to jump-to-self instruction + output fetch_sleep_o; + + // Indicate to the control stage that we had zero delay fetching + // the branch target address + output fetch_quick_branch_o; + + // SPR interface + input [15:0] spr_bus_addr_i; + input spr_bus_we_i; + input spr_bus_stb_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i; + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_o; + output spr_bus_ack_ic_o; + + + // Registers + reg [OPTION_OPERAND_WIDTH-1:0] pc; + reg [OPTION_OPERAND_WIDTH-1:0] fetched_pc; + reg fetch_req; + reg next_insn_will_branch; + reg have_early_pc_next; + reg jump_insn_in_decode; + reg took_early_calc_pc; + reg [1:0] took_early_calc_pc_r; + reg padv_r; + reg took_branch; + reg took_branch_r; + reg execute_waiting_r; + reg sleep; + reg complete_current_req; + reg no_rf_read; + reg new_insn_wasnt_ready; + reg took_early_pc_onto_cache_hit; + reg waited_with_early_pc_onto_cache_hit; + + // Wires + wire [`OR1K_INSN_WIDTH-1:0] new_insn; + wire new_insn_ready; + wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next; + wire [OPTION_OPERAND_WIDTH-1:0] pc_plus_four; + wire [OPTION_OPERAND_WIDTH-1:0] early_pc_next; + wire padv_deasserted; + wire padv_asserted; + wire [`OR1K_OPCODE_WIDTH-1:0] next_insn_opcode; + wire will_go_to_sleep; + wire mini_cache_hit; + wire mini_cache_hit_ungated; + wire [`OR1K_INSN_WIDTH-1:0] mini_cache_insn; + wire hold_decode_output; + wire next_instruction_to_decode_condition; + + assign pc_plus_four = pc + 4; + + assign pc_fetch_next = have_early_pc_next ? + early_pc_next : pc_plus_four; + + assign ibus_adr_o = pc; + assign ibus_req_o = (fetch_req & !(fetch_take_exception_branch_i/* | branch_occur_i*/) + // This is needed in the case that: + // 1. a burst just finished and ack in went low because of this + // 2. the instruction we just ACKed is a multicycle insn so the + // execute_waiting_i goes high, but the bus interface will have + // already put out the request onto the bus. It causes a bug + // if we deassert the req from here 1 cycle later, so put this + // signal into the assign logic so that the first cycle of it + // causes req to go low, after which fetch_req is deasserted + // and should handle it + & !(execute_waiting_i & fetch_req) + & !mini_cache_hit_ungated) | + complete_current_req; + assign ibus_burst_o = 0; + + assign fetch_ready_o = new_insn_ready | jump_insn_in_decode | ibus_err_i; + + assign pc_fetch_next_o = pc_fetch_next; + + assign new_insn = mini_cache_hit ? mini_cache_insn : ibus_dat_i; + + assign new_insn_ready = mini_cache_hit | ibus_ack_i; + + // Register file control + assign fetch_rfa_adr_o = new_insn_ready ? new_insn[`OR1K_RA_SELECT] : 0; + assign fetch_rfb_adr_o = new_insn_ready ? new_insn[`OR1K_RB_SELECT] : 0; + assign fetch_rf_re_o = new_insn_ready & (padv_i | stepping_i) & + !(no_rf_read | hold_decode_output); + + // Pick out opcode of next instruction to go to decode stage + assign next_insn_opcode = new_insn[`OR1K_OPCODE_SELECT]; + + // Can calculate next PC based on instruction coming in + assign early_pc_next = {OPTION_OPERAND_WIDTH{have_early_pc_next}} & + ({{4{new_insn[25]}}, + new_insn[`OR1K_JUMPBRANCH_IMMEDIATE_SELECT], + 2'b00} + pc); + + assign will_go_to_sleep = have_early_pc_next & + (early_pc_next == pc); + + assign fetch_sleep_o = sleep; + + // The pipeline advance signal deasserted for the instruction + // we just put out, and we're still attempting to fetch. This should + // result in a deassert cycle on the request signal out to the bus. + // But, we don't want this to indicate when padv_i was deasserted for + // a branch, because we will know about that, we just want this to + // indicate it was deasserted for other reasons. + assign padv_deasserted = padv_r & !padv_i & fetch_req & !took_branch; + + assign padv_asserted = !padv_r & padv_i; + + // This makes us hold the decode stage output for an additional + // cycle when we've already got the next instruction in the + // register output to the decode stage, but the pipeline has + // stalled. + assign hold_decode_output = (padv_asserted & + mini_cache_hit & took_branch_r & + !new_insn_wasnt_ready & + took_early_calc_pc_r[1]) || + waited_with_early_pc_onto_cache_hit; + always @* + if (new_insn_ready) + case (next_insn_opcode) + `OR1K_OPCODE_J, + `OR1K_OPCODE_JAL: begin + have_early_pc_next = 1; + next_insn_will_branch = 1; + no_rf_read = 1; + end + `OR1K_OPCODE_JR, + `OR1K_OPCODE_JALR: begin + have_early_pc_next = 0; + next_insn_will_branch = 1; + no_rf_read = 0; + end + `OR1K_OPCODE_BNF: begin + have_early_pc_next = !(flag_i | flag_set_i) | flag_clear_i; + next_insn_will_branch = !(flag_i | flag_set_i) | flag_clear_i; + no_rf_read = 1; + end + `OR1K_OPCODE_BF: begin + have_early_pc_next = !(!flag_i | flag_clear_i) |flag_set_i; + next_insn_will_branch = !(!flag_i | flag_clear_i) |flag_set_i; + no_rf_read = 1; + end + `OR1K_OPCODE_SYSTRAPSYNC, + `OR1K_OPCODE_RFE: begin + have_early_pc_next = 0; + next_insn_will_branch = 1; + no_rf_read = 1; + end + default: begin + have_early_pc_next = 0; + next_insn_will_branch = 0; + no_rf_read = 0; + end + endcase // case (next_insn_opcode) + else + begin + have_early_pc_next = 0; + next_insn_will_branch = 0; + no_rf_read = 0; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + begin + pc <= OPTION_RESET_PC; + fetched_pc <= OPTION_RESET_PC; + end + else if (branch_occur_i & !took_early_calc_pc) + begin + pc <= branch_dest_i; + end + else if (fetch_take_exception_branch_i & !du_stall_i) + begin + pc <= branch_dest_i; + end + else if (new_insn_ready & (padv_i | stepping_i) & + !hold_decode_output) + begin + pc <= pc_fetch_next_o; + fetched_pc <= pc; + end + else if (du_restart_i) + begin + pc <= du_restart_pc_i; + end + else if (fetch_take_exception_branch_i & du_stall_i) + begin + pc <= du_restart_pc_i; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + new_insn_wasnt_ready <= 0; + else if (branch_occur_i & !took_early_calc_pc) + new_insn_wasnt_ready <= !new_insn_ready; + else if (new_insn_ready & (padv_i | stepping_i) & !padv_deasserted) + new_insn_wasnt_ready <= 0; + + assign fetched_pc_o = fetched_pc; + + assign next_instruction_to_decode_condition = new_insn_ready & + (padv_i | stepping_i) & + !padv_deasserted & + !hold_decode_output & + !((branch_occur_i & padv_i & + !took_early_calc_pc) | + fetch_take_exception_branch_i); + + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (sleep | du_stall_i) + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (next_instruction_to_decode_condition) + decode_insn_o <= new_insn; + else if (branch_occur_i & padv_i) + // We've just taken a branch, put a nop on the + // instruction to the rest of the pipeline + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (fetch_take_exception_branch_i) + // Exception was just taken, get rid of whatever + // we're outputting + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (took_early_calc_pc) + // This covers the case where, for some reason, + // we don't get the branch_occur_i + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (ctrl_insn_done_i & !new_insn_ready) + // If the current instruction in the decode stage is retired + // then let's put a no-op back in the pipeline + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetch_req <= 1'b1; + else if (fetch_req & stepping_i & new_insn_ready) + // Deassert on ack + fetch_req <= 1'b0; + else if (!fetch_req & du_stall_i) + fetch_req <= 1'b0; + else if (ibus_err_i) + fetch_req <= 1'b0; + else if (sleep) + fetch_req <= 1'b0; + else if (next_insn_will_branch) + fetch_req <= 1'b0; + else if (execute_waiting_i) + /* + Put the execute wait signal through this register to break any long + chains of logic from the execute stage (LSU, ALU) which could result + from using it to just gate the req signal out. + TODO - actually check the impact of gating fetch_req_o with + execute_waiting_i + */ + fetch_req <= 1'b0; + else if (padv_deasserted) + fetch_req <= 1'b0; + else if (mini_cache_hit_ungated) + // We'll get this ungated signal immediately after we've + // terminated a burst, so we'll know if we really should + // fetch the branch target or whether it's in cache. + fetch_req <= 1'b0; + else + fetch_req <= 1'b1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + took_early_pc_onto_cache_hit <= 0; + else if (padv_i) + took_early_pc_onto_cache_hit <= took_early_calc_pc & mini_cache_hit & + !fetch_take_exception_branch_i; + else if (ctrl_insn_done_i) + took_early_pc_onto_cache_hit <= 0; + + // This register signifies when: + // a) we had a branch to somewhere where we took the early calculated PC and + // that branch location was a hit in the cache + // b) the subsequent instruction wasn't in the cache, so we put the + // insn out to the decode stage, but wasn't immediately retired by the + // control stage, so we must wait until the next instruction is ready + // before it will be completed by the control stage + always @(posedge clk `OR_ASYNC_RST) + if (rst) + waited_with_early_pc_onto_cache_hit <= 0; + else if (took_branch_r | padv_i) + waited_with_early_pc_onto_cache_hit <= took_early_pc_onto_cache_hit & + !fetch_ready_o; + else if (ctrl_insn_done_i) + waited_with_early_pc_onto_cache_hit <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + jump_insn_in_decode <= 0; + else if (sleep) + jump_insn_in_decode <= 0; + else if (!jump_insn_in_decode & next_insn_will_branch & new_insn_ready & padv_i) + jump_insn_in_decode <= 1; + else + jump_insn_in_decode <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + took_early_calc_pc <= 0; + else if (sleep) + took_early_calc_pc <= 0; + else if (next_insn_will_branch & have_early_pc_next & padv_i) + took_early_calc_pc <= 1; + else + took_early_calc_pc <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + took_early_calc_pc_r <= 0; + else + took_early_calc_pc_r <= {took_early_calc_pc_r[0], took_early_calc_pc}; + + always @(posedge clk) + padv_r <= padv_i; + + /* Whether it was early branch or not, we've branched, and this + signal will be asserted the cycle after. */ + always @(posedge clk) + begin + took_branch <= (branch_occur_i | fetch_take_exception_branch_i) & + fetch_ready_o; + took_branch_r <= took_branch; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_except_ibus_err_o <= 0; + else if ((padv_i | fetch_take_exception_branch_i) & + branch_occur_i | du_stall_i) + decode_except_ibus_err_o <= 0; + else if (fetch_req) + decode_except_ibus_err_o <= ibus_err_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + sleep <= 1'b0; + else if (fetch_take_exception_branch_i | du_stall_i) + sleep <= 1'b0; + else if (will_go_to_sleep & !stepping_i) + sleep <= 1'b1; + + // A signal to make sure the request out line stays high + // if we've already issued an instruction request and padv_i + // goes low. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + complete_current_req <= 0; + else if (fetch_req & padv_deasserted & !new_insn_ready) + complete_current_req <= 1; + else if (new_insn_ready & complete_current_req) + complete_current_req <= 0; + + // Mini cache logic + genvar i; + generate + /* verilator lint_off WIDTH */ + if (FEATURE_INSTRUCTIONCACHE != "ENABLED") + /* verilator lint_on WIDTH */ + begin : no_mini_cache + assign mini_cache_hit = 0; + assign mini_cache_hit_ungated = 0; + assign mini_cache_insn = {`OR1K_INSN_WIDTH{1'b0}}; + assign fetch_quick_branch_o = 0; + end + else + begin : mini_cache + localparam NUMBER_MINI_CACHE_WORDS = (1< + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_fetch_tcm_prontoespresso + (/*AUTOARG*/ + // Outputs + ibus_adr_o, ibus_req_o, decode_insn_o, fetched_pc_o, fetch_ready_o, + fetch_rfa_adr_o, fetch_rfb_adr_o, fetch_rf_re_o, pc_fetch_next_o, + decode_except_ibus_err_o, fetch_sleep_o, + // Inputs + clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, padv_i, + branch_occur_i, branch_dest_i, du_restart_i, du_restart_pc_i, + fetch_take_exception_branch_i, execute_waiting_i, du_stall_i, + stepping_i, flag_i, flag_clear_i, flag_set_i + ); + + parameter OPTION_OPERAND_WIDTH = 32; + parameter OPTION_RF_ADDR_WIDTH = 5; + parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}}, + `OR1K_RESET_VECTOR,8'd0}; + + input clk, rst; + + // interface to ibus + output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o; + output ibus_req_o; + input ibus_err_i; + input ibus_ack_i; + input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i; + + // pipeline control input + input padv_i; + + // interface to decode unit + output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o; + + // PC of the current instruction, SPR_PPC basically + output reg [OPTION_OPERAND_WIDTH-1:0] fetched_pc_o; + + // Indication to pipeline control that the fetch stage is ready + output fetch_ready_o; + + // Signals going to register file to do the read access as we + // register the instruction out to the decode stage + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o; + output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o; + output fetch_rf_re_o; + + // Signal back to the control which pc we're goint to + // deliver next + output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o; + + + // branch/jump indication + input branch_occur_i; + input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i; + + // restart signals from debug unit + input du_restart_i; + input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i; + + input fetch_take_exception_branch_i; + + input execute_waiting_i; + + // CPU is stalled + input du_stall_i; + + // We're single stepping - this should cause us to fetch only a single insn + input stepping_i; + + // Flag status information + input flag_i, flag_clear_i, flag_set_i; + + // instruction ibus error indication out + output reg decode_except_ibus_err_o; + + // fetch sleep mode enabled (due to jump-to-self instruction + output fetch_sleep_o; + + + reg [OPTION_OPERAND_WIDTH-1:0] current_bus_pc; + wire [OPTION_OPERAND_WIDTH-1:0] next_bus_pc; + reg [OPTION_OPERAND_WIDTH-1:0] insn_buffer; + + wire first_bus_req_cycle; + reg addr_pipelined; + reg bus_req, bus_req_r; + wire [`OR1K_OPCODE_WIDTH-1:0] next_insn_opcode; + reg next_insn_will_branch; + reg jump_insn_in_decode; + reg just_took_branch_addr; + wire taking_branch_addr; + reg insn_from_branch_on_input; + reg insn_from_branch_in_pipeline; + reg execute_waiting_r; + wire execute_waiting_deasserted; + wire execute_waiting_asserted; + reg execute_waiting_asserted_r; + wire execute_waited_single_cycle; + reg just_waited_single_cycle; + reg just_waited_single_cycle_r; + reg insn_buffered; + wire buffered_insn_is_jump; + reg push_buffered_jump_through_pipeline; + wire will_go_to_sleep; + reg sleep; + reg fetch_take_exception_branch_r; + reg [3:0] padv_r; + wire long_stall; + + + assign next_bus_pc = current_bus_pc + 4; + assign ibus_adr_o = addr_pipelined ? next_bus_pc : current_bus_pc; + + assign pc_fetch_next_o = ibus_adr_o; + + assign ibus_req_o = bus_req & !(stepping_i & ibus_ack_i) | + (execute_waiting_deasserted & + !(insn_buffered & next_insn_will_branch)) | + fetch_take_exception_branch_r; + + // Signal rising edge on bus request signal + assign first_bus_req_cycle = ibus_req_o & !bus_req_r; + + assign taking_branch_addr = (branch_occur_i & padv_i) | + fetch_take_exception_branch_i; + + assign buffered_insn_is_jump = insn_buffered & next_insn_will_branch; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + begin + current_bus_pc <= OPTION_RESET_PC; + just_took_branch_addr <= 0; + end + else if (du_restart_i) + begin + current_bus_pc <= du_restart_pc_i; + just_took_branch_addr <= 0; + end + else if (fetch_take_exception_branch_i) + begin + current_bus_pc <= branch_dest_i; + just_took_branch_addr <= 1; + end + else if (branch_occur_i & padv_i) + begin + current_bus_pc <= branch_dest_i; + just_took_branch_addr <= 1; + end + else if (ibus_ack_i & (padv_i | (just_waited_single_cycle_r && + !({padv_r[0],padv_i}==2'b00))) & + !execute_waited_single_cycle & !stepping_i) + begin + current_bus_pc <= next_bus_pc; + just_took_branch_addr <= 0; + end + else if (execute_waiting_asserted & ibus_ack_i & !just_took_branch_addr) + begin + current_bus_pc <= next_bus_pc; + end + else if (just_took_branch_addr) + begin + just_took_branch_addr <= 0; + end + + else if (long_stall) + begin + // Long wait - this is a work around for an annoying bug which + // I can't solve any other way! + current_bus_pc <= fetched_pc_o + 4; + end + + // BIG assumptions here - that the read only takes a single cycle!! + always @(posedge clk `OR_ASYNC_RST) + if (rst) + begin + insn_from_branch_on_input <= 0; + insn_from_branch_in_pipeline <= 0; + end + else + begin + insn_from_branch_on_input <= just_took_branch_addr; + insn_from_branch_in_pipeline <= insn_from_branch_on_input; + end + + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + bus_req <= 1'b0; + else if (stepping_i & ibus_ack_i) + // Deassert on ack of stepping + bus_req <= 1'b0; + else if (du_stall_i) + bus_req <= 1'b0; + else if (ibus_err_i | decode_except_ibus_err_o) + bus_req <= 1'b0; + else if (sleep) + bus_req <= 1'b0; + else if (execute_waiting_i) + bus_req <= 1'b0; + else if (buffered_insn_is_jump) + bus_req <= 1'b0; + else + bus_req <= 1'b1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + bus_req_r <= 0; + else + bus_req_r <= ibus_req_o; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + addr_pipelined <= 0; + else if (ibus_err_i | decode_except_ibus_err_o | + fetch_take_exception_branch_i) + addr_pipelined <= 0; + else if (first_bus_req_cycle) + addr_pipelined <= 1; + else if (taking_branch_addr) + addr_pipelined <= 0; + else if (just_took_branch_addr) + addr_pipelined <= 1; + else if (just_waited_single_cycle) + addr_pipelined <= 1; + else if (!bus_req) + addr_pipelined <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + begin + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + fetched_pc_o <= 0; + end + else if (sleep | (du_stall_i & !execute_waiting_i)) + begin + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + end + else if (fetch_take_exception_branch_i & !du_stall_i) + begin + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + end + else if ((padv_i | stepping_i) & ibus_ack_i & (ibus_req_o | stepping_i) & + ((!jump_insn_in_decode & !just_took_branch_addr) | + (insn_from_branch_on_input)) + & !(execute_waited_single_cycle | just_waited_single_cycle)) + begin + decode_insn_o <= ibus_dat_i; + fetched_pc_o <= current_bus_pc; + end + else if (just_waited_single_cycle_r & !execute_waiting_i) + begin + decode_insn_o <= ibus_dat_i; + fetched_pc_o <= current_bus_pc; + end + else if (execute_waiting_deasserted & insn_buffered) + begin + decode_insn_o <= insn_buffer; + fetched_pc_o <= fetched_pc_o + 4; + end + else if ((jump_insn_in_decode | branch_occur_i) & padv_i) + // About to jump - remove this instruction from the pipeline + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (fetch_take_exception_branch_i) + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + else if (push_buffered_jump_through_pipeline) + decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0}; + + reg fetch_ready_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetch_ready_r <= 0; + else + fetch_ready_r <= fetch_ready_o; + + assign fetch_ready_o = (ibus_ack_i | insn_buffered ) & + !(just_took_branch_addr) & + !(just_waited_single_cycle) & + !du_stall_i | + push_buffered_jump_through_pipeline ; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + decode_except_ibus_err_o <= 0; + else if ((padv_i | fetch_take_exception_branch_i) & + branch_occur_i | du_stall_i) + decode_except_ibus_err_o <= 0; + else if (bus_req) + decode_except_ibus_err_o <= ibus_err_i; + + assign fetch_sleep_o = sleep; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_waiting_r <= 0; + else + execute_waiting_r <= execute_waiting_i; + + assign execute_waiting_deasserted = !execute_waiting_i & execute_waiting_r; + assign execute_waiting_asserted = execute_waiting_i & !execute_waiting_r; + + + // Register file control + assign fetch_rfa_adr_o = insn_buffered ? insn_buffer[`OR1K_RA_SELECT] : + ibus_dat_i[`OR1K_RA_SELECT]; + assign fetch_rfb_adr_o = insn_buffered ? insn_buffer[`OR1K_RB_SELECT] : + ibus_dat_i[`OR1K_RB_SELECT]; + assign fetch_rf_re_o = (ibus_ack_i | execute_waiting_deasserted) & + (padv_i | stepping_i); + + // Pick out opcode of next instruction to go to decode stage + assign next_insn_opcode = insn_buffered ? + insn_buffer[`OR1K_OPCODE_SELECT] : + ibus_dat_i[`OR1K_OPCODE_SELECT]; + + always @* + if ((ibus_ack_i & !just_took_branch_addr) | insn_buffered) + case (next_insn_opcode) + `OR1K_OPCODE_J, + `OR1K_OPCODE_JAL: begin + next_insn_will_branch = 1; + end + `OR1K_OPCODE_JR, + `OR1K_OPCODE_JALR: begin + next_insn_will_branch = 1; + end + `OR1K_OPCODE_BNF: begin + next_insn_will_branch = !(flag_i | flag_set_i) | flag_clear_i; + end + `OR1K_OPCODE_BF: begin + next_insn_will_branch = !(!flag_i | flag_clear_i) |flag_set_i; + end + `OR1K_OPCODE_SYSTRAPSYNC, + `OR1K_OPCODE_RFE: begin + next_insn_will_branch = 1; + end + default: begin + next_insn_will_branch = 0; + end + endcase // case (next_insn_opcode) + else + begin + next_insn_will_branch = 0; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + jump_insn_in_decode <= 0; + else if (sleep) + jump_insn_in_decode <= 0; + else if (!jump_insn_in_decode & next_insn_will_branch & ibus_ack_i) + jump_insn_in_decode <= 1; + else + jump_insn_in_decode <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + insn_buffer <= 0; + else if (execute_waiting_asserted & ibus_ack_i & !just_took_branch_addr) + insn_buffer <= ibus_dat_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + insn_buffered <= 0; + else if (execute_waiting_asserted & ibus_ack_i & !just_took_branch_addr) + insn_buffered <= 1; + else if (execute_waiting_deasserted) + insn_buffered <= 0; + else if (fetch_take_exception_branch_i) + insn_buffered <= 0; + else if (long_stall) + insn_buffered <= 0; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + push_buffered_jump_through_pipeline <= 0; + else + push_buffered_jump_through_pipeline <= buffered_insn_is_jump & + execute_waiting_deasserted; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + fetch_take_exception_branch_r <= 0; + else + fetch_take_exception_branch_r <= fetch_take_exception_branch_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + sleep <= 1'b0; + else if (fetch_take_exception_branch_i) + sleep <= 1'b0; + else if (will_go_to_sleep) + sleep <= 1'b1; + + assign will_go_to_sleep = ibus_dat_i==0 & padv_i & ibus_ack_i & + ibus_req_o & ((!jump_insn_in_decode & + !just_took_branch_addr) | + (insn_from_branch_on_input)); + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_waiting_asserted_r <= 0; + else + execute_waiting_asserted_r <= execute_waiting_asserted; + + assign execute_waited_single_cycle = execute_waiting_asserted_r & + !execute_waiting_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + begin + just_waited_single_cycle <= 0; + just_waited_single_cycle_r <= 0; + end + else + begin + just_waited_single_cycle <= execute_waited_single_cycle; + just_waited_single_cycle_r <= just_waited_single_cycle; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + padv_r <= 4'd0; + else + padv_r <= {padv_r[2:0],padv_i}; + + assign long_stall = {padv_r,padv_i}==5'b10000 && execute_waiting_i; + +endmodule // mor1kx_fetch_tcm_prontoespresso diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_icache.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_icache.v new file mode 100644 index 0000000..ecc5397 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_icache.v @@ -0,0 +1,484 @@ +/****************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Instruction cache implementation + + Copyright (C) 2012-2013 + Stefan Kristiansson + Stefan Wallentowitz + + ******************************************************************************/ + +`include "mor1kx-defines.v" + +module mor1kx_icache + #( + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_ICACHE_BLOCK_WIDTH = 5, + parameter OPTION_ICACHE_SET_WIDTH = 9, + parameter OPTION_ICACHE_WAYS = 2, + parameter OPTION_ICACHE_LIMIT_WIDTH = 32 + ) + ( + input clk, + input rst, + + input ic_imem_err_i, + input ic_access_i, + output refill_o, + output refill_req_o, + output refill_done_o, + output invalidate_o, + + // CPU Interface + output cpu_ack_o, + output reg [`OR1K_INSN_WIDTH-1:0] cpu_dat_o, + input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_i, + input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_match_i, + input cpu_req_i, + + input [OPTION_OPERAND_WIDTH-1:0] wradr_i, + input [`OR1K_INSN_WIDTH-1:0] wrdat_i, + input we_i, + + // SPR interface + input [15:0] spr_bus_addr_i, + input spr_bus_we_i, + input spr_bus_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i, + + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + output reg spr_bus_ack_o + ); + + // States + localparam IDLE = 4'b0001; + localparam READ = 4'b0010; + localparam REFILL = 4'b0100; + localparam INVALIDATE = 4'b1000; + + // Address space in bytes for a way + localparam WAY_WIDTH = OPTION_ICACHE_BLOCK_WIDTH + OPTION_ICACHE_SET_WIDTH; + /* + * Tag memory layout + * +---------------------------------------------------------+ + * (index) -> | LRU | wayN valid | wayN tag |...| way0 valid | way0 tag | + * +---------------------------------------------------------+ + */ + + // The tag is the part left of the index + localparam TAG_WIDTH = (OPTION_ICACHE_LIMIT_WIDTH - WAY_WIDTH); + + // The tag memory contains entries with OPTION_ICACHE_WAYS parts of + // each TAGMEM_WAY_WIDTH. Each of those is tag and a valid flag. + localparam TAGMEM_WAY_WIDTH = TAG_WIDTH + 1; + localparam TAGMEM_WAY_VALID = TAGMEM_WAY_WIDTH - 1; + + // Additionally, the tag memory entry contains an LRU value. The + // width of this is actually 0 for OPTION_ICACHE_LIMIT_WIDTH==1 + localparam TAG_LRU_WIDTH = OPTION_ICACHE_WAYS*(OPTION_ICACHE_WAYS-1) >> 1; + + // We have signals for the LRU which are not used for one way + // caches. To avoid signal width [-1:0] this generates [0:0] + // vectors for them, which are removed automatically then. + localparam TAG_LRU_WIDTH_BITS = (OPTION_ICACHE_WAYS >= 2) ? TAG_LRU_WIDTH : 1; + + // Compute the total sum of the entry elements + localparam TAGMEM_WIDTH = TAGMEM_WAY_WIDTH * OPTION_ICACHE_WAYS + TAG_LRU_WIDTH; + + // For convenience we define the position of the LRU in the tag + // memory entries + localparam TAG_LRU_MSB = TAGMEM_WIDTH - 1; + localparam TAG_LRU_LSB = TAG_LRU_MSB - TAG_LRU_WIDTH + 1; + + // FSM state signals + reg [3:0] state; + wire read; + wire refill; + wire invalidate; + + reg [WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH] invalidate_adr; + wire [31:0] next_refill_adr; + wire refill_done; + wire refill_hit; + reg [(1<<(OPTION_ICACHE_BLOCK_WIDTH-2))-1:0] refill_valid; + reg [(1<<(OPTION_ICACHE_BLOCK_WIDTH-2))-1:0] refill_valid_r; + + // The index we read and write from tag memory + wire [OPTION_ICACHE_SET_WIDTH-1:0] tag_rindex; + wire [OPTION_ICACHE_SET_WIDTH-1:0] tag_windex; + + // The data from the tag memory + wire [TAGMEM_WIDTH-1:0] tag_dout; + wire [TAG_LRU_WIDTH_BITS-1:0] tag_lru_out; + wire [TAGMEM_WAY_WIDTH-1:0] tag_way_out [OPTION_ICACHE_WAYS-1:0]; + + // The data to the tag memory + wire [TAGMEM_WIDTH-1:0] tag_din; + reg [TAG_LRU_WIDTH_BITS-1:0] tag_lru_in; + reg [TAGMEM_WAY_WIDTH-1:0] tag_way_in [OPTION_ICACHE_WAYS-1:0]; + + reg [TAGMEM_WAY_WIDTH-1:0] tag_way_save [OPTION_ICACHE_WAYS-1:0]; + + // Whether to write to the tag memory in this cycle + reg tag_we; + + // This is the tag we need to write to the tag memory during refill + wire [TAG_WIDTH-1:0] tag_wtag; + + // This is the tag we check against + wire [TAG_WIDTH-1:0] tag_tag; + + // Access to the way memories + wire [WAY_WIDTH-3:0] way_raddr[OPTION_ICACHE_WAYS-1:0]; + wire [WAY_WIDTH-3:0] way_waddr[OPTION_ICACHE_WAYS-1:0]; + wire [OPTION_OPERAND_WIDTH-1:0] way_din[OPTION_ICACHE_WAYS-1:0]; + wire [OPTION_OPERAND_WIDTH-1:0] way_dout[OPTION_ICACHE_WAYS-1:0]; + reg [OPTION_ICACHE_WAYS-1:0] way_we; + + // Does any way hit? + wire hit; + wire [OPTION_ICACHE_WAYS-1:0] way_hit; + + // This is the least recently used value before access the memory. + // Those are one hot encoded. + wire [OPTION_ICACHE_WAYS-1:0] lru; + + // Register that stores the LRU value from lru + reg [OPTION_ICACHE_WAYS-1:0] tag_save_lru; + + // The access vector to update the LRU history is the way that has + // a hit or is refilled. It is also one-hot encoded. + reg [OPTION_ICACHE_WAYS-1:0] access; + + // The current LRU history as read from tag memory and the update + // value after we accessed it to write back to tag memory. + wire [TAG_LRU_WIDTH_BITS-1:0] current_lru_history; + wire [TAG_LRU_WIDTH_BITS-1:0] next_lru_history; + + // Intermediate signals to ease debugging + wire [TAG_WIDTH-1:0] check_way_tag [OPTION_ICACHE_WAYS-1:0]; + wire check_way_match [OPTION_ICACHE_WAYS-1:0]; + wire check_way_valid [OPTION_ICACHE_WAYS-1:0]; + + genvar i; + + // Allowing (out of the cache line being refilled) accesses during refill + // exposes a bug somewhere, causing the Linux kernel to end up with a + // bus error UNHANDLED EXCEPTION. + // Until that is sorted out, disable it. + assign cpu_ack_o = (read /*| refill & ic_access_i*/) & hit | + refill_hit & ic_access_i; + + assign tag_rindex = cpu_adr_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH]; + /* + * The tag mem is written during reads to write the lru info and during + * refill and invalidate + */ + assign tag_windex = read ? + cpu_adr_match_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH] : + invalidate ? invalidate_adr : + wradr_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH]; + assign tag_tag = cpu_adr_match_i[OPTION_ICACHE_LIMIT_WIDTH-1:WAY_WIDTH]; + assign tag_wtag = wradr_i[OPTION_ICACHE_LIMIT_WIDTH-1:WAY_WIDTH]; + + generate + if (OPTION_ICACHE_WAYS >= 2) begin + // Multiplex the LRU history from and to tag memory + assign current_lru_history = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB]; + assign tag_din[TAG_LRU_MSB:TAG_LRU_LSB] = tag_lru_in; + assign tag_lru_out = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB]; + end + + for (i = 0; i < OPTION_ICACHE_WAYS; i=i+1) begin : ways + assign way_raddr[i] = cpu_adr_i[WAY_WIDTH-1:2]; + assign way_waddr[i] = wradr_i[WAY_WIDTH-1:2]; + assign way_din[i] = wrdat_i; + + // compare stored tag with incoming tag and check valid bit + assign check_way_tag[i] = tag_way_out[i][TAG_WIDTH-1:0]; + assign check_way_match[i] = (check_way_tag[i] == tag_tag); + assign check_way_valid[i] = tag_way_out[i][TAGMEM_WAY_VALID]; + + assign way_hit[i] = check_way_valid[i] & check_way_match[i]; + + // Multiplex the way entries in the tag memory + assign tag_din[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH] = tag_way_in[i]; + assign tag_way_out[i] = tag_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH]; + end + endgenerate + + assign hit = |way_hit; + + integer w0; + always @(*) begin + cpu_dat_o = {OPTION_OPERAND_WIDTH{1'bx}}; + + // Put correct way on the data port + for (w0 = 0; w0 < OPTION_ICACHE_WAYS; w0 = w0 + 1) begin + if (way_hit[w0] | (refill_hit & tag_save_lru[w0])) begin + cpu_dat_o = way_dout[w0]; + end + end + end + + assign next_refill_adr = (OPTION_ICACHE_BLOCK_WIDTH == 5) ? + {wradr_i[31:5], wradr_i[4:0] + 5'd4} : // 32 byte + {wradr_i[31:4], wradr_i[3:0] + 4'd4}; // 16 byte + + assign refill_done_o = refill_done; + assign refill_done = refill_valid[next_refill_adr[OPTION_ICACHE_BLOCK_WIDTH-1:2]]; + assign refill_hit = refill_valid_r[cpu_adr_match_i[OPTION_ICACHE_BLOCK_WIDTH-1:2]] & + cpu_adr_match_i[OPTION_ICACHE_LIMIT_WIDTH-1: + OPTION_ICACHE_BLOCK_WIDTH] == + wradr_i[OPTION_ICACHE_LIMIT_WIDTH-1: + OPTION_ICACHE_BLOCK_WIDTH] & + refill; + + assign refill = (state == REFILL); + assign read = (state == READ); + assign invalidate = (state == INVALIDATE); + + assign refill_o = refill; + + assign refill_req_o = read & cpu_req_i & !hit | refill; + + /* + * SPR bus interface + */ + assign invalidate_o = spr_bus_stb_i & spr_bus_we_i & + (spr_bus_addr_i == `OR1K_SPR_ICBIR_ADDR); + + /* + * Cache FSM + */ + integer w1; + always @(posedge clk `OR_ASYNC_RST) begin + refill_valid_r <= refill_valid; + spr_bus_ack_o <= 0; + case (state) + IDLE: begin + if (cpu_req_i) + state <= READ; + end + + READ: begin + if (ic_access_i) begin + if (hit) begin + state <= READ; + end else if (cpu_req_i) begin + refill_valid <= 0; + refill_valid_r <= 0; + + // Store the LRU information for correct replacement + // on refill. Always one when only one way. + tag_save_lru <= (OPTION_ICACHE_WAYS==1) | lru; + + for (w1 = 0; w1 < OPTION_ICACHE_WAYS; w1 = w1 + 1) begin + tag_way_save[w1] <= tag_way_out[w1]; + end + + state <= REFILL; + end + end else begin + state <= IDLE; + end + end + + REFILL: begin + if (we_i) begin + refill_valid[wradr_i[OPTION_ICACHE_BLOCK_WIDTH-1:2]] <= 1; + + if (refill_done) + state <= IDLE; + end + end + + INVALIDATE: begin + if (!invalidate_o) + state <= IDLE; + spr_bus_ack_o <= 1; + end + + default: + state <= IDLE; + endcase + + if (invalidate_o & !refill) begin + invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH]; + spr_bus_ack_o <= 1; + state <= INVALIDATE; + end + + if (rst) + state <= IDLE; + else if(ic_imem_err_i) + state <= IDLE; + end + + integer w2; + always @(*) begin + // Default is to keep data, don't write and don't access + tag_lru_in = tag_lru_out; + for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin + tag_way_in[w2] = tag_way_out[w2]; + end + + tag_we = 1'b0; + way_we = {(OPTION_ICACHE_WAYS){1'b0}}; + + access = {(OPTION_ICACHE_WAYS){1'b0}}; + + case (state) + READ: begin + if (hit) begin + // We got a hit. The LRU module gets the access + // information. Depending on this we update the LRU + // history in the tag. + access = way_hit; + + // This is the updated LRU history after hit + tag_lru_in = next_lru_history; + + tag_we = 1'b1; + end + end + + REFILL: begin + if (we_i) begin + // Write the data to the way that is replaced (which is + // the LRU) + way_we = tag_save_lru; + + // Access pattern + access = tag_save_lru; + + /* Invalidate the way on the first write */ + if (refill_valid == 0) begin + for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin + if (tag_save_lru[w2]) begin + tag_way_in[w2][TAGMEM_WAY_VALID] = 1'b0; + end + end + + tag_we = 1'b1; + end + + // After refill update the tag memory entry of the + // filled way with the LRU history, the tag and set + // valid to 1. + if (refill_done) begin + for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin + tag_way_in[w2] = tag_way_save[w2]; + if (tag_save_lru[w2]) begin + tag_way_in[w2] = { 1'b1, tag_wtag }; + end + end + tag_lru_in = next_lru_history; + + tag_we = 1'b1; + end + end + end + + INVALIDATE: begin + // Lazy invalidation, invalidate everything that matches tag address + tag_lru_in = 0; + for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin + tag_way_in[w2] = 0; + end + + tag_we = 1'b1; + end + + default: begin + end + endcase + end + + /* mor1kx_simple_dpram_sclk AUTO_TEMPLATE ( + // Outputs + .dout (way_dout[i][OPTION_OPERAND_WIDTH-1:0]), + // Inputs + .raddr (way_raddr[i][WAY_WIDTH-3:0]), + .re (1'b1), + .waddr (way_waddr[i][WAY_WIDTH-3:0]), + .we (way_we[i]), + .din (way_din[i][31:0])); + */ + generate + for (i = 0; i < OPTION_ICACHE_WAYS; i=i+1) begin : way_memories + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH(WAY_WIDTH-2), + .DATA_WIDTH(OPTION_OPERAND_WIDTH), + .ENABLE_BYPASS(0) + ) + way_data_ram + (/*AUTOINST*/ + // Outputs + .dout (way_dout[i][OPTION_OPERAND_WIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .raddr (way_raddr[i][WAY_WIDTH-3:0]), // Templated + .re (1'b1), // Templated + .waddr (way_waddr[i][WAY_WIDTH-3:0]), // Templated + .we (way_we[i]), // Templated + .din (way_din[i][31:0])); // Templated + + end // block: way_memories + + if (OPTION_ICACHE_WAYS >= 2) begin : gen_u_lru + /* mor1kx_cache_lru AUTO_TEMPLATE( + .current (current_lru_history), + .update (next_lru_history), + .lru_pre (lru), + .lru_post (), + .access (access), + ); */ + + mor1kx_cache_lru + #(.NUMWAYS(OPTION_ICACHE_WAYS)) + u_lru(/*AUTOINST*/ + // Outputs + .update (next_lru_history), // Templated + .lru_pre (lru), // Templated + .lru_post (), // Templated + // Inputs + .current (current_lru_history), // Templated + .access (access)); // Templated + end // if (OPTION_ICACHE_WAYS >= 2) + endgenerate + + /* mor1kx_simple_dpram_sclk AUTO_TEMPLATE ( + // Outputs + .dout (tag_dout[TAGMEM_WIDTH-1:0]), + // Inputs + .raddr (tag_rindex), + .re (1'b1), + .waddr (tag_windex), + .we (tag_we), + .din (tag_din)); + */ + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH(OPTION_ICACHE_SET_WIDTH), + .DATA_WIDTH(TAGMEM_WIDTH), + .ENABLE_BYPASS(0) + ) + tag_ram + (/*AUTOINST*/ + // Outputs + .dout (tag_dout[TAGMEM_WIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .raddr (tag_rindex), // Templated + .re (1'b1), // Templated + .waddr (tag_windex), // Templated + .we (tag_we), // Templated + .din (tag_din)); // Templated + +endmodule diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_immu.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_immu.v new file mode 100644 index 0000000..937bc3c --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_immu.v @@ -0,0 +1,452 @@ +/****************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Instruction MMU implementation + + Copyright (C) 2013 Stefan Kristiansson + + ******************************************************************************/ + +`include "mor1kx-defines.v" + +module mor1kx_immu + #( + parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_IMMU_SET_WIDTH = 6, + parameter OPTION_IMMU_WAYS = 1 + ) + ( + input clk, + input rst, + + input enable_i, + + output busy_o, + + input [OPTION_OPERAND_WIDTH-1:0] virt_addr_i, + input [OPTION_OPERAND_WIDTH-1:0] virt_addr_match_i, + output reg [OPTION_OPERAND_WIDTH-1:0] phys_addr_o, + output reg cache_inhibit_o, + + input supervisor_mode_i, + + output reg tlb_miss_o, + output pagefault_o, + + output reg tlb_reload_req_o, + input tlb_reload_ack_i, + output reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr_o, + input [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data_i, + output tlb_reload_pagefault_o, + input tlb_reload_pagefault_clear_i, + output tlb_reload_busy_o, + + // SPR interface + input [15:0] spr_bus_addr_i, + input spr_bus_we_i, + input spr_bus_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i, + + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o, + output spr_bus_ack_o + ); + + wire [OPTION_OPERAND_WIDTH-1:0] itlb_match_dout[OPTION_IMMU_WAYS-1:0]; + wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_match_addr; + reg [OPTION_IMMU_WAYS-1:0] itlb_match_we; + wire [OPTION_OPERAND_WIDTH-1:0] itlb_match_din; + + wire [OPTION_OPERAND_WIDTH-1:0] itlb_match_huge_dout[OPTION_IMMU_WAYS-1:0]; + wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_match_huge_addr; + wire itlb_match_huge_we; + + wire [OPTION_OPERAND_WIDTH-1:0] itlb_trans_dout[OPTION_IMMU_WAYS-1:0]; + wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_trans_addr; + reg [OPTION_IMMU_WAYS-1:0] itlb_trans_we; + wire [OPTION_OPERAND_WIDTH-1:0] itlb_trans_din; + + wire [OPTION_OPERAND_WIDTH-1:0] itlb_trans_huge_dout[OPTION_IMMU_WAYS-1:0]; + wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_trans_huge_addr; + wire itlb_trans_huge_we; + + reg itlb_match_reload_we; + reg [OPTION_OPERAND_WIDTH-1:0] itlb_match_reload_din; + + reg itlb_trans_reload_we; + reg [OPTION_OPERAND_WIDTH-1:0] itlb_trans_reload_din; + + wire itlb_match_spr_cs; + reg itlb_match_spr_cs_r; + wire itlb_trans_spr_cs; + reg itlb_trans_spr_cs_r; + + wire immucr_spr_cs; + reg immucr_spr_cs_r; + reg [OPTION_OPERAND_WIDTH-1:0] immucr; + + wire [1:0] spr_way_idx; + reg [1:0] spr_way_idx_r; + + wire [OPTION_IMMU_WAYS-1:0] way_huge; + + wire [OPTION_IMMU_WAYS-1:0] way_hit; + wire [OPTION_IMMU_WAYS-1:0] way_huge_hit; + + reg tlb_reload_pagefault; + reg tlb_reload_huge; + + // sxe: supervisor execute enable + // uxe: user exexute enable + reg sxe; + reg uxe; + + reg spr_bus_ack; + reg spr_bus_ack_r; + wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat; + reg [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_r; + + genvar i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_bus_ack <= 0; + else if (spr_bus_stb_i & spr_bus_addr_i[15:11] == 5'd2) + spr_bus_ack <= 1; + else + spr_bus_ack <= 0; + + always @(posedge clk) + spr_bus_ack_r <= spr_bus_ack; + + always @(posedge clk) + if (spr_bus_ack & !spr_bus_ack_r) + spr_bus_dat_r <= spr_bus_dat; + + assign spr_bus_ack_o = spr_bus_ack & spr_bus_stb_i & + spr_bus_addr_i[15:11] == 5'd2; + +generate +for (i = 0; i < OPTION_IMMU_WAYS; i=i+1) begin : ways + assign way_huge[i] = &itlb_match_huge_dout[i][1:0]; // huge & valid + + assign way_hit[i] = (itlb_match_dout[i][31:13] == virt_addr_match_i[31:13]) & + itlb_match_dout[i][0]; // valid bit + + assign way_huge_hit[i] = (itlb_match_huge_dout[i][31:24] == + virt_addr_match_i[31:24]) & + itlb_match_huge_dout[i][0]; +end +endgenerate + + integer j; + always @(*) begin + tlb_miss_o = !tlb_reload_pagefault & !busy_o; + phys_addr_o = virt_addr_match_i[23:0]; + sxe = 0; + uxe = 0; + cache_inhibit_o = 0; + + for (j = 0; j < OPTION_IMMU_WAYS; j=j+1) begin + if (way_huge[j] & way_huge_hit[j] | !way_huge[j] & way_hit[j]) + tlb_miss_o = 0; + + if (way_huge[j] & way_huge_hit[j]) begin + phys_addr_o = {itlb_trans_huge_dout[j][31:24], virt_addr_match_i[23:0]}; + sxe = itlb_trans_huge_dout[j][6]; + uxe = itlb_trans_huge_dout[j][7]; + cache_inhibit_o = itlb_trans_huge_dout[j][1]; + end else if (!way_huge[j] & way_hit[j])begin + phys_addr_o = {itlb_trans_dout[j][31:13], virt_addr_match_i[12:0]}; + sxe = itlb_trans_dout[j][6]; + uxe = itlb_trans_dout[j][7]; + cache_inhibit_o = itlb_trans_dout[j][1]; + end + + itlb_match_we[j] = 0; + if (itlb_match_reload_we & !tlb_reload_huge) + itlb_match_we[j] = 1; + if (j == spr_way_idx) + itlb_match_we[j] = itlb_match_spr_cs & spr_bus_we_i & !spr_bus_ack; + + itlb_trans_we[j] = 0; + if (itlb_trans_reload_we & !tlb_reload_huge) + itlb_trans_we[j] = 1; + if (j == spr_way_idx) + itlb_trans_we[j] = itlb_trans_spr_cs & spr_bus_we_i & !spr_bus_ack; + end + end + + assign pagefault_o = (supervisor_mode_i ? !sxe : !uxe) & + !tlb_reload_busy_o & !busy_o; + + assign busy_o = ((itlb_match_spr_cs | itlb_trans_spr_cs) & !spr_bus_ack | + (itlb_match_spr_cs_r | itlb_trans_spr_cs_r) & + spr_bus_ack & !spr_bus_ack_r) & enable_i; + + assign spr_way_idx = {spr_bus_addr_i[10], spr_bus_addr_i[8]}; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + itlb_match_spr_cs_r <= 0; + itlb_trans_spr_cs_r <= 0; + immucr_spr_cs_r <= 0; + spr_way_idx_r <= 0; + end else begin + itlb_match_spr_cs_r <= itlb_match_spr_cs; + itlb_trans_spr_cs_r <= itlb_trans_spr_cs; + immucr_spr_cs_r <= immucr_spr_cs; + spr_way_idx_r <= spr_way_idx; + end + +generate /* verilator lint_off WIDTH */ +if (FEATURE_IMMU_HW_TLB_RELOAD == "ENABLED") begin +/* verilator lint_on WIDTH */ + assign immucr_spr_cs = spr_bus_stb_i & + spr_bus_addr_i == `OR1K_SPR_IMMUCR_ADDR; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + immucr <= 0; + else if (immucr_spr_cs & spr_bus_we_i) + immucr <= spr_bus_dat_i; + +end else begin + assign immucr_spr_cs = 0; + always @(posedge clk) + immucr <= 0; +end +endgenerate + + assign itlb_match_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd2) & + |spr_bus_addr_i[10:9] & !spr_bus_addr_i[7]; + assign itlb_trans_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd2) & + |spr_bus_addr_i[10:9] & spr_bus_addr_i[7]; + + assign itlb_match_addr = itlb_match_spr_cs & !spr_bus_ack ? + spr_bus_addr_i[OPTION_IMMU_SET_WIDTH-1:0] : + virt_addr_i[13+(OPTION_IMMU_SET_WIDTH-1):13]; + assign itlb_trans_addr = itlb_trans_spr_cs & !spr_bus_ack ? + spr_bus_addr_i[OPTION_IMMU_SET_WIDTH-1:0] : + virt_addr_i[13+(OPTION_IMMU_SET_WIDTH-1):13]; + + assign itlb_match_din = itlb_match_spr_cs & spr_bus_we_i & !spr_bus_ack ? + spr_bus_dat_i : itlb_match_reload_din; + assign itlb_trans_din = itlb_trans_spr_cs & spr_bus_we_i & !spr_bus_ack ? + spr_bus_dat_i : itlb_trans_reload_din; + + assign itlb_match_huge_addr = virt_addr_i[24+(OPTION_IMMU_SET_WIDTH-1):24]; + assign itlb_trans_huge_addr = virt_addr_i[24+(OPTION_IMMU_SET_WIDTH-1):24]; + + assign itlb_match_huge_we = itlb_match_reload_we & tlb_reload_huge; + assign itlb_trans_huge_we = itlb_trans_reload_we & tlb_reload_huge; + + assign spr_bus_dat = itlb_match_spr_cs_r ? itlb_match_dout[spr_way_idx_r] : + itlb_trans_spr_cs_r ? itlb_trans_dout[spr_way_idx_r] : + immucr_spr_cs_r ? immucr : 0; + + // Use registered value on all but the first cycle spr_bus_ack is asserted + assign spr_bus_dat_o = spr_bus_ack & !spr_bus_ack_r ? spr_bus_dat : + spr_bus_dat_r; + + localparam TLB_IDLE = 2'd0; + localparam TLB_GET_PTE_POINTER = 2'd1; + localparam TLB_GET_PTE = 2'd2; + localparam TLB_READ = 2'd3; + +generate /* verilator lint_off WIDTH */ +if (FEATURE_IMMU_HW_TLB_RELOAD == "ENABLED") begin + /* verilator lint_on WIDTH */ + + // Hardware TLB reload + // Compliant with the suggestions outlined in this thread: + // http://lists.openrisc.net/pipermail/openrisc/2013-July/001806.html + // + // PTE layout: + // | 31 ... 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + // | PPN | Reserved |PRESENT| L | X | W | U | D | A |WOM|WBC|CI |CC | + // + // Where X/W/U maps into SXE/UXE like this: + // X | W | U SXE | UXE + // --------- --------- + // 0 | x | 0 = 0 | 0 + // 0 | x | 1 = 0 | 0 + // ... + // 1 | x | 0 = 1 | 0 + // 1 | x | 1 = 1 | 1 + + + + reg [1:0] tlb_reload_state = TLB_IDLE; + wire do_reload; + + assign do_reload = enable_i & tlb_miss_o & (immucr[31:10] != 0); + assign tlb_reload_busy_o = (tlb_reload_state != TLB_IDLE) | do_reload; + assign tlb_reload_pagefault_o = tlb_reload_pagefault & + !tlb_reload_pagefault_clear_i; + + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + tlb_reload_pagefault <= 0; + else if(tlb_reload_pagefault_clear_i) + tlb_reload_pagefault <= 0; + itlb_trans_reload_we <= 0; + itlb_trans_reload_din <= 0; + itlb_match_reload_we <= 0; + itlb_match_reload_din <= 0; + + case (tlb_reload_state) + TLB_IDLE: begin + tlb_reload_huge <= 0; + tlb_reload_req_o <= 0; + if (do_reload) begin + tlb_reload_req_o <= 1; + tlb_reload_addr_o <= {immucr[31:10], + virt_addr_match_i[31:24], 2'b00}; + tlb_reload_state <= TLB_GET_PTE_POINTER; + end + end + + // + // Here we get the pointer to the PTE table, next is to fetch + // the actual pte from the offset in the table. + // The offset is calculated by: + // ((virt_addr_match >> PAGE_BITS) & (PTE_CNT-1)) << 2 + // Where PAGE_BITS is 13 (8 kb page) and PTE_CNT is 2048 + // (number of PTEs in the PTE table) + // + TLB_GET_PTE_POINTER: begin + tlb_reload_huge <= 0; + if (tlb_reload_ack_i) begin + if (tlb_reload_data_i[31:13] == 0) begin + tlb_reload_pagefault <= 1; + tlb_reload_req_o <= 0; + tlb_reload_state <= TLB_IDLE; + end else if (tlb_reload_data_i[9]) begin + tlb_reload_huge <= 1; + tlb_reload_req_o <= 0; + tlb_reload_state <= TLB_GET_PTE; + end else begin + tlb_reload_addr_o <= {tlb_reload_data_i[31:13], + virt_addr_match_i[23:13], 2'b00}; + tlb_reload_state <= TLB_GET_PTE; + end + end + end + + // + // Here we get the actual PTE, left to do is to translate the + // PTE data into our translate and match registers. + // + TLB_GET_PTE: begin + if (tlb_reload_ack_i) begin + tlb_reload_req_o <= 0; + // Check PRESENT bit + if (!tlb_reload_data_i[10]) begin + tlb_reload_pagefault <= 1; + tlb_reload_state <= TLB_IDLE; + end else begin + // Translate register generation. + // PPN + itlb_trans_reload_din[31:13] <= tlb_reload_data_i[31:13]; + // UXE = X & U + itlb_trans_reload_din[7] <= tlb_reload_data_i[8] & + tlb_reload_data_i[6]; + // SXE = X + itlb_trans_reload_din[6] <= tlb_reload_data_i[8]; + // Dirty, Accessed, Weakly-Ordered-Memory, Writeback cache, + // Cache inhibit, Cache coherent + itlb_trans_reload_din[5:0] <= tlb_reload_data_i[5:0]; + itlb_trans_reload_we <= 1; + + // Match register generation. + // VPN + itlb_match_reload_din[31:13] <= virt_addr_match_i[31:13]; + // PL1 + itlb_match_reload_din[1] <= tlb_reload_huge; + // Valid + itlb_match_reload_din[0] <= 1; + itlb_match_reload_we <= 1; + + tlb_reload_state <= TLB_READ; + end + end + end + + // Let the just written values propagate out on the read ports + TLB_READ: begin + tlb_reload_state <= TLB_IDLE; + end + + default: + tlb_reload_state <= TLB_IDLE; + + endcase + end +end else begin // if (FEATURE_IMMU_HW_TLB_RELOAD == "ENABLED") + assign tlb_reload_pagefault_o = 0; + assign tlb_reload_busy_o = 0; + always @(posedge clk) begin + tlb_reload_req_o <= 0; + tlb_reload_addr_o <= 0; + tlb_reload_huge <= 1'b0; + tlb_reload_pagefault <= 0; + itlb_trans_reload_we <= 0; + itlb_trans_reload_din <= 0; + itlb_match_reload_we <= 0; + itlb_match_reload_din <= 0; + end +end +endgenerate + +generate +for (i = 0; i < OPTION_IMMU_WAYS; i=i+1) begin : itlb + // ITLB match registers + mor1kx_true_dpram_sclk + #( + .ADDR_WIDTH(OPTION_IMMU_SET_WIDTH), + .DATA_WIDTH(OPTION_OPERAND_WIDTH) + ) + itlb_match_regs + ( + // Outputs + .dout_a (itlb_match_dout[i]), + .dout_b (itlb_match_huge_dout[i]), + // Inputs + .clk (clk), + .addr_a (itlb_match_addr), + .we_a (itlb_match_we[i]), + .din_a (itlb_match_din), + .addr_b (itlb_match_huge_addr), + .we_b (itlb_match_huge_we), + .din_b (itlb_match_reload_din) + ); + + + // ITLB translate registers + mor1kx_true_dpram_sclk + #( + .ADDR_WIDTH(OPTION_IMMU_SET_WIDTH), + .DATA_WIDTH(OPTION_OPERAND_WIDTH) + ) + itlb_translate_regs + ( + // Outputs + .dout_a (itlb_trans_dout[i]), + .dout_b (itlb_trans_huge_dout[i]), + // Inputs + .clk (clk), + .addr_a (itlb_trans_addr), + .we_a (itlb_trans_we[i]), + .din_a (itlb_trans_din), + .addr_b (itlb_trans_huge_addr), + .we_b (itlb_trans_huge_we), + .din_b (itlb_trans_reload_din) + ); +end +endgenerate + +endmodule diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_cappuccino.v new file mode 100644 index 0000000..ff18fce --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_cappuccino.v @@ -0,0 +1,863 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Data bus interface + + All combinatorial outputs to pipeline + Dbus interface request signal out synchronous + + 32-bit specific + + Copyright (C) 2012 Julius Baxter + Copyright (C) 2013 Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_lsu_cappuccino + #( + parameter FEATURE_DATACACHE = "NONE", + parameter OPTION_OPERAND_WIDTH = 32, + parameter OPTION_DCACHE_BLOCK_WIDTH = 5, + parameter OPTION_DCACHE_SET_WIDTH = 9, + parameter OPTION_DCACHE_WAYS = 2, + parameter OPTION_DCACHE_LIMIT_WIDTH = 32, + parameter OPTION_DCACHE_SNOOP = "NONE", + parameter FEATURE_DMMU = "NONE", + parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE", + parameter OPTION_DMMU_SET_WIDTH = 6, + parameter OPTION_DMMU_WAYS = 1, + parameter FEATURE_STORE_BUFFER = "ENABLED", + parameter OPTION_STORE_BUFFER_DEPTH_WIDTH = 8, + parameter FEATURE_ATOMIC = "ENABLED" + ) + ( + input clk, + input rst, + + input padv_execute_i, + input padv_ctrl_i, // needed for dmmu spr + input decode_valid_i, + // calculated address from ALU + input [OPTION_OPERAND_WIDTH-1:0] exec_lsu_adr_i, + input [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_i, + + // register file B in (store operand) + input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i, + + // from decode stage regs, indicate if load or store + input exec_op_lsu_load_i, + input exec_op_lsu_store_i, + input exec_op_lsu_atomic_i, + input ctrl_op_lsu_load_i, + input ctrl_op_lsu_store_i, + input ctrl_op_lsu_atomic_i, + input ctrl_op_msync_i, + input [1:0] ctrl_lsu_length_i, + input ctrl_lsu_zext_i, + + // From control stage, exception PC for the store buffer input + input [OPTION_OPERAND_WIDTH-1:0] ctrl_epcr_i, + // The exception PC as it has went through the store buffer + output [OPTION_OPERAND_WIDTH-1:0] store_buffer_epcr_o, + + output [OPTION_OPERAND_WIDTH-1:0] lsu_result_o, + output lsu_valid_o, + // exception output + output lsu_except_dbus_o, + output lsu_except_align_o, + output lsu_except_dtlb_miss_o, + output lsu_except_dpagefault_o, + + // Indicator that the dbus exception came via the store buffer + output reg store_buffer_err_o, + + // Atomic operation flag set/clear logic + output atomic_flag_set_o, + output atomic_flag_clear_o, + + // stall signal for msync logic + output msync_stall_o, + + // SPR interface + input [15:0] spr_bus_addr_i, + input spr_bus_we_i, + input spr_bus_stb_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_o, + output spr_bus_ack_dc_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_o, + output spr_bus_ack_dmmu_o, + + input dc_enable_i, + input dmmu_enable_i, + input supervisor_mode_i, + + // interface to data bus + output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o, + output reg dbus_req_o, + output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o, + output reg [3:0] dbus_bsel_o, + output dbus_we_o, + output dbus_burst_o, + input dbus_err_i, + input dbus_ack_i, + input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i, + input pipeline_flush_i, + + input [31:0] snoop_adr_i, + input snoop_en_i + ); + + reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_aligned; // comb. + reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_extended; // comb. + + reg access_done; + + wire align_err_word; + wire align_err_short; + + wire align_err; + + wire except_align; + + reg except_dbus; + + reg dbus_ack; + reg dbus_err; + reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat; + reg [OPTION_OPERAND_WIDTH-1:0] dbus_adr; + wire [OPTION_OPERAND_WIDTH-1:0] next_dbus_adr; + reg dbus_we; + reg [3:0] dbus_bsel; + wire dbus_access; + wire dbus_stall; + + wire [OPTION_OPERAND_WIDTH-1:0] lsu_ldat; + wire [OPTION_OPERAND_WIDTH-1:0] lsu_sdat; + wire lsu_ack; + + wire dc_err; + wire dc_ack; + wire [31:0] dc_ldat; + wire [31:0] dc_sdat; + wire [31:0] dc_adr; + wire [31:0] dc_adr_match; + wire dc_req; + wire dc_we; + wire [3:0] dc_bsel; + + wire dc_access; + wire dc_refill_allowed; + wire dc_refill; + wire dc_refill_req; + wire dc_refill_done; + + reg dc_enable_r; + wire dc_enabled; + + wire ctrl_op_lsu; + + // DMMU + wire tlb_miss; + wire pagefault; + wire [OPTION_OPERAND_WIDTH-1:0] dmmu_phys_addr; + wire except_dtlb_miss; + reg except_dtlb_miss_r; + wire except_dpagefault; + reg except_dpagefault_r; + wire dmmu_cache_inhibit; + + wire tlb_reload_req; + wire tlb_reload_busy; + wire [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr; + wire tlb_reload_pagefault; + reg tlb_reload_ack; + reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data; + wire tlb_reload_pagefault_clear; + reg tlb_reload_done; + + // Store buffer + wire store_buffer_write; + wire store_buffer_read; + wire store_buffer_full; + wire store_buffer_empty; + wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_radr; + wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_wadr; + wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_dat; + wire [OPTION_OPERAND_WIDTH/8-1:0] store_buffer_bsel; + wire store_buffer_atomic; + reg store_buffer_write_pending; + + reg dbus_atomic; + + reg last_write; + reg write_done; + + // Atomic operations + reg [OPTION_OPERAND_WIDTH-1:0] atomic_addr; + reg atomic_reserve; + wire swa_success; + + wire snoop_valid; + wire dc_snoop_hit; + + // We have to mask out our snooped bus accesses + assign snoop_valid = (OPTION_DCACHE_SNOOP != "NONE") ? + snoop_en_i & !((snoop_adr_i == dbus_adr_o) & dbus_ack_i) : + 0; + + assign ctrl_op_lsu = ctrl_op_lsu_load_i | ctrl_op_lsu_store_i; + + assign lsu_sdat = (ctrl_lsu_length_i == 2'b00) ? // byte access + {ctrl_rfb_i[7:0],ctrl_rfb_i[7:0], + ctrl_rfb_i[7:0],ctrl_rfb_i[7:0]} : + (ctrl_lsu_length_i == 2'b01) ? // halfword access + {ctrl_rfb_i[15:0],ctrl_rfb_i[15:0]} : + ctrl_rfb_i; // word access + + assign align_err_word = |ctrl_lsu_adr_i[1:0]; + assign align_err_short = ctrl_lsu_adr_i[0]; + + + assign lsu_valid_o = (lsu_ack | access_done) & !tlb_reload_busy & !dc_snoop_hit; + + assign lsu_except_dbus_o = except_dbus | store_buffer_err_o; + + assign align_err = (ctrl_lsu_length_i == 2'b10) & align_err_word | + (ctrl_lsu_length_i == 2'b01) & align_err_short; + + assign except_align = ctrl_op_lsu & align_err; + + assign lsu_except_align_o = except_align & !pipeline_flush_i; + + assign except_dtlb_miss = ctrl_op_lsu & tlb_miss & dmmu_enable_i & + !tlb_reload_busy; + + assign lsu_except_dtlb_miss_o = except_dtlb_miss & !pipeline_flush_i; + + assign except_dpagefault = ctrl_op_lsu & pagefault & dmmu_enable_i & + !tlb_reload_busy | tlb_reload_pagefault; + + assign lsu_except_dpagefault_o = except_dpagefault & !pipeline_flush_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + access_done <= 0; + else if (padv_execute_i) + access_done <= 0; + else if (lsu_ack) + access_done <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + except_dbus <= 0; + else if (padv_execute_i | pipeline_flush_i) + except_dbus <= 0; + else if (dbus_err_i) + except_dbus <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + except_dtlb_miss_r <= 0; + else if (padv_execute_i) + except_dtlb_miss_r <= 0; + else if (except_dtlb_miss) + except_dtlb_miss_r <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + except_dpagefault_r <= 0; + else if (padv_execute_i) + except_dpagefault_r <= 0; + else if (except_dpagefault) + except_dpagefault_r <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + store_buffer_err_o <= 0; + else if (pipeline_flush_i) + store_buffer_err_o <= 0; + else if (dbus_err_i & dbus_we_o) + store_buffer_err_o <= 1; + + // Big endian bus mapping + always @(*) + case (ctrl_lsu_length_i) + 2'b00: // byte access + case(ctrl_lsu_adr_i[1:0]) + 2'b00: + dbus_bsel = 4'b1000; + 2'b01: + dbus_bsel = 4'b0100; + 2'b10: + dbus_bsel = 4'b0010; + 2'b11: + dbus_bsel = 4'b0001; + endcase + 2'b01: // halfword access + case(ctrl_lsu_adr_i[1]) + 1'b0: + dbus_bsel = 4'b1100; + 1'b1: + dbus_bsel = 4'b0011; + endcase + 2'b10, + 2'b11: + dbus_bsel = 4'b1111; + endcase + + // Select part of read word + always @* + case(ctrl_lsu_adr_i[1:0]) + 2'b00: + dbus_dat_aligned = lsu_ldat; + 2'b01: + dbus_dat_aligned = {lsu_ldat[23:0],8'd0}; + 2'b10: + dbus_dat_aligned = {lsu_ldat[15:0],16'd0}; + 2'b11: + dbus_dat_aligned = {lsu_ldat[7:0],24'd0}; + endcase // case (ctrl_lsu_adr_i[1:0]) + + // Do appropriate extension + always @(*) + case({ctrl_lsu_zext_i, ctrl_lsu_length_i}) + 3'b100: // lbz + dbus_dat_extended = {24'd0,dbus_dat_aligned[31:24]}; + 3'b101: // lhz + dbus_dat_extended = {16'd0,dbus_dat_aligned[31:16]}; + 3'b000: // lbs + dbus_dat_extended = {{24{dbus_dat_aligned[31]}}, + dbus_dat_aligned[31:24]}; + 3'b001: // lhs + dbus_dat_extended = {{16{dbus_dat_aligned[31]}}, + dbus_dat_aligned[31:16]}; + default: + dbus_dat_extended = dbus_dat_aligned; + endcase + + assign lsu_result_o = dbus_dat_extended; + + // Bus access logic + localparam [2:0] + IDLE = 3'd0, + READ = 3'd1, + WRITE = 3'd2, + TLB_RELOAD = 3'd3, + DC_REFILL = 3'd4; + + reg [2:0] state; + + assign dbus_access = (!dc_access | tlb_reload_busy | ctrl_op_lsu_store_i) & + (state != DC_REFILL) | (state == WRITE); + reg dc_refill_r; + + always @(posedge clk) + dc_refill_r <= dc_refill; + + wire store_buffer_ack; + assign store_buffer_ack = (FEATURE_STORE_BUFFER!="NONE") ? + store_buffer_write : + write_done; + + assign lsu_ack = (ctrl_op_lsu_store_i | state == WRITE) ? + (store_buffer_ack & !ctrl_op_lsu_atomic_i | + write_done & ctrl_op_lsu_atomic_i) : + (dbus_access ? dbus_ack : dc_ack); + + assign lsu_ldat = dbus_access ? dbus_dat : dc_ldat; + assign dbus_adr_o = dbus_adr; + + assign dbus_dat_o = dbus_dat; + + assign dbus_burst_o = (state == DC_REFILL) & !dc_refill_done; + + // + // Slightly subtle, but if there is an atomic store coming out from the + // store buffer, and the link has been broken while it was waiting there, + // the bus access is still performed as a (discarded) read. + // + assign dbus_we_o = dbus_we & (!dbus_atomic | atomic_reserve); + + assign next_dbus_adr = (OPTION_DCACHE_BLOCK_WIDTH == 5) ? + {dbus_adr[31:5], dbus_adr[4:0] + 5'd4} : // 32 byte + {dbus_adr[31:4], dbus_adr[3:0] + 4'd4}; // 16 byte + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + dbus_err <= 0; + else + dbus_err <= dbus_err_i; + + always @(posedge clk) begin + dbus_ack <= 0; + write_done <= 0; + tlb_reload_ack <= 0; + tlb_reload_done <= 0; + case (state) + IDLE: begin + dbus_req_o <= 0; + dbus_we <= 0; + dbus_adr <= 0; + dbus_bsel_o <= 4'hf; + dbus_atomic <= 0; + last_write <= 0; + if (store_buffer_write | !store_buffer_empty) begin + state <= WRITE; + end else if (ctrl_op_lsu & dbus_access & !dc_refill & !dbus_ack & + !dbus_err & !except_dbus & !access_done & + !pipeline_flush_i) begin + if (tlb_reload_req) begin + dbus_adr <= tlb_reload_addr; + dbus_req_o <= 1; + state <= TLB_RELOAD; + end else if (dmmu_enable_i) begin + dbus_adr <= dmmu_phys_addr; + if (!tlb_miss & !pagefault & !except_align) begin + if (ctrl_op_lsu_load_i) begin + dbus_req_o <= 1; + dbus_bsel_o <= dbus_bsel; + state <= READ; + end + end + end else if (!except_align) begin + dbus_adr <= ctrl_lsu_adr_i; + if (ctrl_op_lsu_load_i) begin + dbus_req_o <= 1; + dbus_bsel_o <= dbus_bsel; + state <= READ; + end + end + end else if (dc_refill_req) begin + dbus_req_o <= 1; + dbus_adr <= dc_adr_match; + state <= DC_REFILL; + end + end + + DC_REFILL: begin + dbus_req_o <= 1; + if (dbus_ack_i) begin + dbus_adr <= next_dbus_adr; + if (dc_refill_done) begin + dbus_req_o <= 0; + state <= IDLE; + end + end + + // TODO: only abort on snoop-hits to refill address + if (dbus_err_i | dc_snoop_hit) begin + dbus_req_o <= 0; + state <= IDLE; + end + end + + READ: begin + dbus_ack <= dbus_ack_i; + dbus_dat <= dbus_dat_i; + if (dbus_ack_i | dbus_err_i) begin + dbus_req_o <= 0; + state <= IDLE; + end + end + + WRITE: begin + dbus_req_o <= 1; + dbus_we <= 1; + + if (!dbus_req_o | dbus_ack_i & !last_write) begin + dbus_bsel_o <= store_buffer_bsel; + dbus_adr <= store_buffer_radr; + dbus_dat <= store_buffer_dat; + dbus_atomic <= store_buffer_atomic; + last_write <= store_buffer_empty; + end + + if (store_buffer_write) + last_write <= 0; + + if (last_write & dbus_ack_i | dbus_err_i) begin + dbus_req_o <= 0; + dbus_we <= 0; + if (!store_buffer_write) begin + state <= IDLE; + write_done <= 1; + end + end + end + + TLB_RELOAD: begin + dbus_adr <= tlb_reload_addr; + tlb_reload_data <= dbus_dat_i; + tlb_reload_ack <= dbus_ack_i & tlb_reload_req; + + if (!tlb_reload_req | dbus_err_i) begin + state <= IDLE; + tlb_reload_done <= 1; + end + + dbus_req_o <= tlb_reload_req; + if (dbus_ack_i | tlb_reload_ack) + dbus_req_o <= 0; + end + + default: + state <= IDLE; + endcase + + if (rst) + state <= IDLE; + end + + assign dbus_stall = tlb_reload_busy | except_align | except_dbus | + except_dtlb_miss | except_dpagefault | + pipeline_flush_i; + + // Stall until the store buffer is empty + assign msync_stall_o = ctrl_op_msync_i & (state == WRITE); + +generate +if (FEATURE_ATOMIC!="NONE") begin : atomic_gen + // Atomic operations logic + reg atomic_flag_set; + reg atomic_flag_clear; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + atomic_reserve <= 0; + else if (pipeline_flush_i) + atomic_reserve <= 0; + else if (ctrl_op_lsu_store_i & ctrl_op_lsu_atomic_i & write_done || + !ctrl_op_lsu_atomic_i & store_buffer_write & + (store_buffer_wadr == atomic_addr) || + (snoop_valid & (snoop_adr_i == atomic_addr))) + atomic_reserve <= 0; + else if (ctrl_op_lsu_load_i & ctrl_op_lsu_atomic_i & padv_ctrl_i) + atomic_reserve <= !(snoop_valid & (snoop_adr_i == dc_adr_match)); + + always @(posedge clk) + if (ctrl_op_lsu_load_i & ctrl_op_lsu_atomic_i & padv_ctrl_i) + atomic_addr <= dc_adr_match; + + assign swa_success = ctrl_op_lsu_store_i & ctrl_op_lsu_atomic_i & + atomic_reserve & (dbus_adr == atomic_addr); + + always @(posedge clk) + if (padv_ctrl_i) + atomic_flag_set <= 0; + else if (write_done) + atomic_flag_set <= swa_success & lsu_valid_o; + + always @(posedge clk) + if (padv_ctrl_i) + atomic_flag_clear <= 0; + else if (write_done) + atomic_flag_clear <= !swa_success & lsu_valid_o & + ctrl_op_lsu_atomic_i & ctrl_op_lsu_store_i; + + assign atomic_flag_set_o = atomic_flag_set; + assign atomic_flag_clear_o = atomic_flag_clear; + +end else begin + assign atomic_flag_set_o = 0; + assign atomic_flag_clear_o = 0; + assign swa_success = 0; + always @(posedge clk) begin + atomic_addr <= 0; + atomic_reserve <= 0; + end +end +endgenerate + + // Store buffer logic + always @(posedge clk) + if (rst) + store_buffer_write_pending <= 0; + else if (store_buffer_write | pipeline_flush_i) + store_buffer_write_pending <= 0; + else if (ctrl_op_lsu_store_i & padv_ctrl_i & !dbus_stall & + (store_buffer_full | dc_refill | dc_refill_r | dc_snoop_hit)) + store_buffer_write_pending <= 1; + + assign store_buffer_write = (ctrl_op_lsu_store_i & + (padv_ctrl_i | tlb_reload_done) | + store_buffer_write_pending) & + !store_buffer_full & !dc_refill & !dc_refill_r & + !dbus_stall & !dc_snoop_hit; + +generate +if (FEATURE_STORE_BUFFER!="NONE") begin : store_buffer_gen + assign store_buffer_read = (state == IDLE) & store_buffer_write | + (state == IDLE) & !store_buffer_empty | + (state == WRITE) & (dbus_ack_i | !dbus_req_o) & + (!store_buffer_empty | store_buffer_write) & + !last_write | + (state == WRITE) & last_write & + store_buffer_write; + + mor1kx_store_buffer + #( + .DEPTH_WIDTH(OPTION_STORE_BUFFER_DEPTH_WIDTH), + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH) + ) + mor1kx_store_buffer + ( + .clk (clk), + .rst (rst), + + .pc_i (ctrl_epcr_i), + .adr_i (store_buffer_wadr), + .dat_i (lsu_sdat), + .bsel_i (dbus_bsel), + .atomic_i (ctrl_op_lsu_atomic_i), + .write_i (store_buffer_write), + + .pc_o (store_buffer_epcr_o), + .adr_o (store_buffer_radr), + .dat_o (store_buffer_dat), + .bsel_o (store_buffer_bsel), + .atomic_o (store_buffer_atomic), + .read_i (store_buffer_read), + + .full_o (store_buffer_full), + .empty_o (store_buffer_empty) + ); +end else begin + assign store_buffer_epcr_o = ctrl_epcr_i; + assign store_buffer_radr = store_buffer_wadr; + assign store_buffer_dat = lsu_sdat; + assign store_buffer_bsel = dbus_bsel; + assign store_buffer_empty = 1'b1; + + reg store_buffer_full_r; + always @(posedge clk) + if (store_buffer_write) + store_buffer_full_r <= 1; + else if (write_done) + store_buffer_full_r <= 0; + + assign store_buffer_full = store_buffer_full_r & !write_done; +end +endgenerate + assign store_buffer_wadr = dc_adr_match; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + dc_enable_r <= 0; + else if (dc_enable_i & !dbus_req_o) + dc_enable_r <= 1; + else if (!dc_enable_i & !dc_refill) + dc_enable_r <= 0; + + assign dc_enabled = dc_enable_i & dc_enable_r; + assign dc_adr = padv_execute_i & + (exec_op_lsu_load_i | exec_op_lsu_store_i) ? + exec_lsu_adr_i : ctrl_lsu_adr_i; + assign dc_adr_match = dmmu_enable_i ? + {dmmu_phys_addr[OPTION_OPERAND_WIDTH-1:2],2'b0} : + {ctrl_lsu_adr_i[OPTION_OPERAND_WIDTH-1:2],2'b0}; + + assign dc_req = ctrl_op_lsu & dc_access & !access_done & !dbus_stall & + !(dbus_atomic & dbus_we & !atomic_reserve); + assign dc_refill_allowed = !(ctrl_op_lsu_store_i | state == WRITE) & + !dc_snoop_hit & !snoop_valid; + +generate +if (FEATURE_DATACACHE!="NONE") begin : dcache_gen + if (OPTION_DCACHE_LIMIT_WIDTH == OPTION_OPERAND_WIDTH) begin + assign dc_access = ctrl_op_lsu_store_i | dc_enabled & + !(dmmu_cache_inhibit & dmmu_enable_i); + end else if (OPTION_DCACHE_LIMIT_WIDTH < OPTION_OPERAND_WIDTH) begin + assign dc_access = ctrl_op_lsu_store_i | dc_enabled & + dc_adr_match[OPTION_OPERAND_WIDTH-1: + OPTION_DCACHE_LIMIT_WIDTH] == 0 & + !(dmmu_cache_inhibit & dmmu_enable_i); + end else begin + initial begin + $display("ERROR: OPTION_DCACHE_LIMIT_WIDTH > OPTION_OPERAND_WIDTH"); + $finish(); + end + end + + assign dc_bsel = dbus_bsel; + assign dc_we = exec_op_lsu_store_i & !exec_op_lsu_atomic_i & padv_execute_i | + dbus_atomic & dbus_we_o & !write_done | + ctrl_op_lsu_store_i & tlb_reload_busy & !tlb_reload_req; + + /* mor1kx_dcache AUTO_TEMPLATE ( + .refill_o (dc_refill), + .refill_req_o (dc_refill_req), + .refill_done_o (dc_refill_done), + .cpu_err_o (dc_err), + .cpu_ack_o (dc_ack), + .cpu_dat_o (dc_ldat), + .spr_bus_dat_o (spr_bus_dat_dc_o), + .spr_bus_ack_o (spr_bus_ack_dc_o), + .snoop_hit_o (dc_snoop_hit), + // Inputs + .clk (clk), + .rst (rst), + .dc_dbus_err_i (dbus_err), + .dc_enable_i (dc_enabled), + .dc_access_i (dc_access), + .cpu_dat_i (lsu_sdat), + .cpu_adr_i (dc_adr), + .cpu_adr_match_i (dc_adr_match), + .cpu_req_i (dc_req), + .cpu_we_i (dc_we), + .cpu_bsel_i (dc_bsel), + .refill_allowed (dc_refill_allowed), + .wradr_i (dbus_adr), + .wrdat_i (dbus_dat_i), + .we_i (dbus_ack_i), + .snoop_valid_i (snoop_valid), + );*/ + + mor1kx_dcache + #( + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH), + .OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH), + .OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS), + .OPTION_DCACHE_LIMIT_WIDTH(OPTION_DCACHE_LIMIT_WIDTH), + .OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP) + ) + mor1kx_dcache + (/*AUTOINST*/ + // Outputs + .refill_o (dc_refill), // Templated + .refill_req_o (dc_refill_req), // Templated + .refill_done_o (dc_refill_done), // Templated + .cpu_err_o (dc_err), // Templated + .cpu_ack_o (dc_ack), // Templated + .cpu_dat_o (dc_ldat), // Templated + .snoop_hit_o (dc_snoop_hit), // Templated + .spr_bus_dat_o (spr_bus_dat_dc_o), // Templated + .spr_bus_ack_o (spr_bus_ack_dc_o), // Templated + // Inputs + .clk (clk), // Templated + .rst (rst), // Templated + .dc_dbus_err_i (dbus_err), // Templated + .dc_enable_i (dc_enabled), // Templated + .dc_access_i (dc_access), // Templated + .cpu_dat_i (lsu_sdat), // Templated + .cpu_adr_i (dc_adr), // Templated + .cpu_adr_match_i (dc_adr_match), // Templated + .cpu_req_i (dc_req), // Templated + .cpu_we_i (dc_we), // Templated + .cpu_bsel_i (dc_bsel), // Templated + .refill_allowed (dc_refill_allowed), // Templated + .wradr_i (dbus_adr), // Templated + .wrdat_i (dbus_dat_i), // Templated + .we_i (dbus_ack_i), // Templated + .snoop_adr_i (snoop_adr_i[31:0]), + .snoop_valid_i (snoop_valid), // Templated + .spr_bus_addr_i (spr_bus_addr_i[15:0]), + .spr_bus_we_i (spr_bus_we_i), + .spr_bus_stb_i (spr_bus_stb_i), + .spr_bus_dat_i (spr_bus_dat_i[OPTION_OPERAND_WIDTH-1:0])); +end else begin + assign dc_access = 0; + assign dc_refill = 0; + assign dc_refill_done = 0; + assign dc_refill_req = 0; + assign dc_err = 0; + assign dc_ack = 0; + assign dc_bsel = 0; + assign dc_we = 0; + assign dc_snoop_hit = 0; +end + +endgenerate + +generate +if (FEATURE_DMMU!="NONE") begin : dmmu_gen + wire [OPTION_OPERAND_WIDTH-1:0] virt_addr; + wire dmmu_spr_bus_stb; + wire dmmu_enable; + + assign virt_addr = dc_adr; + + // small hack to delay dmmu spr reads by one cycle + // ideally the spr accesses should work so that the address is presented + // in execute stage and the delayed data should be available in control + // stage, but this is not how things currently work. + assign dmmu_spr_bus_stb = spr_bus_stb_i & (!padv_ctrl_i | spr_bus_we_i); + + assign tlb_reload_pagefault_clear = !ctrl_op_lsu; // use pipeline_flush_i? + + assign dmmu_enable = dmmu_enable_i & !pipeline_flush_i; + + /* mor1kx_dmmu AUTO_TEMPLATE ( + .enable_i (dmmu_enable), + .phys_addr_o (dmmu_phys_addr), + .cache_inhibit_o (dmmu_cache_inhibit), + .op_store_i (ctrl_op_lsu_store_i), + .op_load_i (ctrl_op_lsu_load_i), + .tlb_miss_o (tlb_miss), + .pagefault_o (pagefault), + .tlb_reload_req_o (tlb_reload_req), + .tlb_reload_busy_o (tlb_reload_busy), + .tlb_reload_addr_o (tlb_reload_addr), + .tlb_reload_pagefault_o (tlb_reload_pagefault), + .tlb_reload_ack_i (tlb_reload_ack), + .tlb_reload_data_i (tlb_reload_data), + .tlb_reload_pagefault_clear_i (tlb_reload_pagefault_clear), + .spr_bus_dat_o (spr_bus_dat_dmmu_o), + .spr_bus_ack_o (spr_bus_ack_dmmu_o), + .spr_bus_stb_i (dmmu_spr_bus_stb), + .virt_addr_i (virt_addr), + .virt_addr_match_i (ctrl_lsu_adr_i), + ); */ + mor1kx_dmmu + #( + .FEATURE_DMMU_HW_TLB_RELOAD(FEATURE_DMMU_HW_TLB_RELOAD), + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH), + .OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH), + .OPTION_DMMU_WAYS(OPTION_DMMU_WAYS) + ) + mor1kx_dmmu + (/*AUTOINST*/ + // Outputs + .phys_addr_o (dmmu_phys_addr), // Templated + .cache_inhibit_o (dmmu_cache_inhibit), // Templated + .tlb_miss_o (tlb_miss), // Templated + .pagefault_o (pagefault), // Templated + .tlb_reload_req_o (tlb_reload_req), // Templated + .tlb_reload_busy_o (tlb_reload_busy), // Templated + .tlb_reload_addr_o (tlb_reload_addr), // Templated + .tlb_reload_pagefault_o (tlb_reload_pagefault), // Templated + .spr_bus_dat_o (spr_bus_dat_dmmu_o), // Templated + .spr_bus_ack_o (spr_bus_ack_dmmu_o), // Templated + // Inputs + .clk (clk), + .rst (rst), + .enable_i (dmmu_enable), // Templated + .virt_addr_i (virt_addr), // Templated + .virt_addr_match_i (ctrl_lsu_adr_i), // Templated + .op_store_i (ctrl_op_lsu_store_i), // Templated + .op_load_i (ctrl_op_lsu_load_i), // Templated + .supervisor_mode_i (supervisor_mode_i), + .tlb_reload_ack_i (tlb_reload_ack), // Templated + .tlb_reload_data_i (tlb_reload_data), // Templated + .tlb_reload_pagefault_clear_i (tlb_reload_pagefault_clear), // Templated + .spr_bus_addr_i (spr_bus_addr_i[15:0]), + .spr_bus_we_i (spr_bus_we_i), + .spr_bus_stb_i (dmmu_spr_bus_stb), // Templated + .spr_bus_dat_i (spr_bus_dat_i[OPTION_OPERAND_WIDTH-1:0])); +end else begin + assign dmmu_cache_inhibit = 0; + assign tlb_miss = 0; + assign pagefault = 0; + assign tlb_reload_busy = 0; + assign tlb_reload_req = 0; + assign tlb_reload_pagefault = 0; +end +endgenerate + +endmodule // mor1kx_lsu_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_espresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_espresso.v new file mode 100644 index 0000000..872013a --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_espresso.v @@ -0,0 +1,275 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Load, store unit for espresso pipeline + + All combinatorial outputs to pipeline + Dbus interface request signal out synchronous + + 32-bit specific due to sign extension of results + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_lsu_espresso + (/*AUTOARG*/ + // Outputs + lsu_result_o, lsu_valid_o, lsu_except_dbus_o, lsu_except_align_o, + dbus_adr_o, dbus_req_o, dbus_dat_o, dbus_bsel_o, dbus_we_o, + dbus_burst_o, + // Inputs + clk, rst, padv_fetch_i, lsu_adr_i, rfb_i, op_lsu_load_i, + op_lsu_store_i, lsu_length_i, lsu_zext_i, exception_taken_i, + du_restart_i, stepping_i, next_fetch_done_i, dbus_err_i, + dbus_ack_i, dbus_dat_i + ); + + parameter OPTION_OPERAND_WIDTH = 32; + parameter OPTION_REGISTERED_IO = "NO"; + + input clk, rst; + + input padv_fetch_i; + // calculated address from ALU + input [OPTION_OPERAND_WIDTH-1:0] lsu_adr_i; + + // register file B in (store operand) + input [OPTION_OPERAND_WIDTH-1:0] rfb_i; + // from decode stage regs, indicate if load or store + input op_lsu_load_i; + input op_lsu_store_i; + input [1:0] lsu_length_i; + input lsu_zext_i; + + input exception_taken_i; + input du_restart_i; + input stepping_i; + input next_fetch_done_i; + + + output [OPTION_OPERAND_WIDTH-1:0] lsu_result_o; + output lsu_valid_o; + // exception output + output lsu_except_dbus_o; + output lsu_except_align_o; + + // interface to data bus + output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o; + output dbus_req_o; + output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o; + output [3:0] dbus_bsel_o; + output dbus_we_o; + output dbus_burst_o; + input dbus_err_i; + input dbus_ack_i; + input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i; + + reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_aligned; // comb. + reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_extended; // comb. + + + reg [OPTION_OPERAND_WIDTH-1:0] dbus_adr_r; + + reg [3:0] dbus_bsel; + + reg dbus_err_r; + + reg access_done; + + reg [OPTION_OPERAND_WIDTH-1:0] lsu_result_r; + + reg op_lsu; + + wire align_err_word; + wire align_err_short; + + wire align_err; + + wire except_align; + reg except_align_r; + + reg except_dbus; + reg execute_go; + + assign dbus_dat_o = (lsu_length_i == 2'b00) ? // byte access + {rfb_i[7:0],rfb_i[7:0],rfb_i[7:0],rfb_i[7:0]} : + (lsu_length_i == 2'b01) ? // halfword access + {rfb_i[15:0],rfb_i[15:0]} : + rfb_i; // word access + + assign align_err_word = |dbus_adr_o[1:0]; + assign align_err_short = dbus_adr_o[0]; + + + assign lsu_valid_o = dbus_ack_i | dbus_err_r| access_done; + assign lsu_except_dbus_o = dbus_err_r | except_dbus; + + assign align_err = (lsu_length_i == 2'b10) & align_err_word | + (lsu_length_i == 2'b01) & align_err_short; + + assign lsu_except_align_o = except_align_r; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + execute_go <= 0; + else + execute_go <= padv_fetch_i | (stepping_i & next_fetch_done_i); + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + access_done <= 0; + else if (padv_fetch_i | du_restart_i) + access_done <= 0; + else if (dbus_ack_i | dbus_err_r | lsu_except_align_o) + access_done <= 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + except_align_r <= 0; + else if (exception_taken_i) + except_align_r <= 0; + else + except_align_r <= except_align; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + except_dbus <= 0; + else if (exception_taken_i) + except_dbus <= 0; + else if (dbus_err_r) + except_dbus <= 1; + + // Need to register address due to behavior of RF when source register is + // same as destination register - value changes after one cycle to the + // forwarding register's value, which is incorrect. + // So we save it on first cycle. + // TODO - perhaps detect in RF when this is case, and make it keep the + // output steady to avoid an extra address registering stage here. + always @(posedge clk `OR_ASYNC_RST) + if (rst) + dbus_adr_r <= 0; + else if (execute_go & (op_lsu_load_i | op_lsu_store_i)) + dbus_adr_r <= lsu_adr_i; + + // Big endian bus mapping + always @(*) + case (lsu_length_i) + 2'b00: // byte access + case(dbus_adr_o[1:0]) + 2'b00: + dbus_bsel = 4'b1000; + 2'b01: + dbus_bsel = 4'b0100; + 2'b10: + dbus_bsel = 4'b0010; + 2'b11: + dbus_bsel = 4'b0001; + endcase + 2'b01: // halfword access + case(dbus_adr_o[1]) + 1'b0: + dbus_bsel = 4'b1100; + 1'b1: + dbus_bsel = 4'b0011; + endcase + 2'b10, + 2'b11: + dbus_bsel = 4'b1111; + endcase + + assign dbus_bsel_o = dbus_bsel; + + assign dbus_we_o = op_lsu_store_i; + + // Select part of read word + // Can use registered address here, as it'll take at least one cycle for + // the data to come back, and by that time dbus_adr_r has the address + always @* + case(dbus_adr_r[1:0]) + 2'b00: + dbus_dat_aligned = dbus_dat_i; + 2'b01: + dbus_dat_aligned = {dbus_dat_i[23:0],8'd0}; + 2'b10: + dbus_dat_aligned = {dbus_dat_i[15:0],16'd0}; + 2'b11: + dbus_dat_aligned = {dbus_dat_i[7:0],24'd0}; + endcase // case (dbus_adr_r[1:0]) + + // Do appropriate extension + always @(*) + case({lsu_zext_i, lsu_length_i}) + 3'b100: // lbz + dbus_dat_extended = {24'd0,dbus_dat_aligned[31:24]}; + 3'b101: // lhz + dbus_dat_extended = {16'd0,dbus_dat_aligned[31:16]}; + 3'b000: // lbs + dbus_dat_extended = {{24{dbus_dat_aligned[31]}}, + dbus_dat_aligned[31:24]}; + 3'b001: // lhs + dbus_dat_extended = {{16{dbus_dat_aligned[31]}}, + dbus_dat_aligned[31:16]}; + default: + dbus_dat_extended = dbus_dat_aligned; + endcase + + // Register result incase writeback doesn't occur for a few cycles + // TODO - remove this - we should write straight into the RF! + always @(posedge clk) + if (dbus_ack_i & op_lsu_load_i) + lsu_result_r <= dbus_dat_extended; + + assign dbus_burst_o = 0; + + // Break up paths of signals which are usually pretty long + generate + if (OPTION_REGISTERED_IO!="NO") + begin : registered_io + + assign dbus_adr_o = dbus_adr_r; + + always @(posedge clk) + begin + dbus_err_r <= dbus_err_i; + op_lsu <= op_lsu_load_i | op_lsu_store_i; + end + + // Make sure padv_i isn't high because we'll be registering the + // fact that this cycle is an LSU op while it is + assign dbus_req_o = !execute_go & op_lsu & + !(except_align | except_align_r) & + !access_done; + + assign except_align = op_lsu & (op_lsu_load_i | op_lsu_store_i) & + align_err & !execute_go; + + end + else + begin : nonregistered_io + + assign dbus_adr_o = execute_go ? lsu_adr_i : dbus_adr_r; + + always @* + begin + dbus_err_r = dbus_err_i; + op_lsu = op_lsu_load_i | op_lsu_store_i; + end + + assign dbus_req_o = op_lsu & !except_align & !access_done; + + assign except_align = op_lsu & align_err; + + end + endgenerate + + assign lsu_result_o = access_done ? lsu_result_r : dbus_dat_extended; + +endmodule // mor1kx_lsu diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_pic.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_pic.v new file mode 100644 index 0000000..38448cc --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_pic.v @@ -0,0 +1,142 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx PIC + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_pic + (/*AUTOARG*/ + // Outputs + spr_picmr_o, spr_picsr_o, spr_bus_ack, spr_dat_o, + // Inputs + clk, rst, irq_i, spr_access_i, spr_we_i, spr_addr_i, spr_dat_i + ); + + parameter OPTION_PIC_TRIGGER="LEVEL"; + parameter OPTION_PIC_NMI_WIDTH = 0; + + input clk; + input rst; + + input [31:0] irq_i; + + output [31:0] spr_picmr_o; + output [31:0] spr_picsr_o; + + // SPR Bus interface + input spr_access_i; + input spr_we_i; + input [15:0] spr_addr_i; + input [31:0] spr_dat_i; + output spr_bus_ack; + output [31:0] spr_dat_o; + + // Registers + reg [31:0] spr_picmr; + reg [31:0] spr_picsr; + + wire spr_picmr_access; + wire spr_picsr_access; + + wire [31:0] irq_unmasked; + + assign spr_picmr_o = spr_picmr; + assign spr_picsr_o = spr_picsr; + + assign spr_picmr_access = + spr_access_i & + (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR)); + assign spr_picsr_access = + spr_access_i & + (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR)); + + assign spr_bus_ack = spr_access_i; + assign spr_dat_o = (spr_access_i & spr_picsr_access) ? spr_picsr : + (spr_access_i & spr_picmr_access) ? spr_picmr : + 0; + + assign irq_unmasked = spr_picmr & irq_i; + + generate + + genvar irqline; + + if (OPTION_PIC_TRIGGER=="EDGE") begin : edge_triggered + reg [31:0] irq_unmasked_r; + wire [31:0] irq_unmasked_edge; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + irq_unmasked_r <= 0; + else + irq_unmasked_r <= irq_unmasked; + + for(irqline=0;irqline<32;irqline=irqline+1) begin: picgenerate + assign irq_unmasked_edge[irqline] = irq_unmasked[irqline] & + !irq_unmasked_r[irqline]; + + // PIC status register + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_picsr[irqline] <= 0; + // Set + else if (irq_unmasked_edge[irqline]) + spr_picsr[irqline] <= 1; + // Clear + else if (spr_we_i & spr_picsr_access & spr_dat_i[irqline]) + spr_picsr[irqline] <= 0; + end + end else if (OPTION_PIC_TRIGGER=="LEVEL") begin : level_triggered + for(irqline=0;irqline<32;irqline=irqline+1) + begin: picsrlevelgenerate + // PIC status register + always @(*) + spr_picsr[irqline] <= irq_unmasked[irqline]; + end + end // if (OPTION_PIC_TRIGGER=="LEVEL") + + else if (OPTION_PIC_TRIGGER=="LATCHED_LEVEL") begin : latched_level + for(irqline=0;irqline<32;irqline=irqline+1) + begin: piclatchedlevelgenerate + // PIC status register + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_picsr[irqline] <= 0; + else if (spr_we_i && spr_picsr_access) + spr_picsr[irqline] <= irq_unmasked[irqline] | + spr_dat_i[irqline]; + else + spr_picsr[irqline] <= spr_picsr[irqline] | + irq_unmasked[irqline]; + end // block: picgenerate + end // if (OPTION_PIC_TRIGGER=="EDGE") + + else begin : invalid + initial begin + $display("Error - invalid PIC level detection option %s", + OPTION_PIC_TRIGGER); + $finish; + end + end // else: !if(OPTION_PIC_TRIGGER=="LEVEL") + endgenerate + + // PIC (un)mask register + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_picmr <= {{(32-OPTION_PIC_NMI_WIDTH){1'b0}}, + {OPTION_PIC_NMI_WIDTH{1'b1}}}; + else if (spr_we_i && spr_picmr_access) + spr_picmr <= {spr_dat_i[31:OPTION_PIC_NMI_WIDTH], + {OPTION_PIC_NMI_WIDTH{1'b1}}}; + +endmodule // mor1kx_pic diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_cappuccino.v new file mode 100644 index 0000000..6a356f2 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_cappuccino.v @@ -0,0 +1,363 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Register file for cappuccino pipeline + Handles reading the register file rams and register bypassing. + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + Stefan Kristiansson + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_rf_cappuccino + #( + parameter FEATURE_FASTCONTEXTS = "NONE", + parameter OPTION_RF_CLEAR_ON_INIT = 0, + parameter OPTION_RF_NUM_SHADOW_GPR = 0, + parameter OPTION_RF_ADDR_WIDTH = 5, + parameter OPTION_RF_WORDS = 32, + parameter FEATURE_DEBUGUNIT = "NONE", + parameter OPTION_OPERAND_WIDTH = 32 + ) + ( + input clk, + input rst, + + // pipeline control signal in + input padv_decode_i, + input padv_execute_i, + input padv_ctrl_i, + + + input decode_valid_i, + + input fetch_rf_adr_valid_i, + + // GPR numbers + input [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_i, + input [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_i, + + input [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_i, + input [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_i, + + input [OPTION_RF_ADDR_WIDTH-1:0] execute_rfd_adr_i, + input [OPTION_RF_ADDR_WIDTH-1:0] ctrl_rfd_adr_i, + input [OPTION_RF_ADDR_WIDTH-1:0] wb_rfd_adr_i, + + // SPR interface + input [15:0] spr_bus_addr_i, + input spr_bus_stb_i, + input spr_bus_we_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i, + output spr_gpr_ack_o, + output [OPTION_OPERAND_WIDTH-1:0] spr_gpr_dat_o, + + // Write back signal indications + input execute_rf_wb_i, + input ctrl_rf_wb_i, + input wb_rf_wb_i, + + input [OPTION_OPERAND_WIDTH-1:0] result_i, + input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i, + + input pipeline_flush_i, + + output [OPTION_OPERAND_WIDTH-1:0] decode_rfa_o, + output [OPTION_OPERAND_WIDTH-1:0] decode_rfb_o, + output [OPTION_OPERAND_WIDTH-1:0] execute_rfa_o, + output [OPTION_OPERAND_WIDTH-1:0] execute_rfb_o + ); + +`include "mor1kx_utils.vh" + + localparam RF_ADDR_WIDTH = OPTION_RF_ADDR_WIDTH + + ((OPTION_RF_NUM_SHADOW_GPR == 1) ? 1 : + `clog2(OPTION_RF_NUM_SHADOW_GPR)); + + wire [OPTION_OPERAND_WIDTH-1:0] rfa_ram_o; + wire [OPTION_OPERAND_WIDTH-1:0] rfb_ram_o; + + reg [OPTION_OPERAND_WIDTH-1:0] wb_hazard_result; + reg [OPTION_OPERAND_WIDTH-1:0] execute_rfa; + reg [OPTION_OPERAND_WIDTH-1:0] execute_rfb; + + wire [RF_ADDR_WIDTH-1:0] rfa_rdad; + wire [RF_ADDR_WIDTH-1:0] rfb_rdad; + + wire rfa_rden; + wire rfb_rden; + + wire rf_wren; + wire [RF_ADDR_WIDTH-1:0] rf_wradr; + wire [OPTION_OPERAND_WIDTH-1:0] rf_wrdat; + + reg flushing; + + // Keep track of the flush signal, this is needed to not wrongly assert + // execute_hazard after an exception (or rfe) has happened. + // What happens in that case is that the instruction in execute stage is + // invalid until the next padv_decode, so it's execute_rfd_adr can not be + // used to evaluate the execute_hazard. + always @(posedge clk) + if (pipeline_flush_i) + flushing <= 1; + else if (padv_decode_i) + flushing <= 0; + + // Detect hazards + reg execute_hazard_a; + reg execute_hazard_b; + always @(posedge clk) + if (pipeline_flush_i) begin + execute_hazard_a <= 0; + execute_hazard_b <= 0; + end else if (padv_decode_i & !flushing) begin + execute_hazard_a <= execute_rf_wb_i & + (execute_rfd_adr_i == decode_rfa_adr_i); + execute_hazard_b <= execute_rf_wb_i & + (execute_rfd_adr_i == decode_rfb_adr_i); + end + + reg [OPTION_OPERAND_WIDTH-1:0] execute_hazard_result_r; + always @(posedge clk) + if (decode_valid_i) + execute_hazard_result_r <= ctrl_alu_result_i; + + wire [OPTION_OPERAND_WIDTH-1:0] execute_hazard_result; + assign execute_hazard_result = decode_valid_i ? ctrl_alu_result_i : + execute_hazard_result_r; + + reg ctrl_hazard_a; + reg ctrl_hazard_b; + always @(posedge clk) + if (padv_decode_i) begin + ctrl_hazard_a <= ctrl_rf_wb_i & (ctrl_rfd_adr_i == decode_rfa_adr_i); + ctrl_hazard_b <= ctrl_rf_wb_i & (ctrl_rfd_adr_i == decode_rfb_adr_i); + end + + reg [OPTION_OPERAND_WIDTH-1:0] ctrl_hazard_result_r; + always @(posedge clk) + if (decode_valid_i) + ctrl_hazard_result_r <= result_i; + + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_hazard_result; + assign ctrl_hazard_result = decode_valid_i ? result_i : ctrl_hazard_result_r; + + reg wb_hazard_a; + reg wb_hazard_b; + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + wb_hazard_a <= 0; + wb_hazard_b <= 0; + end else if (padv_decode_i) begin + wb_hazard_a <= wb_rf_wb_i & (wb_rfd_adr_i == decode_rfa_adr_i); + wb_hazard_b <= wb_rf_wb_i & (wb_rfd_adr_i == decode_rfb_adr_i); + end + + always @(posedge clk) + if (padv_decode_i) + wb_hazard_result <= result_i; + + // Bypassing to decode stage + // + // Since the decode stage doesn't read from the register file, we have to + // save any writes to the current read addresses in decode stage until + // fetch latch in new values. + // When fetch latch in the new values, and a writeback happens at the + // same time, we bypass that value too. + + // Port A + reg use_last_wb_a; + reg wb_to_decode_bypass_a; + reg [OPTION_OPERAND_WIDTH-1:0] wb_to_decode_result_a; + always @(posedge clk) + if (fetch_rf_adr_valid_i) begin + wb_to_decode_result_a <= result_i; + wb_to_decode_bypass_a <= wb_rf_wb_i & (wb_rfd_adr_i == fetch_rfa_adr_i); + use_last_wb_a <= 0; + end else if (wb_rf_wb_i) begin + if (decode_rfa_adr_i == wb_rfd_adr_i) begin + wb_to_decode_result_a <= result_i; + use_last_wb_a <= 1; + end + end + + wire execute_to_decode_bypass_a; + assign execute_to_decode_bypass_a = ctrl_rf_wb_i & + (ctrl_rfd_adr_i == decode_rfa_adr_i); + + wire ctrl_to_decode_bypass_a; + assign ctrl_to_decode_bypass_a = use_last_wb_a | wb_rf_wb_i & + (wb_rfd_adr_i == decode_rfa_adr_i); + + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_to_decode_result_a; + assign ctrl_to_decode_result_a = use_last_wb_a ? + wb_to_decode_result_a : result_i; + + // Port B + reg use_last_wb_b; + reg wb_to_decode_bypass_b; + reg [OPTION_OPERAND_WIDTH-1:0] wb_to_decode_result_b; + always @(posedge clk) + if (fetch_rf_adr_valid_i) begin + wb_to_decode_result_b <= result_i; + wb_to_decode_bypass_b <= wb_rf_wb_i & (wb_rfd_adr_i == fetch_rfb_adr_i); + use_last_wb_b <= 0; + end else if (wb_rf_wb_i) begin + if (decode_rfb_adr_i == wb_rfd_adr_i) begin + wb_to_decode_result_b <= result_i; + use_last_wb_b <= 1; + end + end + + wire execute_to_decode_bypass_b; + assign execute_to_decode_bypass_b = ctrl_rf_wb_i & + (ctrl_rfd_adr_i == decode_rfb_adr_i); + + wire ctrl_to_decode_bypass_b; + assign ctrl_to_decode_bypass_b = use_last_wb_b | wb_rf_wb_i & + (wb_rfd_adr_i == decode_rfb_adr_i); + + wire [OPTION_OPERAND_WIDTH-1:0] ctrl_to_decode_result_b; + assign ctrl_to_decode_result_b = use_last_wb_b ? + wb_to_decode_result_b : result_i; + + + assign decode_rfa_o = execute_to_decode_bypass_a ? ctrl_alu_result_i : + ctrl_to_decode_bypass_a ? ctrl_to_decode_result_a : + wb_to_decode_bypass_a ? wb_to_decode_result_a : + rfa_ram_o; + + assign decode_rfb_o = execute_to_decode_bypass_b ? ctrl_alu_result_i : + ctrl_to_decode_bypass_b ? ctrl_to_decode_result_b : + wb_to_decode_bypass_b ? wb_to_decode_result_b : + rfb_ram_o; + + assign execute_rfa_o = execute_hazard_a ? execute_hazard_result : + ctrl_hazard_a ? ctrl_hazard_result : + wb_hazard_a ? wb_hazard_result : + execute_rfa; + + assign execute_rfb_o = execute_hazard_b ? execute_hazard_result : + ctrl_hazard_b ? ctrl_hazard_result : + wb_hazard_b ? wb_hazard_result : + execute_rfb; + + always @(posedge clk) + if (padv_decode_i) begin + execute_rfa <= decode_rfa_o; + execute_rfb <= decode_rfb_o; + end + +generate +if (FEATURE_DEBUGUNIT!="NONE" || FEATURE_FASTCONTEXTS!="NONE" || + OPTION_RF_NUM_SHADOW_GPR > 0) begin + wire spr_gpr_we; + wire spr_gpr_re; + assign spr_gpr_we = (spr_bus_addr_i[15:9] == 7'h2) & + spr_bus_stb_i & spr_bus_we_i; + assign spr_gpr_re = (spr_bus_addr_i[15:9] == 7'h2) & + spr_bus_stb_i & !spr_bus_we_i & !padv_ctrl_i; + + reg spr_gpr_read_ack; + always @(posedge clk) + spr_gpr_read_ack <= spr_gpr_re; + + assign spr_gpr_ack_o = spr_gpr_we & !wb_rf_wb_i | + spr_gpr_re & spr_gpr_read_ack; + + assign rf_wren = wb_rf_wb_i | spr_gpr_we; + assign rf_wradr = wb_rf_wb_i ? wb_rfd_adr_i : spr_bus_addr_i; + assign rf_wrdat = wb_rf_wb_i ? result_i : spr_bus_dat_i; + + // Zero-pad unused parts of vector + if (OPTION_RF_NUM_SHADOW_GPR > 0) begin + assign rfa_rdad[RF_ADDR_WIDTH-1:OPTION_RF_ADDR_WIDTH] = + {(RF_ADDR_WIDTH-OPTION_RF_ADDR_WIDTH){1'b0}}; + assign rfb_rdad[RF_ADDR_WIDTH-1:OPTION_RF_ADDR_WIDTH] = + {(RF_ADDR_WIDTH-OPTION_RF_ADDR_WIDTH){1'b0}}; + end + +end else begin + assign spr_gpr_ack_o = 1; + + assign rf_wren = wb_rf_wb_i; + assign rf_wradr = wb_rfd_adr_i; + assign rf_wrdat = result_i; +end +endgenerate + + assign rfa_rdad[OPTION_RF_ADDR_WIDTH-1:0] = fetch_rfa_adr_i; + assign rfb_rdad[OPTION_RF_ADDR_WIDTH-1:0] = fetch_rfb_adr_i; + assign rfa_rden = fetch_rf_adr_valid_i; + assign rfb_rden = fetch_rf_adr_valid_i; + + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH (RF_ADDR_WIDTH), + .DATA_WIDTH (OPTION_OPERAND_WIDTH), + .CLEAR_ON_INIT (OPTION_RF_CLEAR_ON_INIT), + .ENABLE_BYPASS (0) + ) + rfa + ( + .clk (clk), + .dout (rfa_ram_o), + .raddr (rfa_rdad), + .re (rfa_rden), + .waddr (rf_wradr), + .we (rf_wren), + .din (rf_wrdat) + ); + + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH (RF_ADDR_WIDTH), + .DATA_WIDTH (OPTION_OPERAND_WIDTH), + .CLEAR_ON_INIT (OPTION_RF_CLEAR_ON_INIT), + .ENABLE_BYPASS (0) + ) + rfb + ( + .clk (clk), + .dout (rfb_ram_o), + .raddr (rfb_rdad), + .re (rfb_rden), + .waddr (rf_wradr), + .we (rf_wren), + .din (rf_wrdat) + ); + +generate +if (FEATURE_DEBUGUNIT!="NONE" || FEATURE_FASTCONTEXTS!="NONE" || + OPTION_RF_NUM_SHADOW_GPR > 0) begin : rfspr_gen + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH (RF_ADDR_WIDTH), + .DATA_WIDTH (OPTION_OPERAND_WIDTH), + .CLEAR_ON_INIT (OPTION_RF_CLEAR_ON_INIT), + .ENABLE_BYPASS (0) + ) + rfspr + ( + .clk (clk), + .dout (spr_gpr_dat_o), + .raddr (spr_bus_addr_i[RF_ADDR_WIDTH-1:0]), + .re (1'b1), + .waddr (rf_wradr), + .we (rf_wren), + .din (rf_wrdat) + ); +end else begin + assign spr_gpr_dat_o = 0; +end +endgenerate + +endmodule // mor1kx_rf_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_espresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_espresso.v new file mode 100644 index 0000000..25a91d6 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_espresso.v @@ -0,0 +1,180 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: Register file for espresso pipeline + + We get addresses for A and B read directly in from the instruction bus + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_rf_espresso + (/*AUTOARG*/ + // Outputs + rfa_o, rfb_o, + // Inputs + clk, rst, rfd_adr_i, rfa_adr_i, rfb_adr_i, rf_we_i, rf_re_i, + result_i + ); + + parameter OPTION_RF_ADDR_WIDTH = 5; + parameter OPTION_RF_WORDS = 32; + + parameter OPTION_OPERAND_WIDTH = 32; + + input clk, rst; + + + // GPR addresses + // These two directly from insn bus + input [OPTION_RF_ADDR_WIDTH-1:0] rfd_adr_i; + input [OPTION_RF_ADDR_WIDTH-1:0] rfa_adr_i; + // This one from the decode stage + input [OPTION_RF_ADDR_WIDTH-1:0] rfb_adr_i; + + // WE strobe from control stage + input rf_we_i; + + // Read enable strobe + input rf_re_i; + + input [OPTION_OPERAND_WIDTH-1:0] result_i; + + + output [OPTION_OPERAND_WIDTH-1:0] rfa_o; + output [OPTION_OPERAND_WIDTH-1:0] rfb_o; + + wire [OPTION_OPERAND_WIDTH-1:0] rfa_o_mux; + wire [OPTION_OPERAND_WIDTH-1:0] rfb_o_mux; + + + wire [OPTION_OPERAND_WIDTH-1:0] rfa_ram_o; + wire [OPTION_OPERAND_WIDTH-1:0] rfb_ram_o; + + reg [OPTION_OPERAND_WIDTH-1:0] result_last; + reg [OPTION_RF_ADDR_WIDTH-1:0] rfd_last; + reg [OPTION_RF_ADDR_WIDTH-1:0] rfd_r; + reg [OPTION_RF_ADDR_WIDTH-1:0] rfa_r; + reg [OPTION_RF_ADDR_WIDTH-1:0] rfb_r; + + wire rfa_o_use_last; + wire rfb_o_use_last; + reg rfa_o_using_last; + reg rfb_o_using_last; + + wire rfa_rden; + wire rfb_rden; + + wire rf_wren; + + // Read enables to make sure the last write-while-read propagates through + // once the use_last signal goes away (we might rely on the value remaining + // what it was, but the last registered result might get written again) so + // this forces a read to get that value out. + wire rfa_rden_for_last; + wire rfb_rden_for_last; + + // Avoid read-write + // Use when this instruction actually will write to its destination + // register. + assign rfa_o_use_last = (rfd_last == rfa_r); + assign rfb_o_use_last = (rfd_last == rfb_r); + + assign rfa_o = rfa_o_use_last ? result_last : rfa_ram_o; + + assign rfb_o = rfb_o_use_last ? result_last : rfb_ram_o; + + assign rfa_rden_for_last = (rfa_o_use_last & !rf_re_i); + assign rfb_rden_for_last = (rfb_o_use_last & !rf_re_i); + + assign rfa_rden = rf_re_i | rfa_rden_for_last; + assign rfb_rden = rf_re_i | rfb_rden_for_last; + + assign rf_wren = rf_we_i; + + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + rfa_r <= 0; + rfb_r <= 0; + rfd_r <= 0; + end + else if (rf_re_i) + begin + rfa_r <= rfa_adr_i; + rfb_r <= rfb_adr_i; + rfd_r <= rfd_adr_i; + end + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + rfd_last <= 0; + else if (rf_wren) + rfd_last <= rfd_adr_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + result_last <= 0; + else if (rf_wren) + result_last <= result_i; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) begin + rfa_o_using_last <= 0; + rfb_o_using_last <= 0; + end + else begin + if (!rfa_o_using_last) + rfa_o_using_last <= rfa_o_use_last & !rfa_rden; + else if (rfa_rden) + rfa_o_using_last <= 0; + + if (!rfb_o_using_last) + rfb_o_using_last <= rfb_o_use_last & !rfb_rden; + else if (rfb_rden) + rfb_o_using_last <= 0; + end + + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH (OPTION_RF_ADDR_WIDTH), + .DATA_WIDTH (OPTION_OPERAND_WIDTH), + .ENABLE_BYPASS (0) + ) + rfa + ( + .clk (clk), + .dout (rfa_ram_o), + .raddr (rfa_adr_i), + .re (rfa_rden), + .waddr (rfd_adr_i), + .we (rf_wren), + .din (result_i) + ); + + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH (OPTION_RF_ADDR_WIDTH), + .DATA_WIDTH (OPTION_OPERAND_WIDTH), + .ENABLE_BYPASS (0) + ) + rfb + ( + .clk (clk), + .dout (rfb_ram_o), + .raddr (rfb_adr_i), + .re (rfb_rden), + .waddr (rfd_adr_i), + .we (rf_wren), + .din (result_i) + ); + +endmodule // mor1kx_execute_alu diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_simple_dpram_sclk.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_simple_dpram_sclk.v new file mode 100644 index 0000000..8af763f --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_simple_dpram_sclk.v @@ -0,0 +1,72 @@ +/****************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: + Simple single clocked dual port ram (separate read and write ports), + with optional bypass logic. + + Copyright (C) 2012 Stefan Kristiansson + + ******************************************************************************/ + +module mor1kx_simple_dpram_sclk + #( + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32, + parameter CLEAR_ON_INIT = 0, + parameter ENABLE_BYPASS = 1 + ) + ( + input clk, + input [ADDR_WIDTH-1:0] raddr, + input re, + input [ADDR_WIDTH-1:0] waddr, + input we, + input [DATA_WIDTH-1:0] din, + output [DATA_WIDTH-1:0] dout + ); + + reg [DATA_WIDTH-1:0] mem[(1< + + ******************************************************************************/ +`include "mor1kx-defines.v" + +module mor1kx_store_buffer + #( + parameter DEPTH_WIDTH = 4, + parameter OPTION_OPERAND_WIDTH = 32 + ) + ( + input clk, + input rst, + + input [OPTION_OPERAND_WIDTH-1:0] pc_i, + input [OPTION_OPERAND_WIDTH-1:0] adr_i, + input [OPTION_OPERAND_WIDTH-1:0] dat_i, + input [OPTION_OPERAND_WIDTH/8-1:0] bsel_i, + input atomic_i, + input write_i, + + output [OPTION_OPERAND_WIDTH-1:0] pc_o, + output [OPTION_OPERAND_WIDTH-1:0] adr_o, + output [OPTION_OPERAND_WIDTH-1:0] dat_o, + output [OPTION_OPERAND_WIDTH/8-1:0] bsel_o, + output atomic_o, + input read_i, + + output full_o, + output empty_o + ); + + // The fifo stores address + data + byte sel + pc + atomic + localparam FIFO_DATA_WIDTH = OPTION_OPERAND_WIDTH*3 + + OPTION_OPERAND_WIDTH/8 + 1; + + wire [FIFO_DATA_WIDTH-1:0] fifo_dout; + wire [FIFO_DATA_WIDTH-1:0] fifo_din; + + reg [DEPTH_WIDTH:0] write_pointer; + reg [DEPTH_WIDTH:0] read_pointer; + + assign fifo_din = {adr_i, dat_i, bsel_i, pc_i, atomic_i}; + assign {adr_o, dat_o, bsel_o, pc_o, atomic_o} = fifo_dout; + + assign full_o = (write_pointer[DEPTH_WIDTH] != read_pointer[DEPTH_WIDTH]) && + (write_pointer[DEPTH_WIDTH-1:0] == read_pointer[DEPTH_WIDTH-1:0]); + assign empty_o = write_pointer == read_pointer; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + write_pointer <= 0; + else if (write_i) + write_pointer <= write_pointer + 1; + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + read_pointer <= 0; + else if (read_i) + read_pointer <= read_pointer + 1; + + mor1kx_simple_dpram_sclk + #( + .ADDR_WIDTH(DEPTH_WIDTH), + .DATA_WIDTH(FIFO_DATA_WIDTH), + .ENABLE_BYPASS(1) + ) + fifo_ram + ( + .clk (clk), + .dout (fifo_dout), + .raddr (read_pointer[DEPTH_WIDTH-1:0]), + .re (read_i), + .waddr (write_pointer[DEPTH_WIDTH-1:0]), + .we (write_i), + .din (fifo_din) + ); + +endmodule diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ticktimer.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ticktimer.v new file mode 100644 index 0000000..f0eb5b5 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ticktimer.v @@ -0,0 +1,90 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: mor1kx tick timer unit + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_ticktimer + ( + input clk, + input rst, + + output [31:0] spr_ttmr_o, + output [31:0] spr_ttcr_o, + + // SPR Bus interface + input spr_access_i, + input spr_we_i, + input [15:0] spr_addr_i, + input [31:0] spr_dat_i, + output spr_bus_ack, + output [31:0] spr_dat_o + ); + + // Registers + reg [31:0] spr_ttmr; + reg [31:0] spr_ttcr; + + wire spr_ttmr_access; + wire spr_ttcr_access; + + // ttcr control wires + wire ttcr_clear; + wire ttcr_run; + wire ttcr_match; + + assign spr_ttmr_o = spr_ttmr; + assign spr_ttcr_o = spr_ttcr; + + assign spr_ttmr_access = + spr_access_i & + (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_TTMR_ADDR)); + assign spr_ttcr_access = + spr_access_i & + (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_TTCR_ADDR)); + + assign spr_bus_ack = spr_access_i; + assign spr_dat_o = (spr_access_i & spr_ttcr_access) ? spr_ttcr : + (spr_access_i & spr_ttmr_access) ? spr_ttmr : 0; + + assign ttcr_match = spr_ttcr[27:0] == spr_ttmr[27:0]; + + // Timer SPR control + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_ttmr <= 0; + else if (spr_we_i & spr_ttmr_access) + spr_ttmr <= spr_dat_i[31:0]; + else if (ttcr_match & spr_ttmr[29]) + spr_ttmr[28] <= 1; // Generate interrupt + + // Modes (spr_ttmr[31:30]): + // 00 Tick timer is disabled. + // 01 Timer is restarted on ttcr_match. + // 10 Timer stops when ttcr_match is true. + // 11 Timer does not stop when ttcr_match is true + assign ttcr_clear = (spr_ttmr[31:30] == 2'b01) & ttcr_match; + assign ttcr_run = (spr_ttmr[31:30] != 2'b00) & !ttcr_match | + (spr_ttmr[31:30] == 2'b11); + + always @(posedge clk `OR_ASYNC_RST) + if (rst) + spr_ttcr <= 0; + else if (spr_we_i & spr_ttcr_access) + spr_ttcr <= spr_dat_i[31:0]; + else if (ttcr_clear) + spr_ttcr <= 0; + else if (ttcr_run) + spr_ttcr <= spr_ttcr + 1; + +endmodule // mor1kx_ticktimer diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_true_dpram_sclk.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_true_dpram_sclk.v new file mode 100644 index 0000000..87ebf75 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_true_dpram_sclk.v @@ -0,0 +1,56 @@ +/****************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: True dual port ram with single clock + + Copyright (C) 2013 Stefan Kristiansson + + ******************************************************************************/ + +module mor1kx_true_dpram_sclk + #( + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32 + ) + ( + input clk, + input [ADDR_WIDTH-1:0] addr_a, + input we_a, + input [DATA_WIDTH-1:0] din_a, + output [DATA_WIDTH-1:0] dout_a, + input [ADDR_WIDTH-1:0] addr_b, + input we_b, + input [DATA_WIDTH-1:0] din_b, + output [DATA_WIDTH-1:0] dout_b + ); + + reg [DATA_WIDTH-1:0] mem[(1< + + ******************************************************************************/ + +`ifndef _MOR1KX_UTILS_VH_ +`define _MOR1KX_UTILS_VH_ 1 +// +// clog2 - replacement for $clog for tools that doesn't support verilog 2005. +// However, icarus doesn't support constant user functions, so it has to be +// implemened with a bit of `define trickery. +// +`ifdef __ICARUS__ +`define clog2 $clog2 +`else +`define clog2 clog2 +`endif + +`endif // _MOR1KX_UTILS_VH_ + +function integer clog2; +input integer in; +begin + in = in - 1; + for (clog2 = 0; in > 0; clog2=clog2+1) + in = in >> 1; +end +endfunction + +// +// Find First 1 - Start from MSB and count downwards, returns 0 when no bit set +// +function integer ff1; +input integer in; +input integer width; +integer i; +begin + ff1 = 0; + for (i = width-1; i >= 0; i=i-1) begin + if (in[i]) + ff1 = i; + end +end +endfunction + +// +// Find Last 1 - Start from LSB and count upwards, returns 0 when no bit set +// +function integer fl1; +input integer in; +input integer width; +integer i; +begin + fl1 = 0; + for (i = 0; i < width; i=i+1) begin + if (in[i]) + fl1 = i; + end +end +endfunction + +// +// Reverse bits in a vector +// +function integer reverse_bits; +input integer in; +input integer width; +integer i; +begin + for (i = 0; i < width; i=i+1) begin + reverse_bits[width-i] = in[i]; + end +end +endfunction + +// +// Reverse bytes in a vector +// +function integer reverse_bytes; +input integer in; +input integer width; +integer i; +begin + for (i = 0; i < width; i=i+8) begin + reverse_bytes[(width-1)-i-:8] = in[i+:8]; + end +end +endfunction diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v new file mode 100644 index 0000000..2d571b2 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v @@ -0,0 +1,55 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: RF writeback mux + + Choose between ALU and LSU input. + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_wb_mux_cappuccino + #( + parameter OPTION_OPERAND_WIDTH = 32 + ) + ( + input clk, + input rst, + + input [OPTION_OPERAND_WIDTH-1:0] alu_result_i, + input [OPTION_OPERAND_WIDTH-1:0] lsu_result_i, + input [OPTION_OPERAND_WIDTH-1:0] mul_result_i, + input [OPTION_OPERAND_WIDTH-1:0] spr_i, + + output [OPTION_OPERAND_WIDTH-1:0] rf_result_o, + + input op_mul_i, + input op_lsu_load_i, + input op_mfspr_i + ); + + reg [OPTION_OPERAND_WIDTH-1:0] rf_result; + reg wb_op_mul; + + assign rf_result_o = wb_op_mul ? mul_result_i : rf_result; + + always @(posedge clk) + if (op_mfspr_i) + rf_result <= spr_i; + else if (op_lsu_load_i) + rf_result <= lsu_result_i; + else + rf_result <= alu_result_i; + + always @(posedge clk) + wb_op_mul <= op_mul_i; + +endmodule // mor1kx_wb_mux_cappuccino diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v new file mode 100644 index 0000000..82a6996 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v @@ -0,0 +1,53 @@ +/* **************************************************************************** + This Source Code Form is subject to the terms of the + Open Hardware Description License, v. 1.0. If a copy + of the OHDL was not distributed with this file, You + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt + + Description: RF writeback mux for espresso pipeline + + Choose between ALU and LSU input. All combinatorial + + Copyright (C) 2012 Authors + + Author(s): Julius Baxter + +***************************************************************************** */ + +`include "mor1kx-defines.v" + +module mor1kx_wb_mux_espresso + (/*AUTOARG*/ + // Outputs + rf_result_o, + // Inputs + clk, rst, alu_result_i, lsu_result_i, ppc_i, pc_fetch_next_i, + spr_i, op_jal_i, op_lsu_load_i, op_mfspr_i + ); + + parameter OPTION_OPERAND_WIDTH = 32; + + input clk, rst; + + input [OPTION_OPERAND_WIDTH-1:0] alu_result_i; + input [OPTION_OPERAND_WIDTH-1:0] lsu_result_i; + input [OPTION_OPERAND_WIDTH-1:0] ppc_i; + input [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_i; + input [OPTION_OPERAND_WIDTH-1:0] spr_i; + + output [OPTION_OPERAND_WIDTH-1:0] rf_result_o; + + input op_jal_i; + input op_lsu_load_i; + input op_mfspr_i; + + + assign rf_result_o = op_lsu_load_i ? lsu_result_i : + op_mfspr_i ? spr_i : + // Use the PC we've calcuated from the fetch unit + // to save inferring a 32-bit adder here like we + // would if we did "ppc_i + 8" + op_jal_i ? pc_fetch_next_i: + alu_result_i; + +endmodule // mor1kx_wb_mux_espresso diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_addsub.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_addsub.v new file mode 100644 index 0000000..9db4a46 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_addsub.v @@ -0,0 +1,338 @@ +////////////////////////////////////////////////////////////////////// +// // +// pfpu32_addsub // +// // +// This file is part of the mor1kx project // +// https://github.com/openrisc/mor1kx // +// // +// Description // +// addition/subtraction pipeline for single precision floating // +// point numbers // +// // +// Author(s): // +// - Original design (FPU100) - // +// Jidan Al-eryani, jidan@gmx.net // +// - Conv. to Verilog and inclusion in OR1200 - // +// Julius Baxter, julius@opencores.org // +// - Update for mor1kx, // +// bug fixing and further development - // +// Andrey Bacherov, avbacherov@opencores.org // +// // +////////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2006, 2010, 2014 // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // +// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // +// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // +// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // +// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // +// POSSIBILITY OF SUCH DAMAGE. // +////////////////////////////////////////////////////////////////////// + +`include "mor1kx-defines.v" + + +module pfpu32_addsub +( + input clk, + input rst, + input flush_i, // flushe pipe + input adv_i, // advance pipe + input start_i, // start add/sub + input is_sub_i, // 1: substruction, 0: addition + // input 'a' related values + input signa_i, + input [9:0] exp10a_i, + input [23:0] fract24a_i, + input infa_i, + // input 'b' related values + input signb_i, + input [9:0] exp10b_i, + input [23:0] fract24b_i, + input infb_i, + // 'a'/'b' related + input snan_i, + input qnan_i, + input anan_sign_i, + input addsub_agtb_i, + input addsub_aeqb_i, + // outputs + output reg add_rdy_o, // ready + output reg add_sign_o, // signum + output reg add_sub_0_o, // flag that actual substruction is performed and result is zero + output reg [4:0] add_shl_o, // do left shift in align stage + output reg [9:0] add_exp10shl_o, // exponent for left shift align + output reg [9:0] add_exp10sh0_o, // exponent for no shift in align + output reg [27:0] add_fract28_o, // fractional with appended {r,s} bits + output reg add_inv_o, // invalid operation flag + output reg add_inf_o, // infinity output reg + output reg add_snan_o, // signaling NaN output reg + output reg add_qnan_o, // quiet NaN output reg + output reg add_anan_sign_o // signum for output nan +); + /* + Any stage's output is registered. + Definitions: + s??o_name - "S"tage number "??", "O"utput + s??t_name - "S"tage number "??", "T"emporary (internally) + */ + + /* Stage #1: pre addition / substruction align */ + + // detection of some exceptions + // inf - inf -> invalid operation; snan output + wire s1t_inv = infa_i & infb_i & + (signa_i ^ (is_sub_i ^ signb_i)); + // inf input + wire s1t_inf_i = infa_i | infb_i; + + // signums for calculation + wire s1t_calc_signa = signa_i; + wire s1t_calc_signb = (signb_i ^ is_sub_i); + + // not shifted operand and its signum + wire [23:0] s1t_fract24_nsh = + addsub_agtb_i ? fract24a_i : fract24b_i; + + // operand for right shift + wire [23:0] s1t_fract24_fsh = + addsub_agtb_i ? fract24b_i : fract24a_i; + + // shift amount + wire [9:0] s1t_exp_diff = + addsub_agtb_i ? (exp10a_i - exp10b_i) : + (exp10b_i - exp10a_i); + + // limiter by 31 + wire [4:0] s1t_shr = s1t_exp_diff[4:0] | {5{|s1t_exp_diff[9:5]}}; + + // stage #1 outputs + // input related + reg s1o_inv, s1o_inf_i, + s1o_snan_i, s1o_qnan_i, s1o_anan_i_sign; + // computation related + reg s1o_aeqb; + reg [4:0] s1o_shr; + reg s1o_sign_nsh; + reg s1o_op_sub; + reg [9:0] s1o_exp10c; + reg [23:0] s1o_fract24_nsh; + reg [23:0] s1o_fract24_fsh; + // registering + always @(posedge clk) begin + if(adv_i) begin + // input related + s1o_inv <= s1t_inv; + s1o_inf_i <= s1t_inf_i; + s1o_snan_i <= snan_i; + s1o_qnan_i <= qnan_i; + s1o_anan_i_sign <= anan_sign_i; + // computation related + s1o_aeqb <= addsub_aeqb_i; + s1o_shr <= s1t_shr & {5{~s1t_inf_i}}; + s1o_sign_nsh <= addsub_agtb_i ? s1t_calc_signa : s1t_calc_signb; + s1o_op_sub <= s1t_calc_signa ^ s1t_calc_signb; + s1o_exp10c <= addsub_agtb_i ? exp10a_i : exp10b_i; + s1o_fract24_nsh <= s1t_fract24_nsh & {24{~s1t_inf_i}}; + s1o_fract24_fsh <= s1t_fract24_fsh & {24{~s1t_inf_i}}; + end // advance + end // posedge clock + + // ready is special case + reg s1o_ready; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + s1o_ready <= 0; + else if(flush_i) + s1o_ready <= 0; + else if(adv_i) + s1o_ready <= start_i; + end // posedge clock + + + /* Stage 2: multiplex and shift */ + + + // shifter + wire [25:0] s2t_fract26_fsh = {s1o_fract24_fsh,2'd0}; + wire [25:0] s2t_fract26_shr = s2t_fract26_fsh >> s1o_shr; + + // sticky + reg s2t_sticky; + always @(s1o_shr or s1o_fract24_fsh) begin + case(s1o_shr) + 5'd0, 5'd1, 5'd2 : s2t_sticky = 1'b0; // two added zero bits + 5'd3 : s2t_sticky = s1o_fract24_fsh[0]; + 5'd4 : s2t_sticky = |s1o_fract24_fsh[1:0]; + 5'd5 : s2t_sticky = |s1o_fract24_fsh[2:0]; + 5'd6 : s2t_sticky = |s1o_fract24_fsh[3:0]; + 5'd7 : s2t_sticky = |s1o_fract24_fsh[4:0]; + 5'd8 : s2t_sticky = |s1o_fract24_fsh[5:0]; + 5'd9 : s2t_sticky = |s1o_fract24_fsh[6:0]; + 5'd10: s2t_sticky = |s1o_fract24_fsh[7:0]; + 5'd11: s2t_sticky = |s1o_fract24_fsh[8:0]; + 5'd12: s2t_sticky = |s1o_fract24_fsh[9:0]; + 5'd13: s2t_sticky = |s1o_fract24_fsh[10:0]; + 5'd14: s2t_sticky = |s1o_fract24_fsh[11:0]; + 5'd15: s2t_sticky = |s1o_fract24_fsh[12:0]; + 5'd16: s2t_sticky = |s1o_fract24_fsh[13:0]; + 5'd17: s2t_sticky = |s1o_fract24_fsh[14:0]; + 5'd18: s2t_sticky = |s1o_fract24_fsh[15:0]; + 5'd19: s2t_sticky = |s1o_fract24_fsh[16:0]; + 5'd20: s2t_sticky = |s1o_fract24_fsh[17:0]; + 5'd21: s2t_sticky = |s1o_fract24_fsh[18:0]; + 5'd22: s2t_sticky = |s1o_fract24_fsh[19:0]; + 5'd23: s2t_sticky = |s1o_fract24_fsh[20:0]; + 5'd24: s2t_sticky = |s1o_fract24_fsh[21:0]; + 5'd25: s2t_sticky = |s1o_fract24_fsh[22:0]; + default: s2t_sticky = |s1o_fract24_fsh[23:0]; + endcase + end + + // add/sub of non-shifted and shifted operands + wire [27:0] s2t_fract28_shr = {1'b0,s2t_fract26_shr,s2t_sticky}; + + wire [27:0] s2t_fract28_add = {1'b0,s1o_fract24_nsh,3'd0} + + (s2t_fract28_shr ^ {28{s1o_op_sub}}) + + {27'd0,s1o_op_sub}; + + + // stage #2 outputs + // input related + reg s2o_inv, s2o_inf_i, + s2o_snan_i, s2o_qnan_i, s2o_anan_i_sign; + // computational related + reg s2o_signc; + reg [9:0] s2o_exp10c; + reg [26:0] s2o_fract27; + reg s2o_sub_0; // actual operation is substruction and the result is zero + reg s2o_sticky; // rounding support + // registering + always @(posedge clk) begin + if(adv_i) begin + // input related + s2o_inv <= s1o_inv; + s2o_inf_i <= s1o_inf_i; + s2o_snan_i <= s1o_snan_i; + s2o_qnan_i <= s1o_qnan_i; + s2o_anan_i_sign <= s1o_anan_i_sign; + // computation related + s2o_signc <= s1o_sign_nsh; + s2o_exp10c <= s1o_exp10c; + s2o_fract27 <= s2t_fract28_add[27:1]; + s2o_sub_0 <= s1o_aeqb & s1o_op_sub; + s2o_sticky <= s2t_sticky; + end // advance + end // posedge clock + + // ready is special case + reg s2o_ready; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + s2o_ready <= 0; + else if(flush_i) + s2o_ready <= 0; + else if(adv_i) + s2o_ready <= s1o_ready; + end // posedge clock + + + /* Stage 4: update exponent */ + + + // for possible left shift + // [26] bit is right shift flag + reg [4:0] s3t_nlz; + always @(s2o_fract27) begin + casez(s2o_fract27) + 27'b1??????????????????????????: s3t_nlz <= 0; // [26] bit: shift right + 27'b01?????????????????????????: s3t_nlz <= 0; // 1 is in place + 27'b001????????????????????????: s3t_nlz <= 1; + 27'b0001???????????????????????: s3t_nlz <= 2; + 27'b00001??????????????????????: s3t_nlz <= 3; + 27'b000001?????????????????????: s3t_nlz <= 4; + 27'b0000001????????????????????: s3t_nlz <= 5; + 27'b00000001???????????????????: s3t_nlz <= 6; + 27'b000000001??????????????????: s3t_nlz <= 7; + 27'b0000000001?????????????????: s3t_nlz <= 8; + 27'b00000000001????????????????: s3t_nlz <= 9; + 27'b000000000001???????????????: s3t_nlz <= 10; + 27'b0000000000001??????????????: s3t_nlz <= 11; + 27'b00000000000001?????????????: s3t_nlz <= 12; + 27'b000000000000001????????????: s3t_nlz <= 13; + 27'b0000000000000001???????????: s3t_nlz <= 14; + 27'b00000000000000001??????????: s3t_nlz <= 15; + 27'b000000000000000001?????????: s3t_nlz <= 16; + 27'b0000000000000000001????????: s3t_nlz <= 17; + 27'b00000000000000000001???????: s3t_nlz <= 18; + 27'b000000000000000000001??????: s3t_nlz <= 19; + 27'b0000000000000000000001?????: s3t_nlz <= 20; + 27'b00000000000000000000001????: s3t_nlz <= 21; + 27'b000000000000000000000001???: s3t_nlz <= 22; + 27'b0000000000000000000000001??: s3t_nlz <= 23; + 27'b00000000000000000000000001?: s3t_nlz <= 24; + 27'b000000000000000000000000001: s3t_nlz <= 25; + 27'b000000000000000000000000000: s3t_nlz <= 0; // zero result + endcase + end // always + + // left shift amount and corrected exponent + wire [4:0] s3t_nlz_m1 = (s3t_nlz - 5'd1); + wire [9:0] s3t_exp10c_m1 = s2o_exp10c - 10'd1; + wire [9:0] s3t_exp10c_mz = s2o_exp10c - {5'd0,s3t_nlz}; + wire [4:0] s3t_shl; + wire [9:0] s3t_exp10shl; + assign {s3t_shl,s3t_exp10shl} = + // shift isn't needed or impossible + (~(|s3t_nlz) | (s2o_exp10c == 10'd1)) ? + {5'd0,s2o_exp10c} : + // normalization is possible + (s2o_exp10c > s3t_nlz) ? {s3t_nlz,s3t_exp10c_mz} : + // denormalized cases + (s2o_exp10c == s3t_nlz) ? {s3t_nlz_m1,10'd1} : + {s3t_exp10c_m1[4:0],10'd1}; + + + // registering output + always @(posedge clk) begin + if(adv_i) begin + // input related + add_inv_o <= s2o_inv; + add_inf_o <= s2o_inf_i; + add_snan_o <= s2o_snan_i; + add_qnan_o <= s2o_qnan_i; + add_anan_sign_o <= s2o_anan_i_sign; + // computation related + add_sign_o <= s2o_signc; + add_sub_0_o <= s2o_sub_0; + add_shl_o <= s3t_shl; + add_exp10shl_o <= s3t_exp10shl; + add_exp10sh0_o <= s2o_exp10c; + add_fract28_o <= {s2o_fract27,s2o_sticky}; + end // advance + end // posedge clock + + // ready is special case + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + add_rdy_o <= 0; + else if(flush_i) + add_rdy_o <= 0; + else if(adv_i) + add_rdy_o <= s2o_ready; + end // posedge clock + +endmodule // pfpu32_addsub diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_cmp.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_cmp.v new file mode 100644 index 0000000..99ab4a0 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_cmp.v @@ -0,0 +1,180 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// pfpu32_cmp //// +//// 32-bit floating point comparision //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// Modified by Julius Baxter, July, 2010 //// +//// julius.baxter@orsoc.se //// +//// //// +//// Update for mor1kx, bug fixing and further development //// +//// Andrey Bacherov, 2014, //// +//// avbacherov@opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`include "mor1kx-defines.v" + +/* completely combinatorial module */ + +module pfpu32_fcmp +( + input fpu_op_is_comp_i, + input [`OR1K_FPUOP_WIDTH-1:0] cmp_type_i, + // operand 'a' related inputs + input signa_i, + input [9:0] exp10a_i, + input [23:0] fract24a_i, + input snana_i, + input qnana_i, + input infa_i, + input zeroa_i, + // operand 'b' related inputs + input signb_i, + input [9:0] exp10b_i, + input [23:0] fract24b_i, + input snanb_i, + input qnanb_i, + input infb_i, + input zerob_i, + // support addsub + output addsub_agtb_o, + output addsub_aeqb_o, + // outputs + output cmp_flag_o, inv_o, inf_o, ready_o +); + +//////////////////////////////////////////////////////////////////////// +// +// Exception Logic +// + +wire qnan = qnana_i | qnanb_i; +wire snan = snana_i | snanb_i; +wire anan = qnan | snan; + + +// Comparison invalid when sNaN in on an equal comparison, +// or any NaN for any other comparison. +wire inv_cmp = (snan & (cmp_type_i == `OR1K_FPCOP_SFEQ)) | + (anan & (cmp_type_i != `OR1K_FPCOP_SFEQ)); + + +//////////////////////////////////////////////////////////////////////// +// +// Comparison Logic +// +wire exp_gt = exp10a_i > exp10b_i; +wire exp_eq = exp10a_i == exp10b_i; +wire exp_lt = (~exp_gt) & (~exp_eq); // exp10a_i < exp10b_i; + +wire fract_gt = fract24a_i > fract24b_i; +wire fract_eq = fract24a_i == fract24b_i; +wire fract_lt = (~fract_gt) & (~fract_eq); // fract24a_i < fract24b_i; + +wire all_zero = zeroa_i & zerob_i; + +reg altb, blta, aeqb; + +always @( qnan or snan or infa_i or infb_i or signa_i or signb_i or + exp_eq or exp_gt or exp_lt or + fract_eq or fract_gt or fract_lt or all_zero) + + casez( {qnan, snan, infa_i, infb_i, signa_i, signb_i, + exp_eq, exp_gt, exp_lt, + fract_eq, fract_gt, fract_lt, all_zero}) + 13'b1?_??_??_???_???_?: {blta, altb, aeqb} = 3'b000; // qnan + 13'b?1_??_??_???_???_?: {blta, altb, aeqb} = 3'b000; // snan + + 13'b00_11_00_???_???_?: {blta, altb, aeqb} = 3'b001; // both op INF comparisson + 13'b00_11_01_???_???_?: {blta, altb, aeqb} = 3'b100; + 13'b00_11_10_???_???_?: {blta, altb, aeqb} = 3'b010; + 13'b00_11_11_???_???_?: {blta, altb, aeqb} = 3'b001; + + 13'b00_10_00_???_???_?: {blta, altb, aeqb} = 3'b100; // opa_i INF comparisson + 13'b00_10_01_???_???_?: {blta, altb, aeqb} = 3'b100; + 13'b00_10_10_???_???_?: {blta, altb, aeqb} = 3'b010; + 13'b00_10_11_???_???_?: {blta, altb, aeqb} = 3'b010; + + 13'b00_01_00_???_???_?: {blta, altb, aeqb} = 3'b010; // opb_i INF comparisson + 13'b00_01_01_???_???_?: {blta, altb, aeqb} = 3'b100; + 13'b00_01_10_???_???_?: {blta, altb, aeqb} = 3'b010; + 13'b00_01_11_???_???_?: {blta, altb, aeqb} = 3'b100; + + 13'b00_00_10_???_???_0: {blta, altb, aeqb} = 3'b010; //compare base on sign + 13'b00_00_01_???_???_0: {blta, altb, aeqb} = 3'b100; //compare base on sign + + 13'b00_00_??_???_???_1: {blta, altb, aeqb} = 3'b001; //compare base on sign both are zero + + 13'b00_00_00_010_???_?: {blta, altb, aeqb} = 3'b100; // cmp exp, equal sign + 13'b00_00_00_001_???_?: {blta, altb, aeqb} = 3'b010; + 13'b00_00_11_010_???_?: {blta, altb, aeqb} = 3'b010; + 13'b00_00_11_001_???_?: {blta, altb, aeqb} = 3'b100; + + 13'b00_00_00_100_010_?: {blta, altb, aeqb} = 3'b100; // compare fractions, equal sign, equal exp + 13'b00_00_00_100_001_?: {blta, altb, aeqb} = 3'b010; + 13'b00_00_11_100_010_?: {blta, altb, aeqb} = 3'b010; + 13'b00_00_11_100_001_?: {blta, altb, aeqb} = 3'b100; + + 13'b00_00_00_100_100_?: {blta, altb, aeqb} = 3'b001; + 13'b00_00_11_100_100_?: {blta, altb, aeqb} = 3'b001; + + default: {blta, altb, aeqb} = 3'b000; + endcase + + +//////////////////////////////////////////////////////////////////////// +// Comparison cmp_flag generation +reg cmp_flag; +always @(altb or blta or aeqb or cmp_type_i) + begin + case(cmp_type_i) + `OR1K_FPCOP_SFEQ: cmp_flag = aeqb; + `OR1K_FPCOP_SFNE: cmp_flag = !aeqb; + `OR1K_FPCOP_SFGT: cmp_flag = blta & !aeqb; + `OR1K_FPCOP_SFGE: cmp_flag = blta | aeqb; + `OR1K_FPCOP_SFLT: cmp_flag = altb & !aeqb; + `OR1K_FPCOP_SFLE: cmp_flag = altb | aeqb; + default: cmp_flag = 0; + endcase // case (fpu_op_r) + end // always@ * + + +//////////////////////////////////////////////////////////////////////// +// output (latching is perfommed on FPU top level) + +assign addsub_agtb_o = exp_gt | (exp_eq & fract_gt); +assign addsub_aeqb_o = exp_eq & fract_eq; + +assign cmp_flag_o = cmp_flag; +assign inv_o = inv_cmp; +assign inf_o = infa_i | infb_i; +assign ready_o = fpu_op_is_comp_i; + +endmodule // pfpu32_fcmp diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_f2i.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_f2i.v new file mode 100644 index 0000000..3d35071 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_f2i.v @@ -0,0 +1,110 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// pfpu32_f2i //// +//// 32-bit floating point to integer converter //// +//// //// +//// Author: Andrey Bacherov //// +//// avbacherov@opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2014 Andrey Bacherov //// +//// avbacherov@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`include "mor1kx-defines.v" + +module pfpu32_f2i +( + input clk, + input rst, + input flush_i, // flush pipe + input adv_i, // advance pipe + input start_i, // start conversion + input signa_i, // input 'a' related values + input [9:0] exp10a_i, + input [23:0] fract24a_i, + input snan_i, // 'a'/'b' related + input qnan_i, + output reg f2i_rdy_o, // f2i is ready + output reg f2i_sign_o, // f2i signum + output reg [23:0] f2i_int24_o, // f2i fractional + output reg [4:0] f2i_shr_o, // f2i required shift right value + output reg [3:0] f2i_shl_o, // f2i required shift left value + output reg f2i_ovf_o, // f2i overflow flag + output reg f2i_snan_o // f2i signaling NaN output reg +); + + /* + Any stage's output is registered. + Definitions: + s??o_name - "S"tage number "??", "O"utput + s??t_name - "S"tage number "??", "T"emporary (internally) + */ + + // exponent after moving binary point at the end of mantissa + // bias is also removed + wire [9:0] s1t_exp10m = exp10a_i - 10'd150; // (- 127 - 23) + + // detect if now shift right is required + wire [9:0] s1t_shr_t = {10{s1t_exp10m[9]}} & (10'd150 - exp10a_i); + // limit right shift by 31 + wire [4:0] s1t_shr = s1t_shr_t[4:0] | {5{|s1t_shr_t[9:5]}}; + + // detect if left shift required for mantissa + // (limited by 15) + wire [3:0] s1t_shl = {4{~s1t_exp10m[9]}} & (s1t_exp10m[3:0] | {4{|s1t_exp10m[9:4]}}); + // check overflow + wire s1t_is_shl_gt8 = s1t_shl[3] & (|s1t_shl[2:0]); + wire s1t_is_shl_eq8 = s1t_shl[3] & (~(|s1t_shl[2:0])); + wire s1t_is_shl_ovf = + s1t_is_shl_gt8 | + (s1t_is_shl_eq8 & (~signa_i)) | + (s1t_is_shl_eq8 & signa_i & (|fract24a_i[22:0])); + + + // registering output + always @(posedge clk) begin + if(adv_i) begin + // input related + f2i_snan_o <= snan_i; + // computation related + f2i_sign_o <= signa_i & (!(qnan_i | snan_i)); // if 'a' is a NaN than ouput is max. positive + f2i_int24_o <= fract24a_i; + f2i_shr_o <= s1t_shr; + f2i_shl_o <= s1t_shl; + f2i_ovf_o <= s1t_is_shl_ovf; + end // (reset or flush) / advance + end // posedge clock + + // ready is special case + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + f2i_rdy_o <= 1'b0; + else if(flush_i) + f2i_rdy_o <= 1'b0; + else if(adv_i) + f2i_rdy_o <= start_i; + end // posedge clock + +endmodule // pfpu32_f2i diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_i2f.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_i2f.v new file mode 100644 index 0000000..e284828 --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_i2f.v @@ -0,0 +1,144 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// pfpu32_i2f //// +//// 32-bit integer to floating point converter //// +//// //// +//// Author: Andrey Bacherov //// +//// avbacherov@opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2014 Andrey Bacherov //// +//// avbacherov@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`include "mor1kx-defines.v" + +module pfpu32_i2f +( + input clk, + input rst, + input flush_i, // flush pipe + input adv_i, // advance pipe + input start_i, // start conversion + input [31:0] opa_i, + output reg i2f_rdy_o, // i2f is ready + output reg i2f_sign_o, // i2f signum + output reg [3:0] i2f_shr_o, + output reg [7:0] i2f_exp8shr_o, + output reg [4:0] i2f_shl_o, + output reg [7:0] i2f_exp8shl_o, + output reg [7:0] i2f_exp8sh0_o, + output reg [31:0] i2f_fract32_o +); + + /* + Any stage's output is registered. + Definitions: + s??o_name - "S"tage number "??", "O"utput + s??t_name - "S"tage number "??", "T"emporary (internally) + */ + + // signum of input + wire s1t_signa = opa_i[31]; + // magnitude (tow's complement for negative input) + wire [31:0] s1t_fract32 = + (opa_i ^ {32{s1t_signa}}) + {31'd0,s1t_signa}; + // normalization shifts + reg [3:0] s1t_shrx; + reg [4:0] s1t_shlx; + // shift goal: + // 23 22 0 + // | | | + // h fffffffffffffffffffffff + // right shift + always @(s1t_fract32[31:24]) begin + casez(s1t_fract32[31:24]) // synopsys full_case parallel_case + 8'b1???????: s1t_shrx = 4'd8; + 8'b01??????: s1t_shrx = 4'd7; + 8'b001?????: s1t_shrx = 4'd6; + 8'b0001????: s1t_shrx = 4'd5; + 8'b00001???: s1t_shrx = 4'd4; + 8'b000001??: s1t_shrx = 4'd3; + 8'b0000001?: s1t_shrx = 4'd2; + 8'b00000001: s1t_shrx = 4'd1; + 8'b00000000: s1t_shrx = 4'd0; + endcase + end + // left shift + always @(s1t_fract32[23:0]) begin + casez(s1t_fract32[23:0]) // synopsys full_case parallel_case + 24'b1???????????????????????: s1t_shlx = 5'd0; // hidden '1' is in its plase + 24'b01??????????????????????: s1t_shlx = 5'd1; + 24'b001?????????????????????: s1t_shlx = 5'd2; + 24'b0001????????????????????: s1t_shlx = 5'd3; + 24'b00001???????????????????: s1t_shlx = 5'd4; + 24'b000001??????????????????: s1t_shlx = 5'd5; + 24'b0000001?????????????????: s1t_shlx = 5'd6; + 24'b00000001????????????????: s1t_shlx = 5'd7; + 24'b000000001???????????????: s1t_shlx = 5'd8; + 24'b0000000001??????????????: s1t_shlx = 5'd9; + 24'b00000000001?????????????: s1t_shlx = 5'd10; + 24'b000000000001????????????: s1t_shlx = 5'd11; + 24'b0000000000001???????????: s1t_shlx = 5'd12; + 24'b00000000000001??????????: s1t_shlx = 5'd13; + 24'b000000000000001?????????: s1t_shlx = 5'd14; + 24'b0000000000000001????????: s1t_shlx = 5'd15; + 24'b00000000000000001???????: s1t_shlx = 5'd16; + 24'b000000000000000001??????: s1t_shlx = 5'd17; + 24'b0000000000000000001?????: s1t_shlx = 5'd18; + 24'b00000000000000000001????: s1t_shlx = 5'd19; + 24'b000000000000000000001???: s1t_shlx = 5'd20; + 24'b0000000000000000000001??: s1t_shlx = 5'd21; + 24'b00000000000000000000001?: s1t_shlx = 5'd22; + 24'b000000000000000000000001: s1t_shlx = 5'd23; + 24'b000000000000000000000000: s1t_shlx = 5'd0; + endcase + end + + + // registering output + always @(posedge clk) begin + if(adv_i) begin + // computation related + i2f_sign_o <= s1t_signa; + i2f_shr_o <= s1t_shrx; + i2f_exp8shr_o <= 8'd150 + {4'd0,s1t_shrx}; // 150=127+23 + i2f_shl_o <= s1t_shlx; + i2f_exp8shl_o <= 8'd150 - {3'd0,s1t_shlx}; + i2f_exp8sh0_o <= {8{s1t_fract32[23]}} & 8'd150; // "1" is in [23] / zero + i2f_fract32_o <= s1t_fract32; + end // advance + end // posedge clock + + // ready is special case + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + i2f_rdy_o <= 1'b0; + else if(flush_i) + i2f_rdy_o <= 1'b0; + else if(adv_i) + i2f_rdy_o <= start_i; + end // posedge clock + +endmodule // pfpu32_i2f diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_muldiv.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_muldiv.v new file mode 100644 index 0000000..17aebac --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_muldiv.v @@ -0,0 +1,807 @@ +////////////////////////////////////////////////////////////////////// +// // +// pfpu32_muldiv // +// // +// This file is part of the mor1kx project // +// https://github.com/openrisc/mor1kx // +// // +// Description // +// combined multiplier/divisor pipeline for // +// single precision floating point numbers // +// // +// Author(s): // +// Andrey Bacherov, avbacherov@opencores.org // +// // +////////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2015 // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // +// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // +// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // +// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // +// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // +// POSSIBILITY OF SUCH DAMAGE. // +////////////////////////////////////////////////////////////////////// + +`include "mor1kx-defines.v" + +module pfpu32_muldiv +( + input clk, + input rst, + input flush_i, // flushe pipe + input adv_i, // advance pipe + input start_i, // start + input is_div_i, // 1: division, 0: multiplication + // input 'a' related values + input signa_i, + input [9:0] exp10a_i, + input [23:0] fract24a_i, + input infa_i, + input zeroa_i, + // input 'b' related values + input signb_i, + input [9:0] exp10b_i, + input [23:0] fract24b_i, + input infb_i, + input zerob_i, + // 'a'/'b' related + input snan_i, + input qnan_i, + input anan_sign_i, + // MUL/DIV common outputs + output reg muldiv_rdy_o, // ready + output reg muldiv_sign_o, // signum + output reg [4:0] muldiv_shr_o, // do right shift in align stage + output reg [9:0] muldiv_exp10shr_o, // exponent for right shift align + output reg muldiv_shl_o, // do left shift in align stage + output reg [9:0] muldiv_exp10shl_o, // exponent for left shift align + output reg [9:0] muldiv_exp10sh0_o, // exponent for no shift in align + output reg [27:0] muldiv_fract28_o, // fractional with appended {r,s} bits + output reg muldiv_inv_o, // invalid operation flag + output reg muldiv_inf_o, // infinity output reg + output reg muldiv_snan_o, // signaling NaN output reg + output reg muldiv_qnan_o, // quiet NaN output reg + output reg muldiv_anan_sign_o, // signum for output nan + // DIV additional outputs + output reg div_op_o, // operation is division + output reg div_sign_rmnd_o, // signum of reminder for IEEE compliant rounding + output reg div_dbz_o // div division by zero flag +); + + /* + !!! If an input is denormalized the additional 1-clk stage + !!! (for normalization) is executed. + !!! But inputs must not change during the stage. + + Any stage's output is registered. + Definitions: + s??o_name - "S"tage number "??", "O"utput + s??t_name - "S"tage number "??", "T"emporary (internally) + */ + + + /* Stage #1: pre-operation stage */ + + + // detection of some exceptions + wire s0t_inv = is_div_i ? ((zeroa_i & zerob_i) | (infa_i & infb_i)) : // div: 0/0, inf/inf -> invalid operation; snan output + ((zeroa_i & infb_i) | (zerob_i & infa_i)); // mul: 0 * inf -> invalid operation; snan output + // division by zero + wire s0t_dbz = is_div_i & (~zeroa_i) & (~infa_i) & zerob_i; + // inf input + wire s0t_inf_i = infa_i | (infb_i & (~is_div_i)); // for DIV only infA is used + + // force intermediate results to zero + wire s0t_opc_0 = zeroa_i | zerob_i | (is_div_i & (infa_i | infb_i)); + + // count leading zeros + reg [4:0] s0t_nlza; + always @(fract24a_i) begin + casez(fract24a_i) // synopsys full_case parallel_case + 24'b1???????????????????????: s0t_nlza = 0; + 24'b01??????????????????????: s0t_nlza = 1; + 24'b001?????????????????????: s0t_nlza = 2; + 24'b0001????????????????????: s0t_nlza = 3; + 24'b00001???????????????????: s0t_nlza = 4; + 24'b000001??????????????????: s0t_nlza = 5; + 24'b0000001?????????????????: s0t_nlza = 6; + 24'b00000001????????????????: s0t_nlza = 7; + 24'b000000001???????????????: s0t_nlza = 8; + 24'b0000000001??????????????: s0t_nlza = 9; + 24'b00000000001?????????????: s0t_nlza = 10; + 24'b000000000001????????????: s0t_nlza = 11; + 24'b0000000000001???????????: s0t_nlza = 12; + 24'b00000000000001??????????: s0t_nlza = 13; + 24'b000000000000001?????????: s0t_nlza = 14; + 24'b0000000000000001????????: s0t_nlza = 15; + 24'b00000000000000001???????: s0t_nlza = 16; + 24'b000000000000000001??????: s0t_nlza = 17; + 24'b0000000000000000001?????: s0t_nlza = 18; + 24'b00000000000000000001????: s0t_nlza = 19; + 24'b000000000000000000001???: s0t_nlza = 20; + 24'b0000000000000000000001??: s0t_nlza = 21; + 24'b00000000000000000000001?: s0t_nlza = 22; + 24'b000000000000000000000001: s0t_nlza = 23; + 24'b000000000000000000000000: s0t_nlza = 0; // zero rezult + endcase + end // nlz for 'a' + + // count leading zeros + reg [4:0] s0t_nlzb; + always @(fract24b_i) begin + casez(fract24b_i) // synopsys full_case parallel_case + 24'b1???????????????????????: s0t_nlzb = 0; + 24'b01??????????????????????: s0t_nlzb = 1; + 24'b001?????????????????????: s0t_nlzb = 2; + 24'b0001????????????????????: s0t_nlzb = 3; + 24'b00001???????????????????: s0t_nlzb = 4; + 24'b000001??????????????????: s0t_nlzb = 5; + 24'b0000001?????????????????: s0t_nlzb = 6; + 24'b00000001????????????????: s0t_nlzb = 7; + 24'b000000001???????????????: s0t_nlzb = 8; + 24'b0000000001??????????????: s0t_nlzb = 9; + 24'b00000000001?????????????: s0t_nlzb = 10; + 24'b000000000001????????????: s0t_nlzb = 11; + 24'b0000000000001???????????: s0t_nlzb = 12; + 24'b00000000000001??????????: s0t_nlzb = 13; + 24'b000000000000001?????????: s0t_nlzb = 14; + 24'b0000000000000001????????: s0t_nlzb = 15; + 24'b00000000000000001???????: s0t_nlzb = 16; + 24'b000000000000000001??????: s0t_nlzb = 17; + 24'b0000000000000000001?????: s0t_nlzb = 18; + 24'b00000000000000000001????: s0t_nlzb = 19; + 24'b000000000000000000001???: s0t_nlzb = 20; + 24'b0000000000000000000001??: s0t_nlzb = 21; + 24'b00000000000000000000001?: s0t_nlzb = 22; + 24'b000000000000000000000001: s0t_nlzb = 23; + 24'b000000000000000000000000: s0t_nlzb = 0; // zero result + endcase + end // nlz of 'b' + + + // pre-norm stage outputs + // input related + reg s0o_inv, s0o_inf_i, + s0o_snan_i, s0o_qnan_i, s0o_anan_i_sign; + // computation related + reg s0o_is_div; + reg s0o_opc_0; + reg s0o_signc; + reg [9:0] s0o_exp10a; + reg [23:0] s0o_fract24a; + reg [4:0] s0o_shla; + reg [9:0] s0o_exp10b; + reg [23:0] s0o_fract24b; + reg [4:0] s0o_shlb; + // DIV additional outputs + reg s0o_dbz; + // registering + always @(posedge clk) begin + if(adv_i) begin + // input related + s0o_inv <= s0t_inv; + s0o_inf_i <= s0t_inf_i; + s0o_snan_i <= snan_i; + s0o_qnan_i <= qnan_i; + s0o_anan_i_sign <= anan_sign_i; + // computation related + s0o_is_div <= is_div_i; + s0o_opc_0 <= s0t_opc_0; + s0o_signc <= signa_i ^ signb_i; + s0o_exp10a <= exp10a_i; + s0o_fract24a <= fract24a_i; + s0o_shla <= s0t_nlza; + s0o_exp10b <= exp10b_i; + s0o_fract24b <= fract24b_i; + s0o_shlb <= s0t_nlzb; + // DIV additional outputs + s0o_dbz <= s0t_dbz; + end // push pipe + end + + // route ready through side back + reg s0o_ready; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + s0o_ready <= 0; + else if(flush_i) + s0o_ready <= 0; + else if(adv_i) + s0o_ready <= start_i; + end // posedge clock + + + // left-shift the dividend and divisor + wire [23:0] s1t_fract24a_shl = s0o_fract24a << s0o_shla; + wire [23:0] s1t_fract24b_shl = s0o_fract24b << s0o_shlb; + + // force result to zero + wire [23:0] s1t_fract24a = s1t_fract24a_shl & {24{~s0o_opc_0}}; + wire [23:0] s1t_fract24b = s1t_fract24b_shl & {24{~s0o_opc_0}}; + + // exponent + wire [9:0] s1t_exp10mux = + s0o_is_div ? (s0o_exp10a - {5'd0,s0o_shla} - s0o_exp10b + {5'd0,s0o_shlb} + 10'd127) : + (s0o_exp10a - {5'd0,s0o_shla} + s0o_exp10b - {5'd0,s0o_shlb} - 10'd127); + + // force result to zero + wire [9:0] s1t_exp10c = s1t_exp10mux & {10{~s0o_opc_0}}; + + + // Goldshmidt division iterations control + reg [10:0] itr_state; // iteration state indicator + // iteration characteristic points: + // quotient is computed + wire itr_rndQ = itr_state[10]; + // iteration control state machine + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + itr_state <= 11'd0; + else if(flush_i) + itr_state <= 11'd0; + else if(adv_i & s0o_ready & s0o_is_div) + itr_state <= 11'd1; + else if(adv_i) + itr_state <= {itr_state[9:0],1'b0}; + end // posedge clock + + // Multiplication operation flag + wire s1t_is_mul = s0o_ready & (~s0o_is_div); + + + // stage #1 outputs + // input related + reg s1o_inv, s1o_inf_i, + s1o_snan_i, s1o_qnan_i, s1o_anan_i_sign; + // computation related + reg s1o_opc_0; + reg s1o_signc; + reg [9:0] s1o_exp10c; + reg [23:0] s1o_fract24a; + reg [23:0] s1o_fract24b; + // DIV additional outputs + reg s1o_dbz; + // registering + always @(posedge clk) begin + if(adv_i) begin + // input related + s1o_inv <= s0o_inv; + s1o_inf_i <= s0o_inf_i; + s1o_snan_i <= s0o_snan_i; + s1o_qnan_i <= s0o_qnan_i; + s1o_anan_i_sign <= s0o_anan_i_sign; + // computation related + s1o_opc_0 <= s0o_opc_0; + s1o_signc <= s0o_signc; + s1o_exp10c <= s1t_exp10c; + s1o_fract24a <= s1t_fract24a; + s1o_fract24b <= s1t_fract24b; + // DIV additional outputs + s1o_dbz <= s0o_dbz; + end // advance pipe + end // posedge clock + + // ready is special case + reg s1o_mul_ready; + reg s1o_div_ready; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + s1o_mul_ready <= 1'b0; + s1o_div_ready <= 1'b0; + end else if(flush_i) begin + s1o_mul_ready <= 1'b0; + s1o_div_ready <= 1'b0; + end else if(adv_i) begin + s1o_mul_ready <= s1t_is_mul; + s1o_div_ready <= itr_rndQ; + end + end // posedge clock + + + /* Stage #2: 1st part of multiplier */ + + + // rigt shift value + // and appropriatelly corrected exponent + wire s1o_exp10c_0 = ~(|s1o_exp10c); + wire [9:0] s2t_shr_of_neg_exp = 11'h401 - {1'b0,s1o_exp10c}; // 1024-v+1 + // variants: + wire [9:0] s2t_shr_t; + wire [9:0] s2t_exp10rx; + assign {s2t_shr_t,s2t_exp10rx} = + // force zero result + s1o_opc_0 ? {10'd0,10'd0} : + // negative exponent sum + // (!) takes 1x.xx case into account automatically + s1o_exp10c[9] ? {s2t_shr_of_neg_exp,10'd1} : + // (a) zero exponent sum (denorm. result potentially) + // (!) takes 1x.xx case into account automatically + // (b) normal case + // (!) 1x.xx case is processed in next stage + {{9'd0,s1o_exp10c_0},(s1o_exp10c | {9'd0,s1o_exp10c_0})}; + // limited by 31 and forced result to zero + wire [4:0] s2t_shrx = s2t_shr_t[4:0] | {5{|s2t_shr_t[9:5]}}; + + + // Support Goldshmidt iteration + // initial estimation of reciprocal + wire [8:0] itr_recip9b; + arecip_lut u_arlut + ( + .b_i(s1o_fract24b[22:16]), + .r_o(itr_recip9b) + ); + // support case: b==1 + wire b_eq_1 = s1o_fract24b[23] & (~(|s1o_fract24b[22:0])); + // reciprocal with restored leading 01 + wire [10:0] itr_recip11b = b_eq_1 ? 11'b10000000000 : + {2'b01,itr_recip9b}; + + // the subsequent two stages multiplier operates with 32-bit inputs + // 25-bits: fractionals (quotient is in range 0.5 to 1) + // 1-bit : rounding bit + // 6-bits: guard (due to truncations of intermediate results) + + // intermediate results: + // updated divisor (D) is rounded up while all other intermediate values + // are just truncated in according with directed rounding analysed in: + // Guy Even, Peter-M.Seidel, Warren E.Ferguson + // "A parametric error analysis of Goldschmidt’s division algorithm" + wire itr_rndD = itr_state[3] | itr_state[6]; + wire itr_rndDvsr; + // align resulting quotient to support subsequent IEEE-compliant rounding + wire [25:0] itr_res_qtnt26; // rounded quotient + // Updated quotient or divisor + wire [32:0] itr_qtnt33; + // 'F' (2-D) or 'Reminder' + wire [32:0] itr_rmnd33; + + + // control for multiplier's input 'A' + // the register also contains quotient to output + wire itr_uinA = s1t_is_mul | + itr_state[0] | itr_state[3] | + itr_state[6] | itr_rndQ; + // multiplexer for multiplier's input 'A' + wire [31:0] itr_mul32a = + s1t_is_mul ? {s1t_fract24a,8'd0} : + itr_state[0] ? {itr_recip11b,21'd0} : + itr_rndQ ? {itr_res_qtnt26,6'd0} : // truncate by 2^(-n-1) + itr_rmnd33[31:0]; + // register of multiplier's input 'A' + reg [15:0] s1o_mul16_al; + reg [15:0] s1o_mul16_ah; + // registering + always @(posedge clk) begin + if(adv_i & itr_uinA) begin + s1o_mul16_al <= itr_mul32a[15: 0]; + s1o_mul16_ah <= itr_mul32a[31:16]; + end + end // posedge clock + + + // control for multiplier's input 'B' + wire itr_uinB = s1t_is_mul | + itr_state[0] | itr_state[1] | + itr_state[3] | itr_state[4] | + itr_state[6] | itr_state[7] | + itr_rndQ; + // multiplexer for multiplier's input 'B' + wire [31:0] itr_mul32b = + s1t_is_mul ? {s1t_fract24b,8'd0} : + (itr_state[0] | itr_rndQ) ? {s1o_fract24b,8'd0} : + itr_state[1] ? {s1o_fract24a,8'd0} : + itr_qtnt33[31:0]; + // register of multiplier's input 'B' + reg [15:0] s1o_mul16_bl; + reg [15:0] s1o_mul16_bh; + always @(posedge clk) begin + if(adv_i & itr_uinB) begin + s1o_mul16_bl <= itr_mul32b[15: 0]; + s1o_mul16_bh <= itr_mul32b[31:16]; + end + end // posedge clock + + // stage #2 outputs + // input related + reg s2o_inv, s2o_inf_i, + s2o_snan_i, s2o_qnan_i, s2o_anan_i_sign; + // DIV additional outputs + reg s2o_dbz; + reg [23:0] s2o_fract24a; + // computation related + reg s2o_opc_0; + reg s2o_signc; + reg [9:0] s2o_exp10c; + reg [4:0] s2o_shrx; + reg s2o_is_shrx; + reg [9:0] s2o_exp10rx; + // multipliers + reg [31:0] s2o_fract32_albl; + reg [31:0] s2o_fract32_albh; + reg [31:0] s2o_fract32_ahbl; + reg [31:0] s2o_fract32_ahbh; + // registering + always @(posedge clk) begin + if(adv_i) begin + // input related + s2o_inv <= s1o_inv; + s2o_inf_i <= s1o_inf_i; + s2o_snan_i <= s1o_snan_i; + s2o_qnan_i <= s1o_qnan_i; + s2o_anan_i_sign <= s1o_anan_i_sign; + // DIV additional outputs + s2o_dbz <= s1o_dbz; + s2o_fract24a <= s1o_fract24a; + // computation related + s2o_opc_0 <= s1o_opc_0; + s2o_signc <= s1o_signc; + s2o_exp10c <= s1o_exp10c; + s2o_shrx <= s2t_shrx; + s2o_is_shrx <= (|s2t_shrx); + s2o_exp10rx <= s2t_exp10rx; + // multipliers + s2o_fract32_albl <= s1o_mul16_al * s1o_mul16_bl; + s2o_fract32_albh <= s1o_mul16_al * s1o_mul16_bh; + s2o_fract32_ahbl <= s1o_mul16_ah * s1o_mul16_bl; + s2o_fract32_ahbh <= s1o_mul16_ah * s1o_mul16_bh; + end // advance pipe + end // posedge clock + + // ready is special case + reg s2o_mul_ready; + reg s2o_div_ready; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + s2o_mul_ready <= 1'b0; + s2o_div_ready <= 1'b0; + end else if(flush_i) begin + s2o_mul_ready <= 1'b0; + s2o_div_ready <= 1'b0; + end else if(adv_i) begin + s2o_mul_ready <= s1o_mul_ready; + s2o_div_ready <= s1o_div_ready; + end + end // posedge clock + + + /* Stage #3: 2nd part of multiplier */ + + + // 2nd stage of multiplier + wire [47:0] s3t_fract48; + assign s3t_fract48 = {s2o_fract32_ahbh, 16'd0} + + {16'd0, s2o_fract32_ahbl} + + {16'd0, s2o_fract32_albh} + + {32'd0, s2o_fract32_albl[31:16]}; + + // stage #3 outputs (for division support) + + // full product + reg [32:0] s3o_mul33o; // output + reg s3o_mul33s; // sticky + // registering + always @(posedge clk) begin + if(adv_i) begin + s3o_mul33o <= s3t_fract48[47:15]; + s3o_mul33s <= (|s3t_fract48[14:0]) | (|s2o_fract32_albl[15:0]); + end + end // posedge clock + + // For pipelinization of division final stage + // input related + reg s3o_inv, s3o_inf_i, + s3o_snan_i, s3o_qnan_i, s3o_anan_i_sign; + // DIV computation related + reg s3o_dbz; + reg [23:0] s3o_fract24a; + reg s3o_opc_0; + reg s3o_signc; + reg [9:0] s3o_exp10c; + reg [4:0] s3o_shrx; + reg s3o_is_shrx; + reg [9:0] s3o_exp10rx; + // registering + always @(posedge clk) begin + if(adv_i) begin + // input related + s3o_inv <= s2o_inv; + s3o_inf_i <= s2o_inf_i; + s3o_snan_i <= s2o_snan_i; + s3o_qnan_i <= s2o_qnan_i; + s3o_anan_i_sign <= s2o_anan_i_sign; + // DIV computation related + s3o_dbz <= s2o_dbz; + s3o_fract24a <= s2o_fract24a; + s3o_opc_0 <= s2o_opc_0; + s3o_signc <= s2o_signc; + s3o_exp10c <= s2o_exp10c; + s3o_shrx <= s2o_shrx; + s3o_is_shrx <= s2o_is_shrx; + s3o_exp10rx <= s2o_exp10rx; + end // advance pipe + end // @clock + + // stage 3 ready makes sense for division only + reg s3o_div_ready; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + s3o_div_ready <= 1'b0; + else if(flush_i) + s3o_div_ready <= 1'b0; + else if(adv_i) + s3o_div_ready <= s2o_div_ready; + end // posedge clock + + + // Feedback from multiplier's output with various rounding tecqs. + // +2^(-n-2) in case of rounding 1.xxx qutient + wire itr_rndQ1xx = s3o_mul33o[31]; + // +2^(-n-2) in case of rounding 0.1xx qutient + wire itr_rndQ01x = (~s3o_mul33o[31]); + // rounding mask: + wire [32:0] itr_rndM33 = // bits [6],[5] ... [0] + { 26'd0,(itr_rndQ & itr_rndQ1xx),(itr_rndQ & itr_rndQ01x), // round resulting quotient + 4'd0,(itr_rndD & s3o_mul33s) }; // round intermediate divisor + // rounding + assign itr_qtnt33 = s3o_mul33o + itr_rndM33; + + + // compute 2's complement or reminder (for sticky bit detection) + // binary point position is located just after bit [30] + wire [32:0] itr_AorT33 = + s3o_div_ready ? {1'b0,s3o_fract24a,8'd0} : // for reminder + {32'h80000000,1'b0}; // for two's complement + + // 'Reminder' / Two's complement + assign itr_rmnd33 = itr_AorT33 - itr_qtnt33; + + // Auxiliary flags: + // - truncated reminder isn't zero + wire s4t_rmnd33_n0 = |itr_rmnd33; + // - rounded quotient is exact + wire s4t_qtnt_exact = ~(s4t_rmnd33_n0 | s3o_mul33s); + // - signum of final reminder + wire s4t_sign_rmnd = itr_rmnd33[32] | ((~s4t_rmnd33_n0) & s3o_mul33s); + + + // Additionally store 26-bit of non-rounded (_raw_) and rounded (_res_) quotients. + // It is used for rounding in cases of denormalized result. + // Stiky bit is forced to be zero. + // The value are marked by stage #2 output + // raw + reg [25:0] s3o_raw_qtnt26; + // rounded + reg [25:0] s3o_res_qtnt26; + assign itr_res_qtnt26 = {itr_qtnt33[31:7],itr_qtnt33[6] & itr_rndQ01x}; + // latching + always @(posedge clk ) begin + if(itr_rndQ) begin + s3o_raw_qtnt26 <= s3o_mul33o[31:6]; + s3o_res_qtnt26 <= itr_res_qtnt26; + end + end + + // Possible left shift computation. + // In fact, as the dividend and divisor was normalized + // and the result is non-zero + // the '1' is maximum number of leading zeros in the quotient. + wire s4t_nlz = ~s3o_res_qtnt26[25]; + wire [9:0] s4t_exp10_m1 = s3o_exp10c - 10'd1; + // left shift flag and corrected exponent + wire s4t_shlx; + wire [9:0] s4t_exp10lx; + assign {s4t_shlx,s4t_exp10lx} = + // shift isn't needed (includes zero result) + (~s4t_nlz) ? {1'b0,s3o_exp10c} : + // normalization is possible + (s3o_exp10c > 10'd1) ? {1'b1,s4t_exp10_m1} : + // denormalized and zero cases + {1'b0,{9'd0,~s3o_opc_0}}; + + // check if quotient is denormalized + wire s4t_denorm = s3o_is_shrx | + ((~s3o_is_shrx) & (~s4t_shlx) & s4t_nlz); + // Select quotient for subsequent align and rounding + // The rounded (_res_) quotient is used: + // - for normalized result + // - exact result + // - non-exact but lesser than infinity precision result + wire [25:0] s4t_qtnt26 = + ( (~s4t_denorm) | s4t_qtnt_exact | + ((~s4t_qtnt_exact) & (~s4t_sign_rmnd)) ) ? s3o_res_qtnt26 : + s3o_raw_qtnt26; + + + // output + always @(posedge clk) begin + if(adv_i) begin + // input related + muldiv_inv_o <= s3o_div_ready ? s3o_inv : s2o_inv; + muldiv_inf_o <= s3o_div_ready ? s3o_inf_i : s2o_inf_i; + muldiv_snan_o <= s3o_div_ready ? s3o_snan_i : s2o_snan_i; + muldiv_qnan_o <= s3o_div_ready ? s3o_qnan_i : s2o_qnan_i; + muldiv_anan_sign_o <= s3o_div_ready ? s3o_anan_i_sign : s2o_anan_i_sign; + // computation related + muldiv_sign_o <= s3o_div_ready ? s3o_signc : s2o_signc; + muldiv_shr_o <= s3o_div_ready ? s3o_shrx : s2o_shrx; + muldiv_exp10shr_o <= s3o_div_ready ? s3o_exp10rx : s2o_exp10rx; + muldiv_shl_o <= s3o_div_ready & s4t_shlx; // makes sense for DIV only + muldiv_exp10shl_o <= {10{s3o_div_ready}} & s4t_exp10lx; // makes sense for DIV only + muldiv_exp10sh0_o <= s3o_div_ready ? s3o_exp10c : s2o_exp10c; + muldiv_fract28_o <= s3o_div_ready ? + {1'b0,s4t_qtnt26,~s4t_qtnt_exact} : // quotient + {s3t_fract48[47:21],|s3t_fract48[20:0]}; // product + // DIV additional outputs + div_op_o <= s3o_div_ready; + div_sign_rmnd_o <= s3o_div_ready & s4t_sign_rmnd; + div_dbz_o <= s3o_div_ready & s3o_dbz; + end // advance pipe + end // posedge clock + + // ready is special case + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + muldiv_rdy_o <= 0; + else if(flush_i) + muldiv_rdy_o <= 0; + else if(adv_i) + muldiv_rdy_o <= s2o_mul_ready | s3o_div_ready; + end // posedge clock + +endmodule // pfpu32_muldiv + + +// initial reciprocal approximation +module arecip_lut +( + input [6:0] b_i, + output reg [8:0] r_o +); + always @(b_i) begin + case(b_i) // synopsys full_case parallel_case + 7'd0 : r_o = 9'd508; + 7'd1 : r_o = 9'd500; + 7'd2 : r_o = 9'd492; + 7'd3 : r_o = 9'd485; + 7'd4 : r_o = 9'd477; + 7'd5 : r_o = 9'd470; + 7'd6 : r_o = 9'd463; + 7'd7 : r_o = 9'd455; + 7'd8 : r_o = 9'd448; + 7'd9 : r_o = 9'd441; + 7'd10 : r_o = 9'd434; + 7'd11 : r_o = 9'd428; + 7'd12 : r_o = 9'd421; + 7'd13 : r_o = 9'd414; + 7'd14 : r_o = 9'd408; + 7'd15 : r_o = 9'd401; + 7'd16 : r_o = 9'd395; + 7'd17 : r_o = 9'd389; + 7'd18 : r_o = 9'd383; + 7'd19 : r_o = 9'd377; + 7'd20 : r_o = 9'd371; + 7'd21 : r_o = 9'd365; + 7'd22 : r_o = 9'd359; + 7'd23 : r_o = 9'd353; + 7'd24 : r_o = 9'd347; + 7'd25 : r_o = 9'd342; + 7'd26 : r_o = 9'd336; + 7'd27 : r_o = 9'd331; + 7'd28 : r_o = 9'd326; + 7'd29 : r_o = 9'd320; + 7'd30 : r_o = 9'd315; + 7'd31 : r_o = 9'd310; + 7'd32 : r_o = 9'd305; + 7'd33 : r_o = 9'd300; + 7'd34 : r_o = 9'd295; + 7'd35 : r_o = 9'd290; + 7'd36 : r_o = 9'd285; + 7'd37 : r_o = 9'd280; + 7'd38 : r_o = 9'd275; + 7'd39 : r_o = 9'd271; + 7'd40 : r_o = 9'd266; + 7'd41 : r_o = 9'd261; + 7'd42 : r_o = 9'd257; + 7'd43 : r_o = 9'd252; + 7'd44 : r_o = 9'd248; + 7'd45 : r_o = 9'd243; + 7'd46 : r_o = 9'd239; + 7'd47 : r_o = 9'd235; + 7'd48 : r_o = 9'd231; + 7'd49 : r_o = 9'd226; + 7'd50 : r_o = 9'd222; + 7'd51 : r_o = 9'd218; + 7'd52 : r_o = 9'd214; + 7'd53 : r_o = 9'd210; + 7'd54 : r_o = 9'd206; + 7'd55 : r_o = 9'd202; + 7'd56 : r_o = 9'd198; + 7'd57 : r_o = 9'd195; + 7'd58 : r_o = 9'd191; + 7'd59 : r_o = 9'd187; + 7'd60 : r_o = 9'd183; + 7'd61 : r_o = 9'd180; + 7'd62 : r_o = 9'd176; + 7'd63 : r_o = 9'd172; + 7'd64 : r_o = 9'd169; + 7'd65 : r_o = 9'd165; + 7'd66 : r_o = 9'd162; + 7'd67 : r_o = 9'd158; + 7'd68 : r_o = 9'd155; + 7'd69 : r_o = 9'd152; + 7'd70 : r_o = 9'd148; + 7'd71 : r_o = 9'd145; + 7'd72 : r_o = 9'd142; + 7'd73 : r_o = 9'd138; + 7'd74 : r_o = 9'd135; + 7'd75 : r_o = 9'd132; + 7'd76 : r_o = 9'd129; + 7'd77 : r_o = 9'd126; + 7'd78 : r_o = 9'd123; + 7'd79 : r_o = 9'd120; + 7'd80 : r_o = 9'd117; + 7'd81 : r_o = 9'd114; + 7'd82 : r_o = 9'd111; + 7'd83 : r_o = 9'd108; + 7'd84 : r_o = 9'd105; + 7'd85 : r_o = 9'd102; + 7'd86 : r_o = 9'd99; + 7'd87 : r_o = 9'd96; + 7'd88 : r_o = 9'd93; + 7'd89 : r_o = 9'd91; + 7'd90 : r_o = 9'd88; + 7'd91 : r_o = 9'd85; + 7'd92 : r_o = 9'd82; + 7'd93 : r_o = 9'd80; + 7'd94 : r_o = 9'd77; + 7'd95 : r_o = 9'd74; + 7'd96 : r_o = 9'd72; + 7'd97 : r_o = 9'd69; + 7'd98 : r_o = 9'd67; + 7'd99 : r_o = 9'd64; + 7'd100 : r_o = 9'd62; + 7'd101 : r_o = 9'd59; + 7'd102 : r_o = 9'd57; + 7'd103 : r_o = 9'd54; + 7'd104 : r_o = 9'd52; + 7'd105 : r_o = 9'd49; + 7'd106 : r_o = 9'd47; + 7'd107 : r_o = 9'd45; + 7'd108 : r_o = 9'd42; + 7'd109 : r_o = 9'd40; + 7'd110 : r_o = 9'd38; + 7'd111 : r_o = 9'd35; + 7'd112 : r_o = 9'd33; + 7'd113 : r_o = 9'd31; + 7'd114 : r_o = 9'd29; + 7'd115 : r_o = 9'd26; + 7'd116 : r_o = 9'd24; + 7'd117 : r_o = 9'd22; + 7'd118 : r_o = 9'd20; + 7'd119 : r_o = 9'd18; + 7'd120 : r_o = 9'd15; + 7'd121 : r_o = 9'd13; + 7'd122 : r_o = 9'd11; + 7'd123 : r_o = 9'd9; + 7'd124 : r_o = 9'd7; + 7'd125 : r_o = 9'd5; + 7'd126 : r_o = 9'd3; + default: r_o = 9'd1; + endcase // LUT for initial approximation of reciprocal + end // always +endmodule diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_rnd.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_rnd.v new file mode 100644 index 0000000..e9acd8a --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_rnd.v @@ -0,0 +1,420 @@ +///////////////////////////////////////////////////////////////////// +// // +// pfpu32_rnd // +// 32-bit common rounding module for FPU // +// // +// This file is part of the mor1kx project // +// https://github.com/openrisc/mor1kx // +// // +// Author: Andrey Bacherov // +// avbacherov@opencores.org // +// // +///////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2014 Andrey Bacherov // +// avbacherov@opencores.org // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // +// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // +// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // +// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // +// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // +// POSSIBILITY OF SUCH DAMAGE. // +// // +///////////////////////////////////////////////////////////////////// + +`include "mor1kx-defines.v" + +module pfpu32_rnd +( + // clocks, resets and other controls + input clk, + input rst, + input flush_i, // flush pipe + input adv_i, // advance pipe + input [1:0] rmode_i, // rounding mode + // input from add/sub + input add_rdy_i, // add/sub is ready + input add_sign_i, // add/sub signum + input add_sub_0_i, // flag that actual substruction is performed and result is zero + input [4:0] add_shl_i, // do left shift in align stage + input [9:0] add_exp10shl_i, // exponent for left shift align + input [9:0] add_exp10sh0_i, // exponent for no shift in align + input [27:0] add_fract28_i, // fractional with appended {r,s} bits + input add_inv_i, // add/sub invalid operation flag + input add_inf_i, // add/sub infinity input + input add_snan_i, // add/sub signaling NaN input + input add_qnan_i, // add/sub quiet NaN input + input add_anan_sign_i, // add/sub signum for output nan + // input from mul + input mul_rdy_i, // mul is ready + input mul_sign_i, // mul signum + input [4:0] mul_shr_i, // do right shift in align stage + input [9:0] mul_exp10shr_i, // exponent for right shift align + input mul_shl_i, // do left shift in align stage + input [9:0] mul_exp10shl_i, // exponent for left shift align + input [9:0] mul_exp10sh0_i, // exponent for no shift in align + input [27:0] mul_fract28_i, // fractional with appended {r,s} bits + input mul_inv_i, // mul invalid operation flag + input mul_inf_i, // mul infinity input + input mul_snan_i, // mul signaling NaN input + input mul_qnan_i, // mul quiet NaN input + input mul_anan_sign_i, // mul signum for output nan + // input from div + input div_op_i, // MUL/DIV output is division + input div_sign_rmnd_i, // signum or reminder for IEEE compliant rounding + input div_dbz_i, // division by zero flag + // input from i2f + input i2f_rdy_i, // i2f is ready + input i2f_sign_i, // i2f signum + input [3:0] i2f_shr_i, + input [7:0] i2f_exp8shr_i, + input [4:0] i2f_shl_i, + input [7:0] i2f_exp8shl_i, + input [7:0] i2f_exp8sh0_i, + input [31:0] i2f_fract32_i, + // input from f2i + input f2i_rdy_i, // f2i is ready + input f2i_sign_i, // f2i signum + input [23:0] f2i_int24_i, // f2i fractional + input [4:0] f2i_shr_i, // f2i required shift right value + input [3:0] f2i_shl_i, // f2i required shift left value + input f2i_ovf_i, // f2i overflow flag + input f2i_snan_i, // f2i signaling NaN input + // input from cmp + input cmp_rdy_i, // cmp is ready + input cmp_res_i, // cmp result + input cmp_inv_i, // cmp invalid flag + input cmp_inf_i, // cmp infinity flag + // outputs + // arithmetic part's outputs + output reg [31:0] fpu_result_o, + output reg fpu_arith_valid_o, + // comparator's outputs + output reg fpu_cmp_flag_o, + output reg fpu_cmp_valid_o, + // common output + output reg [`OR1K_FPCSR_WIDTH-1:0] fpcsr_o +); + + localparam INF = 31'b1111111100000000000000000000000; + localparam QNAN = 31'b1111111110000000000000000000000; + localparam SNAN = 31'b1111111101111111111111111111111; + + // rounding mode isn't require pipelinization + wire rm_nearest = (rmode_i==2'b00); + wire rm_to_zero = (rmode_i==2'b01); + wire rm_to_infp = (rmode_i==2'b10); + wire rm_to_infm = (rmode_i==2'b11); + + /* + Any stage's output is registered. + Definitions: + s??o_name - "S"tage number "??", "O"utput + s??t_name - "S"tage number "??", "T"emporary (internally) + */ + + /* Stage #1: common align */ + + wire s1t_sign; + wire [34:0] s1t_fract35; + wire s1t_inv; + wire s1t_inf; + wire s1t_snan; + wire s1t_qnan; + wire s1t_anan_sign; + wire [4:0] s1t_shr; + wire [4:0] s1t_shl; + + // multiplexer for signums and flags + wire s1t_add_sign = add_sub_0_i ? rm_to_infm : add_sign_i; + + assign {s1t_sign,s1t_inv,s1t_inf,s1t_snan,s1t_qnan,s1t_anan_sign} = + ({6{add_rdy_i}} & {s1t_add_sign,add_inv_i,add_inf_i,add_snan_i,add_qnan_i,add_anan_sign_i}) | + ({6{mul_rdy_i}} & {mul_sign_i,mul_inv_i,mul_inf_i,mul_snan_i,mul_qnan_i,mul_anan_sign_i}) | + ({6{f2i_rdy_i}} & {f2i_sign_i,1'b0,1'b0,f2i_snan_i,1'b0,f2i_sign_i}) | + ({6{i2f_rdy_i}} & {i2f_sign_i,1'b0,1'b0,1'b0,1'b0,1'b0}); + + // multiplexer for fractionals + assign s1t_fract35 = + ({35{add_rdy_i}} & {7'd0, add_fract28_i}) | + ({35{mul_rdy_i}} & {7'd0, mul_fract28_i}) | + ({35{f2i_rdy_i}} & {8'd0, f2i_int24_i, 3'd0}) | + ({35{i2f_rdy_i}} & {i2f_fract32_i,3'd0}); + + // overflow bit for add/mul + wire s1t_addmul_carry = (add_rdy_i & add_fract28_i[27]) | + (mul_rdy_i & mul_fract28_i[27]); + + // multiplexer for shift values + wire [4:0] s1t_shr_t; + assign {s1t_shr_t, s1t_shl} = + ({10{add_rdy_i}} & {5'd0, add_shl_i}) | + ({10{mul_rdy_i}} & {mul_shr_i, {4'd0,mul_shl_i}}) | + ({10{f2i_rdy_i}} & {f2i_shr_i, {1'b0,f2i_shl_i}}) | + ({10{i2f_rdy_i}} & {{1'b0,i2f_shr_i}, i2f_shl_i}); + + assign s1t_shr = (|s1t_shr_t) ? s1t_shr_t : {4'd0,s1t_addmul_carry}; + + // align + wire [34:0] s1t_fract35sh = + (|s1t_shr) ? (s1t_fract35 >> s1t_shr) : + (s1t_fract35 << s1t_shl); + + // update sticky bit for right shift case. + // maximum right shift value is : + // 27 for mul/div + // 8 for i2f + reg s1r_sticky; + always @(s1t_fract35 or s1t_shr) begin + case (s1t_shr) + 5'd0 : s1r_sticky = |s1t_fract35[ 1:0]; + 5'd1 : s1r_sticky = |s1t_fract35[ 2:0]; + 5'd2 : s1r_sticky = |s1t_fract35[ 3:0]; + 5'd3 : s1r_sticky = |s1t_fract35[ 4:0]; + 5'd4 : s1r_sticky = |s1t_fract35[ 5:0]; + 5'd5 : s1r_sticky = |s1t_fract35[ 6:0]; + 5'd6 : s1r_sticky = |s1t_fract35[ 7:0]; + 5'd7 : s1r_sticky = |s1t_fract35[ 8:0]; + 5'd8 : s1r_sticky = |s1t_fract35[ 9:0]; + 5'd9 : s1r_sticky = |s1t_fract35[10:0]; + 5'd10 : s1r_sticky = |s1t_fract35[11:0]; + 5'd11 : s1r_sticky = |s1t_fract35[12:0]; + 5'd12 : s1r_sticky = |s1t_fract35[13:0]; + 5'd13 : s1r_sticky = |s1t_fract35[14:0]; + 5'd14 : s1r_sticky = |s1t_fract35[15:0]; + 5'd15 : s1r_sticky = |s1t_fract35[16:0]; + 5'd16 : s1r_sticky = |s1t_fract35[17:0]; + 5'd17 : s1r_sticky = |s1t_fract35[18:0]; + 5'd18 : s1r_sticky = |s1t_fract35[19:0]; + 5'd19 : s1r_sticky = |s1t_fract35[20:0]; + 5'd20 : s1r_sticky = |s1t_fract35[21:0]; + 5'd21 : s1r_sticky = |s1t_fract35[22:0]; + 5'd22 : s1r_sticky = |s1t_fract35[23:0]; + 5'd23 : s1r_sticky = |s1t_fract35[24:0]; + 5'd24 : s1r_sticky = |s1t_fract35[25:0]; + 5'd25 : s1r_sticky = |s1t_fract35[26:0]; + default: s1r_sticky = |s1t_fract35[27:0]; + endcase + end // always + + // update sticky bit for left shift case. + reg s1l_sticky; + always @(s1t_fract35 or s1t_shl) begin + case (s1t_shl) + 5'd0 : s1l_sticky = |s1t_fract35[1:0]; + 5'd1 : s1l_sticky = s1t_fract35[0]; + default: s1l_sticky = 1'b0; + endcase + end // always + + wire s1t_sticky = (|s1t_shr) ? s1r_sticky : s1l_sticky; + + // two stage multiplexer for exponents + wire [9:0] s1t_exp10shr; + wire [9:0] s1t_exp10shl; + wire [9:0] s1t_exp10sh0; + assign {s1t_exp10shr, s1t_exp10shl, s1t_exp10sh0} = + ({30{add_rdy_i}} & {add_exp10sh0_i, add_exp10shl_i, add_exp10sh0_i}) | + ({30{mul_rdy_i}} & {mul_exp10shr_i, mul_exp10shl_i, mul_exp10sh0_i}) | + ({30{f2i_rdy_i}} & {10'd0, 10'd0, 10'd0}) | + ({30{i2f_rdy_i}} & {{2'd0,i2f_exp8shr_i},{2'd0,i2f_exp8shl_i},{2'd0,i2f_exp8sh0_i}}); + + wire [9:0] s1t_exp10 = + (|s1t_shr_t) ? s1t_exp10shr : + (~(|s1t_shl)) ? (s1t_exp10sh0 + {9'd0,s1t_addmul_carry}) : + s1t_exp10shl; + + // output of align stage + reg s1o_sign; + reg [9:0] s1o_exp10; + reg [31:0] s1o_fract32; + reg [1:0] s1o_rs; + reg s1o_inv; + reg s1o_inf; + reg s1o_snan_i; + reg s1o_qnan_i; + reg s1o_anan_sign_i; + reg s1o_div_op, s1o_div_sign_rmnd, s1o_div_dbz; + reg s1o_f2i_ovf, s1o_f2i; + // registering + always @(posedge clk) begin + if(adv_i) begin + s1o_sign <= s1t_sign; + s1o_exp10 <= s1t_exp10; + s1o_fract32 <= s1t_fract35sh[34:3]; + s1o_rs <= {s1t_fract35sh[2],s1t_sticky}; + // various flags: + s1o_inv <= s1t_inv; + s1o_inf <= s1t_inf; + s1o_snan_i <= s1t_snan; + s1o_qnan_i <= s1t_qnan; + s1o_anan_sign_i <= s1t_anan_sign; + // DIV specials + s1o_div_op <= mul_rdy_i & div_op_i; + s1o_div_sign_rmnd <= div_sign_rmnd_i; + s1o_div_dbz <= div_dbz_i; + // I2F specials + s1o_f2i_ovf <= f2i_ovf_i; + s1o_f2i <= f2i_rdy_i; + end // advance + end // posedge clock + + // ready is special case + reg s1o_ready; + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + s1o_ready <= 1'b0; + else if(flush_i) + s1o_ready <= 1'b0; + else if(adv_i) + s1o_ready <= (add_rdy_i | mul_rdy_i | f2i_rdy_i | i2f_rdy_i); + end // posedge clock + + + /* Stage #2: rounding */ + + + wire s2t_dbz = s1o_div_dbz; + + wire s2t_g = s1o_fract32[0]; + wire s2t_r = s1o_rs[1]; + wire s2t_s = s1o_rs[0]; + wire s2t_lost = s2t_r | s2t_s; + + wire s2t_rnd_up = (rm_nearest & s2t_r & s2t_s) | + (rm_nearest & s2t_g & s2t_r & (~s2t_s)) | + (rm_to_infp & (~s1o_sign) & s2t_lost) | + (rm_to_infm & s1o_sign & s2t_lost); + + // IEEE compliance rounding for qutient + wire s2t_div_rnd_up = + (rm_nearest & s2t_r & s2t_s & (~s1o_div_sign_rmnd)) | + ( ((rm_to_infp & (~s1o_sign)) | (rm_to_infm & s1o_sign)) & + ((s2t_r & s2t_s) | ((~s2t_r) & s2t_s & (~s1o_div_sign_rmnd))) ); + wire s2t_div_rnd_dn = (~s2t_r) & s2t_s & s1o_div_sign_rmnd & + ( (rm_to_infp & s1o_sign) | + (rm_to_infm & (~s1o_sign)) | + rm_to_zero ); + + // set resulting direction of rounding + // a) normalized quotient is rounded by quotient related rules + // b) de-normalized quotient is rounded by common rules + wire s2t_rnd_n_qtnt = s1o_div_op & s1o_fract32[23]; // normalized quotient + wire s2t_set_rnd_up = s2t_rnd_n_qtnt ? s2t_div_rnd_up : s2t_rnd_up; + wire s2t_set_rnd_dn = s2t_rnd_n_qtnt ? s2t_div_rnd_dn : 1'b0; + + // define value for rounding adder + wire [31:0] s2t_rnd_v32 = + s2t_set_rnd_up ? 32'd1 : // +1 + s2t_set_rnd_dn ? 32'hFFFFFFFF : // -1 + 32'd0; // no rounding + // rounded fractional + wire [31:0] s2t_fract32_rnd = s1o_fract32 + s2t_rnd_v32; + + + // floating point output + wire s2t_f32_shr = s2t_fract32_rnd[24]; + // update exponent and fraction + wire [9:0] s2t_f32_exp10 = s1o_exp10 + {9'd0,s2t_f32_shr}; + wire [23:0] s2t_f32_fract24 = s2t_f32_shr ? s2t_fract32_rnd[24:1] : + s2t_fract32_rnd[23:0]; + // denormalized or zero + wire s2t_f32_fract24_dn = ~s2t_f32_fract24[23]; + + + // integer output (f2i) + wire s2t_i32_carry_rnd = s2t_fract32_rnd[31]; + wire s2t_i32_inv = ((~s1o_sign) & s2t_i32_carry_rnd) | s1o_f2i_ovf; + // two's complement for negative number + wire [31:0] s2t_i32_int32 = (s2t_fract32_rnd ^ {32{s1o_sign}}) + {31'd0,s1o_sign}; + // zero + wire s2t_i32_int32_00 = (~s2t_i32_inv) & (~(|s2t_i32_int32)); + // int32 output + wire [31:0] s2t_i32_opc; + assign s2t_i32_opc = + s2t_i32_inv ? (32'h7fffffff ^ {32{s1o_sign}}) : s2t_i32_int32; + + + // Generate result and flags + wire s2t_ine, s2t_ovf, s2t_inf, s2t_unf, s2t_zer; + wire [31:0] s2t_opc; + assign {s2t_opc,s2t_ine,s2t_ovf,s2t_inf,s2t_unf,s2t_zer} = + // f2i + s1o_f2i ? // ine ovf inf unf zer + {s2t_i32_opc,s2t_lost,1'b0,1'b0,1'b0,s2t_i32_int32_00} : + // qnan output + (s1o_snan_i | s1o_qnan_i) ? // ine ovf inf unf zer + {{s1o_anan_sign_i,QNAN}, 1'b0,1'b0,1'b0,1'b0,1'b0} : + // snan output + s1o_inv ? // ine ovf inf unf zer + {{s1o_sign,SNAN},1'b0,1'b0,1'b0,1'b0,1'b0} : + // overflow and infinity + ((s2t_f32_exp10 > 10'd254) | s1o_inf | s2t_dbz) ? // ine ovf inf unf zer + {{s1o_sign,INF},((s2t_lost | (~s1o_inf)) & (~s2t_dbz)),((~s1o_inf) & (~s2t_dbz)),1'b1,1'b0,1'b0} : + // denormalized or zero + (s2t_f32_fract24_dn) ? // ine ovf inf + {{s1o_sign,8'd0,s2t_f32_fract24[22:0]},s2t_lost,1'b0,1'b0, + // unf zer + (s2t_lost & s2t_f32_fract24_dn),~(|s2t_f32_fract24)} : + // normal result ine ovf inf unf zer + {{s1o_sign,s2t_f32_exp10[7:0],s2t_f32_fract24[22:0]},s2t_lost,1'b0,1'b0,1'b0,1'b0}; + + + // Output Register + always @(posedge clk `OR_ASYNC_RST) begin + if (rst) begin + // arithmetic results + fpu_result_o <= 32'd0; + fpu_arith_valid_o <= 1'b0; + // comparison specials + fpu_cmp_flag_o <= 1'b0; + fpu_cmp_valid_o <= 1'b0; + // exeptions + fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}}; + end + else if(flush_i) begin + // arithmetic results + fpu_result_o <= 32'd0; + fpu_arith_valid_o <= 1'b0; + // comparison specials + fpu_cmp_flag_o <= 1'b0; + fpu_cmp_valid_o <= 1'b0; + // exeptions + fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}}; + end + else if(adv_i) begin + // arithmetic results + fpu_result_o <= s2t_opc; + fpu_arith_valid_o <= s1o_ready; + // comparison specials + fpu_cmp_flag_o <= cmp_res_i; + fpu_cmp_valid_o <= cmp_rdy_i; + // exeptions + fpcsr_o[`OR1K_FPCSR_OVF] <= s2t_ovf; + fpcsr_o[`OR1K_FPCSR_UNF] <= s2t_unf; + fpcsr_o[`OR1K_FPCSR_SNF] <= s1o_inv | (s1o_snan_i & s1o_f2i); + fpcsr_o[`OR1K_FPCSR_QNF] <= s1o_qnan_i; + fpcsr_o[`OR1K_FPCSR_ZF] <= s2t_zer; + fpcsr_o[`OR1K_FPCSR_IXF] <= s2t_ine; + fpcsr_o[`OR1K_FPCSR_IVF] <= (s1o_inv | (s2t_i32_inv & s1o_f2i) | s1o_snan_i) | + (cmp_inv_i & cmp_rdy_i); + fpcsr_o[`OR1K_FPCSR_INF] <= s2t_inf | + (cmp_inf_i & cmp_rdy_i); + fpcsr_o[`OR1K_FPCSR_DZF] <= s2t_dbz; + end + end // posedge clock + +endmodule // pfpu32_rnd diff --git a/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_top.v b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_top.v new file mode 100644 index 0000000..f4b82fb --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/verilog/pfpu32/pfpu32_top.v @@ -0,0 +1,444 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// pfpu32_top //// +//// 32-bit floating point top level //// +//// //// +//// Author: Andrey Bacherov //// +//// avbacherov@opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2014 Andrey Bacherov //// +//// avbacherov@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// fpu operations: +// ========================== +// 0000 = add, +// 0001 = substract, +// 0010 = multiply, +// 0011 = divide, +// 0100 = i2f +// 0101 = f2i +// 0110 = unused (rem) +// 0111 = reserved +// 1xxx = comparison + +`include "mor1kx-defines.v" + +module pfpu32_top +#( + parameter OPTION_OPERAND_WIDTH = 32 +) +( + input clk, + input rst, + input flush_i, + input padv_decode_i, + input padv_execute_i, + input [`OR1K_FPUOP_WIDTH-1:0] op_fpu_i, + input [`OR1K_FPCSR_RM_SIZE-1:0] round_mode_i, + input [OPTION_OPERAND_WIDTH-1:0] rfa_i, + input [OPTION_OPERAND_WIDTH-1:0] rfb_i, + output [OPTION_OPERAND_WIDTH-1:0] fpu_result_o, + output fpu_arith_valid_o, + output fpu_cmp_flag_o, + output fpu_cmp_valid_o, + output [`OR1K_FPCSR_WIDTH-1:0] fpcsr_o +); + +// MSB (set by decode stage) indicates FPU instruction +// Get rid of top bit - is FPU op valid bit +wire is_op_fpu = op_fpu_i[`OR1K_FPUOP_WIDTH-1]; +wire [`OR1K_FPUOP_WIDTH-1:0] op_fpu = {1'b0,op_fpu_i[`OR1K_FPUOP_WIDTH-2:0]}; +wire [2:0] op_arith_conv = op_fpu_i[2:0]; // alias +wire a_cmp = op_fpu_i[3]; // alias for compare bit of fpu's opcode + +// advance FPU units +wire padv_fpu_units = padv_execute_i | + ((~fpu_arith_valid_o) & (~fpu_cmp_valid_o)); + +// start logic +reg new_data; +always @(posedge clk `OR_ASYNC_RST) begin + if (rst) + new_data <= 1'b0; + else if(flush_i) + new_data <= 1'b0; + else if(padv_decode_i) + new_data <= 1'b1; + else if(padv_fpu_units) + new_data <= 1'b0; +end // posedge clock + +wire new_fpu_data = new_data & is_op_fpu; + + +// analysis of input values +// split input a +wire in_signa = rfa_i[31]; +wire [7:0] in_expa = rfa_i[30:23]; +wire [22:0] in_fracta = rfa_i[22:0]; +// detect infinity a +wire in_expa_ff = &in_expa; +wire in_infa = in_expa_ff & (~(|in_fracta)); +// signaling NaN: exponent is 8hff, [22] is zero, +// rest of fract is non-zero +// quiet NaN: exponent is 8hff, [22] is 1 +wire in_snan_a = in_expa_ff & (~in_fracta[22]) & (|in_fracta[21:0]); +wire in_qnan_a = in_expa_ff & in_fracta[22]; +// denormalized/zero of a +wire in_opa_0 = ~(|rfa_i[30:0]); +wire in_opa_dn = (~(|in_expa)) & (|in_fracta); + +// split input b +wire in_signb = rfb_i[31]; +wire [7:0] in_expb = rfb_i[30:23]; +wire [22:0] in_fractb = rfb_i[22:0]; +// detect infinity b +wire in_expb_ff = &in_expb; +wire in_infb = in_expb_ff & (~(|in_fractb)); +// detect NaNs in b +wire in_snan_b = in_expb_ff & (~in_fractb[22]) & (|in_fractb[21:0]); +wire in_qnan_b = in_expb_ff & in_fractb[22]; +// denormalized/zero of a +wire in_opb_0 = ~(|rfb_i[30:0]); +wire in_opb_dn = (~(|in_expb)) & (|in_fractb); + +// detection of some exceptions +// a nan input -> qnan output +wire in_snan = in_snan_a | in_snan_b; +wire in_qnan = in_qnan_a | in_qnan_b; +// sign of output nan +wire in_anan_sign = (in_snan_a | in_qnan_a) ? in_signa : + in_signb; + +// restored exponents +wire [9:0] in_exp10a = {2'd0,in_expa[7:1],(in_expa[0] | in_opa_dn)}; +wire [9:0] in_exp10b = {2'd0,in_expb[7:1],(in_expb[0] | in_opb_dn)}; +// restored fractionals +wire [23:0] in_fract24a = {((~in_opa_dn) & (~in_opa_0)),in_fracta}; +wire [23:0] in_fract24b = {((~in_opb_dn) & (~in_opb_0)),in_fractb}; + + +// comparator +// inputs & outputs +wire op_cmp = a_cmp & + new_fpu_data; +wire addsub_agtb_o, addsub_aeqb_o; +wire cmp_result, cmp_ready, + cmp_inv, cmp_inf; +// module istance +pfpu32_fcmp u_f32_cmp +( + .fpu_op_is_comp_i(op_cmp), + .cmp_type_i(op_fpu), + // operand 'a' related inputs + .signa_i(in_signa), + .exp10a_i(in_exp10a), + .fract24a_i(in_fract24a), + .snana_i(in_snan_a), + .qnana_i(in_qnan_a), + .infa_i(in_infa), + .zeroa_i(in_opa_0), + // operand 'b' related inputs + .signb_i(in_signb), + .exp10b_i(in_exp10b), + .fract24b_i(in_fract24b), + .snanb_i(in_snan_b), + .qnanb_i(in_qnan_b), + .infb_i(in_infb), + .zerob_i(in_opb_0), + // support addsub + .addsub_agtb_o(addsub_agtb_o), + .addsub_aeqb_o(addsub_aeqb_o), + // outputs + .cmp_flag_o(cmp_result), + .inv_o(cmp_inv), + .inf_o(cmp_inf), + .ready_o(cmp_ready) +); + + +// addition / substraction +// inputs & outputs +wire the_sub = (op_arith_conv == 3'd1); +wire op_add = (~a_cmp) & ((op_arith_conv == 3'd0) | the_sub); +wire add_start = op_add & + new_fpu_data; +wire add_rdy_o; // add/sub is ready +wire add_sign_o; // add/sub signum +wire add_sub_0_o; // flag that actual substruction is performed and result is zero +wire [4:0] add_shl_o; // do left shift in align stage +wire [9:0] add_exp10shl_o; // exponent for left shift align +wire [9:0] add_exp10sh0_o; // exponent for no shift in align +wire [27:0] add_fract28_o; // fractional with appended {r,s} bits +wire add_inv_o; // add/sub invalid operation flag +wire add_inf_o; // add/sub infinity output reg +wire add_snan_o; // add/sub signaling NaN output reg +wire add_qnan_o; // add/sub quiet NaN output reg +wire add_anan_sign_o; // add/sub signum for output nan +// module istance +pfpu32_addsub u_f32_addsub +( + .clk (clk), + .rst (rst), + .flush_i (flush_i), // flushe pipe + .adv_i (padv_fpu_units), // advance pipe + .start_i (add_start), + .is_sub_i (the_sub), // 1: substruction, 0: addition + // input 'a' related values + .signa_i (in_signa), + .exp10a_i (in_exp10a), + .fract24a_i (in_fract24a), + .infa_i (in_infa), + // input 'b' related values + .signb_i (in_signb), + .exp10b_i (in_exp10b), + .fract24b_i (in_fract24b), + .infb_i (in_infb), + // 'a'/'b' related + .snan_i (in_snan), + .qnan_i (in_qnan), + .anan_sign_i (in_anan_sign), + .addsub_agtb_i (addsub_agtb_o), + .addsub_aeqb_i (addsub_aeqb_o), + // outputs + .add_rdy_o (add_rdy_o), // add/sub is ready + .add_sign_o (add_sign_o), // add/sub signum + .add_sub_0_o (add_sub_0_o), // flag that actual substruction is performed and result is zero + .add_shl_o (add_shl_o), // do left shift in align stage + .add_exp10shl_o (add_exp10shl_o), // exponent for left shift align + .add_exp10sh0_o (add_exp10sh0_o), // exponent for no shift in align + .add_fract28_o (add_fract28_o), // fractional with appended {r,s} bits + .add_inv_o (add_inv_o), // add/sub invalid operation flag + .add_inf_o (add_inf_o), // add/sub infinity output reg + .add_snan_o (add_snan_o), // add/sub signaling NaN output reg + .add_qnan_o (add_qnan_o), // add/sub quiet NaN output reg + .add_anan_sign_o (add_anan_sign_o) // add/sub signum for output nan +); + +// MUL/DIV combined pipeline +// inputs & outputs +wire op_mul = (~a_cmp) & (op_arith_conv == 3'd2); +wire op_div = (~a_cmp) & (op_arith_conv == 3'd3); +wire mul_start = (op_mul | op_div) & + new_fpu_data; +// MUL/DIV common outputs +wire mul_rdy_o; // mul is ready +wire mul_sign_o; // mul signum +wire [4:0] mul_shr_o; // do right shift in align stage +wire [9:0] mul_exp10shr_o; // exponent for right shift align +wire mul_shl_o; // do left shift in align stage +wire [9:0] mul_exp10shl_o; // exponent for left shift align +wire [9:0] mul_exp10sh0_o; // exponent for no shift in align +wire [27:0] mul_fract28_o; // fractional with appended {r,s} bits +wire mul_inv_o; // mul invalid operation flag +wire mul_inf_o; // mul infinity output reg +wire mul_snan_o; // mul signaling NaN output reg +wire mul_qnan_o; // mul quiet NaN output reg +wire mul_anan_sign_o; // mul signum for output nan +// DIV additional outputs +wire div_op_o; // operation is division +wire div_sign_rmnd_o; // signum or reminder for IEEE compliant rounding +wire div_dbz_o; // division by zero flag +// module istance +pfpu32_muldiv u_f32_muldiv +( + .clk (clk), + .rst (rst), + .flush_i (flush_i), // flushe pipe + .adv_i (padv_fpu_units), // advance pipe + .start_i (mul_start), + .is_div_i (op_div), + // input 'a' related values + .signa_i (in_signa), + .exp10a_i (in_exp10a), + .fract24a_i (in_fract24a), + .infa_i (in_infa), + .zeroa_i (in_opa_0), + // input 'b' related values + .signb_i (in_signb), + .exp10b_i (in_exp10b), + .fract24b_i (in_fract24b), + .infb_i (in_infb), + .zerob_i (in_opb_0), + // 'a'/'b' related + .snan_i (in_snan), + .qnan_i (in_qnan), + .anan_sign_i (in_anan_sign), + // MUL/DIV common outputs + .muldiv_rdy_o (mul_rdy_o), // mul is ready + .muldiv_sign_o (mul_sign_o), // mul signum + .muldiv_shr_o (mul_shr_o), // do right shift in align stage + .muldiv_exp10shr_o (mul_exp10shr_o), // exponent for right shift align + .muldiv_shl_o (mul_shl_o), // do left shift in align stage + .muldiv_exp10shl_o (mul_exp10shl_o), // exponent for left shift align + .muldiv_exp10sh0_o (mul_exp10sh0_o), // exponent for no shift in align + .muldiv_fract28_o (mul_fract28_o), // fractional with appended {r,s} bits + .muldiv_inv_o (mul_inv_o), // mul invalid operation flag + .muldiv_inf_o (mul_inf_o), // mul infinity output reg + .muldiv_snan_o (mul_snan_o), // mul signaling NaN output reg + .muldiv_qnan_o (mul_qnan_o), // mul quiet NaN output reg + .muldiv_anan_sign_o (mul_anan_sign_o), // mul signum for output nan + // DIV additional outputs + .div_op_o(div_op_o), // operation is division + .div_sign_rmnd_o(div_sign_rmnd_o), // signum of reminder for IEEE compliant rounding + .div_dbz_o(div_dbz_o) // division by zero flag +); + +// convertor +// i2f signals +wire op_i2f_cnv = (~a_cmp) & (op_arith_conv == 3'd4); +wire i2f_start = op_i2f_cnv & + new_fpu_data; +wire i2f_rdy_o; // i2f is ready +wire i2f_sign_o; // i2f signum +wire [3:0] i2f_shr_o; +wire [7:0] i2f_exp8shr_o; +wire [4:0] i2f_shl_o; +wire [7:0] i2f_exp8shl_o; +wire [7:0] i2f_exp8sh0_o; +wire [31:0] i2f_fract32_o; +// i2f module instance +pfpu32_i2f u_i2f_cnv +( + .clk (clk), + .rst (rst), + .flush_i (flush_i), // flush pipe + .adv_i (padv_fpu_units), // advance pipe + .start_i (i2f_start), // start conversion + .opa_i (rfa_i), + .i2f_rdy_o (i2f_rdy_o), // i2f is ready + .i2f_sign_o (i2f_sign_o), // i2f signum + .i2f_shr_o (i2f_shr_o), + .i2f_exp8shr_o (i2f_exp8shr_o), + .i2f_shl_o (i2f_shl_o), + .i2f_exp8shl_o (i2f_exp8shl_o), + .i2f_exp8sh0_o (i2f_exp8sh0_o), + .i2f_fract32_o (i2f_fract32_o) +); +// f2i signals +wire op_f2i_cnv = (~a_cmp) & (op_arith_conv == 3'd5); +wire f2i_start = op_f2i_cnv & + new_fpu_data; +wire f2i_rdy_o; // f2i is ready +wire f2i_sign_o; // f2i signum +wire [23:0] f2i_int24_o; // f2i fractional +wire [4:0] f2i_shr_o; // f2i required shift right value +wire [3:0] f2i_shl_o; // f2i required shift left value +wire f2i_ovf_o; // f2i overflow flag +wire f2i_snan_o; // f2i signaling NaN output reg +// f2i module instance +pfpu32_f2i u_f2i_cnv +( + .clk (clk), + .rst (rst), + .flush_i (flush_i), // flush pipe + .adv_i (padv_fpu_units), // advance pipe + .start_i (f2i_start), // start conversion + .signa_i (in_signa), // input 'a' related values + .exp10a_i (in_exp10a), + .fract24a_i (in_fract24a), + .snan_i (in_snan), // 'a'/'b' related + .qnan_i (in_qnan), + .f2i_rdy_o (f2i_rdy_o), // f2i is ready + .f2i_sign_o (f2i_sign_o), // f2i signum + .f2i_int24_o (f2i_int24_o), // f2i fractional + .f2i_shr_o (f2i_shr_o), // f2i required shift right value + .f2i_shl_o (f2i_shl_o), // f2i required shift left value + .f2i_ovf_o (f2i_ovf_o), // f2i overflow flag + .f2i_snan_o (f2i_snan_o) // f2i signaling NaN output reg +); + + +// multiplexing and rounding +pfpu32_rnd u_f32_rnd +( + // clocks, resets and other controls + .clk (clk), + .rst (rst), + .flush_i (flush_i), // flush pipe + .adv_i (padv_fpu_units), // advance pipe + .rmode_i (round_mode_i), // rounding mode + // from add/sub + .add_rdy_i (add_rdy_o), // add/sub is ready + .add_sign_i (add_sign_o), // add/sub signum + .add_sub_0_i (add_sub_0_o), // flag that actual substruction is performed and result is zero + .add_shl_i (add_shl_o), // do left shift in align stage + .add_exp10shl_i (add_exp10shl_o), // exponent for left shift align + .add_exp10sh0_i (add_exp10sh0_o), // exponent for no shift in align + .add_fract28_i (add_fract28_o), // fractional with appended {r,s} bits + .add_inv_i (add_inv_o), // add/sub invalid operation flag + .add_inf_i (add_inf_o), // add/sub infinity + .add_snan_i (add_snan_o), // add/sub signaling NaN + .add_qnan_i (add_qnan_o), // add/sub quiet NaN + .add_anan_sign_i (add_anan_sign_o), // add/sub signum for output nan + // from mul + .mul_rdy_i (mul_rdy_o), // mul is ready + .mul_sign_i (mul_sign_o), // mul signum + .mul_shr_i (mul_shr_o), // do right shift in align stage + .mul_exp10shr_i (mul_exp10shr_o), // exponent for right shift align + .mul_shl_i (mul_shl_o), // do left shift in align stage + .mul_exp10shl_i (mul_exp10shl_o), // exponent for left shift align + .mul_exp10sh0_i (mul_exp10sh0_o), // exponent for no shift in align + .mul_fract28_i (mul_fract28_o), // fractional with appended {r,s} bits + .mul_inv_i (mul_inv_o), // mul invalid operation flag + .mul_inf_i (mul_inf_o), // mul infinity + .mul_snan_i (mul_snan_o), // mul signaling NaN + .mul_qnan_i (mul_qnan_o), // mul quiet NaN + .mul_anan_sign_i (mul_anan_sign_o), // mul signum for output nan + .div_op_i (div_op_o), // MUL/DIV output is division + .div_sign_rmnd_i (div_sign_rmnd_o), // signum or reminder for IEEE compliant rounding + .div_dbz_i (div_dbz_o), // division by zero flag + // from i2f + .i2f_rdy_i (i2f_rdy_o), // i2f is ready + .i2f_sign_i (i2f_sign_o), // i2f signum + .i2f_shr_i (i2f_shr_o), + .i2f_exp8shr_i (i2f_exp8shr_o), + .i2f_shl_i (i2f_shl_o), + .i2f_exp8shl_i (i2f_exp8shl_o), + .i2f_exp8sh0_i (i2f_exp8sh0_o), + .i2f_fract32_i (i2f_fract32_o), + // from f2i + .f2i_rdy_i (f2i_rdy_o), // f2i is ready + .f2i_sign_i (f2i_sign_o), // f2i signum + .f2i_int24_i (f2i_int24_o), // f2i fractional + .f2i_shr_i (f2i_shr_o), // f2i required shift right value + .f2i_shl_i (f2i_shl_o), // f2i required shift left value + .f2i_ovf_i (f2i_ovf_o), // f2i overflow flag + .f2i_snan_i (f2i_snan_o), // f2i signaling NaN + // from cmp + .cmp_rdy_i (cmp_ready), // cmp is ready + .cmp_res_i (cmp_result), // cmp result + .cmp_inv_i (cmp_inv), // cmp invalid flag + .cmp_inf_i (cmp_inf), // cmp infinity flag + // outputs + .fpu_result_o (fpu_result_o), + .fpu_arith_valid_o (fpu_arith_valid_o), + .fpu_cmp_flag_o (fpu_cmp_flag_o), + .fpu_cmp_valid_o (fpu_cmp_valid_o), + .fpcsr_o (fpcsr_o) +); + +endmodule // pfpu32_top diff --git a/ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_pkg.vhd b/ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_pkg.vhd new file mode 100644 index 0000000..30e815a --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_pkg.vhd @@ -0,0 +1,110 @@ +library ieee; +use ieee.std_logic_1164.all; + +package mor1kx_pkg is + -- mor1kx-defines (incomplete) + constant OR1K_INSN_WIDTH : integer := 32; + + -- Top Level configs + constant OPTION_OPERAND_WIDTH : integer := 32; + + constant OPTION_CPU0 : string := "CAPPUCCINO"; + + constant FEATURE_DATACACHE : string := "NONE"; + constant OPTION_DCACHE_BLOCK_WIDTH : integer := 5; + constant OPTION_DCACHE_SET_WIDTH : integer := 9; + constant OPTION_DCACHE_WAYS : integer := 2; + constant OPTION_DCACHE_LIMIT_WIDTH : integer := 32; + constant OPTION_DCACHE_SNOOP : string := "NONE"; + constant FEATURE_DMMU : string := "NONE"; + constant FEATURE_DMMU_HW_TLB_RELOAD : string := "NONE"; + constant OPTION_DMMU_SET_WIDTH : integer := 6; + constant OPTION_DMMU_WAYS : integer := 1; + constant FEATURE_INSTRUCTIONCACHE : string := "NONE"; + constant OPTION_ICACHE_BLOCK_WIDTH : integer := 5; + constant OPTION_ICACHE_SET_WIDTH : integer := 9; + constant OPTION_ICACHE_WAYS : integer := 2; + constant OPTION_ICACHE_LIMIT_WIDTH : integer := 32; + constant FEATURE_IMMU : string := "NONE"; + constant FEATURE_IMMU_HW_TLB_RELOAD : string := "NONE"; + constant OPTION_IMMU_SET_WIDTH : integer := 6; + constant OPTION_IMMU_WAYS : integer := 1; + constant FEATURE_TIMER : string := "ENABLED"; + constant FEATURE_DEBUGUNIT : string := "NONE"; + constant FEATURE_PERFCOUNTERS : string := "NONE"; + constant FEATURE_MAC : string := "NONE"; + + constant FEATURE_SYSCALL : string := "ENABLED"; + constant FEATURE_TRAP : string := "ENABLED"; + constant FEATURE_RANGE : string := "ENABLED"; + + constant FEATURE_PIC : string := "ENABLED"; + constant OPTION_PIC_TRIGGER : string := "LEVEL"; + constant OPTION_PIC_NMI_WIDTH : integer := 0; + + constant FEATURE_DSX : string := "ENABLED"; + constant FEATURE_OVERFLOW : string := "ENABLED"; + constant FEATURE_CARRY_FLAG : string := "ENABLED"; + + constant FEATURE_FASTCONTEXTS : string := "NONE"; + constant OPTION_RF_CLEAR_ON_INIT : integer := 0; + constant OPTION_RF_NUM_SHADOW_GPR : integer := 0; + constant OPTION_RF_ADDR_WIDTH : integer := 5; + constant OPTION_RF_WORDS : integer := 32; + + --constant OPTION_RESET_PC : ???? := { { (OPTION_OPERAND_WIDTH-13){1'b0}} ; ` OR1K_RESET_VECTOR ;8'd0}; + + constant FEATURE_MULTIPLIER : string := "THREESTAGE"; + constant FEATURE_DIVIDER : string := "SERIAL"; + + constant FEATURE_ADDC : string := "ENABLED"; + constant FEATURE_SRA : string := "ENABLED"; + constant FEATURE_ROR : string := "NONE"; + constant FEATURE_EXT : string := "NONE"; + constant FEATURE_CMOV : string := "ENABLED"; + constant FEATURE_FFL1 : string := "ENABLED"; + constant FEATURE_ATOMIC : string := "ENABLED"; + + constant FEATURE_CUST1 : string := "NONE"; + constant FEATURE_CUST2 : string := "NONE"; + constant FEATURE_CUST3 : string := "NONE"; + constant FEATURE_CUST4 : string := "NONE"; + constant FEATURE_CUST5 : string := "NONE"; + constant FEATURE_CUST6 : string := "NONE"; + constant FEATURE_CUST7 : string := "NONE"; + constant FEATURE_CUST8 : string := "NONE"; + + constant FEATURE_FPU : string := "NONE"; -- ENABLED|NONE: actual for cappuccino pipeline only + + constant OPTION_SHIFTER : string := "BARREL"; + + constant FEATURE_STORE_BUFFER : string := "ENABLED"; + constant OPTION_STORE_BUFFER_DEPTH_WIDTH : integer := 8; + + constant FEATURE_MULTICORE : string := "NONE"; + + constant FEATURE_TRACEPORT_EXEC : string := "NONE"; + + constant BUS_IF_TYPE : string := "WISHBONE32"; + + constant IBUS_WB_TYPE : string := "CLASSIC"; -- Default: B3_READ_BURSTING + constant DBUS_WB_TYPE : string := "CLASSIC"; + + type debug_interface_i is record + addr : std_logic_vector(15 downto 0); + stb : std_logic; + dat : std_logic_vector(OPTION_OPERAND_WIDTH - 1 downto 0); + we : std_logic; + stall : std_logic; + end record debug_interface_i; + + type debug_interface_o is record + dat : std_logic_vector(OPTION_OPERAND_WIDTH - 1 downto 0); + ack : std_logic; + stall : std_logic; + end record debug_interface_o; + +end package mor1kx_pkg; + +package body mor1kx_pkg is +end package body mor1kx_pkg; diff --git a/ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_vhdl.vhd b/ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_vhdl.vhd new file mode 100644 index 0000000..4614b0f --- /dev/null +++ b/ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_vhdl.vhd @@ -0,0 +1,254 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library mor1kx; +use mor1kx.all; + +use work.wishbone_package.all; +use work.mor1kx_pkg.all; + +entity mor1kx_vhdl is + port( + clk : in std_logic; + rst : in std_logic; + -- Data bus wishbone master: + data_o : out wishbone_v3_master_out; + data_i : in wishbone_v3_master_in; + -- Instruction bus wishbone master: + inst_o : out wishbone_v3_master_out; + inst_i : in wishbone_v3_master_in; + -- IRQ + irq_i : in std_logic_vector(31 downto 0); + -- Debug + debug_o : out debug_interface_o; + debug_i : in debug_interface_i; + -- Trace Port + traceport_exec_valid_o : out std_logic; + traceport_exec_pc_o : out std_logic_vector(31 downto 0); + traceport_exec_insn_o : out std_logic_vector(OR1K_INSN_WIDTH - 1 downto 0); + traceport_exec_wbdata_o : out std_logic_vector(OPTION_OPERAND_WIDTH - 1 downto 0); + traceport_exec_wbreg_o : out std_logic_vector(OPTION_RF_ADDR_WIDTH - 1 downto 0); + traceport_exec_wben_o : out std_logic + ); +end entity mor1kx_vhdl; + +architecture RTL of mor1kx_vhdl is + COMPONENT mor1kx + GENERIC(OPTION_OPERAND_WIDTH : INTEGER := 32; OPTION_CPU0 : STRING := "CAPPUCCINO"; FEATURE_DATACACHE : STRING := "NONE"; OPTION_DCACHE_BLOCK_WIDTH : INTEGER := 5; + OPTION_DCACHE_SET_WIDTH : INTEGER := 9; OPTION_DCACHE_WAYS : INTEGER := 2; OPTION_DCACHE_LIMIT_WIDTH : INTEGER := 32; OPTION_DCACHE_SNOOP : STRING := "NONE"; + FEATURE_DMMU : STRING := "NONE"; FEATURE_DMMU_HW_TLB_RELOAD : STRING := "NONE"; OPTION_DMMU_SET_WIDTH : INTEGER := 6; OPTION_DMMU_WAYS : INTEGER := 1; + FEATURE_INSTRUCTIONCACHE : STRING := "NONE"; OPTION_ICACHE_BLOCK_WIDTH : INTEGER := 5; OPTION_ICACHE_SET_WIDTH : INTEGER := 9; OPTION_ICACHE_WAYS : INTEGER := 2; + OPTION_ICACHE_LIMIT_WIDTH : INTEGER := 32; FEATURE_IMMU : STRING := "NONE"; FEATURE_IMMU_HW_TLB_RELOAD : STRING := "NONE"; OPTION_IMMU_SET_WIDTH : INTEGER := 6; + OPTION_IMMU_WAYS : INTEGER := 1; FEATURE_TIMER : STRING := "ENABLED"; FEATURE_DEBUGUNIT : STRING := "NONE"; FEATURE_PERFCOUNTERS : STRING := "NONE"; + FEATURE_MAC : STRING := "NONE"; FEATURE_SYSCALL : STRING := "ENABLED"; FEATURE_TRAP : STRING := "ENABLED"; FEATURE_RANGE : STRING := "ENABLED"; + FEATURE_PIC : STRING := "ENABLED"; OPTION_PIC_TRIGGER : STRING := "LEVEL"; OPTION_PIC_NMI_WIDTH : INTEGER := 0; FEATURE_DSX : STRING := "ENABLED"; + FEATURE_OVERFLOW : STRING := "ENABLED"; FEATURE_CARRY_FLAG : STRING := "ENABLED"; FEATURE_FASTCONTEXTS : STRING := "NONE"; OPTION_RF_CLEAR_ON_INIT : INTEGER := 0; + OPTION_RF_NUM_SHADOW_GPR : INTEGER := 0; OPTION_RF_ADDR_WIDTH : INTEGER := 5; OPTION_RF_WORDS : INTEGER := 32; + -- OPTION_RESET_PC : STD_LOGIC_VECTOR; + FEATURE_MULTIPLIER : STRING := "THREESTAGE"; FEATURE_DIVIDER : STRING := "SERIAL"; FEATURE_ADDC : STRING := "ENABLED"; FEATURE_SRA : STRING := "ENABLED"; + FEATURE_ROR : STRING := "NONE"; FEATURE_EXT : STRING := "NONE"; FEATURE_CMOV : STRING := "ENABLED"; FEATURE_FFL1 : STRING := "ENABLED"; + FEATURE_ATOMIC : STRING := "ENABLED"; FEATURE_CUST1 : STRING := "NONE"; FEATURE_CUST2 : STRING := "NONE"; FEATURE_CUST3 : STRING := "NONE"; + FEATURE_CUST4 : STRING := "NONE"; FEATURE_CUST5 : STRING := "NONE"; FEATURE_CUST6 : STRING := "NONE"; FEATURE_CUST7 : STRING := "NONE"; + FEATURE_CUST8 : STRING := "NONE"; FEATURE_FPU : STRING := "NONE"; OPTION_SHIFTER : STRING := "BARREL"; FEATURE_STORE_BUFFER : STRING := "ENABLED"; + OPTION_STORE_BUFFER_DEPTH_WIDTH : INTEGER := 8; FEATURE_MULTICORE : STRING := "NONE"; FEATURE_TRACEPORT_EXEC : STRING := "NONE"; BUS_IF_TYPE : STRING := "WISHBONE32"; + IBUS_WB_TYPE : STRING := "B3_READ_BURSTING"; DBUS_WB_TYPE : STRING := "CLASSIC"); + PORT( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + iwbm_adr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + iwbm_stb_o : OUT STD_LOGIC; + iwbm_cyc_o : OUT STD_LOGIC; + iwbm_sel_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + iwbm_we_o : OUT STD_LOGIC; + iwbm_cti_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + iwbm_bte_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + iwbm_dat_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + iwbm_err_i : IN STD_LOGIC; + iwbm_ack_i : IN STD_LOGIC; + iwbm_dat_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + iwbm_rty_i : IN STD_LOGIC; + dwbm_adr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dwbm_stb_o : OUT STD_LOGIC; + dwbm_cyc_o : OUT STD_LOGIC; + dwbm_sel_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dwbm_we_o : OUT STD_LOGIC; + dwbm_cti_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + dwbm_bte_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dwbm_dat_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dwbm_err_i : IN STD_LOGIC; + dwbm_ack_i : IN STD_LOGIC; + dwbm_dat_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dwbm_rty_i : IN STD_LOGIC; + avm_d_address_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + avm_d_byteenable_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + avm_d_read_o : OUT STD_LOGIC; + avm_d_readdata_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + avm_d_burstcount_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + avm_d_write_o : OUT STD_LOGIC; + avm_d_writedata_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + avm_d_waitrequest_i : IN STD_LOGIC; + avm_d_readdatavalid_i : IN STD_LOGIC; + avm_i_address_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + avm_i_byteenable_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + avm_i_read_o : OUT STD_LOGIC; + avm_i_readdata_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + avm_i_burstcount_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + avm_i_waitrequest_i : IN STD_LOGIC; + avm_i_readdatavalid_i : IN STD_LOGIC; + irq_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + du_addr_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + du_stb_i : IN STD_LOGIC; + du_dat_i : IN STD_LOGIC_VECTOR(OPTION_OPERAND_WIDTH - 1 DOWNTO 0); + du_we_i : IN STD_LOGIC; + du_dat_o : OUT STD_LOGIC_VECTOR(OPTION_OPERAND_WIDTH - 1 DOWNTO 0); + du_ack_o : OUT STD_LOGIC; + du_stall_i : IN STD_LOGIC; + du_stall_o : OUT STD_LOGIC; + traceport_exec_valid_o : OUT STD_LOGIC; + traceport_exec_pc_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + traceport_exec_insn_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + traceport_exec_wbdata_o : OUT STD_LOGIC_VECTOR(OPTION_OPERAND_WIDTH - 1 DOWNTO 0); + traceport_exec_wbreg_o : OUT STD_LOGIC_VECTOR(OPTION_RF_ADDR_WIDTH - 1 DOWNTO 0); + traceport_exec_wben_o : OUT STD_LOGIC; + multicore_coreid_i : IN STD_LOGIC_VECTOR(OPTION_OPERAND_WIDTH - 1 DOWNTO 0); + multicore_numcores_i : IN STD_LOGIC_VECTOR(OPTION_OPERAND_WIDTH - 1 DOWNTO 0); + snoop_adr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + snoop_en_i : IN STD_LOGIC + ); + END COMPONENT; + +begin + mor1kx_inst : mor1kx + generic map( + OPTION_OPERAND_WIDTH => OPTION_OPERAND_WIDTH, + OPTION_CPU0 => OPTION_CPU0, + FEATURE_DATACACHE => FEATURE_DATACACHE, + OPTION_DCACHE_BLOCK_WIDTH => OPTION_DCACHE_BLOCK_WIDTH, + OPTION_DCACHE_SET_WIDTH => OPTION_DCACHE_SET_WIDTH, + OPTION_DCACHE_WAYS => OPTION_DCACHE_WAYS, + OPTION_DCACHE_LIMIT_WIDTH => OPTION_DCACHE_LIMIT_WIDTH, + OPTION_DCACHE_SNOOP => OPTION_DCACHE_SNOOP, + FEATURE_DMMU => FEATURE_DMMU, + FEATURE_DMMU_HW_TLB_RELOAD => FEATURE_DMMU_HW_TLB_RELOAD, + OPTION_DMMU_SET_WIDTH => OPTION_DMMU_SET_WIDTH, + OPTION_DMMU_WAYS => OPTION_DMMU_WAYS, + FEATURE_INSTRUCTIONCACHE => FEATURE_INSTRUCTIONCACHE, + OPTION_ICACHE_BLOCK_WIDTH => OPTION_ICACHE_BLOCK_WIDTH, + OPTION_ICACHE_SET_WIDTH => OPTION_ICACHE_SET_WIDTH, + OPTION_ICACHE_WAYS => OPTION_ICACHE_WAYS, + OPTION_ICACHE_LIMIT_WIDTH => OPTION_ICACHE_LIMIT_WIDTH, + FEATURE_IMMU => FEATURE_IMMU, + FEATURE_IMMU_HW_TLB_RELOAD => FEATURE_IMMU_HW_TLB_RELOAD, + OPTION_IMMU_SET_WIDTH => OPTION_IMMU_SET_WIDTH, + OPTION_IMMU_WAYS => OPTION_IMMU_WAYS, + FEATURE_TIMER => FEATURE_TIMER, + FEATURE_DEBUGUNIT => FEATURE_DEBUGUNIT, + FEATURE_PERFCOUNTERS => FEATURE_PERFCOUNTERS, + FEATURE_MAC => FEATURE_MAC, + FEATURE_SYSCALL => FEATURE_SYSCALL, + FEATURE_TRAP => FEATURE_TRAP, + FEATURE_RANGE => FEATURE_RANGE, + FEATURE_PIC => FEATURE_PIC, + OPTION_PIC_TRIGGER => OPTION_PIC_TRIGGER, + OPTION_PIC_NMI_WIDTH => OPTION_PIC_NMI_WIDTH, + FEATURE_DSX => FEATURE_DSX, + FEATURE_OVERFLOW => FEATURE_OVERFLOW, + FEATURE_CARRY_FLAG => FEATURE_CARRY_FLAG, + FEATURE_FASTCONTEXTS => FEATURE_FASTCONTEXTS, + OPTION_RF_CLEAR_ON_INIT => OPTION_RF_CLEAR_ON_INIT, + OPTION_RF_NUM_SHADOW_GPR => OPTION_RF_NUM_SHADOW_GPR, + OPTION_RF_ADDR_WIDTH => OPTION_RF_ADDR_WIDTH, + OPTION_RF_WORDS => OPTION_RF_WORDS, + -- OPTION_RESET_PC => OPTION_RESET_PC, + FEATURE_MULTIPLIER => FEATURE_MULTIPLIER, + FEATURE_DIVIDER => FEATURE_DIVIDER, + FEATURE_ADDC => FEATURE_ADDC, + FEATURE_SRA => FEATURE_SRA, + FEATURE_ROR => FEATURE_ROR, + FEATURE_EXT => FEATURE_EXT, + FEATURE_CMOV => FEATURE_CMOV, + FEATURE_FFL1 => FEATURE_FFL1, + FEATURE_ATOMIC => FEATURE_ATOMIC, + FEATURE_CUST1 => FEATURE_CUST1, + FEATURE_CUST2 => FEATURE_CUST2, + FEATURE_CUST3 => FEATURE_CUST3, + FEATURE_CUST4 => FEATURE_CUST4, + FEATURE_CUST5 => FEATURE_CUST5, + FEATURE_CUST6 => FEATURE_CUST6, + FEATURE_CUST7 => FEATURE_CUST7, + FEATURE_CUST8 => FEATURE_CUST8, + FEATURE_FPU => FEATURE_FPU, + OPTION_SHIFTER => OPTION_SHIFTER, + FEATURE_STORE_BUFFER => FEATURE_STORE_BUFFER, + OPTION_STORE_BUFFER_DEPTH_WIDTH => OPTION_STORE_BUFFER_DEPTH_WIDTH, + FEATURE_MULTICORE => FEATURE_MULTICORE, + FEATURE_TRACEPORT_EXEC => FEATURE_TRACEPORT_EXEC, + BUS_IF_TYPE => BUS_IF_TYPE, + IBUS_WB_TYPE => IBUS_WB_TYPE, + DBUS_WB_TYPE => DBUS_WB_TYPE + ) + port map( + clk => clk, + rst => rst, + iwbm_adr_o => inst_o.ADR, + iwbm_stb_o => inst_o.STB, + iwbm_cyc_o => inst_o.CYC, + iwbm_sel_o => inst_o.SEL, + iwbm_we_o => inst_o.WE, + iwbm_cti_o => inst_o.CTI, + iwbm_bte_o => inst_o.BTE, + iwbm_dat_o => inst_o.DAT, + iwbm_err_i => inst_i.ERR, + iwbm_ack_i => inst_i.ACK, + iwbm_dat_i => inst_i.DAT, + iwbm_rty_i => inst_i.RTY, + dwbm_adr_o => data_o.ADR, + dwbm_stb_o => data_o.STB, + dwbm_cyc_o => data_o.CYC, + dwbm_sel_o => data_o.SEL, + dwbm_we_o => data_o.WE, + dwbm_cti_o => data_o.CTI, + dwbm_bte_o => data_o.BTE, + dwbm_dat_o => data_o.DAT, + dwbm_err_i => data_i.ERR, + dwbm_ack_i => data_i.ACK, + dwbm_dat_i => data_i.DAT, + dwbm_rty_i => data_i.RTY, + -- avm_d_address_o => avm_d_address_o, + -- avm_d_byteenable_o => avm_d_byteenable_o, + -- avm_d_read_o => avm_d_read_o, + avm_d_readdata_i => (others => '0'), + -- avm_d_burstcount_o => avm_d_burstcount_o, + -- avm_d_write_o => avm_d_write_o, + -- avm_d_writedata_o => avm_d_writedata_o, + avm_d_waitrequest_i => '0', + avm_d_readdatavalid_i => '0', + -- avm_i_address_o => avm_i_address_o, + -- avm_i_byteenable_o => avm_i_byteenable_o, + -- avm_i_read_o => avm_i_read_o, + avm_i_readdata_i => (others => '0'), + -- avm_i_burstcount_o => avm_i_burstcount_o, + avm_i_waitrequest_i => '0', + avm_i_readdatavalid_i => '0', + irq_i => irq_i, + du_addr_i => debug_i.addr, + du_stb_i => debug_i.stb, + du_dat_i => debug_i.dat, + du_we_i => debug_i.we, + du_dat_o => debug_o.dat, + du_ack_o => debug_o.ack, + du_stall_i => debug_i.stall, + du_stall_o => debug_o.stall, + traceport_exec_valid_o => traceport_exec_valid_o, + traceport_exec_pc_o => traceport_exec_pc_o, + traceport_exec_insn_o => traceport_exec_insn_o, + traceport_exec_wbdata_o => traceport_exec_wbdata_o, + traceport_exec_wbreg_o => traceport_exec_wbreg_o, + traceport_exec_wben_o => traceport_exec_wben_o, + multicore_coreid_i => std_logic_vector(to_unsigned(0, OPTION_OPERAND_WIDTH)), + multicore_numcores_i => std_logic_vector(to_unsigned(0, OPTION_OPERAND_WIDTH)), + snoop_adr_i => (others => '0'), + snoop_en_i => '0' + ); +end architecture RTL; \ No newline at end of file diff --git a/quartus/mor1kx-bemicrocv.dpf b/quartus/mor1kx-bemicrocv.dpf new file mode 100644 index 0000000..d4ffa68 --- /dev/null +++ b/quartus/mor1kx-bemicrocv.dpf @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/quartus/mor1kx-bemicrocv.out.sdc b/quartus/mor1kx-bemicrocv.out.sdc new file mode 100644 index 0000000..1c7eb65 --- /dev/null +++ b/quartus/mor1kx-bemicrocv.out.sdc @@ -0,0 +1,952 @@ +## Generated SDC file "mor1kx-bemicrocv.out.sdc" + +## Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, the Altera Quartus Prime License Agreement, +## the Altera MegaCore Function License Agreement, or other +## applicable license agreement, including, without limitation, +## that your use is for the sole purpose of programming logic +## devices manufactured by Altera and sold by Altera or its +## authorized distributors. Please refer to the applicable +## agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" + +## DATE "Thu Jun 16 20:57:22 2016" + +## +## DEVICE "5CEFA2F23C7" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}] +create_clock -name {clk_hw} -period 13.333 -waveform { 0.000 10.000 } [get_ports { clk_hw }] +create_clock -name {mem_dqs[0]_IN} -period 3.333 -waveform { 0.000 1.667 } [get_ports {mem_dqs[0]}] -add +create_clock -name {mem_dqs[1]_IN} -period 3.333 -waveform { 0.000 1.667 } [get_ports {mem_dqs[1]}] -add + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 1000000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 1000000 -phase 270.000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll3~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_avl_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 5000000 -phase 9.000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 5000000 -phase 9.000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll6_phy~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_config_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 15000000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll7~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -name {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_registers {ddr3_inst|ddr3_inst|p0|umemphy|uio_pads|dq_ddio[*].ubidir_dq_dqs|altdq_dqs2_inst|dqs_enable_ctrl~DQSENABLEOUT_DFF}] +create_generated_clock -name {mem_ck[0]} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_ck[0]}] +create_generated_clock -name {mem_ck_n[0]} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} -invert [get_ports {mem_ck_n[0]}] +create_generated_clock -name {mem_dqs[0]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs[0]}] -add +create_generated_clock -name {mem_dqs[1]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs[1]}] -add +create_generated_clock -name {mem_dqs_n[0]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs_n[0]}] +create_generated_clock -name {mem_dqs_n[1]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs_n[1]}] + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_IN}] 0.100 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_IN}] 0.100 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_IN}] 0.100 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_IN}] 0.100 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_IN}] 0.100 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_IN}] 0.100 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_IN}] 0.100 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_IN}] 0.100 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {clk_hw}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280 +set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280 +set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {clk_hw}] 0.110 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {clk_hw}] 0.110 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}] 0.000 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck_n[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck[0]}] 0.226 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {clk_hw}] 0.110 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {clk_hw}] 0.110 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060 + + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[0]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[0]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[1]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[1]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[2]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[2]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[3]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[3]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[4]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[4]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[5]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[5]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[6]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[6]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}] 0.158 [get_ports {mem_dq[7]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}] -0.296 [get_ports {mem_dq[7]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[8]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[8]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[9]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[9]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[10]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[10]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[11]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[11]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[12]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[12]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[13]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[13]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[14]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[14]}] +set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}] 0.158 [get_ports {mem_dq[15]}] +set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}] -0.296 [get_ports {mem_dq[15]}] + + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[1]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[1]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[2]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[2]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[3]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[3]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[4]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[4]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[5]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[5]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[6]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[6]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[7]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[7]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[8]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[8]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[9]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[9]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[10]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[10]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[11]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[11]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_a[12]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_a[12]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_ba[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_ba[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_ba[1]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_ba[1]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_ba[2]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_ba[2]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_cas_n[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_cas_n[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_cke[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_cke[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_cs_n[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_cs_n[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dm[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dm[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dm[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dm[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dm[1]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dm[1]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dm[1]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dm[1]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[1]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[1]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[1]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[1]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[2]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[2]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[2]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[2]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[3]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[3]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[3]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[3]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[4]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[4]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[4]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[4]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[5]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[5]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[5]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[5]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[6]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[6]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[6]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[6]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}] 0.341 [get_ports {mem_dq[7]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}] -0.322 [get_ports {mem_dq[7]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}] 0.341 [get_ports {mem_dq[7]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}] -0.322 [get_ports {mem_dq[7]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[8]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[8]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[8]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[8]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[9]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[9]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[9]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[9]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[10]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[10]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[10]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[10]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[11]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[11]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[11]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[11]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[12]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[12]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[12]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[12]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[13]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[13]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[13]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[13]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[14]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[14]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[14]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[14]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}] 0.341 [get_ports {mem_dq[15]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}] -0.322 [get_ports {mem_dq[15]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}] 0.341 [get_ports {mem_dq[15]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}] -0.322 [get_ports {mem_dq[15]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.051 [get_ports {mem_dqs[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.282 [get_ports {mem_dqs[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.051 [get_ports {mem_dqs[1]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.282 [get_ports {mem_dqs[1]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_odt[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_odt[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_ras_n[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_ras_n[0]}] +set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}] 2.027 [get_ports {mem_we_n[0]}] +set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}] 1.407 [get_ports {mem_we_n[0]}] + + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[0]_IN}] -group [get_clocks {mem_dqs[0]_OUT mem_dqs_n[0]_OUT}] +set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[1]_IN}] -group [get_clocks {mem_dqs[1]_OUT mem_dqs_n[1]_OUT}] +set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[0]_IN}] -group [get_clocks {mem_dqs[0]_OUT mem_dqs_n[0]_OUT}] +set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[1]_IN}] -group [get_clocks {mem_dqs[1]_OUT mem_dqs_n[1]_OUT}] + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {mem_ck[0]}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {mem_dqs[0]_IN}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {mem_dqs[1]_IN}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {*_IN}] +set_false_path -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {mem_ck[0]}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {mem_dqs[0]_IN}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {mem_dqs[1]_IN}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {*_IN}] +set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] +set_false_path -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_ports {{mem_a[0]} {mem_a[10]} {mem_a[11]} {mem_a[12]} {mem_a[1]} {mem_a[2]} {mem_a[3]} {mem_a[4]} {mem_a[5]} {mem_a[6]} {mem_a[7]} {mem_a[8]} {mem_a[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} {mem_cas_n[0]} {mem_cke[0]} {mem_cs_n[0]} {mem_odt[0]} {mem_ras_n[0]} {mem_we_n[0]}}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*]}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[0]_OUT}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[1]_OUT}] +set_false_path -from [get_keepers {ddr3:ddr3_inst|ddr3_0002:ddr3_inst|ddr3_p0:p0|ddr3_p0_acv_hard_memphy:umemphy|hphy_inst~FF_39}] -to [get_keepers {rst}] +set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}] +set_false_path -from [get_registers {*altera_jtag_src_crosser:*|sink_data_buffer*}] -to [get_registers {*altera_jtag_src_crosser:*|src_data*}] +set_false_path -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_ports {{mem_a[0]} {mem_a[10]} {mem_a[11]} {mem_a[12]} {mem_a[1]} {mem_a[2]} {mem_a[3]} {mem_a[4]} {mem_a[5]} {mem_a[6]} {mem_a[7]} {mem_a[8]} {mem_a[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} {mem_cas_n[0]} {mem_cke[0]} {mem_cs_n[0]} {mem_odt[0]} {mem_ras_n[0]} {mem_we_n[0]}}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_DFF}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_DFF}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*vfifo~INC_WR_PTR_DFF}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|vfifo~QVLD_IN_DFF}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_OUT_RDATA_VALID_DFF}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|vfifo~QVLD_IN_DFF}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~RD_LATENCY_DFF*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*altdq_dqs2_inst|*output_path_gen[*].ddio_out*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*altdq_dqs2_inst|extra_output_pad_gen[*].ddio_out*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*phase_align_os~DFF*}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] +set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*]}] +set_false_path -to [get_ports {mem_dqs_n[0]}] +set_false_path -to [get_ports {mem_dqs_n[1]}] +set_false_path -to [get_ports {mem_ck[0]}] +set_false_path -to [get_ports {mem_ck_n[0]}] +set_false_path -to [get_ports {mem_reset_n}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[0]_OUT}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[1]_OUT}] +set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|dqs_enable_ctrl~*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|dqs_delay_chain~POSTAMBLE_DFF}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -setup -start -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 5 +set_multicycle_path -hold -start -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 4 +set_multicycle_path -hold -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1 +set_multicycle_path -setup -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 2 +set_multicycle_path -hold -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1 +set_multicycle_path -setup -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 2 +set_multicycle_path -hold -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 1 +set_multicycle_path -setup -start -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 5 +set_multicycle_path -hold -start -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 4 +set_multicycle_path -hold -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1 +set_multicycle_path -setup -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 2 +set_multicycle_path -hold -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1 +set_multicycle_path -setup -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 2 +set_multicycle_path -hold -end -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 1 +set_multicycle_path -setup -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*}] 4 +set_multicycle_path -hold -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*}] 4 +set_multicycle_path -setup -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_FULL_DFF}] 2 +set_multicycle_path -hold -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_FULL_DFF}] 1 +set_multicycle_path -setup -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|*read_fifo~READ_ADDRESS_DFF}] 2 +set_multicycle_path -hold -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|*read_fifo~READ_ADDRESS_DFF}] 1 +set_multicycle_path -setup -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]}] 2 +set_multicycle_path -hold -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]}] 1 + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + +set_max_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[2]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[3]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[4]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[5]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[6]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[7]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[8]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[9]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[10]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[11]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[12]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[13]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[14]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 +set_max_delay -from [get_ports {mem_dq[15]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000 + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + +set_min_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[2]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[3]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[4]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[5]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[6]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[7]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[8]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[9]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[10]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[11]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[12]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[13]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[14]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 +set_min_delay -from [get_ports {mem_dq[15]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667 + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/quartus/mor1kx-bemicrocv.qpf b/quartus/mor1kx-bemicrocv.qpf new file mode 100644 index 0000000..a9136a3 --- /dev/null +++ b/quartus/mor1kx-bemicrocv.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 21:47:28 June 10, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "21:47:28 June 10, 2016" + +# Revisions + +PROJECT_REVISION = "mor1kx-bemicrocv" diff --git a/quartus/mor1kx-bemicrocv.qsf b/quartus/mor1kx-bemicrocv.qsf new file mode 100644 index 0000000..fd69c62 --- /dev/null +++ b/quartus/mor1kx-bemicrocv.qsf @@ -0,0 +1,371 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 21:47:28 June 10, 2016 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# mor1kx-bemicrocv_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + +set_location_assignment PIN_T22 -to jinn_uart_rx +set_location_assignment PIN_T15 -to jinn_uart_tx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to jinn_uart_rx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to jinn_uart_tx +set_location_assignment PIN_N1 -to GPIOA[0] +set_location_assignment PIN_N2 -to GPIOA[1] +set_location_assignment PIN_U1 -to GPIOA[2] +set_location_assignment PIN_U2 -to GPIOA[3] +set_location_assignment PIN_W2 -to GPIOA[4] +set_location_assignment PIN_AA1 -to GPIOA[5] +set_location_assignment PIN_AA2 -to GPIOA[6] +set_location_assignment PIN_Y3 -to GPIOA[7] +set_location_assignment PIN_R22 -to uart_rx +set_location_assignment PIN_R15 -to uart_tx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_rx +set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIOA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_tx +set_instance_assignment -name IO_STANDARD "SSTL-15" -to oct_rzqin -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[0] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[1] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[2] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[3] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[4] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[5] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[6] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[7] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[8] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[9] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[10] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[11] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[12] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[13] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[14] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[15] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[0] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_p0 +set_instance_assignment -name D5_DELAY 4 -to mem_dqs[0] -tag __ddr3_p0 +set_instance_assignment -name D6_DELAY 0 -to mem_dqs[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[1] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_p0 +set_instance_assignment -name D5_DELAY 4 -to mem_dqs[1] -tag __ddr3_p0 +set_instance_assignment -name D6_DELAY 0 -to mem_dqs[1] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[0] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_p0 +set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[0] -tag __ddr3_p0 +set_instance_assignment -name D6_DELAY 0 -to mem_dqs_n[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[1] -tag __ddr3_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_p0 +set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[1] -tag __ddr3_p0 +set_instance_assignment -name D6_DELAY 0 -to mem_dqs_n[1] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck[0] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck[0] -tag __ddr3_p0 +set_instance_assignment -name D5_DELAY 2 -to mem_ck[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck_n[0] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck_n[0] -tag __ddr3_p0 +set_instance_assignment -name D5_DELAY 2 -to mem_ck_n[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[10] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[10] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[11] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[11] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[12] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[12] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[1] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[1] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[2] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[2] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[3] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[3] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[4] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[4] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[5] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[5] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[6] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[6] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[7] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[7] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[8] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[8] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[9] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[9] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[1] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[1] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[2] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[2] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cas_n[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cas_n[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cke[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cke[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cs_n[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cs_n[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_odt[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_odt[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ras_n[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ras_n[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_we_n[0] -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_we_n[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __ddr3_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_reset_n -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[0] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[0] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[1] -tag __ddr3_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[1] -tag __ddr3_p0 +set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_hw +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[8] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[9] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[10] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[11] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[12] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[13] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[14] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[15] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[1] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[1] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[1] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __ddr3_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to ddr3_inst|ddr3_inst|pll0|pll_avl_clk -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to ddr3_inst|ddr3_inst|pll0|pll_config_clk -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|ureset|phy_reset_n -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __ddr3_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ddr3_p0 +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ddr3_inst|ddr3_inst -tag __ddr3_p0 +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to ddr3_inst|ddr3_inst|pll0|fbout -tag __ddr3_p0 +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ECO_REGENERATE_REPORT ON +set_location_assignment PIN_L7 -to mem_a[0] +set_location_assignment PIN_K7 -to mem_a[1] +set_location_assignment PIN_H8 -to mem_a[2] +set_location_assignment PIN_G8 -to mem_a[3] +set_location_assignment PIN_J7 -to mem_a[4] +set_location_assignment PIN_J8 -to mem_a[5] +set_location_assignment PIN_A10 -to mem_a[6] +set_location_assignment PIN_A9 -to mem_a[7] +set_location_assignment PIN_A8 -to mem_a[8] +set_location_assignment PIN_A7 -to mem_a[9] +set_location_assignment PIN_C6 -to mem_a[10] +set_location_assignment PIN_D6 -to mem_a[11] +set_location_assignment PIN_D7 -to mem_a[12] +set_location_assignment PIN_A5 -to mem_ba[0] +set_location_assignment PIN_B10 -to mem_ba[1] +set_location_assignment PIN_C9 -to mem_ba[2] +set_location_assignment PIN_B6 -to mem_cas_n[0] +set_location_assignment PIN_J9 -to mem_ck[0] +set_location_assignment PIN_H9 -to mem_ck_n[0] +set_location_assignment PIN_F14 -to mem_cke[0] +set_location_assignment PIN_E9 -to mem_cs_n[0] +set_location_assignment PIN_G11 -to mem_dm[0] +set_location_assignment PIN_J17 -to mem_dm[1] +set_location_assignment PIN_E12 -to mem_dq[0] +set_location_assignment PIN_D12 -to mem_dq[1] +set_location_assignment PIN_C11 -to mem_dq[2] +set_location_assignment PIN_K9 -to mem_dq[3] +set_location_assignment PIN_C13 -to mem_dq[4] +set_location_assignment PIN_D13 -to mem_dq[5] +set_location_assignment PIN_B12 -to mem_dq[6] +set_location_assignment PIN_F12 -to mem_dq[7] +set_location_assignment PIN_F13 -to mem_dq[8] +set_location_assignment PIN_E14 -to mem_dq[9] +set_location_assignment PIN_J11 -to mem_dq[10] +set_location_assignment PIN_A13 -to mem_dq[11] +set_location_assignment PIN_B15 -to mem_dq[12] +set_location_assignment PIN_C15 -to mem_dq[13] +set_location_assignment PIN_G15 -to mem_dq[14] +set_location_assignment PIN_K16 -to mem_dq[15] +set_location_assignment PIN_H11 -to mem_dqs[0] +set_location_assignment PIN_G12 -to mem_dqs_n[0] +set_location_assignment PIN_H14 -to mem_dqs[1] +set_location_assignment PIN_J13 -to mem_dqs_n[1] +set_location_assignment PIN_L8 -to mem_odt[0] +set_location_assignment PIN_B7 -to mem_ras_n[0] +set_location_assignment PIN_J19 -to mem_reset_n +set_location_assignment PIN_F7 -to mem_we_n[0] +set_location_assignment PIN_B11 -to oct_rzqin +set_location_assignment PIN_H18 -to rst_hw +set_location_assignment PIN_H13 -to clk_hw + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CEFA2F23C7 +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:47:28 JUNE 10, 2016" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + +set_instance_assignment -name IO_STANDARD "1.5 V" -to rst_hw +set_global_assignment -name SDC_FILE "mor1kx-bemicrocv.out.sdc" +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_true_dpram_sclk.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ticktimer.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_store_buffer.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_simple_dpram_sclk.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_espresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_pic.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_espresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_immu.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_icache.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_prontoespresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_espresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_alu.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dmmu.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode_execute_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dcache.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_prontoespresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_espresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_prontoespresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_espresso.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_cappuccino.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cfgrs.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cache_lru.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_wb32.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_avalon.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_branch_prediction.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-sprs.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-defines.v" -library mor1kx +set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx.v" -library mor1kx +set_global_assignment -name QIP_FILE ../ip/altera/ram0.qip +set_global_assignment -name VHDL_FILE "../ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_pkg.vhd" -library ip +set_global_assignment -name VHDL_FILE "../ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_vhdl.vhd" -library ip +set_global_assignment -name VHDL_FILE ../cores/jinn.vhd +set_global_assignment -name VHDL_FILE ../cores/uart/uart_wb.vhd +set_global_assignment -name VHDL_FILE ../cores/uart/uart_tx.vhd +set_global_assignment -name VHDL_FILE ../cores/uart/uart_rx.vhd +set_global_assignment -name VHDL_FILE ../cores/sram/sram_wb.vhd +set_global_assignment -name VHDL_FILE ../cores/generic/synchronizer.vhd +set_global_assignment -name VHDL_FILE ../cores/generic/edgeDetector.vhd +set_global_assignment -name VHDL_FILE ../design/top.vhd +set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/wishbone_package.vhd -library ip +set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/crossbar_v3.vhd -library ip +set_global_assignment -name QIP_FILE ../ip/altera/ddr3.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/quartus/mor1kx-bemicrocv.qws b/quartus/mor1kx-bemicrocv.qws new file mode 100644 index 0000000..39bb1ec Binary files /dev/null and b/quartus/mor1kx-bemicrocv.qws differ diff --git a/quartus/mor1kx-bemicrocv_assignment_defaults.qdf b/quartus/mor1kx-bemicrocv_assignment_defaults.qdf new file mode 100644 index 0000000..5619745 --- /dev/null +++ b/quartus/mor1kx-bemicrocv_assignment_defaults.qdf @@ -0,0 +1,799 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition +# Date created = 20:27:34 June 16, 2016 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix 10" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix 10" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix 10" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Stratix 10" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x1" -family "Stratix 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS Off -family "Stratix 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Stratix 10" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Stratix 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off +set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS OFF -family "Stratix 10" +set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS ON -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000001 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000010 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000100 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0001000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0010000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?