diff --git a/bench/bench_top.vhd b/bench/bench_top.vhd index 2238fa1..dc439fa 100644 --- a/bench/bench_top.vhd +++ b/bench/bench_top.vhd @@ -12,56 +12,88 @@ entity bench_top is end entity bench_top; architecture RTL of bench_top is - signal clk_hw : std_logic; - signal rst_hw : std_logic; - signal GPIOA : std_logic_vector(wishbone_data_width - 1 downto 0); - signal jinn_uart_rx : std_logic; - signal jinn_uart_tx : std_logic; - signal uart_rx : std_logic; - signal uart_tx : std_logic; + signal clk_hw : std_logic; + signal rst_hw : std_logic; + signal GPIOA : std_logic_vector(wishbone_data_width - 1 downto 0); + signal jinn_uart_rx : std_logic; + signal jinn_uart_tx : std_logic; + signal uart_rx : std_logic; + signal uart_tx : std_logic; -- DDR3 - signal mem_a : std_logic_vector(12 downto 0); - signal mem_ba : std_logic_vector(2 downto 0); - signal mem_ck : std_logic_vector(0 downto 0); - signal mem_ck_n : std_logic_vector(0 downto 0); - signal mem_cke : std_logic_vector(0 downto 0); - signal mem_cs_n : std_logic_vector(0 downto 0); - signal mem_dm : std_logic_vector(1 downto 0); - signal mem_ras_n : std_logic_vector(0 downto 0); - signal mem_cas_n : std_logic_vector(0 downto 0); - signal mem_we_n : std_logic_vector(0 downto 0); - signal mem_reset_n : std_logic; - signal mem_dq : std_logic_vector(15 downto 0); - signal mem_dqs : std_logic_vector(1 downto 0); - signal mem_dqs_n : std_logic_vector(1 downto 0); - signal mem_odt : std_logic_vector(0 downto 0); - signal oct_rzqin : std_logic; + signal mem_a : std_logic_vector(12 downto 0); + signal mem_ba : std_logic_vector(2 downto 0); + signal mem_ck : std_logic_vector(0 downto 0); + signal mem_ck_n : std_logic_vector(0 downto 0); + signal mem_cke : std_logic_vector(0 downto 0); + signal mem_cs_n : std_logic_vector(0 downto 0); + signal mem_dm : std_logic_vector(1 downto 0); + signal mem_ras_n : std_logic_vector(0 downto 0); + signal mem_cas_n : std_logic_vector(0 downto 0); + signal mem_we_n : std_logic_vector(0 downto 0); + signal mem_reset_n : std_logic; + signal mem_dq : std_logic_vector(15 downto 0); + signal mem_dqs : std_logic_vector(1 downto 0); + signal mem_dqs_n : std_logic_vector(1 downto 0); + signal mem_odt : std_logic_vector(0 downto 0); + signal oct_rzqin : std_logic; + -- Flash + signal flash_si : std_logic; + signal flash_cs_n : std_logic; + signal flash_sck : std_logic; + signal flash_wp_n : std_logic; + signal flash_reset_n : std_logic; + signal flash_so : std_logic; + signal flash_busy : std_logic; + begin top_inst : entity design.top port map( - clk_hw => clk_hw, - rst_hw => rst_hw, - GPIOA => GPIOA, - jinn_uart_rx => jinn_uart_rx, - jinn_uart_tx => jinn_uart_tx, - uart_rx => uart_rx, - uart_tx => uart_tx, - mem_a => mem_a, - mem_ba => mem_ba, - mem_ck => mem_ck, - mem_ck_n => mem_ck_n, - mem_cke => mem_cke, - mem_cs_n => mem_cs_n, - mem_dm => mem_dm, - mem_ras_n => mem_ras_n, - mem_cas_n => mem_cas_n, - mem_we_n => mem_we_n, - mem_reset_n => mem_reset_n, - mem_dq => mem_dq, - mem_dqs => mem_dqs, - mem_dqs_n => mem_dqs_n, - mem_odt => mem_odt, - oct_rzqin => oct_rzqin + clk_hw => clk_hw, + rst_hw => rst_hw, + GPIOA => GPIOA, + jinn_uart_rx => jinn_uart_rx, + jinn_uart_tx => jinn_uart_tx, + uart_rx => uart_rx, + uart_tx => uart_tx, + mem_a => mem_a, + mem_ba => mem_ba, + mem_ck => mem_ck, + mem_ck_n => mem_ck_n, + mem_cke => mem_cke, + mem_cs_n => mem_cs_n, + mem_dm => mem_dm, + mem_ras_n => mem_ras_n, + mem_cas_n => mem_cas_n, + mem_we_n => mem_we_n, + mem_reset_n => mem_reset_n, + mem_dq => mem_dq, + mem_dqs => mem_dqs, + mem_dqs_n => mem_dqs_n, + mem_odt => mem_odt, + oct_rzqin => oct_rzqin, + flash_si => flash_si, + flash_so => flash_so, + flash_sck => flash_sck, + flash_reset_n => flash_reset_n, + flash_cs_n => flash_cs_n, + flash_wp_n => flash_wp_n + ); + + DataFlash_inst : entity work.DataFlash + generic map( + flashmemory => "devicemodels/memory.txt", + Rapid_interface => true, + fsck => 66, + DEVICE => "AT45DB011D", --AT45DB011D + Tsck => 13.6 ns) + port map( + SI => flash_si, + CSB => flash_cs_n, + SCK => flash_sck, + WPB => flash_wp_n, + RESETB => flash_reset_n, + SO => flash_so, + RDYBSY => flash_busy ); clock_driver : process @@ -69,7 +101,7 @@ begin begin clk_hw <= '0'; wait for period / 2; - clk_hw <= '1'; + clk_hw <= '1'; wait for period / 2; end process clock_driver;