diff --git a/bench/bench_flashrom_controller.vhd b/bench/bench_flashrom_controller.vhd index 0cae27c..1adba4e 100644 --- a/bench/bench_flashrom_controller.vhd +++ b/bench/bench_flashrom_controller.vhd @@ -107,8 +107,11 @@ begin --testbench bench : process is begin - rst <= '1'; - clr <= '0'; + rst <= '1'; + clr <= '0'; + status_update_stb <= '0'; + load_stb <= '0'; + page <= (others => '0'); wait for 10 ns * 2; wait until (rising_edge(clk)); rst <= '0'; @@ -117,7 +120,10 @@ begin -- bench code here wait until ready = '1'; - strobe(load_stb); + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); wait until ready = '1'; strobe(load_stb); @@ -132,7 +138,41 @@ begin strobe(status_update_stb); wait until ready = '1'; - strobe(load_stb); + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + + wait until ready = '1'; + strobe(status_update_stb); + wait; end process bench; diff --git a/cores/flashrom-wb/flashrom_controller.vhd b/cores/flashrom-wb/flashrom_controller.vhd index a4d265a..8673932 100644 --- a/cores/flashrom-wb/flashrom_controller.vhd +++ b/cores/flashrom-wb/flashrom_controller.vhd @@ -37,10 +37,10 @@ end entity flashrom_controller; architecture RTL of flashrom_controller is constant spif_max_word_length : integer := 32; - constant max_dummy_bits : integer := 16; + constant max_dummy_bits : integer := 63; constant bootup_delay : integer := 4000; - type state_t is (INIT, GETINFO, GETSTATUS, IDLE); + type state_t is (INIT, GETINFO, GETSTATUS, LOADPAGE, IDLE); signal state : state_t; signal spif_data_in_valid : std_logic; @@ -106,13 +106,13 @@ begin temp_cnt := 0; end procedure reset_state; - procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector(31 downto 0)) is + procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector) is begin spif_data_in_length <= data_in_length; spif_data_out_length <= data_out_length; spif_data_out_dummy_bits <= data_out_dummy_bits; spif_data_in_valid <= '1'; - spif_data_in <= data_in; + spif_data_in <= data_in & padBits(spif_data_in, data_in); if temp_cnt = nTxWords then spif_data_in_valid <= '0'; @@ -120,7 +120,7 @@ begin temp_cnt := temp_cnt + 1; end if; - if spif_data_out_valid = '1' then + if spif_data_out_valid = '1' and (temp_cnt = nTxWords) then spif_data_in_valid <= '0'; done := true; state <= IDLE; @@ -146,7 +146,7 @@ begin temp_cnt := temp_cnt + 1; end if; when GETINFO => -- TODO: In simulation I can only call this command once?! - run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID)); + run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID); if done then info <= spif_data_out; end if; @@ -156,16 +156,24 @@ begin state <= GETSTATUS; end if; if load_stb = '1' then --debug only - state <= GETINFO; + state <= LOADPAGE; end if; when GETSTATUS => - run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS)); + run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS); if done then status <= spif_data_out(7 downto 0); end if; + when LOADPAGE => + run_command_single(24, 8, 34, 16, FLASHROM_COMMAND_CONT_ARRAY_READ & page); + if done then + report "Load page done." severity note; + end if; end case; end if; end if; end process flashrom_controller_p; ready <= '1' when state = IDLE else '0'; + + data_out <= spif_data_out(7 downto 0); + data_out_valid <= spif_data_out_valid when state = LOADPAGE else '0'; end architecture RTL; diff --git a/cores/flashrom-wb/flashrom_pkg.vhd b/cores/flashrom-wb/flashrom_pkg.vhd index 9c215e5..46bf485 100644 --- a/cores/flashrom-wb/flashrom_pkg.vhd +++ b/cores/flashrom-wb/flashrom_pkg.vhd @@ -6,6 +6,7 @@ package flashrom_pkg is constant FLASHROM_ADDR_WIDTH : integer := 12; constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7"; + constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B"; function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector; end package flashrom_pkg;