From dfcd35b15267b7c1e35b2a5f1b8e896c5334248f Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Sun, 26 Feb 2017 20:39:51 +0100 Subject: [PATCH] Added Flashrom to top level --- design/top.vhd | 91 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 59 insertions(+), 32 deletions(-) diff --git a/design/top.vhd b/design/top.vhd index e472806..655fe4e 100644 --- a/design/top.vhd +++ b/design/top.vhd @@ -10,37 +10,45 @@ use ip.mor1kx_pkg.all; entity top is port( - clk_hw : in std_logic; - rst_hw : in std_logic; + clk_hw : in std_logic; + rst_hw : in std_logic; -- GPIO - GPIOA : inout std_logic_vector(wishbone_data_width - 1 downto 0); + GPIOA : inout std_logic_vector(wishbone_data_width - 1 downto 0); -- JINN - jinn_uart_rx : in std_logic; - jinn_uart_tx : out std_logic; + jinn_uart_rx : in std_logic; + jinn_uart_tx : out std_logic; -- UART - uart_rx : in std_logic; - uart_tx : out std_logic; + uart_rx : in std_logic; + uart_tx : out std_logic; -- DDR3 RAM - mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a - mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba - mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck - mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n - mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke - mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n - mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm - mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n - mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n - mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n - mem_reset_n : out std_logic; -- .mem_reset_n - mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq - mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs - mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n - mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt - oct_rzqin : in std_logic -- oct.rzqin + mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a + mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba + mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n + mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n + mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm + mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n + mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n + mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n + mem_reset_n : out std_logic; -- .mem_reset_n + mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq + mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs + mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n + mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt + oct_rzqin : in std_logic; -- oct.rzqin + + -- SPI Flash Hardware Signals + flash_si : out std_logic; -- spi serial in + flash_so : in std_logic; -- spi serial out + flash_sck : out std_logic; -- spi clock + flash_reset_n : out std_logic; -- spi hard reset + flash_cs_n : out std_logic; -- spi chip select + flash_wp_n : out std_logic -- spi write protect ); end entity top; @@ -50,13 +58,14 @@ architecture RTL of top is constant F_CPU : natural := 50000000; -- WB config - constant masters : natural := 3; - constant slaves : natural := 2; - constant INTERCON_ID_SRAM : natural := 0; - constant INTERCON_ID_DDR3 : natural := 1; - constant INTERCON_ID_GPIO : natural := 2; - constant INTERCON_ID_UART : natural := 3; - constant INTERCON_ID_NS16550 : natural := 4; + constant masters : natural := 3; + constant slaves : natural := 3; + constant INTERCON_ID_SRAM : natural := 0; + constant INTERCON_ID_DDR3 : natural := 1; + constant INTERCON_ID_FLASH : natural := 2; + -- constant INTERCON_ID_GPIO : natural := 2; + -- constant INTERCON_ID_UART : natural := 3; + -- constant INTERCON_ID_NS16550 : natural := 4; constant in_simulation : boolean := false --pragma synthesis_off @@ -297,6 +306,22 @@ begin end if; end process wb2avl; + -- Non Volatile Memory + flashrom_wb_inst : entity work.flashrom_wb + port map( + clk => clk, + rst => rst, + clr => '0', + wb_in => intercon_slave_i(INTERCON_ID_FLASH), + wb_out => intercon_slave_o(INTERCON_ID_FLASH), + spi_si => flash_si, + spi_so => flash_so, + spi_sck => flash_sck, + spi_reset_n => flash_reset_n, + spi_cs_n => flash_cs_n, + spi_wp_n => flash_wp_n + ); + -- Intercon crossbar_inst : entity ip.crossbar generic map( @@ -313,11 +338,13 @@ begin master_o => intercon_slave_i, address => ( INTERCON_ID_SRAM => x"00000000", - INTERCON_ID_DDR3 => x"80000000" + INTERCON_ID_DDR3 => x"10000000", + INTERCON_ID_FLASH => x"90000000" ), mask => ( INTERCON_ID_SRAM => x"ffff0000", - INTERCON_ID_DDR3 => x"f0000000" + INTERCON_ID_DDR3 => x"f0000000", + INTERCON_ID_FLASH => x"f0000000" ) ); end architecture RTL;