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3 Commits

Author SHA1 Message Date
Markus Koch 3fffa6efe3 Added address masking to crossbar switch 2017-03-02 09:31:05 +01:00
Markus Koch 20387479c0 Added UART to top level 2017-03-02 09:30:38 +01:00
Markus Koch 4ca1ba0928 Converted UART to Wishbone v3 2017-03-02 09:29:41 +01:00
3 changed files with 31 additions and 11 deletions

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@ -1,3 +1,6 @@
-- TODO: WARN: SEL bits ignored.
-- TODO: Multiple ports is broken (address mapping * 4), plus some ACK error maybe?
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@ -14,8 +17,8 @@ entity uart_wb is
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
-- Wishbone -- Wishbone
slave_i : in wishbone_slave_in; slave_i : in wishbone_v3_slave_in;
slave_o : out wishbone_slave_out; slave_o : out wishbone_v3_slave_out;
irq_o : out std_logic_vector(portcount - 1 downto 0); irq_o : out std_logic_vector(portcount - 1 downto 0);
-- UART -- UART
rx : in std_logic_vector(portcount - 1 downto 0); rx : in std_logic_vector(portcount - 1 downto 0);
@ -93,7 +96,7 @@ begin
end loop; end loop;
elsif rising_edge(clk) then elsif rising_edge(clk) then
for i in 0 to portcount - 1 loop for i in 0 to portcount - 1 loop
slave_o.ACK <= '0'; slave_o.ACK <= '0';
tx_strobe(i) <= '0'; tx_strobe(i) <= '0';
--SR update --SR update
@ -143,9 +146,8 @@ begin
end if; end if;
end process wb; end process wb;
slave_o.RTY <= '0'; slave_o.RTY <= '0';
slave_o.STALL <= '0'; slave_o.ERR <= '0';
slave_o.ERR <= '0';
applyCR : for i in 0 to portcount - 1 generate applyCR : for i in 0 to portcount - 1 generate
ckDiv(i) <= CR(i)(31 downto 16); ckDiv(i) <= CR(i)(31 downto 16);

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@ -59,12 +59,12 @@ architecture RTL of top is
-- WB config -- WB config
constant masters : natural := 3; constant masters : natural := 3;
constant slaves : natural := 4; constant slaves : natural := 5;
constant INTERCON_ID_SRAM : natural := 0; constant INTERCON_ID_SRAM : natural := 0;
constant INTERCON_ID_DDR3 : natural := 1; constant INTERCON_ID_DDR3 : natural := 1;
constant INTERCON_ID_FLASH : natural := 2; constant INTERCON_ID_FLASH : natural := 2;
constant INTERCON_ID_GPIO : natural := 3; constant INTERCON_ID_GPIO : natural := 3;
-- constant INTERCON_ID_UART : natural := 3; constant INTERCON_ID_UART : natural := 4;
-- constant INTERCON_ID_NS16550 : natural := 4; -- constant INTERCON_ID_NS16550 : natural := 4;
constant in_simulation : boolean := false constant in_simulation : boolean := false
@ -333,6 +333,21 @@ begin
gpio => GPIOA gpio => GPIOA
); );
-- UART
uart_wb_inst : entity work.uart_wb
generic map(
portcount => 1
)
port map(
clk => clk,
rst => rst,
slave_i => intercon_slave_i(INTERCON_ID_UART),
slave_o => intercon_slave_o(INTERCON_ID_UART),
irq_o => open, -- TODO
rx(0) => uart_rx,
tx(0) => uart_tx
);
-- Intercon -- Intercon
crossbar_inst : entity ip.crossbar crossbar_inst : entity ip.crossbar
generic map( generic map(
@ -351,13 +366,15 @@ begin
INTERCON_ID_SRAM => x"00000000", INTERCON_ID_SRAM => x"00000000",
INTERCON_ID_DDR3 => x"10000000", INTERCON_ID_DDR3 => x"10000000",
INTERCON_ID_FLASH => x"40000000", INTERCON_ID_FLASH => x"40000000",
INTERCON_ID_GPIO => x"80000000" INTERCON_ID_GPIO => x"80000000",
INTERCON_ID_UART => x"80000100"
), ),
mask => ( mask => (
INTERCON_ID_SRAM => x"ffff0000", INTERCON_ID_SRAM => x"ffff0000",
INTERCON_ID_DDR3 => x"f0000000", INTERCON_ID_DDR3 => x"f0000000",
INTERCON_ID_FLASH => x"f0000000", INTERCON_ID_FLASH => x"f0000000",
INTERCON_ID_GPIO => x"fffffffc" INTERCON_ID_GPIO => x"fffffff0",
INTERCON_ID_UART => x"ffffffc0"
) )
); );
end architecture RTL; end architecture RTL;

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@ -174,7 +174,8 @@ architecture rtl of crossbar is
DAT => acc.DAT or (slave_i(master).DAT and granted_data)); DAT => acc.DAT or (slave_i(master).DAT and granted_data));
end loop; end loop;
-- acc.ADR := std_logic_vector(unsigned(acc.ADR) - unsigned(address(slave))); -- Address translation -- acc.ADR := std_logic_vector(unsigned(acc.ADR) - unsigned(address(slave))); -- Address translation
o <= acc; acc.ADR := acc.ADR and not mask(slave); -- Address masking
o <= acc;
end slave_logic; end slave_logic;
-- Select the slave pins the master will receive -- Select the slave pins the master will receive