cores/uart/uart_wb.vhd

@@ -1,6 +1,3 @@
--- TODO: WARN: SEL bits ignored.
--- TODO: Multiple ports is broken (address mapping * 4), plus some ACK error maybe?
-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -17,8 +14,8 @@ entity uart_wb is
 		clk     : in  std_logic;
 		rst     : in  std_logic;
 		-- Wishbone
-		slave_i : in  wishbone_v3_slave_in;
-		slave_o : out wishbone_v3_slave_out;
+		slave_i : in  wishbone_slave_in;
+		slave_o : out wishbone_slave_out;
 		irq_o   : out std_logic_vector(portcount - 1 downto 0);
 		-- UART
 		rx      : in  std_logic_vector(portcount - 1 downto 0);
@@ -147,6 +144,7 @@ begin
 	end process wb;
 
 	slave_o.RTY   <= '0';
+	slave_o.STALL <= '0';
 	slave_o.ERR   <= '0';
 
 	applyCR : for i in 0 to portcount - 1 generate

design/top.vhd

@@ -59,12 +59,12 @@ architecture RTL of top is
 
 	-- WB config
 	constant masters           : natural := 3;
-	constant slaves            : natural := 5;
+	constant slaves            : natural := 4;
 	constant INTERCON_ID_SRAM  : natural := 0;
 	constant INTERCON_ID_DDR3  : natural := 1;
 	constant INTERCON_ID_FLASH : natural := 2;
 	constant INTERCON_ID_GPIO  : natural := 3;
-	constant INTERCON_ID_UART  : natural := 4;
+	--	constant INTERCON_ID_UART    : natural := 3;
 	--	constant INTERCON_ID_NS16550 : natural := 4;
 
 	constant in_simulation : boolean := false
@@ -333,21 +333,6 @@ begin
 			gpio   => GPIOA
 		);
 
-	-- UART
-	uart_wb_inst : entity work.uart_wb
-		generic map(
-			portcount => 1
-		)
-		port map(
-			clk     => clk,
-			rst     => rst,
-			slave_i => intercon_slave_i(INTERCON_ID_UART),
-			slave_o => intercon_slave_o(INTERCON_ID_UART),
-			irq_o   => open,            -- TODO
-			rx(0)   => uart_rx,
-			tx(0)   => uart_tx
-		);
-
 	-- Intercon
 	crossbar_inst : entity ip.crossbar
 		generic map(
@@ -366,15 +351,13 @@ begin
 				INTERCON_ID_SRAM => x"00000000",
 				INTERCON_ID_DDR3 => x"10000000",
 				INTERCON_ID_FLASH => x"40000000",
-				INTERCON_ID_GPIO => x"80000000",
-				INTERCON_ID_UART => x"80000100"
+				INTERCON_ID_GPIO => x"80000000"
 			),
 			mask     => (
 				INTERCON_ID_SRAM => x"ffff0000",
 				INTERCON_ID_DDR3 => x"f0000000",
 				INTERCON_ID_FLASH => x"f0000000",
-				INTERCON_ID_GPIO => x"fffffff0",
-				INTERCON_ID_UART => x"ffffffc0"
+				INTERCON_ID_GPIO => x"fffffffc"
 			)
 		);
 end architecture RTL;

ip/intercon/rtl/crossbar_v3.vhd

@@ -174,7 +174,6 @@ architecture rtl of crossbar is
 					DAT  => acc.DAT or (slave_i(master).DAT and granted_data));
 		end loop;
 		-- acc.ADR := std_logic_vector(unsigned(acc.ADR) - unsigned(address(slave))); -- Address translation
-		acc.ADR := acc.ADR and not mask(slave); -- Address masking
 		o <= acc;
 	end slave_logic;