library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library design; use design.all; library ip; use ip.all; use ip.wishbone_package.all; entity bench_sram_wb is end entity bench_sram_wb; architecture RTL of bench_sram_wb is signal clk : std_logic; signal rst : std_logic; signal wb_in : wishbone_v3_slave_in; signal wb_out : wishbone_v3_slave_out; begin sram_wb_inst : entity design.sram_wb port map( clk => clk, rst => rst, wb_in => wb_in, wb_out => wb_out ); clock_driver : process constant period : time := 10 ns; begin clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2; end process clock_driver; wb_in.CYC <= wb_in.STB; test : process is begin rst <= '1'; wb_in.DAT <= (others => '0'); wb_in.STB <= '0'; wb_in.SEL <= "1111"; wb_in.WE <= '0'; wb_in.ADR <= (others => '0'); wait for 20 ns; wait until rising_edge(clk); rst <= '0'; wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk); -- wb_in.DAT <= x"12345678"; -- wb_in.WE <= '1'; -- wb_in.STB <= '1'; -- wait until rising_edge(clk); -- --wait until rising_edge(wb_out.ACK); -- wb_in.STB <= '0'; -- wait until rising_edge(clk); -- wb_in.ADR <= x"00000004"; -- wb_in.DAT <= x"AABBCCDD"; -- wb_in.WE <= '1'; -- wb_in.STB <= '1'; -- wait until rising_edge(clk); -- --wait until rising_edge(wb_out.ACK); -- wb_in.STB <= '0'; -- wait until rising_edge(clk); -- wb_in.ADR <= x"00000004"; -- wb_in.DAT <= x"FF111111"; -- wb_in.SEL <= "1000"; -- wb_in.WE <= '1'; -- wb_in.STB <= '1'; -- wait until rising_edge(clk); -- --wait until rising_edge(wb_out.ACK); -- wb_in.STB <= '0'; -- wb_in.SEL <= "1111"; -- wait until rising_edge(clk); -- -- wait until rising_edge(clk); -- wait until rising_edge(clk); -- wait until rising_edge(clk); -- wb_in.ADR <= x"00000000"; -- wb_in.DAT <= x"FFFFFFFF"; -- wb_in.WE <= '0'; -- wb_in.STB <= '1'; -- wait until rising_edge(clk); -- wait until rising_edge(wb_out.ACK); -- wait until rising_edge(clk); -- wb_in.STB <= '0'; -- wait until rising_edge(clk); -- wb_in.DAT <= x"FFFFFFFF"; -- wb_in.ADR <= x"00000004"; -- wb_in.WE <= '0'; -- wb_in.STB <= '1'; -- wait until rising_edge(clk); -- wait until rising_edge(wb_out.ACK); -- wait until rising_edge(clk); -- wb_in.STB <= '0'; for i in 0 to 1000 loop wait until rising_edge(clk); wb_in.ADR <= std_logic_vector(to_unsigned(i, 30) & "00"); wb_in.WE <= '0'; wb_in.STB <= '1'; wait until rising_edge(clk); wait until rising_edge(wb_out.ACK); wait until rising_edge(clk); wb_in.STB <= '0'; end loop; wait; end process test; end architecture RTL;