// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // -------------------------------------------------------------------------------- //| Avalon ST Idle Remover // -------------------------------------------------------------------------------- `timescale 1ns / 100ps module altera_avalon_st_idle_remover ( // Interface: clk input clk, input reset_n, // Interface: ST in output reg in_ready, input in_valid, input [7: 0] in_data, // Interface: ST out input out_ready, output reg out_valid, output reg [7: 0] out_data ); // --------------------------------------------------------------------- //| Signal Declarations // --------------------------------------------------------------------- reg received_esc; wire escape_char, idle_char; // --------------------------------------------------------------------- //| Thingofamagick // --------------------------------------------------------------------- assign idle_char = (in_data == 8'h4a); assign escape_char = (in_data == 8'h4d); always @(posedge clk or negedge reset_n) begin if (!reset_n) begin received_esc <= 0; end else begin if (in_valid & in_ready) begin if (escape_char & ~received_esc) begin received_esc <= 1; end else if (out_valid) begin received_esc <= 0; end end end end always @* begin in_ready = out_ready; //out valid when in_valid. Except when we get idle or escape //however, if we have received an escape character, then we are valid out_valid = in_valid & ~idle_char & (received_esc | ~escape_char); out_data = received_esc ? (in_data ^ 8'h20) : in_data; end endmodule