library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wishbone_package.all; use work.crossbar_package.all; use work.ebr_package.all; use work.lm32_package.all; use work.simple_pll_package.all; entity example is port( clk_base : in std_logic; rstn_base : in std_logic ); end example; architecture rtl of example is constant masters : natural := 2; constant slaves : natural := 2; signal clk : std_logic; signal rst : std_logic; signal locked : std_logic; signal intercon_slave_i : wishbone_slave_in_vector(masters-1 downto 0); signal intercon_slave_o : wishbone_slave_out_vector(masters-1 downto 0); signal intercon_master_i : wishbone_master_in_vector(slaves-1 downto 0); signal intercon_master_o : wishbone_master_out_vector(slaves-1 downto 0); begin rst <= not rstn_base or not locked; clk_pll : simple_pll generic map ( c0_mul => 2, c0_div => 1, c1_mul => 4, c1_div => 1, in_freq => 50000 ) port map ( inclk0 => clk_base, c0 => clk, c1 => open, locked => locked ); ebr_memory : ebr generic map ( size => 4096 ) port map ( clk => clk, rst => rst, slave_i => intercon_master_o(0), slave_o => intercon_master_i(0) ); monitor_memory : ebr generic map ( size => 2048 ) port map ( clk => clk, rst => rst, slave_i => intercon_master_o(1), slave_o => intercon_master_i(1) ); cpu0 : lm32_vhdl port map ( clk => clk, rst => rst, interrupt => x"00000000", data_o => intercon_slave_i(0), data_i => intercon_slave_o(0), inst_o => intercon_slave_i(1), inst_i => intercon_slave_o(1) ); intercon : crossbar generic map ( masters => masters, slaves => slaves, -- Device 0 has range 00000000-00000fff -- Device 1 has range 10000000-100007ff address => (0 => x"00000000", 1 => x"10000000"), mask => (0 => x"fffff000", 1 => x"fffff800") ) port map ( clk => clk, rst => rst, slave_i => intercon_slave_i, slave_o => intercon_slave_o, master_i => intercon_master_i, master_o => intercon_master_o ); end;