-- An MxS Wishbone crossbar switch.
-- 
-- All masters, slaves, and the crossbar itself must share the same WB clock.
-- All participants must support the same data bus width. 
-- 
-- If a master raises STB_O with an address not mapped by the crossbar,
-- ERR_I will be raised. If the crossbar has overlapping address ranges,
-- the lowest numbered slave is selected. If two masters address the same
-- slave simultaneously, the lowest numbered master is granted access.
-- 
-- The implementation of this crossbar locks a master to a slave so long as
-- CYC_O is held high. If the master tries to address outside the slave's
-- address range, ERR_I will be raised.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_package.all;

package crossbar_package is
   component crossbar is
      generic(
         masters : integer := 2;
         slaves  : integer := 1;
         async   : boolean := false
      );
      port(
         clk	: in	std_logic;
         rst	: in	std_logic;
         -- Master connections (INTERCON is a slave)
         slave_i	: in	wishbone_slave_in_vector(masters-1 downto 0);
         slave_o	: out	wishbone_slave_out_vector(masters-1 downto 0);
         -- Slave connections (INTERCON is a master)
         master_i	: in	wishbone_master_in_vector(slaves-1 downto 0);
         master_o	: out	wishbone_master_out_vector(slaves-1 downto 0);
         -- Address of the slaves connected
         address        : in    wishbone_address_vector(slaves-1 downto 0);
         mask           : in    wishbone_address_vector(slaves-1 downto 0)
       );
   end component;
end;